/*
 * Copyright (c) 2024, Ambiq Micro, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution.
 *
 * 3. Neither the name of the copyright holder nor the names of its
 * contributors may be used to endorse or promote products derived from this
 * software without specific prior written permission.
 *
 * Third party software included in this distribution is subject to the
 * additional license terms as defined in the /docs/licenses directory.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 * @file     apollo4l.h
 * @brief    CMSIS HeaderFile
 * @version  1.0
 * @date     05. June 2024
 * @note     Generated by SVDConv V3.3.42 on Wednesday, 05.06.2024 13:33:40
 *           from File './apollo4l.svd',
 *           last modified on Wednesday, 05.06.2024 18:33:39
 */



/** @addtogroup Ambiq Micro
  * @{
  */


/** @addtogroup apollo4l
  * @{
  */


#ifndef APOLLO4L_H
#define APOLLO4L_H

#ifdef __cplusplus
extern "C" {
#endif


/** @addtogroup Configuration_of_CMSIS
  * @{
  */



/* =========================================================================================================================== */
/* ================                                Interrupt Number Definition                                ================ */
/* =========================================================================================================================== */

typedef enum {
/* =======================================  ARM Cortex-M4 Specific Interrupt Numbers  ======================================== */
  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
  MemoryManagement_IRQn     = -12,              /*!< -12  Memory Management, MPU mismatch, including Access Violation
                                                     and No Match                                                              */
  BusFault_IRQn             = -11,              /*!< -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
                                                     related Fault                                                             */
  UsageFault_IRQn           = -10,              /*!< -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition        */
  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
  DebugMonitor_IRQn         =  -4,              /*!< -4 Debug Monitor                                                          */
  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
/* ==========================================  apollo4l Specific Interrupt Numbers  ========================================== */
  BROWNOUT_IRQn             =   0,              /*!< 0  BROWNOUT_IRQ                                                           */
  WDT_IRQn                  =   1,              /*!< 1  WDT_IRQ                                                                */
  RTC_IRQn                  =   2,              /*!< 2  RTC_IRQ                                                                */
  VCOMP_IRQn                =   3,              /*!< 3  VCOMP_IRQ                                                              */
  IOSLAVE_IRQn              =   4,              /*!< 4  IOSLAVE_IRQ                                                            */
  IOSLAVEACC_IRQn           =   5,              /*!< 5  IOSLAVEACC_IRQ                                                         */
  IOMSTR0_IRQn              =   6,              /*!< 6  IOMSTR0_IRQ                                                            */
  IOMSTR1_IRQn              =   7,              /*!< 7  IOMSTR1_IRQ                                                            */
  IOMSTR2_IRQn              =   8,              /*!< 8  IOMSTR2_IRQ                                                            */
  IOMSTR3_IRQn              =   9,              /*!< 9  IOMSTR3_IRQ                                                            */
  IOMSTR4_IRQn              =  10,              /*!< 10 IOMSTR4_IRQ                                                            */
  IOMSTR5_IRQn              =  11,              /*!< 11 IOMSTR5_IRQ                                                            */
  IOMSTR6_IRQn              =  12,              /*!< 12 IOMSTR6_IRQ                                                            */
  IOMSTR7_IRQn              =  13,              /*!< 13 IOMSTR7_IRQ                                                            */
  TIMER_IRQn                =  14,              /*!< 14 TIMER_IRQ                                                              */
  UART0_IRQn                =  15,              /*!< 15 UART0_IRQ                                                              */
  UART1_IRQn                =  16,              /*!< 16 UART1_IRQ                                                              */
  UART2_IRQn                =  17,              /*!< 17 UART2_IRQ                                                              */
  UART3_IRQn                =  18,              /*!< 18 UART3_IRQ                                                              */
  ADC_IRQn                  =  19,              /*!< 19 ADC_IRQ                                                                */
  MSPI0_IRQn                =  20,              /*!< 20 MSPI0_IRQ                                                              */
  MSPI1_IRQn                =  21,              /*!< 21 MSPI1_IRQ                                                              */
  MSPI2_IRQn                =  22,              /*!< 22 MSPI2_IRQ                                                              */
  CLKGEN_IRQn               =  23,              /*!< 23 CLKGEN_IRQ                                                             */
  CRYPTOSEC_IRQn            =  24,              /*!< 24 CRYPTOSEC_IRQ                                                          */
  SDIO_IRQn                 =  26,              /*!< 26 SDIO_IRQ                                                               */
  GPU_IRQn                  =  28,              /*!< 28 GPU_IRQ                                                                */
  STIMER_CMPR0_IRQn         =  32,              /*!< 32 STIMER_CMPR0_IRQ                                                       */
  STIMER_CMPR1_IRQn         =  33,              /*!< 33 STIMER_CMPR1_IRQ                                                       */
  STIMER_CMPR2_IRQn         =  34,              /*!< 34 STIMER_CMPR2_IRQ                                                       */
  STIMER_CMPR3_IRQn         =  35,              /*!< 35 STIMER_CMPR3_IRQ                                                       */
  STIMER_CMPR4_IRQn         =  36,              /*!< 36 STIMER_CMPR4_IRQ                                                       */
  STIMER_CMPR5_IRQn         =  37,              /*!< 37 STIMER_CMPR5_IRQ                                                       */
  STIMER_CMPR6_IRQn         =  38,              /*!< 38 STIMER_CMPR6_IRQ                                                       */
  STIMER_CMPR7_IRQn         =  39,              /*!< 39 STIMER_CMPR7_IRQ                                                       */
  STIMER_OVF_IRQn           =  40,              /*!< 40 STIMER_OVF_IRQ                                                         */
  I2S0_IRQn                 =  44,              /*!< 44 I2S0_IRQ                                                               */
  PDM0_IRQn                 =  48,              /*!< 48 PDM0_IRQ                                                               */
  GPIO0_001F_IRQn           =  56,              /*!< 56 GPIO0_001F_IRQ                                                         */
  GPIO0_203F_IRQn           =  57,              /*!< 57 GPIO0_203F_IRQ                                                         */
  GPIO0_405F_IRQn           =  58,              /*!< 58 GPIO0_405F_IRQ                                                         */
  GPIO0_607F_IRQn           =  59,              /*!< 59 GPIO0_607F_IRQ                                                         */
  GPIO1_001F_IRQn           =  60,              /*!< 60 GPIO1_001F_IRQ                                                         */
  GPIO1_203F_IRQn           =  61,              /*!< 61 GPIO1_203F_IRQ                                                         */
  GPIO1_405F_IRQn           =  62,              /*!< 62 GPIO1_405F_IRQ                                                         */
  GPIO1_607F_IRQn           =  63,              /*!< 63 GPIO1_607F_IRQ                                                         */
  CPUCPUMB_IRQn             =  64,              /*!< 64 CPUCPUMB_IRQ                                                           */
  DSWP0CPUMB_IRQn           =  65,              /*!< 65 DSWP0CPUMB_IRQ                                                         */
  DSWP1CPUMB_IRQn           =  66,              /*!< 66 DSWP1CPUMB_IRQ                                                         */
  TIMER0_IRQn               =  67,              /*!< 67 TIMER0_IRQ                                                             */
  TIMER1_IRQn               =  68,              /*!< 68 TIMER1_IRQ                                                             */
  TIMER2_IRQn               =  69,              /*!< 69 TIMER2_IRQ                                                             */
  TIMER3_IRQn               =  70,              /*!< 70 TIMER3_IRQ                                                             */
  TIMER4_IRQn               =  71,              /*!< 71 TIMER4_IRQ                                                             */
  TIMER5_IRQn               =  72,              /*!< 72 TIMER5_IRQ                                                             */
  TIMER6_IRQn               =  73,              /*!< 73 TIMER6_IRQ                                                             */
  TIMER7_IRQn               =  74,              /*!< 74 TIMER7_IRQ                                                             */
  TIMER8_IRQn               =  75,              /*!< 75 TIMER8_IRQ                                                             */
  TIMER9_IRQn               =  76,              /*!< 76 TIMER9_IRQ                                                             */
  TIMER10_IRQn              =  77,              /*!< 77 TIMER10_IRQ                                                            */
  TIMER11_IRQn              =  78,              /*!< 78 TIMER11_IRQ                                                            */
  TIMER12_IRQn              =  79,              /*!< 79 TIMER12_IRQ                                                            */
  TIMER13_IRQn              =  80,              /*!< 80 TIMER13_IRQ                                                            */
  TIMER14_IRQn              =  81,              /*!< 81 TIMER14_IRQ                                                            */
  TIMER15_IRQn              =  82,              /*!< 82 TIMER15_IRQ                                                            */
  CACHE_IRQn                =  83,              /*!< 83 CACHE_IRQ                                                              */
  MAX_IRQn                  =  84               /*!< 84 Not a valid IRQ. The maximum IRQ is this value - 1.                    */
} IRQn_Type;



/* =========================================================================================================================== */
/* ================                           Processor and Core Peripheral Section                           ================ */
/* =========================================================================================================================== */

/* ===========================  Configuration of the ARM Cortex-M4 Processor and Core Peripherals  =========================== */
#define __CM4_REV                 0x0100U       /*!< CM4 Core Revision                                                         */
#define __NVIC_PRIO_BITS               3        /*!< Number of Bits used for Priority Levels                                   */
#define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
#define __VTOR_PRESENT                 1        /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
#define __MPU_PRESENT                  1        /*!< MPU present                                                               */
#define __FPU_PRESENT                  1        /*!< FPU present                                                               */
#define __FPU_DP                       0        /*!< Double Precision FPU                                                      */
#define __DSP_PRESENT                  0        /*!< DSP extension present                                                     */
#define __ICACHE_PRESENT               1        /*!< Instruction Cache present                                                 */
#define __DCACHE_PRESENT               1        /*!< Data Cache present                                                        */
#define __ITCM_PRESENT                 1        /*!< Instruction TCM present                                                   */
#define __DTCM_PRESENT                 1        /*!< Data TCM present                                                          */
#define __SAUREGION_PRESENT            0        /*!< SAU region present                                                        */
#define __PMU_PRESENT                  0        /*!< PMU present                                                               */
#define __PMU_NUM_EVENTCNT             0        /*!< PMU Event Counters                                                        */


/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm4.h"                           /*!< ARM Cortex-M4 processor and core peripherals                              */
#include "system_apollo4l.h"                    /*!< apollo4l System                                                           */

#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __IM   __I
#endif
#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __OM   __O
#endif
#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
  #define __IOM  __IO
#endif


/* ========================================  Start of section using anonymous unions  ======================================== */
#if defined (__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined (__ICCARM__)
  #pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
  #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
  #pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif


/* =========================================================================================================================== */
/* ================                            Device Specific Peripheral Section                             ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                            ADC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Analog Digital Converter Control (ADC)
  */

typedef struct {                                /*!< (@ 0x40038000) ADC Structure                                              */

  union {
    __IOM uint32_t CFG;                         /*!< (@ 0x00000000) The ADC Configuration Register contains the software
                                                                    control for selecting the clock frequency
                                                                    used for the SAR conversions, the trigger
                                                                    polarity, the trigger select, the reference
                                                                    voltage select, the low power mode, the
                                                                    operating mode (single scan per trigger
                                                                    vs. repeating mode) and ADC enable.                        */

    struct {
      __IOM uint32_t ADCEN      : 1;            /*!< [0..0] This bit enables the ADC module. While the ADC is enabled,
                                                     the ADCCFG and SLOT Configuration regsiter settings must
                                                     remain stable and unchanged. All configuration register
                                                     settings, slot configuration settings and window comparison
                                                     settings should be written prior to setting the ADCEN bit
                                                     to '1'.                                                                   */
            uint32_t            : 1;
      __IOM uint32_t RPTEN      : 1;            /*!< [2..2] This bit enables Repeating Scan Mode.                              */
      __IOM uint32_t LPMODE     : 1;            /*!< [3..3] Select power mode to enter between active scans.                   */
      __IOM uint32_t CKMODE     : 1;            /*!< [4..4] Clock mode register                                                */
            uint32_t            : 7;
      __IOM uint32_t DFIFORDEN  : 1;            /*!< [12..12] Destructive FIFO Read Enable. Setting this will enable
                                                     FIFO pop upon reading the FIFOPR register.                                */
            uint32_t            : 3;
      __IOM uint32_t TRIGSEL    : 3;            /*!< [18..16] Select the ADC trigger source.                                   */
      __IOM uint32_t TRIGPOL    : 1;            /*!< [19..19] This bit selects the ADC trigger polarity for external
                                                     off chip triggers.                                                        */
      __IOM uint32_t RPTTRIGSEL : 1;            /*!< [20..20] This bit selects which periodic trigger to use with
                                                     RPTEN = 1.                                                                */
            uint32_t            : 3;
      __IOM uint32_t CLKSEL     : 2;            /*!< [25..24] Select the source and frequency for the general purpose
                                                     ADC clock. HFRC_24MHZ is the only valid GP ADC clock selection
                                                     and must be configured for proper operation.                              */
            uint32_t            : 6;
    } CFG_b;
  } ;

  union {
    __IOM uint32_t STAT;                        /*!< (@ 0x00000004) This register indicates the basic power status
                                                                    for the ADC. For detailed power status,
                                                                    see the power control power status register.
                                                                    ADC power mode 0 indicates the ADC is in
                                                                    its full power state and is ready to process
                                                                    scans. ADC Power mode 1 indicates the ADC
                                                                    enabled and in a low power state.                          */

    struct {
      __IOM uint32_t PWDSTAT    : 1;            /*!< [0..0] Indicates the power-status of the ADC.                             */
            uint32_t            : 31;
    } STAT_b;
  } ;

  union {
    __IOM uint32_t SWT;                         /*!< (@ 0x00000008) This register enables initiating an ADC scan
                                                                    through software.                                          */

    struct {
      __IOM uint32_t SWT        : 8;            /*!< [7..0] Writing 0x37 to this register generates a software trigger.        */
            uint32_t            : 24;
    } SWT_b;
  } ;

  union {
    __IOM uint32_t SL0CFG;                      /*!< (@ 0x0000000C) Slot 0 Configuration                                       */

    struct {
      __IOM uint32_t SLEN0      : 1;            /*!< [0..0] This bit enables slot 0 for ADC conversions.                       */
      __IOM uint32_t WCEN0      : 1;            /*!< [1..1] This bit enables the window compare function for slot
                                                     0.                                                                        */
            uint32_t            : 6;
      __IOM uint32_t CHSEL0     : 4;            /*!< [11..8] Select one of the 11 channel inputs for this slot.                */
            uint32_t            : 4;
      __IOM uint32_t PRMODE0    : 2;            /*!< [17..16] Set the Precision Mode For Slot 0.                               */
      __IOM uint32_t TRKCYC0    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
                                                     to the specified number of ADC clock cycles. (Note that
                                                     a value of 0 in this register specifies the minimum required
                                                     5 cycles. A maximum of 64 specifies 69 cycles.)                           */
      __IOM uint32_t ADSEL0     : 3;            /*!< [26..24] Select the number of measurements to average in the
                                                     accumulate divide module for this slot.                                   */
            uint32_t            : 5;
    } SL0CFG_b;
  } ;

  union {
    __IOM uint32_t SL1CFG;                      /*!< (@ 0x00000010) Slot 1 Configuration                                       */

    struct {
      __IOM uint32_t SLEN1      : 1;            /*!< [0..0] This bit enables slot 1 for ADC conversions.                       */
      __IOM uint32_t WCEN1      : 1;            /*!< [1..1] This bit enables the window compare function for slot
                                                     1.                                                                        */
            uint32_t            : 6;
      __IOM uint32_t CHSEL1     : 4;            /*!< [11..8] Select one of the 11 channel inputs for this slot.                */
            uint32_t            : 4;
      __IOM uint32_t PRMODE1    : 2;            /*!< [17..16] Set the Precision Mode For Slot 1.                               */
      __IOM uint32_t TRKCYC1    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
                                                     to the specified number of ADC clock cycles. (Note that
                                                     a value of 0 in this register specifies the minimum required
                                                     5 cycles. A maximum of 64 specifies 69 cycles.)                           */
      __IOM uint32_t ADSEL1     : 3;            /*!< [26..24] Select the number of measurements to average in the
                                                     accumulate divide module for this slot.                                   */
            uint32_t            : 5;
    } SL1CFG_b;
  } ;

  union {
    __IOM uint32_t SL2CFG;                      /*!< (@ 0x00000014) Slot 2 Configuration                                       */

    struct {
      __IOM uint32_t SLEN2      : 1;            /*!< [0..0] This bit enables slot 2 for ADC conversions.                       */
      __IOM uint32_t WCEN2      : 1;            /*!< [1..1] This bit enables the window compare function for slot
                                                     2.                                                                        */
            uint32_t            : 6;
      __IOM uint32_t CHSEL2     : 4;            /*!< [11..8] Select one of the 11 channel inputs for this slot.                */
            uint32_t            : 4;
      __IOM uint32_t PRMODE2    : 2;            /*!< [17..16] Set the Precision Mode For Slot 2.                               */
      __IOM uint32_t TRKCYC2    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
                                                     to the specified number of ADC clock cycles. (Note that
                                                     a value of 0 in this register specifies the minimum required
                                                     5 cycles. A maximum of 64 specifies 69 cycles.)                           */
      __IOM uint32_t ADSEL2     : 3;            /*!< [26..24] Select the number of measurements to average in the
                                                     accumulate divide module for this slot.                                   */
            uint32_t            : 5;
    } SL2CFG_b;
  } ;

  union {
    __IOM uint32_t SL3CFG;                      /*!< (@ 0x00000018) Slot 3 Configuration                                       */

    struct {
      __IOM uint32_t SLEN3      : 1;            /*!< [0..0] This bit enables slot 3 for ADC conversions.                       */
      __IOM uint32_t WCEN3      : 1;            /*!< [1..1] This bit enables the window compare function for slot
                                                     3.                                                                        */
            uint32_t            : 6;
      __IOM uint32_t CHSEL3     : 4;            /*!< [11..8] Select one of the 11 channel inputs for this slot.                */
            uint32_t            : 4;
      __IOM uint32_t PRMODE3    : 2;            /*!< [17..16] Set the Precision Mode For Slot 3.                               */
      __IOM uint32_t TRKCYC3    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
                                                     to the specified number of ADC clock cycles. (Note that
                                                     a value of 0 in this register specifies the minimum required
                                                     5 cycles. A maximum of 64 specifies 69 cycles.)                           */
      __IOM uint32_t ADSEL3     : 3;            /*!< [26..24] Select the number of measurements to average in the
                                                     accumulate divide module for this slot.                                   */
            uint32_t            : 5;
    } SL3CFG_b;
  } ;

  union {
    __IOM uint32_t SL4CFG;                      /*!< (@ 0x0000001C) Slot 4 Configuration                                       */

    struct {
      __IOM uint32_t SLEN4      : 1;            /*!< [0..0] This bit enables slot 4 for ADC conversions.                       */
      __IOM uint32_t WCEN4      : 1;            /*!< [1..1] This bit enables the window compare function for slot
                                                     4.                                                                        */
            uint32_t            : 6;
      __IOM uint32_t CHSEL4     : 4;            /*!< [11..8] Select one of the 11 channel inputs for this slot.                */
            uint32_t            : 4;
      __IOM uint32_t PRMODE4    : 2;            /*!< [17..16] Set the Precision Mode For Slot 4.                               */
      __IOM uint32_t TRKCYC4    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
                                                     to the specified number of ADC clock cycles. (Note that
                                                     a value of 0 in this register specifies the minimum required
                                                     5 cycles. A maximum of 64 specifies 69 cycles.)                           */
      __IOM uint32_t ADSEL4     : 3;            /*!< [26..24] Select the number of measurements to average in the
                                                     accumulate divide module for this slot.                                   */
            uint32_t            : 5;
    } SL4CFG_b;
  } ;

  union {
    __IOM uint32_t SL5CFG;                      /*!< (@ 0x00000020) Slot 5 Configuration                                       */

    struct {
      __IOM uint32_t SLEN5      : 1;            /*!< [0..0] This bit enables slot 5 for ADC conversions.                       */
      __IOM uint32_t WCEN5      : 1;            /*!< [1..1] This bit enables the window compare function for slot
                                                     5.                                                                        */
            uint32_t            : 6;
      __IOM uint32_t CHSEL5     : 4;            /*!< [11..8] Select one of the 11 channel inputs for this slot.                */
            uint32_t            : 4;
      __IOM uint32_t PRMODE5    : 2;            /*!< [17..16] Set the Precision Mode For Slot 5.                               */
      __IOM uint32_t TRKCYC5    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
                                                     to the specified number of ADC clock cycles. (Note that
                                                     a value of 0 in this register specifies the minimum required
                                                     5 cycles. A maximum of 64 specifies 69 cycles.)                           */
      __IOM uint32_t ADSEL5     : 3;            /*!< [26..24] Select the number of measurements to average in the
                                                     accumulate divide module for this slot.                                   */
            uint32_t            : 5;
    } SL5CFG_b;
  } ;

  union {
    __IOM uint32_t SL6CFG;                      /*!< (@ 0x00000024) Slot 6 Configuration                                       */

    struct {
      __IOM uint32_t SLEN6      : 1;            /*!< [0..0] This bit enables slot 6 for ADC conversions.                       */
      __IOM uint32_t WCEN6      : 1;            /*!< [1..1] This bit enables the window compare function for slot
                                                     6.                                                                        */
            uint32_t            : 6;
      __IOM uint32_t CHSEL6     : 4;            /*!< [11..8] Select one of the 11 channel inputs for this slot.                */
            uint32_t            : 4;
      __IOM uint32_t PRMODE6    : 2;            /*!< [17..16] Set the Precision Mode For Slot 6.                               */
      __IOM uint32_t TRKCYC6    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
                                                     to the specified number of ADC clock cycles. (Note that
                                                     a value of 0 in this register specifies the minimum required
                                                     5 cycles. A maximum of 64 specifies 69 cycles.)                           */
      __IOM uint32_t ADSEL6     : 3;            /*!< [26..24] Select the number of measurements to average in the
                                                     accumulate divide module for this slot.                                   */
            uint32_t            : 5;
    } SL6CFG_b;
  } ;

  union {
    __IOM uint32_t SL7CFG;                      /*!< (@ 0x00000028) Slot 7 Configuration                                       */

    struct {
      __IOM uint32_t SLEN7      : 1;            /*!< [0..0] This bit enables slot 7 for ADC conversions.                       */
      __IOM uint32_t WCEN7      : 1;            /*!< [1..1] This bit enables the window compare function for slot
                                                     7.                                                                        */
            uint32_t            : 6;
      __IOM uint32_t CHSEL7     : 4;            /*!< [11..8] Select one of the 11 channel inputs for this slot.                */
            uint32_t            : 4;
      __IOM uint32_t PRMODE7    : 2;            /*!< [17..16] Set the Precision Mode For Slot 7.                               */
      __IOM uint32_t TRKCYC7    : 6;            /*!< [23..18] Set additional input signal sampling/tracking time
                                                     to the specified number of ADC clock cycles. (Note that
                                                     a value of 0 in this register specifies the minimum required
                                                     5 cycles. A maximum of 64 specifies 69 cycles.)                           */
      __IOM uint32_t ADSEL7     : 3;            /*!< [26..24] Select the number of measurements to average in the
                                                     accumulate divide module for this slot.                                   */
            uint32_t            : 5;
    } SL7CFG_b;
  } ;

  union {
    __IOM uint32_t WULIM;                       /*!< (@ 0x0000002C) Window Comparator Upper Limits                             */

    struct {
      __IOM uint32_t ULIM       : 20;           /*!< [19..0] Sets the upper limit for the window comparator.                   */
            uint32_t            : 12;
    } WULIM_b;
  } ;

  union {
    __IOM uint32_t WLLIM;                       /*!< (@ 0x00000030) Window Comparator Lower Limits                             */

    struct {
      __IOM uint32_t LLIM       : 20;           /*!< [19..0] Sets the lower limit for the window comparator.                   */
            uint32_t            : 12;
    } WLLIM_b;
  } ;

  union {
    __IOM uint32_t SCWLIM;                      /*!< (@ 0x00000034) Scale Window Comparator Limits                             */

    struct {
      __IOM uint32_t SCWLIMEN   : 1;            /*!< [0..0] Scale the window limits compare values per precision
                                                     mode. When set to 0x0 (default), the values in the 20-bit
                                                     limits registers will compare directly with the FIFO values
                                                     regardless of the precision mode the slot is configured
                                                     to. When set to 0x1, the compare values will be divided
                                                     by the difference in precision bits while performing the
                                                     window limit comparisons.                                                 */
            uint32_t            : 31;
    } SCWLIM_b;
  } ;

  union {
    __IOM uint32_t FIFO;                        /*!< (@ 0x00000038) The ADC FIFO Register contains the slot number
                                                                    and fifo data for the oldest conversion
                                                                    data in the FIFO. The COUNT field indicates
                                                                    the total number of valid entries in the
                                                                    FIFO. A write to this register will pop
                                                                    one of the FIFO entries off the FIFO and
                                                                    decrease the COUNT by 1 if the COUNT is
                                                                    greater than zero.                                         */

    struct {
      __IOM uint32_t DATA       : 20;           /*!< [19..0] Oldest data in the FIFO.                                          */
      __IOM uint32_t COUNT      : 8;            /*!< [27..20] Number of valid entries in the ADC FIFO.                         */
      __IOM uint32_t SLOTNUM    : 3;            /*!< [30..28] Slot number associated with this FIFO data.                      */
      __IOM uint32_t RSVD       : 1;            /*!< [31..31] RESERVED.                                                        */
    } FIFO_b;
  } ;

  union {
    __IOM uint32_t FIFOPR;                      /*!< (@ 0x0000003C) This is a Pop Read mirrored copy of the ADCFIFO
                                                                    register with the only difference being
                                                                    that reading this register will result in
                                                                    a simultaneous FIFO POP which is also achieved
                                                                    by writing to the ADCFIFO Register. Note:
                                                                    The DFIFORDEN bit must be set in the CFG
                                                                    register for the the destructive read to
                                                                    be enabled.                                                */

    struct {
      __IOM uint32_t DATA       : 20;           /*!< [19..0] Oldest data in the FIFO.                                          */
      __IOM uint32_t COUNT      : 8;            /*!< [27..20] Number of valid entries in the ADC FIFO.                         */
      __IOM uint32_t SLOTNUMPR  : 3;            /*!< [30..28] Slot number associated with this FIFO data.                      */
      __IOM uint32_t RSVDPR     : 1;            /*!< [31..31] RESERVED.                                                        */
    } FIFOPR_b;
  } ;

  union {
    __IOM uint32_t INTTRIGTIMER;                /*!< (@ 0x00000040) ADC-Internal Repeating Trigger Timer Configuration         */

    struct {
      __IOM uint32_t TIMERMAX   : 10;           /*!< [9..0] Trigger counter count max, used as initial condition
                                                     to trigger. Also used repeatedly each time counter reaches
                                                     it to restart trigger timer at zero. To update this value,
                                                     first disable the INTTRIGTIMER by setting TIMEREN to DIS,
                                                     change TIMERMAX, and then reenable it INTTRIGTIMER by setting
                                                     TIMEREN to EN again.                                                      */
            uint32_t            : 6;
      __IOM uint32_t CLKDIV     : 3;            /*!< [18..16] Configure number of divide-by-2 of clock source as
                                                     input to trigger counter. (Max value of 5.) A value of
                                                     0 in this register would not divide down the ADC input
                                                     clock. A value of 1 would divide the ADC input clock frequency
                                                     by 2. A value of 5 would divide the ADC input clock frequency
                                                     by 2^5 = 32. To update this value, first disable the INTTRIGTIMER
                                                     by setting TIMEREN to DIS, change CLKDIV, and then reenable
                                                     it INTTRIGTIMER by setting TIMEREN to EN again.                           */
            uint32_t            : 12;
      __IOM uint32_t TIMEREN    : 1;            /*!< [31..31] ADC-internal trigger timer enable.                               */
    } INTTRIGTIMER_b;
  } ;
  __IM  uint32_t  RESERVED[7];

  union {
    __IOM uint32_t ZXCFG;                       /*!< (@ 0x00000060) Zero Crossing Comparator Configuration                     */

    struct {
      __IOM uint32_t ZXEN       : 1;            /*!< [0..0] Enable the ZX comparator                                           */
            uint32_t            : 3;
      __IOM uint32_t ZXCHANSEL  : 1;            /*!< [4..4] Select which slots to use for zero crossing measurement.
                                                     0 enables zero crossing detection on slots 0 and 2. 1 enables
                                                     zero crossing detection on slots 1 and 3.                                 */
            uint32_t            : 27;
    } ZXCFG_b;
  } ;

  union {
    __IOM uint32_t ZXLIM;                       /*!< (@ 0x00000064) Zero Crossing Comparator Limits                            */

    struct {
      __IOM uint32_t LZXC       : 12;           /*!< [11..0] Sets the lower integer sample limit for the ZX comparator.
                                                     Note that these values are raw ADC values whose bounds
                                                     are specified by PRMODE but not maniupulated by accumulate/divide
                                                     logic. Therefore, there is no oversampling and no binary
                                                     point in this value. Samples must enter the range between
                                                     UZXC and LZXC in order for a zero crossing to be recognized.              */
            uint32_t            : 4;
      __IOM uint32_t UZXC       : 12;           /*!< [27..16] Sets the upper integer sample limit for the ZX comparator.
                                                     Note that these values are raw ADC values whose bounds
                                                     are specified by PRMODE but not maniupulated by accumulate/divide
                                                     logic. Therefore, there is no oversampling and no binary
                                                     point in this value. Samples must enter the range between
                                                     UZXC and LZXC in order for a zero crossing to be recognized.              */
            uint32_t            : 4;
    } ZXLIM_b;
  } ;

  union {
    __IOM uint32_t GAINCFG;                     /*!< (@ 0x00000068) PGA Gain Configuration                                     */

    struct {
      __IOM uint32_t PGACTRLEN  : 1;            /*!< [0..0] Enable PGA gain updates.                                           */
            uint32_t            : 3;
      __IOM uint32_t UPDATEMODE : 1;            /*!< [4..4] PGA update mode                                                    */
            uint32_t            : 27;
    } GAINCFG_b;
  } ;

  union {
    __IOM uint32_t GAIN;                        /*!< (@ 0x0000006C) PGA Gain Codes                                             */

    struct {
      __IOM uint32_t LGA        : 7;            /*!< [6..0] Specifies the low gain code (0 to 102 decimal specifies
                                                     -6.0 dB to 45.0 dB in half-dB increments) for channel A
                                                     (slot 0).                                                                 */
            uint32_t            : 1;
      __IOM uint32_t HGADELTA   : 7;            /*!< [14..8] Specifies the high gain code as an delta from the LGA
                                                     field for channel A (slot 1).                                             */
            uint32_t            : 1;
      __IOM uint32_t LGB        : 7;            /*!< [22..16] Specifies the low gain code (0 to 102 decimal specifies
                                                     -6.0 dB to 45.0 dB in half-dB increments) for channel B
                                                     (slot 2).                                                                 */
            uint32_t            : 1;
      __IOM uint32_t HGBDELTA   : 7;            /*!< [30..24] Specifies the high gain code as an delta from the LGB
                                                     field for channel B (slot 3).                                             */
            uint32_t            : 1;
    } GAIN_b;
  } ;
  __IM  uint32_t  RESERVED1[13];

  union {
    __IOM uint32_t SATCFG;                      /*!< (@ 0x000000A4) Saturation Comparator Configuration                        */

    struct {
      __IOM uint32_t SATEN      : 1;            /*!< [0..0] Enable the saturation comparator                                   */
            uint32_t            : 3;
      __IOM uint32_t SATCHANSEL : 1;            /*!< [4..4] Select which slots to use for saturation measurement.
                                                     0 enables saturation on slots 0 and 2. 1 enables saturation
                                                     on slots 1 and 3.                                                         */
            uint32_t            : 27;
    } SATCFG_b;
  } ;

  union {
    __IOM uint32_t SATLIM;                      /*!< (@ 0x000000A8) Saturation Comparator Limits                               */

    struct {
      __IOM uint32_t LSATC      : 12;           /*!< [11..0] Sets the lower integer sample limit for the saturation
                                                     comparator. Note that these values are raw ADC values whose
                                                     bounds are specified by PRMODE but not manipulated by accumulate/divide
                                                     logic. Therefore, there is no oversampling and no binary
                                                     point in this value.                                                      */
            uint32_t            : 4;
      __IOM uint32_t USATC      : 12;           /*!< [27..16] Sets the upper integer sample limit for the saturation
                                                     comparator. Note that these values are raw ADC values whose
                                                     bounds are specified by PRMODE but not manipulated by accumulate/divide
                                                     logic. Therefore, there is no oversampling and no binary
                                                     point in this value.                                                      */
            uint32_t            : 4;
    } SATLIM_b;
  } ;

  union {
    __IOM uint32_t SATMAX;                      /*!< (@ 0x000000AC) Saturation Comparator Event Counter Limits                 */

    struct {
      __IOM uint32_t SATCAMAX   : 12;           /*!< [11..0] Sets the number of saturation events that may occur
                                                     before a SATCA interrupt occurs. Once this interrupt occurs,
                                                     the saturation event counter must be cleared by writing
                                                     the SATCLR register. A value of 0 is invalid and will cause
                                                     the saturation interrupt to assert immediately.                           */
            uint32_t            : 4;
      __IOM uint32_t SATCBMAX   : 12;           /*!< [27..16] Sets the number of saturation events that may occur
                                                     before a SATCB interrupt occurs. Once this interrupt occurs,
                                                     the saturation event counter must be cleared by writing
                                                     the SATCLR register. A value of 0 is invalid and will cause
                                                     the saturation interrupt to assert immediately.                           */
            uint32_t            : 4;
    } SATMAX_b;
  } ;

  union {
    __IOM uint32_t SATCLR;                      /*!< (@ 0x000000B0) Clears the saturation event counter registers              */

    struct {
      __IOM uint32_t SATCACLR   : 1;            /*!< [0..0] Clear saturation event counter register for channel A
                                                     (slots 0 or 1, depending on SATCHANSEL)                                   */
      __IOM uint32_t SATCBCLR   : 1;            /*!< [1..1] Clear saturation event counter register for channel B
                                                     (slots 2 or 3, depending on SATCHANSEL)                                   */
            uint32_t            : 30;
    } SATCLR_b;
  } ;
  __IM  uint32_t  RESERVED2[25];

  union {
    __IOM uint32_t CALCTRL;                     /*!< (@ 0x00000118) Calibration Control                                        */

    struct {
      __IOM uint32_t RESETDLY   : 10;           /*!< [9..0] Sets the delay between the deassertion of ADC reset and
                                                     the start of calibration in ADC CLKs. Minimum per spec
                                                     is 8 CLKs. Specifying a value smaller than 8 is not supported.            */
      __IOM uint32_t ISODLY     : 10;           /*!< [19..10] Sets the delay between the deassertion of ADC isolation
                                                     and the deassertion of ADC reset in ADC CLKs. This allows
                                                     for synchronous reset of logic within the ADC.                            */
            uint32_t            : 12;
    } CALCTRL_b;
  } ;
  __IM  uint32_t  RESERVED3[57];

  union {
    __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
      __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
      __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
      __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
      __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
      __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
      __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
      __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
      __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
      __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
      __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
      __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
            uint32_t            : 20;
    } INTEN_b;
  } ;

  union {
    __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
      __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
      __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
      __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
      __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
      __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
      __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
      __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
      __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
      __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
      __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
      __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
            uint32_t            : 20;
    } INTSTAT_b;
  } ;

  union {
    __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
      __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
      __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
      __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
      __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
      __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
      __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
      __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
      __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
      __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
      __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
      __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
            uint32_t            : 20;
    } INTCLR_b;
  } ;

  union {
    __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
      __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
      __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
      __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
      __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
      __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
      __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
      __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
      __IOM uint32_t ZXCA       : 1;            /*!< [8..8] Zero Crossing - Channel A (Slots 0 or 1)                           */
      __IOM uint32_t ZXCB       : 1;            /*!< [9..9] Zero Crossing - Channel B (Slots 2 or 3)                           */
      __IOM uint32_t SATCA      : 1;            /*!< [10..10] Saturation - Channel A (Slots 0 or 1)                            */
      __IOM uint32_t SATCB      : 1;            /*!< [11..11] Saturation - Channel B (Slots 2 or 3)                            */
            uint32_t            : 20;
    } INTSET_b;
  } ;
  __IM  uint32_t  RESERVED4[12];

  union {
    __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000240) DMA Trigger Enable                                         */

    struct {
      __IOM uint32_t DFIFO75    : 1;            /*!< [0..0] Trigger DMA upon FIFO 75 percent Full                              */
      __IOM uint32_t DFIFOFULL  : 1;            /*!< [1..1] Trigger DMA upon FIFO 100 percent Full                             */
            uint32_t            : 30;
    } DMATRIGEN_b;
  } ;

  union {
    __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000244) DMA Trigger Status                                         */

    struct {
      __IOM uint32_t D75STAT    : 1;            /*!< [0..0] Triggered DMA from FIFO 75 percent Full                            */
      __IOM uint32_t DFULLSTAT  : 1;            /*!< [1..1] Triggered DMA from FIFO 100 percent Full                           */
            uint32_t            : 30;
    } DMATRIGSTAT_b;
  } ;
  __IM  uint32_t  RESERVED5[14];

  union {
    __IOM uint32_t DMACFG;                      /*!< (@ 0x00000280) DMA Configuration                                          */

    struct {
      __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable                                                         */
            uint32_t            : 1;
      __IOM uint32_t DMADIR     : 1;            /*!< [2..2] Direction                                                          */
            uint32_t            : 5;
      __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
      __IOM uint32_t DMADYNPRI  : 1;            /*!< [9..9] Enables dynamic priority based on FIFO fullness. When
                                                     FIFO is full, priority is automatically set to HIGH. Otherwise,
                                                     DMAPRI is used.                                                           */
            uint32_t            : 7;
      __IOM uint32_t DMAMSK     : 1;            /*!< [17..17] Mask the FIFOCNT and SLOTNUM when transferring FIFO
                                                     contents to memory                                                        */
      __IOM uint32_t DPWROFF    : 1;            /*!< [18..18] Power Off the ADC System upon DMACPL.                            */
            uint32_t            : 13;
    } DMACFG_b;
  } ;
  __IM  uint32_t  RESERVED6;

  union {
    __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000288) DMA Total Transfer Count                                   */

    struct {
            uint32_t            : 2;
      __IOM uint32_t TOTCOUNT   : 16;           /*!< [17..2] Total Transfer Count                                              */
            uint32_t            : 14;
    } DMATOTCOUNT_b;
  } ;

  union {
    __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x0000028C) DMA Target Address                                         */

    struct {
      __IOM uint32_t LTARGADDR  : 28;           /*!< [27..0] DMA Target Address                                                */
      __IOM uint32_t UTARGADDR  : 4;            /*!< [31..28] SRAM Target                                                      */
    } DMATARGADDR_b;
  } ;

  union {
    __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000290) DMA Status                                                 */

    struct {
      __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress                                           */
      __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete                                              */
      __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error                                                          */
            uint32_t            : 29;
    } DMASTAT_b;
  } ;
} ADC_Type;                                     /*!< Size = 660 (0x294)                                                        */



/* =========================================================================================================================== */
/* ================                                          APBDMA                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief APB DMA Register Interfaces (APBDMA)
  */

typedef struct {                                /*!< (@ 0x40011000) APBDMA Structure                                           */

  union {
    __IOM uint32_t BBVALUE;                     /*!< (@ 0x00000000) Control                                                    */

    struct {
      __IOM uint32_t DATAOUT    : 8;            /*!< [7..0] Data Output Values                                                 */
            uint32_t            : 8;
      __IOM uint32_t PIN        : 8;            /*!< [23..16] PIO values                                                       */
            uint32_t            : 8;
    } BBVALUE_b;
  } ;

  union {
    __IOM uint32_t BBSETCLEAR;                  /*!< (@ 0x00000004) Set/Clear                                                  */

    struct {
      __IOM uint32_t SET        : 8;            /*!< [7..0] Write 1 to Set PIO value (set hier priority than clear
                                                     if both bit set)                                                          */
            uint32_t            : 8;
      __IOM uint32_t CLEAR      : 8;            /*!< [23..16] Write 1 to Clear PIO value                                       */
            uint32_t            : 8;
    } BBSETCLEAR_b;
  } ;

  union {
    __IOM uint32_t BBINPUT;                     /*!< (@ 0x00000008) PIO Input Values                                           */

    struct {
      __IOM uint32_t DATAIN     : 8;            /*!< [7..0] PIO values                                                         */
            uint32_t            : 24;
    } BBINPUT_b;
  } ;
  __IM  uint32_t  RESERVED[5];

  union {
    __IOM uint32_t DEBUGDATA;                   /*!< (@ 0x00000020) PIO Input Values                                           */

    struct {
      __IOM uint32_t DEBUGDATA  : 32;           /*!< [31..0] Debug Data                                                        */
    } DEBUGDATA_b;
  } ;
  __IM  uint32_t  RESERVED1[7];

  union {
    __IOM uint32_t DEBUG;                       /*!< (@ 0x00000040) PIO Input Values                                           */

    struct {
      __IOM uint32_t DEBUGEN    : 4;            /*!< [3..0] Debug Enable                                                       */
            uint32_t            : 28;
    } DEBUG_b;
  } ;
} APBDMA_Type;                                  /*!< Size = 68 (0x44)                                                          */



/* =========================================================================================================================== */
/* ================                                          CLKGEN                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Clock Generator (CLKGEN)
  */

typedef struct {                                /*!< (@ 0x40004000) CLKGEN Structure                                           */
  __IM  uint32_t  RESERVED[3];

  union {
    __IOM uint32_t OCTRL;                       /*!< (@ 0x0000000C) This register includes controls for autocalibration
                                                                    in addition to the RTC oscillator controls.                */

    struct {
            uint32_t            : 7;
      __IOM uint32_t OSEL       : 1;            /*!< [7..7] Selects the RTC oscillator (1=LFRC, 0=XT)                          */
            uint32_t            : 24;
    } OCTRL_b;
  } ;

  union {
    __IOM uint32_t CLKOUT;                      /*!< (@ 0x00000010) This register enables the CLKOUT to the GPIOs,
                                                                    and selects the clock source to that.                      */

    struct {
      __IOM uint32_t CKSEL      : 6;            /*!< [5..0] CLKOUT signal select                                               */
            uint32_t            : 1;
      __IOM uint32_t CKEN       : 1;            /*!< [7..7] Enable the CLKOUT signal                                           */
            uint32_t            : 24;
    } CLKOUT_b;
  } ;
  __IM  uint32_t  RESERVED1[3];

  union {
    __IOM uint32_t HFADJ;                       /*!< (@ 0x00000020) This register controls the HFRC adjustment. The
                                                                    HFRC clock can change with temperature and
                                                                    process corners, and this register controls
                                                                    the HFRC adjustment logic which reduces
                                                                    the fluctuations to the clock.                             */

    struct {
      __IOM uint32_t HFADJEN    : 1;            /*!< [0..0] HFRC adjustment control                                            */
      __IOM uint32_t HFADJCK    : 3;            /*!< [3..1] Repeat period for HFRC adjustment                                  */
            uint32_t            : 4;
      __IOM uint32_t HFXTADJ    : 12;           /*!< [19..8] Target HFRC adjustment value.                                     */
      __IOM uint32_t HFWARMUP   : 1;            /*!< [20..20] XT warmup period for HFRC adjustment                             */
      __IOM uint32_t HFADJGAIN  : 3;            /*!< [23..21] Gain control for HFRC adjustment                                 */
      __IOM uint32_t HFADJMAXDELTA : 5;         /*!< [28..24] Maximum delta for HF Adjustments. 0=Disabled, 1-31=maximum
                                                     delta step                                                                */
            uint32_t            : 3;
    } HFADJ_b;
  } ;
  __IM  uint32_t  RESERVED2[3];

  union {
    __IOM uint32_t CLOCKENSTAT;                 /*!< (@ 0x00000030) This register provides the enable status to all
                                                                    the peripheral clocks.                                     */

    struct {
      __IOM uint32_t CLOCKENSTAT : 32;          /*!< [31..0] Clock enable status                                               */
    } CLOCKENSTAT_b;
  } ;

  union {
    __IOM uint32_t CLOCKEN2STAT;                /*!< (@ 0x00000034) This is a continuation of the clock enable status.         */

    struct {
      __IOM uint32_t CLOCKEN2STAT : 32;         /*!< [31..0] Clock enable status 2                                             */
    } CLOCKEN2STAT_b;
  } ;

  union {
    __IOM uint32_t CLOCKEN3STAT;                /*!< (@ 0x00000038) This is a continuation of the clock enable status.         */

    struct {
      __IOM uint32_t CLOCKEN3STAT : 32;         /*!< [31..0] Clock enable status 3                                             */
    } CLOCKEN3STAT_b;
  } ;
  __IM  uint32_t  RESERVED3[2];

  union {
    __IOM uint32_t MISC;                        /*!< (@ 0x00000044) This register controls a 'safe' mode for burst,
                                                                    which disables the clock when burst transition
                                                                    is happening. It also includes a register
                                                                    to force the HFRC during deep sleep. It
                                                                    is mainly used for debug and testing.                      */

    struct {
      __IOM uint32_t FRCHFRC    : 1;            /*!< [0..0] Force HFRC On .                                                    */
      __IOM uint32_t FRCBURSTOFF : 1;           /*!< [1..1] Force fclk, hclk, fclk_wic and fclk_pmu to be turned
                                                     off during burst transition.                                              */
      __IOM uint32_t USEHFRC2FQ48MHZ : 1;       /*!< [2..2] Use HFRC-48MHz or HFRC2-48MHz for DSP                              */
      __IOM uint32_t USEHFRC2FQ96MHZ : 1;       /*!< [3..3] Use HFRC-96MHz or HFRC2-96MHz for DSP                              */
      __IOM uint32_t USEHFRC2FQ192MHZ : 1;      /*!< [4..4] Use HFRC-192MHz or HFRC2-192MHz for MCU                            */
      __IOM uint32_t FRCHFRC2   : 1;            /*!< [5..5] Force HFRC2 On.Setting this bit forces HFRC2 to remain
                                                     on, including in deep sleep. When changing a module's clock
                                                     source to HFRC2, this bit must be set and remain set when
                                                     any module is using HFRC2 as its clock.                                   */
            uint32_t            : 2;
      __IOM uint32_t PWRONCLKENGFX : 1;         /*!< [8..8] Chicken bit to disable Rev B clock enable during reset             */
            uint32_t            : 1;
      __IOM uint32_t PWRONCLKENSDIO : 1;        /*!< [10..10] Chicken bit to disable Rev B clock enable during reset           */
      __IOM uint32_t PWRONCLKENCRYPTO : 1;      /*!< [11..11] Chicken bit to disable Rev B clock enable during reset           */
      __IOM uint32_t PWRONCLKENI2S0 : 1;        /*!< [12..12] Chicken bit to disable Rev B clock enable during reset           */
      __IOM uint32_t PWRONCLKENI2S1 : 1;        /*!< [13..13] Chicken bit to disable Rev B clock enable during reset           */
      __IOM uint32_t AXIXACLKENOVRRIDE : 1;     /*!< [14..14] Chicken bit to disable Rev B added clock gating                  */
      __IOM uint32_t PWRONCLKENI2S0REFCLK : 1;  /*!< [15..15] Chicken bit to disable Rev B clock enable during reset           */
      __IOM uint32_t PWRONCLKENI2S1REFCLK : 1;  /*!< [16..16] Chicken bit to disable Rev B clock enable during reset           */
            uint32_t            : 1;
      __IOM uint32_t CM4DAXICLKGATEEN : 1;      /*!< [18..18] Chicken bit to enable clock gating on CM4 DAXI CLK               */
      __IOM uint32_t GFXCLKCLKGATEEN : 1;       /*!< [19..19] Chicken bit to enable clock gating on GFX CLK                    */
      __IOM uint32_t GFXAXICLKCLKGATEEN : 1;    /*!< [20..20] Chicken bit to enable clock gating on GFX AXI CLK                */
      __IOM uint32_t APBDMACPUCLKCLKGATEEN : 1; /*!< [21..21] Chicken bit to enable clock gating on APB DMA CPU CLK            */
      __IOM uint32_t ETMTRACECLKCLKGATEEN : 1;  /*!< [22..22] Chicken bit to enable clock gating on ETM TRACE CLK              */
      __IOM uint32_t HFRCFUNCCLKGATEEN : 1;     /*!< [23..23] Chicken bit to enable clock gating on HFRC_FUNC_CLK              */
      __IOM uint32_t HFRC96TRUNKGATE : 1;       /*!< [24..24] DO NOT USE. HFRC96_TRUNK_GATE. Setting this bit when
                                                     BIT23=0, will kill HFRC root clock.                                       */
      __IOM uint32_t CLKGENMISCSPARE : 1;       /*!< [25..25] Spare/Unused Chicken Bit                                         */
            uint32_t            : 6;
    } MISC_b;
  } ;

  union {
    __IOM uint32_t HF2ADJ0;                     /*!< (@ 0x00000048) This register controls hf2adj enable, fast_start
                                                                    enable, fast_start_delay setting and counter
                                                                    input offset.                                              */

    struct {
      __IOM uint32_t HF2ADJEN   : 1;            /*!< [0..0] HF2ADJ control                                                     */
      __IOM uint32_t HF2ADJFASTSTREN : 1;       /*!< [1..1] Fast_start_delay control                                           */
      __IOM uint32_t HF2ADJFASTSTRDLY : 13;     /*!< [14..2] Fast_start_delay value setting                                    */
      __IOM uint32_t HF2ADJCNTINOFFSET : 14;    /*!< [28..15] Counter input offset                                             */
      __IOM uint32_t HF2ADJXTHSMUXSEL : 1;      /*!< [29..29] 0=XTHS 1=EXTREF select                                           */
            uint32_t            : 2;
    } HF2ADJ0_b;
  } ;

  union {
    __IOM uint32_t HF2ADJ1;                     /*!< (@ 0x0000004C) This register controls hf2adj trimming enable
                                                                    and trimming offset.                                       */

    struct {
      __IOM uint32_t HF2ADJTRIMEN : 3;          /*!< [2..0] HF2ADJ output selection                                            */
      __IOM uint32_t HF2ADJTRIMOFFSET : 11;     /*!< [13..3] HF2ADJ trimming offset. (signed number)                           */
            uint32_t            : 18;
    } HF2ADJ1_b;
  } ;

  union {
    __IOM uint32_t HF2ADJ2;                     /*!< (@ 0x00000050) This register controls xtal32m divider ratio
                                                                    and HF2ADJ ration setting.                                 */

    struct {
      __IOM uint32_t HF2ADJXTALDIVRATIO : 2;    /*!< [1..0] XTAL32MHz divider ratio for HF2ADJ.                                */
      __IOM uint32_t HF2ADJRATIO : 29;          /*!< [30..2] HF2ADJ ratio setting.                                             */
            uint32_t            : 1;
    } HF2ADJ2_b;
  } ;

  union {
    __IOM uint32_t HF2VAL;                      /*!< (@ 0x00000054) This register provides the read back of the HF2TUNE        */

    struct {
      __IOM uint32_t HF2ADJTRIMOUT : 11;        /*!< [10..0] HF2ADJ trimming output                                            */
            uint32_t            : 21;
    } HF2VAL_b;
  } ;
  __IM  uint32_t  RESERVED4[8];

  union {
    __IOM uint32_t LFRCCTRL;                    /*!< (@ 0x00000078) LFRC control                                               */

    struct {
      __IOM uint32_t LFRCOUT    : 1;            /*!< [0..0] Disable LFRC output                                                */
      __IOM uint32_t LFRCPWD    : 1;            /*!< [1..1] Power down LFRC                                                    */
            uint32_t            : 30;
    } LFRCCTRL_b;
  } ;
  __IM  uint32_t  RESERVED5[2];

  union {
    __IOM uint32_t DISPCLKCTRL;                 /*!< (@ 0x00000084) Provides ability to select the PLL reference
                                                                    clock, and derivative of the display clock                 */

    struct {
      __IOM uint32_t PLLCLKSEL  : 2;            /*!< [1..0] Selection for PLL reference clock.                                 */
            uint32_t            : 1;
      __IOM uint32_t PLLCLKEN   : 1;            /*!< [3..3] Enable for the PLL clock through clkgen                            */
      __IOM uint32_t DISPCLKSEL : 2;            /*!< [5..4] Selection for PLL reference clock.                                 */
            uint32_t            : 26;
    } DISPCLKCTRL_b;
  } ;

  union {
    __IOM uint32_t CLKGENSPARES;                /*!< (@ 0x00000088) CLKGEN Spare Regs                                          */

    struct {
      __IOM uint32_t CLKGENSPARES : 32;         /*!< [31..0] Placeholer spare registes that can be used as needed
                                                     for future use                                                            */
    } CLKGENSPARES_b;
  } ;

  union {
    __IOM uint32_t HFRCIDLECOUNTERS;            /*!< (@ 0x0000008C) Provides SW controlled # idle cycles before powering
                                                                    down HFRC, HFRC2., core clock enable(s)                    */

    struct {
      __IOM uint32_t HFRCPWRDOWNDELAY : 6;      /*!< [5..0] Idle counter for HFRC POWER DOWN DELAY                             */
            uint32_t            : 2;
      __IOM uint32_t HFRCCLKREQDELAY : 6;       /*!< [13..8] Idle counter for HFRC CLK REQ DELAY                               */
            uint32_t            : 2;
      __IOM uint32_t HFRC2PWRDOWNDELAY : 6;     /*!< [21..16] Idle counter for HFRC2 POWER DOWN DELAY                          */
            uint32_t            : 2;
      __IOM uint32_t HFRC2CLKREQDELAY : 6;      /*!< [29..24] Enable for the PLL clock through clkgen                          */
            uint32_t            : 1;
      __IOM uint32_t UPDATEENABLE : 1;          /*!< [31..31] usage : Clear UPDATEENABLE or 1'b0; Update other bits
                                                     fields of this register. Set this register to 1'b1 for
                                                     HW to update.                                                             */
    } HFRCIDLECOUNTERS_b;
  } ;
  __IM  uint32_t  RESERVED6[28];

  union {
    __IOM uint32_t INTRPTEN;                    /*!< (@ 0x00000100) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t OF         : 1;            /*!< [0..0] XT Oscillator Fail interrupt                                       */
            uint32_t            : 31;
    } INTRPTEN_b;
  } ;

  union {
    __IOM uint32_t INTRPTSTAT;                  /*!< (@ 0x00000104) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t OF         : 1;            /*!< [0..0] XT Oscillator Fail interrupt                                       */
            uint32_t            : 31;
    } INTRPTSTAT_b;
  } ;

  union {
    __IOM uint32_t INTRPTCLR;                   /*!< (@ 0x00000108) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t OF         : 1;            /*!< [0..0] XT Oscillator Fail interrupt                                       */
            uint32_t            : 31;
    } INTRPTCLR_b;
  } ;

  union {
    __IOM uint32_t INTRPTSET;                   /*!< (@ 0x0000010C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t OF         : 1;            /*!< [0..0] XT Oscillator Fail interrupt                                       */
            uint32_t            : 31;
    } INTRPTSET_b;
  } ;
} CLKGEN_Type;                                  /*!< Size = 272 (0x110)                                                        */



/* =========================================================================================================================== */
/* ================                                            CPU                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief CM4 Complex Registers (Cache, TCM, DAXI) (CPU)
  */

typedef struct {                                /*!< (@ 0x48000000) CPU Structure                                              */

  union {
    __IOM uint32_t CACHECFG;                    /*!< (@ 0x00000000) CM4 Cache Control                                          */

    struct {
      __IOM uint32_t ENABLE     : 1;            /*!< [0..0] Enables the CM4 cache controller and enables power to
                                                     the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE should
                                                     be set to enable caching for each type of access.                         */
      __IOM uint32_t LRU        : 1;            /*!< [1..1] Sets the cache repleacment policy. 0=LRR (least recently
                                                     replaced), 1=LRU (least recently used). LRR minimizes writes
                                                     to the TAG SRAM.                                                          */
      __IOM uint32_t NC0ENABLE  : 1;            /*!< [2..2] Enable Non-cacheable region 0. See NCR0 registers to
                                                     define the region.                                                        */
      __IOM uint32_t NC1ENABLE  : 1;            /*!< [3..3] Enable Non-cacheable region 1. See NCR1 registers to
                                                     define the region.                                                        */
      __IOM uint32_t CONFIG     : 4;            /*!< [7..4] Sets the cache configuration                                       */
      __IOM uint32_t IENABLE    : 1;            /*!< [8..8] Enable CM4 Instruction Caching                                     */
      __IOM uint32_t DENABLE    : 1;            /*!< [9..9] Enable CM4 Data Caching.                                           */
      __IOM uint32_t CLKGATE    : 1;            /*!< [10..10] Enable clock gating of cache TAG RAM. Software should
                                                     enable this bit for optimal power efficiency.                             */
      __IOM uint32_t LS         : 1;            /*!< [11..11] Enable LS (light sleep) of cache RAMs. Software should
                                                     DISABLE this bit since cache activity is too high to benefit
                                                     from LS usage.                                                            */
      __IOM uint32_t NC1CACHELOCK : 1;          /*!< [12..12] Only valid when Cache Mode D is set. When high sets
                                                     the mode of the the NC1 region such that all accesse to
                                                     this region are cached in to the upper half of the cache.
                                                     When set low then NCR1 is non cacheable.                                  */
      __IOM uint32_t NC0CACHELOCK : 1;          /*!< [13..13] Only valid when Cache Mode D is set. When high sets
                                                     the mode of the the NC0 region such that all accesse to
                                                     this region are cached in to the lower half of the cache.
                                                     When set low then NCR0 is non cacheable.                                  */
            uint32_t            : 6;
      __IOM uint32_t DATACLKGATE : 1;           /*!< [20..20] Enable aggressive clock gating of entire data array.
                                                     This bit should be set to 1 for optimal power efficiency.                 */
            uint32_t            : 3;
      __IOM uint32_t ENABLEMONITOR : 1;         /*!< [24..24] Enable Cache Monitoring Stats. Cache monitoring consumes
                                                     additional power and should only be enabled when profiling
                                                     code and counters will increment when this bit is set.
                                                     Counter values will be retained when this is set to 0,
                                                     allowing software to enable/disable counting for multiple
                                                     code segments.                                                            */
            uint32_t            : 7;
    } CACHECFG_b;
  } ;
  __IM  uint32_t  RESERVED;

  union {
    __IOM uint32_t CACHECTRL;                   /*!< (@ 0x00000008) Cache Control                                              */

    struct {
      __IOM uint32_t INVALIDATE : 1;            /*!< [0..0] Writing a 1 to this bitfield invalidates the CM4 cache
                                                     contents.                                                                 */
      __IOM uint32_t RESETSTAT  : 1;            /*!< [1..1] Reset Cache Statistics. When written to a 1, the cache
                                                     monitor counters will be cleared. The monitor counters
                                                     can be reset only when the CACHECFG.ENABLE_MONITOR bit
                                                     is set.                                                                   */
      __IOM uint32_t CACHEREADY : 1;            /*!< [2..2] Cache Ready Status (enabled and not processing an invalidate
                                                     operation)                                                                */
            uint32_t            : 29;
    } CACHECTRL_b;
  } ;
  __IM  uint32_t  RESERVED1;

  union {
    __IOM uint32_t NCR0START;                   /*!< (@ 0x00000010) CM4 Cache Noncachable Region 0 Start                       */

    struct {
            uint32_t            : 4;
      __IOM uint32_t ADDR       : 25;           /*!< [28..4] Start address for non-cacheable region 0                          */
            uint32_t            : 3;
    } NCR0START_b;
  } ;

  union {
    __IOM uint32_t NCR0END;                     /*!< (@ 0x00000014) CM4 Cache Noncachable Region 0 End                         */

    struct {
            uint32_t            : 4;
      __IOM uint32_t ADDR       : 25;           /*!< [28..4] End address for non-cacheable region 0                            */
            uint32_t            : 3;
    } NCR0END_b;
  } ;

  union {
    __IOM uint32_t NCR1START;                   /*!< (@ 0x00000018) CM4 Cache Noncachable Region 1 Start                       */

    struct {
            uint32_t            : 4;
      __IOM uint32_t ADDR       : 25;           /*!< [28..4] Start address for non-cacheable region 1                          */
            uint32_t            : 3;
    } NCR1START_b;
  } ;

  union {
    __IOM uint32_t NCR1END;                     /*!< (@ 0x0000001C) CM4 Cache Noncachable Region 1 End                         */

    struct {
            uint32_t            : 4;
      __IOM uint32_t ADDR       : 25;           /*!< [28..4] End address for non-cacheable region 1                            */
            uint32_t            : 3;
    } NCR1END_b;
  } ;
  __IM  uint32_t  RESERVED2[12];

  union {
    __IOM uint32_t DAXICFG;                     /*!< (@ 0x00000050) DAXI Config                                                */

    struct {
      __IOM uint32_t FLUSHLEVEL : 1;            /*!< [0..0] Level of free buffers to flush out dirty buffers.                  */
      __IOM uint32_t AGINGSENABLE : 1;          /*!< [1..1] Enables flushing out shared lines using the aging mechanism.       */
      __IOM uint32_t DAXIPASSTHROUGH : 1;       /*!< [2..2] Passes requests through DAXI logic, disables caching
                                                     lines in the DAXI line buffers.                                           */
      __IOM uint32_t DAXIBECLKGATEEN : 1;       /*!< [3..3] Enables clock gating of DAXI line buffer byte enables.             */
      __IOM uint32_t DAXIDATACLKGATEEN : 1;     /*!< [4..4] Enables clock gating of DAXI line buffer data.                     */
      __IOM uint32_t DAXISTATECLKGATEEN : 1;    /*!< [5..5] Enables clock gating of DAXI state.                                */
            uint32_t            : 2;
      __IOM uint32_t BUFFERENABLE : 4;          /*!< [11..8] Enables DAXI buffers                                              */
            uint32_t            : 4;
      __IOM uint32_t AGINGCOUNTER : 5;          /*!< [20..16] Specifies the relative time that DAXI buffers may remain
                                                     unused before being flushed. Counter is based on CPU clock
                                                     cycles and buffers will generally be flushed in 1-2 AGINGCOUNTER
                                                     timesteps.                                                                */
            uint32_t            : 3;
      __IOM uint32_t MRUGROUPLEVEL : 2;         /*!< [25..24] Sets the MRU group population limit.                             */
            uint32_t            : 6;
    } DAXICFG_b;
  } ;

  union {
    __IOM uint32_t DAXICTRL;                    /*!< (@ 0x00000054) DAXI Control                                               */

    struct {
      __IOM uint32_t DAXIFLUSHWRITE : 1;        /*!< [0..0] Writing a 1 to this bitfield forces a flush of WRITE
                                                     (W->I) or MODIFIED buffers (M->S).                                        */
      __IOM uint32_t DAXIINVALIDATE : 1;        /*!< [1..1] Writing a 1 to this bitfield invalidates any SHARED data
                                                     buffers (S->I).                                                           */
      __IOM uint32_t DAXIREADY  : 1;            /*!< [2..2] DAXI Ready Status (enabled and not processing a flush
                                                     of WRITE or MODIFIED buffers)                                             */
      __IOM uint32_t DAXIBUSY   : 1;            /*!< [3..3] DAXI status indicating DAXI is busy.                               */
      __IOM uint32_t DAXIAHBBUSY : 1;           /*!< [4..4] DAXI status indicating DAXI AHB interface is busy.                 */
      __IOM uint32_t DAXISHARED : 1;            /*!< [5..5] DAXI status indicating at least one full buffer is shared.         */
      __IOM uint32_t DAXIMODIFIED : 1;          /*!< [6..6] DAXI status indicating at least one full buffer has modified
                                                     data.                                                                     */
      __IOM uint32_t DAXIWRITE  : 1;            /*!< [7..7] DAXI status indicating at least one partially written
                                                     buffer has modified data.                                                 */
      __IOM uint32_t DAXIWALLOC : 1;            /*!< [8..8] DAXI status indicating at least one write allocation
                                                     is waiting for prior store to complete.                                   */
      __IOM uint32_t DAXIWRLOAD : 1;            /*!< [9..9] DAXI status indicating at least one partially written
                                                     buffer is waiting for load to convert to modified.                        */
      __IOM uint32_t DAXISTORE  : 1;            /*!< [10..10] DAXI status indicating at least one buffer has outstanding
                                                     store waiting to complete.                                                */
      __IOM uint32_t DAXIBRESPPENDING : 1;      /*!< [11..11] DAXI status indicating at least one AXI B repsonse
                                                     for a store is pending.                                                   */
      __IOM uint32_t DAXIRAXIBUSY : 1;          /*!< [12..12] DAXI status indicating the DAXI RAXI interface is busy.          */
            uint32_t            : 19;
    } DAXICTRL_b;
  } ;
  __IM  uint32_t  RESERVED3[10];

  union {
    __IOM uint32_t ICODEFAULTADDR;              /*!< (@ 0x00000080) ICODE bus address which was present when a bus
                                                                    fault occurred.                                            */

    struct {
      __IOM uint32_t ICODEFAULTADDR : 32;       /*!< [31..0] The ICODE bus address observed when a Bus Fault occurred.
                                                     Once an address is captured in this field, it is held until
                                                     the corresponding Fault Observed bit is cleared in the
                                                     FAULTSTATUS register.                                                     */
    } ICODEFAULTADDR_b;
  } ;

  union {
    __IOM uint32_t DCODEFAULTADDR;              /*!< (@ 0x00000084) DCODE bus address which was present when a bus
                                                                    fault occurred.                                            */

    struct {
      __IOM uint32_t DCODEFAULTADDR : 32;       /*!< [31..0] The DCODE bus address observed when a Bus Fault occurred.
                                                     Once an address is captured in this field, it is held until
                                                     the corresponding Fault Observed bit is cleared in the
                                                     FAULTSTATUS register.                                                     */
    } DCODEFAULTADDR_b;
  } ;

  union {
    __IOM uint32_t SYSFAULTADDR;                /*!< (@ 0x00000088) System bus address which was present when a bus
                                                                    fault occurred.                                            */

    struct {
      __IOM uint32_t SYSFAULTADDR : 32;         /*!< [31..0] SYS bus address observed when a Bus Fault occurred.
                                                     Once an address is captured in this field, it is held until
                                                     the corresponding Fault Observed bit is cleared in the
                                                     FAULTSTATUS register.                                                     */
    } SYSFAULTADDR_b;
  } ;

  union {
    __IOM uint32_t FAULTSTATUS;                 /*!< (@ 0x0000008C) Reflects the status of the bus decoders' fault
                                                                    detection. Any write to this register will
                                                                    clear all of the status bits within the
                                                                    register.                                                  */

    struct {
      __IOM uint32_t ICODEFAULT : 1;            /*!< [0..0] The ICODE Bus Decoder Fault Detected bit. When set, a
                                                     fault has been detected, and the ICODEFAULTADDR register
                                                     will contain the bus address which generated the fault.                   */
      __IOM uint32_t DCODEFAULT : 1;            /*!< [1..1] DCODE Bus Decoder Fault Detected bit. When set, a fault
                                                     has been detected, and the DCODEFAULTADDR register will
                                                     contain the bus address which generated the fault.                        */
      __IOM uint32_t SYSFAULT   : 1;            /*!< [2..2] SYS Bus Decoder Fault Detected bit. When set, a fault
                                                     has been detected, and the SYSFAULTADDR register will contain
                                                     the bus address which generated the fault.                                */
            uint32_t            : 29;
    } FAULTSTATUS_b;
  } ;

  union {
    __IOM uint32_t FAULTCAPTUREEN;              /*!< (@ 0x00000090) Enable the fault capture registers                         */

    struct {
      __IOM uint32_t FAULTCAPTUREEN : 1;        /*!< [0..0] Fault Capture Enable field. When set, the Fault Capture
                                                     monitors are enabled and addresses which generate a hard
                                                     fault are captured into the FAULTADDR registers.                          */
            uint32_t            : 31;
    } FAULTCAPTUREEN_b;
  } ;
  __IM  uint32_t  RESERVED4[11];

  union {
    __IOM uint32_t INTEN;                       /*!< (@ 0x000000C0) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t AXIWERROR  : 1;            /*!< [0..0] AXI Write Error Occurred                                           */
            uint32_t            : 31;
    } INTEN_b;
  } ;

  union {
    __IOM uint32_t INTSTAT;                     /*!< (@ 0x000000C4) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t AXIWERROR  : 1;            /*!< [0..0] AXI Write Error Occurred                                           */
            uint32_t            : 31;
    } INTSTAT_b;
  } ;

  union {
    __IOM uint32_t INTCLR;                      /*!< (@ 0x000000C8) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t AXIWERROR  : 1;            /*!< [0..0] AXI Write Error Occurred                                           */
            uint32_t            : 31;
    } INTCLR_b;
  } ;

  union {
    __IOM uint32_t INTSET;                      /*!< (@ 0x000000CC) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t AXIWERROR  : 1;            /*!< [0..0] AXI Write Error Occurred                                           */
            uint32_t            : 31;
    } INTSET_b;
  } ;

  union {
    __IOM uint32_t WRITEERRADDR;                /*!< (@ 0x000000D0) DAXI Write Error Address                                   */

    struct {
      __IOM uint32_t WERRADDR   : 32;           /*!< [31..0] This address will be approximate since multiple write
                                                     transactions might be in flight at any given time. However,
                                                     it should be accurate when debugging/single-stepping                      */
    } WRITEERRADDR_b;
  } ;
  __IM  uint32_t  RESERVED5[11];

  union {
    __IOM uint32_t DMON0;                       /*!< (@ 0x00000100) Data Cache Total Accesses                                  */

    struct {
      __IOM uint32_t DACCESS    : 32;           /*!< [31..0] Total accesses to data cache. All performance metrics
                                                     should be relative to the number of accesses performed.                   */
    } DMON0_b;
  } ;

  union {
    __IOM uint32_t DMON1;                       /*!< (@ 0x00000104) Data Cache Tag Lookups                                     */

    struct {
      __IOM uint32_t DLOOKUP    : 32;           /*!< [31..0] Total tag lookups from data cache.                                */
    } DMON1_b;
  } ;

  union {
    __IOM uint32_t DMON2;                       /*!< (@ 0x00000108) Data Cache Hits                                            */

    struct {
      __IOM uint32_t DHIT       : 32;           /*!< [31..0] Cache hits from lookup operations.                                */
    } DMON2_b;
  } ;

  union {
    __IOM uint32_t DMON3;                       /*!< (@ 0x0000010C) Data Cache Line Hits                                       */

    struct {
      __IOM uint32_t DLINE      : 32;           /*!< [31..0] Cache hits from line cache                                        */
    } DMON3_b;
  } ;

  union {
    __IOM uint32_t IMON0;                       /*!< (@ 0x00000110) Instruction Cache Total Accesses                           */

    struct {
      __IOM uint32_t IACCESS    : 32;           /*!< [31..0] Total accesses to Instruction cache                               */
    } IMON0_b;
  } ;

  union {
    __IOM uint32_t IMON1;                       /*!< (@ 0x00000114) Instruction Cache Tag Lookups                              */

    struct {
      __IOM uint32_t ILOOKUP    : 32;           /*!< [31..0] Total tag lookups from Instruction cache                          */
    } IMON1_b;
  } ;

  union {
    __IOM uint32_t IMON2;                       /*!< (@ 0x00000118) Instruction Cache Hits                                     */

    struct {
      __IOM uint32_t IHIT       : 32;           /*!< [31..0] Cache hits from lookup operations                                 */
    } IMON2_b;
  } ;

  union {
    __IOM uint32_t IMON3;                       /*!< (@ 0x0000011C) Instruction Cache Line Hits                                */

    struct {
      __IOM uint32_t ILINE      : 32;           /*!< [31..0] Cache hits from line cache                                        */
    } IMON3_b;
  } ;
} CPU_Type;                                     /*!< Size = 288 (0x120)                                                        */



/* =========================================================================================================================== */
/* ================                                          CRYPTO                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Embedded security and cryptographic services (CRYPTO)
  */

typedef struct {                                /*!< (@ 0x400C0000) CRYPTO Structure                                           */

  union {
    __IOM uint32_t MEMORYMAP0;                  /*!< (@ 0x00000000) This register maps the virtual register R0 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP0 : 10;         /*!< [10..1] Contains the physical address in memory to map the R0
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP0_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP1;                  /*!< (@ 0x00000004) This register maps the virtual register R1 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP1 : 10;         /*!< [10..1] Contains the physical address in memory to map the R1
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP1_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP2;                  /*!< (@ 0x00000008) This register maps the virtual register R2 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP2 : 10;         /*!< [10..1] Contains the physical address in memory to map the R2
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP2_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP3;                  /*!< (@ 0x0000000C) This register maps the virtual register R3 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP3 : 10;         /*!< [10..1] Contains the physical address in memory to map the R3
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP3_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP4;                  /*!< (@ 0x00000010) This register maps the virtual register R4 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP4 : 10;         /*!< [10..1] Contains the physical address in memory to map the R4
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP4_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP5;                  /*!< (@ 0x00000014) This register maps the virtual register R5 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP5 : 10;         /*!< [10..1] Contains the physical address in memory to map the R5
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP5_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP6;                  /*!< (@ 0x00000018) This register maps the virtual register R6 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP6 : 10;         /*!< [10..1] Contains the physical address in memory to map the R6
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP6_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP7;                  /*!< (@ 0x0000001C) This register maps the virtual register R7 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP7 : 10;         /*!< [10..1] Contains the physical address in memory to map the R7
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP7_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP8;                  /*!< (@ 0x00000020) This register maps the virtual register R8 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP8 : 10;         /*!< [10..1] Contains the physical address in memory to map the R8
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP8_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP9;                  /*!< (@ 0x00000024) This register maps the virtual register R9 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP9 : 10;         /*!< [10..1] Contains the physical address in memory to map the R9
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP9_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP10;                 /*!< (@ 0x00000028) This register maps the virtual register R10 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP10 : 10;        /*!< [10..1] Contains the physical address in memory to map the R10
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP10_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP11;                 /*!< (@ 0x0000002C) This register maps the virtual register R11 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP11 : 10;        /*!< [10..1] Contains the physical address in memory to map the R11
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP11_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP12;                 /*!< (@ 0x00000030) This register maps the virtual register R12 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP12 : 10;        /*!< [10..1] Contains the physical address in memory to map the R12
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP12_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP13;                 /*!< (@ 0x00000034) This register maps the virtual register R13 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP13 : 10;        /*!< [10..1] Contains the physical address in memory to map the R13
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP13_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP14;                 /*!< (@ 0x00000038) This register maps the virtual register R14 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP14 : 10;        /*!< [10..1] Contains the physical address in memory to map the R14
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP14_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP15;                 /*!< (@ 0x0000003C) This register maps the virtual register R15 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP15 : 10;        /*!< [10..1] Contains the physical address in memory to map the R15
                                                     registero.                                                                */
            uint32_t            : 21;
    } MEMORYMAP15_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP16;                 /*!< (@ 0x00000040) This register maps the virtual register R16 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP16 : 10;        /*!< [10..1] Contains the physical address in memory to map the R16
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP16_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP17;                 /*!< (@ 0x00000044) This register maps the virtual register R17 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP17 : 10;        /*!< [10..1] Contains the physical address in memory to map the R17
                                                     registero.                                                                */
            uint32_t            : 21;
    } MEMORYMAP17_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP18;                 /*!< (@ 0x00000048) This register maps the virtual register R18 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP18 : 10;        /*!< [10..1] Contains the physical address in memory to map the R18
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP18_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP19;                 /*!< (@ 0x0000004C) This register maps the virtual register R19 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP19 : 10;        /*!< [10..1] Contains the physical address in memory to map the R19
                                                     register to.                                                              */
            uint32_t            : 21;
    } MEMORYMAP19_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP20;                 /*!< (@ 0x00000050) This register maps the virtual register R20 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP20 : 10;        /*!< [10..1] Contains the physical address in memory to map the R20
                                                     register to.                                                              */
            uint32_t            : 21;
    } MEMORYMAP20_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP21;                 /*!< (@ 0x00000054) This register maps the virtual register R21 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP21 : 10;        /*!< [10..1] Contains the physical address in memory to map the R21
                                                     register to.                                                              */
            uint32_t            : 21;
    } MEMORYMAP21_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP22;                 /*!< (@ 0x00000058) This register maps the virtual register R22 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP22 : 10;        /*!< [10..1] Contains the physical address in memory to map the R22
                                                     register to.                                                              */
            uint32_t            : 21;
    } MEMORYMAP22_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP23;                 /*!< (@ 0x0000005C) This register maps the virtual register R23 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP23 : 10;        /*!< [10..1] Contains the physical address in memory to map the R23
                                                     register to.                                                              */
            uint32_t            : 21;
    } MEMORYMAP23_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP24;                 /*!< (@ 0x00000060) This register maps the virtual register R24 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP24 : 10;        /*!< [10..1] Contains the physical address in memory to map the R24
                                                     register to.                                                              */
            uint32_t            : 21;
    } MEMORYMAP24_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP25;                 /*!< (@ 0x00000064) This register maps the virtual register R25 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP25 : 10;        /*!< [10..1] Contains the physical address in memory to map the R25
                                                     register to.                                                              */
            uint32_t            : 21;
    } MEMORYMAP25_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP26;                 /*!< (@ 0x00000068) This register maps the virtual register R26 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP26 : 10;        /*!< [10..1] Contains the physical address in memory to map the R26
                                                     register to.                                                              */
            uint32_t            : 21;
    } MEMORYMAP26_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP27;                 /*!< (@ 0x0000006C) This register maps the virtual register R27 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP27 : 10;        /*!< [10..1] Contains the physical address in memory to map the R27
                                                     register to.                                                              */
            uint32_t            : 21;
    } MEMORYMAP27_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP28;                 /*!< (@ 0x00000070) This register maps the virtual register R28 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP28 : 10;        /*!< [10..1] Contains the physical address in memory to map the R28
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP28_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP29;                 /*!< (@ 0x00000074) This register maps the virtual register R29 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP29 : 10;        /*!< [10..1] Contains the physical address in memory to map the R29
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP29_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP30;                 /*!< (@ 0x00000078) This register maps the virtual register R30 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP30 : 10;        /*!< [10..1] Contains the physical address in memory to map the R30
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP30_b;
  } ;

  union {
    __IOM uint32_t MEMORYMAP31;                 /*!< (@ 0x0000007C) This register maps the virtual register R31 to
                                                                    a physical address in memory.                              */

    struct {
            uint32_t            : 1;
      __IOM uint32_t PHYSADDRMAP31 : 10;        /*!< [10..1] Contains the physical address in memory to map the R31
                                                     register.                                                                 */
            uint32_t            : 21;
    } MEMORYMAP31_b;
  } ;

  union {
    __IOM uint32_t OPCODE;                      /*!< (@ 0x00000080) This register holds the PKAs OPCODE.                       */

    struct {
      __IOM uint32_t TAG        : 6;            /*!< [5..0] Holds the operations tag or the operand C virtual address.         */
      __IOM uint32_t REGR       : 6;            /*!< [11..6] Result register virtual address 0-15.                             */
      __IOM uint32_t REGB       : 6;            /*!< [17..12] Operand B virtual address 0-15.                                  */
      __IOM uint32_t REGA       : 6;            /*!< [23..18] Operand A virtual address 0-15.                                  */
      __IOM uint32_t LEN        : 3;            /*!< [26..24] The length of the operation. The value serves as a
                                                     pointer to PKA length register, for example, if the value
                                                     is 0, PKA_L0 holds the size of the operation.                             */
      __IOM uint32_t OPCODE     : 5;            /*!< [31..27] Defines the PKA operation:                                       */
    } OPCODE_b;
  } ;

  union {
    __IOM uint32_t NNPT0T1ADDR;                 /*!< (@ 0x00000084) This register maps N_NP_T0_T1 to a virtual address.        */

    struct {
      __IOM uint32_t NVIRTUALADDR : 5;          /*!< [4..0] Virtual address of register N.                                     */
      __IOM uint32_t NPVIRTUALADDR : 5;         /*!< [9..5] Virtual address of register NP.                                    */
      __IOM uint32_t T0VIRTUALADDR : 5;         /*!< [14..10] Virtual address of temporary register number 0                   */
      __IOM uint32_t T1VIRTUALADDR : 5;         /*!< [19..15] Virtual address of temporary register number 1                   */
            uint32_t            : 12;
    } NNPT0T1ADDR_b;
  } ;

  union {
    __IOM uint32_t PKASTATUS;                   /*!< (@ 0x00000088) This register holds the PKA pipe status.                   */

    struct {
      __IOM uint32_t ALUMSB4BITS : 4;           /*!< [3..0] The most significant 4-bits of the operand updated in
                                                     shift operation.                                                          */
      __IOM uint32_t ALULSB4BITS : 4;           /*!< [7..4] The least significant 4-bits of the operand updated in
                                                     shift operation.                                                          */
      __IOM uint32_t ALUSIGNOUT : 1;            /*!< [8..8] Indicates the last operations sign (MSB).                          */
      __IOM uint32_t ALUCARRY   : 1;            /*!< [9..9] Holds the carry of the last ALU operation.                         */
      __IOM uint32_t ALUCARRYMOD : 1;           /*!< [10..10] holds the carry of the last Modular operation.                   */
      __IOM uint32_t ALUSUBISZERO : 1;          /*!< [11..11] Indicates the last subtraction operations sign .                 */
      __IOM uint32_t ALUOUTZERO : 1;            /*!< [12..12] Indicates if the result of ALU OUT is zero.                      */
      __IOM uint32_t ALUMODOVRFLW : 1;          /*!< [13..13] Modular overflow flag.                                           */
      __IOM uint32_t DIVBYZERO  : 1;            /*!< [14..14] Indication if the division is done by zero.                      */
      __IOM uint32_t MODINVOFZERO : 1;          /*!< [15..15] Indicates the Modular inverse of zero.                           */
      __IOM uint32_t OPCODE     : 5;            /*!< [20..16] Opcode of the last operation                                     */
            uint32_t            : 11;
    } PKASTATUS_b;
  } ;

  union {
    __IOM uint32_t PKASWRESET;                  /*!< (@ 0x0000008C) Writing to this register triggers a software
                                                                    reset of the PKA.                                          */

    struct {
      __IOM uint32_t PKASWRESET : 1;            /*!< [0..0] The reset mechanism takes about four PKA clock cycles
                                                     until the reset line is deasserted                                        */
            uint32_t            : 31;
    } PKASWRESET_b;
  } ;

  union {
    __IOM uint32_t PKAL0;                       /*!< (@ 0x00000090) This register holds one of the optional size
                                                                    of the operation.                                          */

    struct {
      __IOM uint32_t PKAL0      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
            uint32_t            : 19;
    } PKAL0_b;
  } ;

  union {
    __IOM uint32_t PKAL1;                       /*!< (@ 0x00000094) This register holds one of the optional size
                                                                    of the operation.                                          */

    struct {
      __IOM uint32_t PKAL1      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
            uint32_t            : 19;
    } PKAL1_b;
  } ;

  union {
    __IOM uint32_t PKAL2;                       /*!< (@ 0x00000098) This register holds one of the optional size
                                                                    of the operation.                                          */

    struct {
      __IOM uint32_t PKAL2      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
            uint32_t            : 19;
    } PKAL2_b;
  } ;

  union {
    __IOM uint32_t PKAL3;                       /*!< (@ 0x0000009C) This register holds one of the optional size
                                                                    of the operation.                                          */

    struct {
      __IOM uint32_t PKAL3      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
            uint32_t            : 19;
    } PKAL3_b;
  } ;

  union {
    __IOM uint32_t PKAL4;                       /*!< (@ 0x000000A0) This register holds one of the optional size
                                                                    of the operation.                                          */

    struct {
      __IOM uint32_t PKAL4      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
            uint32_t            : 19;
    } PKAL4_b;
  } ;

  union {
    __IOM uint32_t PKAL5;                       /*!< (@ 0x000000A4) This register holds one of the optional size
                                                                    of the operation.                                          */

    struct {
      __IOM uint32_t PKAL5      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
            uint32_t            : 19;
    } PKAL5_b;
  } ;

  union {
    __IOM uint32_t PKAL6;                       /*!< (@ 0x000000A8) This register holds one of the optional size
                                                                    of the operation.                                          */

    struct {
      __IOM uint32_t PKAL6      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
            uint32_t            : 19;
    } PKAL6_b;
  } ;

  union {
    __IOM uint32_t PKAL7;                       /*!< (@ 0x000000AC) This register holds one of the optional size
                                                                    of the operation.                                          */

    struct {
      __IOM uint32_t PKAL7      : 13;           /*!< [12..0] Size of the operation in bytes.                                   */
            uint32_t            : 19;
    } PKAL7_b;
  } ;

  union {
    __IOM uint32_t PKAPIPERDY;                  /*!< (@ 0x000000B0) This register indicates whether the PKA pipe
                                                                    is ready to receive a new OPCODE.                          */

    struct {
      __IOM uint32_t PKAPIPERDY : 1;            /*!< [0..0] Indication whether PKA pipe is ready for new OPCODE.               */
            uint32_t            : 31;
    } PKAPIPERDY_b;
  } ;

  union {
    __IOM uint32_t PKADONE;                     /*!< (@ 0x000000B4) This register indicates whether PKA operation
                                                                    is completed.                                              */

    struct {
      __IOM uint32_t PKADONE    : 1;            /*!< [0..0] Indicates if PKA operation is completed, and pipe is
                                                     empty.                                                                    */
            uint32_t            : 31;
    } PKADONE_b;
  } ;

  union {
    __IOM uint32_t PKAMONSELECT;                /*!< (@ 0x000000B8) This register defines which PKA FSM monitor is
                                                                    being output.                                              */

    struct {
      __IOM uint32_t PKAMONSELECT : 4;          /*!< [3..0] Defines which PKA FSM monitor is being output.                     */
            uint32_t            : 28;
    } PKAMONSELECT_b;
  } ;
  __IM  uint32_t  RESERVED[2];

  union {
    __IOM uint32_t PKAVERSION;                  /*!< (@ 0x000000C4) This register holds the pka version                        */

    struct {
      __IOM uint32_t PKAVERSION : 32;           /*!< [31..0] This is the PKA version                                           */
    } PKAVERSION_b;
  } ;
  __IM  uint32_t  RESERVED1[2];

  union {
    __IOM uint32_t PKAMONREAD;                  /*!< (@ 0x000000D0) The PKA monitor bus register.                              */

    struct {
      __IOM uint32_t PKAMONREAD : 32;           /*!< [31..0] This is the PKA monitor bus register output                       */
    } PKAMONREAD_b;
  } ;

  union {
    __IOM uint32_t PKASRAMADDR;                 /*!< (@ 0x000000D4) first address given to PKA SRAM for write transactions.    */

    struct {
      __IOM uint32_t PKASRAMADDR : 32;          /*!< [31..0] PKA SRAM write starting address                                   */
    } PKASRAMADDR_b;
  } ;

  union {
    __IOM uint32_t PKASRAMWDATA;                /*!< (@ 0x000000D8) Write data to PKA SRAM.                                    */

    struct {
      __IOM uint32_t PKASRAMWDATA : 32;         /*!< [31..0] 32 bit write to PKA SRAM: triggers the SRAM write DMA
                                                     address automatically incremented                                         */
    } PKASRAMWDATA_b;
  } ;

  union {
    __IOM uint32_t PKASRAMRDATA;                /*!< (@ 0x000000DC) Read data from PKA SRAM.                                   */

    struct {
      __IOM uint32_t PKASRAMRDATA : 32;         /*!< [31..0] 32 bit read from PKA SRAM: read - triggers the SRAM
                                                     read DMA address automatically incremented                                */
    } PKASRAMRDATA_b;
  } ;

  union {
    __IOM uint32_t PKASRAMWRCLR;                /*!< (@ 0x000000E0) Write buffer clean.                                        */

    struct {
      __IOM uint32_t PKASRAMWRCLR : 32;         /*!< [31..0] Clear the write buffer.                                           */
    } PKASRAMWRCLR_b;
  } ;

  union {
    __IOM uint32_t PKASRAMRADDR;                /*!< (@ 0x000000E4) first address given to PKA SRAM for read transactions.     */

    struct {
      __IOM uint32_t PKASRAMRADDR : 32;         /*!< [31..0] PKA SRAM read starting address                                    */
    } PKASRAMRADDR_b;
  } ;
  __IM  uint32_t  RESERVED2[2];

  union {
    __IOM uint32_t PKAWORDACCESS;               /*!< (@ 0x000000F0) This register holds the data written to PKA memory
                                                                    using the wop opcode.                                      */

    struct {
      __IOM uint32_t PKAWORDACCESS : 32;        /*!< [31..0] 32 bit read_write data.                                           */
    } PKAWORDACCESS_b;
  } ;
  __IM  uint32_t  RESERVED3;

  union {
    __IOM uint32_t PKABUFFADDR;                 /*!< (@ 0x000000F8) This register maps the virtual buffer registers
                                                                    to a physical address in memory.                           */

    struct {
      __IOM uint32_t PKABUFADDR : 12;           /*!< [11..0] Contains the physical address in memory to map the buffer
                                                     registers.                                                                */
            uint32_t            : 20;
    } PKABUFFADDR_b;
  } ;
  __IM  uint32_t  RESERVED4;

  union {
    __IOM uint32_t RNGIMR;                      /*!< (@ 0x00000100) Interrupt masking register. Consists of {prng_imr
                                                                    trng_imr} bit[31-16] - PRNG_IMR bit[15-0]
                                                                    - TRNG_IMR(Ws - PRNG bit exists only if
                                                                    PRNG_EXISTS flag)                                          */

    struct {
      __IOM uint32_t EHRVALIDINTMASK : 1;       /*!< [0..0] 0x1 - masks the EHR interrupt. No interrupt is generated.          */
      __IOM uint32_t AUTOCORRERRINTMASK : 1;    /*!< [1..1] 0x1 - masks the autocorrelation interrupt. No interrupt
                                                     is generated.                                                             */
      __IOM uint32_t CRNGTERRINTMASK : 1;       /*!< [2..2] 0x1 - masks the CRNGT error interrupt. No interrupt is
                                                     generated.                                                                */
      __IOM uint32_t VNERRINTMASK : 1;          /*!< [3..3] 0x1 - masks the Von-Neumann error interrupt. No interrupt
                                                     is generated.                                                             */
      __IOM uint32_t WATCHDOGINTMASK : 1;       /*!< [4..4] 0x1 - masks the watchdog interrupt. No interrupt is generated.     */
      __IOM uint32_t RNGDMADONEINT : 1;         /*!< [5..5] 0x1 - masks the RNG DMA completion interrupt. No interrupt
                                                     is generated.                                                             */
            uint32_t            : 26;
    } RNGIMR_b;
  } ;

  union {
    __IOM uint32_t RNGISR;                      /*!< (@ 0x00000104) Status register. If corresponding RNG_IMR bit
                                                                    is unmasked, an interrupt is generated.Consists
                                                                    of trng_isr and prng_isr bit[15-0] - TRNG
                                                                    bit[31-16] - PRNG                                          */

    struct {
      __IOM uint32_t EHRVALID   : 1;            /*!< [0..0] 0x1 indicates that 192 bits have been collected in the
                                                     TRNG and are ready to be read.                                            */
      __IOM uint32_t AUTOCORRERR : 1;           /*!< [1..1] 0x1 indicates Autocorrelation test failed four times
                                                     in a row. When it set ,TRNG ceases to function until next
                                                     reset.                                                                    */
      __IOM uint32_t CRNGTERR   : 1;            /*!< [2..2] 0x1 indicates CRNGT in the TRNG test failed. Failure
                                                     occurs when two consecutive blocks of 16 collected bits
                                                     are equal.                                                                */
      __IOM uint32_t VNERR      : 1;            /*!< [3..3] 0x1 indicates Von Neumann error. Error in von Neumann
                                                     occurs if 32 consecutive collected bits are identical,
                                                     ZERO, or ONE.                                                             */
            uint32_t            : 1;
      __IOM uint32_t RNGDMADONE : 1;            /*!< [5..5] 0x1 indicates RNG DMA to SRAM is completed.                        */
            uint32_t            : 10;
      __IOM uint32_t RESEEDINGDONE : 1;         /*!< [16..16] 0x1 indicates completion of reseeding algorithm with
                                                     no errors.                                                                */
      __IOM uint32_t INSTANTIATIONDONE : 1;     /*!< [17..17] 0x1 indicates completion of instantiation algorithm
                                                     with no errors.                                                           */
      __IOM uint32_t FINALUPDATEDONE : 1;       /*!< [18..18] 0x1 indicates completion of final update algorithm.              */
      __IOM uint32_t OUTPUTREADY : 1;           /*!< [19..19] 0x1 indicates that the result of PRNG is valid and
                                                     ready to be read. The result can be read from the RNG_READOUT
                                                     register.                                                                 */
      __IOM uint32_t RESEEDCNTRFULL : 1;        /*!< [20..20] 0x1 indicates that the reseed counter has reached 2^48,
                                                     requiring to run the reseed algorithm before generating
                                                     new random numbers.                                                       */
      __IOM uint32_t RESEEDCNTRTOP40 : 1;       /*!< [21..21] 0x1 indicates that the top 40 bits of the reseed counter
                                                     are set (that is the reseed counter is larger than 2^48-2^8).
                                                     This is a recommendation for running the reseed algorithm
                                                     before the counter reaches its max value.                                 */
      __IOM uint32_t PRNGCRNGTERR : 1;          /*!< [22..22] 0x1 indicates CRNGT in the PRNG test failed. Failure
                                                     occurs when two consecutive results of AES are equal                      */
      __IOM uint32_t REQSIZE    : 1;            /*!< [23..23] 0x1 indicates that the request size counter (which
                                                     represents how many generations of random bits in the PRNG
                                                     have been produced) has reached 2^12, thus requiring a
                                                     working state update before generating new random numbers.                */
      __IOM uint32_t KATERR     : 1;            /*!< [24..24] 0x1 indicates that one of the KAT (Known Answer Tests)
                                                     tests has failed. When set, the entire engine ceases to
                                                     function.                                                                 */
      __IOM uint32_t WHICHKATERR : 2;           /*!< [26..25] When the KAT_ERR bit is set, these bits represent which
                                                     Known Answer Test had failed:                                             */
            uint32_t            : 5;
    } RNGISR_b;
  } ;

  union {
    __IOM uint32_t RNGICR;                      /*!< (@ 0x00000108) Interrupt_status bit clear Register. Consists
                                                                    of trng_icr and prng_icr bit[15-0] - TRNG
                                                                    bit[31-16] - PRNG                                          */

    struct {
      __IOM uint32_t EHRVALID   : 1;            /*!< [0..0] Writing value 0x1 - clears corresponding bit in RNGISR             */
      __IOM uint32_t AUTOCORRERR : 1;           /*!< [1..1] Cannot be cleared by SW! Only RNG reset clears this bit.           */
      __IOM uint32_t CRNGTERR   : 1;            /*!< [2..2] Writing value 0x1 - clears corresponding bit in RNGISR             */
      __IOM uint32_t VNERR      : 1;            /*!< [3..3] Writing value 0x1 - clears corresponding bit in RNGISR             */
      __IOM uint32_t RNGWATCHDOG : 1;           /*!< [4..4] Writing value 0x1 - clears corresponding bit in RNGISR             */
      __IOM uint32_t RNGDMADONE : 1;            /*!< [5..5] Writing value 0x1 - clears corresponding bit in RNGISR             */
            uint32_t            : 10;
      __IOM uint32_t RESEEDINGDONE : 1;         /*!< [16..16] Writing value 0x1 - clears corresponding bit in RNGISR           */
      __IOM uint32_t INSTANTIATIONDONE : 1;     /*!< [17..17] Writing value 0x1 - clears corresponding bit in RNGISR           */
      __IOM uint32_t FINALUPDATEDONE : 1;       /*!< [18..18] Writing value 0x1 - clears corresponding bit in RNGISR           */
      __IOM uint32_t OUTPUTREADY : 1;           /*!< [19..19] Writing value 0x1 - clears corresponding bit in RNGISR           */
      __IOM uint32_t RESEEDCNTRFULL : 1;        /*!< [20..20] Writing value 0x1 - clears corresponding bit in RNGISR           */
      __IOM uint32_t RESEEDCNTRTOP40 : 1;       /*!< [21..21] Writing value 0x1 - clears corresponding bit in RNGISR           */
      __IOM uint32_t PRNGCRNGTERR : 1;          /*!< [22..22] Writing value 0x1 - clears corresponding bit in RNGISR           */
      __IOM uint32_t REQSIZE    : 1;            /*!< [23..23] Writing value 0x1 - clears corresponding bit in RNGISR           */
      __IOM uint32_t KATERR     : 1;            /*!< [24..24] Cannot be cleared by SW! Only RNG reset clears this
                                                     bit.                                                                      */
      __IOM uint32_t WHICHKATERR : 2;           /*!< [26..25] Cannot be cleared by SW! Only RNG reset clears this
                                                     bit.                                                                      */
            uint32_t            : 5;
    } RNGICR_b;
  } ;

  union {
    __IOM uint32_t TRNGCONFIG;                  /*!< (@ 0x0000010C) This register handles TRNG configuration                   */

    struct {
      __IOM uint32_t RNDSRCSEL  : 2;            /*!< [1..0] Defines the length of the oscillator ring (= the number
                                                     of inverters) out of four possible selections.                            */
      __IOM uint32_t SOPSEL     : 1;            /*!< [2..2] Secure Output Port selection:                                      */
            uint32_t            : 29;
    } TRNGCONFIG_b;
  } ;

  union {
    __IOM uint32_t TRNGVALID;                   /*!< (@ 0x00000110) This register indicates that the TRNG data is
                                                                    valid.                                                     */

    struct {
      __IOM uint32_t EHRVALID   : 1;            /*!< [0..0] 0x1 indicates that collection of bits in the TRNG is
                                                     completed, and data can be read from the EHR_DATA register.               */
            uint32_t            : 31;
    } TRNGVALID_b;
  } ;

  union {
    __IOM uint32_t EHRDATA0;                    /*!< (@ 0x00000114) This register contains the data collected in
                                                                    the TRNG[31_0]. Note: can only be set while
                                                                    in debug mode (rng_debug_enable input is
                                                                    set).                                                      */

    struct {
      __IOM uint32_t EHRDATA    : 32;           /*!< [31..0] Contains the data collected in the TRNG[31_0]. Note:
                                                     can only be set while in debug mode (rng_debug_enable input
                                                     is set).                                                                  */
    } EHRDATA0_b;
  } ;

  union {
    __IOM uint32_t EHRDATA1;                    /*!< (@ 0x00000118) This register contains the data collected in
                                                                    the TRNG[63_32]. Note: can only be set while
                                                                    in debug mode (rng_debug_enable input is
                                                                    set).                                                      */

    struct {
      __IOM uint32_t EHRDATA    : 32;           /*!< [31..0] Contains the data collected in the TRNG[63_32]. Note:
                                                     can only be set while in debug mode (rng_debug_enable input
                                                     is set).                                                                  */
    } EHRDATA1_b;
  } ;

  union {
    __IOM uint32_t EHRDATA2;                    /*!< (@ 0x0000011C) This register contains the data collected in
                                                                    the TRNG[95_64]. Note: can only be set while
                                                                    in debug mode (rng_debug_enable input is
                                                                    set).                                                      */

    struct {
      __IOM uint32_t EHRDATA    : 32;           /*!< [31..0] Contains the data collected in the TRNG[95_64]. Note:
                                                     can only be set while in debug mode (rng_debug_enable input
                                                     is set).                                                                  */
    } EHRDATA2_b;
  } ;

  union {
    __IOM uint32_t EHRDATA3;                    /*!< (@ 0x00000120) This register contains the data collected in
                                                                    the TRNG[127_96]. Note: can only be set
                                                                    while in debug mode (rng_debug_enable input
                                                                    is set).                                                   */

    struct {
      __IOM uint32_t EHRDATA    : 32;           /*!< [31..0] Contains the data collected in the TRNG[127_96]. Note:
                                                     can only be set while in debug mode (rng_debug_enable input
                                                     is set).                                                                  */
    } EHRDATA3_b;
  } ;

  union {
    __IOM uint32_t EHRDATA4;                    /*!< (@ 0x00000124) This register contains the data collected in
                                                                    the TRNG[159_128]. Note: can only be set
                                                                    while in debug mode (rng_debug_enable input
                                                                    is set).                                                   */

    struct {
      __IOM uint32_t EHRDATA    : 32;           /*!< [31..0] Contains the data collected in the TRNG[159_128]. Note:
                                                     can only be set while in debug mode (rng_debug_enable input
                                                     is set).                                                                  */
    } EHRDATA4_b;
  } ;

  union {
    __IOM uint32_t EHRDATA5;                    /*!< (@ 0x00000128) This register contains the data collected in
                                                                    the TRNG[191_160]. Note: can only be set
                                                                    while in debug mode (rng_debug_enable input
                                                                    is set).                                                   */

    struct {
      __IOM uint32_t EHRDATA    : 32;           /*!< [31..0] Contains the data collected in the TRNG[191_160]. Note:
                                                     can only be set while in debug mode (rng_debug_enable input
                                                     is set).                                                                  */
    } EHRDATA5_b;
  } ;

  union {
    __IOM uint32_t RNDSOURCEENABLE;             /*!< (@ 0x0000012C) This register holds the enable signal for the
                                                                    random source.                                             */

    struct {
      __IOM uint32_t RNDSRCEN   : 1;            /*!< [0..0] Enable signal for the random source.                               */
            uint32_t            : 31;
    } RNDSOURCEENABLE_b;
  } ;

  union {
    __IOM uint32_t SAMPLECNT1;                  /*!< (@ 0x00000130) Counts clocks between sampling of random bit.              */

    struct {
      __IOM uint32_t SAMPLECNTR1 : 32;          /*!< [31..0] Sets the number of rng_clk cycles between two consecutive
                                                     ring oscillator samples. Note: If the Von-Neumann is bypassed,
                                                     the minimum value for sample counter must not be less than
                                                     decimal seventeen.                                                        */
    } SAMPLECNT1_b;
  } ;

  union {
    __IOM uint32_t AUTOCORRSTATISTIC;           /*!< (@ 0x00000134) Statistics about autocorrelation test activations.         */

    struct {
      __IOM uint32_t AUTOCORRTRYS : 14;         /*!< [13..0] Count each time an autocorrelation test starts. Any
                                                     write to the register resets the counter. Stops collecting
                                                     statistics if one of the counters has reached the limit.                  */
      __IOM uint32_t AUTOCORRFAILS : 8;         /*!< [21..14] Count each time an autocorrelation test fails. Any
                                                     write to the register resets the counter. Stops collecting
                                                     statistics if one of the counters has reached the limit.                  */
            uint32_t            : 10;
    } AUTOCORRSTATISTIC_b;
  } ;

  union {
    __IOM uint32_t TRNGDEBUGCONTROL;            /*!< (@ 0x00000138) This register is used to debug the TRNG                    */

    struct {
            uint32_t            : 1;
      __IOM uint32_t VNCBYPASS  : 1;            /*!< [1..1] When this bit is set, the Von-Neumann balancer is bypassed
                                                     (including the 32 consecutive bits test). Note: Can only
                                                     be set while in debug mode. If TRNG_TESTS_BYPASS_EN HW
                                                     flag is defined, this bit can be set while not in debug
                                                     mode.                                                                     */
      __IOM uint32_t TRNGCRNGTBYPASS : 1;       /*!< [2..2] When this bit is set, the CRNGT test in the TRNG is bypassed.
                                                     Note: Can only be set while in debug mode. If TRNG_TESTS_BYPASS_EN
                                                     HW flag is defined, this bit can be set while not in debug
                                                     mode.                                                                     */
      __IOM uint32_t AUTOCORRELATEBYPASS : 1;   /*!< [3..3] When this bit is set, the autocorrelation test in the
                                                     TRNG module is bypassed. Note: Can only be set while in
                                                     debug mode. If TRNG_TESTS_BYPASS_EN HW flag is defined,
                                                     this bit can be set while not in debug mode.                              */
            uint32_t            : 28;
    } TRNGDEBUGCONTROL_b;
  } ;
  __IM  uint32_t  RESERVED5;

  union {
    __IOM uint32_t RNGSWRESET;                  /*!< (@ 0x00000140) Generate SW reset solely to RNG block.                     */

    struct {
      __IOM uint32_t RNGSWRESET : 1;            /*!< [0..0] Any value written (0x0 or 0x1) causes a reset cycle to
                                                     the TRNG block.                                                           */
            uint32_t            : 31;
    } RNGSWRESET_b;
  } ;
  __IM  uint32_t  RESERVED6[28];

  union {
    __IOM uint32_t RNGDEBUGENINPUT;             /*!< (@ 0x000001B4) Defines the RNG in debug mode                              */

    struct {
      __IOM uint32_t RNGDEBUGEN : 1;            /*!< [0..0] Reflects the rng_debug_enable input port                           */
            uint32_t            : 31;
    } RNGDEBUGENINPUT_b;
  } ;

  union {
    __IOM uint32_t RNGBUSY;                     /*!< (@ 0x000001B8) RNG busy indication                                        */

    struct {
      __IOM uint32_t RNGBUSY    : 1;            /*!< [0..0] Reflects rng_busy output port which Consists of trng_busy
                                                     and prng_busy.                                                            */
      __IOM uint32_t TRNGBUSY   : 1;            /*!< [1..1] Reflects trng_busy.                                                */
      __IOM uint32_t PRNGBUSY   : 1;            /*!< [2..2] Reflects prng_busy.                                                */
            uint32_t            : 29;
    } RNGBUSY_b;
  } ;

  union {
    __IOM uint32_t RSTBITSCOUNTER;              /*!< (@ 0x000001BC) Resets the counter of collected bits in the TRNG           */

    struct {
      __IOM uint32_t RSTBITSCOUNTER : 1;        /*!< [0..0] Writing any value to this address resets the bits counter
                                                     and trng valid registers.                                                 */
            uint32_t            : 31;
    } RSTBITSCOUNTER_b;
  } ;

  union {
    __IOM uint32_t RNGVERSION;                  /*!< (@ 0x000001C0) This register holds the RNG version                        */

    struct {
      __IOM uint32_t EHRWIDTH192 : 1;           /*!< [0..0] EHR width selection.                                               */
      __IOM uint32_t CRNGTEXISTS : 1;           /*!< [1..1] CRNGT exists.                                                      */
      __IOM uint32_t AUTOCORREXISTS : 1;        /*!< [2..2] Auto correct exists.                                               */
      __IOM uint32_t TRNGTESTSBYPASSEN : 1;     /*!< [3..3] TRNG tests bypass enable.                                          */
      __IOM uint32_t PRNGEXISTS : 1;            /*!< [4..4] PRNG Exists.                                                       */
      __IOM uint32_t KATEXISTS  : 1;            /*!< [5..5] KAT exists.                                                        */
      __IOM uint32_t RESEEDINGEXISTS : 1;       /*!< [6..6] Reseeding exists.                                                  */
      __IOM uint32_t RNGUSE5SBOXES : 1;         /*!< [7..7] RNG use 5 (or 20) SBOX AES                                         */
            uint32_t            : 24;
    } RNGVERSION_b;
  } ;

  union {
    __IOM uint32_t RNGCLKENABLE;                /*!< (@ 0x000001C4) Writing to this register enables_disables the
                                                                    RNG clock.                                                 */

    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Writing value 0x1 enables RNG clock.                               */
            uint32_t            : 31;
    } RNGCLKENABLE_b;
  } ;

  union {
    __IOM uint32_t RNGDMAENABLE;                /*!< (@ 0x000001C8) Writing to this register enables_disables the
                                                                    RNG DMA.                                                   */

    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Writing value 0x1 enables RNG DMA to SRAM. The Value
                                                     is cleared when DMA completes its operation.                              */
            uint32_t            : 31;
    } RNGDMAENABLE_b;
  } ;

  union {
    __IOM uint32_t RNGDMASRCMASK;               /*!< (@ 0x000001CC) This register defines which ring-oscillator length
                                                                    should be used when using the RNG DMA.                     */

    struct {
      __IOM uint32_t ENSRCSEL0  : 1;            /*!< [0..0] Writing value 0x1 enables SRC_SEL 0.                               */
      __IOM uint32_t ENSRCSEL1  : 1;            /*!< [1..1] Writing value 0x1 enables SRC_SEL 1.                               */
      __IOM uint32_t ENSRCSEL2  : 1;            /*!< [2..2] Writing value 0x1 enables SRC_SEL 2.                               */
      __IOM uint32_t ENSRCSEL3  : 1;            /*!< [3..3] Writing value 0x1 enables SRC_SEL 3.                               */
            uint32_t            : 28;
    } RNGDMASRCMASK_b;
  } ;

  union {
    __IOM uint32_t RNGDMASRAMADDR;              /*!< (@ 0x000001D0) This register defines the start address of the
                                                                    DMA for the TRNG data.                                     */

    struct {
      __IOM uint32_t RNGSRAMDMAADDR : 11;       /*!< [10..0] Defines the start address of the DMA for the TRNG data.           */
            uint32_t            : 21;
    } RNGDMASRAMADDR_b;
  } ;
  __IM  uint32_t  RESERVED7;

  union {
    __IOM uint32_t RNGWATCHDOGVAL;              /*!< (@ 0x000001D8) This register defines the number of 192-bits
                                                                    samples that the DMA collects per RNG configuration.bitfie
                                                                    d 7:0 RNG_SAMPLES_NUM rw 0x0 Defines the
                                                                    number of 192-bits samples that the DMA
                                                                    collects per RNG configuration.bitfield
                                                                    31:8 RESERVED rw 0x0 ReservedThis register
                                                                    defines the maximum number of clock cycles
                                                                    per TRNG collection of 192 samples. If the
                                                                    number of cycles for a collection exceeds
                                                                    this threshold, TRNG signals an interrupt.                 */

    struct {
      __IOM uint32_t RNGWATCHDOGVAL : 32;       /*!< [31..0] Defines the maximum number of clock cycles per TRNG
                                                     collection of 192 samples. If the number of cycles for
                                                     a collection exceeds this threshold, TRNG signals an interrupt.           */
    } RNGWATCHDOGVAL_b;
  } ;

  union {
    __IOM uint32_t RNGDMASTATUS;                /*!< (@ 0x000001DC) This register holds the RNG DMA status.                    */

    struct {
      __IOM uint32_t RNGDMABUSY : 1;            /*!< [0..0] Indicates whether DMA is busy.                                     */
      __IOM uint32_t DMASRCSEL  : 2;            /*!< [2..1] The active ring oscillator length using by DMA                     */
      __IOM uint32_t NUMOFSAMPLES : 8;          /*!< [10..3] Number of samples already collected in the current ring
                                                     oscillator chain length.                                                  */
            uint32_t            : 21;
    } RNGDMASTATUS_b;
  } ;
  __IM  uint32_t  RESERVED8[104];

  union {
    __IOM uint32_t CHACHACONTROLREG;            /*!< (@ 0x00000380) CHACHA general configuration.                              */

    struct {
      __IOM uint32_t CHACHAORSALSA : 1;         /*!< [0..0] Core:                                                              */
      __IOM uint32_t INITFROMHOST : 1;          /*!< [1..1] Start init for new Message:                                        */
      __IOM uint32_t CALCKEYFORPOLY1305 : 1;    /*!< [2..2] Only if ChaCha core:                                               */
      __IOM uint32_t KEYLEN     : 1;            /*!< [3..3] For All Core:                                                      */
      __IOM uint32_t NUMOFROUNDS : 2;           /*!< [5..4] The core of ChaCha is a hash function which based on
                                                     rotation operations. The hash function consist in application
                                                     of 20 rounds (default value). In additional, ChaCha have
                                                     two variants (they work exactly as the original algorithm):
                                                     ChaCha20_8 and ChaCha20_12 (using 8 and 12 rounds).                       */
            uint32_t            : 3;
      __IOM uint32_t RESETBLOCKCNT : 1;         /*!< [9..9] For new message                                                    */
      __IOM uint32_t USEIV96BIT : 1;            /*!< [10..10] If use 96bit IV                                                  */
            uint32_t            : 21;
    } CHACHACONTROLREG_b;
  } ;

  union {
    __IOM uint32_t CHACHAVERSION;               /*!< (@ 0x00000384) CHACHA Version                                             */

    struct {
      __IOM uint32_t CHACHAVERSION : 32;        /*!< [31..0] CHACHA version.                                                   */
    } CHACHAVERSION_b;
  } ;

  union {
    __IOM uint32_t CHACHAKEY0;                  /*!< (@ 0x00000388) bits 255:224 of CHACHA Key                                 */

    struct {
      __IOM uint32_t CHACHAKEY0 : 32;           /*!< [31..0] bits 255:224 of CHACHA Key                                        */
    } CHACHAKEY0_b;
  } ;

  union {
    __IOM uint32_t CHACHAKEY1;                  /*!< (@ 0x0000038C) bits 223:192 of CHACHA Key                                 */

    struct {
      __IOM uint32_t CHACHAKEY1 : 32;           /*!< [31..0] bits 223:192 of CHACHA Key                                        */
    } CHACHAKEY1_b;
  } ;

  union {
    __IOM uint32_t CHACHAKEY2;                  /*!< (@ 0x00000390) bits 191:160 of CHACHA Key                                 */

    struct {
      __IOM uint32_t CHACHAKEY2 : 32;           /*!< [31..0] bits191:160 of CHACHA Key                                         */
    } CHACHAKEY2_b;
  } ;

  union {
    __IOM uint32_t CHACHAKEY3;                  /*!< (@ 0x00000394) bits159:128 of CHACHA Key                                  */

    struct {
      __IOM uint32_t CHACHAKEY3 : 32;           /*!< [31..0] bits 159:128 of CHACHA Key                                        */
    } CHACHAKEY3_b;
  } ;

  union {
    __IOM uint32_t CHACHAKEY4;                  /*!< (@ 0x00000398) bits 127:96 of CHACHA Key                                  */

    struct {
      __IOM uint32_t CHACHAKEY4 : 32;           /*!< [31..0] bits 127:96 of CHACHA Key                                         */
    } CHACHAKEY4_b;
  } ;

  union {
    __IOM uint32_t CHACHAKEY5;                  /*!< (@ 0x0000039C) bits 95:64 of CHACHA Key                                   */

    struct {
      __IOM uint32_t CHACHAKEY5 : 32;           /*!< [31..0] bits 95:64 of CHACHA Key                                          */
    } CHACHAKEY5_b;
  } ;

  union {
    __IOM uint32_t CHACHAKEY6;                  /*!< (@ 0x000003A0) bits 63:32 of CHACHA Key                                   */

    struct {
      __IOM uint32_t CHACHAKEY6 : 32;           /*!< [31..0] bits 63:32 of CHACHA Key                                          */
    } CHACHAKEY6_b;
  } ;

  union {
    __IOM uint32_t CHACHAKEY7;                  /*!< (@ 0x000003A4) bits 31:0 of CHACHA Key                                    */

    struct {
      __IOM uint32_t CHACHAKEY7 : 32;           /*!< [31..0] bits 31:0 of CHACHA Key                                           */
    } CHACHAKEY7_b;
  } ;

  union {
    __IOM uint32_t CHACHAIV0;                   /*!< (@ 0x000003A8) bits 31:0 of CHACHA_IV0 register                           */

    struct {
      __IOM uint32_t CHACHAIV0  : 32;           /*!< [31..0] bits 31:0 of CHACHA_IV0 register                                  */
    } CHACHAIV0_b;
  } ;

  union {
    __IOM uint32_t CHACHAIV1;                   /*!< (@ 0x000003AC) bits 31:0 of CHACHA_IV1 register                           */

    struct {
      __IOM uint32_t CHACHAIV1  : 32;           /*!< [31..0] bits 31:0 of CHACHA_IV1 register                                  */
    } CHACHAIV1_b;
  } ;

  union {
    __IOM uint32_t CHACHABUSY;                  /*!< (@ 0x000003B0) This register is set when the CHACHA_SALSA core
                                                                    is active                                                  */

    struct {
      __IOM uint32_t CHACHABUSY : 1;            /*!< [0..0] CHACHA_BUSY Register. This register is set when the CHACHA_SALSA
                                                     core is active.                                                           */
            uint32_t            : 31;
    } CHACHABUSY_b;
  } ;

  union {
    __IOM uint32_t CHACHAHWFLAGS;               /*!< (@ 0x000003B4) This register holds the pre-synthesis HW flag
                                                                    configuration of the CHACHA_SALSA engine                   */

    struct {
      __IOM uint32_t CHACHAEXISTS : 1;          /*!< [0..0] If this flag is set, the Salsa_ChaCha engine include
                                                     ChaCha implementation:                                                    */
      __IOM uint32_t SALSAEXISTS : 1;           /*!< [1..1] If this flag is set, the Salsa_ChaCha engine include
                                                     Salsa implementation:                                                     */
      __IOM uint32_t FASTCHACHA : 1;            /*!< [2..2] If this flag is set, the next matrix calculated when
                                                     the current one is written to data output path (same flag
                                                     for Salsa core):                                                          */
            uint32_t            : 29;
    } CHACHAHWFLAGS_b;
  } ;

  union {
    __IOM uint32_t CHACHABLOCKCNTLSB;           /*!< (@ 0x000003B8) The two first words (n) in the last row of the
                                                                    cipher matrix are the block counter. At
                                                                    the end of each block (512b), the block_cnt
                                                                    for the next block is written by HW to the
                                                                    block_cnt_lsb and block_cnt_msb registers.
                                                                    Need reset block counter , if start new
                                                                    message.                                                   */

    struct {
      __IOM uint32_t CHACHABLOCKCNTLSB : 32;    /*!< [31..0] bits 31:0 of CHACHA_BLOCK_CNT_LSB register.                       */
    } CHACHABLOCKCNTLSB_b;
  } ;

  union {
    __IOM uint32_t CHACHABLOCKCNTMSB;           /*!< (@ 0x000003BC) The two first words (n) in the last row of the
                                                                    cipher matrix are the block counter. At
                                                                    the end of each block (512b), the block_cnt
                                                                    for the next block is written by HW to the
                                                                    block_cnt_lsb and block_cnt_msb registers.
                                                                    Need reset block counter , if start new
                                                                    message.                                                   */

    struct {
      __IOM uint32_t CHACHABLOCKCNTMSB : 32;    /*!< [31..0] bits 31:0 of CHACHA_BLOCK_CNT_MSB register.                       */
    } CHACHABLOCKCNTMSB_b;
  } ;

  union {
    __IOM uint32_t CHACHASWRESET;               /*!< (@ 0x000003C0) Resets CHACHA_SALSA engine.                                */

    struct {
      __IOM uint32_t CHACHSWRESET : 1;          /*!< [0..0] Writing to this address resets the only FSM of CHACHA
                                                     engine. The reset takes 4 CORE_CLK cycles.                                */
            uint32_t            : 31;
    } CHACHASWRESET_b;
  } ;

  union {
    __IOM uint32_t CHACHAFORPOLYKEY0;           /*!< (@ 0x000003C4) bits 255:224 of CHACHA_FOR_POLY_KEY                        */

    struct {
      __IOM uint32_t CHACHAFORPOLYKEY0 : 32;    /*!< [31..0] bits 255:224 of CHACHA_FOR_POLY_KEY                               */
    } CHACHAFORPOLYKEY0_b;
  } ;

  union {
    __IOM uint32_t CHACHAFORPOLYKEY1;           /*!< (@ 0x000003C8) bits 223:192 of CHACHA_FOR_POLY_KEY                        */

    struct {
      __IOM uint32_t CHACHAFORPOLYKEY1 : 32;    /*!< [31..0] bits 223:192 of CHACHA_FOR_POLY_KEY                               */
    } CHACHAFORPOLYKEY1_b;
  } ;

  union {
    __IOM uint32_t CHACHAFORPOLYKEY2;           /*!< (@ 0x000003CC) bits191:160 of CHACHA_FOR_POLY_KEY                         */

    struct {
      __IOM uint32_t CHACHAFORPOLYKEY2 : 32;    /*!< [31..0] bits191:160 of CHACHA_FOR_POLY_KEY                                */
    } CHACHAFORPOLYKEY2_b;
  } ;

  union {
    __IOM uint32_t CHACHAFORPOLYKEY3;           /*!< (@ 0x000003D0) bits159:128 of CHACHA_FOR_POLY_KEY                         */

    struct {
      __IOM uint32_t CHACHAFORPOLYKEY3 : 32;    /*!< [31..0] bits 159:128 of CHACHA_FOR_POLY_KEY                               */
    } CHACHAFORPOLYKEY3_b;
  } ;

  union {
    __IOM uint32_t CHACHAFORPOLYKEY4;           /*!< (@ 0x000003D4) bits 127:96 of CHACHA_FOR_POLY_KEY                         */

    struct {
      __IOM uint32_t CHACHAFORPOLYKEY4 : 32;    /*!< [31..0] bits 127:96 of CHACHA_FOR_POLY_KEY                                */
    } CHACHAFORPOLYKEY4_b;
  } ;

  union {
    __IOM uint32_t CHACHAFORPOLYKEY5;           /*!< (@ 0x000003D8) bits 95:64 of CHACHA_FOR_POLY_KEY                          */

    struct {
      __IOM uint32_t CHACHAFORPOLYKEY5 : 32;    /*!< [31..0] bits 95:64 of CHACHA_FOR_POLY_KEY                                 */
    } CHACHAFORPOLYKEY5_b;
  } ;

  union {
    __IOM uint32_t CHACHAFORPOLYKEY6;           /*!< (@ 0x000003DC) bits 63:32 of CHACHA_FOR_POLY_KEY                          */

    struct {
      __IOM uint32_t CHACHAFORPOLYKEY6 : 32;    /*!< [31..0] bits 63:32 of CHACHA_FOR_POLY_KEY                                 */
    } CHACHAFORPOLYKEY6_b;
  } ;

  union {
    __IOM uint32_t CHACHAFORPOLYKEY7;           /*!< (@ 0x000003E0) bits 31:0 of CHACHA_FOR_POLY_KEY                           */

    struct {
      __IOM uint32_t CHACHAFORPOLYKEY7 : 32;    /*!< [31..0] bits 31:0 of CHACHA_FOR_POLY_KEY                                  */
    } CHACHAFORPOLYKEY7_b;
  } ;

  union {
    __IOM uint32_t CHACHABYTEWORDORDERCNTLREG;  /*!< (@ 0x000003E4) CHACHA_SALSA DATA ORDER configuration.                     */

    struct {
      __IOM uint32_t CHACHADINWORDORDER : 1;    /*!< [0..0] Change the words order of the input data.                          */
      __IOM uint32_t CHACHADINBYTEORDER : 1;    /*!< [1..1] Change the byte order of the input data.                           */
      __IOM uint32_t CHACHACOREMATRIXLBEORDER : 1;/*!< [2..2] Change the quarter of a matrix order in core                     */
      __IOM uint32_t CHACHADOUTWORDORDER : 1;   /*!< [3..3] Change the words order of the output data.                         */
      __IOM uint32_t CHACHADOUTBYTEORDER : 1;   /*!< [4..4] Change the byte order of the output data.                          */
            uint32_t            : 27;
    } CHACHABYTEWORDORDERCNTLREG_b;
  } ;

  union {
    __IOM uint32_t CHACHADEBUGREG;              /*!< (@ 0x000003E8) This register is used to debug the CHACHA engine           */

    struct {
      __IOM uint32_t CHACHADEBUGFSMSTATE : 2;   /*!< [1..0] CHACHA_DEBUG_FSM_STATE                                             */
            uint32_t            : 30;
    } CHACHADEBUGREG_b;
  } ;
  __IM  uint32_t  RESERVED9[5];

  union {
    __IOM uint32_t AESKEY00;                    /*!< (@ 0x00000400) bits 31:0 of AES Key0 (used as the AES key in
                                                                    non-tunneling operations, and as the first
                                                                    tunnel stage key in tunneling operations).                 */

    struct {
      __IOM uint32_t AESKEY00   : 32;           /*!< [31..0] bits 31:0 of AES Key0.                                            */
    } AESKEY00_b;
  } ;

  union {
    __IOM uint32_t AESKEY01;                    /*!< (@ 0x00000404) bits 63:32 of AES Key0 (used as the AES key in
                                                                    non-tunneling operations, and as the first
                                                                    tunnel stage key in tunneling operations).                 */

    struct {
      __IOM uint32_t AESKEY01   : 32;           /*!< [31..0] bits 63:32 of AES Key0.                                           */
    } AESKEY01_b;
  } ;

  union {
    __IOM uint32_t AESKEY02;                    /*!< (@ 0x00000408) bits 95:64 of AES Key0 (used as the AES key in
                                                                    non-tunneling operations, and as the first
                                                                    tunnel stage key in tunneling operations).                 */

    struct {
      __IOM uint32_t AESKEY02   : 32;           /*!< [31..0] bits 95:64 of AES Key0.                                           */
    } AESKEY02_b;
  } ;

  union {
    __IOM uint32_t AESKEY03;                    /*!< (@ 0x0000040C) bits 127:96 of AES Key0 (used as the AES key
                                                                    in non-tunneling operations, and as the
                                                                    first tunnel stage key in tunneling operations).           */

    struct {
      __IOM uint32_t AESKEY03   : 32;           /*!< [31..0] bits 127:96 of AES Key0.                                          */
    } AESKEY03_b;
  } ;

  union {
    __IOM uint32_t AESKEY04;                    /*!< (@ 0x00000410) bits 159:128 of AES Key0 (used as the AES key
                                                                    in non-tunneling operations, and as the
                                                                    first tunnel stage key in tunneling operations).           */

    struct {
      __IOM uint32_t AESKEY04   : 32;           /*!< [31..0] bits 159:128 of AES Key0 .                                        */
    } AESKEY04_b;
  } ;

  union {
    __IOM uint32_t AESKEY05;                    /*!< (@ 0x00000414) bits 191:160 of AES Key0 (used as the AES key
                                                                    in non-tunneling operations, and as the
                                                                    first tunnel stage key in tunneling operations).           */

    struct {
      __IOM uint32_t AESKEY05   : 32;           /*!< [31..0] bits 191:160 of AES Key0.                                         */
    } AESKEY05_b;
  } ;

  union {
    __IOM uint32_t AESKEY06;                    /*!< (@ 0x00000418) bits 223:192 of AES Key0 (used as the AES key
                                                                    in non-tunneling operations, and as the
                                                                    first tunnel stage key in tunneling operations).           */

    struct {
      __IOM uint32_t AESKEY06   : 32;           /*!< [31..0] bits 223:192 of AES Key0.                                         */
    } AESKEY06_b;
  } ;

  union {
    __IOM uint32_t AESKEY07;                    /*!< (@ 0x0000041C) bits 255:224 of AES Key0 (used as the AES key
                                                                    in non-tunneling operations, and as the
                                                                    first tunnel stage key in tunneling operations).           */

    struct {
      __IOM uint32_t AESKEY07   : 32;           /*!< [31..0] bits 255:224 of AES Key0.                                         */
    } AESKEY07_b;
  } ;

  union {
    __IOM uint32_t AESKEY10;                    /*!< (@ 0x00000420) bits 31:0 of AES Key1 (used as the second AES
                                                                    tunnel stage key in tunneling operations).                 */

    struct {
      __IOM uint32_t AESKEY10   : 32;           /*!< [31..0] bits 31:0 of AES Key1.                                            */
    } AESKEY10_b;
  } ;

  union {
    __IOM uint32_t AESKEY11;                    /*!< (@ 0x00000424) bits 63:32 of AES Key1 (used as the second AES
                                                                    tunnel stage key in tunneling operations).                 */

    struct {
      __IOM uint32_t AESKEY11   : 32;           /*!< [31..0] bits 63:32 of AES Key1.                                           */
    } AESKEY11_b;
  } ;

  union {
    __IOM uint32_t AESKEY12;                    /*!< (@ 0x00000428) bits 95:64 of AES Key1 (used as the second AES
                                                                    tunnel stage key in tunneling operations).                 */

    struct {
      __IOM uint32_t AESKEY12   : 32;           /*!< [31..0] bits 95:64 of AES Key1.                                           */
    } AESKEY12_b;
  } ;

  union {
    __IOM uint32_t AESKEY13;                    /*!< (@ 0x0000042C) bits 127:96 of AES Key1 (used as the second AES
                                                                    tunnel stage key in tunneling operations).                 */

    struct {
      __IOM uint32_t AESKEY13   : 32;           /*!< [31..0] bits 127:96 of AES Key1.                                          */
    } AESKEY13_b;
  } ;

  union {
    __IOM uint32_t AESKEY14;                    /*!< (@ 0x00000430) bits 159:128 of AES Key1 (used as the second
                                                                    AES tunnel stage key in tunneling operations).             */

    struct {
      __IOM uint32_t AESKEY14   : 32;           /*!< [31..0] bits 159:128 of AES Key1.                                         */
    } AESKEY14_b;
  } ;

  union {
    __IOM uint32_t AESKEY15;                    /*!< (@ 0x00000434) bits 191:160 of AES Key1 (used as the second
                                                                    AES tunnel stage key in tunneling operations).             */

    struct {
      __IOM uint32_t AESKEY15   : 32;           /*!< [31..0] bits 191:160 of AES Key1.                                         */
    } AESKEY15_b;
  } ;

  union {
    __IOM uint32_t AESKEY16;                    /*!< (@ 0x00000438) bits 223:192 of AES Key1 (used as the second
                                                                    AES tunnel stage key in tunneling operations).             */

    struct {
      __IOM uint32_t AESKEY16   : 32;           /*!< [31..0] bits 223:192 of AES Key1.                                         */
    } AESKEY16_b;
  } ;

  union {
    __IOM uint32_t AESKEY17;                    /*!< (@ 0x0000043C) bits 255:224 of AES Key1 (used as the second
                                                                    AES tunnel stage key in tunneling operations).             */

    struct {
      __IOM uint32_t AESKEY17   : 32;           /*!< [31..0] bits 255:224 of AES Key1.                                         */
    } AESKEY17_b;
  } ;

  union {
    __IOM uint32_t AESIV00;                     /*!< (@ 0x00000440) bits 31:0 of AES_IV0 register. AES IV0 is used
                                                                    as the AES IV (Initialization Value) register
                                                                    in non-tunneling operations,and as the first
                                                                    tunnel stage IV register in tunneling operations.The
                                                                    IV register should be loaded according to
                                                                    the AES mode:in AES CBC_CBC-MAC - the AES
                                                                    IV register should be loaded with the IV
                                                                    (initialization vector).in XTS-AES - the
                                                                    AES IV register should be loaded with the
                                                                    T value (unless the HW T calculation mode
                                                                    is active, in which the T value is calculated
                                                                    by the HW                                                  */

    struct {
      __IOM uint32_t AESIV00    : 32;           /*!< [31..0] bits 31:0 of AES_IV0 register.                                    */
    } AESIV00_b;
  } ;

  union {
    __IOM uint32_t AESIV01;                     /*!< (@ 0x00000444) bits 63:32 of AES_IV0 128b register.For the description
                                                                    of AES_IV0, see the AES_IV_0_0 register
                                                                    description                                                */

    struct {
      __IOM uint32_t AESIV01    : 32;           /*!< [31..0] bits 63:32 of AES_IV0 register.                                   */
    } AESIV01_b;
  } ;

  union {
    __IOM uint32_t AESIV02;                     /*!< (@ 0x00000448) bits 95:64 of AES_IV0 128b register.For the description
                                                                    of AES_IV0, see the AES_IV_0_0 register
                                                                    description                                                */

    struct {
      __IOM uint32_t AESIV02    : 32;           /*!< [31..0] bits 95:64 of AES_IV0 register.                                   */
    } AESIV02_b;
  } ;

  union {
    __IOM uint32_t AESIV03;                     /*!< (@ 0x0000044C) bits 127:96 of AES_IV0 128b register.For the
                                                                    description of AES_IV0, see the AES_IV_0_0
                                                                    register description                                       */

    struct {
      __IOM uint32_t AESIV03    : 32;           /*!< [31..0] bits 127:96 of AES_IV0 register.                                  */
    } AESIV03_b;
  } ;

  union {
    __IOM uint32_t AESIV10;                     /*!< (@ 0x00000450) bits 31:0 of AES_IV1 128b register.AES IV1 is
                                                                    used as the AES IV (Initialization Value)
                                                                    register as the second tunnel stage IV register
                                                                    in tunneling operations.The IV register
                                                                    should be loaded according to the AES mode:in
                                                                    AES CBC_CBC-MAC - the AES IV register should
                                                                    be loaded with the IV (initialization vector).in
                                                                    XTS-AES - the AES IV register should be
                                                                    loaded with the T value (unless the HW T
                                                                    calculation mode is active, in which the
                                                                    T value is calculated by the HW.                           */

    struct {
      __IOM uint32_t AESIV10    : 32;           /*!< [31..0] bits 31:0 of AES_IV1 register.                                    */
    } AESIV10_b;
  } ;

  union {
    __IOM uint32_t AESIV11;                     /*!< (@ 0x00000454) bits 63:32 of AES_IV1 128b register.For the description
                                                                    of AES_IV1, see the AES_IV_1_0 register
                                                                    description                                                */

    struct {
      __IOM uint32_t AESIV11    : 32;           /*!< [31..0] bits 63:32 of AES_IV1 register.                                   */
    } AESIV11_b;
  } ;

  union {
    __IOM uint32_t AESIV12;                     /*!< (@ 0x00000458) bits 95:64 of AES_IV1 128b register.For the description
                                                                    of AES_IV1, see the AES_IV_1_0 register
                                                                    description                                                */

    struct {
      __IOM uint32_t AESIV12    : 32;           /*!< [31..0] bits 95:64 of AES_IV1 register.                                   */
    } AESIV12_b;
  } ;

  union {
    __IOM uint32_t AESIV13;                     /*!< (@ 0x0000045C) bits 127:96 of AES_IV1 128b register.For the
                                                                    description of AES_IV1, see the AES_IV_1_0
                                                                    register description                                       */

    struct {
      __IOM uint32_t AESIV13    : 32;           /*!< [31..0] bits 127:96 of AES_IV1 register.                                  */
    } AESIV13_b;
  } ;

  union {
    __IOM uint32_t AESCTR00;                    /*!< (@ 0x00000460) bits 31:0 of AES_CTR0 128b register.AES CTR0
                                                                    is used as the AES CTR (counter) register
                                                                    in non-tunneling operations, and as the
                                                                    first tunnel stage CTR register in tunneling
                                                                    operations.The CTR register should be loaded
                                                                    according to the AES mode:in AES CTR_GCTR
                                                                    - the AES CTR register should be loaded
                                                                    with the counter value.in XTS-AES - the
                                                                    AES CTR register should be loaded with the
                                                                    i value (in order to calculate the T value
                                                                    from it, if HW T calculation is supported).                */

    struct {
      __IOM uint32_t AESCTR00   : 32;           /*!< [31..0] bits 31:0 of AES_CTR0 register.                                   */
    } AESCTR00_b;
  } ;

  union {
    __IOM uint32_t AESCTR01;                    /*!< (@ 0x00000464) bits 63:32 of AES_CTR0 128b register.For the
                                                                    description of AES_CTR0, see the AES_CTR_0_0
                                                                    register description.                                      */

    struct {
      __IOM uint32_t AESCTR01   : 32;           /*!< [31..0] bits 63:32 of AES_CTR0 register.                                  */
    } AESCTR01_b;
  } ;

  union {
    __IOM uint32_t AESCTR02;                    /*!< (@ 0x00000468) bits 95:64 of AES_CTR0 128b register.For the
                                                                    description of AES_CTR0, see the AES_CTR_0_0
                                                                    register description.                                      */

    struct {
      __IOM uint32_t AESCTR02   : 32;           /*!< [31..0] bits 95:64 of AES_CTR0 register.                                  */
    } AESCTR02_b;
  } ;

  union {
    __IOM uint32_t AESCTR03;                    /*!< (@ 0x0000046C) bits 127:96 of AES_CTR0 128b register.For the
                                                                    description of AES_CTR0, see the AES_CTR_0_0
                                                                    register description.                                      */

    struct {
      __IOM uint32_t AESCTR03   : 32;           /*!< [31..0] bits 127:96 of AES_CTR0 register.                                 */
    } AESCTR03_b;
  } ;

  union {
    __IOM uint32_t AESBUSY;                     /*!< (@ 0x00000470) This register is set when the AES core is active           */

    struct {
      __IOM uint32_t AESBUSY    : 1;            /*!< [0..0] AES_BUSY register. This register is set when the AES
                                                     core is active                                                            */
            uint32_t            : 31;
    } AESBUSY_b;
  } ;
  __IM  uint32_t  RESERVED10;

  union {
    __IOM uint32_t AESSK;                       /*!< (@ 0x00000478) writing to this address causes sampling of the
                                                                    HW key to the AES_KEY0 register                            */

    struct {
      __IOM uint32_t AESSK      : 1;            /*!< [0..0] writing to this address causes sampling of the HW key
                                                     to the AES_KEY0 register                                                  */
            uint32_t            : 31;
    } AESSK_b;
  } ;

  union {
    __IOM uint32_t AESCMACINIT;                 /*!< (@ 0x0000047C) Writing to this address triggers the AES engine
                                                                    generating of K1 and K2 for AES CMAC operations.
                                                                    Note: This is a special register, affected
                                                                    by internal logic. Test result of this register
                                                                    is NA.                                                     */

    struct {
      __IOM uint32_t AESCMACINIT : 1;           /*!< [0..0] Writing to this address starts the generating of K1 and
                                                     K2 for AES CMAC operations                                                */
            uint32_t            : 31;
    } AESCMACINIT_b;
  } ;
  __IM  uint32_t  RESERVED11[13];

  union {
    __IOM uint32_t AESSK1;                      /*!< (@ 0x000004B4) writing to this address causes sampling of the
                                                                    HW key to the AES_KEY1 register                            */

    struct {
      __IOM uint32_t AESSK1     : 1;            /*!< [0..0] writing to this address causes sampling of the HW key
                                                     to the AES_KEY1 register                                                  */
            uint32_t            : 31;
    } AESSK1_b;
  } ;
  __IM  uint32_t  RESERVED12;

  union {
    __IOM uint32_t AESREMAININGBYTES;           /*!< (@ 0x000004BC) This register should be set with the amount of
                                                                    remaining bytes until the end of the current
                                                                    AES operation. The AES engine counts down
                                                                    from this value to determine the last _
                                                                    one before last blocks in AES CMAC, XTS
                                                                    AES and AES CCM.                                           */

    struct {
      __IOM uint32_t AESREMAININGBYTES : 32;    /*!< [31..0] This register should be set with the amount of remaining
                                                     bytes until the end of the current AES operation. The AES
                                                     engine counts down from this value to determine the last
                                                     _ one before last blocks in AES CMAC, XTS AES and AES CCM.                */
    } AESREMAININGBYTES_b;
  } ;

  union {
    __IOM uint32_t AESCONTROL;                  /*!< (@ 0x000004C0) This register holds the configuration of the
                                                                    AES engine. Note: This is a special register,
                                                                    affected by internal logic. Test result
                                                                    of this register is NA.                                    */

    struct {
      __IOM uint32_t DECKEY0    : 1;            /*!< [0..0] This field determines whether the AES performs Decrypt_Encrypt
                                                     operations, in non-tunneling operations:                                  */
      __IOM uint32_t MODE0ISCBCCTS : 1;         /*!< [1..1] If MODE_KEY0 is set to 3b001 (CBC), and this field is
                                                     set - the mode is CBC-CTS. In addition, If MODE_KEY0 is
                                                     set to 3b010 (CTR), and this field is set - the mode is
                                                     GCTR.                                                                     */
      __IOM uint32_t MODEKEY0   : 3;            /*!< [4..2] This field determines the AES mode in non tunneling operations,
                                                     and the AES mode of the first stage in tunneling operations:              */
      __IOM uint32_t MODEKEY1   : 3;            /*!< [7..5] This field determines the AES mode of the second stage
                                                     operation in tunneling operations:                                        */
      __IOM uint32_t CBCISESSIV : 1;            /*!< [8..8] If MODE_KEY0 is set to 3b001 (CBC), and this field is
                                                     set - the mode is CBC with ESSIV.                                         */
            uint32_t            : 1;
      __IOM uint32_t AESTUNNELISON : 1;         /*!< [10..10] This field determines whether the AES performs dual-tunnel
                                                     operations or standard non-tunneling operations:                          */
      __IOM uint32_t CBCISBITLOCKER : 1;        /*!< [11..11] If MODE_KEY0 is set to 3b001 (CBC), and this field
                                                     is set - the mode isBITLOCKER.                                            */
      __IOM uint32_t NKKEY0     : 2;            /*!< [13..12] This field determines the AES Key length in non tunneling
                                                     operations, and the AES key length of the first stage in
                                                     tunneling operations:                                                     */
      __IOM uint32_t NKKEY1     : 2;            /*!< [15..14] This field determines the AES key length of the second
                                                     stage operation in tunneling operations:                                  */
            uint32_t            : 6;
      __IOM uint32_t AESTUNNEL1DECRYPT : 1;     /*!< [22..22] This field determines whether the second tunnel stage
                                                     performs encrypt or decrypt operation :                                   */
      __IOM uint32_t AESTUNB1USESPADDEDDATAIN : 1;/*!< [23..23] This field determines, for tunneling operations, the
                                                     data that is fed to the second tunneling stage:                           */
      __IOM uint32_t AESTUNNEL0ENCRYPT : 1;     /*!< [24..24] This field determines whether the first tunnel stage
                                                     performs encrypt or decrypt operation :                                   */
      __IOM uint32_t AESOUTPUTMIDTUNNELDATA : 1;/*!< [25..25] This fields determines whether the AES output is the
                                                     result of the first or second tunneling stage:                            */
      __IOM uint32_t AESTUNNELB1PADEN : 1;      /*!< [26..26] This field determines whether the input data to the
                                                     second tunnel stage is padded with zeroes (according to
                                                     the remaining_bytes value) or not:                                        */
            uint32_t            : 1;
      __IOM uint32_t AESOUTMIDTUNTOHASH : 1;    /*!< [28..28] This field determines for AES-TO-HASH-AND-DOUT tunneling
                                                     operations, whether the AES outputs to the HASH the result
                                                     of the first or the second tunneling stage:                               */
      __IOM uint32_t AESXORCRYPTOKEY : 1;       /*!< [29..29] This field determines the value that is written to
                                                     AES_KEY0, when AES_SK is kicked:                                          */
            uint32_t            : 1;
      __IOM uint32_t DIRECTACCESS : 1;          /*!< [31..31] Using direct access and not the din-dout interface               */
    } AESCONTROL_b;
  } ;
  __IM  uint32_t  RESERVED13;

  union {
    __IOM uint32_t AESHWFLAGS;                  /*!< (@ 0x000004C8) This register holds the pre-synthesis HW flag
                                                                    configuration of the AES engine                            */

    struct {
      __IOM uint32_t SUPPORT256192KEY : 1;      /*!< [0..0] the SUPPORT_256_192_KEY flag                                       */
      __IOM uint32_t AESLARGERKEK : 1;          /*!< [1..1] the AES_LARGE_RKEK flag                                            */
      __IOM uint32_t DPACNTRMSREXIST : 1;       /*!< [2..2] the DPA_CNTRMSR_EXIST flag                                         */
      __IOM uint32_t CTREXIST   : 1;            /*!< [3..3] the CTR_EXIST flag                                                 */
      __IOM uint32_t ONLYENCRYPT : 1;           /*!< [4..4] the ONLY_ENCRYPT flag                                              */
      __IOM uint32_t USESBOXTABLE : 1;          /*!< [5..5] the USE_SBOX_TABLE flag                                            */
            uint32_t            : 2;
      __IOM uint32_t USE5SBOXES : 1;            /*!< [8..8] the USE_5_SBOXES flag                                              */
      __IOM uint32_t AESSUPPORTPREVIV : 1;      /*!< [9..9] the AES_SUPPORT_PREV_IV flag                                       */
      __IOM uint32_t aestunnelexists : 1;       /*!< [10..10] the aes_tunnel_exists flag                                       */
      __IOM uint32_t SECONDREGSSETEXIST : 1;    /*!< [11..11] the SECOND_REGS_SET_EXIST flag                                   */
      __IOM uint32_t DFACNTRMSREXIST : 1;       /*!< [12..12] the DFA_CNTRMSR_EXIST flag                                       */
            uint32_t            : 19;
    } AESHWFLAGS_b;
  } ;
  __IM  uint32_t  RESERVED14[3];

  union {
    __IOM uint32_t AESCTRNOINCREMENT;           /*!< (@ 0x000004D8) This register enables the AES CTR no increment
                                                                    mode (in which the counter mode is not incremented
                                                                    between 2 blocks)                                          */

    struct {
      __IOM uint32_t AESCTRNOINCREMENT : 1;     /*!< [0..0] This field enables the AES CTR 'no increment' mode (in
                                                     which the counter mode is not incremented between 2 blocks)               */
            uint32_t            : 31;
    } AESCTRNOINCREMENT_b;
  } ;
  __IM  uint32_t  RESERVED15[5];

  union {
    __IOM uint32_t AESDFAISON;                  /*!< (@ 0x000004F0) This register disable_enable the AES dfa. Note:
                                                                    This is a special register, affected by
                                                                    internal logic. Test result of this register
                                                                    is NA.                                                     */

    struct {
      __IOM uint32_t AESDFAISON : 1;            /*!< [0..0] writing to this register turns the DFA counter-measures
                                                     on. this register exists only if DFA countermeasures are
                                                     supported                                                                 */
            uint32_t            : 31;
    } AESDFAISON_b;
  } ;
  __IM  uint32_t  RESERVED16;

  union {
    __IOM uint32_t AESDFAERRSTATUS;             /*!< (@ 0x000004F8) dfa error status register.                                 */

    struct {
      __IOM uint32_t AESDFAERRSTATUS : 1;       /*!< [0..0] after a DFA violation this register is set and the AES
                                                     block is disabled) until the next reset. this register
                                                     only exists if DFA countermeasures is are supported                       */
            uint32_t            : 31;
    } AESDFAERRSTATUS_b;
  } ;
  __IM  uint32_t  RESERVED17[10];

  union {
    __IOM uint32_t AESCMACSIZE0KICK;            /*!< (@ 0x00000524) writing to this address triggers the AES engine
                                                                    to perform a CMAC operation with size 0.
                                                                    The CMAC result can be read from the AES_IV0
                                                                    register.                                                  */

    struct {
      __IOM uint32_t AESCMACSIZE0KICK : 1;      /*!< [0..0] writing to this address triggers the AES engine to perform
                                                     a CMAC operation with size 0. The CMAC result can be read
                                                     from the AES_IV0 register.                                                */
            uint32_t            : 31;
    } AESCMACSIZE0KICK_b;
  } ;
  __IM  uint32_t  RESERVED18[70];

  union {
    __IOM uint32_t HASHH0;                      /*!< (@ 0x00000640) H0 data. can only be written in the following
                                                                    HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256
                                                                    SHA384 SHA512                                              */

    struct {
      __IOM uint32_t HASHH0     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
    } HASHH0_b;
  } ;

  union {
    __IOM uint32_t HASHH1;                      /*!< (@ 0x00000644) H1 data. can only be written in the following
                                                                    HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256
                                                                    SHA384 SHA512                                              */

    struct {
      __IOM uint32_t HASHH1     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
    } HASHH1_b;
  } ;

  union {
    __IOM uint32_t HASHH2;                      /*!< (@ 0x00000648) H2 data. can only be written in the following
                                                                    HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256
                                                                    SHA384 SHA512                                              */

    struct {
      __IOM uint32_t HASHH2     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
    } HASHH2_b;
  } ;

  union {
    __IOM uint32_t HASHH3;                      /*!< (@ 0x0000064C) H3 data. can only be written in the following
                                                                    HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256
                                                                    SHA384 SHA512                                              */

    struct {
      __IOM uint32_t HASHH3     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
    } HASHH3_b;
  } ;

  union {
    __IOM uint32_t HASHH4;                      /*!< (@ 0x00000650) H4 data. can only be written in the following
                                                                    HASH_CONTROL modes: SHA1 SHA224 SHA256 SHA384
                                                                    SHA512                                                     */

    struct {
      __IOM uint32_t HASHH4     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
    } HASHH4_b;
  } ;

  union {
    __IOM uint32_t HASHH5;                      /*!< (@ 0x00000654) H5 data. can only be written in the following
                                                                    HASH_CONTROL modes: SHA224 SHA256 SHA384
                                                                    SHA512                                                     */

    struct {
      __IOM uint32_t HASHH5     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
    } HASHH5_b;
  } ;

  union {
    __IOM uint32_t HASHH6;                      /*!< (@ 0x00000658) H6 data. can only be written in the following
                                                                    HASH_CONTROL modes: SHA224 SHA256 SHA384
                                                                    SHA512                                                     */

    struct {
      __IOM uint32_t HASHH6     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
    } HASHH6_b;
  } ;

  union {
    __IOM uint32_t HASHH7;                      /*!< (@ 0x0000065C) H7 data. can only be written in the following
                                                                    HASH_CONTROL modes: SHA224 SHA256 SHA384
                                                                    SHA512                                                     */

    struct {
      __IOM uint32_t HASHH7     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
    } HASHH7_b;
  } ;

  union {
    __IOM uint32_t HASHH8;                      /*!< (@ 0x00000660) H8 data. can only be written in the following
                                                                    HASH_CONTROL modes: SHA384 SHA512                          */

    struct {
      __IOM uint32_t HASHH8     : 32;           /*!< [31..0] 1) Write initial Hash value.                                      */
    } HASHH8_b;
  } ;
  __IM  uint32_t  RESERVED19[8];

  union {
    __IOM uint32_t AUTOHWPADDING;               /*!< (@ 0x00000684) HW padding automatically activated by engine.
                                                                    For the special case of ZERO bytes data
                                                                    vector this register should not be used!
                                                                    instead use HASH_PAD_CFG                                   */

    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] 0x1 - Enable Automatic HW padding (No need for SW intervention
                                                     by writing PAD_CFG). Note: Not supported for 0 bytes !
                                                     Note: Disable this register when HASH op is done                          */
            uint32_t            : 31;
    } AUTOHWPADDING_b;
  } ;

  union {
    __IOM uint32_t HASHXORDIN;                  /*!< (@ 0x00000688) This register is always xored with the input
                                                                    to the hash engine,it should be 0 if xored
                                                                    is not reqiured .                                          */

    struct {
      __IOM uint32_t HASHXORDATA : 32;          /*!< [31..0] This register holds the value to be xor-ed with hash
                                                     input data.                                                               */
    } HASHXORDIN_b;
  } ;
  __IM  uint32_t  RESERVED20[2];

  union {
    __IOM uint32_t LOADINITSTATE;               /*!< (@ 0x00000694) Indication to HASH that the following data is
                                                                    to be loaded into initial value registers
                                                                    in HASH(H0:H15) or IV to AES MAC                           */

    struct {
      __IOM uint32_t LOAD       : 1;            /*!< [0..0] Load data to initial state registers. digest_iv for hash_aes_mac.
                                                     When done loading data this bit should be reset                           */
            uint32_t            : 31;
    } LOADINITSTATE_b;
  } ;
  __IM  uint32_t  RESERVED21[3];

  union {
    __IOM uint32_t HASHSELAESMAC;               /*!< (@ 0x000006A4) select the AES MAC module rather than the hash
                                                                    module                                                     */

    struct {
      __IOM uint32_t HASHSELAESMAC : 1;         /*!< [0..0] Hash or AES MAC module select.                                     */
      __IOM uint32_t GHASHSEL   : 1;            /*!< [1..1] GHASH select.                                                      */
            uint32_t            : 30;
    } HASHSELAESMAC_b;
  } ;
  __IM  uint32_t  RESERVED22[66];

  union {
    __IOM uint32_t HASHVERSION;                 /*!< (@ 0x000007B0) HASH VERSION Register                                      */

    struct {
      __IOM uint32_t FIXES      : 8;            /*!< [7..0] Fixes field.                                                       */
      __IOM uint32_t MINORVERSIONNUMBER : 4;    /*!< [11..8] minor version number                                              */
      __IOM uint32_t MAJORVERSIONNUMBER : 4;    /*!< [15..12] major version number                                             */
            uint32_t            : 16;
    } HASHVERSION_b;
  } ;
  __IM  uint32_t  RESERVED23[3];

  union {
    __IOM uint32_t HASHCONTROL;                 /*!< (@ 0x000007C0) Selects which HASH mode to run                             */

    struct {
      __IOM uint32_t MODE01     : 2;            /*!< [1..0] bits 1:0 of the HASH mode field. The hash mode field
                                                     possible values are:                                                      */
            uint32_t            : 1;
      __IOM uint32_t MODE3      : 1;            /*!< [3..3] bit 3 of the HASH mode field. The hash mode field possible
                                                     values are:4b0000 - MD5 if present 0x0001 SHA 1 4b0010
                                                     - SHA-256 4b1010 - SHA-224                                                */
            uint32_t            : 28;
    } HASHCONTROL_b;
  } ;

  union {
    __IOM uint32_t HASHPADEN;                   /*!< (@ 0x000007C4) Enables the hash hw padding.                               */

    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] 0x1 : Enable generation of padding by HW Pad block. 0x0
                                                     : Disable generation of padding by HW Pad block.                          */
            uint32_t            : 31;
    } HASHPADEN_b;
  } ;

  union {
    __IOM uint32_t HASHPADCFG;                  /*!< (@ 0x000007C8) This is a special register, affected by internal
                                                                    logic. Test result of this register is NA.                 */

    struct {
            uint32_t            : 2;
      __IOM uint32_t DOPAD      : 1;            /*!< [2..2] Enable Padding generation. must be reset upon completion
                                                     of padding.                                                               */
            uint32_t            : 29;
    } HASHPADCFG_b;
  } ;

  union {
    __IOM uint32_t HASHCURLEN0;                 /*!< (@ 0x000007CC) This register holds the length of current hash
                                                                    operation bit 31:0.                                        */

    struct {
      __IOM uint32_t Length     : 32;           /*!< [31..0] Represent the current length of valid bits where digest
                                                     need to be computed In Bytes.                                             */
    } HASHCURLEN0_b;
  } ;

  union {
    __IOM uint32_t HASHCURLEN1;                 /*!< (@ 0x000007D0) This register holds the length of current hash
                                                                    operation bit 63:32.                                       */

    struct {
      __IOM uint32_t Length     : 32;           /*!< [31..0] Represent the current length of valid bits where digest
                                                     need to be computed In Bytes.                                             */
    } HASHCURLEN1_b;
  } ;
  __IM  uint32_t  RESERVED24[2];

  union {
    __IOM uint32_t HASHPARAM;                   /*!< (@ 0x000007DC) HASH_PARAM Register.                                       */

    struct {
      __IOM uint32_t CW         : 4;            /*!< [3..0] Indicates the number of concurrent words the hash is
                                                     using to compute signature. 1 - One concurrent w(t). 2
                                                     - Two concurrent w(t).                                                    */
      __IOM uint32_t CH         : 4;            /*!< [7..4] Indicate if Hi adders are present for each Hi value or
                                                     1 adder is shared for all Hi. 0 - One Hi value is updated
                                                     at a time 1 - All Hi values are updated at the same time.                 */
      __IOM uint32_t DW         : 4;            /*!< [11..8] Determine the granularity of word size. 0 - 32 bit word
                                                     data. 1 - 64 bit word data.                                               */
      __IOM uint32_t SHA512EXISTS : 1;          /*!< [12..12] Indicate if SHA-512 is present in the design. By default
                                                     SHA-1 and SHA-256 are present. 0 - SHA-1 and SHA-256 are
                                                     present only 1 - SHA-1 and all SHA-2 are present (SHA-256
                                                     SHA-512).                                                                 */
      __IOM uint32_t PADEXISTS  : 1;            /*!< [13..13] Indicate if pad block is present in the design. 0 -
                                                     pad function is not supported by hardware. 1 - pad function
                                                     is supported by hardware.                                                 */
      __IOM uint32_t MD5EXISTS  : 1;            /*!< [14..14] Indicate if MD5 is present in HW                                 */
      __IOM uint32_t HMACEXISTS : 1;            /*!< [15..15] Indicate if HMAC logic is present in the design                  */
      __IOM uint32_t SHA256EXISTS : 1;          /*!< [16..16] Indicate if SHA-256 is present in the design                     */
      __IOM uint32_t HASHCOMPAREEXISTS : 1;     /*!< [17..17] Indicate if COMPARE digest logic is present in the
                                                     design                                                                    */
      __IOM uint32_t DUMPHASHTODOUTEXISTS : 1;  /*!< [18..18] Indicate if HASH to dout is present in the design                */
            uint32_t            : 13;
    } HASHPARAM_b;
  } ;
  __IM  uint32_t  RESERVED25;

  union {
    __IOM uint32_t HASHAESSWRESET;              /*!< (@ 0x000007E4) Software reset of the AES.                                 */

    struct {
      __IOM uint32_t HASHAESSWRESET : 1;        /*!< [0..0] Hash receive reset internally.                                     */
            uint32_t            : 31;
    } HASHAESSWRESET_b;
  } ;

  union {
    __IOM uint32_t HASHENDIANESS;               /*!< (@ 0x000007E8) This register holds the HASH_ENDIANESS configuration.      */

    struct {
      __IOM uint32_t ENDIAN     : 1;            /*!< [0..0] The default value is little-endian. The data and generation
                                                     of padding can be swapped to be big-endian.                               */
            uint32_t            : 31;
    } HASHENDIANESS_b;
  } ;
  __IM  uint32_t  RESERVED26[9];

  union {
    __IOM uint32_t AESCLKENABLE;                /*!< (@ 0x00000810) This is a special register, affected by internal
                                                                    logic. Test result of this register is NA.                 */

    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Enable the AES clock.                                              */
            uint32_t            : 31;
    } AESCLKENABLE_b;
  } ;
  __IM  uint32_t  RESERVED27;

  union {
    __IOM uint32_t HASHCLKENABLE;               /*!< (@ 0x00000818) The HASH clock enable register. Note: This is
                                                                    a special register, affected by internal
                                                                    logic. Test result of this register is NA.                 */

    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Enable the hash clock.                                             */
            uint32_t            : 31;
    } HASHCLKENABLE_b;
  } ;

  union {
    __IOM uint32_t PKACLKENABLE;                /*!< (@ 0x0000081C) The PKA clock enable register. Note: This is
                                                                    a special register, affected by internal
                                                                    logic. Test result of this register is NA.                 */

    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Enable the PKA clock.                                              */
            uint32_t            : 31;
    } PKACLKENABLE_b;
  } ;

  union {
    __IOM uint32_t DMACLKENABLE;                /*!< (@ 0x00000820) DMA_CLK enable register. Note: This is a special
                                                                    register, affected by internal logic. Test
                                                                    result of this register is NA.                             */

    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Enable the DMA clock.                                              */
            uint32_t            : 31;
    } DMACLKENABLE_b;
  } ;

  union {
    __IOM uint32_t CLKSTATUS;                   /*!< (@ 0x00000824) The CryptoCell clocks status register. Note:
                                                                    This is a special register, affected by
                                                                    internal logic. Test result of this register
                                                                    is NA.                                                     */

    struct {
      __IOM uint32_t AESCLKSTATUS : 1;          /*!< [0..0] Status of AES clock enable.                                        */
            uint32_t            : 1;
      __IOM uint32_t HASHCLKSTATUS : 1;         /*!< [2..2] Status of HASH clock clock enable.                                 */
      __IOM uint32_t PKACLKSTATUS : 1;          /*!< [3..3] Status of PKA clock enable.                                        */
            uint32_t            : 3;
      __IOM uint32_t CHACHACLKSTATUS : 1;       /*!< [7..7] Status of CHACHA clock enable.                                     */
      __IOM uint32_t DMACLKSTATUS : 1;          /*!< [8..8] Status of DMA clock enable.                                        */
            uint32_t            : 23;
    } CLKSTATUS_b;
  } ;
  __IM  uint32_t  RESERVED28[12];

  union {
    __IOM uint32_t CHACHACLKENABLE;             /*!< (@ 0x00000858) CHACHA _SALSA clock enable register. Note: This
                                                                    is a special register, affected by internal
                                                                    logic. Test result of this register is NA.                 */

    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] Enable the CHACHA SALSA clock enable.                              */
            uint32_t            : 31;
    } CHACHACLKENABLE_b;
  } ;
  __IM  uint32_t  RESERVED29[41];

  union {
    __IOM uint32_t CRYPTOCTL;                   /*!< (@ 0x00000900) Defines the cryptographic flow.                            */

    struct {
      __IOM uint32_t MODE       : 5;            /*!< [4..0] Determines the active cryptographic engine:                        */
            uint32_t            : 27;
    } CRYPTOCTL_b;
  } ;
  __IM  uint32_t  RESERVED30[3];

  union {
    __IOM uint32_t CRYPTOBUSY;                  /*!< (@ 0x00000910) This register is set when the cryptographic core
                                                                    is busy.                                                   */

    struct {
      __IOM uint32_t CRYPTOBUSY : 1;            /*!< [0..0] Crypto busy status.                                                */
            uint32_t            : 31;
    } CRYPTOBUSY_b;
  } ;
  __IM  uint32_t  RESERVED31[2];

  union {
    __IOM uint32_t HASHBUSY;                    /*!< (@ 0x0000091C) This register is set when the Hash engine is
                                                                    busy.                                                      */

    struct {
      __IOM uint32_t HASHBUSY   : 1;            /*!< [0..0] Hash busy status.                                                  */
            uint32_t            : 31;
    } HASHBUSY_b;
  } ;
  __IM  uint32_t  RESERVED32[4];

  union {
    __IOM uint32_t CONTEXTID;                   /*!< (@ 0x00000930) A general RD_WR register. For Firmware use.                */

    struct {
      __IOM uint32_t CONTEXTID  : 8;            /*!< [7..0] Context ID                                                         */
            uint32_t            : 24;
    } CONTEXTID_b;
  } ;
  __IM  uint32_t  RESERVED33[11];

  union {
    __IOM uint32_t GHASHSUBKEY00;               /*!< (@ 0x00000960) Bits 31:0 of GHASH Key0 (used as the GHASH module
                                                                    key).                                                      */

    struct {
      __IOM uint32_t GHASHSUBKEY00 : 32;        /*!< [31..0] Bits 31:0 of GHASH Key0.                                          */
    } GHASHSUBKEY00_b;
  } ;

  union {
    __IOM uint32_t GHASHSUBKEY01;               /*!< (@ 0x00000964) Bits 63:32 of GHASH Key0 (used as the GHASH module
                                                                    key).                                                      */

    struct {
      __IOM uint32_t GHASHSUBKEY01 : 32;        /*!< [31..0] Bits 63:32 of GHASH Key0.                                         */
    } GHASHSUBKEY01_b;
  } ;

  union {
    __IOM uint32_t GHASHSUBKEY02;               /*!< (@ 0x00000968) Bits 95:64 of GHASH Key0 (used as the GHASH module
                                                                    key).                                                      */

    struct {
      __IOM uint32_t GHASHSUBKEY02 : 32;        /*!< [31..0] Bits 95:64 of GHASH Key0.                                         */
    } GHASHSUBKEY02_b;
  } ;

  union {
    __IOM uint32_t GHASHSUBKEY03;               /*!< (@ 0x0000096C) Bits 127:96 of GHASH Key0 (used as the GHASH
                                                                    module key).                                               */

    struct {
      __IOM uint32_t GHASHSUBKEY03 : 32;        /*!< [31..0] Bits 127:96 of GHASH Key0.                                        */
    } GHASHSUBKEY03_b;
  } ;

  union {
    __IOM uint32_t GHASHIV00;                   /*!< (@ 0x00000970) Bits 31:0 of GHASH_IV0 register. GHASH IV0 is
                                                                    used as the GHASH IV (Initialization Value)
                                                                    register.                                                  */

    struct {
      __IOM uint32_t GHASHIV00  : 32;           /*!< [31..0] Bits 31:0 of GHASH_IV0 register of the GHASH module.
                                                     For the description of GHASH_IV0, see the GHASH_0_0 register
                                                     description                                                               */
    } GHASHIV00_b;
  } ;

  union {
    __IOM uint32_t GHASHIV01;                   /*!< (@ 0x00000974) Bits 63:32 of GHASH_IV0 register. GHASH IV0 is
                                                                    used as the GHASH IV (Initialization Value)
                                                                    register.                                                  */

    struct {
      __IOM uint32_t GHASHIV01  : 32;           /*!< [31..0] Bits 63:32 of GHASH_IV0 register of the GHASH module.             */
    } GHASHIV01_b;
  } ;

  union {
    __IOM uint32_t GHASHIV02;                   /*!< (@ 0x00000978) Bits 95:64 of GHASH_IV0 register. GHASH IV0 is
                                                                    used as the GHASH IV (Initialization Value)
                                                                    register.                                                  */

    struct {
      __IOM uint32_t GHASHIV02  : 32;           /*!< [31..0] Bits 95:64 of GHASH_IV0 register of the GHASH module.             */
    } GHASHIV02_b;
  } ;

  union {
    __IOM uint32_t GHASHIV03;                   /*!< (@ 0x0000097C) Bits 127:96 of GHASH_IV0 register.GHASH IV0 is
                                                                    used as the GHASH IV (Initialization Value)
                                                                    register.                                                  */

    struct {
      __IOM uint32_t GHASHIV03  : 32;           /*!< [31..0] Bits 127:96 of GHASH_IV0 register of the GHASH module.            */
    } GHASHIV03_b;
  } ;

  union {
    __IOM uint32_t GHASHBUSY;                   /*!< (@ 0x00000980) The GHASH module GHASH_BUSY Register. This register
                                                                    is set when the GHASH core is active.                      */

    struct {
      __IOM uint32_t GHASHBUSY  : 1;            /*!< [0..0] GHASH_BUSY Register. This register is set when the GHASH
                                                     core is active                                                            */
            uint32_t            : 31;
    } GHASHBUSY_b;
  } ;

  union {
    __IOM uint32_t GHASHINIT;                   /*!< (@ 0x00000984) Writing to this address sets the GHASH engine
                                                                    to be ready to a new GHASH operation.                      */

    struct {
      __IOM uint32_t GHASHINIT  : 1;            /*!< [0..0] Writing to this address sets the GHASH engine to be ready
                                                     to a new GHASH operation.                                                 */
            uint32_t            : 31;
    } GHASHINIT_b;
  } ;
  __IM  uint32_t  RESERVED34[30];

  union {
    __IOM uint32_t HOSTRGFIRR;                  /*!< (@ 0x00000A00) The Interrupt Request register. Each bit of this
                                                                    register holds the interrupt status of a
                                                                    single interrupt source.                                   */

    struct {
            uint32_t            : 4;
      __IOM uint32_t SRAMTODININT : 1;          /*!< [4..4] The SRAM to DIN DMA done interrupt status. This interrupt
                                                     is asserted when all data was delivered to DIN buffer from
                                                     SRAM.                                                                     */
      __IOM uint32_t DOUTTOSRAMINT : 1;         /*!< [5..5] The DOUT to SRAM DMA done interrupt status. This interrupt
                                                     is asserted when all data was delivered to SRAM buffer
                                                     from DOUT.                                                                */
      __IOM uint32_t MEMTODININT : 1;           /*!< [6..6] The memory to DIN DMA done interrupt status. This interrupt
                                                     is asserted when all data was delivered to DIN buffer from
                                                     memory.                                                                   */
      __IOM uint32_t DOUTTOMEMINT : 1;          /*!< [7..7] The DOUT to memory DMA done interrupt status. This interrupt
                                                     is asserted when all data was delivered to memory buffer
                                                     from DOUT.                                                                */
      __IOM uint32_t AHBERRINT  : 1;            /*!< [8..8] The AXI error interrupt status.                                    */
      __IOM uint32_t PKAEXPINT  : 1;            /*!< [9..9] The PKA end of operation interrupt status.                         */
      __IOM uint32_t RNGINT     : 1;            /*!< [10..10] The RNG interrupt status.                                        */
      __IOM uint32_t SYMDMACOMPLETED : 1;       /*!< [11..11] The GPR interrupt status.                                        */
            uint32_t            : 20;
    } HOSTRGFIRR_b;
  } ;

  union {
    __IOM uint32_t HOSTRGFIMR;                  /*!< (@ 0x00000A04) The Interrupt Mask register. Each bit of this
                                                                    register holds the mask of a single interrupt
                                                                    source.                                                    */

    struct {
            uint32_t            : 4;
      __IOM uint32_t SRAMTODINMASK : 1;         /*!< [4..4] The SRAM to DIN DMA done interrupt mask.                           */
      __IOM uint32_t DOUTTOSRAMMASK : 1;        /*!< [5..5] The DOUT to SRAM DMA done interrupt mask.                          */
      __IOM uint32_t MEMTODINMASK : 1;          /*!< [6..6] The memory to DIN DMA done interrupt mask.                         */
      __IOM uint32_t DOUTTOMEMMASK : 1;         /*!< [7..7] The DOUT to memory DMA done interrupt mask.                        */
      __IOM uint32_t AXIERRMASK : 1;            /*!< [8..8] The AXI error interrupt mask.                                      */
      __IOM uint32_t PKAEXPMASK : 1;            /*!< [9..9] The PKA end of operation interrupt mask.                           */
      __IOM uint32_t RNGINTMASK : 1;            /*!< [10..10] The RNG interrupt mask.                                          */
      __IOM uint32_t SYMDMACOMPLETEDMASK : 1;   /*!< [11..11] The GPR interrupt mask.                                          */
            uint32_t            : 20;
    } HOSTRGFIMR_b;
  } ;

  union {
    __IOM uint32_t HOSTRGFICR;                  /*!< (@ 0x00000A08) Interrupt Clear Register.                                  */

    struct {
            uint32_t            : 4;
      __IOM uint32_t SRAMTODINCLEAR : 1;        /*!< [4..4] The SRAM to DIN DMA done interrupt clear.                          */
      __IOM uint32_t DOUTTOSRAMCLEAR : 1;       /*!< [5..5] The DOUT to SRAM DMA done interrupt clear.                         */
      __IOM uint32_t MEMTODINCLEAR : 1;         /*!< [6..6] The memory to DIN DMA done interrupt clear.                        */
      __IOM uint32_t DOUTTOMEMCLEAR : 1;        /*!< [7..7] The DOUT to memory DMA done interrupt clear.                       */
      __IOM uint32_t AXIERRCLEAR : 1;           /*!< [8..8] The AXI error interrupt clear.                                     */
      __IOM uint32_t PKAEXPCLEAR : 1;           /*!< [9..9] The PKA end of operation interrupt clear.                          */
      __IOM uint32_t RNGINTCLEAR : 1;           /*!< [10..10] The RNG interrupt clear.                                         */
      __IOM uint32_t SYMDMACOMPLETEDCLEAR : 1;  /*!< [11..11] The GPR interrupt clear.                                         */
            uint32_t            : 20;
    } HOSTRGFICR_b;
  } ;

  union {
    __IOM uint32_t HOSTRGFENDIAN;               /*!< (@ 0x00000A0C) This register defines the endianness of the Host-accessible
                                                                    registers. Note: This is a special register,
                                                                    affected by internal logic. Test result
                                                                    of this register is NA.                                    */

    struct {
            uint32_t            : 3;
      __IOM uint32_t DOUTWRBG   : 1;            /*!< [3..3] DOUT write endianness:                                             */
            uint32_t            : 3;
      __IOM uint32_t DINRDBG    : 1;            /*!< [7..7] DIN write endianness:                                              */
            uint32_t            : 3;
      __IOM uint32_t DOUTWRWBG  : 1;            /*!< [11..11] DOUT write word endianness:                                      */
            uint32_t            : 3;
      __IOM uint32_t DINRDWBG   : 1;            /*!< [15..15] DIN write word endianness:                                       */
            uint32_t            : 16;
    } HOSTRGFENDIAN_b;
  } ;
  __IM  uint32_t  RESERVED35[5];

  union {
    __IOM uint32_t HOSTRGFSIGNATURE;            /*!< (@ 0x00000A24) This register holds the CryptoCell product signature.      */

    struct {
      __IOM uint32_t HOSTSIGNATURE : 32;        /*!< [31..0] Identification 'signature': always returns a fixed value,
                                                     used by Host driver to verify CryptoCell presence at this
                                                     address.                                                                  */
    } HOSTRGFSIGNATURE_b;
  } ;

  union {
    __IOM uint32_t HOSTBOOT;                    /*!< (@ 0x00000A28) This register holds the values of CryptoCells
                                                                    pre-synthesis flags                                        */

    struct {
      __IOM uint32_t SYNTHESISCONFIG : 1;       /*!< [0..0] POWER_GATING_EXISTS_LOCAL                                          */
      __IOM uint32_t LARGERKEKLOCAL : 1;        /*!< [1..1] LARGE_RKEK_LOCAL                                                   */
      __IOM uint32_t HASHINFUSESLOCAL : 1;      /*!< [2..2] HASH_IN_FUSES_LOCAL                                                */
      __IOM uint32_t EXTMEMSECUREDLOCAL : 1;    /*!< [3..3] EXT_MEM_SECURED_LOCAL                                              */
            uint32_t            : 1;
      __IOM uint32_t RKEKECCEXISTSLOCALN : 1;   /*!< [5..5] RKEK_ECC_EXISTS_LOCAL_N                                            */
      __IOM uint32_t SRAMSIZELOCAL : 3;         /*!< [8..6] SRAM_SIZE_LOCAL                                                    */
      __IOM uint32_t DSCRPTREXISTSLOCAL : 1;    /*!< [9..9] DSCRPTR_EXISTS_LOCAL                                               */
      __IOM uint32_t PAUEXISTSLOCAL : 1;        /*!< [10..10] PAU_EXISTS_LOCAL                                                 */
      __IOM uint32_t RNGEXISTSLOCAL : 1;        /*!< [11..11] RNG_EXISTS_LOCAL                                                 */
      __IOM uint32_t PKAEXISTSLOCAL : 1;        /*!< [12..12] PKA_EXISTS_LOCAL                                                 */
      __IOM uint32_t RC4EXISTSLOCAL : 1;        /*!< [13..13] RC4_EXISTS_LOCAL                                                 */
      __IOM uint32_t SHA512PRSNTLOCAL : 1;      /*!< [14..14] SHA_512_PRSNT_LOCAL                                              */
      __IOM uint32_t SHA256PRSNTLOCAL : 1;      /*!< [15..15] SHA_256_PRSNT_LOCAL                                              */
      __IOM uint32_t MD5PRSNTLOCAL : 1;         /*!< [16..16] MD5_PRSNT_LOCAL                                                  */
      __IOM uint32_t HASHEXISTSLOCAL : 1;       /*!< [17..17] HASH_EXISTS_LOCAL                                                */
      __IOM uint32_t C2EXISTSLOCAL : 1;         /*!< [18..18] C2_EXISTS_LOCAL                                                  */
      __IOM uint32_t DESEXISTSLOCAL : 1;        /*!< [19..19] DES_EXISTS_LOCAL                                                 */
      __IOM uint32_t AESXCBCMACEXISTSLOCAL : 1; /*!< [20..20] AES_XCBC_MAC_EXISTS_LOCAL                                        */
      __IOM uint32_t AESCMACEXISTSLOCAL : 1;    /*!< [21..21] AES_CMAC_EXISTS_LOCAL                                            */
      __IOM uint32_t AESCCMEXISTSLOCAL : 1;     /*!< [22..22] AES_CCM_EXISTS_LOCAL                                             */
      __IOM uint32_t AESXEXHWTCALCLOCAL : 1;    /*!< [23..23] AES_XEX_HW_T_CALC_LOCAL                                          */
      __IOM uint32_t AESXEXEXISTSLOCAL : 1;     /*!< [24..24] AES_XEX_EXISTS_LOCAL                                             */
      __IOM uint32_t CTREXISTSLOCAL : 1;        /*!< [25..25] CTR_EXISTS_LOCAL                                                 */
      __IOM uint32_t AESDINBYTERESOLUTIONLOCAL : 1;/*!< [26..26] AES_DIN_BYTE_RESOLUTION_LOCAL                                 */
      __IOM uint32_t TUNNELINGENBLOCAL : 1;     /*!< [27..27] TUNNELING_ENB_LOCAL                                              */
      __IOM uint32_t SUPPORT256192KEYLOCAL : 1; /*!< [28..28] SUPPORT_256_192_KEY_LOCAL                                        */
      __IOM uint32_t ONLYENCRYPTLOCAL : 1;      /*!< [29..29] ONLY_ENCRYPT_LOCAL                                               */
      __IOM uint32_t AESEXISTSLOCAL : 1;        /*!< [30..30] AES_EXISTS_LOCAL                                                 */
            uint32_t            : 1;
    } HOSTBOOT_b;
  } ;
  __IM  uint32_t  RESERVED36[3];

  union {
    __IOM uint32_t HOSTCRYPTOKEYSEL;            /*!< (@ 0x00000A38) AES hardware key select. Note: This is a special
                                                                    register, affected by internal logic. Test
                                                                    result of this register is NA.                             */

    struct {
      __IOM uint32_t SELCRYPTOKEY : 3;          /*!< [2..0] Select the source of the HW key that is used by the AES
                                                     engine:                                                                   */
            uint32_t            : 29;
    } HOSTCRYPTOKEYSEL_b;
  } ;
  __IM  uint32_t  RESERVED37[15];

  union {
    __IOM uint32_t HOSTCORECLKGATINGENABLE;     /*!< (@ 0x00000A78) This register enables the core clk gating by
                                                                    masking_enabling the cc_idle_state output
                                                                    signal.                                                    */

    struct {
      __IOM uint32_t HOSTCORECLKGATINGENABLE : 1;/*!< [0..0] Enable the core clk gating,                                       */
            uint32_t            : 31;
    } HOSTCORECLKGATINGENABLE_b;
  } ;

  union {
    __IOM uint32_t HOSTCCISIDLE;                /*!< (@ 0x00000A7C) This register holds the idle indication of CC
                                                                    . Note: This is a special register, affected
                                                                    by internal logic. Test result of this register
                                                                    is NA.                                                     */

    struct {
      __IOM uint32_t HOSTCCISIDLE : 1;          /*!< [0..0] Read if CC is idle.                                                */
      __IOM uint32_t HOSTCCISIDLEEVENT : 1;     /*!< [1..1] The event that indicates that CC is idle.                          */
      __IOM uint32_t SYMISBUSY  : 1;            /*!< [2..2] symetric flow is busy                                              */
      __IOM uint32_t AHBISIDLE  : 1;            /*!< [3..3] ahb stste machine is idle                                          */
      __IOM uint32_t NVMARBISIDLE : 1;          /*!< [4..4] nvm arbiter is idle                                                */
      __IOM uint32_t NVMISIDLE  : 1;            /*!< [5..5] nvm is idle                                                        */
      __IOM uint32_t FATALWR    : 1;            /*!< [6..6] fatal write                                                        */
      __IOM uint32_t RNGISIDLE  : 1;            /*!< [7..7] rng is idle                                                        */
      __IOM uint32_t PKAISIDLE  : 1;            /*!< [8..8] pka is idle                                                        */
      __IOM uint32_t CRYPTOISIDLE : 1;          /*!< [9..9] crypto flow is done                                                */
            uint32_t            : 22;
    } HOSTCCISIDLE_b;
  } ;

  union {
    __IOM uint32_t HOSTPOWERDOWN;               /*!< (@ 0x00000A80) This register start the power-down sequence.
                                                                    Note: This is a special register, affected
                                                                    by internal logic. Test result of this register
                                                                    is NA.                                                     */

    struct {
      __IOM uint32_t HOSTPOWERDOWN : 1;         /*!< [0..0] Power down enable register.                                        */
            uint32_t            : 31;
    } HOSTPOWERDOWN_b;
  } ;

  union {
    __IOM uint32_t HOSTREMOVEGHASHENGINE;       /*!< (@ 0x00000A84) These inputs are to be statically tied to 0 or
                                                                    1 by the customers. When such an input is
                                                                    set, the matching engines inputs are tied
                                                                    to zero and its outputs are disconnected,
                                                                    so that the engine will be entirely removed
                                                                    by Synthesis                                               */

    struct {
      __IOM uint32_t HOSTREMOVEGHASHENGINE : 1; /*!< [0..0] Read the Remove_chacha_engine input                                */
            uint32_t            : 31;
    } HOSTREMOVEGHASHENGINE_b;
  } ;

  union {
    __IOM uint32_t HOSTREMOVECHACHAENGINE;      /*!< (@ 0x00000A88) These inputs are to be statically tied to 0 or
                                                                    1 by the customers. When such an input is
                                                                    set, the matching engines inputs are tied
                                                                    to zero and its outputs are disconnected,
                                                                    so that the engine will be entirely removed
                                                                    by Synthesis                                               */

    struct {
      __IOM uint32_t HOSTREMOVECHACHAENGINE : 1;/*!< [0..0] Read the Remove_ghash_engine input                                 */
            uint32_t            : 31;
    } HOSTREMOVECHACHAENGINE_b;
  } ;
  __IM  uint32_t  RESERVED38[29];

  union {
    __IOM uint32_t AHBMSINGLES;                 /*!< (@ 0x00000B00) This register forces the ahb transactions to
                                                                    be always singles.                                         */

    struct {
      __IOM uint32_t AHBSINGLES : 1;            /*!< [0..0] Force ahb singles                                                  */
            uint32_t            : 31;
    } AHBMSINGLES_b;
  } ;

  union {
    __IOM uint32_t AHBMHPROT;                   /*!< (@ 0x00000B04) This register holds the ahb prot value                     */

    struct {
      __IOM uint32_t AHBPROT    : 4;            /*!< [3..0] The ahb prot value                                                 */
            uint32_t            : 28;
    } AHBMHPROT_b;
  } ;

  union {
    __IOM uint32_t AHBMHMASTLOCK;               /*!< (@ 0x00000B08) This register holds ahb hmastlock value                    */

    struct {
      __IOM uint32_t AHBHMASTLOCK : 1;          /*!< [0..0] The hmastlock value.                                               */
            uint32_t            : 31;
    } AHBMHMASTLOCK_b;
  } ;

  union {
    __IOM uint32_t AHBMHNONSEC;                 /*!< (@ 0x00000B0C) This register holds ahb hnonsec value                      */

    struct {
      __IOM uint32_t AHBWRITEHNONSEC : 1;       /*!< [0..0] The hnonsec value for write transaction.                           */
      __IOM uint32_t AHBREADHNONSEC : 1;        /*!< [1..1] The hnonsec value for read transaction.                            */
            uint32_t            : 30;
    } AHBMHNONSEC_b;
  } ;
  __IM  uint32_t  RESERVED39[60];

  union {
    __IOM uint32_t DINBUFFER;                   /*!< (@ 0x00000C00) This address can be used by the CPU to write
                                                                    data directly to the DIN buffer to be sent
                                                                    to engines.                                                */

    struct {
      __IOM uint32_t DINBUFFERDATA : 32;        /*!< [31..0] This register is mapped into 8 addresses in order to
                                                     enable a CPU burst.                                                       */
    } DINBUFFER_b;
  } ;
  __IM  uint32_t  RESERVED40[7];

  union {
    __IOM uint32_t DINMEMDMABUSY;               /*!< (@ 0x00000C20) Indicates whether memory (AXI) source DMA (DIN)
                                                                    is busy.                                                   */

    struct {
      __IOM uint32_t DINMEMDMABUSY : 1;         /*!< [0..0] DIN memory DMA busy                                                */
            uint32_t            : 31;
    } DINMEMDMABUSY_b;
  } ;
  __IM  uint32_t  RESERVED41;

  union {
    __IOM uint32_t SRCLLIWORD0;                 /*!< (@ 0x00000C28) This register is used in direct LLI mode - holds
                                                                    the location of the data source in the memory
                                                                    (AXI).                                                     */

    struct {
      __IOM uint32_t SRCLLIWORD0 : 32;          /*!< [31..0] Source address within memory.                                     */
    } SRCLLIWORD0_b;
  } ;

  union {
    __IOM uint32_t SRCLLIWORD1;                 /*!< (@ 0x00000C2C) This register is used in direct LLI mode - holds
                                                                    the number of bytes to be read from the
                                                                    memory (AXI). Writing to this register triggers
                                                                    the DMA. Note: This is a special register,
                                                                    affected by internal logic. Test result
                                                                    of this register is NA.                                    */

    struct {
      __IOM uint32_t BYTESNUM   : 30;           /*!< [29..0] Total number of bytes to read using DMA in this entry             */
      __IOM uint32_t FIRST      : 1;            /*!< [30..30] 0x1 - Indicates the first LLI entry                              */
      __IOM uint32_t LAST       : 1;            /*!< [31..31] 0x1 - Indicates the last LLI entry                               */
    } SRCLLIWORD1_b;
  } ;

  union {
    __IOM uint32_t SRAMSRCADDR;                 /*!< (@ 0x00000C30) Location of data (start address) to be read from
                                                                    SRAM. Note: This is a special register,
                                                                    affected by internal logic. Test result
                                                                    of this register is NA.                                    */

    struct {
      __IOM uint32_t SRAMSOURCE : 32;           /*!< [31..0] SRAM source base address of data                                  */
    } SRAMSRCADDR_b;
  } ;

  union {
    __IOM uint32_t DINSRAMBYTESLEN;             /*!< (@ 0x00000C34) This register holds the size of the data (in
                                                                    bytes) to be read from the SRAM. Note: This
                                                                    is a special register, affected by internal
                                                                    logic. Test result of this register is NA.                 */

    struct {
      __IOM uint32_t BYTESLEN   : 32;           /*!< [31..0] Size of data to read from SRAM (bytes). This is the
                                                     trigger to the SRAM SRC DMA.                                              */
    } DINSRAMBYTESLEN_b;
  } ;

  union {
    __IOM uint32_t DINSRAMDMABUSY;              /*!< (@ 0x00000C38) This register holds the status of the SRAM DMA
                                                                    DIN.                                                       */

    struct {
      __IOM uint32_t BUSY       : 1;            /*!< [0..0] DIN SRAM DMA busy:                                                 */
            uint32_t            : 31;
    } DINSRAMDMABUSY_b;
  } ;

  union {
    __IOM uint32_t DINSRAMENDIANNESS;           /*!< (@ 0x00000C3C) This register defines the endianness of the DIN
                                                                    interface to SRAM.                                         */

    struct {
      __IOM uint32_t SRAMDINENDIANNESS : 1;     /*!< [0..0] Defines the endianness of DIN interface to SRAM:                   */
            uint32_t            : 31;
    } DINSRAMENDIANNESS_b;
  } ;
  __IM  uint32_t  RESERVED42[2];

  union {
    __IOM uint32_t DINCPUDATASIZE;              /*!< (@ 0x00000C48) This register hold the number of bytes to be
                                                                    transmited using external DMA. Note: This
                                                                    is a special register, affected by internal
                                                                    logic. Test result of this register is NA.                 */

    struct {
      __IOM uint32_t CPUDINSIZE : 16;           /*!< [15..0] When using external DMA, the size of transmited data
                                                     in bytes should be written to this register.                              */
            uint32_t            : 16;
    } DINCPUDATASIZE_b;
  } ;
  __IM  uint32_t  RESERVED43;

  union {
    __IOM uint32_t FIFOINEMPTY;                 /*!< (@ 0x00000C50) DIN FIFO empty indication                                  */

    struct {
      __IOM uint32_t EMPTY      : 1;            /*!< [0..0] 0x1 - FIFO empty                                                   */
            uint32_t            : 31;
    } FIFOINEMPTY_b;
  } ;
  __IM  uint32_t  RESERVED44;

  union {
    __IOM uint32_t DINFIFORSTPNTR;              /*!< (@ 0x00000C58) Writing to this register resets the DIN_FIFO
                                                                    pointers.                                                  */

    struct {
      __IOM uint32_t RST        : 1;            /*!< [0..0] Writing any value to this address resets the DIN_FIFO
                                                     pointers.                                                                 */
            uint32_t            : 31;
    } DINFIFORSTPNTR_b;
  } ;
  __IM  uint32_t  RESERVED45[41];

  union {
    __IOM uint32_t DOUTBUFFER;                  /*!< (@ 0x00000D00) Cryptographic result - CPU can directly access
                                                                    it. Note: This is a special register, affected
                                                                    by internal logic. Test result of this register
                                                                    is NA.                                                     */

    struct {
      __IOM uint32_t DATA       : 32;           /*!< [31..0] DOUT This address can be used by the CPU to read data
                                                     directly from the DOUT buffer.                                            */
    } DOUTBUFFER_b;
  } ;
  __IM  uint32_t  RESERVED46[7];

  union {
    __IOM uint32_t DOUTMEMDMABUSY;              /*!< (@ 0x00000D20) DOUT memory DMA busy - Indicates that memory
                                                                    (AXI) destination DMA (DOUT) is busy,                      */

    struct {
      __IOM uint32_t DOUTMEMDMABUSY : 1;        /*!< [0..0] DOUT memory DMA busy:                                              */
            uint32_t            : 31;
    } DOUTMEMDMABUSY_b;
  } ;
  __IM  uint32_t  RESERVED47;

  union {
    __IOM uint32_t DSTLLIWORD0;                 /*!< (@ 0x00000D28) This register is used in direct LLI mode - holds
                                                                    the location of the data destination in
                                                                    the memory (AXI)                                           */

    struct {
      __IOM uint32_t DSTLLIWORD0 : 32;          /*!< [31..0] Destination address within memory                                 */
    } DSTLLIWORD0_b;
  } ;

  union {
    __IOM uint32_t DSTLLIWORD1;                 /*!< (@ 0x00000D2C) This register is used in direct LLI mode - holds
                                                                    the number of bytes to be written to the
                                                                    memory (AXI). Note: This is a special register,
                                                                    affected by internal logic. Test result
                                                                    of this register is NA.                                    */

    struct {
      __IOM uint32_t BYTESNUM   : 30;           /*!< [29..0] Total byte number to be written by DMA in this entry              */
      __IOM uint32_t FIRST      : 1;            /*!< [30..30] 0x1 - Indicates the first LLI entry                              */
      __IOM uint32_t LAST       : 1;            /*!< [31..31] 0x1 - Indicates the last LLI entry                               */
    } DSTLLIWORD1_b;
  } ;

  union {
    __IOM uint32_t SRAMDESTADDR;                /*!< (@ 0x00000D30) Location of result to be sent to in SRAM. Note:
                                                                    This is a special register, affected by
                                                                    internal logic. Test result of this register
                                                                    is NA.                                                     */

    struct {
      __IOM uint32_t SRAMDEST   : 32;           /*!< [31..0] SRAM destination base address for data.                           */
    } SRAMDESTADDR_b;
  } ;

  union {
    __IOM uint32_t DOUTSRAMBYTESLEN;            /*!< (@ 0x00000D34) This register holds the size of the data (in
                                                                    bytes) to be written to the SRAM. Note:
                                                                    This is a special register, affected by
                                                                    internal logic. Test result of this register
                                                                    is NA.                                                     */

    struct {
      __IOM uint32_t BYTESLEN   : 32;           /*!< [31..0] Size of data to write to SRAM (bytes). This is the trigger
                                                     to the SRAM DST DMA.                                                      */
    } DOUTSRAMBYTESLEN_b;
  } ;

  union {
    __IOM uint32_t DOUTSRAMDMABUSY;             /*!< (@ 0x00000D38) This register holds the status of the SRAM DMA
                                                                    DOUT.                                                      */

    struct {
      __IOM uint32_t BUSY       : 1;            /*!< [0..0] DOUT SRAM DMA busy status.                                         */
            uint32_t            : 31;
    } DOUTSRAMDMABUSY_b;
  } ;

  union {
    __IOM uint32_t DOUTSRAMENDIANNESS;          /*!< (@ 0x00000D3C) This register defines the endianness of the DOUT
                                                                    interface from SRAM.                                       */

    struct {
      __IOM uint32_t DOUTSRAMENDIANNESS : 1;    /*!< [0..0] Defines the endianness of DOUT interface from SRAM:                */
            uint32_t            : 31;
    } DOUTSRAMENDIANNESS_b;
  } ;
  __IM  uint32_t  RESERVED48;

  union {
    __IOM uint32_t READALIGNLAST;               /*!< (@ 0x00000D44) Indication that the next read from the CPU is
                                                                    the last one. This is needed only when the
                                                                    data size is NOT modulo 4 (e.g. HASH padding).             */

    struct {
      __IOM uint32_t LAST       : 1;            /*!< [0..0] 0x1 - Flush the read aligner content (used for reading
                                                     the last data).                                                           */
            uint32_t            : 31;
    } READALIGNLAST_b;
  } ;
  __IM  uint32_t  RESERVED49[2];

  union {
    __IOM uint32_t DOUTFIFOEMPTY;               /*!< (@ 0x00000D50) DOUT_FIFO_EMPTY Register.                                  */

    struct {
      __IOM uint32_t DOUTFIFOEMPTY : 1;         /*!< [0..0] DOUT FIFO empty status.                                            */
            uint32_t            : 31;
    } DOUTFIFOEMPTY_b;
  } ;
  __IM  uint32_t  RESERVED50[107];

  union {
    __IOM uint32_t SRAMDATA;                    /*!< (@ 0x00000F00) READ WRITE DATA FROM SRAM. Note: This is a special
                                                                    register, affected by internal logic. Test
                                                                    result of this register is NA.                             */

    struct {
      __IOM uint32_t SRAMDATA   : 32;           /*!< [31..0] 32 bit write or read from SRAM: read - triggers the
                                                     SRAM read DMA address automatically incremented write -
                                                     triggers the SRAM write DMA address automatically incremented             */
    } SRAMDATA_b;
  } ;

  union {
    __IOM uint32_t SRAMADDR;                    /*!< (@ 0x00000F04) first address given to SRAM DMA for read_write
                                                                    transactions from SRAM                                     */

    struct {
      __IOM uint32_t SRAMADDR   : 15;           /*!< [14..0] SRAM starting address                                             */
            uint32_t            : 17;
    } SRAMADDR_b;
  } ;

  union {
    __IOM uint32_t SRAMDATAREADY;               /*!< (@ 0x00000F08) The SRAM content is ready for read in SRAM_DATA.           */

    struct {
      __IOM uint32_t SRAMREADY  : 1;            /*!< [0..0] SRAM content is ready for read in SRAM_DATA.                       */
            uint32_t            : 31;
    } SRAMDATAREADY_b;
  } ;
  __IM  uint32_t  RESERVED51[49];

  union {
    __IOM uint32_t PERIPHERALID4;               /*!< (@ 0x00000FD0) Peripheral ID 4 (PID4).                                    */

    struct {
      __IOM uint32_t DES2JEP106 : 4;            /*!< [3..0] for ARM products.                                                  */
            uint32_t            : 28;
    } PERIPHERALID4_b;
  } ;
  __IM  uint32_t  RESERVED52[3];

  union {
    __IOM uint32_t PERIPHERALID0;               /*!< (@ 0x00000FE0) Peripheral ID 0 (PID0).                                    */

    struct {
      __IOM uint32_t PART0      : 8;            /*!< [7..0] Identification register part number, bits[7:0]                     */
            uint32_t            : 24;
    } PERIPHERALID0_b;
  } ;

  union {
    __IOM uint32_t PERIPHERALID1;               /*!< (@ 0x00000FE4) Peripheral ID 1 (PID1).                                    */

    struct {
      __IOM uint32_t PART1      : 4;            /*!< [3..0] Identification register part number, bits[11:8]                    */
      __IOM uint32_t DES0JEP106 : 4;            /*!< [7..4] for ARM products.                                                  */
            uint32_t            : 24;
    } PERIPHERALID1_b;
  } ;

  union {
    __IOM uint32_t PERIPHERALID2;               /*!< (@ 0x00000FE8) Peripheral ID 2 (PID2).                                    */

    struct {
      __IOM uint32_t DES1JEP106 : 3;            /*!< [2..0] for ARM products.                                                  */
      __IOM uint32_t JEDEC      : 1;            /*!< [3..3] constant 0x1. Indicates that a JEDEC assigned value is
                                                     used.                                                                     */
      __IOM uint32_t REVISION   : 4;            /*!< [7..4] starts at zero and increments for every new IP release.            */
            uint32_t            : 24;
    } PERIPHERALID2_b;
  } ;

  union {
    __IOM uint32_t PERIPHERALID3;               /*!< (@ 0x00000FEC) Peripheral ID 3 (PID3).                                    */

    struct {
      __IOM uint32_t CMOD       : 4;            /*!< [3..0] Customer Modified, normally zero, but if a partner applies
                                                     any changes themselves, they must change this value.                      */
      __IOM uint32_t REVAND     : 4;            /*!< [7..4] starts at zero for every Revision, and increments if
                                                     metal fixes are applied between 2 IP releases.                            */
            uint32_t            : 24;
    } PERIPHERALID3_b;
  } ;

  union {
    __IOM uint32_t COMPONENTID0;                /*!< (@ 0x00000FF0) Component ID0.                                             */

    struct {
      __IOM uint32_t PRMBL0     : 8;            /*!< [7..0] constant 0xD                                                       */
            uint32_t            : 24;
    } COMPONENTID0_b;
  } ;

  union {
    __IOM uint32_t COMPONENTID1;                /*!< (@ 0x00000FF4) Component ID1.                                             */

    struct {
      __IOM uint32_t PRMBL1     : 4;            /*!< [3..0] constant 0x0                                                       */
      __IOM uint32_t CLASS      : 4;            /*!< [7..4] component type 0 0xF for Cryptocell                                */
            uint32_t            : 24;
    } COMPONENTID1_b;
  } ;

  union {
    __IOM uint32_t COMPONENTID2;                /*!< (@ 0x00000FF8) Component ID2.                                             */

    struct {
      __IOM uint32_t PRMBL2     : 8;            /*!< [7..0] constant 0x5                                                       */
            uint32_t            : 24;
    } COMPONENTID2_b;
  } ;

  union {
    __IOM uint32_t COMPONENTID3;                /*!< (@ 0x00000FFC) Component ID3.                                             */

    struct {
      __IOM uint32_t PRMBL3     : 8;            /*!< [7..0] constant 0xB1                                                      */
            uint32_t            : 24;
    } COMPONENTID3_b;
  } ;
  __IM  uint32_t  RESERVED53[896];

  union {
    __IOM uint32_t HOSTDCUEN0;                  /*!< (@ 0x00001E00) The DCU [31:0] enable register. Note: This is
                                                                    a special register, affected by internal
                                                                    logic. Test result of this register is NA.                 */

    struct {
      __IOM uint32_t HOSTDCUEN0 : 32;           /*!< [31..0] Debug Control Unit (DCU) Enable bits.                             */
    } HOSTDCUEN0_b;
  } ;

  union {
    __IOM uint32_t HOSTDCUEN1;                  /*!< (@ 0x00001E04) The DCU [63:32] enable register. Note: This is
                                                                    a special register, affected by internal
                                                                    logic. Test result of this register is NA.                 */

    struct {
      __IOM uint32_t HOSTDCUEN1 : 32;           /*!< [31..0] Debug Control Unit (DCU) Enable bits.                             */
    } HOSTDCUEN1_b;
  } ;

  union {
    __IOM uint32_t HOSTDCUEN2;                  /*!< (@ 0x00001E08) The DCU [95:64] enable register. Note: This is
                                                                    a special register, affected by internal
                                                                    logic. Test result of this register is NA.                 */

    struct {
      __IOM uint32_t HOSTDCUEN2 : 32;           /*!< [31..0] Debug Control Unit (DCU) Enable bits.                             */
    } HOSTDCUEN2_b;
  } ;

  union {
    __IOM uint32_t HOSTDCUEN3;                  /*!< (@ 0x00001E0C) The DCU [1271:96] enable register. Note: This
                                                                    is a special register, affected by internal
                                                                    logic. Test result of this register is NA.                 */

    struct {
      __IOM uint32_t HOSTDCUEN3 : 32;           /*!< [31..0] Debug Control Unit (DCU) Enable bits.                             */
    } HOSTDCUEN3_b;
  } ;

  union {
    __IOM uint32_t HOSTDCULOCK0;                /*!< (@ 0x00001E10) The DCU lock register. Note: This is a special
                                                                    register, affected by internal logic. Test
                                                                    result of this register is NA.                             */

    struct {
      __IOM uint32_t HOSTDCULOCK0 : 32;         /*!< [31..0] DCU_lock [31:0] register (a dedicated lock register
                                                     per DCU bit).                                                             */
    } HOSTDCULOCK0_b;
  } ;

  union {
    __IOM uint32_t HOSTDCULOCK1;                /*!< (@ 0x00001E14) The DCU lock register. Note: This is a special
                                                                    register, affected by internal logic. Test
                                                                    result of this register is NA.                             */

    struct {
      __IOM uint32_t HOSTDCULOCK1 : 32;         /*!< [31..0] DCU_lock [63:32] register (a dedicated lock register
                                                     per DCU bit).                                                             */
    } HOSTDCULOCK1_b;
  } ;

  union {
    __IOM uint32_t HOSTDCULOCK2;                /*!< (@ 0x00001E18) The DCU lock register. Note: This is a special
                                                                    register, affected by internal logic. Test
                                                                    result of this register is NA.                             */

    struct {
      __IOM uint32_t HOSTDCULOCK2 : 32;         /*!< [31..0] DCU_lock [95:64] register (a dedicated lock register
                                                     per DCU bit).                                                             */
    } HOSTDCULOCK2_b;
  } ;

  union {
    __IOM uint32_t HOSTDCULOCK3;                /*!< (@ 0x00001E1C) The DCU lock register. Note: This is a special
                                                                    register, affected by internal logic. Test
                                                                    result of this register is NA.                             */

    struct {
      __IOM uint32_t HOSTDCULOCK3 : 32;         /*!< [31..0] DCU_lock [127:96] register (a dedicated lock register
                                                     per DCU bit).                                                             */
    } HOSTDCULOCK3_b;
  } ;

  union {
    __IOM uint32_t AOICVDCURESTRICTIONMASK0;    /*!< (@ 0x00001E20) The DCU lock register.                                     */

    struct {
      __IOM uint32_t AOICVDCURESTRICTIONMASK0 : 32;/*!< [31..0] AO_ICV_DCU_RESTRICTION_MASK [31:0] parameter, that will
                                                     be a customer modifiable.                                                 */
    } AOICVDCURESTRICTIONMASK0_b;
  } ;

  union {
    __IOM uint32_t AOICVDCURESTRICTIONMASK1;    /*!< (@ 0x00001E24) The 'ICV_DCU_restriction_mask' parameter is read
                                                                    by FW during the secure debug verification
                                                                    to prevent OEM from setting specific DCUs
                                                                    that protect ICV secrets                                   */

    struct {
      __IOM uint32_t AOICVDCURESTRICTIONMASK1 : 32;/*!< [31..0] AO_ICV_DCU_RESTRICTION_MASK [63:32] parameter, that
                                                     will be a customer modifiable.                                            */
    } AOICVDCURESTRICTIONMASK1_b;
  } ;

  union {
    __IOM uint32_t AOICVDCURESTRICTIONMASK2;    /*!< (@ 0x00001E28) The 'ICV_DCU_restriction_mask' parameter is read
                                                                    by FW during the secure debug verification
                                                                    to prevent OEM from setting specific DCUs
                                                                    that protect ICV secrets                                   */

    struct {
      __IOM uint32_t AOICVDCURESTRICTIONMASK2 : 32;/*!< [31..0] AO_ICV_DCU_RESTRICTION_MASK [95:64] parameter, that
                                                     will be a customer modifiable.                                            */
    } AOICVDCURESTRICTIONMASK2_b;
  } ;

  union {
    __IOM uint32_t AOICVDCURESTRICTIONMASK3;    /*!< (@ 0x00001E2C) The 'ICV_DCU_restriction_mask' parameter is read
                                                                    by FW during the secure debug verification
                                                                    to prevent OEM from setting specific DCUs
                                                                    that protect ICV secrets                                   */

    struct {
      __IOM uint32_t AOICVDCURESTRICTIONMASK3 : 32;/*!< [31..0] AO_ICV_DCU_RESTRICTION_MASK [127:96] parameter, that
                                                     will be a customer modifiable.                                            */
    } AOICVDCURESTRICTIONMASK3_b;
  } ;

  union {
    __IOM uint32_t AOCCSECDEBUGRESET;           /*!< (@ 0x00001E30) The reset-upon-debug indication                            */

    struct {
      __IOM uint32_t AOCCSECDEBUGRESET : 1;     /*!< [0..0] For resets Cerberus, and prevents loading the HW keys
                                                     after that reset                                                          */
            uint32_t            : 31;
    } AOCCSECDEBUGRESET_b;
  } ;

  union {
    __IOM uint32_t HOSTAOLOCKBITS;              /*!< (@ 0x00001E34) These masks will define, per LCS, which DCU bits
                                                                    will be tied to zero, even if the Host tries
                                                                    to set them. Note: This is a special register,
                                                                    affected by internal logic. Test result
                                                                    of this register is NA.                                    */

    struct {
      __IOM uint32_t HOSTFATALERR : 1;          /*!< [0..0] When the 'FATAL_ERROR' register is asserted - HW keys
                                                     will not be copied from OTP                                               */
      __IOM uint32_t HOSTKPICVLOCK : 1;         /*!< [1..1] When this FW controlled register is set, the Kpicv HW
                                                     key is masked (to zero).                                                  */
      __IOM uint32_t HOSTKCEICVLOCK : 1;        /*!< [2..2] When this FW controlled register is set, the Kceicv HW
                                                     key is masked (to zero).                                                  */
      __IOM uint32_t HOSTKCPLOCK : 1;           /*!< [3..3] When this FW controlled register is set, the Kcp HW key
                                                     is masked (to zero).                                                      */
      __IOM uint32_t HOSTKCELOCK : 1;           /*!< [4..4] When this FW controlled register is set, the Kce HW key
                                                     is masked (to zero).                                                      */
      __IOM uint32_t HOSTICVRMALOCK : 1;        /*!< [5..5] The ICV_RMA_LOCK register is set-once (per POR).                   */
      __IOM uint32_t RESETUPONDEBUGDISABLE : 1; /*!< [6..6] The RESET_UPON_DEBUG_DISABLE register is set-once (per
                                                     POR).                                                                     */
      __IOM uint32_t HOSTFORCEDFAENABLE : 1;    /*!< [7..7] When this FW controlled register is set, the AES DFA
                                                     countermeasures are enabled_disabled (regardless of the
                                                     AES_DFA_IS_ON register value).                                            */
      __IOM uint32_t HOSTDFAENABLELOCK : 1;     /*!< [8..8] When this FW control is set, the DFA_ENABLE register
                                                     cant be written until the next POR. The DFA_ENABLE_LOCK
                                                     register is set-once (per POR).                                           */
            uint32_t            : 23;
    } HOSTAOLOCKBITS_b;
  } ;

  union {
    __IOM uint32_t AOAPBFILTERING;              /*!< (@ 0x00001E38) This register holds the AO_APB_FILTERING data.
                                                                    Note: This is a special register, affected
                                                                    by internal logic. Test result of this register
                                                                    is NA.                                                     */

    struct {
      __IOM uint32_t ONLYSECACCESSALLOW : 1;    /*!< [0..0] when this FW controlled register is set, the APB slave
                                                     accepts only secure accesses                                              */
      __IOM uint32_t ONLYSECACCESSALLOWLOCK : 1;/*!< [1..1] when this FW controlled register is set, the ONLY_SEC_ACCESS_ALLOWED
                                                     register cant be modified (until the next POR).                           */
      __IOM uint32_t ONLYPRIVACCESSALLOW : 1;   /*!< [2..2] when this FW controlled register is set, the APB slave
                                                     accepts only privileged accesses                                          */
      __IOM uint32_t ONLYPRIVACCESSALLOWLOCK : 1;/*!< [3..3] when this FW controlled register is set, the APBC_ONLY_PRIV_ACCESS_ALLO
                                                     ED register cant be modified (until the next POR)                         */
      __IOM uint32_t APBCONLYSECACCESSALLOW : 1;/*!< [4..4] when this FW controlled register is set, the APB-C slave
                                                     accepts only secure accesses                                              */
      __IOM uint32_t APBCONLYSECACCESSALLOWLOCK : 1;/*!< [5..5] when this FW controlled register is set, the APBC_ONLY_SEC_ACCESS_ALLOW
                                                     D register cant be modified (until the next POR).                         */
      __IOM uint32_t APBCONLYPRIVACCESSALLOW : 1;/*!< [6..6] when this FW controlled register is set, the APB-C slave
                                                     accepts only privileged accesses                                          */
      __IOM uint32_t APBCONLYPRIVACCESSALLOWLOCK : 1;/*!< [7..7] when this FW controlled register is set, the APBC_ONLY_PRIV_ACCESS_ALLO
                                                     ED register cant be modified (until the next POR)                         */
      __IOM uint32_t APBCONLYINSTACCESSALLOW : 1;/*!< [8..8] when this FW controlled register is set, the APB-C slave
                                                     accepts only instruction accesses                                         */
      __IOM uint32_t APBCONLYINSTACCESSALLOWLOCK : 1;/*!< [9..9] when this FW controlled register is set, the APBC_ONLY_INST_ACCESS_ALLO
                                                     ED register cant be modified (until the next POR)                         */
            uint32_t            : 22;
    } AOAPBFILTERING_b;
  } ;

  union {
    __IOM uint32_t AOCCGPPC;                    /*!< (@ 0x00001E3C) holds the AO_CC_GPPC value from AONote: This
                                                                    is a special register, affected by internal
                                                                    logic. Test result of this register is NA.                 */

    struct {
      __IOM uint32_t AOCCGPPC   : 8;            /*!< [7..0] The AO_CC_GPPC value                                               */
            uint32_t            : 24;
    } AOCCGPPC_b;
  } ;

  union {
    __IOM uint32_t HOSTRGFCCSWRST;              /*!< (@ 0x00001E40) Writing to this register generates a general
                                                                    reset to CryptoCell. This reset takes about
                                                                    4 core clock cycles.Note: This is a special
                                                                    register, affected by internal logic. Test
                                                                    result of this register is NA.                             */

    struct {
      __IOM uint32_t HOSTRGFCCSWRST : 1;        /*!< [0..0] Writing 1 to this field generates a general reset to
                                                     CryptoCell.                                                               */
            uint32_t            : 31;
    } HOSTRGFCCSWRST_b;
  } ;
  __IM  uint32_t  RESERVED54[48];

  union {
    __IOM uint32_t AIBFUSEPROGCOMPLETED;        /*!< (@ 0x00001F04) This register reflects the fuse_aib_prog_completed
                                                                    input, which indicates that the fuse programming
                                                                    was completed.Note: This is a special register,
                                                                    affected by internal logic. Test result
                                                                    of this register is NA.                                    */

    struct {
      __IOM uint32_t AIBFUSEPROGCOMPLETED : 1;  /*!< [0..0] Indicates if the fuse programming operation has been
                                                     completed.                                                                */
            uint32_t            : 31;
    } AIBFUSEPROGCOMPLETED_b;
  } ;

  union {
    __IOM uint32_t NVMDEBUGSTATUS;              /*!< (@ 0x00001F08) AIB debug status register. Note: This is a special
                                                                    register, affected by internal logic. Test
                                                                    result of this register is NA.                             */

    struct {
            uint32_t            : 1;
      __IOM uint32_t NVMSM      : 3;            /*!< [3..1] Main nvm fsm                                                       */
            uint32_t            : 28;
    } NVMDEBUGSTATUS_b;
  } ;

  union {
    __IOM uint32_t LCSISVALID;                  /*!< (@ 0x00001F0C) Indicates that the LCS register holds a valid
                                                                    value.Note: This is a special register,
                                                                    affected by internal logic. Test result
                                                                    of this register is NA.                                    */

    struct {
      __IOM uint32_t LCSISVALIDREG : 1;         /*!< [0..0] Indicates whether LCS is valid.                                    */
            uint32_t            : 31;
    } LCSISVALID_b;
  } ;

  union {
    __IOM uint32_t NVMISIDLE;                   /*!< (@ 0x00001F10) Indicates that the LCS register holds a valid
                                                                    value.Note: This is a special register,
                                                                    affected by internal logic. Test result
                                                                    of this register is NA.                                    */

    struct {
      __IOM uint32_t NVMISIDLEREG : 1;          /*!< [0..0] Indicates whether the NVM manager finishes its operation,
                                                     calculates the LCS, reads the HW keys, compares the number
                                                     of zeros and clears the keys                                              */
            uint32_t            : 31;
    } NVMISIDLE_b;
  } ;

  union {
    __IOM uint32_t LCSREG;                      /*!< (@ 0x00001F14) The lifecycle state register. Note: This is a
                                                                    special register, affected by internal logic.
                                                                    Test result of this register is NA.                        */

    struct {
      __IOM uint32_t LCSREG     : 3;            /*!< [2..0] Indicates the LCS (Lifecycle State) value.                         */
            uint32_t            : 5;
      __IOM uint32_t ERRORKDRZEROCNT : 1;       /*!< [8..8] Indication that the number of zeroes in the loaded KDR
                                                     is not equal to the value set in the manufacture flag.                    */
      __IOM uint32_t ERRORPROVZEROCNT : 1;      /*!< [9..9] Indication that the number of zeroes in the loaded KCP
                                                     is not equal to the value set in the OEM flag.                            */
      __IOM uint32_t ERRORKCEZEROCNT : 1;       /*!< [10..10] Indication that the number of zeroes in the loaded
                                                     KCE is not equal to the value set in the OEM flag.                        */
      __IOM uint32_t ERRORKPICVZEROCNT : 1;     /*!< [11..11] Indication that the number of zeroes in the loaded
                                                     KPICV is not equal to the value set in the manufacture
                                                     flag.                                                                     */
      __IOM uint32_t ERRORKCEICVZEROCNT : 1;    /*!< [12..12] Indication that the number of zeroes in the loaded
                                                     KCEICV is not equal to the value set in the manufacture
                                                     flag.                                                                     */
            uint32_t            : 19;
    } LCSREG_b;
  } ;

  union {
    __IOM uint32_t HOSTSHADOWKDRREG;            /*!< (@ 0x00001F18) This register interface is used to update the
                                                                    RKEK(KDR) registers when the device is in
                                                                    CM or DM mode , it is Write-once (per warm
                                                                    boot) in RMA LCS, The RKEK is updated by
                                                                    shifting .                                                 */

    struct {
      __IOM uint32_t HOSTSHADOWKDRREG : 1;      /*!< [0..0] This field is used to update the KDR registers when the
                                                     device is in CM , DM or RMA mode, The KDR is updated by
                                                     shifting .                                                                */
            uint32_t            : 31;
    } HOSTSHADOWKDRREG_b;
  } ;

  union {
    __IOM uint32_t HOSTSHADOWKCPREG;            /*!< (@ 0x00001F1C) This register interface is used to update the
                                                                    KCP registers when the device is in CM or
                                                                    DM mode, The KCP is updated by shifting                    */

    struct {
      __IOM uint32_t HOSTSHADOWKCPREG : 1;      /*!< [0..0] This field is used to update the KCP registers when the
                                                     device is in CM or DM mode, The KCP is updated by shifting                */
            uint32_t            : 31;
    } HOSTSHADOWKCPREG_b;
  } ;

  union {
    __IOM uint32_t HOSTSHADOWKCEREG;            /*!< (@ 0x00001F20) This register interface is used to update the
                                                                    KCE registers when the device is in CM or
                                                                    DM mode, The KCE is updated by shifting                    */

    struct {
      __IOM uint32_t HOSTSHADOWKCEREG : 1;      /*!< [0..0] This field is used to update the KCE registers when the
                                                     device is in CM or DM mode, The KCE is updated by shifting                */
            uint32_t            : 31;
    } HOSTSHADOWKCEREG_b;
  } ;

  union {
    __IOM uint32_t HOSTSHADOWKPICVREG;          /*!< (@ 0x00001F24) This register interface is used to update the
                                                                    KPICV registers when the device is in CM
                                                                    or DM mode, The KPICV is updated by shifting               */

    struct {
      __IOM uint32_t HOSTSHADOWKPICVREG : 1;    /*!< [0..0] This field is used to update the KPICV registers when
                                                     the device is in CM or DM mode, The KPICV is updated by
                                                     shifting                                                                  */
            uint32_t            : 31;
    } HOSTSHADOWKPICVREG_b;
  } ;

  union {
    __IOM uint32_t HOSTSHADOWKCEICVREG;         /*!< (@ 0x00001F28) This register interface is used to update the
                                                                    KCEICV registers when the device is in CM
                                                                    or DM mode, The KCEICV is updated by shifting              */

    struct {
      __IOM uint32_t HOSTSHADOWKCEICVREG : 1;   /*!< [0..0] This field is used to update the KCEICV registers when
                                                     the device is in CM or DM mode, The KCEICV is updated by
                                                     shifting                                                                  */
            uint32_t            : 31;
    } HOSTSHADOWKCEICVREG_b;
  } ;

  union {
    __IOM uint32_t OTPADDRWIDTHDEF;             /*!< (@ 0x00001F2C) OTP_ADDR_WIDTH parameter, that will define the
                                                                    integrated OTP address width (address in
                                                                    words). The supported sizes are 6 (for 2
                                                                    Kbits),7,8,9,11 (for 64 Kbits). The default
                                                                    value in the provided RTL will be 6.Note:
                                                                    This is a special register, affected by
                                                                    internal logic. Test result of this register
                                                                    is NA.                                                     */

    struct {
      __IOM uint32_t OTPADDRWIDTHDEF : 4;       /*!< [3..0] Holds the OTP_ADDR_WIDTH_DEF value.                                */
            uint32_t            : 28;
    } OTPADDRWIDTHDEF_b;
  } ;
} CRYPTO_Type;                                  /*!< Size = 7984 (0x1f30)                                                      */



/* =========================================================================================================================== */
/* ================                                            DSP                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief DSP Control Interface (DSP)
  */

typedef struct {                                /*!< (@ 0x40100000) DSP Structure                                              */
  __IM  uint32_t  RESERVED[16];

  union {
    __IOM uint32_t MUTEX0;                      /*!< (@ 0x00000040) MUTEX 0                                                    */

    struct {
      __IOM uint32_t MUTEX0     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
                                                     owns mutex, 100=DSP1 owns mutex)                                          */
            uint32_t            : 29;
    } MUTEX0_b;
  } ;

  union {
    __IOM uint32_t MUTEX1;                      /*!< (@ 0x00000044) MUTEX 1                                                    */

    struct {
      __IOM uint32_t MUTEX1     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
                                                     owns mutex, 100=DSP1 owns mutex)                                          */
            uint32_t            : 29;
    } MUTEX1_b;
  } ;

  union {
    __IOM uint32_t MUTEX2;                      /*!< (@ 0x00000048) MUTEX 2                                                    */

    struct {
      __IOM uint32_t MUTEX2     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
                                                     owns mutex, 100=DSP1 owns mutex)                                          */
            uint32_t            : 29;
    } MUTEX2_b;
  } ;

  union {
    __IOM uint32_t MUTEX3;                      /*!< (@ 0x0000004C) MUTEX 3                                                    */

    struct {
      __IOM uint32_t MUTEX3     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
                                                     owns mutex, 100=DSP1 owns mutex)                                          */
            uint32_t            : 29;
    } MUTEX3_b;
  } ;

  union {
    __IOM uint32_t MUTEX4;                      /*!< (@ 0x00000050) MUTEX 4                                                    */

    struct {
      __IOM uint32_t MUTEX4     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
                                                     owns mutex, 100=DSP1 owns mutex)                                          */
            uint32_t            : 29;
    } MUTEX4_b;
  } ;

  union {
    __IOM uint32_t MUTEX5;                      /*!< (@ 0x00000054) MUTEX 5                                                    */

    struct {
      __IOM uint32_t MUTEX5     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
                                                     owns mutex, 100=DSP1 owns mutex)                                          */
            uint32_t            : 29;
    } MUTEX5_b;
  } ;

  union {
    __IOM uint32_t MUTEX6;                      /*!< (@ 0x00000058) MUTEX 6                                                    */

    struct {
      __IOM uint32_t MUTEX6     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
                                                     owns mutex, 100=DSP1 owns mutex)                                          */
            uint32_t            : 29;
    } MUTEX6_b;
  } ;

  union {
    __IOM uint32_t MUTEX7;                      /*!< (@ 0x0000005C) MUTEX 7                                                    */

    struct {
      __IOM uint32_t MUTEX7     : 3;            /*!< [2..0] Mutex Value (000=resource free, 001=CPU owns mutex, 010=DSP0
                                                     owns mutex, 100=DSP1 owns mutex)                                          */
            uint32_t            : 29;
    } MUTEX7_b;
  } ;
  __IM  uint32_t  RESERVED1[8];

  union {
    __IOM uint32_t CPUMBINTSET;                 /*!< (@ 0x00000080) CPU Mailbox Interrupt Set                                  */

    struct {
      __IOM uint32_t CPUMBINTSET : 32;          /*!< [31..0] CPU Mailbox interrupt Set. The corresponding data bit
                                                     will set the interrupt.                                                   */
    } CPUMBINTSET_b;
  } ;

  union {
    __IOM uint32_t CPUMBINTCLR;                 /*!< (@ 0x00000084) CPU Mailbox Interrupt Clear                                */

    struct {
      __IOM uint32_t CPUMBINTCLR : 32;          /*!< [31..0] CPU Mailbox interrupt Clear. The corresponding data
                                                     bit will clear the interrupt.                                             */
    } CPUMBINTCLR_b;
  } ;

  union {
    __IOM uint32_t CPUMBINTSTAT;                /*!< (@ 0x00000088) CPU Mailbox Interrupt Status                               */

    struct {
      __IOM uint32_t CPUMBINTSTAT : 32;         /*!< [31..0] CPU CPU Mailbox interrupt status                                  */
    } CPUMBINTSTAT_b;
  } ;

  union {
    __IOM uint32_t CPUCPUMBDATA;                /*!< (@ 0x0000008C) CPU CPU Mailbox Data                                       */

    struct {
      __IOM uint32_t CPUCPUMBDATA : 32;         /*!< [31..0] CPU CPU Mailbox data                                              */
    } CPUCPUMBDATA_b;
  } ;

  union {
    __IOM uint32_t DSP0CPUMBDATA;               /*!< (@ 0x00000090) DSP0 to CPU Mailbox Data                                   */

    struct {
      __IOM uint32_t DSP0CPUMBDATA : 32;        /*!< [31..0] DSP0 to CPU Mailbox data                                          */
    } DSP0CPUMBDATA_b;
  } ;

  union {
    __IOM uint32_t DSP1CPUMBDATA;               /*!< (@ 0x00000094) DSP1 to CPU Mailbox Data                                   */

    struct {
      __IOM uint32_t DSP1CPUMBDATA : 32;        /*!< [31..0] DSP1 to CPU Mailbox data                                          */
    } DSP1CPUMBDATA_b;
  } ;
  __IM  uint32_t  RESERVED2[2];

  union {
    __IOM uint32_t DSP0MBINTSET;                /*!< (@ 0x000000A0) DSP0 Mailbox Interrupt Set                                 */

    struct {
      __IOM uint32_t DSP0MBINTSET : 32;         /*!< [31..0] DSP0 Mailbox interrupt Set. The corresponding data bit
                                                     will set the interrupt.                                                   */
    } DSP0MBINTSET_b;
  } ;

  union {
    __IOM uint32_t DSP0MBINTCLR;                /*!< (@ 0x000000A4) DSP0 Mailbox Interrupt Clear                               */

    struct {
      __IOM uint32_t DSP0MBINTCLR : 32;         /*!< [31..0] DSP0 Mailbox interrupt Clear. The corresponding data
                                                     bit will clear the interrupt.                                             */
    } DSP0MBINTCLR_b;
  } ;

  union {
    __IOM uint32_t DSP0MBINTSTAT;               /*!< (@ 0x000000A8) DSP 0 Mailbox Interrupt Status                             */

    struct {
      __IOM uint32_t DSP0MBINTSTAT : 32;        /*!< [31..0] DSP 0 CPU Mailbox interrupt                                       */
    } DSP0MBINTSTAT_b;
  } ;

  union {
    __IOM uint32_t CPUDSP0MBDATA;               /*!< (@ 0x000000AC) CPU to DSP 0 Mailbox Data                                  */

    struct {
      __IOM uint32_t CPUDSP0MBDATA : 32;        /*!< [31..0] DSP 0 CPU Mailbox data                                            */
    } CPUDSP0MBDATA_b;
  } ;

  union {
    __IOM uint32_t DSP0DSP0MBDATA;              /*!< (@ 0x000000B0) DSP0 to DSP 0 Mailbox Data                                 */

    struct {
      __IOM uint32_t DSP0DSP0MBDATA : 32;       /*!< [31..0] DSP0 to DSP 0 Mailbox data                                        */
    } DSP0DSP0MBDATA_b;
  } ;

  union {
    __IOM uint32_t DSP1DSP0MBDATA;              /*!< (@ 0x000000B4) DSP1 to DSP 0 Mailbox Data                                 */

    struct {
      __IOM uint32_t DSP1DSP0MBDATA : 32;       /*!< [31..0] DSP1 to DSP 0 Mailbox data                                        */
    } DSP1DSP0MBDATA_b;
  } ;
  __IM  uint32_t  RESERVED3[2];

  union {
    __IOM uint32_t DSP1MBINTSET;                /*!< (@ 0x000000C0) DSP1 Mailbox Interrupt Set                                 */

    struct {
      __IOM uint32_t DSP1MBINTSET : 32;         /*!< [31..0] DSP1 Mailbox interrupt Set. The corresponding data bit
                                                     will set the interrupt.                                                   */
    } DSP1MBINTSET_b;
  } ;

  union {
    __IOM uint32_t DSP1MBINTCLR;                /*!< (@ 0x000000C4) DSP1 Mailbox Interrupt Clear                               */

    struct {
      __IOM uint32_t DSP1MBINTCLR : 32;         /*!< [31..0] DSP1 Mailbox interrupt Clear. The corresponding data
                                                     bit will clear the interrupt.                                             */
    } DSP1MBINTCLR_b;
  } ;

  union {
    __IOM uint32_t DSP1MBINTSTAT;               /*!< (@ 0x000000C8) DSP 1 Mailbox Interrupt Status                             */

    struct {
      __IOM uint32_t DSP1MBINTSTAT : 32;        /*!< [31..0] DSP 1 CPU Mailbox interrupt                                       */
    } DSP1MBINTSTAT_b;
  } ;

  union {
    __IOM uint32_t CPUDSP1MBDATA;               /*!< (@ 0x000000CC) CPU to DSP 1 Mailbox Data                                  */

    struct {
      __IOM uint32_t CPUDSP1MBDATA : 32;        /*!< [31..0] DSP 1 CPU Mailbox data                                            */
    } CPUDSP1MBDATA_b;
  } ;

  union {
    __IOM uint32_t DSP0DSP1MBDATA;              /*!< (@ 0x000000D0) DSP0 to DSP 1 Mailbox Data                                 */

    struct {
      __IOM uint32_t DSP0DSP1MBDATA : 32;       /*!< [31..0] DSP0 to DSP 1 Mailbox data                                        */
    } DSP0DSP1MBDATA_b;
  } ;

  union {
    __IOM uint32_t DSP1DSP1MBDATA;              /*!< (@ 0x000000D4) DSP1 to DSP 1 Mailbox Data                                 */

    struct {
      __IOM uint32_t DSP1DSP1MBDATA : 32;       /*!< [31..0] DSP1 to DSP 1 Mailbox data                                        */
    } DSP1DSP1MBDATA_b;
  } ;
  __IM  uint32_t  RESERVED4[10];

  union {
    __IOM uint32_t DSP0CONTROL;                 /*!< (@ 0x00000100) DSP 0 control settings                                     */

    struct {
      __IOM uint32_t DSP0STATVECSEL : 1;        /*!< [0..0] DSP 0 StatVectorSel                                                */
      __IOM uint32_t DSP0BRESET : 1;            /*!< [1..1] DSP0 BReset. This is the reset used for Xtensa core.
                                                     S/w must clear this reset to use Dsp.                                     */
      __IOM uint32_t DSP0DRESET : 1;            /*!< [2..2] DSP0 DReset. This is the reset used for debug functionality
                                                     like OCD/TRAX etc.                                                        */
      __IOM uint32_t DSP0RUNSTALL : 1;          /*!< [3..3] DSP 0 RunStall. When asserted, DSP 0 will stall until
                                                     bit is cleared.                                                           */
      __IOM uint32_t DSP0IDMATRIG : 2;          /*!< [5..4] DSP 0 IDMA Trigger Control                                         */
            uint32_t            : 2;
      __IOM uint32_t DSP0IDMAXTRIGSRC : 23;     /*!< [30..8] DSP 0 IDMA Cross Trigger Source. All enabled sources
                                                     are ANDed to generate a trigger enable.
                                                     Bit30-12:IRQ18-0 Bit11: IDMATRIGPULSE, Bit10: DSP Timer1,
                                                     Bit9: DSP Timer0, Bit8: alternate DSP iDMA trigger out                    */
            uint32_t            : 1;
    } DSP0CONTROL_b;
  } ;

  union {
    __IOM uint32_t DSP0RESETVEC;                /*!< (@ 0x00000104) DSP 0 Reset Vector                                         */

    struct {
      __IOM uint32_t DSP0RESETVEC : 32;         /*!< [31..0] DSP 0 Reset Vector Address.                                       */
    } DSP0RESETVEC_b;
  } ;

  union {
    __IOM uint32_t DSP0IRQMASK;                 /*!< (@ 0x00000108) DSP 0 IRQ Mask                                             */

    struct {
      __IOM uint32_t DSP0IRQMASK : 23;          /*!< [22..0] DSP 0 IRQ Mask                                                    */
            uint32_t            : 9;
    } DSP0IRQMASK_b;
  } ;

  union {
    __IOM uint32_t DSP0WAKEMASK;                /*!< (@ 0x0000010C) DSP 0 IRQ Wake Mask                                        */

    struct {
      __IOM uint32_t DSP0WAKEMASK : 23;         /*!< [22..0] DSP 0 IRQ Wake Mask                                               */
            uint32_t            : 9;
    } DSP0WAKEMASK_b;
  } ;

  union {
    __IOM uint32_t DSP0RAWIRQSTAT31to0;         /*!< (@ 0x00000110) DSP 0 Raw IRQ31-0 Status                                   */

    struct {
      __IOM uint32_t DSP0RAWIRQSTAT31to0 : 32;  /*!< [31..0] DSP 0 Raw IRQ31-0 Status                                          */
    } DSP0RAWIRQSTAT31to0_b;
  } ;

  union {
    __IOM uint32_t DSP0RAWIRQSTAT63to32;        /*!< (@ 0x00000114) DSP 0 Raw IRQ63-32 Status                                  */

    struct {
      __IOM uint32_t DSP0RAWIRQSTAT63to32 : 32; /*!< [31..0] DSP 0 Raw IRQ63-32 Status                                         */
    } DSP0RAWIRQSTAT63to32_b;
  } ;

  union {
    __IOM uint32_t DSP0RAWIRQSTAT95to64;        /*!< (@ 0x00000118) DSP 0 Raw IRQ95-64 Status                                  */

    struct {
      __IOM uint32_t DSP0RAWIRQSTAT95to64 : 32; /*!< [31..0] DSP 0 Raw IRQ95-64 Status                                         */
    } DSP0RAWIRQSTAT95to64_b;
  } ;
  __IM  uint32_t  RESERVED5;

  union {
    __IOM uint32_t DSP0L2LVLINT;                /*!< (@ 0x00000120) DSP 0 L2 Level Interrupt Mux                               */

    struct {
      __IOM uint32_t DSP0L2LVLINT : 19;         /*!< [18..0] DSP 0 L2 Level Interrupt Mux                                      */
            uint32_t            : 13;
    } DSP0L2LVLINT_b;
  } ;

  union {
    __IOM uint32_t DSP0L3LVLINT;                /*!< (@ 0x00000124) DSP 0 L3 Level Interrupt Mux                               */

    struct {
      __IOM uint32_t DSP0L3LVLINT : 19;         /*!< [18..0] DSP 0 L3 Level Interrupt Mux                                      */
            uint32_t            : 13;
    } DSP0L3LVLINT_b;
  } ;

  union {
    __IOM uint32_t DSP0L4LVLINT;                /*!< (@ 0x00000128) DSP 0 L4 Level Interrupt Mux                               */

    struct {
      __IOM uint32_t DSP0L4LVLINT : 19;         /*!< [18..0] DSP 0 L4 Level Interrupt Mux                                      */
            uint32_t            : 13;
    } DSP0L4LVLINT_b;
  } ;

  union {
    __IOM uint32_t DSP0L5LVLINT;                /*!< (@ 0x0000012C) DSP 0 L5 Level Interrupt Mux                               */

    struct {
      __IOM uint32_t DSP0L5LVLINT : 19;         /*!< [18..0] DSP 0 L5 Level Interrupt Mux                                      */
            uint32_t            : 13;
    } DSP0L5LVLINT_b;
  } ;

  union {
    __IOM uint32_t DSP0IDMATRIGCTL;             /*!< (@ 0x00000130) DSP 0 IDMA Trigger Control and Status                      */

    struct {
      __IOM uint32_t DSP0IDMATRIGSTAT : 1;      /*!< [0..0] DSP 0 iDMA Trigger Status                                          */
            uint32_t            : 3;
      __IOM uint32_t DSP0IDMATRIGPULSE : 1;     /*!< [4..4] DSP 0 iDMA Trigger Pulse - When written a '1', this will
                                                     cause a single step enable (valid only when IDMATRIG is
                                                     set to SSTEP)                                                             */
            uint32_t            : 27;
    } DSP0IDMATRIGCTL_b;
  } ;
  __IM  uint32_t  RESERVED6[3];

  union {
    __IOM uint32_t DSP0INTORMASK31TO0A;         /*!< (@ 0x00000140) DSP0 Interrupt OR Mask A for IRQ31-0                       */

    struct {
      __IOM uint32_t DSP0INTMCUIOORMASKA : 32;  /*!< [31..0] DSP0 MCU IO Interrupt OR Mask A                                   */
    } DSP0INTORMASK31TO0A_b;
  } ;

  union {
    __IOM uint32_t DSP0INTORMASK63TO32A;        /*!< (@ 0x00000144) DSP0 Interrupt OR Mask A for IRQ63-32                      */

    struct {
      __IOM uint32_t DSP0TMRORMASKA : 10;       /*!< [9..0] DSP0 Timer Interrupt OR Mask A                                     */
            uint32_t            : 2;
      __IOM uint32_t DSP0I2SORMASKA : 4;        /*!< [15..12] DSP0 I2S Interrupt OR Mask A                                     */
      __IOM uint32_t DSP0PDMORMASKA : 4;        /*!< [19..16] DSP0 PDM Interrupt OR Mask A                                     */
            uint32_t            : 4;
      __IOM uint32_t DSP0GPIOORMASKA : 6;       /*!< [29..24] DSP0 GPIO Interrupt OR Mask A                                    */
            uint32_t            : 2;
    } DSP0INTORMASK63TO32A_b;
  } ;

  union {
    __IOM uint32_t DSP0INTORMASK95TO64A;        /*!< (@ 0x00000148) DSP0 Interrupt OR Mask A for IRQ95-64                      */

    struct {
      __IOM uint32_t DSP0MBINTORMASKA : 32;     /*!< [31..0] DSP0 Mailbox Interrupt OR Mask A                                  */
    } DSP0INTORMASK95TO64A_b;
  } ;
  __IM  uint32_t  RESERVED7;

  union {
    __IOM uint32_t DSP0INTORMASK31to0B;         /*!< (@ 0x00000150) DSP0 Interrupt OR Mask B for IRQ31-0                       */

    struct {
      __IOM uint32_t DSP0INTMCUIOORMASKB : 32;  /*!< [31..0] DSP0 MCU IO Interrupt OR Mask B                                   */
    } DSP0INTORMASK31to0B_b;
  } ;

  union {
    __IOM uint32_t DSP0INTORMASK63TO32B;        /*!< (@ 0x00000154) DSP0 Interrupt OR Mask A for IRQ63-32                      */

    struct {
      __IOM uint32_t DSP0TMRORMASKB : 10;       /*!< [9..0] DSP0 Timer Interrupt OR Mask B                                     */
            uint32_t            : 2;
      __IOM uint32_t DSP0I2SORMASKB : 4;        /*!< [15..12] DSP0 I2S Interrupt OR Mask B                                     */
      __IOM uint32_t DSP0PDMORMASKB : 4;        /*!< [19..16] DSP0 PDM Interrupt OR Mask B                                     */
            uint32_t            : 4;
      __IOM uint32_t DSP0GPIOORMASKB : 6;       /*!< [29..24] DSP0 GPIO Interrupt OR Mask B                                    */
            uint32_t            : 2;
    } DSP0INTORMASK63TO32B_b;
  } ;

  union {
    __IOM uint32_t DSP0INTORMASK95TO64B;        /*!< (@ 0x00000158) DSP0 Interrupt OR Mask B for IRQ95-64                      */

    struct {
      __IOM uint32_t DSP0MBINTORMASKB : 32;     /*!< [31..0] DSP0 Mailbox Interrupt OR Mask B                                  */
    } DSP0INTORMASK95TO64B_b;
  } ;
  __IM  uint32_t  RESERVED8;

  union {
    __IOM uint32_t DSP0INTENIRQ31TO0;           /*!< (@ 0x00000160) DSP0 INT Enable for IRQ31-0                                */

    struct {
      __IOM uint32_t DSP0INTENIRQ31TO0 : 32;    /*!< [31..0] DSP0 INT Enable for IRQ31-0                                       */
    } DSP0INTENIRQ31TO0_b;
  } ;

  union {
    __IOM uint32_t DSP0INTENIRQ63TO32;          /*!< (@ 0x00000164) DSP0 INT Enable for IRQ63-32                               */

    struct {
      __IOM uint32_t DSP0INTENIRQ63TO32 : 32;   /*!< [31..0] DSP0 INT Enable for IRQ63-32                                      */
    } DSP0INTENIRQ63TO32_b;
  } ;

  union {
    __IOM uint32_t DSP0INTENIRQ95TO64;          /*!< (@ 0x00000168) DSP0 INT Enable for IRQ95-64                               */

    struct {
      __IOM uint32_t DSP0INTENIRQ95TO64 : 32;   /*!< [31..0] DSP0 INT Enable for IRQ95-64                                      */
    } DSP0INTENIRQ95TO64_b;
  } ;
  __IM  uint32_t  RESERVED9[37];

  union {
    __IOM uint32_t DSP1CONTROL;                 /*!< (@ 0x00000200) DSP 1 control settings                                     */

    struct {
      __IOM uint32_t DSP1STATVECSEL : 1;        /*!< [0..0] DSP 1 StatVectorSel                                                */
      __IOM uint32_t DSP1BRESET : 1;            /*!< [1..1] DSP1 BReset. This is the reset used for Xtensa core.
                                                     S/w must clear this reset to use Dsp.                                     */
      __IOM uint32_t DSP1DRESET : 1;            /*!< [2..2] DSP1 DReset. This is the reset used for debug functionality
                                                     like OCD/TRAX etc.                                                        */
      __IOM uint32_t DSP1RUNSTALL : 1;          /*!< [3..3] DSP 1 RunStall. When asserted, DSP 1 will stall until
                                                     bit is cleared.                                                           */
      __IOM uint32_t DSP1IDMATRIG : 2;          /*!< [5..4] DSP 1 IDMA Trigger Control                                         */
            uint32_t            : 2;
      __IOM uint32_t DSP1IDMAXTRIGSRC : 23;     /*!< [30..8] DSP 1 IDMA Cross Trigger Source. All enabled sources
                                                     are ANDed to generate a trigger enable.
                                                     Bit30-12:IRQ18-0 Bit11: IDMATRIGPULSE, Bit10: DSP Timer1,
                                                     Bit9: DSP Timer0, Bit8: alternate DSP iDMA trigger out                    */
            uint32_t            : 1;
    } DSP1CONTROL_b;
  } ;

  union {
    __IOM uint32_t DSP1RESETVEC;                /*!< (@ 0x00000204) DSP 1 Reset Vector                                         */

    struct {
      __IOM uint32_t DSP1RESETVEC : 32;         /*!< [31..0] DSP 1 Reset Vector Address.                                       */
    } DSP1RESETVEC_b;
  } ;

  union {
    __IOM uint32_t DSP1IRQMASK;                 /*!< (@ 0x00000208) DSP 1 IRQ Mask                                             */

    struct {
      __IOM uint32_t DSP1IRQMASK : 23;          /*!< [22..0] DSP 1 IRQ Mask                                                    */
            uint32_t            : 9;
    } DSP1IRQMASK_b;
  } ;

  union {
    __IOM uint32_t DSP1WAKEMASK;                /*!< (@ 0x0000020C) DSP 1 IRQ Wake Mask                                        */

    struct {
      __IOM uint32_t DSP1WAKEMASK : 23;         /*!< [22..0] DSP 1 IRQ Wake Mask                                               */
            uint32_t            : 9;
    } DSP1WAKEMASK_b;
  } ;

  union {
    __IOM uint32_t DSP1RAWIRQSTAT31to0;         /*!< (@ 0x00000210) DSP 1 Raw IRQ31-0 Status                                   */

    struct {
      __IOM uint32_t DSP1RAWIRQSTAT31to0 : 32;  /*!< [31..0] DSP 1 Raw IRQ31-0 Status                                          */
    } DSP1RAWIRQSTAT31to0_b;
  } ;

  union {
    __IOM uint32_t DSP1RAWIRQSTAT63to32;        /*!< (@ 0x00000214) DSP 1 Raw IRQ63-32 Status                                  */

    struct {
      __IOM uint32_t DSP1RAWIRQSTAT63to32 : 32; /*!< [31..0] DSP 1 Raw IRQ63-32 Status                                         */
    } DSP1RAWIRQSTAT63to32_b;
  } ;

  union {
    __IOM uint32_t DSP1RAWIRQSTAT95to64;        /*!< (@ 0x00000218) DSP 1 Raw IRQ95-64 Status                                  */

    struct {
      __IOM uint32_t DSP1RAWIRQSTAT95to64 : 32; /*!< [31..0] DSP 1 Raw IRQ95-64 Status                                         */
    } DSP1RAWIRQSTAT95to64_b;
  } ;
  __IM  uint32_t  RESERVED10;

  union {
    __IOM uint32_t DSP1L2LVLINT;                /*!< (@ 0x00000220) DSP 1 L2 Level Interrupt Mux                               */

    struct {
      __IOM uint32_t DSP1L2LVLINT : 19;         /*!< [18..0] DSP 1 L2 Level Interrupt Mux                                      */
            uint32_t            : 13;
    } DSP1L2LVLINT_b;
  } ;

  union {
    __IOM uint32_t DSP1L3LVLINT;                /*!< (@ 0x00000224) DSP 1 L3 Level Interrupt Mux                               */

    struct {
      __IOM uint32_t DSP1L3LVLINT : 19;         /*!< [18..0] DSP 1 L3 Level Interrupt Mux                                      */
            uint32_t            : 13;
    } DSP1L3LVLINT_b;
  } ;

  union {
    __IOM uint32_t DSP1L4LVLINT;                /*!< (@ 0x00000228) DSP 1 L4 Level Interrupt Mux                               */

    struct {
      __IOM uint32_t DSP1L4LVLINT : 19;         /*!< [18..0] DSP 1 L4 Level Interrupt Mux                                      */
            uint32_t            : 13;
    } DSP1L4LVLINT_b;
  } ;

  union {
    __IOM uint32_t DSP1L5LVLINT;                /*!< (@ 0x0000022C) DSP 1 L5 Level Interrupt Mux                               */

    struct {
      __IOM uint32_t DSP1L5LVLINT : 19;         /*!< [18..0] DSP 1 L5 Level Interrupt Mux                                      */
            uint32_t            : 13;
    } DSP1L5LVLINT_b;
  } ;

  union {
    __IOM uint32_t DSP1IDMATRIGCTL;             /*!< (@ 0x00000230) DSP 1 IDMA Trigger Control and Status                      */

    struct {
      __IOM uint32_t DSP1IDMATRIGSTAT : 1;      /*!< [0..0] DSP 1 iDMA Trigger Status                                          */
            uint32_t            : 3;
      __IOM uint32_t DSP1IDMATRIGPULSE : 1;     /*!< [4..4] DSP 1 iDMA Trigger Pulse - When written a '1', this will
                                                     cause a single step enable (valid only when IDMATRIG is
                                                     set to SSTEP)                                                             */
            uint32_t            : 27;
    } DSP1IDMATRIGCTL_b;
  } ;
  __IM  uint32_t  RESERVED11[3];

  union {
    __IOM uint32_t DSP1INTORMASK31TO0A;         /*!< (@ 0x00000240) DSP1 Interrupt OR Mask A for IRQ31-0                       */

    struct {
      __IOM uint32_t DSP1INTMCUIOORMASKA : 32;  /*!< [31..0] DSP1 MCU IO Interrupt OR Mask A                                   */
    } DSP1INTORMASK31TO0A_b;
  } ;

  union {
    __IOM uint32_t DSP1INTORMASK63TO32A;        /*!< (@ 0x00000244) DSP1 Interrupt OR Mask A for IRQ63-32                      */

    struct {
      __IOM uint32_t DSP1TMRORMASKA : 10;       /*!< [9..0] DSP1 Timer Interrupt OR Mask A                                     */
            uint32_t            : 2;
      __IOM uint32_t DSP1I2SORMASKA : 4;        /*!< [15..12] DSP1 I2S Interrupt OR Mask A                                     */
      __IOM uint32_t DSP1PDMORMASKA : 4;        /*!< [19..16] DSP1 PDM Interrupt OR Mask A                                     */
            uint32_t            : 4;
      __IOM uint32_t DSP1GPIOORMASKA : 6;       /*!< [29..24] DSP1 GPIO Interrupt OR Mask A                                    */
            uint32_t            : 2;
    } DSP1INTORMASK63TO32A_b;
  } ;

  union {
    __IOM uint32_t DSP1INTORMASK95TO64A;        /*!< (@ 0x00000248) DSP1 Interrupt OR Mask A for IRQ95-64                      */

    struct {
      __IOM uint32_t DSP1MBINTORMASKA : 32;     /*!< [31..0] DSP1 Mailbox Interrupt OR Mask A                                  */
    } DSP1INTORMASK95TO64A_b;
  } ;
  __IM  uint32_t  RESERVED12;

  union {
    __IOM uint32_t DSP1INTORMASK31to0B;         /*!< (@ 0x00000250) DSP1 Interrupt OR Mask B for IRQ31-0                       */

    struct {
      __IOM uint32_t DSP1INTMCUIOORMASKB : 32;  /*!< [31..0] DSP1 MCU IO Interrupt OR Mask B                                   */
    } DSP1INTORMASK31to0B_b;
  } ;

  union {
    __IOM uint32_t DSP1INTORMASK63TO32B;        /*!< (@ 0x00000254) DSP1 Interrupt OR Mask A for IRQ63-32                      */

    struct {
      __IOM uint32_t DSP1TMRORMASKB : 10;       /*!< [9..0] DSP1 Timer Interrupt OR Mask B                                     */
            uint32_t            : 2;
      __IOM uint32_t DSP1I2SORMASKB : 4;        /*!< [15..12] DSP1 I2S Interrupt OR Mask B                                     */
      __IOM uint32_t DSP1PDMORMASKB : 4;        /*!< [19..16] DSP1 PDM Interrupt OR Mask B                                     */
            uint32_t            : 4;
      __IOM uint32_t DSP1GPIOORMASKB : 6;       /*!< [29..24] DSP1 GPIO Interrupt OR Mask B                                    */
            uint32_t            : 2;
    } DSP1INTORMASK63TO32B_b;
  } ;

  union {
    __IOM uint32_t DSP1INTORMASK95TO64B;        /*!< (@ 0x00000258) DSP1 Interrupt OR Mask B for IRQ95-64                      */

    struct {
      __IOM uint32_t DSP1MBINTORMASKB : 32;     /*!< [31..0] DSP1 Mailbox Interrupt OR Mask B                                  */
    } DSP1INTORMASK95TO64B_b;
  } ;
  __IM  uint32_t  RESERVED13;

  union {
    __IOM uint32_t DSP1INTENIRQ31TO0;           /*!< (@ 0x00000260) DSP1 INT Enable for IRQ31-0                                */

    struct {
      __IOM uint32_t DSP1INTENIRQ31TO0 : 32;    /*!< [31..0] DSP1 INT Enable for IRQ31-0                                       */
    } DSP1INTENIRQ31TO0_b;
  } ;

  union {
    __IOM uint32_t DSP1INTENIRQ63TO32;          /*!< (@ 0x00000264) DSP1 INT Enable for IRQ63-32                               */

    struct {
      __IOM uint32_t DSP1INTENIRQ63TO32 : 32;   /*!< [31..0] DSP1 INT Enable for IRQ63-32                                      */
    } DSP1INTENIRQ63TO32_b;
  } ;

  union {
    __IOM uint32_t DSP1INTENIRQ95TO64;          /*!< (@ 0x00000268) DSP1 INT Enable for IRQ95-64                               */

    struct {
      __IOM uint32_t DSP1INTENIRQ95TO64 : 32;   /*!< [31..0] DSP1 INT Enable for IRQ95-64                                      */
    } DSP1INTENIRQ95TO64_b;
  } ;
} DSP_Type;                                     /*!< Size = 620 (0x26c)                                                        */



/* =========================================================================================================================== */
/* ================                                           FPIO                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Fast PIO access (FPIO)
  */

typedef struct {                                /*!< (@ 0x48001000) FPIO Structure                                             */

  union {
    __IOM uint32_t RD0;                         /*!< (@ 0x00000000) GPIO Input 0 (31-0)                                        */

    struct {
      __IOM uint32_t RD0        : 32;           /*!< [31..0] GPIO31-0 Reads pin state - read only. Returns the pad
                                                     pin state for pins 0-31 if the PINCFG's input enable (INPEN)
                                                     is active and RDZERO is inactive.                                         */
    } RD0_b;
  } ;

  union {
    __IOM uint32_t RD1;                         /*!< (@ 0x00000004) GPIO Input 1 (63-32)                                       */

    struct {
      __IOM uint32_t RD1        : 32;           /*!< [31..0] GPIO63-32 Reads pin state - read only. Returns the pad
                                                     pin state for pins 0-31 if the PINCFG's input enable (INPEN)
                                                     is active and RDZERO is inactive.                                         */
    } RD1_b;
  } ;

  union {
    __IOM uint32_t RD2;                         /*!< (@ 0x00000008) GPIO Input 2 (95-64)                                       */

    struct {
      __IOM uint32_t RD2        : 32;           /*!< [31..0] GPIO95-64 Reads pin state - read only. Returns the pad
                                                     pin state for pins 0-31 if the PINCFG's input enable (INPEN)
                                                     is active and RDZERO is inactive.                                         */
    } RD2_b;
  } ;

  union {
    __IOM uint32_t RD3;                         /*!< (@ 0x0000000C) GPIO Input 3 (127-96)                                      */

    struct {
      __IOM uint32_t RD3        : 32;           /*!< [31..0] GPIO127-96 Reads pin state - read only. Returns the
                                                     pad pin state for pins 0-31 if the PINCFG's input enable
                                                     (INPEN) is active and RDZERO is inactive.                                 */
    } RD3_b;
  } ;

  union {
    __IOM uint32_t WT0;                         /*!< (@ 0x00000010) GPIO Output 0 (31-0)                                       */

    struct {
      __IOM uint32_t WT0        : 32;           /*!< [31..0] GPIO31-0 Reads or writes pin state. Writes of 1 bits
                                                     set output pad signal if the GPIO is enabled for output.
                                                     Reads return status, including sets/clears through the
                                                     WTS and WTC registers.                                                    */
    } WT0_b;
  } ;

  union {
    __IOM uint32_t WT1;                         /*!< (@ 0x00000014) GPIO Output 1 (63-32)                                      */

    struct {
      __IOM uint32_t WT1        : 32;           /*!< [31..0] GPIO63-32 Reads or writes pin state. Writes of 1 bits
                                                     set output pad signal if the GPIO is enabled for output.
                                                     Reads return status, including sets/clears through the
                                                     WTS and WTC registers.                                                    */
    } WT1_b;
  } ;

  union {
    __IOM uint32_t WT2;                         /*!< (@ 0x00000018) GPIO Output 2 (95-64)                                      */

    struct {
      __IOM uint32_t WT2        : 32;           /*!< [31..0] GPIO95-64 Reads or writes pin state. Writes of 1 bits
                                                     set output pad signal if the GPIO is enabled for output.
                                                     Reads return status, including sets/clears through the
                                                     WTS and WTC registers.                                                    */
    } WT2_b;
  } ;

  union {
    __IOM uint32_t WT3;                         /*!< (@ 0x0000001C) GPIO Output 3 (127-96)                                     */

    struct {
      __IOM uint32_t WT3        : 32;           /*!< [31..0] GPIO127-96 Reads or writes pin state. Writes of 1 bits
                                                     set output pad signal if the GPIO is enabled for output.
                                                     Reads return status, including sets/clears through the
                                                     WTS and WTC registers.                                                    */
    } WT3_b;
  } ;

  union {
    __IOM uint32_t WTS0;                        /*!< (@ 0x00000020) GPIO Output Set 0 (31-0)                                   */

    struct {
      __IOM uint32_t WTS0       : 32;           /*!< [31..0] GPIO31-0 Sets pin state. Writing a 1 to any bit sets
                                                     the corresponding bit in the WT register if the GPIO is
                                                     enabled for output. Writing a value of 0 has no effect
                                                     on the corresponding bit in the WT register. Status reads
                                                     should be made via the WT Register.                                       */
    } WTS0_b;
  } ;

  union {
    __IOM uint32_t WTS1;                        /*!< (@ 0x00000024) GPIO Output Set 1 (63-32)                                  */

    struct {
      __IOM uint32_t WTS1       : 32;           /*!< [31..0] GPIO63-32 Sets pin state. Writing a 1 to any bit sets
                                                     the corresponding bit in the WT register if the GPIO is
                                                     enabled for output. Writing a value of 0 has no effect
                                                     on the corresponding bit in the WT register. Status reads
                                                     should be made via the WT Register.                                       */
    } WTS1_b;
  } ;

  union {
    __IOM uint32_t WTS2;                        /*!< (@ 0x00000028) GPIO Output Set 2 (95-64)                                  */

    struct {
      __IOM uint32_t WTS2       : 32;           /*!< [31..0] GPIO95-64 Sets pin state. Writing a 1 to any bit sets
                                                     the corresponding bit in the WT register if the GPIO is
                                                     enabled for output. Writing a value of 0 has no effect
                                                     on the corresponding bit in the WT register. Status reads
                                                     should be made via the WT Register.                                       */
    } WTS2_b;
  } ;

  union {
    __IOM uint32_t WTS3;                        /*!< (@ 0x0000002C) GPIO Output Set 3 (127-96)                                 */

    struct {
      __IOM uint32_t WTS3       : 32;           /*!< [31..0] GPIO127-96 Sets pin state. Writing a 1 to any bit sets
                                                     the corresponding bit in the WT register if the GPIO is
                                                     enabled for output. Writing a value of 0 has no effect
                                                     on the corresponding bit in the WT register. Status reads
                                                     should be made via the WT Register.                                       */
    } WTS3_b;
  } ;

  union {
    __IOM uint32_t WTC0;                        /*!< (@ 0x00000030) GPIO Output Clear 0 (31-0)                                 */

    struct {
      __IOM uint32_t WTC0       : 32;           /*!< [31..0] GPIO31-0 Clears pin state. Writing a 1 to any bit clears
                                                     the corresponding bit in the WT register if the GPIO is
                                                     enabled for output. Writing a value of 0 has no effect
                                                     on the corresponding bit in the WT register. Status reads
                                                     should be made via the WT register.                                       */
    } WTC0_b;
  } ;

  union {
    __IOM uint32_t WTC1;                        /*!< (@ 0x00000034) GPIO Output Clear 1 (63-32)                                */

    struct {
      __IOM uint32_t WTC1       : 32;           /*!< [31..0] GPIO63-32 Clears pin state. Writing a 1 to any bit clears
                                                     the corresponding bit in the WT register if the GPIO is
                                                     enabled for output. Writing a value of 0 has no effect
                                                     on the corresponding bit in the WT register. Status reads
                                                     should be made via the WT register.                                       */
    } WTC1_b;
  } ;

  union {
    __IOM uint32_t WTC2;                        /*!< (@ 0x00000038) GPIO Output Clear 2 (95-64)                                */

    struct {
      __IOM uint32_t WTC2       : 32;           /*!< [31..0] GPIO95-64 Clears pin state. Writing a 1 to any bit clears
                                                     the corresponding bit in the WT register if the GPIO is
                                                     enabled for output. Writing a value of 0 has no effect
                                                     on the corresponding bit in the WT register. Status reads
                                                     should be made via the WT register.                                       */
    } WTC2_b;
  } ;

  union {
    __IOM uint32_t WTC3;                        /*!< (@ 0x0000003C) GPIO Output Clear 3 (127-96)                               */

    struct {
      __IOM uint32_t WTC3       : 32;           /*!< [31..0] GPIO127-96 Clears pin state. Writing a 1 to any bit
                                                     clears the corresponding bit in the WT register if the
                                                     GPIO is enabled for output. Writing a value of 0 has no
                                                     effect on the corresponding bit in the WT register. Status
                                                     reads should be made via the WT register.                                 */
    } WTC3_b;
  } ;

  union {
    __IOM uint32_t EN0;                         /*!< (@ 0x00000040) GPIO Enable 0 (31-0)                                       */

    struct {
      __IOM uint32_t EN0        : 32;           /*!< [31..0] GPIO31-0 Enables tri-state pin output. Writing a 1 to
                                                     any bit enables, and writing a 0 to any bit disables, the
                                                     output for the corresponding GPIO. Reads return output
                                                     enable/disable status of GPIO.                                            */
    } EN0_b;
  } ;

  union {
    __IOM uint32_t EN1;                         /*!< (@ 0x00000044) GPIO Enable 1 (63-32)                                      */

    struct {
      __IOM uint32_t EN1        : 32;           /*!< [31..0] GPIO63-32 Enables tri-state pin output. Writing a 1
                                                     to any bit enables, and writing a 0 to any bit disables,
                                                     the output for the corresponding GPIO. Reads return output
                                                     enable/disable status of GPIO.                                            */
    } EN1_b;
  } ;

  union {
    __IOM uint32_t EN2;                         /*!< (@ 0x00000048) GPIO Enable 2 (95-64)                                      */

    struct {
      __IOM uint32_t EN2        : 32;           /*!< [31..0] GPIO95-64 Enables tri-state pin output. Writing a 1
                                                     to any bit enables, and writing a 0 to any bit disables,
                                                     the output for the corresponding GPIO. Reads return output
                                                     enable/disable status of GPIO.                                            */
    } EN2_b;
  } ;

  union {
    __IOM uint32_t EN3;                         /*!< (@ 0x0000004C) GPIO Enable 3 (127-96)                                     */

    struct {
      __IOM uint32_t EN3        : 32;           /*!< [31..0] GPIO127-96 Enables tri-state pin output. Writing a 1
                                                     to any bit enables, and writing a 0 to any bit disables,
                                                     the output for the corresponding GPIO. Reads return output
                                                     enable/disable status of GPIO.                                            */
    } EN3_b;
  } ;

  union {
    __IOM uint32_t ENS0;                        /*!< (@ 0x00000050) GPIO Enable Set 0 (31-0)                                   */

    struct {
      __IOM uint32_t ENS0       : 32;           /*!< [31..0] GPIO31-0 Sets pin tri-state output enables. Writing
                                                     a 1 to any bit sets the corresponding bit in the EN register.
                                                     Writing a value of 0 has no effect on the corresponding
                                                     bit in the EN register. Status reads should be made to
                                                     the EN Register.                                                          */
    } ENS0_b;
  } ;

  union {
    __IOM uint32_t ENS1;                        /*!< (@ 0x00000054) GPIO Enable Set 1 (63-32)                                  */

    struct {
      __IOM uint32_t ENS1       : 32;           /*!< [31..0] GPIO63-32 Sets pin tri-state output enables. Writing
                                                     a 1 to any bit sets the corresponding bit in the EN register.
                                                     Writing a value of 0 has no effect on the corresponding
                                                     bit in the EN register. Status reads should be made to
                                                     the EN Register.                                                          */
    } ENS1_b;
  } ;

  union {
    __IOM uint32_t ENS2;                        /*!< (@ 0x00000058) GPIO Enable Set 2 (95-64)                                  */

    struct {
      __IOM uint32_t ENS2       : 32;           /*!< [31..0] GPIO95-64 Sets pin tri-state output enables. Writing
                                                     a 1 to any bit sets the corresponding bit in the EN register.
                                                     Writing a value of 0 has no effect on the corresponding
                                                     bit in the EN register. Status reads should be made to
                                                     the EN Register.                                                          */
    } ENS2_b;
  } ;

  union {
    __IOM uint32_t ENS3;                        /*!< (@ 0x0000005C) GPIO Enable Set 3 (127-96)                                 */

    struct {
      __IOM uint32_t ENS3       : 32;           /*!< [31..0] GPIO127-96 Sets pin tri-state output enables. Writing
                                                     a 1 to any bit sets the corresponding bit in the EN register.
                                                     Writing a value of 0 has no effect on the corresponding
                                                     bit in the EN register. Status reads should be made to
                                                     the EN Register.                                                          */
    } ENS3_b;
  } ;

  union {
    __IOM uint32_t ENC0;                        /*!< (@ 0x00000060) GPIO Enable Clear 0 (31-0)                                 */

    struct {
      __IOM uint32_t ENC0       : 32;           /*!< [31..0] GPIO31-0 Clears pin tri-state output enables. Writing
                                                     a 1 to any bit clears the corresponding bit in the EN register.
                                                     Writing a value of 0 has no effect on the corresponding
                                                     bit in the EN register. Status reads should be made to
                                                     the EN Register.                                                          */
    } ENC0_b;
  } ;

  union {
    __IOM uint32_t ENC1;                        /*!< (@ 0x00000064) GPIO Enable Clear 1 (63-32)                                */

    struct {
      __IOM uint32_t ENC1       : 32;           /*!< [31..0] GPIO63-32 Clears pin tri-state output enables. Writing
                                                     a 1 to any bit clears the corresponding bit in the EN register.
                                                     Writing a value of 0 has no effect on the corresponding
                                                     bit in the EN register. Status reads should be made to
                                                     the EN Register.                                                          */
    } ENC1_b;
  } ;

  union {
    __IOM uint32_t ENC2;                        /*!< (@ 0x00000068) GPIO Enable Clear 2 (95-64)                                */

    struct {
      __IOM uint32_t ENC2       : 32;           /*!< [31..0] GPIO95-64 Clears pin tri-state output enables. Writing
                                                     a 1 to any bit clears the corresponding bit in the EN register.
                                                     Writing a value of 0 has no effect on the corresponding
                                                     bit in the EN register. Status reads should be made to
                                                     the EN Register.                                                          */
    } ENC2_b;
  } ;

  union {
    __IOM uint32_t ENC3;                        /*!< (@ 0x0000006C) GPIO Enable Clear 3 (127-96)                               */

    struct {
      __IOM uint32_t ENC3       : 32;           /*!< [31..0] GPIO127-96 Clears pin tri-state output enables. Writing
                                                     a 1 to any bit clears the corresponding bit in the EN register.
                                                     Writing a value of 0 has no effect on the corresponding
                                                     bit in the EN register. Status reads should be made to
                                                     the EN Register.                                                          */
    } ENC3_b;
  } ;
} FPIO_Type;                                    /*!< Size = 112 (0x70)                                                         */



/* =========================================================================================================================== */
/* ================                                           GPIO                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief General Purpose IO (GPIO)
  */

typedef struct {                                /*!< (@ 0x40010000) GPIO Structure                                             */

  union {
    __IOM uint32_t PINCFG0;                     /*!< (@ 0x00000000) Controls the operation of GPIO pin 0.                      */

    struct {
      __IOM uint32_t FNCSEL0    : 4;            /*!< [3..0] Function select for GPIO pin 0                                     */
      __IOM uint32_t INPEN0     : 1;            /*!< [4..4] Input enable for GPIO 0                                            */
      __IOM uint32_t RDZERO0    : 1;            /*!< [5..5] Return 0 for read data on GPIO 0                                   */
      __IOM uint32_t IRPTEN0    : 2;            /*!< [7..6] Interrupt enable for GPIO 0                                        */
      __IOM uint32_t OUTCFG0    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 0                               */
      __IOM uint32_t DS0        : 2;            /*!< [11..10] Drive strength selection for GPIO 0                              */
      __IOM uint32_t SR0        : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG0   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 0                         */
      __IOM uint32_t NCESRC0    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 0, DISP control signals DE,
                                                     CSX, and CS. Polarity is determined by CE_POLARITY field                  */
      __IOM uint32_t NCEPOL0    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 0                               */
            uint32_t            : 3;
      __IOM uint32_t FIEN0      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN0      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG0_b;
  } ;

  union {
    __IOM uint32_t PINCFG1;                     /*!< (@ 0x00000004) Controls the operation of GPIO pin 1.                      */

    struct {
      __IOM uint32_t FNCSEL1    : 4;            /*!< [3..0] Function select for GPIO pin 1                                     */
      __IOM uint32_t INPEN1     : 1;            /*!< [4..4] Input enable for GPIO 1                                            */
      __IOM uint32_t RDZERO1    : 1;            /*!< [5..5] Return 0 for read data on GPIO 1                                   */
      __IOM uint32_t IRPTEN1    : 2;            /*!< [7..6] Interrupt enable for GPIO 1                                        */
      __IOM uint32_t OUTCFG1    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 1                               */
      __IOM uint32_t DS1        : 2;            /*!< [11..10] Drive strength selection for GPIO 1                              */
      __IOM uint32_t SR1        : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG1   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 1                         */
      __IOM uint32_t NCESRC1    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 1, DISP control signals DE,
                                                     CSX, and CS. Polarity is determined by CE_POLARITY field                  */
      __IOM uint32_t NCEPOL1    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 1                               */
            uint32_t            : 3;
      __IOM uint32_t FIEN1      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN1      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG1_b;
  } ;

  union {
    __IOM uint32_t PINCFG2;                     /*!< (@ 0x00000008) Controls the operation of GPIO pin 2.                      */

    struct {
      __IOM uint32_t FNCSEL2    : 4;            /*!< [3..0] Function select for GPIO pin 2                                     */
      __IOM uint32_t INPEN2     : 1;            /*!< [4..4] Input enable for GPIO 2                                            */
      __IOM uint32_t RDZERO2    : 1;            /*!< [5..5] Return 0 for read data on GPIO 2                                   */
      __IOM uint32_t IRPTEN2    : 2;            /*!< [7..6] Interrupt enable for GPIO 2                                        */
      __IOM uint32_t OUTCFG2    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 2                               */
      __IOM uint32_t DS2        : 2;            /*!< [11..10] Drive strength selection for GPIO 2                              */
      __IOM uint32_t SR2        : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG2   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 2                         */
      __IOM uint32_t NCESRC2    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 2, DISP control signals DE,
                                                     CSX, and CS. Polarity is determined by CE_POLARITY field                  */
      __IOM uint32_t NCEPOL2    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 2                               */
            uint32_t            : 3;
      __IOM uint32_t FIEN2      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN2      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG2_b;
  } ;

  union {
    __IOM uint32_t PINCFG3;                     /*!< (@ 0x0000000C) Controls the operation of GPIO pin 3.                      */

    struct {
      __IOM uint32_t FNCSEL3    : 4;            /*!< [3..0] Function select for GPIO pin 3                                     */
      __IOM uint32_t INPEN3     : 1;            /*!< [4..4] Input enable for GPIO 3                                            */
      __IOM uint32_t RDZERO3    : 1;            /*!< [5..5] Return 0 for read data on GPIO 3                                   */
      __IOM uint32_t IRPTEN3    : 2;            /*!< [7..6] Interrupt enable for GPIO 3                                        */
      __IOM uint32_t OUTCFG3    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 3                               */
      __IOM uint32_t DS3        : 2;            /*!< [11..10] Drive strength selection for GPIO 3                              */
      __IOM uint32_t SR3        : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG3   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 3                         */
      __IOM uint32_t NCESRC3    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 3, DISP control signals DE,
                                                     CSX, and CS. Polarity is determined by CE_POLARITY field                  */
      __IOM uint32_t NCEPOL3    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 3                               */
            uint32_t            : 3;
      __IOM uint32_t FIEN3      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN3      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG3_b;
  } ;

  union {
    __IOM uint32_t PINCFG4;                     /*!< (@ 0x00000010) Controls the operation of GPIO pin 4.                      */

    struct {
      __IOM uint32_t FNCSEL4    : 4;            /*!< [3..0] Function select for GPIO pin 4                                     */
      __IOM uint32_t INPEN4     : 1;            /*!< [4..4] Input enable for GPIO 4                                            */
      __IOM uint32_t RDZERO4    : 1;            /*!< [5..5] Return 0 for read data on GPIO 4                                   */
      __IOM uint32_t IRPTEN4    : 2;            /*!< [7..6] Interrupt enable for GPIO 4                                        */
      __IOM uint32_t OUTCFG4    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 4                               */
      __IOM uint32_t DS4        : 2;            /*!< [11..10] Drive strength selection for GPIO 4                              */
      __IOM uint32_t SR4        : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG4   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 4                         */
      __IOM uint32_t NCESRC4    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 4, DISP control signals DE,
                                                     CSX, and CS. Polarity is determined by CE_POLARITY field                  */
      __IOM uint32_t NCEPOL4    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 4                               */
            uint32_t            : 3;
      __IOM uint32_t FIEN4      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN4      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG4_b;
  } ;

  union {
    __IOM uint32_t PINCFG5;                     /*!< (@ 0x00000014) Controls the operation of GPIO pin 5.                      */

    struct {
      __IOM uint32_t FNCSEL5    : 4;            /*!< [3..0] Function select for GPIO pin 5                                     */
      __IOM uint32_t INPEN5     : 1;            /*!< [4..4] Input enable for GPIO 5                                            */
      __IOM uint32_t RDZERO5    : 1;            /*!< [5..5] Return 0 for read data on GPIO 5                                   */
      __IOM uint32_t IRPTEN5    : 2;            /*!< [7..6] Interrupt enable for GPIO 5                                        */
      __IOM uint32_t OUTCFG5    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 5                               */
      __IOM uint32_t DS5        : 2;            /*!< [11..10] Drive strength selection for GPIO 5                              */
      __IOM uint32_t SR5        : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG5   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 5                         */
      __IOM uint32_t NCESRC5    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 5, DISP control signals DE,
                                                     CSX, and CS. Polarity is determined by CE_POLARITY field                  */
      __IOM uint32_t NCEPOL5    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 5                               */
            uint32_t            : 3;
      __IOM uint32_t FIEN5      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN5      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG5_b;
  } ;

  union {
    __IOM uint32_t PINCFG6;                     /*!< (@ 0x00000018) Controls the operation of GPIO pin 6.                      */

    struct {
      __IOM uint32_t FNCSEL6    : 4;            /*!< [3..0] Function select for GPIO pin 6                                     */
      __IOM uint32_t INPEN6     : 1;            /*!< [4..4] Input enable for GPIO 6                                            */
      __IOM uint32_t RDZERO6    : 1;            /*!< [5..5] Return 0 for read data on GPIO 6                                   */
      __IOM uint32_t IRPTEN6    : 2;            /*!< [7..6] Interrupt enable for GPIO 6                                        */
      __IOM uint32_t OUTCFG6    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 6                               */
      __IOM uint32_t DS6        : 2;            /*!< [11..10] Drive strength selection for GPIO 6                              */
      __IOM uint32_t SR6        : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG6   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 6                         */
      __IOM uint32_t NCESRC6    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 6, DISP control signals DE,
                                                     CSX, and CS. Polarity is determined by CE_POLARITY field                  */
      __IOM uint32_t NCEPOL6    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 6                               */
            uint32_t            : 3;
      __IOM uint32_t FIEN6      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN6      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG6_b;
  } ;

  union {
    __IOM uint32_t PINCFG7;                     /*!< (@ 0x0000001C) Controls the operation of GPIO pin 7.                      */

    struct {
      __IOM uint32_t FNCSEL7    : 4;            /*!< [3..0] Function select for GPIO pin 7                                     */
      __IOM uint32_t INPEN7     : 1;            /*!< [4..4] Input enable for GPIO 7                                            */
      __IOM uint32_t RDZERO7    : 1;            /*!< [5..5] Return 0 for read data on GPIO 7                                   */
      __IOM uint32_t IRPTEN7    : 2;            /*!< [7..6] Interrupt enable for GPIO 7                                        */
      __IOM uint32_t OUTCFG7    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 7                               */
      __IOM uint32_t DS7        : 2;            /*!< [11..10] Drive strength selection for GPIO 7                              */
      __IOM uint32_t SR7        : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG7   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 7                         */
      __IOM uint32_t NCESRC7    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 7, DISP control signals DE,
                                                     CSX, and CS. Polarity is determined by CE_POLARITY field                  */
      __IOM uint32_t NCEPOL7    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 7                               */
            uint32_t            : 3;
      __IOM uint32_t FIEN7      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN7      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG7_b;
  } ;

  union {
    __IOM uint32_t PINCFG8;                     /*!< (@ 0x00000020) Controls the operation of GPIO pin 8.                      */

    struct {
      __IOM uint32_t FNCSEL8    : 4;            /*!< [3..0] Function select for GPIO pin 8                                     */
      __IOM uint32_t INPEN8     : 1;            /*!< [4..4] Input enable for GPIO 8                                            */
      __IOM uint32_t RDZERO8    : 1;            /*!< [5..5] Return 0 for read data on GPIO 8                                   */
      __IOM uint32_t IRPTEN8    : 2;            /*!< [7..6] Interrupt enable for GPIO 8                                        */
      __IOM uint32_t OUTCFG8    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 8                               */
      __IOM uint32_t DS8        : 2;            /*!< [11..10] Drive strength selection for GPIO 8                              */
      __IOM uint32_t SR8        : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG8   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 8                         */
      __IOM uint32_t NCESRC8    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 8, DISP control signals DE,
                                                     CSX, and CS. Polarity is determined by CE_POLARITY field                  */
      __IOM uint32_t NCEPOL8    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 8                               */
            uint32_t            : 3;
      __IOM uint32_t FIEN8      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN8      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG8_b;
  } ;

  union {
    __IOM uint32_t PINCFG9;                     /*!< (@ 0x00000024) Controls the operation of GPIO pin 9.                      */

    struct {
      __IOM uint32_t FNCSEL9    : 4;            /*!< [3..0] Function select for GPIO pin 9                                     */
      __IOM uint32_t INPEN9     : 1;            /*!< [4..4] Input enable for GPIO 9                                            */
      __IOM uint32_t RDZERO9    : 1;            /*!< [5..5] Return 0 for read data on GPIO 9                                   */
      __IOM uint32_t IRPTEN9    : 2;            /*!< [7..6] Interrupt enable for GPIO 9                                        */
      __IOM uint32_t OUTCFG9    : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 9                               */
      __IOM uint32_t DS9        : 2;            /*!< [11..10] Drive strength selection for GPIO 9                              */
      __IOM uint32_t SR9        : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG9   : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 9                         */
      __IOM uint32_t NCESRC9    : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 9, DISP control signals DE,
                                                     CSX, and CS. Polarity is determined by CE_POLARITY field                  */
      __IOM uint32_t NCEPOL9    : 1;            /*!< [22..22] Polarity select for NCE for GPIO 9                               */
            uint32_t            : 3;
      __IOM uint32_t FIEN9      : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN9      : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG9_b;
  } ;

  union {
    __IOM uint32_t PINCFG10;                    /*!< (@ 0x00000028) Controls the operation of GPIO pin 10.                     */

    struct {
      __IOM uint32_t FNCSEL10   : 4;            /*!< [3..0] Function select for GPIO pin 10                                    */
      __IOM uint32_t INPEN10    : 1;            /*!< [4..4] Input enable for GPIO 10                                           */
      __IOM uint32_t RDZERO10   : 1;            /*!< [5..5] Return 0 for read data on GPIO 10                                  */
      __IOM uint32_t IRPTEN10   : 2;            /*!< [7..6] Interrupt enable for GPIO 10                                       */
      __IOM uint32_t OUTCFG10   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 10                              */
      __IOM uint32_t DS10       : 2;            /*!< [11..10] Drive strength selection for GPIO 10                             */
      __IOM uint32_t SR10       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG10  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 10                        */
      __IOM uint32_t NCESRC10   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 10, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL10   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 10                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN10     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN10     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG10_b;
  } ;

  union {
    __IOM uint32_t PINCFG11;                    /*!< (@ 0x0000002C) Controls the operation of GPIO pin 11.                     */

    struct {
      __IOM uint32_t FNCSEL11   : 4;            /*!< [3..0] Function select for GPIO pin 11                                    */
      __IOM uint32_t INPEN11    : 1;            /*!< [4..4] Input enable for GPIO 11                                           */
      __IOM uint32_t RDZERO11   : 1;            /*!< [5..5] Return 0 for read data on GPIO 11                                  */
      __IOM uint32_t IRPTEN11   : 2;            /*!< [7..6] Interrupt enable for GPIO 11                                       */
      __IOM uint32_t OUTCFG11   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 11                              */
      __IOM uint32_t DS11       : 2;            /*!< [11..10] Drive strength selection for GPIO 11                             */
      __IOM uint32_t SR11       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG11  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 11                        */
      __IOM uint32_t NCESRC11   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 11, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL11   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 11                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN11     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN11     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG11_b;
  } ;

  union {
    __IOM uint32_t PINCFG12;                    /*!< (@ 0x00000030) Controls the operation of GPIO pin 12.                     */

    struct {
      __IOM uint32_t FNCSEL12   : 4;            /*!< [3..0] Function select for GPIO pin 12                                    */
      __IOM uint32_t INPEN12    : 1;            /*!< [4..4] Input enable for GPIO 12                                           */
      __IOM uint32_t RDZERO12   : 1;            /*!< [5..5] Return 0 for read data on GPIO 12                                  */
      __IOM uint32_t IRPTEN12   : 2;            /*!< [7..6] Interrupt enable for GPIO 12                                       */
      __IOM uint32_t OUTCFG12   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 12                              */
      __IOM uint32_t DS12       : 2;            /*!< [11..10] Drive strength selection for GPIO 12                             */
      __IOM uint32_t SR12       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG12  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 12                        */
      __IOM uint32_t NCESRC12   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 12, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL12   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 12                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN12     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN12     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG12_b;
  } ;

  union {
    __IOM uint32_t PINCFG13;                    /*!< (@ 0x00000034) Controls the operation of GPIO pin 13.                     */

    struct {
      __IOM uint32_t FNCSEL13   : 4;            /*!< [3..0] Function select for GPIO pin 13                                    */
      __IOM uint32_t INPEN13    : 1;            /*!< [4..4] Input enable for GPIO 13                                           */
      __IOM uint32_t RDZERO13   : 1;            /*!< [5..5] Return 0 for read data on GPIO 13                                  */
      __IOM uint32_t IRPTEN13   : 2;            /*!< [7..6] Interrupt enable for GPIO 13                                       */
      __IOM uint32_t OUTCFG13   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 13                              */
      __IOM uint32_t DS13       : 2;            /*!< [11..10] Drive strength selection for GPIO 13                             */
      __IOM uint32_t SR13       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG13  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 13                        */
      __IOM uint32_t NCESRC13   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 13, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL13   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 13                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN13     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN13     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG13_b;
  } ;

  union {
    __IOM uint32_t PINCFG14;                    /*!< (@ 0x00000038) Controls the operation of GPIO pin 14.                     */

    struct {
      __IOM uint32_t FNCSEL14   : 4;            /*!< [3..0] Function select for GPIO pin 14                                    */
      __IOM uint32_t INPEN14    : 1;            /*!< [4..4] Input enable for GPIO 14                                           */
      __IOM uint32_t RDZERO14   : 1;            /*!< [5..5] Return 0 for read data on GPIO 14                                  */
      __IOM uint32_t IRPTEN14   : 2;            /*!< [7..6] Interrupt enable for GPIO 14                                       */
      __IOM uint32_t OUTCFG14   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 14                              */
      __IOM uint32_t DS14       : 2;            /*!< [11..10] Drive strength selection for GPIO 14                             */
      __IOM uint32_t SR14       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG14  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 14                        */
      __IOM uint32_t NCESRC14   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 14, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL14   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 14                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN14     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN14     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG14_b;
  } ;

  union {
    __IOM uint32_t PINCFG15;                    /*!< (@ 0x0000003C) Controls the operation of GPIO pin 15.                     */

    struct {
      __IOM uint32_t FNCSEL15   : 4;            /*!< [3..0] Function select for GPIO pin 15                                    */
      __IOM uint32_t INPEN15    : 1;            /*!< [4..4] Input enable for GPIO 15                                           */
      __IOM uint32_t RDZERO15   : 1;            /*!< [5..5] Return 0 for read data on GPIO 15                                  */
      __IOM uint32_t IRPTEN15   : 2;            /*!< [7..6] Interrupt enable for GPIO 15                                       */
      __IOM uint32_t OUTCFG15   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 15                              */
      __IOM uint32_t DS15       : 2;            /*!< [11..10] Drive strength selection for GPIO 15                             */
      __IOM uint32_t SR15       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG15  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 15                        */
      __IOM uint32_t NCESRC15   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 15, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL15   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 15                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN15     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN15     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG15_b;
  } ;

  union {
    __IOM uint32_t PINCFG16;                    /*!< (@ 0x00000040) Controls the operation of GPIO pin 16.                     */

    struct {
      __IOM uint32_t FNCSEL16   : 4;            /*!< [3..0] Function select for GPIO pin 16                                    */
      __IOM uint32_t INPEN16    : 1;            /*!< [4..4] Input enable for GPIO 16                                           */
      __IOM uint32_t RDZERO16   : 1;            /*!< [5..5] Return 0 for read data on GPIO 16                                  */
      __IOM uint32_t IRPTEN16   : 2;            /*!< [7..6] Interrupt enable for GPIO 16                                       */
      __IOM uint32_t OUTCFG16   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 16                              */
      __IOM uint32_t DS16       : 2;            /*!< [11..10] Drive strength selection for GPIO 16                             */
      __IOM uint32_t SR16       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG16  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 16                        */
      __IOM uint32_t NCESRC16   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 16, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL16   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 16                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN16     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN16     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG16_b;
  } ;

  union {
    __IOM uint32_t PINCFG17;                    /*!< (@ 0x00000044) Controls the operation of GPIO pin 17.                     */

    struct {
      __IOM uint32_t FNCSEL17   : 4;            /*!< [3..0] Function select for GPIO pin 17                                    */
      __IOM uint32_t INPEN17    : 1;            /*!< [4..4] Input enable for GPIO 17                                           */
      __IOM uint32_t RDZERO17   : 1;            /*!< [5..5] Return 0 for read data on GPIO 17                                  */
      __IOM uint32_t IRPTEN17   : 2;            /*!< [7..6] Interrupt enable for GPIO 17                                       */
      __IOM uint32_t OUTCFG17   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 17                              */
      __IOM uint32_t DS17       : 2;            /*!< [11..10] Drive strength selection for GPIO 17                             */
      __IOM uint32_t SR17       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG17  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 17                        */
      __IOM uint32_t NCESRC17   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 17, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL17   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 17                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN17     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN17     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG17_b;
  } ;

  union {
    __IOM uint32_t PINCFG18;                    /*!< (@ 0x00000048) Controls the operation of GPIO pin 18.                     */

    struct {
      __IOM uint32_t FNCSEL18   : 4;            /*!< [3..0] Function select for GPIO pin 18                                    */
      __IOM uint32_t INPEN18    : 1;            /*!< [4..4] Input enable for GPIO 18                                           */
      __IOM uint32_t RDZERO18   : 1;            /*!< [5..5] Return 0 for read data on GPIO 18                                  */
      __IOM uint32_t IRPTEN18   : 2;            /*!< [7..6] Interrupt enable for GPIO 18                                       */
      __IOM uint32_t OUTCFG18   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 18                              */
      __IOM uint32_t DS18       : 2;            /*!< [11..10] Drive strength selection for GPIO 18                             */
      __IOM uint32_t SR18       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG18  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 18                        */
      __IOM uint32_t NCESRC18   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 18, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL18   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 18                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN18     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN18     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG18_b;
  } ;

  union {
    __IOM uint32_t PINCFG19;                    /*!< (@ 0x0000004C) Controls the operation of GPIO pin 19.                     */

    struct {
      __IOM uint32_t FNCSEL19   : 4;            /*!< [3..0] Function select for GPIO pin 19                                    */
      __IOM uint32_t INPEN19    : 1;            /*!< [4..4] Input enable for GPIO 19                                           */
      __IOM uint32_t RDZERO19   : 1;            /*!< [5..5] Return 0 for read data on GPIO 19                                  */
      __IOM uint32_t IRPTEN19   : 2;            /*!< [7..6] Interrupt enable for GPIO 19                                       */
      __IOM uint32_t OUTCFG19   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 19                              */
      __IOM uint32_t DS19       : 2;            /*!< [11..10] Drive strength selection for GPIO 19                             */
      __IOM uint32_t SR19       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG19  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 19                        */
      __IOM uint32_t NCESRC19   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 19, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL19   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 19                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN19     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN19     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG19_b;
  } ;

  union {
    __IOM uint32_t PINCFG20;                    /*!< (@ 0x00000050) Controls the operation of GPIO pin 20.                     */

    struct {
      __IOM uint32_t FNCSEL20   : 4;            /*!< [3..0] Function select for GPIO pin 20                                    */
      __IOM uint32_t INPEN20    : 1;            /*!< [4..4] Input enable for GPIO 20                                           */
      __IOM uint32_t RDZERO20   : 1;            /*!< [5..5] Return 0 for read data on GPIO 20                                  */
      __IOM uint32_t IRPTEN20   : 2;            /*!< [7..6] Interrupt enable for GPIO 20                                       */
      __IOM uint32_t OUTCFG20   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 20                              */
      __IOM uint32_t DS20       : 2;            /*!< [11..10] Drive strength selection for GPIO 20                             */
      __IOM uint32_t SR20       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG20  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 20                        */
      __IOM uint32_t NCESRC20   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 20, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL20   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 20                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN20     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN20     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG20_b;
  } ;

  union {
    __IOM uint32_t PINCFG21;                    /*!< (@ 0x00000054) Controls the operation of GPIO pin 21.                     */

    struct {
      __IOM uint32_t FNCSEL21   : 4;            /*!< [3..0] Function select for GPIO pin 21                                    */
      __IOM uint32_t INPEN21    : 1;            /*!< [4..4] Input enable for GPIO 21                                           */
      __IOM uint32_t RDZERO21   : 1;            /*!< [5..5] Return 0 for read data on GPIO 21                                  */
      __IOM uint32_t IRPTEN21   : 2;            /*!< [7..6] Interrupt enable for GPIO 21                                       */
      __IOM uint32_t OUTCFG21   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 21                              */
      __IOM uint32_t DS21       : 2;            /*!< [11..10] Drive strength selection for GPIO 21                             */
      __IOM uint32_t SR21       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG21  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 21                        */
      __IOM uint32_t NCESRC21   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 21, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL21   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 21                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN21     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN21     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG21_b;
  } ;

  union {
    __IOM uint32_t PINCFG22;                    /*!< (@ 0x00000058) Controls the operation of GPIO pin 22.                     */

    struct {
      __IOM uint32_t FNCSEL22   : 4;            /*!< [3..0] Function select for GPIO pin 22                                    */
      __IOM uint32_t INPEN22    : 1;            /*!< [4..4] Input enable for GPIO 22                                           */
      __IOM uint32_t RDZERO22   : 1;            /*!< [5..5] Return 0 for read data on GPIO 22                                  */
      __IOM uint32_t IRPTEN22   : 2;            /*!< [7..6] Interrupt enable for GPIO 22                                       */
      __IOM uint32_t OUTCFG22   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 22                              */
      __IOM uint32_t DS22       : 2;            /*!< [11..10] Drive strength selection for GPIO 22                             */
      __IOM uint32_t SR22       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG22  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 22                        */
      __IOM uint32_t NCESRC22   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 22, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL22   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 22                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN22     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN22     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG22_b;
  } ;

  union {
    __IOM uint32_t PINCFG23;                    /*!< (@ 0x0000005C) Controls the operation of GPIO pin 23.                     */

    struct {
      __IOM uint32_t FNCSEL23   : 4;            /*!< [3..0] Function select for GPIO pin 23                                    */
      __IOM uint32_t INPEN23    : 1;            /*!< [4..4] Input enable for GPIO 23                                           */
      __IOM uint32_t RDZERO23   : 1;            /*!< [5..5] Return 0 for read data on GPIO 23                                  */
      __IOM uint32_t IRPTEN23   : 2;            /*!< [7..6] Interrupt enable for GPIO 23                                       */
      __IOM uint32_t OUTCFG23   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 23                              */
      __IOM uint32_t DS23       : 2;            /*!< [11..10] Drive strength selection for GPIO 23                             */
      __IOM uint32_t SR23       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG23  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 23                        */
      __IOM uint32_t NCESRC23   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 23, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL23   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 23                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN23     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN23     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG23_b;
  } ;

  union {
    __IOM uint32_t PINCFG24;                    /*!< (@ 0x00000060) Controls the operation of GPIO pin 24.                     */

    struct {
      __IOM uint32_t FNCSEL24   : 4;            /*!< [3..0] Function select for GPIO pin 24                                    */
      __IOM uint32_t INPEN24    : 1;            /*!< [4..4] Input enable for GPIO 24                                           */
      __IOM uint32_t RDZERO24   : 1;            /*!< [5..5] Return 0 for read data on GPIO 24                                  */
      __IOM uint32_t IRPTEN24   : 2;            /*!< [7..6] Interrupt enable for GPIO 24                                       */
      __IOM uint32_t OUTCFG24   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 24                              */
      __IOM uint32_t DS24       : 2;            /*!< [11..10] Drive strength selection for GPIO 24                             */
      __IOM uint32_t SR24       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG24  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 24                        */
      __IOM uint32_t NCESRC24   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 24, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL24   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 24                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN24     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN24     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG24_b;
  } ;

  union {
    __IOM uint32_t PINCFG25;                    /*!< (@ 0x00000064) Controls the operation of GPIO pin 25.                     */

    struct {
      __IOM uint32_t FNCSEL25   : 4;            /*!< [3..0] Function select for GPIO pin 25                                    */
      __IOM uint32_t INPEN25    : 1;            /*!< [4..4] Input enable for GPIO 25                                           */
      __IOM uint32_t RDZERO25   : 1;            /*!< [5..5] Return 0 for read data on GPIO 25                                  */
      __IOM uint32_t IRPTEN25   : 2;            /*!< [7..6] Interrupt enable for GPIO 25                                       */
      __IOM uint32_t OUTCFG25   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 25                              */
      __IOM uint32_t DS25       : 2;            /*!< [11..10] Drive strength selection for GPIO 25                             */
      __IOM uint32_t SR25       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG25  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 25                        */
      __IOM uint32_t NCESRC25   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 25, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL25   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 25                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN25     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN25     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG25_b;
  } ;

  union {
    __IOM uint32_t PINCFG26;                    /*!< (@ 0x00000068) Controls the operation of GPIO pin 26.                     */

    struct {
      __IOM uint32_t FNCSEL26   : 4;            /*!< [3..0] Function select for GPIO pin 26                                    */
      __IOM uint32_t INPEN26    : 1;            /*!< [4..4] Input enable for GPIO 26                                           */
      __IOM uint32_t RDZERO26   : 1;            /*!< [5..5] Return 0 for read data on GPIO 26                                  */
      __IOM uint32_t IRPTEN26   : 2;            /*!< [7..6] Interrupt enable for GPIO 26                                       */
      __IOM uint32_t OUTCFG26   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 26                              */
      __IOM uint32_t DS26       : 2;            /*!< [11..10] Drive strength selection for GPIO 26                             */
      __IOM uint32_t SR26       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG26  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 26                        */
      __IOM uint32_t NCESRC26   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 26, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL26   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 26                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN26     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN26     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG26_b;
  } ;

  union {
    __IOM uint32_t PINCFG27;                    /*!< (@ 0x0000006C) Controls the operation of GPIO pin 27.                     */

    struct {
      __IOM uint32_t FNCSEL27   : 4;            /*!< [3..0] Function select for GPIO pin 27                                    */
      __IOM uint32_t INPEN27    : 1;            /*!< [4..4] Input enable for GPIO 27                                           */
      __IOM uint32_t RDZERO27   : 1;            /*!< [5..5] Return 0 for read data on GPIO 27                                  */
      __IOM uint32_t IRPTEN27   : 2;            /*!< [7..6] Interrupt enable for GPIO 27                                       */
      __IOM uint32_t OUTCFG27   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 27                              */
      __IOM uint32_t DS27       : 2;            /*!< [11..10] Drive strength selection for GPIO 27                             */
      __IOM uint32_t SR27       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG27  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 27                        */
      __IOM uint32_t NCESRC27   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 27, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL27   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 27                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN27     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN27     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG27_b;
  } ;

  union {
    __IOM uint32_t PINCFG28;                    /*!< (@ 0x00000070) Controls the operation of GPIO pin 28.                     */

    struct {
      __IOM uint32_t FNCSEL28   : 4;            /*!< [3..0] Function select for GPIO pin 28                                    */
      __IOM uint32_t INPEN28    : 1;            /*!< [4..4] Input enable for GPIO 28                                           */
      __IOM uint32_t RDZERO28   : 1;            /*!< [5..5] Return 0 for read data on GPIO 28                                  */
      __IOM uint32_t IRPTEN28   : 2;            /*!< [7..6] Interrupt enable for GPIO 28                                       */
      __IOM uint32_t OUTCFG28   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 28                              */
      __IOM uint32_t DS28       : 2;            /*!< [11..10] Drive strength selection for GPIO 28                             */
      __IOM uint32_t SR28       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG28  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 28                        */
      __IOM uint32_t NCESRC28   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 28, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL28   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 28                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN28     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN28     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG28_b;
  } ;

  union {
    __IOM uint32_t PINCFG29;                    /*!< (@ 0x00000074) Controls the operation of GPIO pin 29.                     */

    struct {
      __IOM uint32_t FNCSEL29   : 4;            /*!< [3..0] Function select for GPIO pin 29                                    */
      __IOM uint32_t INPEN29    : 1;            /*!< [4..4] Input enable for GPIO 29                                           */
      __IOM uint32_t RDZERO29   : 1;            /*!< [5..5] Return 0 for read data on GPIO 29                                  */
      __IOM uint32_t IRPTEN29   : 2;            /*!< [7..6] Interrupt enable for GPIO 29                                       */
      __IOM uint32_t OUTCFG29   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 29                              */
      __IOM uint32_t DS29       : 2;            /*!< [11..10] Drive strength selection for GPIO 29                             */
      __IOM uint32_t SR29       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG29  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 29                        */
      __IOM uint32_t NCESRC29   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 29, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL29   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 29                              */
            uint32_t            : 2;
      __IOM uint32_t VSSPWRSWEN29 : 1;          /*!< [25..25] VSS power switch enable. Enable VSS power switch when
                                                     driving pad signal to 0 for GPIO 29                                       */
      __IOM uint32_t FIEN29     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN29     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG29_b;
  } ;

  union {
    __IOM uint32_t PINCFG30;                    /*!< (@ 0x00000078) Controls the operation of GPIO pin 30.                     */

    struct {
      __IOM uint32_t FNCSEL30   : 4;            /*!< [3..0] Function select for GPIO pin 30                                    */
      __IOM uint32_t INPEN30    : 1;            /*!< [4..4] Input enable for GPIO 30                                           */
      __IOM uint32_t RDZERO30   : 1;            /*!< [5..5] Return 0 for read data on GPIO 30                                  */
      __IOM uint32_t IRPTEN30   : 2;            /*!< [7..6] Interrupt enable for GPIO 30                                       */
      __IOM uint32_t OUTCFG30   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 30                              */
      __IOM uint32_t DS30       : 2;            /*!< [11..10] Drive strength selection for GPIO 30                             */
      __IOM uint32_t SR30       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG30  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 30                        */
      __IOM uint32_t NCESRC30   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 30, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL30   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 30                              */
            uint32_t            : 2;
      __IOM uint32_t VDDPWRSWEN30 : 1;          /*!< [25..25] VDD power switch enable. Enable VDD power switch when
                                                     driving pad signal to 1 for GPIO 30                                       */
      __IOM uint32_t FIEN30     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN30     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG30_b;
  } ;

  union {
    __IOM uint32_t PINCFG31;                    /*!< (@ 0x0000007C) Controls the operation of GPIO pin 31.                     */

    struct {
      __IOM uint32_t FNCSEL31   : 4;            /*!< [3..0] Function select for GPIO pin 31                                    */
      __IOM uint32_t INPEN31    : 1;            /*!< [4..4] Input enable for GPIO 31                                           */
      __IOM uint32_t RDZERO31   : 1;            /*!< [5..5] Return 0 for read data on GPIO 31                                  */
      __IOM uint32_t IRPTEN31   : 2;            /*!< [7..6] Interrupt enable for GPIO 31                                       */
      __IOM uint32_t OUTCFG31   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 31                              */
      __IOM uint32_t DS31       : 2;            /*!< [11..10] Drive strength selection for GPIO 31                             */
      __IOM uint32_t SR31       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG31  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 31                        */
      __IOM uint32_t NCESRC31   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 31, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL31   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 31                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN31     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN31     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG31_b;
  } ;

  union {
    __IOM uint32_t PINCFG32;                    /*!< (@ 0x00000080) Controls the operation of GPIO pin 32.                     */

    struct {
      __IOM uint32_t FNCSEL32   : 4;            /*!< [3..0] Function select for GPIO pin 32                                    */
      __IOM uint32_t INPEN32    : 1;            /*!< [4..4] Input enable for GPIO 32                                           */
      __IOM uint32_t RDZERO32   : 1;            /*!< [5..5] Return 0 for read data on GPIO 32                                  */
      __IOM uint32_t IRPTEN32   : 2;            /*!< [7..6] Interrupt enable for GPIO 32                                       */
      __IOM uint32_t OUTCFG32   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 32                              */
      __IOM uint32_t DS32       : 2;            /*!< [11..10] Drive strength selection for GPIO 32                             */
      __IOM uint32_t SR32       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG32  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 32                        */
      __IOM uint32_t NCESRC32   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 32, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL32   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 32                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN32     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN32     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG32_b;
  } ;

  union {
    __IOM uint32_t PINCFG33;                    /*!< (@ 0x00000084) Controls the operation of GPIO pin 33.                     */

    struct {
      __IOM uint32_t FNCSEL33   : 4;            /*!< [3..0] Function select for GPIO pin 33                                    */
      __IOM uint32_t INPEN33    : 1;            /*!< [4..4] Input enable for GPIO 33                                           */
      __IOM uint32_t RDZERO33   : 1;            /*!< [5..5] Return 0 for read data on GPIO 33                                  */
      __IOM uint32_t IRPTEN33   : 2;            /*!< [7..6] Interrupt enable for GPIO 33                                       */
      __IOM uint32_t OUTCFG33   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 33                              */
      __IOM uint32_t DS33       : 2;            /*!< [11..10] Drive strength selection for GPIO 33                             */
      __IOM uint32_t SR33       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG33  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 33                        */
      __IOM uint32_t NCESRC33   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 33, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL33   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 33                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN33     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN33     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG33_b;
  } ;

  union {
    __IOM uint32_t PINCFG34;                    /*!< (@ 0x00000088) Controls the operation of GPIO pin 34.                     */

    struct {
      __IOM uint32_t FNCSEL34   : 4;            /*!< [3..0] Function select for GPIO pin 34                                    */
      __IOM uint32_t INPEN34    : 1;            /*!< [4..4] Input enable for GPIO 34                                           */
      __IOM uint32_t RDZERO34   : 1;            /*!< [5..5] Return 0 for read data on GPIO 34                                  */
      __IOM uint32_t IRPTEN34   : 2;            /*!< [7..6] Interrupt enable for GPIO 34                                       */
      __IOM uint32_t OUTCFG34   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 34                              */
      __IOM uint32_t DS34       : 2;            /*!< [11..10] Drive strength selection for GPIO 34                             */
      __IOM uint32_t SR34       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG34  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 34                        */
      __IOM uint32_t NCESRC34   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 34, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL34   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 34                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN34     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN34     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG34_b;
  } ;

  union {
    __IOM uint32_t PINCFG35;                    /*!< (@ 0x0000008C) Controls the operation of GPIO pin 35.                     */

    struct {
      __IOM uint32_t FNCSEL35   : 4;            /*!< [3..0] Function select for GPIO pin 35                                    */
      __IOM uint32_t INPEN35    : 1;            /*!< [4..4] Input enable for GPIO 35                                           */
      __IOM uint32_t RDZERO35   : 1;            /*!< [5..5] Return 0 for read data on GPIO 35                                  */
      __IOM uint32_t IRPTEN35   : 2;            /*!< [7..6] Interrupt enable for GPIO 35                                       */
      __IOM uint32_t OUTCFG35   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 35                              */
      __IOM uint32_t DS35       : 2;            /*!< [11..10] Drive strength selection for GPIO 35                             */
      __IOM uint32_t SR35       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG35  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 35                        */
      __IOM uint32_t NCESRC35   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 35, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL35   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 35                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN35     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN35     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG35_b;
  } ;

  union {
    __IOM uint32_t PINCFG36;                    /*!< (@ 0x00000090) Controls the operation of GPIO pin 36.                     */

    struct {
      __IOM uint32_t FNCSEL36   : 4;            /*!< [3..0] Function select for GPIO pin 36                                    */
      __IOM uint32_t INPEN36    : 1;            /*!< [4..4] Input enable for GPIO 36                                           */
      __IOM uint32_t RDZERO36   : 1;            /*!< [5..5] Return 0 for read data on GPIO 36                                  */
      __IOM uint32_t IRPTEN36   : 2;            /*!< [7..6] Interrupt enable for GPIO 36                                       */
      __IOM uint32_t OUTCFG36   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 36                              */
      __IOM uint32_t DS36       : 2;            /*!< [11..10] Drive strength selection for GPIO 36                             */
      __IOM uint32_t SR36       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG36  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 36                        */
      __IOM uint32_t NCESRC36   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 36, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL36   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 36                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN36     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN36     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG36_b;
  } ;

  union {
    __IOM uint32_t PINCFG37;                    /*!< (@ 0x00000094) Controls the operation of GPIO pin 37.                     */

    struct {
      __IOM uint32_t FNCSEL37   : 4;            /*!< [3..0] Function select for GPIO pin 37                                    */
      __IOM uint32_t INPEN37    : 1;            /*!< [4..4] Input enable for GPIO 37                                           */
      __IOM uint32_t RDZERO37   : 1;            /*!< [5..5] Return 0 for read data on GPIO 37                                  */
      __IOM uint32_t IRPTEN37   : 2;            /*!< [7..6] Interrupt enable for GPIO 37                                       */
      __IOM uint32_t OUTCFG37   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 37                              */
      __IOM uint32_t DS37       : 2;            /*!< [11..10] Drive strength selection for GPIO 37                             */
      __IOM uint32_t SR37       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG37  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 37                        */
      __IOM uint32_t NCESRC37   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 37, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL37   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 37                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN37     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN37     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG37_b;
  } ;

  union {
    __IOM uint32_t PINCFG38;                    /*!< (@ 0x00000098) Controls the operation of GPIO pin 38.                     */

    struct {
      __IOM uint32_t FNCSEL38   : 4;            /*!< [3..0] Function select for GPIO pin 38                                    */
      __IOM uint32_t INPEN38    : 1;            /*!< [4..4] Input enable for GPIO 38                                           */
      __IOM uint32_t RDZERO38   : 1;            /*!< [5..5] Return 0 for read data on GPIO 38                                  */
      __IOM uint32_t IRPTEN38   : 2;            /*!< [7..6] Interrupt enable for GPIO 38                                       */
      __IOM uint32_t OUTCFG38   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 38                              */
      __IOM uint32_t DS38       : 2;            /*!< [11..10] Drive strength selection for GPIO 38                             */
      __IOM uint32_t SR38       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG38  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 38                        */
      __IOM uint32_t NCESRC38   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 38, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL38   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 38                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN38     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN38     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG38_b;
  } ;

  union {
    __IOM uint32_t PINCFG39;                    /*!< (@ 0x0000009C) Controls the operation of GPIO pin 39.                     */

    struct {
      __IOM uint32_t FNCSEL39   : 4;            /*!< [3..0] Function select for GPIO pin 39                                    */
      __IOM uint32_t INPEN39    : 1;            /*!< [4..4] Input enable for GPIO 39                                           */
      __IOM uint32_t RDZERO39   : 1;            /*!< [5..5] Return 0 for read data on GPIO 39                                  */
      __IOM uint32_t IRPTEN39   : 2;            /*!< [7..6] Interrupt enable for GPIO 39                                       */
      __IOM uint32_t OUTCFG39   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 39                              */
      __IOM uint32_t DS39       : 2;            /*!< [11..10] Drive strength selection for GPIO 39                             */
      __IOM uint32_t SR39       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG39  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 39                        */
      __IOM uint32_t NCESRC39   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 39, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL39   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 39                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN39     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN39     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG39_b;
  } ;

  union {
    __IOM uint32_t PINCFG40;                    /*!< (@ 0x000000A0) Controls the operation of GPIO pin 40.                     */

    struct {
      __IOM uint32_t FNCSEL40   : 4;            /*!< [3..0] Function select for GPIO pin 40                                    */
      __IOM uint32_t INPEN40    : 1;            /*!< [4..4] Input enable for GPIO 40                                           */
      __IOM uint32_t RDZERO40   : 1;            /*!< [5..5] Return 0 for read data on GPIO 40                                  */
      __IOM uint32_t IRPTEN40   : 2;            /*!< [7..6] Interrupt enable for GPIO 40                                       */
      __IOM uint32_t OUTCFG40   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 40                              */
      __IOM uint32_t DS40       : 2;            /*!< [11..10] Drive strength selection for GPIO 40                             */
      __IOM uint32_t SR40       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG40  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 40                        */
      __IOM uint32_t NCESRC40   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 40, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL40   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 40                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN40     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN40     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG40_b;
  } ;

  union {
    __IOM uint32_t PINCFG41;                    /*!< (@ 0x000000A4) Controls the operation of GPIO pin 41.                     */

    struct {
      __IOM uint32_t FNCSEL41   : 4;            /*!< [3..0] Function select for GPIO pin 41                                    */
      __IOM uint32_t INPEN41    : 1;            /*!< [4..4] Input enable for GPIO 41                                           */
      __IOM uint32_t RDZERO41   : 1;            /*!< [5..5] Return 0 for read data on GPIO 41                                  */
      __IOM uint32_t IRPTEN41   : 2;            /*!< [7..6] Interrupt enable for GPIO 41                                       */
      __IOM uint32_t OUTCFG41   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 41                              */
      __IOM uint32_t DS41       : 2;            /*!< [11..10] Drive strength selection for GPIO 41                             */
      __IOM uint32_t SR41       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG41  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 41                        */
      __IOM uint32_t NCESRC41   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 41, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL41   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 41                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN41     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN41     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG41_b;
  } ;

  union {
    __IOM uint32_t PINCFG42;                    /*!< (@ 0x000000A8) Controls the operation of GPIO pin 42.                     */

    struct {
      __IOM uint32_t FNCSEL42   : 4;            /*!< [3..0] Function select for GPIO pin 42                                    */
      __IOM uint32_t INPEN42    : 1;            /*!< [4..4] Input enable for GPIO 42                                           */
      __IOM uint32_t RDZERO42   : 1;            /*!< [5..5] Return 0 for read data on GPIO 42                                  */
      __IOM uint32_t IRPTEN42   : 2;            /*!< [7..6] Interrupt enable for GPIO 42                                       */
      __IOM uint32_t OUTCFG42   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 42                              */
      __IOM uint32_t DS42       : 2;            /*!< [11..10] Drive strength selection for GPIO 42                             */
      __IOM uint32_t SR42       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG42  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 42                        */
      __IOM uint32_t NCESRC42   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 42, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL42   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 42                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN42     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN42     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG42_b;
  } ;

  union {
    __IOM uint32_t PINCFG43;                    /*!< (@ 0x000000AC) Controls the operation of GPIO pin 43.                     */

    struct {
      __IOM uint32_t FNCSEL43   : 4;            /*!< [3..0] Function select for GPIO pin 43                                    */
      __IOM uint32_t INPEN43    : 1;            /*!< [4..4] Input enable for GPIO 43                                           */
      __IOM uint32_t RDZERO43   : 1;            /*!< [5..5] Return 0 for read data on GPIO 43                                  */
      __IOM uint32_t IRPTEN43   : 2;            /*!< [7..6] Interrupt enable for GPIO 43                                       */
      __IOM uint32_t OUTCFG43   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 43                              */
      __IOM uint32_t DS43       : 2;            /*!< [11..10] Drive strength selection for GPIO 43                             */
      __IOM uint32_t SR43       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG43  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 43                        */
      __IOM uint32_t NCESRC43   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 43, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL43   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 43                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN43     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN43     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG43_b;
  } ;

  union {
    __IOM uint32_t PINCFG44;                    /*!< (@ 0x000000B0) Controls the operation of GPIO pin 44.                     */

    struct {
      __IOM uint32_t FNCSEL44   : 4;            /*!< [3..0] Function select for GPIO pin 44                                    */
      __IOM uint32_t INPEN44    : 1;            /*!< [4..4] Input enable for GPIO 44                                           */
      __IOM uint32_t RDZERO44   : 1;            /*!< [5..5] Return 0 for read data on GPIO 44                                  */
      __IOM uint32_t IRPTEN44   : 2;            /*!< [7..6] Interrupt enable for GPIO 44                                       */
      __IOM uint32_t OUTCFG44   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 44                              */
      __IOM uint32_t DS44       : 2;            /*!< [11..10] Drive strength selection for GPIO 44                             */
      __IOM uint32_t SR44       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG44  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 44                        */
      __IOM uint32_t NCESRC44   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 44, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL44   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 44                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN44     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN44     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG44_b;
  } ;

  union {
    __IOM uint32_t PINCFG45;                    /*!< (@ 0x000000B4) Controls the operation of GPIO pin 45.                     */

    struct {
      __IOM uint32_t FNCSEL45   : 4;            /*!< [3..0] Function select for GPIO pin 45                                    */
      __IOM uint32_t INPEN45    : 1;            /*!< [4..4] Input enable for GPIO 45                                           */
      __IOM uint32_t RDZERO45   : 1;            /*!< [5..5] Return 0 for read data on GPIO 45                                  */
      __IOM uint32_t IRPTEN45   : 2;            /*!< [7..6] Interrupt enable for GPIO 45                                       */
      __IOM uint32_t OUTCFG45   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 45                              */
      __IOM uint32_t DS45       : 2;            /*!< [11..10] Drive strength selection for GPIO 45                             */
      __IOM uint32_t SR45       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG45  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 45                        */
      __IOM uint32_t NCESRC45   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 45, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL45   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 45                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN45     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN45     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG45_b;
  } ;

  union {
    __IOM uint32_t PINCFG46;                    /*!< (@ 0x000000B8) Controls the operation of GPIO pin 46.                     */

    struct {
      __IOM uint32_t FNCSEL46   : 4;            /*!< [3..0] Function select for GPIO pin 46                                    */
      __IOM uint32_t INPEN46    : 1;            /*!< [4..4] Input enable for GPIO 46                                           */
      __IOM uint32_t RDZERO46   : 1;            /*!< [5..5] Return 0 for read data on GPIO 46                                  */
      __IOM uint32_t IRPTEN46   : 2;            /*!< [7..6] Interrupt enable for GPIO 46                                       */
      __IOM uint32_t OUTCFG46   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 46                              */
      __IOM uint32_t DS46       : 2;            /*!< [11..10] Drive strength selection for GPIO 46                             */
      __IOM uint32_t SR46       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG46  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 46                        */
      __IOM uint32_t NCESRC46   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 46, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL46   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 46                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN46     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN46     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG46_b;
  } ;

  union {
    __IOM uint32_t PINCFG47;                    /*!< (@ 0x000000BC) Controls the operation of GPIO pin 47.                     */

    struct {
      __IOM uint32_t FNCSEL47   : 4;            /*!< [3..0] Function select for GPIO pin 47                                    */
      __IOM uint32_t INPEN47    : 1;            /*!< [4..4] Input enable for GPIO 47                                           */
      __IOM uint32_t RDZERO47   : 1;            /*!< [5..5] Return 0 for read data on GPIO 47                                  */
      __IOM uint32_t IRPTEN47   : 2;            /*!< [7..6] Interrupt enable for GPIO 47                                       */
      __IOM uint32_t OUTCFG47   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 47                              */
      __IOM uint32_t DS47       : 2;            /*!< [11..10] Drive strength selection for GPIO 47                             */
      __IOM uint32_t SR47       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG47  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 47                        */
      __IOM uint32_t NCESRC47   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 47, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL47   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 47                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN47     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN47     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG47_b;
  } ;

  union {
    __IOM uint32_t PINCFG48;                    /*!< (@ 0x000000C0) Controls the operation of GPIO pin 48.                     */

    struct {
      __IOM uint32_t FNCSEL48   : 4;            /*!< [3..0] Function select for GPIO pin 48                                    */
      __IOM uint32_t INPEN48    : 1;            /*!< [4..4] Input enable for GPIO 48                                           */
      __IOM uint32_t RDZERO48   : 1;            /*!< [5..5] Return 0 for read data on GPIO 48                                  */
      __IOM uint32_t IRPTEN48   : 2;            /*!< [7..6] Interrupt enable for GPIO 48                                       */
      __IOM uint32_t OUTCFG48   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 48                              */
      __IOM uint32_t DS48       : 2;            /*!< [11..10] Drive strength selection for GPIO 48                             */
      __IOM uint32_t SR48       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG48  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 48                        */
      __IOM uint32_t NCESRC48   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 48, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL48   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 48                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN48     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN48     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG48_b;
  } ;

  union {
    __IOM uint32_t PINCFG49;                    /*!< (@ 0x000000C4) Controls the operation of GPIO pin 49.                     */

    struct {
      __IOM uint32_t FNCSEL49   : 4;            /*!< [3..0] Function select for GPIO pin 49                                    */
      __IOM uint32_t INPEN49    : 1;            /*!< [4..4] Input enable for GPIO 49                                           */
      __IOM uint32_t RDZERO49   : 1;            /*!< [5..5] Return 0 for read data on GPIO 49                                  */
      __IOM uint32_t IRPTEN49   : 2;            /*!< [7..6] Interrupt enable for GPIO 49                                       */
      __IOM uint32_t OUTCFG49   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 49                              */
      __IOM uint32_t DS49       : 2;            /*!< [11..10] Drive strength selection for GPIO 49                             */
      __IOM uint32_t SR49       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG49  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 49                        */
      __IOM uint32_t NCESRC49   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 49, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL49   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 49                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN49     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN49     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG49_b;
  } ;

  union {
    __IOM uint32_t PINCFG50;                    /*!< (@ 0x000000C8) Controls the operation of GPIO pin 50.                     */

    struct {
      __IOM uint32_t FNCSEL50   : 4;            /*!< [3..0] Function select for GPIO pin 50                                    */
      __IOM uint32_t INPEN50    : 1;            /*!< [4..4] Input enable for GPIO 50                                           */
      __IOM uint32_t RDZERO50   : 1;            /*!< [5..5] Return 0 for read data on GPIO 50                                  */
      __IOM uint32_t IRPTEN50   : 2;            /*!< [7..6] Interrupt enable for GPIO 50                                       */
      __IOM uint32_t OUTCFG50   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 50                              */
      __IOM uint32_t DS50       : 2;            /*!< [11..10] Drive strength selection for GPIO 50                             */
      __IOM uint32_t SR50       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG50  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 50                        */
      __IOM uint32_t NCESRC50   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 50, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL50   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 50                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN50     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN50     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG50_b;
  } ;

  union {
    __IOM uint32_t PINCFG51;                    /*!< (@ 0x000000CC) Controls the operation of GPIO pin 51.                     */

    struct {
      __IOM uint32_t FNCSEL51   : 4;            /*!< [3..0] Function select for GPIO pin 51                                    */
      __IOM uint32_t INPEN51    : 1;            /*!< [4..4] Input enable for GPIO 51                                           */
      __IOM uint32_t RDZERO51   : 1;            /*!< [5..5] Return 0 for read data on GPIO 51                                  */
      __IOM uint32_t IRPTEN51   : 2;            /*!< [7..6] Interrupt enable for GPIO 51                                       */
      __IOM uint32_t OUTCFG51   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 51                              */
      __IOM uint32_t DS51       : 2;            /*!< [11..10] Drive strength selection for GPIO 51                             */
      __IOM uint32_t SR51       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG51  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 51                        */
      __IOM uint32_t NCESRC51   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 51, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL51   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 51                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN51     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN51     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG51_b;
  } ;

  union {
    __IOM uint32_t PINCFG52;                    /*!< (@ 0x000000D0) Controls the operation of GPIO pin 52.                     */

    struct {
      __IOM uint32_t FNCSEL52   : 4;            /*!< [3..0] Function select for GPIO pin 52                                    */
      __IOM uint32_t INPEN52    : 1;            /*!< [4..4] Input enable for GPIO 52                                           */
      __IOM uint32_t RDZERO52   : 1;            /*!< [5..5] Return 0 for read data on GPIO 52                                  */
      __IOM uint32_t IRPTEN52   : 2;            /*!< [7..6] Interrupt enable for GPIO 52                                       */
      __IOM uint32_t OUTCFG52   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 52                              */
      __IOM uint32_t DS52       : 2;            /*!< [11..10] Drive strength selection for GPIO 52                             */
      __IOM uint32_t SR52       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG52  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 52                        */
      __IOM uint32_t NCESRC52   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 52, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL52   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 52                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN52     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN52     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG52_b;
  } ;

  union {
    __IOM uint32_t PINCFG53;                    /*!< (@ 0x000000D4) Controls the operation of GPIO pin 53.                     */

    struct {
      __IOM uint32_t FNCSEL53   : 4;            /*!< [3..0] Function select for GPIO pin 53                                    */
      __IOM uint32_t INPEN53    : 1;            /*!< [4..4] Input enable for GPIO 53                                           */
      __IOM uint32_t RDZERO53   : 1;            /*!< [5..5] Return 0 for read data on GPIO 53                                  */
      __IOM uint32_t IRPTEN53   : 2;            /*!< [7..6] Interrupt enable for GPIO 53                                       */
      __IOM uint32_t OUTCFG53   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 53                              */
      __IOM uint32_t DS53       : 2;            /*!< [11..10] Drive strength selection for GPIO 53                             */
      __IOM uint32_t SR53       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG53  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 53                        */
      __IOM uint32_t NCESRC53   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 53, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL53   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 53                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN53     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN53     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG53_b;
  } ;

  union {
    __IOM uint32_t PINCFG54;                    /*!< (@ 0x000000D8) Controls the operation of GPIO pin 54.                     */

    struct {
      __IOM uint32_t FNCSEL54   : 4;            /*!< [3..0] Function select for GPIO pin 54                                    */
      __IOM uint32_t INPEN54    : 1;            /*!< [4..4] Input enable for GPIO 54                                           */
      __IOM uint32_t RDZERO54   : 1;            /*!< [5..5] Return 0 for read data on GPIO 54                                  */
      __IOM uint32_t IRPTEN54   : 2;            /*!< [7..6] Interrupt enable for GPIO 54                                       */
      __IOM uint32_t OUTCFG54   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 54                              */
      __IOM uint32_t DS54       : 2;            /*!< [11..10] Drive strength selection for GPIO 54                             */
      __IOM uint32_t SR54       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG54  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 54                        */
      __IOM uint32_t NCESRC54   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 54, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL54   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 54                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN54     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN54     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG54_b;
  } ;

  union {
    __IOM uint32_t PINCFG55;                    /*!< (@ 0x000000DC) Controls the operation of GPIO pin 55.                     */

    struct {
      __IOM uint32_t FNCSEL55   : 4;            /*!< [3..0] Function select for GPIO pin 55                                    */
      __IOM uint32_t INPEN55    : 1;            /*!< [4..4] Input enable for GPIO 55                                           */
      __IOM uint32_t RDZERO55   : 1;            /*!< [5..5] Return 0 for read data on GPIO 55                                  */
      __IOM uint32_t IRPTEN55   : 2;            /*!< [7..6] Interrupt enable for GPIO 55                                       */
      __IOM uint32_t OUTCFG55   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 55                              */
      __IOM uint32_t DS55       : 2;            /*!< [11..10] Drive strength selection for GPIO 55                             */
      __IOM uint32_t SR55       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG55  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 55                        */
      __IOM uint32_t NCESRC55   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 55, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL55   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 55                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN55     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN55     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG55_b;
  } ;

  union {
    __IOM uint32_t PINCFG56;                    /*!< (@ 0x000000E0) Controls the operation of GPIO pin 56.                     */

    struct {
      __IOM uint32_t FNCSEL56   : 4;            /*!< [3..0] Function select for GPIO pin 56                                    */
      __IOM uint32_t INPEN56    : 1;            /*!< [4..4] Input enable for GPIO 56                                           */
      __IOM uint32_t RDZERO56   : 1;            /*!< [5..5] Return 0 for read data on GPIO 56                                  */
      __IOM uint32_t IRPTEN56   : 2;            /*!< [7..6] Interrupt enable for GPIO 56                                       */
      __IOM uint32_t OUTCFG56   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 56                              */
      __IOM uint32_t DS56       : 2;            /*!< [11..10] Drive strength selection for GPIO 56                             */
      __IOM uint32_t SR56       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG56  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 56                        */
      __IOM uint32_t NCESRC56   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 56, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL56   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 56                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN56     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN56     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG56_b;
  } ;

  union {
    __IOM uint32_t PINCFG57;                    /*!< (@ 0x000000E4) Controls the operation of GPIO pin 57.                     */

    struct {
      __IOM uint32_t FNCSEL57   : 4;            /*!< [3..0] Function select for GPIO pin 57                                    */
      __IOM uint32_t INPEN57    : 1;            /*!< [4..4] Input enable for GPIO 57                                           */
      __IOM uint32_t RDZERO57   : 1;            /*!< [5..5] Return 0 for read data on GPIO 57                                  */
      __IOM uint32_t IRPTEN57   : 2;            /*!< [7..6] Interrupt enable for GPIO 57                                       */
      __IOM uint32_t OUTCFG57   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 57                              */
      __IOM uint32_t DS57       : 2;            /*!< [11..10] Drive strength selection for GPIO 57                             */
      __IOM uint32_t SR57       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG57  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 57                        */
      __IOM uint32_t NCESRC57   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 57, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL57   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 57                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN57     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN57     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG57_b;
  } ;

  union {
    __IOM uint32_t PINCFG58;                    /*!< (@ 0x000000E8) Controls the operation of GPIO pin 58.                     */

    struct {
      __IOM uint32_t FNCSEL58   : 4;            /*!< [3..0] Function select for GPIO pin 58                                    */
      __IOM uint32_t INPEN58    : 1;            /*!< [4..4] Input enable for GPIO 58                                           */
      __IOM uint32_t RDZERO58   : 1;            /*!< [5..5] Return 0 for read data on GPIO 58                                  */
      __IOM uint32_t IRPTEN58   : 2;            /*!< [7..6] Interrupt enable for GPIO 58                                       */
      __IOM uint32_t OUTCFG58   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 58                              */
      __IOM uint32_t DS58       : 2;            /*!< [11..10] Drive strength selection for GPIO 58                             */
      __IOM uint32_t SR58       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG58  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 58                        */
      __IOM uint32_t NCESRC58   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 58, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL58   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 58                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN58     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN58     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG58_b;
  } ;

  union {
    __IOM uint32_t PINCFG59;                    /*!< (@ 0x000000EC) Controls the operation of GPIO pin 59.                     */

    struct {
      __IOM uint32_t FNCSEL59   : 4;            /*!< [3..0] Function select for GPIO pin 59                                    */
      __IOM uint32_t INPEN59    : 1;            /*!< [4..4] Input enable for GPIO 59                                           */
      __IOM uint32_t RDZERO59   : 1;            /*!< [5..5] Return 0 for read data on GPIO 59                                  */
      __IOM uint32_t IRPTEN59   : 2;            /*!< [7..6] Interrupt enable for GPIO 59                                       */
      __IOM uint32_t OUTCFG59   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 59                              */
      __IOM uint32_t DS59       : 2;            /*!< [11..10] Drive strength selection for GPIO 59                             */
      __IOM uint32_t SR59       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG59  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 59                        */
      __IOM uint32_t NCESRC59   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 59, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL59   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 59                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN59     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN59     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG59_b;
  } ;

  union {
    __IOM uint32_t PINCFG60;                    /*!< (@ 0x000000F0) Controls the operation of GPIO pin 60.                     */

    struct {
      __IOM uint32_t FNCSEL60   : 4;            /*!< [3..0] Function select for GPIO pin 60                                    */
      __IOM uint32_t INPEN60    : 1;            /*!< [4..4] Input enable for GPIO 60                                           */
      __IOM uint32_t RDZERO60   : 1;            /*!< [5..5] Return 0 for read data on GPIO 60                                  */
      __IOM uint32_t IRPTEN60   : 2;            /*!< [7..6] Interrupt enable for GPIO 60                                       */
      __IOM uint32_t OUTCFG60   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 60                              */
      __IOM uint32_t DS60       : 2;            /*!< [11..10] Drive strength selection for GPIO 60                             */
      __IOM uint32_t SR60       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG60  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 60                        */
      __IOM uint32_t NCESRC60   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 60, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL60   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 60                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN60     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN60     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG60_b;
  } ;

  union {
    __IOM uint32_t PINCFG61;                    /*!< (@ 0x000000F4) Controls the operation of GPIO pin 61.                     */

    struct {
      __IOM uint32_t FNCSEL61   : 4;            /*!< [3..0] Function select for GPIO pin 61                                    */
      __IOM uint32_t INPEN61    : 1;            /*!< [4..4] Input enable for GPIO 61                                           */
      __IOM uint32_t RDZERO61   : 1;            /*!< [5..5] Return 0 for read data on GPIO 61                                  */
      __IOM uint32_t IRPTEN61   : 2;            /*!< [7..6] Interrupt enable for GPIO 61                                       */
      __IOM uint32_t OUTCFG61   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 61                              */
      __IOM uint32_t DS61       : 2;            /*!< [11..10] Drive strength selection for GPIO 61                             */
      __IOM uint32_t SR61       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG61  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 61                        */
      __IOM uint32_t NCESRC61   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 61, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL61   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 61                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN61     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN61     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG61_b;
  } ;

  union {
    __IOM uint32_t PINCFG62;                    /*!< (@ 0x000000F8) Controls the operation of GPIO pin 62.                     */

    struct {
      __IOM uint32_t FNCSEL62   : 4;            /*!< [3..0] Function select for GPIO pin 62                                    */
      __IOM uint32_t INPEN62    : 1;            /*!< [4..4] Input enable for GPIO 62                                           */
      __IOM uint32_t RDZERO62   : 1;            /*!< [5..5] Return 0 for read data on GPIO 62                                  */
      __IOM uint32_t IRPTEN62   : 2;            /*!< [7..6] Interrupt enable for GPIO 62                                       */
      __IOM uint32_t OUTCFG62   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 62                              */
      __IOM uint32_t DS62       : 2;            /*!< [11..10] Drive strength selection for GPIO 62                             */
      __IOM uint32_t SR62       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG62  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 62                        */
      __IOM uint32_t NCESRC62   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 62, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL62   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 62                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN62     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN62     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG62_b;
  } ;

  union {
    __IOM uint32_t PINCFG63;                    /*!< (@ 0x000000FC) Controls the operation of GPIO pin 63.                     */

    struct {
      __IOM uint32_t FNCSEL63   : 4;            /*!< [3..0] Function select for GPIO pin 63                                    */
      __IOM uint32_t INPEN63    : 1;            /*!< [4..4] Input enable for GPIO 63                                           */
      __IOM uint32_t RDZERO63   : 1;            /*!< [5..5] Return 0 for read data on GPIO 63                                  */
      __IOM uint32_t IRPTEN63   : 2;            /*!< [7..6] Interrupt enable for GPIO 63                                       */
      __IOM uint32_t OUTCFG63   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 63                              */
      __IOM uint32_t DS63       : 2;            /*!< [11..10] Drive strength selection for GPIO 63                             */
      __IOM uint32_t SR63       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG63  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 63                        */
      __IOM uint32_t NCESRC63   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 63, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL63   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 63                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN63     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN63     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG63_b;
  } ;

  union {
    __IOM uint32_t PINCFG64;                    /*!< (@ 0x00000100) Controls the operation of GPIO pin 64.                     */

    struct {
      __IOM uint32_t FNCSEL64   : 4;            /*!< [3..0] Function select for GPIO pin 64                                    */
      __IOM uint32_t INPEN64    : 1;            /*!< [4..4] Input enable for GPIO 64                                           */
      __IOM uint32_t RDZERO64   : 1;            /*!< [5..5] Return 0 for read data on GPIO 64                                  */
      __IOM uint32_t IRPTEN64   : 2;            /*!< [7..6] Interrupt enable for GPIO 64                                       */
      __IOM uint32_t OUTCFG64   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 64                              */
      __IOM uint32_t DS64       : 2;            /*!< [11..10] Drive strength selection for GPIO 64                             */
      __IOM uint32_t SR64       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG64  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 64                        */
      __IOM uint32_t NCESRC64   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 64, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL64   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 64                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN64     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN64     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG64_b;
  } ;

  union {
    __IOM uint32_t PINCFG65;                    /*!< (@ 0x00000104) Controls the operation of GPIO pin 65.                     */

    struct {
      __IOM uint32_t FNCSEL65   : 4;            /*!< [3..0] Function select for GPIO pin 65                                    */
      __IOM uint32_t INPEN65    : 1;            /*!< [4..4] Input enable for GPIO 65                                           */
      __IOM uint32_t RDZERO65   : 1;            /*!< [5..5] Return 0 for read data on GPIO 65                                  */
      __IOM uint32_t IRPTEN65   : 2;            /*!< [7..6] Interrupt enable for GPIO 65                                       */
      __IOM uint32_t OUTCFG65   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 65                              */
      __IOM uint32_t DS65       : 2;            /*!< [11..10] Drive strength selection for GPIO 65                             */
      __IOM uint32_t SR65       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG65  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 65                        */
      __IOM uint32_t NCESRC65   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 65, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL65   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 65                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN65     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN65     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG65_b;
  } ;

  union {
    __IOM uint32_t PINCFG66;                    /*!< (@ 0x00000108) Controls the operation of GPIO pin 66.                     */

    struct {
      __IOM uint32_t FNCSEL66   : 4;            /*!< [3..0] Function select for GPIO pin 66                                    */
      __IOM uint32_t INPEN66    : 1;            /*!< [4..4] Input enable for GPIO 66                                           */
      __IOM uint32_t RDZERO66   : 1;            /*!< [5..5] Return 0 for read data on GPIO 66                                  */
      __IOM uint32_t IRPTEN66   : 2;            /*!< [7..6] Interrupt enable for GPIO 66                                       */
      __IOM uint32_t OUTCFG66   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 66                              */
      __IOM uint32_t DS66       : 2;            /*!< [11..10] Drive strength selection for GPIO 66                             */
      __IOM uint32_t SR66       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG66  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 66                        */
      __IOM uint32_t NCESRC66   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 66, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL66   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 66                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN66     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN66     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG66_b;
  } ;

  union {
    __IOM uint32_t PINCFG67;                    /*!< (@ 0x0000010C) Controls the operation of GPIO pin 67.                     */

    struct {
      __IOM uint32_t FNCSEL67   : 4;            /*!< [3..0] Function select for GPIO pin 67                                    */
      __IOM uint32_t INPEN67    : 1;            /*!< [4..4] Input enable for GPIO 67                                           */
      __IOM uint32_t RDZERO67   : 1;            /*!< [5..5] Return 0 for read data on GPIO 67                                  */
      __IOM uint32_t IRPTEN67   : 2;            /*!< [7..6] Interrupt enable for GPIO 67                                       */
      __IOM uint32_t OUTCFG67   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 67                              */
      __IOM uint32_t DS67       : 2;            /*!< [11..10] Drive strength selection for GPIO 67                             */
      __IOM uint32_t SR67       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG67  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 67                        */
      __IOM uint32_t NCESRC67   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 67, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL67   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 67                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN67     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN67     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG67_b;
  } ;

  union {
    __IOM uint32_t PINCFG68;                    /*!< (@ 0x00000110) Controls the operation of GPIO pin 68.                     */

    struct {
      __IOM uint32_t FNCSEL68   : 4;            /*!< [3..0] Function select for GPIO pin 68                                    */
      __IOM uint32_t INPEN68    : 1;            /*!< [4..4] Input enable for GPIO 68                                           */
      __IOM uint32_t RDZERO68   : 1;            /*!< [5..5] Return 0 for read data on GPIO 68                                  */
      __IOM uint32_t IRPTEN68   : 2;            /*!< [7..6] Interrupt enable for GPIO 68                                       */
      __IOM uint32_t OUTCFG68   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 68                              */
      __IOM uint32_t DS68       : 2;            /*!< [11..10] Drive strength selection for GPIO 68                             */
      __IOM uint32_t SR68       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG68  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 68                        */
      __IOM uint32_t NCESRC68   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 68, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL68   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 68                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN68     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN68     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG68_b;
  } ;

  union {
    __IOM uint32_t PINCFG69;                    /*!< (@ 0x00000114) Controls the operation of GPIO pin 69.                     */

    struct {
      __IOM uint32_t FNCSEL69   : 4;            /*!< [3..0] Function select for GPIO pin 69                                    */
      __IOM uint32_t INPEN69    : 1;            /*!< [4..4] Input enable for GPIO 69                                           */
      __IOM uint32_t RDZERO69   : 1;            /*!< [5..5] Return 0 for read data on GPIO 69                                  */
      __IOM uint32_t IRPTEN69   : 2;            /*!< [7..6] Interrupt enable for GPIO 69                                       */
      __IOM uint32_t OUTCFG69   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 69                              */
      __IOM uint32_t DS69       : 2;            /*!< [11..10] Drive strength selection for GPIO 69                             */
      __IOM uint32_t SR69       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG69  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 69                        */
      __IOM uint32_t NCESRC69   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 69, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL69   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 69                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN69     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN69     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG69_b;
  } ;

  union {
    __IOM uint32_t PINCFG70;                    /*!< (@ 0x00000118) Controls the operation of GPIO pin 70.                     */

    struct {
      __IOM uint32_t FNCSEL70   : 4;            /*!< [3..0] Function select for GPIO pin 70                                    */
      __IOM uint32_t INPEN70    : 1;            /*!< [4..4] Input enable for GPIO 70                                           */
      __IOM uint32_t RDZERO70   : 1;            /*!< [5..5] Return 0 for read data on GPIO 70                                  */
      __IOM uint32_t IRPTEN70   : 2;            /*!< [7..6] Interrupt enable for GPIO 70                                       */
      __IOM uint32_t OUTCFG70   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 70                              */
      __IOM uint32_t DS70       : 2;            /*!< [11..10] Drive strength selection for GPIO 70                             */
      __IOM uint32_t SR70       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG70  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 70                        */
      __IOM uint32_t NCESRC70   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 70, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL70   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 70                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN70     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN70     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG70_b;
  } ;

  union {
    __IOM uint32_t PINCFG71;                    /*!< (@ 0x0000011C) Controls the operation of GPIO pin 71.                     */

    struct {
      __IOM uint32_t FNCSEL71   : 4;            /*!< [3..0] Function select for GPIO pin 71                                    */
      __IOM uint32_t INPEN71    : 1;            /*!< [4..4] Input enable for GPIO 71                                           */
      __IOM uint32_t RDZERO71   : 1;            /*!< [5..5] Return 0 for read data on GPIO 71                                  */
      __IOM uint32_t IRPTEN71   : 2;            /*!< [7..6] Interrupt enable for GPIO 71                                       */
      __IOM uint32_t OUTCFG71   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 71                              */
      __IOM uint32_t DS71       : 2;            /*!< [11..10] Drive strength selection for GPIO 71                             */
      __IOM uint32_t SR71       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG71  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 71                        */
      __IOM uint32_t NCESRC71   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 71, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL71   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 71                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN71     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN71     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG71_b;
  } ;

  union {
    __IOM uint32_t PINCFG72;                    /*!< (@ 0x00000120) Controls the operation of GPIO pin 72.                     */

    struct {
      __IOM uint32_t FNCSEL72   : 4;            /*!< [3..0] Function select for GPIO pin 72                                    */
      __IOM uint32_t INPEN72    : 1;            /*!< [4..4] Input enable for GPIO 72                                           */
      __IOM uint32_t RDZERO72   : 1;            /*!< [5..5] Return 0 for read data on GPIO 72                                  */
      __IOM uint32_t IRPTEN72   : 2;            /*!< [7..6] Interrupt enable for GPIO 72                                       */
      __IOM uint32_t OUTCFG72   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 72                              */
      __IOM uint32_t DS72       : 2;            /*!< [11..10] Drive strength selection for GPIO 72                             */
      __IOM uint32_t SR72       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG72  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 72                        */
      __IOM uint32_t NCESRC72   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 72, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL72   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 72                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN72     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN72     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG72_b;
  } ;

  union {
    __IOM uint32_t PINCFG73;                    /*!< (@ 0x00000124) Controls the operation of GPIO pin 73.                     */

    struct {
      __IOM uint32_t FNCSEL73   : 4;            /*!< [3..0] Function select for GPIO pin 73                                    */
      __IOM uint32_t INPEN73    : 1;            /*!< [4..4] Input enable for GPIO 73                                           */
      __IOM uint32_t RDZERO73   : 1;            /*!< [5..5] Return 0 for read data on GPIO 73                                  */
      __IOM uint32_t IRPTEN73   : 2;            /*!< [7..6] Interrupt enable for GPIO 73                                       */
      __IOM uint32_t OUTCFG73   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 73                              */
      __IOM uint32_t DS73       : 2;            /*!< [11..10] Drive strength selection for GPIO 73                             */
      __IOM uint32_t SR73       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG73  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 73                        */
      __IOM uint32_t NCESRC73   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 73, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL73   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 73                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN73     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN73     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG73_b;
  } ;

  union {
    __IOM uint32_t PINCFG74;                    /*!< (@ 0x00000128) Controls the operation of GPIO pin 74.                     */

    struct {
      __IOM uint32_t FNCSEL74   : 4;            /*!< [3..0] Function select for GPIO pin 74                                    */
      __IOM uint32_t INPEN74    : 1;            /*!< [4..4] Input enable for GPIO 74                                           */
      __IOM uint32_t RDZERO74   : 1;            /*!< [5..5] Return 0 for read data on GPIO 74                                  */
      __IOM uint32_t IRPTEN74   : 2;            /*!< [7..6] Interrupt enable for GPIO 74                                       */
      __IOM uint32_t OUTCFG74   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 74                              */
      __IOM uint32_t DS74       : 2;            /*!< [11..10] Drive strength selection for GPIO 74                             */
      __IOM uint32_t SR74       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG74  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 74                        */
      __IOM uint32_t NCESRC74   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 74, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL74   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 74                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN74     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN74     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG74_b;
  } ;

  union {
    __IOM uint32_t PINCFG75;                    /*!< (@ 0x0000012C) Controls the operation of GPIO pin 75.                     */

    struct {
      __IOM uint32_t FNCSEL75   : 4;            /*!< [3..0] Function select for GPIO pin 75                                    */
      __IOM uint32_t INPEN75    : 1;            /*!< [4..4] Input enable for GPIO 75                                           */
      __IOM uint32_t RDZERO75   : 1;            /*!< [5..5] Return 0 for read data on GPIO 75                                  */
      __IOM uint32_t IRPTEN75   : 2;            /*!< [7..6] Interrupt enable for GPIO 75                                       */
      __IOM uint32_t OUTCFG75   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 75                              */
      __IOM uint32_t DS75       : 2;            /*!< [11..10] Drive strength selection for GPIO 75                             */
      __IOM uint32_t SR75       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG75  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 75                        */
      __IOM uint32_t NCESRC75   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 75, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL75   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 75                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN75     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN75     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG75_b;
  } ;

  union {
    __IOM uint32_t PINCFG76;                    /*!< (@ 0x00000130) Controls the operation of GPIO pin 76.                     */

    struct {
      __IOM uint32_t FNCSEL76   : 4;            /*!< [3..0] Function select for GPIO pin 76                                    */
      __IOM uint32_t INPEN76    : 1;            /*!< [4..4] Input enable for GPIO 76                                           */
      __IOM uint32_t RDZERO76   : 1;            /*!< [5..5] Return 0 for read data on GPIO 76                                  */
      __IOM uint32_t IRPTEN76   : 2;            /*!< [7..6] Interrupt enable for GPIO 76                                       */
      __IOM uint32_t OUTCFG76   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 76                              */
      __IOM uint32_t DS76       : 2;            /*!< [11..10] Drive strength selection for GPIO 76                             */
      __IOM uint32_t SR76       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG76  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 76                        */
      __IOM uint32_t NCESRC76   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 76, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL76   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 76                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN76     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN76     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG76_b;
  } ;

  union {
    __IOM uint32_t PINCFG77;                    /*!< (@ 0x00000134) Controls the operation of GPIO pin 77.                     */

    struct {
      __IOM uint32_t FNCSEL77   : 4;            /*!< [3..0] Function select for GPIO pin 77                                    */
      __IOM uint32_t INPEN77    : 1;            /*!< [4..4] Input enable for GPIO 77                                           */
      __IOM uint32_t RDZERO77   : 1;            /*!< [5..5] Return 0 for read data on GPIO 77                                  */
      __IOM uint32_t IRPTEN77   : 2;            /*!< [7..6] Interrupt enable for GPIO 77                                       */
      __IOM uint32_t OUTCFG77   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 77                              */
      __IOM uint32_t DS77       : 2;            /*!< [11..10] Drive strength selection for GPIO 77                             */
      __IOM uint32_t SR77       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG77  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 77                        */
      __IOM uint32_t NCESRC77   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 77, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL77   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 77                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN77     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN77     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG77_b;
  } ;

  union {
    __IOM uint32_t PINCFG78;                    /*!< (@ 0x00000138) Controls the operation of GPIO pin 78.                     */

    struct {
      __IOM uint32_t FNCSEL78   : 4;            /*!< [3..0] Function select for GPIO pin 78                                    */
      __IOM uint32_t INPEN78    : 1;            /*!< [4..4] Input enable for GPIO 78                                           */
      __IOM uint32_t RDZERO78   : 1;            /*!< [5..5] Return 0 for read data on GPIO 78                                  */
      __IOM uint32_t IRPTEN78   : 2;            /*!< [7..6] Interrupt enable for GPIO 78                                       */
      __IOM uint32_t OUTCFG78   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 78                              */
      __IOM uint32_t DS78       : 2;            /*!< [11..10] Drive strength selection for GPIO 78                             */
      __IOM uint32_t SR78       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG78  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 78                        */
      __IOM uint32_t NCESRC78   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 78, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL78   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 78                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN78     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN78     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG78_b;
  } ;

  union {
    __IOM uint32_t PINCFG79;                    /*!< (@ 0x0000013C) Controls the operation of GPIO pin 79.                     */

    struct {
      __IOM uint32_t FNCSEL79   : 4;            /*!< [3..0] Function select for GPIO pin 79                                    */
      __IOM uint32_t INPEN79    : 1;            /*!< [4..4] Input enable for GPIO 79                                           */
      __IOM uint32_t RDZERO79   : 1;            /*!< [5..5] Return 0 for read data on GPIO 79                                  */
      __IOM uint32_t IRPTEN79   : 2;            /*!< [7..6] Interrupt enable for GPIO 79                                       */
      __IOM uint32_t OUTCFG79   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 79                              */
      __IOM uint32_t DS79       : 2;            /*!< [11..10] Drive strength selection for GPIO 79                             */
      __IOM uint32_t SR79       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG79  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 79                        */
      __IOM uint32_t NCESRC79   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 79, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL79   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 79                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN79     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN79     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG79_b;
  } ;

  union {
    __IOM uint32_t PINCFG80;                    /*!< (@ 0x00000140) Controls the operation of GPIO pin 80.                     */

    struct {
      __IOM uint32_t FNCSEL80   : 4;            /*!< [3..0] Function select for GPIO pin 80                                    */
      __IOM uint32_t INPEN80    : 1;            /*!< [4..4] Input enable for GPIO 80                                           */
      __IOM uint32_t RDZERO80   : 1;            /*!< [5..5] Return 0 for read data on GPIO 80                                  */
      __IOM uint32_t IRPTEN80   : 2;            /*!< [7..6] Interrupt enable for GPIO 80                                       */
      __IOM uint32_t OUTCFG80   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 80                              */
      __IOM uint32_t DS80       : 2;            /*!< [11..10] Drive strength selection for GPIO 80                             */
      __IOM uint32_t SR80       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG80  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 80                        */
      __IOM uint32_t NCESRC80   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 80, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL80   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 80                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN80     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN80     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG80_b;
  } ;

  union {
    __IOM uint32_t PINCFG81;                    /*!< (@ 0x00000144) Controls the operation of GPIO pin 81.                     */

    struct {
      __IOM uint32_t FNCSEL81   : 4;            /*!< [3..0] Function select for GPIO pin 81                                    */
      __IOM uint32_t INPEN81    : 1;            /*!< [4..4] Input enable for GPIO 81                                           */
      __IOM uint32_t RDZERO81   : 1;            /*!< [5..5] Return 0 for read data on GPIO 81                                  */
      __IOM uint32_t IRPTEN81   : 2;            /*!< [7..6] Interrupt enable for GPIO 81                                       */
      __IOM uint32_t OUTCFG81   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 81                              */
      __IOM uint32_t DS81       : 2;            /*!< [11..10] Drive strength selection for GPIO 81                             */
      __IOM uint32_t SR81       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG81  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 81                        */
      __IOM uint32_t NCESRC81   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 81, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL81   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 81                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN81     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN81     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG81_b;
  } ;

  union {
    __IOM uint32_t PINCFG82;                    /*!< (@ 0x00000148) Controls the operation of GPIO pin 82.                     */

    struct {
      __IOM uint32_t FNCSEL82   : 4;            /*!< [3..0] Function select for GPIO pin 82                                    */
      __IOM uint32_t INPEN82    : 1;            /*!< [4..4] Input enable for GPIO 82                                           */
      __IOM uint32_t RDZERO82   : 1;            /*!< [5..5] Return 0 for read data on GPIO 82                                  */
      __IOM uint32_t IRPTEN82   : 2;            /*!< [7..6] Interrupt enable for GPIO 82                                       */
      __IOM uint32_t OUTCFG82   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 82                              */
      __IOM uint32_t DS82       : 2;            /*!< [11..10] Drive strength selection for GPIO 82                             */
      __IOM uint32_t SR82       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG82  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 82                        */
      __IOM uint32_t NCESRC82   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 82, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL82   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 82                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN82     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN82     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG82_b;
  } ;

  union {
    __IOM uint32_t PINCFG83;                    /*!< (@ 0x0000014C) Controls the operation of GPIO pin 83.                     */

    struct {
      __IOM uint32_t FNCSEL83   : 4;            /*!< [3..0] Function select for GPIO pin 83                                    */
      __IOM uint32_t INPEN83    : 1;            /*!< [4..4] Input enable for GPIO 83                                           */
      __IOM uint32_t RDZERO83   : 1;            /*!< [5..5] Return 0 for read data on GPIO 83                                  */
      __IOM uint32_t IRPTEN83   : 2;            /*!< [7..6] Interrupt enable for GPIO 83                                       */
      __IOM uint32_t OUTCFG83   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 83                              */
      __IOM uint32_t DS83       : 2;            /*!< [11..10] Drive strength selection for GPIO 83                             */
      __IOM uint32_t SR83       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG83  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 83                        */
      __IOM uint32_t NCESRC83   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 83, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL83   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 83                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN83     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN83     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG83_b;
  } ;

  union {
    __IOM uint32_t PINCFG84;                    /*!< (@ 0x00000150) Controls the operation of GPIO pin 84.                     */

    struct {
      __IOM uint32_t FNCSEL84   : 4;            /*!< [3..0] Function select for GPIO pin 84                                    */
      __IOM uint32_t INPEN84    : 1;            /*!< [4..4] Input enable for GPIO 84                                           */
      __IOM uint32_t RDZERO84   : 1;            /*!< [5..5] Return 0 for read data on GPIO 84                                  */
      __IOM uint32_t IRPTEN84   : 2;            /*!< [7..6] Interrupt enable for GPIO 84                                       */
      __IOM uint32_t OUTCFG84   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 84                              */
      __IOM uint32_t DS84       : 2;            /*!< [11..10] Drive strength selection for GPIO 84                             */
      __IOM uint32_t SR84       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG84  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 84                        */
      __IOM uint32_t NCESRC84   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 84, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL84   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 84                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN84     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN84     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG84_b;
  } ;

  union {
    __IOM uint32_t PINCFG85;                    /*!< (@ 0x00000154) Controls the operation of GPIO pin 85.                     */

    struct {
      __IOM uint32_t FNCSEL85   : 4;            /*!< [3..0] Function select for GPIO pin 85                                    */
      __IOM uint32_t INPEN85    : 1;            /*!< [4..4] Input enable for GPIO 85                                           */
      __IOM uint32_t RDZERO85   : 1;            /*!< [5..5] Return 0 for read data on GPIO 85                                  */
      __IOM uint32_t IRPTEN85   : 2;            /*!< [7..6] Interrupt enable for GPIO 85                                       */
      __IOM uint32_t OUTCFG85   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 85                              */
      __IOM uint32_t DS85       : 2;            /*!< [11..10] Drive strength selection for GPIO 85                             */
      __IOM uint32_t SR85       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG85  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 85                        */
      __IOM uint32_t NCESRC85   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 85, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL85   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 85                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN85     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN85     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG85_b;
  } ;

  union {
    __IOM uint32_t PINCFG86;                    /*!< (@ 0x00000158) Controls the operation of GPIO pin 86.                     */

    struct {
      __IOM uint32_t FNCSEL86   : 4;            /*!< [3..0] Function select for GPIO pin 86                                    */
      __IOM uint32_t INPEN86    : 1;            /*!< [4..4] Input enable for GPIO 86                                           */
      __IOM uint32_t RDZERO86   : 1;            /*!< [5..5] Return 0 for read data on GPIO 86                                  */
      __IOM uint32_t IRPTEN86   : 2;            /*!< [7..6] Interrupt enable for GPIO 86                                       */
      __IOM uint32_t OUTCFG86   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 86                              */
      __IOM uint32_t DS86       : 2;            /*!< [11..10] Drive strength selection for GPIO 86                             */
      __IOM uint32_t SR86       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG86  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 86                        */
      __IOM uint32_t NCESRC86   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 86, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL86   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 86                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN86     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN86     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG86_b;
  } ;

  union {
    __IOM uint32_t PINCFG87;                    /*!< (@ 0x0000015C) Controls the operation of GPIO pin 87.                     */

    struct {
      __IOM uint32_t FNCSEL87   : 4;            /*!< [3..0] Function select for GPIO pin 87                                    */
      __IOM uint32_t INPEN87    : 1;            /*!< [4..4] Input enable for GPIO 87                                           */
      __IOM uint32_t RDZERO87   : 1;            /*!< [5..5] Return 0 for read data on GPIO 87                                  */
      __IOM uint32_t IRPTEN87   : 2;            /*!< [7..6] Interrupt enable for GPIO 87                                       */
      __IOM uint32_t OUTCFG87   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 87                              */
      __IOM uint32_t DS87       : 2;            /*!< [11..10] Drive strength selection for GPIO 87                             */
      __IOM uint32_t SR87       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG87  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 87                        */
      __IOM uint32_t NCESRC87   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 87, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL87   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 87                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN87     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN87     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG87_b;
  } ;

  union {
    __IOM uint32_t PINCFG88;                    /*!< (@ 0x00000160) Controls the operation of GPIO pin 88.                     */

    struct {
      __IOM uint32_t FNCSEL88   : 4;            /*!< [3..0] Function select for GPIO pin 88                                    */
      __IOM uint32_t INPEN88    : 1;            /*!< [4..4] Input enable for GPIO 88                                           */
      __IOM uint32_t RDZERO88   : 1;            /*!< [5..5] Return 0 for read data on GPIO 88                                  */
      __IOM uint32_t IRPTEN88   : 2;            /*!< [7..6] Interrupt enable for GPIO 88                                       */
      __IOM uint32_t OUTCFG88   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 88                              */
      __IOM uint32_t DS88       : 2;            /*!< [11..10] Drive strength selection for GPIO 88                             */
      __IOM uint32_t SR88       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG88  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 88                        */
      __IOM uint32_t NCESRC88   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 88, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL88   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 88                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN88     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN88     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG88_b;
  } ;

  union {
    __IOM uint32_t PINCFG89;                    /*!< (@ 0x00000164) Controls the operation of GPIO pin 89.                     */

    struct {
      __IOM uint32_t FNCSEL89   : 4;            /*!< [3..0] Function select for GPIO pin 89                                    */
      __IOM uint32_t INPEN89    : 1;            /*!< [4..4] Input enable for GPIO 89                                           */
      __IOM uint32_t RDZERO89   : 1;            /*!< [5..5] Return 0 for read data on GPIO 89                                  */
      __IOM uint32_t IRPTEN89   : 2;            /*!< [7..6] Interrupt enable for GPIO 89                                       */
      __IOM uint32_t OUTCFG89   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 89                              */
      __IOM uint32_t DS89       : 2;            /*!< [11..10] Drive strength selection for GPIO 89                             */
      __IOM uint32_t SR89       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG89  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 89                        */
      __IOM uint32_t NCESRC89   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 89, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL89   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 89                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN89     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN89     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG89_b;
  } ;

  union {
    __IOM uint32_t PINCFG90;                    /*!< (@ 0x00000168) Controls the operation of GPIO pin 90.                     */

    struct {
      __IOM uint32_t FNCSEL90   : 4;            /*!< [3..0] Function select for GPIO pin 90                                    */
      __IOM uint32_t INPEN90    : 1;            /*!< [4..4] Input enable for GPIO 90                                           */
      __IOM uint32_t RDZERO90   : 1;            /*!< [5..5] Return 0 for read data on GPIO 90                                  */
      __IOM uint32_t IRPTEN90   : 2;            /*!< [7..6] Interrupt enable for GPIO 90                                       */
      __IOM uint32_t OUTCFG90   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 90                              */
      __IOM uint32_t DS90       : 2;            /*!< [11..10] Drive strength selection for GPIO 90                             */
      __IOM uint32_t SR90       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG90  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 90                        */
      __IOM uint32_t NCESRC90   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 90, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL90   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 90                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN90     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN90     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG90_b;
  } ;

  union {
    __IOM uint32_t PINCFG91;                    /*!< (@ 0x0000016C) Controls the operation of GPIO pin 91.                     */

    struct {
      __IOM uint32_t FNCSEL91   : 4;            /*!< [3..0] Function select for GPIO pin 91                                    */
      __IOM uint32_t INPEN91    : 1;            /*!< [4..4] Input enable for GPIO 91                                           */
      __IOM uint32_t RDZERO91   : 1;            /*!< [5..5] Return 0 for read data on GPIO 91                                  */
      __IOM uint32_t IRPTEN91   : 2;            /*!< [7..6] Interrupt enable for GPIO 91                                       */
      __IOM uint32_t OUTCFG91   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 91                              */
      __IOM uint32_t DS91       : 2;            /*!< [11..10] Drive strength selection for GPIO 91                             */
      __IOM uint32_t SR91       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG91  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 91                        */
      __IOM uint32_t NCESRC91   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 91, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL91   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 91                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN91     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN91     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG91_b;
  } ;

  union {
    __IOM uint32_t PINCFG92;                    /*!< (@ 0x00000170) Controls the operation of GPIO pin 92.                     */

    struct {
      __IOM uint32_t FNCSEL92   : 4;            /*!< [3..0] Function select for GPIO pin 92                                    */
      __IOM uint32_t INPEN92    : 1;            /*!< [4..4] Input enable for GPIO 92                                           */
      __IOM uint32_t RDZERO92   : 1;            /*!< [5..5] Return 0 for read data on GPIO 92                                  */
      __IOM uint32_t IRPTEN92   : 2;            /*!< [7..6] Interrupt enable for GPIO 92                                       */
      __IOM uint32_t OUTCFG92   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 92                              */
      __IOM uint32_t DS92       : 2;            /*!< [11..10] Drive strength selection for GPIO 92                             */
      __IOM uint32_t SR92       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG92  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 92                        */
      __IOM uint32_t NCESRC92   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 92, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL92   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 92                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN92     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN92     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG92_b;
  } ;

  union {
    __IOM uint32_t PINCFG93;                    /*!< (@ 0x00000174) Controls the operation of GPIO pin 93.                     */

    struct {
      __IOM uint32_t FNCSEL93   : 4;            /*!< [3..0] Function select for GPIO pin 93                                    */
      __IOM uint32_t INPEN93    : 1;            /*!< [4..4] Input enable for GPIO 93                                           */
      __IOM uint32_t RDZERO93   : 1;            /*!< [5..5] Return 0 for read data on GPIO 93                                  */
      __IOM uint32_t IRPTEN93   : 2;            /*!< [7..6] Interrupt enable for GPIO 93                                       */
      __IOM uint32_t OUTCFG93   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 93                              */
      __IOM uint32_t DS93       : 2;            /*!< [11..10] Drive strength selection for GPIO 93                             */
      __IOM uint32_t SR93       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG93  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 93                        */
      __IOM uint32_t NCESRC93   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 93, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL93   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 93                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN93     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN93     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG93_b;
  } ;

  union {
    __IOM uint32_t PINCFG94;                    /*!< (@ 0x00000178) Controls the operation of GPIO pin 94.                     */

    struct {
      __IOM uint32_t FNCSEL94   : 4;            /*!< [3..0] Function select for GPIO pin 94                                    */
      __IOM uint32_t INPEN94    : 1;            /*!< [4..4] Input enable for GPIO 94                                           */
      __IOM uint32_t RDZERO94   : 1;            /*!< [5..5] Return 0 for read data on GPIO 94                                  */
      __IOM uint32_t IRPTEN94   : 2;            /*!< [7..6] Interrupt enable for GPIO 94                                       */
      __IOM uint32_t OUTCFG94   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 94                              */
      __IOM uint32_t DS94       : 2;            /*!< [11..10] Drive strength selection for GPIO 94                             */
      __IOM uint32_t SR94       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG94  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 94                        */
      __IOM uint32_t NCESRC94   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 94, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL94   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 94                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN94     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN94     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG94_b;
  } ;

  union {
    __IOM uint32_t PINCFG95;                    /*!< (@ 0x0000017C) Controls the operation of GPIO pin 95.                     */

    struct {
      __IOM uint32_t FNCSEL95   : 4;            /*!< [3..0] Function select for GPIO pin 95                                    */
      __IOM uint32_t INPEN95    : 1;            /*!< [4..4] Input enable for GPIO 95                                           */
      __IOM uint32_t RDZERO95   : 1;            /*!< [5..5] Return 0 for read data on GPIO 95                                  */
      __IOM uint32_t IRPTEN95   : 2;            /*!< [7..6] Interrupt enable for GPIO 95                                       */
      __IOM uint32_t OUTCFG95   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 95                              */
      __IOM uint32_t DS95       : 2;            /*!< [11..10] Drive strength selection for GPIO 95                             */
      __IOM uint32_t SR95       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG95  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 95                        */
      __IOM uint32_t NCESRC95   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 95, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL95   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 95                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN95     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN95     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG95_b;
  } ;

  union {
    __IOM uint32_t PINCFG96;                    /*!< (@ 0x00000180) Controls the operation of GPIO pin 96.                     */

    struct {
      __IOM uint32_t FNCSEL96   : 4;            /*!< [3..0] Function select for GPIO pin 96                                    */
      __IOM uint32_t INPEN96    : 1;            /*!< [4..4] Input enable for GPIO 96                                           */
      __IOM uint32_t RDZERO96   : 1;            /*!< [5..5] Return 0 for read data on GPIO 96                                  */
      __IOM uint32_t IRPTEN96   : 2;            /*!< [7..6] Interrupt enable for GPIO 96                                       */
      __IOM uint32_t OUTCFG96   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 96                              */
      __IOM uint32_t DS96       : 2;            /*!< [11..10] Drive strength selection for GPIO 96                             */
      __IOM uint32_t SR96       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG96  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 96                        */
      __IOM uint32_t NCESRC96   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 96, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL96   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 96                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN96     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN96     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG96_b;
  } ;

  union {
    __IOM uint32_t PINCFG97;                    /*!< (@ 0x00000184) Controls the operation of GPIO pin 97.                     */

    struct {
      __IOM uint32_t FNCSEL97   : 4;            /*!< [3..0] Function select for GPIO pin 97                                    */
      __IOM uint32_t INPEN97    : 1;            /*!< [4..4] Input enable for GPIO 97                                           */
      __IOM uint32_t RDZERO97   : 1;            /*!< [5..5] Return 0 for read data on GPIO 97                                  */
      __IOM uint32_t IRPTEN97   : 2;            /*!< [7..6] Interrupt enable for GPIO 97                                       */
      __IOM uint32_t OUTCFG97   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 97                              */
      __IOM uint32_t DS97       : 2;            /*!< [11..10] Drive strength selection for GPIO 97                             */
      __IOM uint32_t SR97       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG97  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 97                        */
      __IOM uint32_t NCESRC97   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 97, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL97   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 97                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN97     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN97     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG97_b;
  } ;

  union {
    __IOM uint32_t PINCFG98;                    /*!< (@ 0x00000188) Controls the operation of GPIO pin 98.                     */

    struct {
      __IOM uint32_t FNCSEL98   : 4;            /*!< [3..0] Function select for GPIO pin 98                                    */
      __IOM uint32_t INPEN98    : 1;            /*!< [4..4] Input enable for GPIO 98                                           */
      __IOM uint32_t RDZERO98   : 1;            /*!< [5..5] Return 0 for read data on GPIO 98                                  */
      __IOM uint32_t IRPTEN98   : 2;            /*!< [7..6] Interrupt enable for GPIO 98                                       */
      __IOM uint32_t OUTCFG98   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 98                              */
      __IOM uint32_t DS98       : 2;            /*!< [11..10] Drive strength selection for GPIO 98                             */
      __IOM uint32_t SR98       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG98  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 98                        */
      __IOM uint32_t NCESRC98   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 98, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL98   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 98                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN98     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN98     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG98_b;
  } ;

  union {
    __IOM uint32_t PINCFG99;                    /*!< (@ 0x0000018C) Controls the operation of GPIO pin 99.                     */

    struct {
      __IOM uint32_t FNCSEL99   : 4;            /*!< [3..0] Function select for GPIO pin 99                                    */
      __IOM uint32_t INPEN99    : 1;            /*!< [4..4] Input enable for GPIO 99                                           */
      __IOM uint32_t RDZERO99   : 1;            /*!< [5..5] Return 0 for read data on GPIO 99                                  */
      __IOM uint32_t IRPTEN99   : 2;            /*!< [7..6] Interrupt enable for GPIO 99                                       */
      __IOM uint32_t OUTCFG99   : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 99                              */
      __IOM uint32_t DS99       : 2;            /*!< [11..10] Drive strength selection for GPIO 99                             */
      __IOM uint32_t SR99       : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG99  : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 99                        */
      __IOM uint32_t NCESRC99   : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 99, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL99   : 1;            /*!< [22..22] Polarity select for NCE for GPIO 99                              */
            uint32_t            : 3;
      __IOM uint32_t FIEN99     : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN99     : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG99_b;
  } ;

  union {
    __IOM uint32_t PINCFG100;                   /*!< (@ 0x00000190) Controls the operation of GPIO pin 100.                    */

    struct {
      __IOM uint32_t FNCSEL100  : 4;            /*!< [3..0] Function select for GPIO pin 100                                   */
      __IOM uint32_t INPEN100   : 1;            /*!< [4..4] Input enable for GPIO 100                                          */
      __IOM uint32_t RDZERO100  : 1;            /*!< [5..5] Return 0 for read data on GPIO 100                                 */
      __IOM uint32_t IRPTEN100  : 2;            /*!< [7..6] Interrupt enable for GPIO 100                                      */
      __IOM uint32_t OUTCFG100  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 100                             */
      __IOM uint32_t DS100      : 2;            /*!< [11..10] Drive strength selection for GPIO 100                            */
      __IOM uint32_t SR100      : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG100 : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 100                       */
      __IOM uint32_t NCESRC100  : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 100, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL100  : 1;            /*!< [22..22] Polarity select for NCE for GPIO 100                             */
            uint32_t            : 3;
      __IOM uint32_t FIEN100    : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN100    : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG100_b;
  } ;

  union {
    __IOM uint32_t PINCFG101;                   /*!< (@ 0x00000194) Controls the operation of GPIO pin 101.                    */

    struct {
      __IOM uint32_t FNCSEL101  : 4;            /*!< [3..0] Function select for GPIO pin 101                                   */
      __IOM uint32_t INPEN101   : 1;            /*!< [4..4] Input enable for GPIO 101                                          */
      __IOM uint32_t RDZERO101  : 1;            /*!< [5..5] Return 0 for read data on GPIO 101                                 */
      __IOM uint32_t IRPTEN101  : 2;            /*!< [7..6] Interrupt enable for GPIO 101                                      */
      __IOM uint32_t OUTCFG101  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 101                             */
      __IOM uint32_t DS101      : 2;            /*!< [11..10] Drive strength selection for GPIO 101                            */
      __IOM uint32_t SR101      : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG101 : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 101                       */
      __IOM uint32_t NCESRC101  : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 101, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL101  : 1;            /*!< [22..22] Polarity select for NCE for GPIO 101                             */
            uint32_t            : 3;
      __IOM uint32_t FIEN101    : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN101    : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG101_b;
  } ;

  union {
    __IOM uint32_t PINCFG102;                   /*!< (@ 0x00000198) Controls the operation of GPIO pin 102.                    */

    struct {
      __IOM uint32_t FNCSEL102  : 4;            /*!< [3..0] Function select for GPIO pin 102                                   */
      __IOM uint32_t INPEN102   : 1;            /*!< [4..4] Input enable for GPIO 102                                          */
      __IOM uint32_t RDZERO102  : 1;            /*!< [5..5] Return 0 for read data on GPIO 102                                 */
      __IOM uint32_t IRPTEN102  : 2;            /*!< [7..6] Interrupt enable for GPIO 102                                      */
      __IOM uint32_t OUTCFG102  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 102                             */
      __IOM uint32_t DS102      : 2;            /*!< [11..10] Drive strength selection for GPIO 102                            */
      __IOM uint32_t SR102      : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG102 : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 102                       */
      __IOM uint32_t NCESRC102  : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 102, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL102  : 1;            /*!< [22..22] Polarity select for NCE for GPIO 102                             */
            uint32_t            : 3;
      __IOM uint32_t FIEN102    : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN102    : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG102_b;
  } ;

  union {
    __IOM uint32_t PINCFG103;                   /*!< (@ 0x0000019C) Controls the operation of GPIO pin 103.                    */

    struct {
      __IOM uint32_t FNCSEL103  : 4;            /*!< [3..0] Function select for GPIO pin 103                                   */
      __IOM uint32_t INPEN103   : 1;            /*!< [4..4] Input enable for GPIO 103                                          */
      __IOM uint32_t RDZERO103  : 1;            /*!< [5..5] Return 0 for read data on GPIO 103                                 */
      __IOM uint32_t IRPTEN103  : 2;            /*!< [7..6] Interrupt enable for GPIO 103                                      */
      __IOM uint32_t OUTCFG103  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 103                             */
      __IOM uint32_t DS103      : 2;            /*!< [11..10] Drive strength selection for GPIO 103                            */
      __IOM uint32_t SR103      : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG103 : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 103                       */
      __IOM uint32_t NCESRC103  : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 103, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL103  : 1;            /*!< [22..22] Polarity select for NCE for GPIO 103                             */
            uint32_t            : 3;
      __IOM uint32_t FIEN103    : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN103    : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG103_b;
  } ;

  union {
    __IOM uint32_t PINCFG104;                   /*!< (@ 0x000001A0) Controls the operation of GPIO pin 104.                    */

    struct {
      __IOM uint32_t FNCSEL104  : 4;            /*!< [3..0] Function select for GPIO pin 104                                   */
      __IOM uint32_t INPEN104   : 1;            /*!< [4..4] Input enable for GPIO 104                                          */
      __IOM uint32_t RDZERO104  : 1;            /*!< [5..5] Return 0 for read data on GPIO 104                                 */
      __IOM uint32_t IRPTEN104  : 2;            /*!< [7..6] Interrupt enable for GPIO 104                                      */
      __IOM uint32_t OUTCFG104  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 104                             */
      __IOM uint32_t DS104      : 2;            /*!< [11..10] Drive strength selection for GPIO 104                            */
      __IOM uint32_t SR104      : 1;            /*!< [12..12] Configure the slew rate                                          */
      __IOM uint32_t PULLCFG104 : 3;            /*!< [15..13] Pullup/Pulldown configuration for GPIO 104                       */
      __IOM uint32_t NCESRC104  : 6;            /*!< [21..16] IOMSTR/MSPI N Chip Select 104, DISP control signals
                                                     DE, CSX, and CS. Polarity is determined by CE_POLARITY
                                                     field                                                                     */
      __IOM uint32_t NCEPOL104  : 1;            /*!< [22..22] Polarity select for NCE for GPIO 104                             */
            uint32_t            : 3;
      __IOM uint32_t FIEN104    : 1;            /*!< [26..26] Force input enable active regardless of function selected.
                                                     Otherwise the selected function will enable the input only
                                                     when needed                                                               */
      __IOM uint32_t FOEN104    : 1;            /*!< [27..27] Force output enable active regardless of function selected.
                                                     Otherwise the selected function will enable the output
                                                     only when needed                                                          */
            uint32_t            : 4;
    } PINCFG104_b;
  } ;

  union {
    __IOM uint32_t PINCFG105;                   /*!< (@ 0x000001A4) Controls the operation of virtual GPIO pin 105.            */

    struct {
      __IOM uint32_t FNCSEL105  : 4;            /*!< [3..0] Function select for GPIO pin 105                                   */
      __IOM uint32_t INPEN105   : 1;            /*!< [4..4] Input enable for GPIO 105                                          */
      __IOM uint32_t RDZERO105  : 1;            /*!< [5..5] Return 0 for read data on GPIO 105                                 */
      __IOM uint32_t IRPTEN105  : 2;            /*!< [7..6] Interrupt enable for GPIO 105                                      */
      __IOM uint32_t OUTCFG105  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 105                             */
            uint32_t            : 22;
    } PINCFG105_b;
  } ;

  union {
    __IOM uint32_t PINCFG106;                   /*!< (@ 0x000001A8) Controls the operation of virtual GPIO pin 106.            */

    struct {
      __IOM uint32_t FNCSEL106  : 4;            /*!< [3..0] Function select for GPIO pin 106                                   */
      __IOM uint32_t INPEN106   : 1;            /*!< [4..4] Input enable for GPIO 106                                          */
      __IOM uint32_t RDZERO106  : 1;            /*!< [5..5] Return 0 for read data on GPIO 106                                 */
      __IOM uint32_t IRPTEN106  : 2;            /*!< [7..6] Interrupt enable for GPIO 106                                      */
      __IOM uint32_t OUTCFG106  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 106                             */
            uint32_t            : 22;
    } PINCFG106_b;
  } ;

  union {
    __IOM uint32_t PINCFG107;                   /*!< (@ 0x000001AC) Controls the operation of virtual GPIO pin 107.            */

    struct {
      __IOM uint32_t FNCSEL107  : 4;            /*!< [3..0] Function select for GPIO pin 107                                   */
      __IOM uint32_t INPEN107   : 1;            /*!< [4..4] Input enable for GPIO 107                                          */
      __IOM uint32_t RDZERO107  : 1;            /*!< [5..5] Return 0 for read data on GPIO 107                                 */
      __IOM uint32_t IRPTEN107  : 2;            /*!< [7..6] Interrupt enable for GPIO 107                                      */
      __IOM uint32_t OUTCFG107  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 107                             */
            uint32_t            : 22;
    } PINCFG107_b;
  } ;

  union {
    __IOM uint32_t PINCFG108;                   /*!< (@ 0x000001B0) Controls the operation of virtual GPIO pin 108.            */

    struct {
      __IOM uint32_t FNCSEL108  : 4;            /*!< [3..0] Function select for GPIO pin 108                                   */
      __IOM uint32_t INPEN108   : 1;            /*!< [4..4] Input enable for GPIO 108                                          */
      __IOM uint32_t RDZERO108  : 1;            /*!< [5..5] Return 0 for read data on GPIO 108                                 */
      __IOM uint32_t IRPTEN108  : 2;            /*!< [7..6] Interrupt enable for GPIO 108                                      */
      __IOM uint32_t OUTCFG108  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 108                             */
            uint32_t            : 22;
    } PINCFG108_b;
  } ;

  union {
    __IOM uint32_t PINCFG109;                   /*!< (@ 0x000001B4) Controls the operation of virtual GPIO pin 109.            */

    struct {
      __IOM uint32_t FNCSEL109  : 4;            /*!< [3..0] Function select for GPIO pin 109                                   */
      __IOM uint32_t INPEN109   : 1;            /*!< [4..4] Input enable for GPIO 109                                          */
      __IOM uint32_t RDZERO109  : 1;            /*!< [5..5] Return 0 for read data on GPIO 109                                 */
      __IOM uint32_t IRPTEN109  : 2;            /*!< [7..6] Interrupt enable for GPIO 109                                      */
      __IOM uint32_t OUTCFG109  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 109                             */
            uint32_t            : 22;
    } PINCFG109_b;
  } ;

  union {
    __IOM uint32_t PINCFG110;                   /*!< (@ 0x000001B8) Controls the operation of virtual GPIO pin 110.            */

    struct {
      __IOM uint32_t FNCSEL110  : 4;            /*!< [3..0] Function select for GPIO pin 110                                   */
      __IOM uint32_t INPEN110   : 1;            /*!< [4..4] Input enable for GPIO 110                                          */
      __IOM uint32_t RDZERO110  : 1;            /*!< [5..5] Return 0 for read data on GPIO 110                                 */
      __IOM uint32_t IRPTEN110  : 2;            /*!< [7..6] Interrupt enable for GPIO 110                                      */
      __IOM uint32_t OUTCFG110  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 110                             */
            uint32_t            : 22;
    } PINCFG110_b;
  } ;

  union {
    __IOM uint32_t PINCFG111;                   /*!< (@ 0x000001BC) Controls the operation of virtual GPIO pin 111.            */

    struct {
      __IOM uint32_t FNCSEL111  : 4;            /*!< [3..0] Function select for GPIO pin 111                                   */
      __IOM uint32_t INPEN111   : 1;            /*!< [4..4] Input enable for GPIO 111                                          */
      __IOM uint32_t RDZERO111  : 1;            /*!< [5..5] Return 0 for read data on GPIO 111                                 */
      __IOM uint32_t IRPTEN111  : 2;            /*!< [7..6] Interrupt enable for GPIO 111                                      */
      __IOM uint32_t OUTCFG111  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 111                             */
            uint32_t            : 22;
    } PINCFG111_b;
  } ;

  union {
    __IOM uint32_t PINCFG112;                   /*!< (@ 0x000001C0) Controls the operation of virtual GPIO pin 112.            */

    struct {
      __IOM uint32_t FNCSEL112  : 4;            /*!< [3..0] Function select for GPIO pin 112                                   */
      __IOM uint32_t INPEN112   : 1;            /*!< [4..4] Input enable for GPIO 112                                          */
      __IOM uint32_t RDZERO112  : 1;            /*!< [5..5] Return 0 for read data on GPIO 112                                 */
      __IOM uint32_t IRPTEN112  : 2;            /*!< [7..6] Interrupt enable for GPIO 112                                      */
      __IOM uint32_t OUTCFG112  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 112                             */
            uint32_t            : 22;
    } PINCFG112_b;
  } ;

  union {
    __IOM uint32_t PINCFG113;                   /*!< (@ 0x000001C4) Controls the operation of virtual GPIO pin 113.            */

    struct {
      __IOM uint32_t FNCSEL113  : 4;            /*!< [3..0] Function select for GPIO pin 113                                   */
      __IOM uint32_t INPEN113   : 1;            /*!< [4..4] Input enable for GPIO 113                                          */
      __IOM uint32_t RDZERO113  : 1;            /*!< [5..5] Return 0 for read data on GPIO 113                                 */
      __IOM uint32_t IRPTEN113  : 2;            /*!< [7..6] Interrupt enable for GPIO 113                                      */
      __IOM uint32_t OUTCFG113  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 113                             */
            uint32_t            : 22;
    } PINCFG113_b;
  } ;

  union {
    __IOM uint32_t PINCFG114;                   /*!< (@ 0x000001C8) Controls the operation of virtual GPIO pin 114.            */

    struct {
      __IOM uint32_t FNCSEL114  : 4;            /*!< [3..0] Function select for GPIO pin 114                                   */
      __IOM uint32_t INPEN114   : 1;            /*!< [4..4] Input enable for GPIO 114                                          */
      __IOM uint32_t RDZERO114  : 1;            /*!< [5..5] Return 0 for read data on GPIO 114                                 */
      __IOM uint32_t IRPTEN114  : 2;            /*!< [7..6] Interrupt enable for GPIO 114                                      */
      __IOM uint32_t OUTCFG114  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 114                             */
            uint32_t            : 22;
    } PINCFG114_b;
  } ;

  union {
    __IOM uint32_t PINCFG115;                   /*!< (@ 0x000001CC) Controls the operation of virtual GPIO pin 115.            */

    struct {
      __IOM uint32_t FNCSEL115  : 4;            /*!< [3..0] Function select for GPIO pin 115                                   */
      __IOM uint32_t INPEN115   : 1;            /*!< [4..4] Input enable for GPIO 115                                          */
      __IOM uint32_t RDZERO115  : 1;            /*!< [5..5] Return 0 for read data on GPIO 115                                 */
      __IOM uint32_t IRPTEN115  : 2;            /*!< [7..6] Interrupt enable for GPIO 115                                      */
      __IOM uint32_t OUTCFG115  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 115                             */
            uint32_t            : 22;
    } PINCFG115_b;
  } ;

  union {
    __IOM uint32_t PINCFG116;                   /*!< (@ 0x000001D0) Controls the operation of virtual GPIO pin 116.            */

    struct {
      __IOM uint32_t FNCSEL116  : 4;            /*!< [3..0] Function select for GPIO pin 116                                   */
      __IOM uint32_t INPEN116   : 1;            /*!< [4..4] Input enable for GPIO 116                                          */
      __IOM uint32_t RDZERO116  : 1;            /*!< [5..5] Return 0 for read data on GPIO 116                                 */
      __IOM uint32_t IRPTEN116  : 2;            /*!< [7..6] Interrupt enable for GPIO 116                                      */
      __IOM uint32_t OUTCFG116  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 116                             */
            uint32_t            : 22;
    } PINCFG116_b;
  } ;

  union {
    __IOM uint32_t PINCFG117;                   /*!< (@ 0x000001D4) Controls the operation of virtual GPIO pin 117.            */

    struct {
      __IOM uint32_t FNCSEL117  : 4;            /*!< [3..0] Function select for GPIO pin 117                                   */
      __IOM uint32_t INPEN117   : 1;            /*!< [4..4] Input enable for GPIO 117                                          */
      __IOM uint32_t RDZERO117  : 1;            /*!< [5..5] Return 0 for read data on GPIO 117                                 */
      __IOM uint32_t IRPTEN117  : 2;            /*!< [7..6] Interrupt enable for GPIO 117                                      */
      __IOM uint32_t OUTCFG117  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 117                             */
            uint32_t            : 22;
    } PINCFG117_b;
  } ;

  union {
    __IOM uint32_t PINCFG118;                   /*!< (@ 0x000001D8) Controls the operation of virtual GPIO pin 118.            */

    struct {
      __IOM uint32_t FNCSEL118  : 4;            /*!< [3..0] Function select for GPIO pin 118                                   */
      __IOM uint32_t INPEN118   : 1;            /*!< [4..4] Input enable for GPIO 118                                          */
      __IOM uint32_t RDZERO118  : 1;            /*!< [5..5] Return 0 for read data on GPIO 118                                 */
      __IOM uint32_t IRPTEN118  : 2;            /*!< [7..6] Interrupt enable for GPIO 118                                      */
      __IOM uint32_t OUTCFG118  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 118                             */
            uint32_t            : 22;
    } PINCFG118_b;
  } ;

  union {
    __IOM uint32_t PINCFG119;                   /*!< (@ 0x000001DC) Controls the operation of virtual GPIO pin 119.            */

    struct {
      __IOM uint32_t FNCSEL119  : 4;            /*!< [3..0] Function select for GPIO pin 119                                   */
      __IOM uint32_t INPEN119   : 1;            /*!< [4..4] Input enable for GPIO 119                                          */
      __IOM uint32_t RDZERO119  : 1;            /*!< [5..5] Return 0 for read data on GPIO 119                                 */
      __IOM uint32_t IRPTEN119  : 2;            /*!< [7..6] Interrupt enable for GPIO 119                                      */
      __IOM uint32_t OUTCFG119  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 119                             */
            uint32_t            : 22;
    } PINCFG119_b;
  } ;

  union {
    __IOM uint32_t PINCFG120;                   /*!< (@ 0x000001E0) Controls the operation of virtual GPIO pin 120.            */

    struct {
      __IOM uint32_t FNCSEL120  : 4;            /*!< [3..0] Function select for GPIO pin 120                                   */
      __IOM uint32_t INPEN120   : 1;            /*!< [4..4] Input enable for GPIO 120                                          */
      __IOM uint32_t RDZERO120  : 1;            /*!< [5..5] Return 0 for read data on GPIO 120                                 */
      __IOM uint32_t IRPTEN120  : 2;            /*!< [7..6] Interrupt enable for GPIO 120                                      */
      __IOM uint32_t OUTCFG120  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 120                             */
            uint32_t            : 22;
    } PINCFG120_b;
  } ;

  union {
    __IOM uint32_t PINCFG121;                   /*!< (@ 0x000001E4) Controls the operation of virtual GPIO pin 121.            */

    struct {
      __IOM uint32_t FNCSEL121  : 4;            /*!< [3..0] Function select for GPIO pin 121                                   */
      __IOM uint32_t INPEN121   : 1;            /*!< [4..4] Input enable for GPIO 121                                          */
      __IOM uint32_t RDZERO121  : 1;            /*!< [5..5] Return 0 for read data on GPIO 121                                 */
      __IOM uint32_t IRPTEN121  : 2;            /*!< [7..6] Interrupt enable for GPIO 121                                      */
      __IOM uint32_t OUTCFG121  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 121                             */
            uint32_t            : 22;
    } PINCFG121_b;
  } ;

  union {
    __IOM uint32_t PINCFG122;                   /*!< (@ 0x000001E8) Controls the operation of virtual GPIO pin 122.            */

    struct {
      __IOM uint32_t FNCSEL122  : 4;            /*!< [3..0] Function select for GPIO pin 122                                   */
      __IOM uint32_t INPEN122   : 1;            /*!< [4..4] Input enable for GPIO 122                                          */
      __IOM uint32_t RDZERO122  : 1;            /*!< [5..5] Return 0 for read data on GPIO 122                                 */
      __IOM uint32_t IRPTEN122  : 2;            /*!< [7..6] Interrupt enable for GPIO 122                                      */
      __IOM uint32_t OUTCFG122  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 122                             */
            uint32_t            : 22;
    } PINCFG122_b;
  } ;

  union {
    __IOM uint32_t PINCFG123;                   /*!< (@ 0x000001EC) Controls the operation of virtual GPIO pin 123.            */

    struct {
      __IOM uint32_t FNCSEL123  : 4;            /*!< [3..0] Function select for GPIO pin 123                                   */
      __IOM uint32_t INPEN123   : 1;            /*!< [4..4] Input enable for GPIO 123                                          */
      __IOM uint32_t RDZERO123  : 1;            /*!< [5..5] Return 0 for read data on GPIO 123                                 */
      __IOM uint32_t IRPTEN123  : 2;            /*!< [7..6] Interrupt enable for GPIO 123                                      */
      __IOM uint32_t OUTCFG123  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 123                             */
            uint32_t            : 22;
    } PINCFG123_b;
  } ;

  union {
    __IOM uint32_t PINCFG124;                   /*!< (@ 0x000001F0) Controls the operation of virtual GPIO pin 124.            */

    struct {
      __IOM uint32_t FNCSEL124  : 4;            /*!< [3..0] Function select for GPIO pin 124                                   */
      __IOM uint32_t INPEN124   : 1;            /*!< [4..4] Input enable for GPIO 124                                          */
      __IOM uint32_t RDZERO124  : 1;            /*!< [5..5] Return 0 for read data on GPIO 124                                 */
      __IOM uint32_t IRPTEN124  : 2;            /*!< [7..6] Interrupt enable for GPIO 124                                      */
      __IOM uint32_t OUTCFG124  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 124                             */
            uint32_t            : 22;
    } PINCFG124_b;
  } ;

  union {
    __IOM uint32_t PINCFG125;                   /*!< (@ 0x000001F4) Controls the operation of virtual GPIO pin 125.            */

    struct {
      __IOM uint32_t FNCSEL125  : 4;            /*!< [3..0] Function select for GPIO pin 125                                   */
      __IOM uint32_t INPEN125   : 1;            /*!< [4..4] Input enable for GPIO 125                                          */
      __IOM uint32_t RDZERO125  : 1;            /*!< [5..5] Return 0 for read data on GPIO 125                                 */
      __IOM uint32_t IRPTEN125  : 2;            /*!< [7..6] Interrupt enable for GPIO 125                                      */
      __IOM uint32_t OUTCFG125  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 125                             */
            uint32_t            : 22;
    } PINCFG125_b;
  } ;

  union {
    __IOM uint32_t PINCFG126;                   /*!< (@ 0x000001F8) Controls the operation of virtual GPIO pin 126.            */

    struct {
      __IOM uint32_t FNCSEL126  : 4;            /*!< [3..0] Function select for GPIO pin 126                                   */
      __IOM uint32_t INPEN126   : 1;            /*!< [4..4] Input enable for GPIO 126                                          */
      __IOM uint32_t RDZERO126  : 1;            /*!< [5..5] Return 0 for read data on GPIO 126                                 */
      __IOM uint32_t IRPTEN126  : 2;            /*!< [7..6] Interrupt enable for GPIO 126                                      */
      __IOM uint32_t OUTCFG126  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 126                             */
            uint32_t            : 22;
    } PINCFG126_b;
  } ;

  union {
    __IOM uint32_t PINCFG127;                   /*!< (@ 0x000001FC) Controls the operation of virtual GPIO pin 127.            */

    struct {
      __IOM uint32_t FNCSEL127  : 4;            /*!< [3..0] Function select for GPIO pin 127                                   */
      __IOM uint32_t INPEN127   : 1;            /*!< [4..4] Input enable for GPIO 127                                          */
      __IOM uint32_t RDZERO127  : 1;            /*!< [5..5] Return 0 for read data on GPIO 127                                 */
      __IOM uint32_t IRPTEN127  : 2;            /*!< [7..6] Interrupt enable for GPIO 127                                      */
      __IOM uint32_t OUTCFG127  : 2;            /*!< [9..8] Pin IO mode selection for GPIO pin 127                             */
            uint32_t            : 22;
    } PINCFG127_b;
  } ;

  union {
    __IOM uint32_t PADKEY;                      /*!< (@ 0x00000200) Lock state of the PINCFG and GPIO configuration
                                                                    registers. Write a value of 0x73 to unlock
                                                                    write access to the PAD and GPIO.                          */

    struct {
      __IOM uint32_t PADKEY     : 32;           /*!< [31..0] Key register value.                                               */
    } PADKEY_b;
  } ;

  union {
    __IOM uint32_t RD0;                         /*!< (@ 0x00000204) GPIO Input 0 (31-0)                                        */

    struct {
      __IOM uint32_t RD0        : 32;           /*!< [31..0] GPIO31-0 Reads pin state - read only. Returns the pad
                                                     pin state for pins 0-31 if the PINCFG's input enable (INPEN)
                                                     is active and RDZERO is inactive.                                         */
    } RD0_b;
  } ;

  union {
    __IOM uint32_t RD1;                         /*!< (@ 0x00000208) GPIO Input 1 (63-32)                                       */

    struct {
      __IOM uint32_t RD1        : 32;           /*!< [31..0] GPIO63-32 Reads pin state - read only. Returns the pad
                                                     pin state for pins 0-31 if the PINCFG's input enable (INPEN)
                                                     is active and RDZERO is inactive.                                         */
    } RD1_b;
  } ;

  union {
    __IOM uint32_t RD2;                         /*!< (@ 0x0000020C) GPIO Input 2 (95-64)                                       */

    struct {
      __IOM uint32_t RD2        : 32;           /*!< [31..0] GPIO95-64 Reads pin state - read only. Returns the pad
                                                     pin state for pins 0-31 if the PINCFG's input enable (INPEN)
                                                     is active and RDZERO is inactive.                                         */
    } RD2_b;
  } ;

  union {
    __IOM uint32_t RD3;                         /*!< (@ 0x00000210) GPIO Input 3 (127-96)                                      */

    struct {
      __IOM uint32_t RD3        : 32;           /*!< [31..0] GPIO127-96 Reads pin state - read only. Returns the
                                                     pad pin state for pins 0-31 if the PINCFG's input enable
                                                     (INPEN) is active and RDZERO is inactive.                                 */
    } RD3_b;
  } ;

  union {
    __IOM uint32_t WT0;                         /*!< (@ 0x00000214) GPIO Output 0 (31-0)                                       */

    struct {
      __IOM uint32_t WT0        : 32;           /*!< [31..0] GPIO31-0 Reads or writes pin state. Writes of 1 bits
                                                     set output pad signal if the GPIO is enabled for output.
                                                     Reads return status, including sets/clears through the
                                                     WTS and WTC registers.                                                    */
    } WT0_b;
  } ;

  union {
    __IOM uint32_t WT1;                         /*!< (@ 0x00000218) GPIO Output 1 (63-32)                                      */

    struct {
      __IOM uint32_t WT1        : 32;           /*!< [31..0] GPIO63-32 Reads or writes pin state. Writes of 1 bits
                                                     set output pad signal if the GPIO is enabled for output.
                                                     Reads return status, including sets/clears through the
                                                     WTS and WTC registers.                                                    */
    } WT1_b;
  } ;

  union {
    __IOM uint32_t WT2;                         /*!< (@ 0x0000021C) GPIO Output 2 (95-64)                                      */

    struct {
      __IOM uint32_t WT2        : 32;           /*!< [31..0] GPIO95-64 Reads or writes pin state. Writes of 1 bits
                                                     set output pad signal if the GPIO is enabled for output.
                                                     Reads return status, including sets/clears through the
                                                     WTS and WTC registers.                                                    */
    } WT2_b;
  } ;

  union {
    __IOM uint32_t WT3;                         /*!< (@ 0x00000220) GPIO Output 3 (127-96)                                     */

    struct {
      __IOM uint32_t WT3        : 32;           /*!< [31..0] GPIO127-96 Reads or writes pin state. Writes of 1 bits
                                                     set output pad signal if the GPIO is enabled for output.
                                                     Reads return status, including sets/clears through the
                                                     WTS and WTC registers.                                                    */
    } WT3_b;
  } ;

  union {
    __IOM uint32_t WTS0;                        /*!< (@ 0x00000224) GPIO Output Set 0 (31-0)                                   */

    struct {
      __IOM uint32_t WTS0       : 32;           /*!< [31..0] GPIO31-0 Sets pin state. Writing a 1 to any bit sets
                                                     the corresponding bit in the WT register if the GPIO is
                                                     enabled for output. Writing a value of 0 has no effect
                                                     on the corresponding bit in the WT register. Status reads
                                                     should be made via the WT Register.                                       */
    } WTS0_b;
  } ;

  union {
    __IOM uint32_t WTS1;                        /*!< (@ 0x00000228) GPIO Output Set 1 (63-32)                                  */

    struct {
      __IOM uint32_t WTS1       : 32;           /*!< [31..0] GPIO63-32 Sets pin state. Writing a 1 to any bit sets
                                                     the corresponding bit in the WT register if the GPIO is
                                                     enabled for output. Writing a value of 0 has no effect
                                                     on the corresponding bit in the WT register. Status reads
                                                     should be made via the WT Register.                                       */
    } WTS1_b;
  } ;

  union {
    __IOM uint32_t WTS2;                        /*!< (@ 0x0000022C) GPIO Output Set 2 (95-64)                                  */

    struct {
      __IOM uint32_t WTS2       : 32;           /*!< [31..0] GPIO95-64 Sets pin state. Writing a 1 to any bit sets
                                                     the corresponding bit in the WT register if the GPIO is
                                                     enabled for output. Writing a value of 0 has no effect
                                                     on the corresponding bit in the WT register. Status reads
                                                     should be made via the WT Register.                                       */
    } WTS2_b;
  } ;

  union {
    __IOM uint32_t WTS3;                        /*!< (@ 0x00000230) GPIO Output Set 3 (127-96)                                 */

    struct {
      __IOM uint32_t WTS3       : 32;           /*!< [31..0] GPIO127-96 Sets pin state. Writing a 1 to any bit sets
                                                     the corresponding bit in the WT register if the GPIO is
                                                     enabled for output. Writing a value of 0 has no effect
                                                     on the corresponding bit in the WT register. Status reads
                                                     should be made via the WT Register.                                       */
    } WTS3_b;
  } ;

  union {
    __IOM uint32_t WTC0;                        /*!< (@ 0x00000234) GPIO Output Clear 0 (31-0)                                 */

    struct {
      __IOM uint32_t WTC0       : 32;           /*!< [31..0] GPIO31-0 Clears pin state. Writing a 1 to any bit clears
                                                     the corresponding bit in the WT register if the GPIO is
                                                     enabled for output. Writing a value of 0 has no effect
                                                     on the corresponding bit in the WT register. Status reads
                                                     should be made via the WT register.                                       */
    } WTC0_b;
  } ;

  union {
    __IOM uint32_t WTC1;                        /*!< (@ 0x00000238) GPIO Output Clear 1 (63-32)                                */

    struct {
      __IOM uint32_t WTC1       : 32;           /*!< [31..0] GPIO63-32 Clears pin state. Writing a 1 to any bit clears
                                                     the corresponding bit in the WT register if the GPIO is
                                                     enabled for output. Writing a value of 0 has no effect
                                                     on the corresponding bit in the WT register. Status reads
                                                     should be made via the WT register.                                       */
    } WTC1_b;
  } ;

  union {
    __IOM uint32_t WTC2;                        /*!< (@ 0x0000023C) GPIO Output Clear 2 (95-64)                                */

    struct {
      __IOM uint32_t WTC2       : 32;           /*!< [31..0] GPIO95-64 Clears pin state. Writing a 1 to any bit clears
                                                     the corresponding bit in the WT register if the GPIO is
                                                     enabled for output. Writing a value of 0 has no effect
                                                     on the corresponding bit in the WT register. Status reads
                                                     should be made via the WT register.                                       */
    } WTC2_b;
  } ;

  union {
    __IOM uint32_t WTC3;                        /*!< (@ 0x00000240) GPIO Output Clear 3 (127-96)                               */

    struct {
      __IOM uint32_t WTC3       : 32;           /*!< [31..0] GPIO127-96 Clears pin state. Writing a 1 to any bit
                                                     clears the corresponding bit in the WT register if the
                                                     GPIO is enabled for output. Writing a value of 0 has no
                                                     effect on the corresponding bit in the WT register. Status
                                                     reads should be made via the WT register.                                 */
    } WTC3_b;
  } ;

  union {
    __IOM uint32_t EN0;                         /*!< (@ 0x00000244) GPIO Enable 0 (31-0)                                       */

    struct {
      __IOM uint32_t EN0        : 32;           /*!< [31..0] GPIO31-0 Enables tri-state pin output. Writing a 1 to
                                                     any bit enables, and writing a 0 to any bit disables, the
                                                     output for the corresponding GPIO. Reads return output
                                                     enable/disable status of GPIO.                                            */
    } EN0_b;
  } ;

  union {
    __IOM uint32_t EN1;                         /*!< (@ 0x00000248) GPIO Enable 1 (63-32)                                      */

    struct {
      __IOM uint32_t EN1        : 32;           /*!< [31..0] GPIO63-32 Enables tri-state pin output. Writing a 1
                                                     to any bit enables, and writing a 0 to any bit disables,
                                                     the output for the corresponding GPIO. Reads return output
                                                     enable/disable status of GPIO.                                            */
    } EN1_b;
  } ;

  union {
    __IOM uint32_t EN2;                         /*!< (@ 0x0000024C) GPIO Enable 2 (95-64)                                      */

    struct {
      __IOM uint32_t EN2        : 32;           /*!< [31..0] GPIO95-64 Enables tri-state pin output. Writing a 1
                                                     to any bit enables, and writing a 0 to any bit disables,
                                                     the output for the corresponding GPIO. Reads return output
                                                     enable/disable status of GPIO.                                            */
    } EN2_b;
  } ;

  union {
    __IOM uint32_t EN3;                         /*!< (@ 0x00000250) GPIO Enable 3 (127-96)                                     */

    struct {
      __IOM uint32_t EN3        : 32;           /*!< [31..0] GPIO127-96 Enables tri-state pin output. Writing a 1
                                                     to any bit enables, and writing a 0 to any bit disables,
                                                     the output for the corresponding GPIO. Reads return output
                                                     enable/disable status of GPIO.                                            */
    } EN3_b;
  } ;

  union {
    __IOM uint32_t ENS0;                        /*!< (@ 0x00000254) GPIO Enable Set 0 (31-0)                                   */

    struct {
      __IOM uint32_t ENS0       : 32;           /*!< [31..0] GPIO31-0 Sets pin tri-state output enables. Writing
                                                     a 1 to any bit sets the corresponding bit in the EN register.
                                                     Writing a value of 0 has no effect on the corresponding
                                                     bit in the EN register. Status reads should be made to
                                                     the EN Register.                                                          */
    } ENS0_b;
  } ;

  union {
    __IOM uint32_t ENS1;                        /*!< (@ 0x00000258) GPIO Enable Set 1 (63-32)                                  */

    struct {
      __IOM uint32_t ENS1       : 32;           /*!< [31..0] GPIO63-32 Sets pin tri-state output enables. Writing
                                                     a 1 to any bit sets the corresponding bit in the EN register.
                                                     Writing a value of 0 has no effect on the corresponding
                                                     bit in the EN register. Status reads should be made to
                                                     the EN Register.                                                          */
    } ENS1_b;
  } ;

  union {
    __IOM uint32_t ENS2;                        /*!< (@ 0x0000025C) GPIO Enable Set 2 (95-64)                                  */

    struct {
      __IOM uint32_t ENS2       : 32;           /*!< [31..0] GPIO95-64 Sets pin tri-state output enables. Writing
                                                     a 1 to any bit sets the corresponding bit in the EN register.
                                                     Writing a value of 0 has no effect on the corresponding
                                                     bit in the EN register. Status reads should be made to
                                                     the EN Register.                                                          */
    } ENS2_b;
  } ;

  union {
    __IOM uint32_t ENS3;                        /*!< (@ 0x00000260) GPIO Enable Set 3 (127-96)                                 */

    struct {
      __IOM uint32_t ENS3       : 32;           /*!< [31..0] GPIO127-96 Sets pin tri-state output enables. Writing
                                                     a 1 to any bit sets the corresponding bit in the EN register.
                                                     Writing a value of 0 has no effect on the corresponding
                                                     bit in the EN register. Status reads should be made to
                                                     the EN Register.                                                          */
    } ENS3_b;
  } ;

  union {
    __IOM uint32_t ENC0;                        /*!< (@ 0x00000264) GPIO Enable Clear 0 (31-0)                                 */

    struct {
      __IOM uint32_t ENC0       : 32;           /*!< [31..0] GPIO31-0 Clears pin tri-state output enables. Writing
                                                     a 1 to any bit clears the corresponding bit in the EN register.
                                                     Writing a value of 0 has no effect on the corresponding
                                                     bit in the EN register. Status reads should be made to
                                                     the EN Register.                                                          */
    } ENC0_b;
  } ;

  union {
    __IOM uint32_t ENC1;                        /*!< (@ 0x00000268) GPIO Enable Clear 1 (63-32)                                */

    struct {
      __IOM uint32_t ENC1       : 32;           /*!< [31..0] GPIO63-32 Clears pin tri-state output enables. Writing
                                                     a 1 to any bit clears the corresponding bit in the EN register.
                                                     Writing a value of 0 has no effect on the corresponding
                                                     bit in the EN register. Status reads should be made to
                                                     the EN Register.                                                          */
    } ENC1_b;
  } ;

  union {
    __IOM uint32_t ENC2;                        /*!< (@ 0x0000026C) GPIO Enable Clear 2 (95-64)                                */

    struct {
      __IOM uint32_t ENC2       : 32;           /*!< [31..0] GPIO95-64 Clears pin tri-state output enables. Writing
                                                     a 1 to any bit clears the corresponding bit in the EN register.
                                                     Writing a value of 0 has no effect on the corresponding
                                                     bit in the EN register. Status reads should be made to
                                                     the EN Register.                                                          */
    } ENC2_b;
  } ;

  union {
    __IOM uint32_t ENC3;                        /*!< (@ 0x00000270) GPIO Enable Clear 3 (127-96)                               */

    struct {
      __IOM uint32_t ENC3       : 32;           /*!< [31..0] GPIO127-96 Clears pin tri-state output enables. Writing
                                                     a 1 to any bit clears the corresponding bit in the EN register.
                                                     Writing a value of 0 has no effect on the corresponding
                                                     bit in the EN register. Status reads should be made to
                                                     the EN Register.                                                          */
    } ENC3_b;
  } ;

  union {
    __IOM uint32_t IOM0IRQ;                     /*!< (@ 0x00000274) IOM0 IRQ select for flow control.                          */

    struct {
      __IOM uint32_t IOM0IRQ    : 7;            /*!< [6..0] IOM0 IRQ pad select.                                               */
            uint32_t            : 25;
    } IOM0IRQ_b;
  } ;

  union {
    __IOM uint32_t IOM1IRQ;                     /*!< (@ 0x00000278) IOM1 IRQ select for flow control.                          */

    struct {
      __IOM uint32_t IOM1IRQ    : 7;            /*!< [6..0] IOM1 IRQ pad select.                                               */
            uint32_t            : 25;
    } IOM1IRQ_b;
  } ;

  union {
    __IOM uint32_t IOM2IRQ;                     /*!< (@ 0x0000027C) IOM2 IRQ select for flow control.                          */

    struct {
      __IOM uint32_t IOM2IRQ    : 7;            /*!< [6..0] IOM2 IRQ pad select.                                               */
            uint32_t            : 25;
    } IOM2IRQ_b;
  } ;

  union {
    __IOM uint32_t IOM3IRQ;                     /*!< (@ 0x00000280) IOM3 IRQ select for flow control.                          */

    struct {
      __IOM uint32_t IOM3IRQ    : 7;            /*!< [6..0] IOM3 IRQ pad select.                                               */
            uint32_t            : 25;
    } IOM3IRQ_b;
  } ;

  union {
    __IOM uint32_t IOM4IRQ;                     /*!< (@ 0x00000284) IOM4 IRQ select for flow control.                          */

    struct {
      __IOM uint32_t IOM4IRQ    : 7;            /*!< [6..0] IOM4 IRQ pad select.                                               */
            uint32_t            : 25;
    } IOM4IRQ_b;
  } ;

  union {
    __IOM uint32_t IOM5IRQ;                     /*!< (@ 0x00000288) IOM5 IRQ select for flow control.                          */

    struct {
      __IOM uint32_t IOM5IRQ    : 7;            /*!< [6..0] IOM5 IRQ pad select.                                               */
            uint32_t            : 25;
    } IOM5IRQ_b;
  } ;

  union {
    __IOM uint32_t IOM6IRQ;                     /*!< (@ 0x0000028C) IOM6 IRQ select for flow control.                          */

    struct {
      __IOM uint32_t IOM6IRQ    : 7;            /*!< [6..0] IOM6 IRQ pad select.                                               */
            uint32_t            : 25;
    } IOM6IRQ_b;
  } ;

  union {
    __IOM uint32_t IOM7IRQ;                     /*!< (@ 0x00000290) IOM7 IRQ select for flow control.                          */

    struct {
      __IOM uint32_t IOM7IRQ    : 7;            /*!< [6..0] IOM7 IRQ pad select.                                               */
            uint32_t            : 25;
    } IOM7IRQ_b;
  } ;

  union {
    __IOM uint32_t SDIFCDWP;                    /*!< (@ 0x00000294) SDIF CD and WP Select.                                     */

    struct {
      __IOM uint32_t SDIFCD     : 7;            /*!< [6..0] SDIF CD pad select.                                                */
            uint32_t            : 1;
      __IOM uint32_t SDIFWP     : 7;            /*!< [14..8] SDIF WP pad select.                                               */
            uint32_t            : 17;
    } SDIFCDWP_b;
  } ;

  union {
    __IOM uint32_t OBSDATA;                     /*!< (@ 0x00000298) GPIO Observation mode sample                               */

    struct {
      __IOM uint32_t OBSDATA    : 16;           /*!< [15..0] Sample of the data output on the GPIO observation port.
                                                     May have async sampling issues, as the data is not synronized
                                                     to the read operation. Intended for debug purposes only.                  */
            uint32_t            : 16;
    } OBSDATA_b;
  } ;

  union {
    __IOM uint32_t IEOBS0;                      /*!< (@ 0x0000029C) Read only. Reflects the value of the input enable
                                                                    signals for pads 31-0 sent to the pad.                     */

    struct {
      __IOM uint32_t IEDATA0    : 32;           /*!< [31..0] 1 indicates the input_en is active and the value of
                                                     the pad will be trasmitted to the internal logic within
                                                     the device.                                                               */
    } IEOBS0_b;
  } ;

  union {
    __IOM uint32_t IEOBS1;                      /*!< (@ 0x000002A0) Read only. Reflects the value of the input enable
                                                                    signals for pads 63-32 sent to the pad.                    */

    struct {
      __IOM uint32_t IEDATA1    : 32;           /*!< [31..0] 1 indicates the input_en is active and the value of
                                                     the pad will be trasmitted to the internal logic within
                                                     the device.                                                               */
    } IEOBS1_b;
  } ;

  union {
    __IOM uint32_t IEOBS2;                      /*!< (@ 0x000002A4) Read only. Reflects the value of the input enable
                                                                    signals for pads 95-64 sent to the pad.                    */

    struct {
      __IOM uint32_t IEDATA2    : 32;           /*!< [31..0] 1 indicates the input_en is active and the value of
                                                     the pad will be trasmitted to the internal logic within
                                                     the device.                                                               */
    } IEOBS2_b;
  } ;

  union {
    __IOM uint32_t IEOBS3;                      /*!< (@ 0x000002A8) Read only. Reflects the value of the input enable
                                                                    signals for pads 127-96 sent to the pad.                   */

    struct {
      __IOM uint32_t IEDATA3    : 32;           /*!< [31..0] 1 indicates the input_en is active and the value of
                                                     the pad will be trasmitted to the internal logic within
                                                     the device.                                                               */
    } IEOBS3_b;
  } ;

  union {
    __IOM uint32_t OEOBS0;                      /*!< (@ 0x000002AC) Read only. Reflects the value of the output enable
                                                                    signals for pads 31-0 sent to the pad.                     */

    struct {
      __IOM uint32_t OEDATA0    : 32;           /*!< [31..0] The signal is negative active, and a value of 0 indicates
                                                     the output_en_ is active and the MCU will be driving the
                                                     pad.                                                                      */
    } OEOBS0_b;
  } ;

  union {
    __IOM uint32_t OEOBS1;                      /*!< (@ 0x000002B0) Read only. Reflects the value of the output enable
                                                                    signals for pads 63-32 sent to the pad.                    */

    struct {
      __IOM uint32_t OEDATA1    : 32;           /*!< [31..0] The signal is negative active, and a value of 0 indicates
                                                     the output_en_ is active and the MCU will be driving the
                                                     pad.                                                                      */
    } OEOBS1_b;
  } ;

  union {
    __IOM uint32_t OEOBS2;                      /*!< (@ 0x000002B4) Read only. Reflects the value of the output enable
                                                                    signals for pads 95-64 sent to the pad.                    */

    struct {
      __IOM uint32_t OEDATA2    : 32;           /*!< [31..0] The signal is negative active, and a value of 0 indicates
                                                     the output_en_ is active and the MCU will be driving the
                                                     pad.                                                                      */
    } OEOBS2_b;
  } ;

  union {
    __IOM uint32_t OEOBS3;                      /*!< (@ 0x000002B8) Read only. Reflects the value of the output enable
                                                                    signals for pads 127-96 sent to the pad.                   */

    struct {
      __IOM uint32_t OEDATA3    : 32;           /*!< [31..0] The signal is negative active, and a value of 0 indicates
                                                     the output_en_ is active and the MCU will be driving the
                                                     pad.                                                                      */
    } OEOBS3_b;
  } ;
  __IM  uint32_t  RESERVED;

  union {
    __IOM uint32_t MCUN0INT0EN;                 /*!< (@ 0x000002C0) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t MCUN0GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N0-priority interrupt.                                */
    } MCUN0INT0EN_b;
  } ;

  union {
    __IOM uint32_t MCUN0INT0STAT;               /*!< (@ 0x000002C4) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t MCUN0GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N0-priority interrupt.                                */
    } MCUN0INT0STAT_b;
  } ;

  union {
    __IOM uint32_t MCUN0INT0CLR;                /*!< (@ 0x000002C8) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t MCUN0GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N0-priority interrupt.                                */
    } MCUN0INT0CLR_b;
  } ;

  union {
    __IOM uint32_t MCUN0INT0SET;                /*!< (@ 0x000002CC) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t MCUN0GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N0-priority interrupt.                                   */
      __IOM uint32_t MCUN0GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N0-priority interrupt.                                */
    } MCUN0INT0SET_b;
  } ;

  union {
    __IOM uint32_t MCUN0INT1EN;                 /*!< (@ 0x000002D0) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t MCUN0GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N0-priority interrupt.                                */
    } MCUN0INT1EN_b;
  } ;

  union {
    __IOM uint32_t MCUN0INT1STAT;               /*!< (@ 0x000002D4) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t MCUN0GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N0-priority interrupt.                                */
    } MCUN0INT1STAT_b;
  } ;

  union {
    __IOM uint32_t MCUN0INT1CLR;                /*!< (@ 0x000002D8) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t MCUN0GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N0-priority interrupt.                                */
    } MCUN0INT1CLR_b;
  } ;

  union {
    __IOM uint32_t MCUN0INT1SET;                /*!< (@ 0x000002DC) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t MCUN0GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N0-priority interrupt.                                */
    } MCUN0INT1SET_b;
  } ;

  union {
    __IOM uint32_t MCUN0INT2EN;                 /*!< (@ 0x000002E0) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t MCUN0GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N0-priority interrupt.                                */
    } MCUN0INT2EN_b;
  } ;

  union {
    __IOM uint32_t MCUN0INT2STAT;               /*!< (@ 0x000002E4) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t MCUN0GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N0-priority interrupt.                                */
    } MCUN0INT2STAT_b;
  } ;

  union {
    __IOM uint32_t MCUN0INT2CLR;                /*!< (@ 0x000002E8) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t MCUN0GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N0-priority interrupt.                                */
    } MCUN0INT2CLR_b;
  } ;

  union {
    __IOM uint32_t MCUN0INT2SET;                /*!< (@ 0x000002EC) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t MCUN0GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N0-priority interrupt.                                */
      __IOM uint32_t MCUN0GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N0-priority interrupt.                                */
    } MCUN0INT2SET_b;
  } ;

  union {
    __IOM uint32_t MCUN0INT3EN;                 /*!< (@ 0x000002F0) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t MCUN0GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N0-priority interrupt.                               */
    } MCUN0INT3EN_b;
  } ;

  union {
    __IOM uint32_t MCUN0INT3STAT;               /*!< (@ 0x000002F4) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t MCUN0GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N0-priority interrupt.                               */
    } MCUN0INT3STAT_b;
  } ;

  union {
    __IOM uint32_t MCUN0INT3CLR;                /*!< (@ 0x000002F8) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t MCUN0GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N0-priority interrupt.                               */
    } MCUN0INT3CLR_b;
  } ;

  union {
    __IOM uint32_t MCUN0INT3SET;                /*!< (@ 0x000002FC) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t MCUN0GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N0-priority interrupt.                                  */
      __IOM uint32_t MCUN0GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N0-priority interrupt.                                 */
      __IOM uint32_t MCUN0GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N0-priority interrupt.                               */
      __IOM uint32_t MCUN0GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N0-priority interrupt.                               */
    } MCUN0INT3SET_b;
  } ;

  union {
    __IOM uint32_t MCUN1INT0EN;                 /*!< (@ 0x00000300) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t MCUN1GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N1-priority interrupt.                                */
    } MCUN1INT0EN_b;
  } ;

  union {
    __IOM uint32_t MCUN1INT0STAT;               /*!< (@ 0x00000304) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t MCUN1GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N1-priority interrupt.                                */
    } MCUN1INT0STAT_b;
  } ;

  union {
    __IOM uint32_t MCUN1INT0CLR;                /*!< (@ 0x00000308) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t MCUN1GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N1-priority interrupt.                                */
    } MCUN1INT0CLR_b;
  } ;

  union {
    __IOM uint32_t MCUN1INT0SET;                /*!< (@ 0x0000030C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t MCUN1GPIO0 : 1;            /*!< [0..0] GPIO0 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO1 : 1;            /*!< [1..1] GPIO1 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO2 : 1;            /*!< [2..2] GPIO2 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO3 : 1;            /*!< [3..3] GPIO3 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO4 : 1;            /*!< [4..4] GPIO4 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO5 : 1;            /*!< [5..5] GPIO5 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO6 : 1;            /*!< [6..6] GPIO6 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO7 : 1;            /*!< [7..7] GPIO7 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO8 : 1;            /*!< [8..8] GPIO8 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO9 : 1;            /*!< [9..9] GPIO9 MCU N1-priority interrupt.                                   */
      __IOM uint32_t MCUN1GPIO10 : 1;           /*!< [10..10] GPIO10 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO11 : 1;           /*!< [11..11] GPIO11 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO12 : 1;           /*!< [12..12] GPIO12 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO13 : 1;           /*!< [13..13] GPIO13 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO14 : 1;           /*!< [14..14] GPIO14 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO15 : 1;           /*!< [15..15] GPIO15 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO16 : 1;           /*!< [16..16] GPIO16 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO17 : 1;           /*!< [17..17] GPIO17 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO18 : 1;           /*!< [18..18] GPIO18 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO19 : 1;           /*!< [19..19] GPIO19 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO20 : 1;           /*!< [20..20] GPIO20 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO21 : 1;           /*!< [21..21] GPIO21 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO22 : 1;           /*!< [22..22] GPIO22 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO23 : 1;           /*!< [23..23] GPIO23 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO24 : 1;           /*!< [24..24] GPIO24 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO25 : 1;           /*!< [25..25] GPIO25 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO26 : 1;           /*!< [26..26] GPIO26 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO27 : 1;           /*!< [27..27] GPIO27 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO28 : 1;           /*!< [28..28] GPIO28 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO29 : 1;           /*!< [29..29] GPIO29 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO30 : 1;           /*!< [30..30] GPIO30 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO31 : 1;           /*!< [31..31] GPIO31 MCU N1-priority interrupt.                                */
    } MCUN1INT0SET_b;
  } ;

  union {
    __IOM uint32_t MCUN1INT1EN;                 /*!< (@ 0x00000310) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t MCUN1GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N1-priority interrupt.                                */
    } MCUN1INT1EN_b;
  } ;

  union {
    __IOM uint32_t MCUN1INT1STAT;               /*!< (@ 0x00000314) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t MCUN1GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N1-priority interrupt.                                */
    } MCUN1INT1STAT_b;
  } ;

  union {
    __IOM uint32_t MCUN1INT1CLR;                /*!< (@ 0x00000318) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t MCUN1GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N1-priority interrupt.                                */
    } MCUN1INT1CLR_b;
  } ;

  union {
    __IOM uint32_t MCUN1INT1SET;                /*!< (@ 0x0000031C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t MCUN1GPIO32 : 1;           /*!< [0..0] GPIO32 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO33 : 1;           /*!< [1..1] GPIO33 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO34 : 1;           /*!< [2..2] GPIO34 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO35 : 1;           /*!< [3..3] GPIO35 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO36 : 1;           /*!< [4..4] GPIO36 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO37 : 1;           /*!< [5..5] GPIO37 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO38 : 1;           /*!< [6..6] GPIO38 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO39 : 1;           /*!< [7..7] GPIO39 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO40 : 1;           /*!< [8..8] GPIO40 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO41 : 1;           /*!< [9..9] GPIO41 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO42 : 1;           /*!< [10..10] GPIO42 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO43 : 1;           /*!< [11..11] GPIO43 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO44 : 1;           /*!< [12..12] GPIO44 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO45 : 1;           /*!< [13..13] GPIO45 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO46 : 1;           /*!< [14..14] GPIO46 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO47 : 1;           /*!< [15..15] GPIO47 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO48 : 1;           /*!< [16..16] GPIO48 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO49 : 1;           /*!< [17..17] GPIO49 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO50 : 1;           /*!< [18..18] GPIO50 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO51 : 1;           /*!< [19..19] GPIO51 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO52 : 1;           /*!< [20..20] GPIO52 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO53 : 1;           /*!< [21..21] GPIO53 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO54 : 1;           /*!< [22..22] GPIO54 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO55 : 1;           /*!< [23..23] GPIO55 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO56 : 1;           /*!< [24..24] GPIO56 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO57 : 1;           /*!< [25..25] GPIO57 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO58 : 1;           /*!< [26..26] GPIO58 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO59 : 1;           /*!< [27..27] GPIO59 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO60 : 1;           /*!< [28..28] GPIO60 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO61 : 1;           /*!< [29..29] GPIO61 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO62 : 1;           /*!< [30..30] GPIO62 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO63 : 1;           /*!< [31..31] GPIO63 MCU N1-priority interrupt.                                */
    } MCUN1INT1SET_b;
  } ;

  union {
    __IOM uint32_t MCUN1INT2EN;                 /*!< (@ 0x00000320) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t MCUN1GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N1-priority interrupt.                                */
    } MCUN1INT2EN_b;
  } ;

  union {
    __IOM uint32_t MCUN1INT2STAT;               /*!< (@ 0x00000324) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t MCUN1GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N1-priority interrupt.                                */
    } MCUN1INT2STAT_b;
  } ;

  union {
    __IOM uint32_t MCUN1INT2CLR;                /*!< (@ 0x00000328) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t MCUN1GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N1-priority interrupt.                                */
    } MCUN1INT2CLR_b;
  } ;

  union {
    __IOM uint32_t MCUN1INT2SET;                /*!< (@ 0x0000032C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t MCUN1GPIO64 : 1;           /*!< [0..0] GPIO64 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO65 : 1;           /*!< [1..1] GPIO65 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO66 : 1;           /*!< [2..2] GPIO66 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO67 : 1;           /*!< [3..3] GPIO67 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO68 : 1;           /*!< [4..4] GPIO68 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO69 : 1;           /*!< [5..5] GPIO69 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO70 : 1;           /*!< [6..6] GPIO70 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO71 : 1;           /*!< [7..7] GPIO71 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO72 : 1;           /*!< [8..8] GPIO72 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO73 : 1;           /*!< [9..9] GPIO73 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO74 : 1;           /*!< [10..10] GPIO74 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO75 : 1;           /*!< [11..11] GPIO75 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO76 : 1;           /*!< [12..12] GPIO76 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO77 : 1;           /*!< [13..13] GPIO77 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO78 : 1;           /*!< [14..14] GPIO78 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO79 : 1;           /*!< [15..15] GPIO79 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO80 : 1;           /*!< [16..16] GPIO80 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO81 : 1;           /*!< [17..17] GPIO81 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO82 : 1;           /*!< [18..18] GPIO82 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO83 : 1;           /*!< [19..19] GPIO83 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO84 : 1;           /*!< [20..20] GPIO84 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO85 : 1;           /*!< [21..21] GPIO85 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO86 : 1;           /*!< [22..22] GPIO86 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO87 : 1;           /*!< [23..23] GPIO87 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO88 : 1;           /*!< [24..24] GPIO88 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO89 : 1;           /*!< [25..25] GPIO89 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO90 : 1;           /*!< [26..26] GPIO90 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO91 : 1;           /*!< [27..27] GPIO91 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO92 : 1;           /*!< [28..28] GPIO92 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO93 : 1;           /*!< [29..29] GPIO93 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO94 : 1;           /*!< [30..30] GPIO94 MCU N1-priority interrupt.                                */
      __IOM uint32_t MCUN1GPIO95 : 1;           /*!< [31..31] GPIO95 MCU N1-priority interrupt.                                */
    } MCUN1INT2SET_b;
  } ;

  union {
    __IOM uint32_t MCUN1INT3EN;                 /*!< (@ 0x00000330) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t MCUN1GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N1-priority interrupt.                               */
    } MCUN1INT3EN_b;
  } ;

  union {
    __IOM uint32_t MCUN1INT3STAT;               /*!< (@ 0x00000334) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t MCUN1GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N1-priority interrupt.                               */
    } MCUN1INT3STAT_b;
  } ;

  union {
    __IOM uint32_t MCUN1INT3CLR;                /*!< (@ 0x00000338) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t MCUN1GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N1-priority interrupt.                               */
    } MCUN1INT3CLR_b;
  } ;

  union {
    __IOM uint32_t MCUN1INT3SET;                /*!< (@ 0x0000033C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t MCUN1GPIO96 : 1;           /*!< [0..0] GPIO96 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO97 : 1;           /*!< [1..1] GPIO97 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO98 : 1;           /*!< [2..2] GPIO98 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO99 : 1;           /*!< [3..3] GPIO99 MCU N1-priority interrupt.                                  */
      __IOM uint32_t MCUN1GPIO100 : 1;          /*!< [4..4] GPIO100 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO101 : 1;          /*!< [5..5] GPIO101 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO102 : 1;          /*!< [6..6] GPIO102 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO103 : 1;          /*!< [7..7] GPIO103 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO104 : 1;          /*!< [8..8] GPIO104 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO105 : 1;          /*!< [9..9] GPIO105 MCU N1-priority interrupt.                                 */
      __IOM uint32_t MCUN1GPIO106 : 1;          /*!< [10..10] GPIO106 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO107 : 1;          /*!< [11..11] GPIO107 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO108 : 1;          /*!< [12..12] GPIO108 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO109 : 1;          /*!< [13..13] GPIO109 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO110 : 1;          /*!< [14..14] GPIO110 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO111 : 1;          /*!< [15..15] GPIO111 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO112 : 1;          /*!< [16..16] GPIO112 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO113 : 1;          /*!< [17..17] GPIO113 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO114 : 1;          /*!< [18..18] GPIO114 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO115 : 1;          /*!< [19..19] GPIO115 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO116 : 1;          /*!< [20..20] GPIO116 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO117 : 1;          /*!< [21..21] GPIO117 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO118 : 1;          /*!< [22..22] GPIO118 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO119 : 1;          /*!< [23..23] GPIO119 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO120 : 1;          /*!< [24..24] GPIO120 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO121 : 1;          /*!< [25..25] GPIO121 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO122 : 1;          /*!< [26..26] GPIO122 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO123 : 1;          /*!< [27..27] GPIO123 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO124 : 1;          /*!< [28..28] GPIO124 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO125 : 1;          /*!< [29..29] GPIO125 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO126 : 1;          /*!< [30..30] GPIO126 MCU N1-priority interrupt.                               */
      __IOM uint32_t MCUN1GPIO127 : 1;          /*!< [31..31] GPIO127 MCU N1-priority interrupt.                               */
    } MCUN1INT3SET_b;
  } ;

  union {
    __IOM uint32_t DSP0N0INT0EN;                /*!< (@ 0x00000340) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t DSP0N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N0-priority interrupt.                               */
    } DSP0N0INT0EN_b;
  } ;

  union {
    __IOM uint32_t DSP0N0INT0STAT;              /*!< (@ 0x00000344) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t DSP0N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N0-priority interrupt.                               */
    } DSP0N0INT0STAT_b;
  } ;

  union {
    __IOM uint32_t DSP0N0INT0CLR;               /*!< (@ 0x00000348) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t DSP0N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N0-priority interrupt.                               */
    } DSP0N0INT0CLR_b;
  } ;

  union {
    __IOM uint32_t DSP0N0INT0SET;               /*!< (@ 0x0000034C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t DSP0N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N0-priority interrupt.                                  */
      __IOM uint32_t DSP0N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N0-priority interrupt.                               */
    } DSP0N0INT0SET_b;
  } ;

  union {
    __IOM uint32_t DSP0N0INT1EN;                /*!< (@ 0x00000350) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t DSP0N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N0-priority interrupt.                               */
    } DSP0N0INT1EN_b;
  } ;

  union {
    __IOM uint32_t DSP0N0INT1STAT;              /*!< (@ 0x00000354) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t DSP0N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N0-priority interrupt.                               */
    } DSP0N0INT1STAT_b;
  } ;

  union {
    __IOM uint32_t DSP0N0INT1CLR;               /*!< (@ 0x00000358) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t DSP0N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N0-priority interrupt.                               */
    } DSP0N0INT1CLR_b;
  } ;

  union {
    __IOM uint32_t DSP0N0INT1SET;               /*!< (@ 0x0000035C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t DSP0N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N0-priority interrupt.                               */
    } DSP0N0INT1SET_b;
  } ;

  union {
    __IOM uint32_t DSP0N0INT2EN;                /*!< (@ 0x00000360) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t DSP0N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N0-priority interrupt.                               */
    } DSP0N0INT2EN_b;
  } ;

  union {
    __IOM uint32_t DSP0N0INT2STAT;              /*!< (@ 0x00000364) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t DSP0N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N0-priority interrupt.                               */
    } DSP0N0INT2STAT_b;
  } ;

  union {
    __IOM uint32_t DSP0N0INT2CLR;               /*!< (@ 0x00000368) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t DSP0N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N0-priority interrupt.                               */
    } DSP0N0INT2CLR_b;
  } ;

  union {
    __IOM uint32_t DSP0N0INT2SET;               /*!< (@ 0x0000036C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t DSP0N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N0-priority interrupt.                               */
      __IOM uint32_t DSP0N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N0-priority interrupt.                               */
    } DSP0N0INT2SET_b;
  } ;

  union {
    __IOM uint32_t DSP0N0INT3EN;                /*!< (@ 0x00000370) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t DSP0N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N0-priority interrupt.                              */
    } DSP0N0INT3EN_b;
  } ;

  union {
    __IOM uint32_t DSP0N0INT3STAT;              /*!< (@ 0x00000374) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t DSP0N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N0-priority interrupt.                              */
    } DSP0N0INT3STAT_b;
  } ;

  union {
    __IOM uint32_t DSP0N0INT3CLR;               /*!< (@ 0x00000378) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t DSP0N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N0-priority interrupt.                              */
    } DSP0N0INT3CLR_b;
  } ;

  union {
    __IOM uint32_t DSP0N0INT3SET;               /*!< (@ 0x0000037C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t DSP0N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N0-priority interrupt.                                 */
      __IOM uint32_t DSP0N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N0-priority interrupt.                                */
      __IOM uint32_t DSP0N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N0-priority interrupt.                              */
      __IOM uint32_t DSP0N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N0-priority interrupt.                              */
    } DSP0N0INT3SET_b;
  } ;

  union {
    __IOM uint32_t DSP0N1INT0EN;                /*!< (@ 0x00000380) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t DSP0N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N1-priority interrupt.                               */
    } DSP0N1INT0EN_b;
  } ;

  union {
    __IOM uint32_t DSP0N1INT0STAT;              /*!< (@ 0x00000384) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t DSP0N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N1-priority interrupt.                               */
    } DSP0N1INT0STAT_b;
  } ;

  union {
    __IOM uint32_t DSP0N1INT0CLR;               /*!< (@ 0x00000388) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t DSP0N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N1-priority interrupt.                               */
    } DSP0N1INT0CLR_b;
  } ;

  union {
    __IOM uint32_t DSP0N1INT0SET;               /*!< (@ 0x0000038C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t DSP0N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP0 N1-priority interrupt.                                  */
      __IOM uint32_t DSP0N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP0 N1-priority interrupt.                               */
    } DSP0N1INT0SET_b;
  } ;

  union {
    __IOM uint32_t DSP0N1INT1EN;                /*!< (@ 0x00000390) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t DSP0N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N1-priority interrupt.                               */
    } DSP0N1INT1EN_b;
  } ;

  union {
    __IOM uint32_t DSP0N1INT1STAT;              /*!< (@ 0x00000394) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t DSP0N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N1-priority interrupt.                               */
    } DSP0N1INT1STAT_b;
  } ;

  union {
    __IOM uint32_t DSP0N1INT1CLR;               /*!< (@ 0x00000398) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t DSP0N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N1-priority interrupt.                               */
    } DSP0N1INT1CLR_b;
  } ;

  union {
    __IOM uint32_t DSP0N1INT1SET;               /*!< (@ 0x0000039C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t DSP0N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP0 N1-priority interrupt.                               */
    } DSP0N1INT1SET_b;
  } ;

  union {
    __IOM uint32_t DSP0N1INT2EN;                /*!< (@ 0x000003A0) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t DSP0N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N1-priority interrupt.                               */
    } DSP0N1INT2EN_b;
  } ;

  union {
    __IOM uint32_t DSP0N1INT2STAT;              /*!< (@ 0x000003A4) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t DSP0N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N1-priority interrupt.                               */
    } DSP0N1INT2STAT_b;
  } ;

  union {
    __IOM uint32_t DSP0N1INT2CLR;               /*!< (@ 0x000003A8) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t DSP0N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N1-priority interrupt.                               */
    } DSP0N1INT2CLR_b;
  } ;

  union {
    __IOM uint32_t DSP0N1INT2SET;               /*!< (@ 0x000003AC) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t DSP0N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP0 N1-priority interrupt.                               */
      __IOM uint32_t DSP0N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP0 N1-priority interrupt.                               */
    } DSP0N1INT2SET_b;
  } ;

  union {
    __IOM uint32_t DSP0N1INT3EN;                /*!< (@ 0x000003B0) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t DSP0N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N1-priority interrupt.                              */
    } DSP0N1INT3EN_b;
  } ;

  union {
    __IOM uint32_t DSP0N1INT3STAT;              /*!< (@ 0x000003B4) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t DSP0N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N1-priority interrupt.                              */
    } DSP0N1INT3STAT_b;
  } ;

  union {
    __IOM uint32_t DSP0N1INT3CLR;               /*!< (@ 0x000003B8) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t DSP0N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N1-priority interrupt.                              */
    } DSP0N1INT3CLR_b;
  } ;

  union {
    __IOM uint32_t DSP0N1INT3SET;               /*!< (@ 0x000003BC) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t DSP0N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP0 N1-priority interrupt.                                 */
      __IOM uint32_t DSP0N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP0 N1-priority interrupt.                                */
      __IOM uint32_t DSP0N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP0 N1-priority interrupt.                              */
      __IOM uint32_t DSP0N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP0 N1-priority interrupt.                              */
    } DSP0N1INT3SET_b;
  } ;

  union {
    __IOM uint32_t DSP1N0INT0EN;                /*!< (@ 0x000003C0) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t DSP1N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N0-priority interrupt.                               */
    } DSP1N0INT0EN_b;
  } ;

  union {
    __IOM uint32_t DSP1N0INT0STAT;              /*!< (@ 0x000003C4) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t DSP1N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N0-priority interrupt.                               */
    } DSP1N0INT0STAT_b;
  } ;

  union {
    __IOM uint32_t DSP1N0INT0CLR;               /*!< (@ 0x000003C8) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t DSP1N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N0-priority interrupt.                               */
    } DSP1N0INT0CLR_b;
  } ;

  union {
    __IOM uint32_t DSP1N0INT0SET;               /*!< (@ 0x000003CC) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t DSP1N0GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N0-priority interrupt.                                  */
      __IOM uint32_t DSP1N0GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N0-priority interrupt.                               */
    } DSP1N0INT0SET_b;
  } ;

  union {
    __IOM uint32_t DSP1N0INT1EN;                /*!< (@ 0x000003D0) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t DSP1N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N0-priority interrupt.                               */
    } DSP1N0INT1EN_b;
  } ;

  union {
    __IOM uint32_t DSP1N0INT1STAT;              /*!< (@ 0x000003D4) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t DSP1N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N0-priority interrupt.                               */
    } DSP1N0INT1STAT_b;
  } ;

  union {
    __IOM uint32_t DSP1N0INT1CLR;               /*!< (@ 0x000003D8) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t DSP1N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N0-priority interrupt.                               */
    } DSP1N0INT1CLR_b;
  } ;

  union {
    __IOM uint32_t DSP1N0INT1SET;               /*!< (@ 0x000003DC) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t DSP1N0GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N0-priority interrupt.                               */
    } DSP1N0INT1SET_b;
  } ;

  union {
    __IOM uint32_t DSP1N0INT2EN;                /*!< (@ 0x000003E0) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t DSP1N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N0-priority interrupt.                               */
    } DSP1N0INT2EN_b;
  } ;

  union {
    __IOM uint32_t DSP1N0INT2STAT;              /*!< (@ 0x000003E4) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t DSP1N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N0-priority interrupt.                               */
    } DSP1N0INT2STAT_b;
  } ;

  union {
    __IOM uint32_t DSP1N0INT2CLR;               /*!< (@ 0x000003E8) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t DSP1N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N0-priority interrupt.                               */
    } DSP1N0INT2CLR_b;
  } ;

  union {
    __IOM uint32_t DSP1N0INT2SET;               /*!< (@ 0x000003EC) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t DSP1N0GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N0-priority interrupt.                               */
      __IOM uint32_t DSP1N0GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N0-priority interrupt.                               */
    } DSP1N0INT2SET_b;
  } ;

  union {
    __IOM uint32_t DSP1N0INT3EN;                /*!< (@ 0x000003F0) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t DSP1N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N0-priority interrupt.                              */
    } DSP1N0INT3EN_b;
  } ;

  union {
    __IOM uint32_t DSP1N0INT3STAT;              /*!< (@ 0x000003F4) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t DSP1N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N0-priority interrupt.                              */
    } DSP1N0INT3STAT_b;
  } ;

  union {
    __IOM uint32_t DSP1N0INT3CLR;               /*!< (@ 0x000003F8) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t DSP1N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N0-priority interrupt.                              */
    } DSP1N0INT3CLR_b;
  } ;

  union {
    __IOM uint32_t DSP1N0INT3SET;               /*!< (@ 0x000003FC) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t DSP1N0GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N0-priority interrupt.                                 */
      __IOM uint32_t DSP1N0GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N0-priority interrupt.                                */
      __IOM uint32_t DSP1N0GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N0-priority interrupt.                              */
      __IOM uint32_t DSP1N0GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N0-priority interrupt.                              */
    } DSP1N0INT3SET_b;
  } ;

  union {
    __IOM uint32_t DSP1N1INT0EN;                /*!< (@ 0x00000400) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t DSP1N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N1-priority interrupt.                               */
    } DSP1N1INT0EN_b;
  } ;

  union {
    __IOM uint32_t DSP1N1INT0STAT;              /*!< (@ 0x00000404) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t DSP1N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N1-priority interrupt.                               */
    } DSP1N1INT0STAT_b;
  } ;

  union {
    __IOM uint32_t DSP1N1INT0CLR;               /*!< (@ 0x00000408) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t DSP1N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N1-priority interrupt.                               */
    } DSP1N1INT0CLR_b;
  } ;

  union {
    __IOM uint32_t DSP1N1INT0SET;               /*!< (@ 0x0000040C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t DSP1N1GPIO0 : 1;           /*!< [0..0] GPIO0 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO1 : 1;           /*!< [1..1] GPIO1 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO2 : 1;           /*!< [2..2] GPIO2 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO3 : 1;           /*!< [3..3] GPIO3 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO4 : 1;           /*!< [4..4] GPIO4 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO5 : 1;           /*!< [5..5] GPIO5 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO6 : 1;           /*!< [6..6] GPIO6 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO7 : 1;           /*!< [7..7] GPIO7 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO8 : 1;           /*!< [8..8] GPIO8 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO9 : 1;           /*!< [9..9] GPIO9 DSP1 N1-priority interrupt.                                  */
      __IOM uint32_t DSP1N1GPIO10 : 1;          /*!< [10..10] GPIO10 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO11 : 1;          /*!< [11..11] GPIO11 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO12 : 1;          /*!< [12..12] GPIO12 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO13 : 1;          /*!< [13..13] GPIO13 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO14 : 1;          /*!< [14..14] GPIO14 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO15 : 1;          /*!< [15..15] GPIO15 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO16 : 1;          /*!< [16..16] GPIO16 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO17 : 1;          /*!< [17..17] GPIO17 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO18 : 1;          /*!< [18..18] GPIO18 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO19 : 1;          /*!< [19..19] GPIO19 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO20 : 1;          /*!< [20..20] GPIO20 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO21 : 1;          /*!< [21..21] GPIO21 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO22 : 1;          /*!< [22..22] GPIO22 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO23 : 1;          /*!< [23..23] GPIO23 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO24 : 1;          /*!< [24..24] GPIO24 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO25 : 1;          /*!< [25..25] GPIO25 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO26 : 1;          /*!< [26..26] GPIO26 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO27 : 1;          /*!< [27..27] GPIO27 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO28 : 1;          /*!< [28..28] GPIO28 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO29 : 1;          /*!< [29..29] GPIO29 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO30 : 1;          /*!< [30..30] GPIO30 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO31 : 1;          /*!< [31..31] GPIO31 DSP1 N1-priority interrupt.                               */
    } DSP1N1INT0SET_b;
  } ;

  union {
    __IOM uint32_t DSP1N1INT1EN;                /*!< (@ 0x00000410) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t DSP1N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N1-priority interrupt.                               */
    } DSP1N1INT1EN_b;
  } ;

  union {
    __IOM uint32_t DSP1N1INT1STAT;              /*!< (@ 0x00000414) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t DSP1N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N1-priority interrupt.                               */
    } DSP1N1INT1STAT_b;
  } ;

  union {
    __IOM uint32_t DSP1N1INT1CLR;               /*!< (@ 0x00000418) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t DSP1N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N1-priority interrupt.                               */
    } DSP1N1INT1CLR_b;
  } ;

  union {
    __IOM uint32_t DSP1N1INT1SET;               /*!< (@ 0x0000041C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t DSP1N1GPIO32 : 1;          /*!< [0..0] GPIO32 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO33 : 1;          /*!< [1..1] GPIO33 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO34 : 1;          /*!< [2..2] GPIO34 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO35 : 1;          /*!< [3..3] GPIO35 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO36 : 1;          /*!< [4..4] GPIO36 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO37 : 1;          /*!< [5..5] GPIO37 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO38 : 1;          /*!< [6..6] GPIO38 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO39 : 1;          /*!< [7..7] GPIO39 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO40 : 1;          /*!< [8..8] GPIO40 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO41 : 1;          /*!< [9..9] GPIO41 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO42 : 1;          /*!< [10..10] GPIO42 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO43 : 1;          /*!< [11..11] GPIO43 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO44 : 1;          /*!< [12..12] GPIO44 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO45 : 1;          /*!< [13..13] GPIO45 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO46 : 1;          /*!< [14..14] GPIO46 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO47 : 1;          /*!< [15..15] GPIO47 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO48 : 1;          /*!< [16..16] GPIO48 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO49 : 1;          /*!< [17..17] GPIO49 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO50 : 1;          /*!< [18..18] GPIO50 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO51 : 1;          /*!< [19..19] GPIO51 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO52 : 1;          /*!< [20..20] GPIO52 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO53 : 1;          /*!< [21..21] GPIO53 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO54 : 1;          /*!< [22..22] GPIO54 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO55 : 1;          /*!< [23..23] GPIO55 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO56 : 1;          /*!< [24..24] GPIO56 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO57 : 1;          /*!< [25..25] GPIO57 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO58 : 1;          /*!< [26..26] GPIO58 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO59 : 1;          /*!< [27..27] GPIO59 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO60 : 1;          /*!< [28..28] GPIO60 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO61 : 1;          /*!< [29..29] GPIO61 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO62 : 1;          /*!< [30..30] GPIO62 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO63 : 1;          /*!< [31..31] GPIO63 DSP1 N1-priority interrupt.                               */
    } DSP1N1INT1SET_b;
  } ;

  union {
    __IOM uint32_t DSP1N1INT2EN;                /*!< (@ 0x00000420) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t DSP1N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N1-priority interrupt.                               */
    } DSP1N1INT2EN_b;
  } ;

  union {
    __IOM uint32_t DSP1N1INT2STAT;              /*!< (@ 0x00000424) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t DSP1N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N1-priority interrupt.                               */
    } DSP1N1INT2STAT_b;
  } ;

  union {
    __IOM uint32_t DSP1N1INT2CLR;               /*!< (@ 0x00000428) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t DSP1N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N1-priority interrupt.                               */
    } DSP1N1INT2CLR_b;
  } ;

  union {
    __IOM uint32_t DSP1N1INT2SET;               /*!< (@ 0x0000042C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t DSP1N1GPIO64 : 1;          /*!< [0..0] GPIO64 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO65 : 1;          /*!< [1..1] GPIO65 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO66 : 1;          /*!< [2..2] GPIO66 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO67 : 1;          /*!< [3..3] GPIO67 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO68 : 1;          /*!< [4..4] GPIO68 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO69 : 1;          /*!< [5..5] GPIO69 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO70 : 1;          /*!< [6..6] GPIO70 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO71 : 1;          /*!< [7..7] GPIO71 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO72 : 1;          /*!< [8..8] GPIO72 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO73 : 1;          /*!< [9..9] GPIO73 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO74 : 1;          /*!< [10..10] GPIO74 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO75 : 1;          /*!< [11..11] GPIO75 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO76 : 1;          /*!< [12..12] GPIO76 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO77 : 1;          /*!< [13..13] GPIO77 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO78 : 1;          /*!< [14..14] GPIO78 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO79 : 1;          /*!< [15..15] GPIO79 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO80 : 1;          /*!< [16..16] GPIO80 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO81 : 1;          /*!< [17..17] GPIO81 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO82 : 1;          /*!< [18..18] GPIO82 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO83 : 1;          /*!< [19..19] GPIO83 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO84 : 1;          /*!< [20..20] GPIO84 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO85 : 1;          /*!< [21..21] GPIO85 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO86 : 1;          /*!< [22..22] GPIO86 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO87 : 1;          /*!< [23..23] GPIO87 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO88 : 1;          /*!< [24..24] GPIO88 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO89 : 1;          /*!< [25..25] GPIO89 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO90 : 1;          /*!< [26..26] GPIO90 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO91 : 1;          /*!< [27..27] GPIO91 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO92 : 1;          /*!< [28..28] GPIO92 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO93 : 1;          /*!< [29..29] GPIO93 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO94 : 1;          /*!< [30..30] GPIO94 DSP1 N1-priority interrupt.                               */
      __IOM uint32_t DSP1N1GPIO95 : 1;          /*!< [31..31] GPIO95 DSP1 N1-priority interrupt.                               */
    } DSP1N1INT2SET_b;
  } ;

  union {
    __IOM uint32_t DSP1N1INT3EN;                /*!< (@ 0x00000430) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t DSP1N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N1-priority interrupt.                              */
    } DSP1N1INT3EN_b;
  } ;

  union {
    __IOM uint32_t DSP1N1INT3STAT;              /*!< (@ 0x00000434) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t DSP1N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N1-priority interrupt.                              */
    } DSP1N1INT3STAT_b;
  } ;

  union {
    __IOM uint32_t DSP1N1INT3CLR;               /*!< (@ 0x00000438) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t DSP1N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N1-priority interrupt.                              */
    } DSP1N1INT3CLR_b;
  } ;

  union {
    __IOM uint32_t DSP1N1INT3SET;               /*!< (@ 0x0000043C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t DSP1N1GPIO96 : 1;          /*!< [0..0] GPIO96 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO97 : 1;          /*!< [1..1] GPIO97 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO98 : 1;          /*!< [2..2] GPIO98 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO99 : 1;          /*!< [3..3] GPIO99 DSP1 N1-priority interrupt.                                 */
      __IOM uint32_t DSP1N1GPIO100 : 1;         /*!< [4..4] GPIO100 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO101 : 1;         /*!< [5..5] GPIO101 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO102 : 1;         /*!< [6..6] GPIO102 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO103 : 1;         /*!< [7..7] GPIO103 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO104 : 1;         /*!< [8..8] GPIO104 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO105 : 1;         /*!< [9..9] GPIO105 DSP1 N1-priority interrupt.                                */
      __IOM uint32_t DSP1N1GPIO106 : 1;         /*!< [10..10] GPIO106 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO107 : 1;         /*!< [11..11] GPIO107 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO108 : 1;         /*!< [12..12] GPIO108 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO109 : 1;         /*!< [13..13] GPIO109 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO110 : 1;         /*!< [14..14] GPIO110 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO111 : 1;         /*!< [15..15] GPIO111 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO112 : 1;         /*!< [16..16] GPIO112 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO113 : 1;         /*!< [17..17] GPIO113 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO114 : 1;         /*!< [18..18] GPIO114 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO115 : 1;         /*!< [19..19] GPIO115 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO116 : 1;         /*!< [20..20] GPIO116 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO117 : 1;         /*!< [21..21] GPIO117 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO118 : 1;         /*!< [22..22] GPIO118 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO119 : 1;         /*!< [23..23] GPIO119 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO120 : 1;         /*!< [24..24] GPIO120 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO121 : 1;         /*!< [25..25] GPIO121 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO122 : 1;         /*!< [26..26] GPIO122 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO123 : 1;         /*!< [27..27] GPIO123 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO124 : 1;         /*!< [28..28] GPIO124 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO125 : 1;         /*!< [29..29] GPIO125 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO126 : 1;         /*!< [30..30] GPIO126 DSP1 N1-priority interrupt.                              */
      __IOM uint32_t DSP1N1GPIO127 : 1;         /*!< [31..31] GPIO127 DSP1 N1-priority interrupt.                              */
    } DSP1N1INT3SET_b;
  } ;
} GPIO_Type;                                    /*!< Size = 1088 (0x440)                                                       */



/* =========================================================================================================================== */
/* ================                                            GPU                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Graphics Processing Unit (GPU)
  */

typedef struct {                                /*!< (@ 0x40090000) GPU Structure                                              */

  union {
    __IOM uint32_t TEX0BASE;                    /*!< (@ 0x00000000) Base address of the drawing surface 0 (must be
                                                                    word aligned).                                             */

    struct {
      __IOM uint32_t Base       : 32;           /*!< [31..0] Address 0: base address of the drawing surface 0 (must
                                                     be word aligned).                                                         */
    } TEX0BASE_b;
  } ;

  union {
    __IOM uint32_t TEX0STRIDE;                  /*!< (@ 0x00000004) Image 0 mode and stride.                                   */

    struct {
      __IOM uint32_t IMGSTRD    : 16;           /*!< [15..0] image stride (signed) distance in bytes from one scanline
                                                     to another                                                                */
      __IOM uint32_t IMGMODE    : 8;            /*!< [23..16] Image Mode                                                       */
      __IOM uint32_t IMGFMT     : 8;            /*!< [31..24] Image Format                                                     */
    } TEX0STRIDE_b;
  } ;

  union {
    __IOM uint32_t TEX0RES;                     /*!< (@ 0x00000008) Image 0 resolution.                                        */

    struct {
      __IOM uint32_t RESX       : 16;           /*!< [15..0] resolution X size                                                 */
      __IOM uint32_t RESY       : 16;           /*!< [31..16] resolution Y size                                                */
    } TEX0RES_b;
  } ;
  __IM  uint32_t  RESERVED;

  union {
    __IOM uint32_t TEX1BASE;                    /*!< (@ 0x00000010) Base address of the drawing surface 1 (must be
                                                                    word aligned).                                             */

    struct {
      __IOM uint32_t Base       : 32;           /*!< [31..0] address 1: base address of the drawing surface 1 (must
                                                     be word aligned).                                                         */
    } TEX1BASE_b;
  } ;

  union {
    __IOM uint32_t TEX1STRIDE;                  /*!< (@ 0x00000014) Image 1 mode and stride.                                   */

    struct {
      __IOM uint32_t IMGSTRD    : 16;           /*!< [15..0] image stride (signed) distance in bytes from one scanline
                                                     to another                                                                */
      __IOM uint32_t IMGMODE    : 8;            /*!< [23..16] Image Mode                                                       */
      __IOM uint32_t IMGFMT     : 8;            /*!< [31..24] Image Format                                                     */
    } TEX1STRIDE_b;
  } ;

  union {
    __IOM uint32_t TEX1RES;                     /*!< (@ 0x00000018) Image 1 resolution.                                        */

    struct {
      __IOM uint32_t RESX       : 16;           /*!< [15..0] resolution X size                                                 */
      __IOM uint32_t RESY       : 16;           /*!< [31..16] resolution Y size                                                */
    } TEX1RES_b;
  } ;

  union {
    __IOM uint32_t TEX1COLOR;                   /*!< (@ 0x0000001C) Texture maps default color.Used with luminance
                                                                    and alpha-only color formats.                              */

    struct {
      __IOM uint32_t RED        : 8;            /*!< [7..0] red value                                                          */
      __IOM uint32_t GREEN      : 8;            /*!< [15..8] green value                                                       */
      __IOM uint32_t BLUE       : 8;            /*!< [23..16] blue value                                                       */
      __IOM uint32_t ALPHA      : 8;            /*!< [31..24] alpha value                                                      */
    } TEX1COLOR_b;
  } ;

  union {
    __IOM uint32_t TEX2BASE;                    /*!< (@ 0x00000020) Base address of the drawing surface 2 (must be
                                                                    word aligned).                                             */

    struct {
      __IOM uint32_t Drawing    : 32;           /*!< [31..0] surface 2 Base address of the drawing surface 2                   */
    } TEX2BASE_b;
  } ;

  union {
    __IOM uint32_t TEX2STRIDE;                  /*!< (@ 0x00000024) Image 2 mode and stride.                                   */

    struct {
      __IOM uint32_t IMGSTRD    : 16;           /*!< [15..0] image stride (signed) distance in bytes from one scanline
                                                     to another                                                                */
      __IOM uint32_t IMGMODE    : 8;            /*!< [23..16] image mode                                                       */
      __IOM uint32_t IMGFMT     : 8;            /*!< [31..24] image format                                                     */
    } TEX2STRIDE_b;
  } ;

  union {
    __IOM uint32_t TEX2RES;                     /*!< (@ 0x00000028) Image 2 resolution.                                        */

    struct {
      __IOM uint32_t RESX       : 16;           /*!< [15..0] resolution X size                                                 */
      __IOM uint32_t RESY       : 16;           /*!< [31..16] resolution Y size                                                */
    } TEX2RES_b;
  } ;
  __IM  uint32_t  RESERVED1;

  union {
    __IOM uint32_t TEX3BASE;                    /*!< (@ 0x00000030) Base address of the drawing surface 3 (must be
                                                                    word aligned).                                             */

    struct {
      __IOM uint32_t Image      : 32;           /*!< [31..0] 3 Base address of the drawing surface                             */
    } TEX3BASE_b;
  } ;

  union {
    __IOM uint32_t TEX3STRIDE;                  /*!< (@ 0x00000034) mode and stride.                                           */

    struct {
      __IOM uint32_t IMGSTRD    : 16;           /*!< [15..0] image stride (signed) distance in bytes from one scanline
                                                     to another                                                                */
      __IOM uint32_t IMGMODE    : 8;            /*!< [23..16] image mode                                                       */
      __IOM uint32_t IMGFMT     : 8;            /*!< [31..24] image format                                                     */
    } TEX3STRIDE_b;
  } ;

  union {
    __IOM uint32_t TEX3RES;                     /*!< (@ 0x00000038) Image 3 resolution.                                        */

    struct {
      __IOM uint32_t RESX       : 16;           /*!< [15..0] resolution X size                                                 */
      __IOM uint32_t RESY       : 16;           /*!< [31..16] resolution Y size                                                */
    } TEX3RES_b;
  } ;
  __IM  uint32_t  RESERVED2[21];

  union {
    __IOM uint32_t CGCMD;                       /*!< (@ 0x00000090) Clock gating enable                                        */

    struct {
      __IOM uint32_t STOP       : 1;            /*!< [0..0] stop clock                                                         */
      __IOM uint32_t START      : 1;            /*!< [1..1] start clock                                                        */
            uint32_t            : 30;
    } CGCMD_b;
  } ;

  union {
    __IOM uint32_t CGCTRL;                      /*!< (@ 0x00000094) CGCTRL register description needed here.                   */

    struct {
      __IOM uint32_t DISCLKPROC : 1;            /*!< [0..0] disable clock gating for command list processor                    */
      __IOM uint32_t DISCLKCFG  : 1;            /*!< [1..1] disable clock gating for configuration file                        */
      __IOM uint32_t DISCLKFRAME : 2;           /*!< [3..2] disable clock gating for framebuffer 0 (MISTAKE ?)                 */
      __IOM uint32_t RSVD0      : 19;           /*!< [22..4] This bitfield is reserved.                                        */
      __IOM uint32_t DISCLKCORE : 1;            /*!< [23..23] disable clock gating for core 0                                  */
      __IOM uint32_t RSVD1      : 6;            /*!< [29..24] This bitfield is reserved.                                       */
      __IOM uint32_t DISCLKMOD  : 2;            /*!< [31..30] disable clock gating for all modules (MISTAKE ?)                 */
    } CGCTRL_b;
  } ;

  union {
    __IOM uint32_t DIRTYTRIGMIN;                /*!< (@ 0x00000098) Resets dirty region to resolution size when written.       */

    struct {
      __IOM uint32_t DRTYREG    : 32;           /*!< [31..0] Resets dirty region to resolution size when written.              */
    } DIRTYTRIGMIN_b;
  } ;

  union {
    __IOM uint32_t DIRTYTRIGMAX;                /*!< (@ 0x0000009C) Resets dirty region to resolution size when written.       */

    struct {
      __IOM uint32_t DRTYREG    : 32;           /*!< [31..0] Resets dirty region to resolution size when written.              */
    } DIRTYTRIGMAX_b;
  } ;
  __IM  uint32_t  RESERVED3[4];

  union {
    __IOM uint32_t STATUS;                      /*!< (@ 0x000000B0) On read, returns GPU status (CHECK address!!).             */

    struct {
      __IOM uint32_t COREBSY    : 4;            /*!< [3..0] processing core busy (Cores 3-0)                                   */
      __IOM uint32_t PIPEBSY    : 4;            /*!< [7..4] pipeline busy (Cores 3-0)                                          */
      __IOM uint32_t TEXTMAPBSY : 4;            /*!< [11..8] texture map busy (Cores 3-0)                                      */
      __IOM uint32_t RENDERBSY  : 4;            /*!< [15..12] render output unit busy (Cores 3-0)                              */
      __IOM uint32_t DEPTHFIFOBSY : 4;          /*!< [19..16] depth buffer busy (Cores 3-0)                                    */
            uint32_t            : 4;
      __IOM uint32_t RASTBSY    : 4;            /*!< [27..24] rasterizer busy                                                  */
      __IOM uint32_t CLPBSY     : 1;            /*!< [28..28] command list processor busy                                      */
      __IOM uint32_t CLBSY      : 1;            /*!< [29..29] command list bus busy                                            */
      __IOM uint32_t MEMBSY     : 1;            /*!< [30..30] memory system busy                                               */
      __IOM uint32_t SYSBSY     : 1;            /*!< [31..31] system busy                                                      */
    } STATUS_b;
  } ;
  __IM  uint32_t  RESERVED4[3];

  union {
    __IOM uint32_t BUSCTRL;                     /*!< (@ 0x000000C0) Bus Control                                                */

    struct {
      __IOM uint32_t BUSCTRL    : 32;           /*!< [31..0] Bus Control                                                       */
    } BUSCTRL_b;
  } ;

  union {
    __IOM uint32_t IMEMLDIADDR;                 /*!< (@ 0x000000C4) Load shader instruction memory address.                    */

    struct {
      __IOM uint32_t IMEM       : 32;           /*!< [31..0] ADDR Load shader. Load shader instruction memory address.         */
    } IMEMLDIADDR_b;
  } ;

  union {
    __IOM uint32_t IMEMLDIDATAHL;               /*!< (@ 0x000000C8) Load shader instruction Memory data (31:0).                */

    struct {
      __IOM uint32_t IMEM       : 32;           /*!< [31..0] DATA Load shader. Load shader instruction Memory data
                                                     (31:0).                                                                   */
    } IMEMLDIDATAHL_b;
  } ;

  union {
    __IOM uint32_t IMEMLDIDATAHH;               /*!< (@ 0x000000CC) Load shader instruction Memory data (63:32).               */

    struct {
      __IOM uint32_t IMEM       : 32;           /*!< [31..0] DATA Load shader. Load shader instruction Memory data
                                                     (63:32).                                                                  */
    } IMEMLDIDATAHH_b;
  } ;
  __IM  uint32_t  RESERVED5[6];

  union {
    __IOM uint32_t CMDLISTSTATUS;               /*!< (@ 0x000000E8) On read, returns command list processor status;
                                                                    On write, resets command list processor.                   */

    struct {
      __IOM uint32_t LIST       : 1;            /*!< [0..0] processor status                                                   */
            uint32_t            : 31;
    } CMDLISTSTATUS_b;
  } ;

  union {
    __IOM uint32_t CMDLISTRINGSTOP;             /*!< (@ 0x000000EC) Updates GPU command list pointer to stop executing.        */

    struct {
      __IOM uint32_t UPDATEPRT  : 32;           /*!< [31..0] Updates GPU command list pointer to stop executing.               */
    } CMDLISTRINGSTOP_b;
  } ;

  union {
    __IOM uint32_t CMDLISTADDR;                 /*!< (@ 0x000000F0) Command list base pointer.                                 */

    struct {
      __IOM uint32_t BASEPTR    : 32;           /*!< [31..0] Command list base pointer.                                        */
    } CMDLISTADDR_b;
  } ;

  union {
    __IOM uint32_t CMDLISTSIZE;                 /*!< (@ 0x000000F4) Command list length in words.                              */

    struct {
      __IOM uint32_t LISTWORDS  : 32;           /*!< [31..0] Command list length in words.                                     */
    } CMDLISTSIZE_b;
  } ;

  union {
    __IOM uint32_t INTERRUPTCTRL;               /*!< (@ 0x000000F8) On write, clears the IRQ (CHECK address!).                 */

    struct {
      __IOM uint32_t IRQACTIVE  : 1;            /*!< [0..0] if set to zero IRQ is active high, if set to one IRQ
                                                     is active low                                                             */
      __IOM uint32_t INTCMDEND  : 1;            /*!< [1..1] if set, signals interrupt at the end of command list               */
      __IOM uint32_t INTDRAWEND : 1;            /*!< [2..2] if set, signals interrupt at the end of drawing command            */
      __IOM uint32_t AUTOCLR    : 1;            /*!< [3..3] if set, auto clears interrupt                                      */
      __IOM uint32_t RSVD       : 26;           /*!< [29..4] This bitfield is reserved.                                        */
      __IOM uint32_t CHANGEFREQ : 2;            /*!< [31..30] change frequency of asynchronous clock                           */
    } INTERRUPTCTRL_b;
  } ;

  union {
    __IOM uint32_t SYSCLEAR;                    /*!< (@ 0x000000FC) On write, resets the GPU (CHECK address!).                 */

    struct {
      __IOM uint32_t RESETGPU   : 32;           /*!< [31..0] On write, resets the GPU (CHECK address!).                        */
    } SYSCLEAR_b;
  } ;

  union {
    __IOM uint32_t DRAWCMD;                     /*!< (@ 0x00000100) Rasterizer drawing command.                                */

    struct {
      __IOM uint32_t START      : 3;            /*!< [2..0] Start the draw command                                             */
      __IOM uint32_t RSVD       : 29;           /*!< [31..3] This bitfield is reserved.                                        */
    } DRAWCMD_b;
  } ;

  union {
    __IOM uint32_t DRAWPT0;                     /*!< (@ 0x00000104) Stores only integer values. For greater accurancy
                                                                    DRAWPT0X and DRAWPT0Y registers are used
                                                                    which are 16, 16 fixed point.                              */

    struct {
      __IOM uint32_t COORDX     : 16;           /*!< [15..0] vertex 0 X coordinate (integer value)                             */
      __IOM uint32_t COORDY     : 16;           /*!< [31..16] vertex 0 Y coordinate (integer value)                            */
    } DRAWPT0_b;
  } ;

  union {
    __IOM uint32_t DRAWPT1;                     /*!< (@ 0x00000108) Stores only integer values. Vertex 1 drawing
                                                                    primitive. Stores only integer values. For
                                                                    greater accurancy DRAWPT1X and DRAWPT1Y
                                                                    registers are used which are 16, 16 fixed
                                                                    point.                                                     */

    struct {
      __IOM uint32_t COORDX     : 16;           /*!< [15..0] vertex 0 X coordinate (integer value)                             */
      __IOM uint32_t COORDY     : 16;           /*!< [31..16] vertex 0 Y coordinate (integer value)                            */
    } DRAWPT1_b;
  } ;
  __IM  uint32_t  RESERVED6;

  union {
    __IOM uint32_t CLIPMIN;                     /*!< (@ 0x00000110) Clipping rectangle upper left vertex.                      */

    struct {
      __IOM uint32_t COORDX     : 16;           /*!< [15..0] upper left X coordinate                                           */
      __IOM uint32_t COORDY     : 16;           /*!< [31..16] upper left Y coordinate                                          */
    } CLIPMIN_b;
  } ;

  union {
    __IOM uint32_t CLIPMAX;                     /*!< (@ 0x00000114) Clipping rectangle bottom right vertex.                    */

    struct {
      __IOM uint32_t COORDX     : 16;           /*!< [15..0] bottom right X coordinate                                         */
      __IOM uint32_t COORDY     : 16;           /*!< [31..16] bottom right Y coordinate                                        */
    } CLIPMAX_b;
  } ;

  union {
    __IOM uint32_t RASTCTRL;                    /*!< (@ 0x00000118) Rasterizer matrix multiplication control                   */

    struct {
      __IOM uint32_t RSVD       : 28;           /*!< [27..0] This bitfield is reserved.                                        */
      __IOM uint32_t BYPASS     : 1;            /*!< [28..28] tells module to bypass calculations                              */
      __IOM uint32_t ADD        : 1;            /*!< [29..29] adds 0.5 to X and Y                                              */
      __IOM uint32_t PERSP      : 2;            /*!< [31..30] when set to 0 is in perspective mode (MISTAKE IN DOC?)           */
    } RASTCTRL_b;
  } ;

  union {
    __IOM uint32_t DRAWCODEPTR;                 /*!< (@ 0x0000011C) DRAWCODEPTR register description needed here.              */

    struct {
      __IOM uint32_t FRGND      : 16;           /*!< [15..0] the pointer for the instruction that will be executed
                                                     for foreground pixel                                                      */
      __IOM uint32_t BKGND      : 16;           /*!< [31..16] the pointer for the instruction that will be executed
                                                     for background pixel                                                      */
    } DRAWCODEPTR_b;
  } ;

  union {
    __IOM uint32_t DRAWPT0X;                    /*!< (@ 0x00000120) X coordinate of Vertex 0 drawing primitive 16,
                                                                    16 fixed point.                                            */

    struct {
      __IOM uint32_t DRAW0X     : 32;           /*!< [31..0] X coordinate                                                      */
    } DRAWPT0X_b;
  } ;

  union {
    __IOM uint32_t DRAWPT0Y;                    /*!< (@ 0x00000124) Y coordinate of Vertex 0 drawing primitive 16,
                                                                    16 fixed point.                                            */

    struct {
      __IOM uint32_t DRAW0Y     : 32;           /*!< [31..0] Y coordinate                                                      */
    } DRAWPT0Y_b;
  } ;

  union {
    __IOM uint32_t DRAWPT0Z;                    /*!< (@ 0x00000128) DRAWPTOX register description needed here.                 */

    struct {
      __IOM uint32_t DRAW0Z     : 32;           /*!< [31..0] This bitfield is reserved.                                        */
    } DRAWPT0Z_b;
  } ;

  union {
    __IOM uint32_t DRAWCOLOR;                   /*!< (@ 0x0000012C) DRAWCOLOR register description needed here.                */

    struct {
      __IOM uint32_t RASTPRIM   : 32;           /*!< [31..0] Rasterizer drawing                                                */
    } DRAWCOLOR_b;
  } ;

  union {
    __IOM uint32_t DRAWPT1X;                    /*!< (@ 0x00000130) X coordinate of Vertex 1 drawing primitive 16,
                                                                    16 fixed point.                                            */

    struct {
      __IOM uint32_t DRAW1X     : 32;           /*!< [31..0] X coordinate                                                      */
    } DRAWPT1X_b;
  } ;

  union {
    __IOM uint32_t DRAWPT1Y;                    /*!< (@ 0x00000134) Y coordinate of Vertex 1 drawing primitive 16,
                                                                    16 fixed point.                                            */

    struct {
      __IOM uint32_t DRAW1Y     : 32;           /*!< [31..0] Y coordinate                                                      */
    } DRAWPT1Y_b;
  } ;

  union {
    __IOM uint32_t DRAWPT1Z;                    /*!< (@ 0x00000138) DRAWPT1Z register description needed here.                 */

    struct {
      __IOM uint32_t DRAW1Z     : 32;           /*!< [31..0] This bitfield is reserved.                                        */
    } DRAWPT1Z_b;
  } ;
  __IM  uint32_t  RESERVED7;

  union {
    __IOM uint32_t DRAWPT2X;                    /*!< (@ 0x00000140) X coordinate of Vertex 2 drawing primitive 16,
                                                                    16 fixed point.                                            */

    struct {
      __IOM uint32_t DRAW2X     : 32;           /*!< [31..0] X coordinate                                                      */
    } DRAWPT2X_b;
  } ;

  union {
    __IOM uint32_t DRAWPT2Y;                    /*!< (@ 0x00000144) Y coordinate of Vertex 2 drawing primitive 16,
                                                                    16 fixed point.                                            */

    struct {
      __IOM uint32_t DRAW2Y     : 32;           /*!< [31..0] Y coordinate                                                      */
    } DRAWPT2Y_b;
  } ;

  union {
    __IOM uint32_t DRAWPT2Z;                    /*!< (@ 0x00000148) DRAWPT2Z register description needed here.                 */

    struct {
      __IOM uint32_t RSVD       : 32;           /*!< [31..0] This bitfield is reserved.                                        */
    } DRAWPT2Z_b;
  } ;
  __IM  uint32_t  RESERVED8;

  union {
    __IOM uint32_t DRAWPT3X;                    /*!< (@ 0x00000150) X coordinate of Vertex 3 drawing primitive 16,
                                                                    16 fixed point.                                            */

    struct {
      __IOM uint32_t DRAW3X     : 32;           /*!< [31..0] X coordinate                                                      */
    } DRAWPT3X_b;
  } ;

  union {
    __IOM uint32_t DRAWPT3Y;                    /*!< (@ 0x00000154) Y coordinate of Vertex 3 drawing primitive 16,
                                                                    16 fixed point.                                            */

    struct {
      __IOM uint32_t DRAW3Y     : 32;           /*!< [31..0] Y coordinate.                                                     */
    } DRAWPT3Y_b;
  } ;

  union {
    __IOM uint32_t DRAWPT3Z;                    /*!< (@ 0x00000158) Fixed value (not accessible). Registers 0x160-0x180
                                                                    are the elements of the 3x3 transformation
                                                                    matrix used for homogeneous conversion from
                                                                    screen coordinates to texture coordinates;
                                                                    the elements are floating points                           */

    struct {
      __IOM uint32_t DRAW3Z     : 32;           /*!< [31..0] Fixed value (not accessible)                                      */
    } DRAWPT3Z_b;
  } ;
  __IM  uint32_t  RESERVED9;

  union {
    __IOM uint32_t MM00;                        /*!< (@ 0x00000160) matrix floating point element.                             */

    struct {
      __IOM uint32_t MTX        : 32;           /*!< [31..0] (0,0). matrix floating point element.                             */
    } MM00_b;
  } ;

  union {
    __IOM uint32_t MM01;                        /*!< (@ 0x00000164) matrix floating point element.                             */

    struct {
      __IOM uint32_t MTX        : 32;           /*!< [31..0] (0,1). matrix floating point element.                             */
    } MM01_b;
  } ;

  union {
    __IOM uint32_t MM02;                        /*!< (@ 0x00000168) matrix floating point element; sets to unit matrix
                                                                    if previously written element is MM12.                     */

    struct {
      __IOM uint32_t MTX        : 32;           /*!< [31..0] (0,2). matrix floating point element.                             */
    } MM02_b;
  } ;

  union {
    __IOM uint32_t MM10;                        /*!< (@ 0x0000016C) matrix floating point element.                             */

    struct {
      __IOM uint32_t MTX        : 32;           /*!< [31..0] (1,0). matrix floating point element.                             */
    } MM10_b;
  } ;

  union {
    __IOM uint32_t MM11;                        /*!< (@ 0x00000170) matrix floating point element.                             */

    struct {
      __IOM uint32_t MTX        : 32;           /*!< [31..0] (1,1). matrix floating point element                              */
    } MM11_b;
  } ;

  union {
    __IOM uint32_t MM12;                        /*!< (@ 0x00000174) matrix floating point element.                             */

    struct {
      __IOM uint32_t MTX        : 32;           /*!< [31..0] (1,2). matrix floating point element.                             */
    } MM12_b;
  } ;

  union {
    __IOM uint32_t MM20;                        /*!< (@ 0x00000178) matrix floating point element.                             */

    struct {
      __IOM uint32_t MTX        : 32;           /*!< [31..0] (2,0). matrix floating point element.                             */
    } MM20_b;
  } ;

  union {
    __IOM uint32_t MM21;                        /*!< (@ 0x0000017C) matrix floating point element.                             */

    struct {
      __IOM uint32_t MTX        : 32;           /*!< [31..0] (2,1). matrix floating point element.                             */
    } MM21_b;
  } ;

  union {
    __IOM uint32_t MM22;                        /*!< (@ 0x00000180) matrix floating point element.                             */

    struct {
      __IOM uint32_t MTX        : 32;           /*!< [31..0] (2,2). matrix floating point element                              */
    } MM22_b;
  } ;

  union {
    __IOM uint32_t DEPTHSTARTL;                 /*!< (@ 0x00000184) Depth value of START pixel, (32 low bits fractional.)      */

    struct {
      __IOM uint32_t DEPTH32LO  : 32;           /*!< [31..0] Depth value of START pixel                                        */
    } DEPTHSTARTL_b;
  } ;

  union {
    __IOM uint32_t DEPTHSTARTH;                 /*!< (@ 0x00000188) Depth value of START pixel, (32 high bits integral.)       */

    struct {
      __IOM uint32_t DEPTH32HI  : 32;           /*!< [31..0] Depth value of START pixel                                        */
    } DEPTHSTARTH_b;
  } ;

  union {
    __IOM uint32_t DEPTHDXL;                    /*!< (@ 0x0000018C) Added depth value for each step at x-axis (32
                                                                    low bits fractional.)                                      */

    struct {
      __IOM uint32_t XAXISLO    : 32;           /*!< [31..0] Added depth value for each step at x-axis                         */
    } DEPTHDXL_b;
  } ;

  union {
    __IOM uint32_t DEPTHDXH;                    /*!< (@ 0x00000190) Added depth value for each step at x-axis (32
                                                                    high bits integral.)                                       */

    struct {
      __IOM uint32_t XAXISHI    : 32;           /*!< [31..0] Added depth value for each step at x-axis                         */
    } DEPTHDXH_b;
  } ;

  union {
    __IOM uint32_t DEPTHDYL;                    /*!< (@ 0x00000194) Added depth value for each step at y-axis (32
                                                                    low bits fractional.)                                      */

    struct {
      __IOM uint32_t YAXISLO    : 32;           /*!< [31..0] Added depth value for each step at y-axis                         */
    } DEPTHDYL_b;
  } ;

  union {
    __IOM uint32_t DEPTHDYH;                    /*!< (@ 0x00000198) Added depth value for each step at y-axis (32
                                                                    high bits integral.)                                       */

    struct {
      __IOM uint32_t YAXISHI    : 32;           /*!< [31..0] Added depth value for each step at y-axis                         */
    } DEPTHDYH_b;
  } ;
  __IM  uint32_t  RESERVED10;

  union {
    __IOM uint32_t REDX;                        /*!< (@ 0x000001A0) Added red value for each step at x-axis, (16,
                                                                    16 fixed point)                                            */

    struct {
      __IOM uint32_t REDX       : 32;           /*!< [31..0] Added red value for each step at x-axis                           */
    } REDX_b;
  } ;

  union {
    __IOM uint32_t REDY;                        /*!< (@ 0x000001A4) Added red value for each step at y-axis, (16,
                                                                    16 fixed point)                                            */

    struct {
      __IOM uint32_t REDY       : 32;           /*!< [31..0] red value for each step at y-axis                                 */
    } REDY_b;
  } ;

  union {
    __IOM uint32_t GREENX;                      /*!< (@ 0x000001A8) Added green value for each step at x-axis, (16,
                                                                    16 fixed point)                                            */

    struct {
      __IOM uint32_t GREENX     : 32;           /*!< [31..0] Added green value for each step at x-axis                         */
    } GREENX_b;
  } ;

  union {
    __IOM uint32_t GREENY;                      /*!< (@ 0x000001AC) Added green value for each step at y-axis, (16,
                                                                    16 fixed point)                                            */

    struct {
      __IOM uint32_t GREENY     : 32;           /*!< [31..0] Added green value for each step at y-axis                         */
    } GREENY_b;
  } ;

  union {
    __IOM uint32_t BLUEX;                       /*!< (@ 0x000001B0) Added blue value for each step at x-axis, (16,
                                                                    16 fixed point)                                            */

    struct {
      __IOM uint32_t BLUEX      : 32;           /*!< [31..0] Added blue value for each step at x-axis                          */
    } BLUEX_b;
  } ;

  union {
    __IOM uint32_t BLUEY;                       /*!< (@ 0x000001B4) Added blue value for each step at y-axis, (16,
                                                                    16 fixed point)                                            */

    struct {
      __IOM uint32_t BLUEY      : 32;           /*!< [31..0] Added blue value for each step at y-axis                          */
    } BLUEY_b;
  } ;

  union {
    __IOM uint32_t ALFX;                        /*!< (@ 0x000001B8) Added alfa value for each step at x-axis, (16,
                                                                    16 fixed point)                                            */

    struct {
      __IOM uint32_t ALFX       : 32;           /*!< [31..0] Added alfa value for each step at x-axis                          */
    } ALFX_b;
  } ;

  union {
    __IOM uint32_t ALFY;                        /*!< (@ 0x000001BC) Added alfa value for each step at y-axis, (16,
                                                                    16 fixed point)                                            */

    struct {
      __IOM uint32_t ALFY       : 32;           /*!< [31..0] Added alfa value for each step at y-axis                          */
    } ALFY_b;
  } ;

  union {
    __IOM uint32_t REDINIT;                     /*!< (@ 0x000001C0) Red value of STARTXY pixel, (16, 16 fixed point)           */

    struct {
      __IOM uint32_t REDXY      : 32;           /*!< [31..0] Red value of STARTXY pixel                                        */
    } REDINIT_b;
  } ;

  union {
    __IOM uint32_t GREINIT;                     /*!< (@ 0x000001C4) Green value of STARTXY pixel, (16, 16 fixed point)         */

    struct {
      __IOM uint32_t GREENXY    : 32;           /*!< [31..0] Green value of STARTXY pixel                                      */
    } GREINIT_b;
  } ;

  union {
    __IOM uint32_t BLUINIT;                     /*!< (@ 0x000001C8) Blue value of STARTXY pixel, (16, 16 fixed point)          */

    struct {
      __IOM uint32_t BLUEXY     : 32;           /*!< [31..0] Blue value of STARTXY pixel                                       */
    } BLUINIT_b;
  } ;

  union {
    __IOM uint32_t ALFINIT;                     /*!< (@ 0x000001CC) Alfa value of STARTXY pixel, (16, 16 fixed point)
                                                                    Shader Registers                                           */

    struct {
      __IOM uint32_t ALFXY      : 32;           /*!< [31..0] Alfa value of STARTXY pixel                                       */
    } ALFINIT_b;
  } ;
  __IM  uint32_t  RESERVED11[7];

  union {
    __IOM uint32_t IDREG;                       /*!< (@ 0x000001EC) Fixed value                                                */

    struct {
      __IOM uint32_t GPUID      : 32;           /*!< [31..0] Fixed value for GPU ID                                            */
    } IDREG_b;
  } ;

  union {
    __IOM uint32_t LOADCTRL;                    /*!< (@ 0x000001F0) Load Control                                               */

    struct {
      __IOM uint32_t LOADCTRL   : 32;           /*!< [31..0] Load Control                                                      */
    } LOADCTRL_b;
  } ;
  __IM  uint32_t  RESERVED12[3];

  union {
    __IOM uint32_t C0REG;                       /*!< (@ 0x00000200) Shader constant register 0.                                */

    struct {
      __IOM uint32_t C0SHADER   : 32;           /*!< [31..0] Shader constant register 0.                                       */
    } C0REG_b;
  } ;

  union {
    __IOM uint32_t C1REG;                       /*!< (@ 0x00000204) Shader constant register 1.                                */

    struct {
      __IOM uint32_t C1SHADER   : 32;           /*!< [31..0] Shader constant register 1.                                       */
    } C1REG_b;
  } ;

  union {
    __IOM uint32_t C2REG;                       /*!< (@ 0x00000208) Shader constant register 2.                                */

    struct {
      __IOM uint32_t C2SHADER   : 32;           /*!< [31..0] Shader constant register 2                                        */
    } C2REG_b;
  } ;

  union {
    __IOM uint32_t C3REG;                       /*!< (@ 0x0000020C) Shader constant register 3, the dirty Region
                                                                    Register                                                   */

    struct {
      __IOM uint32_t C3SHADER   : 32;           /*!< [31..0] Shader constant register 3                                        */
    } C3REG_b;
  } ;
  __IM  uint32_t  RESERVED13[888];

  union {
    __IOM uint32_t IRQID;                       /*!< (@ 0x00000FF0) Signals interrupt when set (CHECK address!).               */

    struct {
      __IOM uint32_t IRQID      : 32;           /*!< [31..0] Signals interrupt when set (CHECK address!                        */
    } IRQID_b;
  } ;
} GPU_Type;                                     /*!< Size = 4084 (0xff4)                                                       */



/* =========================================================================================================================== */
/* ================                                           I2S0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief I2S Master/Slave Module (I2S0)
  */

typedef struct {                                /*!< (@ 0x40208000) I2S0 Structure                                             */

  union {
    __IOM uint32_t RXDATA;                      /*!< (@ 0x00000000) Read only access to the i2S receive data                   */

    struct {
      __IOM uint32_t RXSAMPLE   : 32;           /*!< [31..0] 32b audio sample from the internal receive FIFO. MSB
                                                     is always in bit 31                                                       */
    } RXDATA_b;
  } ;

  union {
    __IOM uint32_t RXCHANID;                    /*!< (@ 0x00000004) Read only received channel identification register         */

    struct {
      __IOM uint32_t RXCHANID   : 8;            /*!< [7..0] Channel ID value 0-255.                                            */
            uint32_t            : 24;
    } RXCHANID_b;
  } ;

  union {
    __IOM uint32_t RXFIFOSTATUS;                /*!< (@ 0x00000008) Holds the number of samples currently in the
                                                                    receive FIFO, and the empty condition flag                 */

    struct {
      __IOM uint32_t RXSAMPLECNT : 28;          /*!< [27..0] The count of the number of samples currently in the
                                                     receive FIFO.                                                             */
      __IOM uint32_t RXEMPTY    : 1;            /*!< [28..28] Receive FIFO empty bit. a 1 indicates the receive FIFO
                                                     is empty.                                                                 */
            uint32_t            : 3;
    } RXFIFOSTATUS_b;
  } ;

  union {
    __IOM uint32_t RXFIFOSIZE;                  /*!< (@ 0x0000000C) Holds the size of the receive FIFO in samples              */

    struct {
      __IOM uint32_t SIZE       : 32;           /*!< [31..0] Size of the receive FIFO in units of i2S samples. Read
                                                     only value.                                                               */
    } RXFIFOSIZE_b;
  } ;

  union {
    __IOM uint32_t RXUPPERLIMIT;                /*!< (@ 0x00000010) The number of samples required to be in the RX
                                                                    FIFO before asserting the RX_FFi interrupt
                                                                    bit                                                        */

    struct {
      __IOM uint32_t SIZE       : 32;           /*!< [31..0] When the I2S sample count stored within the receive
                                                     FIFO reaches this value or is larger, the interrupt RX_FFi
                                                     bit is asserted.                                                          */
    } RXUPPERLIMIT_b;
  } ;
  __IM  uint32_t  RESERVED[3];

  union {
    __IOM uint32_t TXDATA;                      /*!< (@ 0x00000020) Write only register to hold the i2S sample to
                                                                    transmit via the write FIFO                                */

    struct {
      __IOM uint32_t TXSAMPLE   : 32;           /*!< [31..0] 32b I2S sample to send out of the I2S module via the
                                                     external pins. All sample have the MSB in bit 31 regardless
                                                     of number of bits per sample and data justification                       */
    } TXDATA_b;
  } ;

  union {
    __IOM uint32_t TXCHANID;                    /*!< (@ 0x00000024) Channel ID used for the next audio sample to
                                                                    be written to the data transmission register               */

    struct {
      __IOM uint32_t TXCHANID   : 8;            /*!< [7..0] Channel ID value 0-255.                                            */
            uint32_t            : 24;
    } TXCHANID_b;
  } ;

  union {
    __IOM uint32_t TXFIFOSTATUS;                /*!< (@ 0x00000028) Holds the number of samples currently in the
                                                                    transmit FIFO, and the full condition flag                 */

    struct {
      __IOM uint32_t TXFIFOCNT  : 28;           /*!< [27..0] The count of the number of samples currently in the
                                                     transmit FIFO.                                                            */
            uint32_t            : 1;
      __IOM uint32_t TXFIFOFULL : 1;            /*!< [29..29] Transmit FIFO full bit. a 1 indicates the transmit
                                                     FIFO is full.                                                             */
            uint32_t            : 2;
    } TXFIFOSTATUS_b;
  } ;

  union {
    __IOM uint32_t TXFIFOSIZE;                  /*!< (@ 0x0000002C) Holds the size of the transmit FIFO in samples             */

    struct {
      __IOM uint32_t SIZE       : 32;           /*!< [31..0] Size of the transmit FIFO in units of I2S samples. Read
                                                     only value.                                                               */
    } TXFIFOSIZE_b;
  } ;

  union {
    __IOM uint32_t TXLOWERLIMIT;                /*!< (@ 0x00000030) Minimum number of samples have been reached in
                                                                    the transmit FIFO.                                         */

    struct {
      __IOM uint32_t SIZE       : 32;           /*!< [31..0] When the number of sample in the TX FIFO goes below
                                                     this value, the interrupt TX_FFi bit is asserted.                         */
    } TXLOWERLIMIT_b;
  } ;
  __IM  uint32_t  RESERVED1[3];

  union {
    __IOM uint32_t I2SDATACFG;                  /*!< (@ 0x00000040) Specifies the data format of I2S sub frames                */

    struct {
      __IOM uint32_t SSZ1       : 3;            /*!< [2..0] Receive audio sample length for phase 1. 0: 8b, 2: 16b,
                                                     4: 24b, 5: 32b, 1,3,6,7: Reserved                                         */
      __IOM uint32_t JUST       : 1;            /*!< [3..3] Audio sample justification. 0: Left-justified, 1: Right-justified  */
            uint32_t            : 1;
      __IOM uint32_t WDLEN1     : 3;            /*!< [7..5] Receive channel length in bits for phase 1. 0: 8b, 2:
                                                     16b, 4: 24b, 5: 32b, 1,3,6,7: Reserved                                    */
      __IOM uint32_t FRLEN1     : 7;            /*!< [14..8] Number of channels in phase 1; 0: 1 Channel in phase
                                                     2, .. 0x7: 8 channels in phase 1                                          */
            uint32_t            : 1;
      __IOM uint32_t SSZ2       : 3;            /*!< [18..16] Receive audio sample length for phase 2. 0: 8b, 2:
                                                     16b, 4: 24b, 5: 32b, 1,3,6,7: Reserved                                    */
      __IOM uint32_t DATADLY    : 2;            /*!< [20..19] Receive data delay bit count. Valid values are 0-2,
                                                     3 is reserved.                                                            */
      __IOM uint32_t WDLEN2     : 3;            /*!< [23..21] Receive channel length in bits for phase 2. 0: 8b,
                                                     2: 16b, 4: 24b, 5: 32b, 1,3,6,7: Reserved                                 */
      __IOM uint32_t FRLEN2     : 7;            /*!< [30..24] Number of channels in phase 2; 0: 1 Channel in phase
                                                     2, .. 0x7: 8 channels in phase 2                                          */
      __IOM uint32_t PH         : 1;            /*!< [31..31] Read Phase Bit. 0: Single Phase frame; 1: Dual-Phase
                                                     frame.                                                                    */
    } I2SDATACFG_b;
  } ;

  union {
    __IOM uint32_t I2SIOCFG;                    /*!< (@ 0x00000044) Specified polarity and clock configuration of
                                                                    the I2S IPB clocks and IO signals                          */

    struct {
      __IOM uint32_t OEN        : 1;            /*!< [0..0] Output enable for SDATA output                                     */
            uint32_t            : 3;
      __IOM uint32_t FPER       : 12;           /*!< [15..4] Frame period in units of sclk. Period is FPER + 1 sclks
                                                     in length. 0: 1 sclk, 0x3F: 64 sclks                                      */
      __IOM uint32_t FSP        : 1;            /*!< [16..16] Polarity of fsync/lr_clk signal. 0: Active high. 1:
                                                     Active low                                                                */
      __IOM uint32_t PRTX       : 1;            /*!< [17..17] Transmit clock edge polarity bit. 0: sdata is transmitted
                                                     starting from the falling edge of sclk. 1: sdata is transmitted
                                                     starting from the rising edge of sclk.                                    */
      __IOM uint32_t MSL        : 1;            /*!< [18..18] Master/Slave clock configuration. 0: External clock(sclk
                                                     and lr_clk provided externally). 1: Internal clock (sclk
                                                     and lr_clk sourced internally).                                           */
      __IOM uint32_t PRx        : 1;            /*!< [19..19] Receive clock edge polarity bit. 0: sdata is sampled
                                                     on the rising edge of sclk. 1: sdata is sampled on the
                                                     falling edge of sclk.                                                     */
      __IOM uint32_t FWID       : 8;            /*!< [27..20] period of fsync/lr_clk in units of sclks                         */
            uint32_t            : 4;
    } I2SIOCFG_b;
  } ;

  union {
    __IOM uint32_t I2SCTL;                      /*!< (@ 0x00000048) Specified polarity and clock configuration of
                                                                    the I2S IPB clocks and IO signals                          */

    struct {
      __IOM uint32_t TXEN       : 1;            /*!< [0..0] Transmit enable signal. 1 will enable the transmission
                                                     of serial audio. For Full duplex operation, RXEN and TXEN
                                                     MUST be set in a single register write access, or the Slave
                                                     FSM may ignore one of the bit-field read-modify-write accesses.
                                                     TXRST and RXRST must be cleared in advance.                               */
      __IOM uint32_t TXRST      : 1;            /*!< [1..1] Transmit reset signal. 1 will reset the TX side registers
                                                     and flush the TX FIFO.                                                    */
            uint32_t            : 2;
      __IOM uint32_t RXEN       : 1;            /*!< [4..4] Receive enable control. 1: Enables capture of serial
                                                     audio, starting with first channel. 0: No receive data
                                                     captured. For Full duplex operation, RXEN and TXEN MUST
                                                     be set in a single register write access, or the Slave
                                                     FSM may ignore one of the bit-field read-modify-write accesses.
                                                     TXRST and RXRST must be cleared in advance.                               */
      __IOM uint32_t RXRST      : 1;            /*!< [5..5] Active high receiver reset signal. 1: Flush the RX FIFO            */
            uint32_t            : 25;
      __IOM uint32_t I2SVAL     : 1;            /*!< [31..31] I2S validity bit mode. 1: RX data stored only when
                                                     validity mask condition is asserted. 0: No validity mask
                                                     conditions checking is done.                                              */
    } I2SCTL_b;
  } ;

  union {
    __IOM uint32_t IPBIRPT;                     /*!< (@ 0x0000004C) Additional mask and status registers for the
                                                                    IPB core.                                                  */

    struct {
      __IOM uint32_t RXFFM      : 1;            /*!< [0..0] Receive FIFO interrupt mask. Will assert interrupt when
                                                     = 1 and RXFFI is asserted                                                 */
      __IOM uint32_t TXFFM      : 1;            /*!< [1..1] Transmit FIFO interrupt mask. Will assert interrupt when
                                                     = 1 and TXFFI is asserted                                                 */
      __IOM uint32_t RXFM       : 1;            /*!< [2..2] Receive FIFO interrupt mask. Will assert interrupt when
                                                     = 1 and RXFI is asserted                                                  */
      __IOM uint32_t TXEM       : 1;            /*!< [3..3] Transmit FIFO interrupt mask. Will assert interrupt when
                                                     = 1 and TXEI is asserted                                                  */
      __IOM uint32_t RXDMAM     : 1;            /*!< [4..4] Receive FIFO interrupt mask. Will assert interrupt when
                                                     = 1 and cimdmareq_rx is asserted                                          */
      __IOM uint32_t TXDMAM     : 1;            /*!< [5..5] Transmit FIFO interrupt mask. Will assert interrupt when
                                                     = 1 and cimdmareq_tx is asserted                                          */
            uint32_t            : 10;
      __IOM uint32_t RXFFI      : 1;            /*!< [16..16] Receive fifo high limit interrupt                                */
      __IOM uint32_t TXFFI      : 1;            /*!< [17..17] Transmit fifo low limit interrupt                                */
      __IOM uint32_t RXFI       : 1;            /*!< [18..18] RX Full interrupt. RX unit attempted to write to a
                                                     full FIFO                                                                 */
      __IOM uint32_t TXEI       : 1;            /*!< [19..19] TX Empty interrupt. TX unit attempted to read an empty
                                                     FIFO                                                                      */
      __IOM uint32_t RXDMAI     : 1;            /*!< [20..20] RX dma interrupt                                                 */
      __IOM uint32_t TXDMAI     : 1;            /*!< [21..21] TX dma interrupt                                                 */
            uint32_t            : 10;
    } IPBIRPT_b;
  } ;

  union {
    __IOM uint32_t IPCOREID;                    /*!< (@ 0x00000050) Returns the core ID of the IPB core, and used
                                                                    to write the I2S validity mask.                            */

    struct {
            uint32_t            : 16;
      __IOM uint32_t COREID     : 8;            /*!< [23..16] Core ID of the IPB core                                          */
      __IOM uint32_t COREFAM    : 8;            /*!< [31..24] Core Family. Also bit 31 is used to set the I2S validity
                                                     bit when a write is done.                                                 */
    } IPCOREID_b;
  } ;

  union {
    __IOM uint32_t AMQCFG;                      /*!< (@ 0x00000054) Control the enablement of the ASRC module and
                                                                    the source of the MCLK used in the IPB core.               */

    struct {
      __IOM uint32_t MCLKSRC    : 1;            /*!< [0..0] MCLK source. 1: Output of nco_clk divider. 0: MCLK from
                                                     ambiq clock configuration directly                                        */
            uint32_t            : 31;
    } AMQCFG_b;
  } ;
  __IM  uint32_t  RESERVED2[42];

  union {
    __IOM uint32_t CLKCFG;                      /*!< (@ 0x00000100) Provides clock selection and control for I2S
                                                                    clocks                                                     */

    struct {
      __IOM uint32_t MCLKEN     : 1;            /*!< [0..0] Enable for the master audio clock.                                 */
            uint32_t            : 3;
      __IOM uint32_t FSEL       : 5;            /*!< [8..4] Select the input clock frequency for the MCLK.Whenever
                                                     changing the clock source here, the MISC_HFRC2FRC bit in
                                                     the CLKGEN module must first be set. The sequence for changing
                                                     the clock source regardless of clock selection is to first
                                                     force HFRC2 on by setting the CLKGEN_MISC_HFRC2FRC bit,
                                                     select the clock source in this field, clear the CLKGEN_MISC_HFRC2FRC
                                                     bit only if HFRC2 is NOT selected, and then engage the
                                                     peripheral.If HFRC2 is the clock source, then shutting
                                                     the module down cleanly requires switchin                                 */
            uint32_t            : 3;
      __IOM uint32_t REFCLKEN   : 1;            /*!< [12..12] FUTURE USE Enable for the reference clock                        */
            uint32_t            : 3;
      __IOM uint32_t REFFSEL    : 2;            /*!< [17..16] FUTURE USE Select the input clock frequency for the
                                                     ref_clk. 0: HFRC_48MHz 1: HFRC_48MHz_GATED 2: XT_24MHz
                                                     3: HFRC2_48MHz                                                            */
            uint32_t            : 2;
      __IOM uint32_t DIV3       : 1;            /*!< [20..20] 0: no change to the clock selected by FSEL 1: frequency
                                                     divide-by-3 of the clock selected by FSEL                                 */
            uint32_t            : 11;
    } CLKCFG_b;
  } ;
  __IM  uint32_t  RESERVED3[63];

  union {
    __IOM uint32_t DMACFG;                      /*!< (@ 0x00000200) Configuration control of the DMA process, including
                                                                    the direction of DMA, and enablement of
                                                                    DMA                                                        */

    struct {
      __IOM uint32_t RXDMAEN    : 1;            /*!< [0..0] DMA Enable for RX channel. Setting this bit to EN will
                                                     start the DMA operation. This should be the last DMA related
                                                     register set prior to issuing the command                                 */
      __IOM uint32_t RXDMAPRI   : 1;            /*!< [1..1] Sets the Priority of the RXDMA request                             */
            uint32_t            : 2;
      __IOM uint32_t TXDMAEN    : 1;            /*!< [4..4] DMA Enable for TX channel. Setting this bit to EN will
                                                     start the DMA operation. This should be the last DMA related
                                                     register set prior to issuing the command                                 */
      __IOM uint32_t TXDMAPRI   : 1;            /*!< [5..5] Sets the Priority of the TXDMA request                             */
            uint32_t            : 2;
      __IOM uint32_t TXREQCNT   : 8;            /*!< [15..8] Number of blocks of samples transferred before asserting
                                                     the TXREQCNT interrupt signal. A block is 8 samples. The
                                                     interrupt will assert if enabled and after TXREQCNT blocks
                                                     of data has been transferred to the I2S module from the
                                                     device. A value of 0 will cause the assertion of the interrupt
                                                     for every block of transfer done.                                         */
      __IOM uint32_t RXREQCNT   : 8;            /*!< [23..16] Number of blocks of samples transferred before asserting
                                                     the RXREQCNT interrupt signal. A block is 8 samples. The
                                                     interrupt will assert if enabled and after RXREQCNT blocks
                                                     of data has been transferred from the I2S into the device.
                                                     A value of 0 will cause the assertion of the interrupt
                                                     for every block of transfer done.                                         */
            uint32_t            : 8;
    } DMACFG_b;
  } ;

  union {
    __IOM uint32_t RXDMATOTCNT;                 /*!< (@ 0x00000204) Contains the total count of samples to be stored
                                                                    for the current RX DMA operation. This register
                                                                    is updated as DMA beats complete.                          */

    struct {
      __IOM uint32_t RXTOTCNT   : 12;           /*!< [11..0] Number of 32b audio samples to transfer for RX DMA.               */
            uint32_t            : 20;
    } RXDMATOTCNT_b;
  } ;

  union {
    __IOM uint32_t RXDMAADDR;                   /*!< (@ 0x00000208) The address which the DMA operation will store
                                                                    the incoming audio samples. This address
                                                                    is updated as the samples are stored.                      */

    struct {
      __IOM uint32_t RXTARGADDR : 32;           /*!< [31..0] Address bits of the target byte address for source of
                                                     RX write DMA.                                                             */
    } RXDMAADDR_b;
  } ;

  union {
    __IOM uint32_t RXDMASTAT;                   /*!< (@ 0x0000020C) Status of the RX DMA operation currently in progress.      */

    struct {
      __IOM uint32_t RXDMATIP   : 1;            /*!< [0..0] RX DMA Transfer In Progress indicator. 1 will indicate
                                                     that a DMA transfer is active. The DMA transfer may be
                                                     waiting on data, transferring data, or waiting for priority.All
                                                     of these will be indicated with a 1. A 0 will indicate
                                                     that the DMA is fully complete and no further transactions
                                                     will be done. This bit is read only.                                      */
      __IOM uint32_t RXDMACPL   : 1;            /*!< [1..1] RX DMA Transfer Complete. This signals the end of the
                                                     DMA operation. This bit can be cleared by writing to 0,
                                                     and will also be cleared when a new DMA is started.                       */
      __IOM uint32_t RXDMAERR   : 1;            /*!< [2..2] RX DMA Error. This active high bit signals an error was
                                                     encountered during the DMA operation. The bit can be cleared
                                                     by writing to 0. Once set, this bit will remain set until
                                                     cleared by software.                                                      */
            uint32_t            : 29;
    } RXDMASTAT_b;
  } ;

  union {
    __IOM uint32_t TXDMATOTCNT;                 /*!< (@ 0x00000210) Contains the total count of samples to be read
                                                                    and transmitted for the current TX DMA operation.
                                                                    This register is updated as DMA beats complete.            */

    struct {
      __IOM uint32_t TXTOTCNT   : 12;           /*!< [11..0] Number of 32b audio samples to transmit                           */
            uint32_t            : 20;
    } TXDMATOTCNT_b;
  } ;

  union {
    __IOM uint32_t TXDMAADDR;                   /*!< (@ 0x00000214) The address which the DMA operation will fetch
                                                                    the audio samples. This address is updated
                                                                    as the samples are stored.                                 */

    struct {
      __IOM uint32_t TXTARGADDR : 32;           /*!< [31..0] Address bits of the target byte address for source of
                                                     TX write DMA.                                                             */
    } TXDMAADDR_b;
  } ;

  union {
    __IOM uint32_t TXDMASTAT;                   /*!< (@ 0x00000218) Status of the TX DMA operation currently in progress.      */

    struct {
      __IOM uint32_t TXDMATIP   : 1;            /*!< [0..0] TX DMA Transfer In Progress indicator. 1 will indicate
                                                     that a DMA transfer is active. The DMA transfer may be
                                                     waiting on data, transferring data, or waiting for priority.All
                                                     of these will be indicated with a 1. A 0 will indicate
                                                     that the DMA is fully complete and no further transactions
                                                     will be done. This bit is read only.                                      */
      __IOM uint32_t TXDMACPL   : 1;            /*!< [1..1] TX DMA Transfer Complete. This signals the end of the
                                                     DMA operation. This bit can be cleared by writing to 0,
                                                     and will also be cleared when a new DMA is started.                       */
      __IOM uint32_t TXDMAERR   : 1;            /*!< [2..2] TX DMA Error. This active high bit signals an error was
                                                     encountered during the DMA operation. The bit can be cleared
                                                     by writing to 0. Once set, this bit will remain set until
                                                     cleared by software.                                                      */
            uint32_t            : 29;
    } TXDMASTAT_b;
  } ;
  __IM  uint32_t  RESERVED4[5];

  union {
    __IOM uint32_t STATUS;                      /*!< (@ 0x00000230) I2S Module Status                                          */

    struct {
      __IOM uint32_t TBD        : 1;            /*!< [0..0] To Be determined.                                                  */
            uint32_t            : 31;
    } STATUS_b;
  } ;
  __IM  uint32_t  RESERVED5[51];

  union {
    __IOM uint32_t INTEN;                       /*!< (@ 0x00000300) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t IPB        : 1;            /*!< [0..0] Interrupt from I2S module                                          */
      __IOM uint32_t RXREQCNT   : 1;            /*!< [1..1] The I2S module has completed RXREQCNT number of DMA transfers
                                                     of size 8 samples. This interrupt allows servicing of buffers
                                                     at a programmable location within the overall DMA transfer.               */
      __IOM uint32_t TXREQCNT   : 1;            /*!< [2..2] The I2S module has asserted the dma read request, based
                                                     on TX fifo level.                                                         */
      __IOM uint32_t TXDMACPL   : 1;            /*!< [3..3] A TX dma operation has completed                                   */
      __IOM uint32_t RXDMACPL   : 1;            /*!< [4..4] A RX dma operation has completed                                   */
            uint32_t            : 27;
    } INTEN_b;
  } ;

  union {
    __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000304) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t IPB        : 1;            /*!< [0..0] Interrupt from I2S module                                          */
      __IOM uint32_t RXREQCNT   : 1;            /*!< [1..1] The I2S module has completed RXREQCNT number of DMA transfers
                                                     of size 8 samples. This interrupt allows servicing of buffers
                                                     at a programmable location within the overall DMA transfer.               */
      __IOM uint32_t TXREQCNT   : 1;            /*!< [2..2] The I2S module has asserted the dma read request, based
                                                     on TX fifo level.                                                         */
      __IOM uint32_t TXDMACPL   : 1;            /*!< [3..3] A TX dma operation has completed                                   */
      __IOM uint32_t RXDMACPL   : 1;            /*!< [4..4] A RX dma operation has completed                                   */
            uint32_t            : 27;
    } INTSTAT_b;
  } ;

  union {
    __IOM uint32_t INTCLR;                      /*!< (@ 0x00000308) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t IPB        : 1;            /*!< [0..0] Interrupt from I2S module                                          */
      __IOM uint32_t RXREQCNT   : 1;            /*!< [1..1] The I2S module has completed RXREQCNT number of DMA transfers
                                                     of size 8 samples. This interrupt allows servicing of buffers
                                                     at a programmable location within the overall DMA transfer.               */
      __IOM uint32_t TXREQCNT   : 1;            /*!< [2..2] The I2S module has asserted the dma read request, based
                                                     on TX fifo level.                                                         */
      __IOM uint32_t TXDMACPL   : 1;            /*!< [3..3] A TX dma operation has completed                                   */
      __IOM uint32_t RXDMACPL   : 1;            /*!< [4..4] A RX dma operation has completed                                   */
            uint32_t            : 27;
    } INTCLR_b;
  } ;

  union {
    __IOM uint32_t INTSET;                      /*!< (@ 0x0000030C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t IPB        : 1;            /*!< [0..0] Interrupt from I2S module                                          */
      __IOM uint32_t RXREQCNT   : 1;            /*!< [1..1] The I2S module has completed RXREQCNT number of DMA transfers
                                                     of size 8 samples. This interrupt allows servicing of buffers
                                                     at a programmable location within the overall DMA transfer.               */
      __IOM uint32_t TXREQCNT   : 1;            /*!< [2..2] The I2S module has asserted the dma read request, based
                                                     on TX fifo level.                                                         */
      __IOM uint32_t TXDMACPL   : 1;            /*!< [3..3] A TX dma operation has completed                                   */
      __IOM uint32_t RXDMACPL   : 1;            /*!< [4..4] A RX dma operation has completed                                   */
            uint32_t            : 27;
    } INTSET_b;
  } ;
  __IM  uint32_t  RESERVED6[60];

  union {
    __IOM uint32_t I2SDBG;                      /*!< (@ 0x00000400) Debug control                                              */

    struct {
      __IOM uint32_t DBGEN      : 1;            /*!< [0..0] Debug Enable. Setting bit will enable the update of data
                                                     within this register, otherwise it is clock gated for power
                                                     savings                                                                   */
      __IOM uint32_t MCLKON     : 1;            /*!< [1..1] MCLK debug clock control. Enable MCLK to be active when
                                                     this bit is '1'. Otherwise, the clock is controlled with
                                                     gating from the logic as needed.                                          */
      __IOM uint32_t APBCLKON   : 1;            /*!< [2..2] APBCLK debug clock control. Enable APB_CLK to be active
                                                     when this bit is '1'. Otherwise, the clock is controlled
                                                     with gating from the logic as needed.                                     */
      __IOM uint32_t DBGDATA    : 29;           /*!< [31..3] Debug control for various options. DBGDATA[1:0] is used
                                                     to select between different debug data available in the
                                                     DBG0 and DBG1 registers.                                                  */
    } I2SDBG_b;
  } ;
} I2S0_Type;                                    /*!< Size = 1028 (0x404)                                                       */



/* =========================================================================================================================== */
/* ================                                           IOM0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief IO Peripheral Master (IOM0)
  */

typedef struct {                                /*!< (@ 0x40050000) IOM0 Structure                                             */

  union {
    __IOM uint32_t FIFO;                        /*!< (@ 0x00000000) Provides direct random access to both input and
                                                                    output fifos. The state of the FIFO is not
                                                                    distured by reading these locations (ie
                                                                    no POP will be done). FIFO0 is accessible
                                                                    from addresses 0x0 - 0x1C, and is used for
                                                                    data outuput from the IOM to external devices.
                                                                    These FIFO locations can be read and written
                                                                    directly.FIFO locations 0x20 - 0x3C provide
                                                                    read only access to the input fifo. These
                                                                    FIFO locations cannot be directly written
                                                                    by the MCU, and are updated only by the
                                                                    internal hardware.                                         */

    struct {
      __IOM uint32_t FIFO       : 32;           /*!< [31..0] FIFO direct access. Only locations 0 - 3F will return
                                                     valid information.                                                        */
    } FIFO_b;
  } ;
  __IM  uint32_t  RESERVED[63];

  union {
    __IOM uint32_t FIFOPTR;                     /*!< (@ 0x00000100) Provides the current valid byte count of data
                                                                    within the FIFO as seen from the internal
                                                                    state machines. FIFO0 is dedicated to outgoing
                                                                    transactions and FIFO1 is dedicated to incoming
                                                                    transactions. All counts are specified in
                                                                    units of bytes.                                            */

    struct {
      __IOM uint32_t FIFO0SIZ   : 8;            /*!< [7..0] The number of valid data bytes currently in the FIFO
                                                     0 (written by MCU, read by interface)                                     */
      __IOM uint32_t FIFO0REM   : 8;            /*!< [15..8] The number of remaining data bytes slots currently in
                                                     FIFO 0 (written by MCU, read by interface)                                */
      __IOM uint32_t FIFO1SIZ   : 8;            /*!< [23..16] The number of valid data bytes currently in FIFO 1
                                                     (written by interface, read by MCU)                                       */
      __IOM uint32_t FIFO1REM   : 8;            /*!< [31..24] The number of remaining data bytes slots currently
                                                     in FIFO 1 (written by interface, read by MCU)                             */
    } FIFOPTR_b;
  } ;

  union {
    __IOM uint32_t FIFOTHR;                     /*!< (@ 0x00000104) Sets the threshold values for incoming and outgoing
                                                                    transactions. The threshold values are used
                                                                    to assert the interrupt if enabled, and
                                                                    also used during DMA to set the transfer
                                                                    size as a result of DMATHR trigger.The WTHR
                                                                    is used to indicate when there are more
                                                                    than WTHR bytes of open fifo locations available
                                                                    in the outgoing FIFO (FIFO0). The intended
                                                                    use to invoke an interrupt or DMA transfer
                                                                    that will refill the FIFO with a byte count
                                                                    up to this value.The RTHR is used to indicate
                                                                    when t                                                     */

    struct {
      __IOM uint32_t FIFORTHR   : 6;            /*!< [5..0] FIFO read threshold in bytes. A value of 0 will disable
                                                     the read FIFO level from activating the threshold interrupt.
                                                     If this field is non-zero, it will trigger a threshold
                                                     interrupt when the read fifo contains FIFORTHR valid bytes
                                                     of data, as indicated by the FIFO1SIZ field. This is intended
                                                     to signal when a data transfer of FIFORTHR bytes can be
                                                     done from the IOM module to the host via the read fifo
                                                     to support large IOM read operations.                                     */
            uint32_t            : 2;
      __IOM uint32_t FIFOWTHR   : 6;            /*!< [13..8] FIFO write threshold in bytes. A value of 0 will disable
                                                     the write FIFO level from activating the threshold interrupt.
                                                     If this field is non-zero, it will trigger a threshold
                                                     interrupt when the write fifo contains FIFOWTHR free bytes,
                                                     as indicated by the FIFO0REM field. This is intended to
                                                     signal when a transfer of FIFOWTHR bytes can be done from
                                                     the host to the IOM write fifo to support large IOM write
                                                     operations.                                                               */
            uint32_t            : 18;
    } FIFOTHR_b;
  } ;

  union {
    __IOM uint32_t FIFOPOP;                     /*!< (@ 0x00000108) Will advance the internal read pointer of the
                                                                    incoming FIFO (FIFO1) when read, if POPWR
                                                                    is not active. If POPWR is active, a write
                                                                    to this register is needed to advance the
                                                                    internal FIFO pointer.                                     */

    struct {
      __IOM uint32_t FIFODOUT   : 32;           /*!< [31..0] This register will return the read data indicated by
                                                     the current read pointer on reads. If the POPWR control
                                                     bit in the FIFOCTRL register is reset (0), the fifo read
                                                     pointer will be advanced by one word as a result of the
                                                     read.If the POPWR bit is set (1), the fifo read pointer
                                                     will only be advanced after a write operation to this register.
                                                     The write data is ignored for this register.If less than
                                                     a even word multiple is available, and the command is completed,
                                                     the module will return the word containing                                */
    } FIFOPOP_b;
  } ;

  union {
    __IOM uint32_t FIFOPUSH;                    /*!< (@ 0x0000010C) Will write new data into the outgoing FIFO and
                                                                    advance the internal write pointer.                        */

    struct {
      __IOM uint32_t FIFODIN    : 32;           /*!< [31..0] This register is used to write the FIFORAM in FIFO mode
                                                     and will cause a push event to occur to the next open slot
                                                     within the FIFORAM. Writing to this register will cause
                                                     the write point to increment by 1 word(4 bytes).                          */
    } FIFOPUSH_b;
  } ;

  union {
    __IOM uint32_t FIFOCTRL;                    /*!< (@ 0x00000110) Provides controls for the operation of the internal
                                                                    FIFOs. Contains fields used to control the
                                                                    operation of the POP register, and also
                                                                    controls to reset the internal pointers
                                                                    of the FIFOs.                                              */

    struct {
      __IOM uint32_t POPWR      : 1;            /*!< [0..0] Selects the mode in which 'pop' events are done for the
                                                     fifo read operations. A value of '1' will prevent a pop
                                                     event on a read operation, and will require a write to
                                                     the FIFOPOP register to create a pop event.A value of '0'
                                                     in this register will allow a pop event to occur on the
                                                     read of the FIFOPOP register, and may cause inadvertant
                                                     fifo pops when used in a debugging mode.                                  */
      __IOM uint32_t FIFORSTN   : 1;            /*!< [1..1] Active low manual reset of the fifo. Write to 0 to reset
                                                     fifo, and then write to 1 to remove the reset.                            */
            uint32_t            : 30;
    } FIFOCTRL_b;
  } ;

  union {
    __IOM uint32_t FIFOLOC;                     /*!< (@ 0x00000114) Provides a read only value of the current read
                                                                    and write pointers. This register is read
                                                                    only and can be used alogn with the FIFO
                                                                    direct access method to determine the next
                                                                    data to be used for input and output functions.            */

    struct {
      __IOM uint32_t FIFOWPTR   : 4;            /*!< [3..0] Current FIFO write pointer. Value is the index into the
                                                     outgoing FIFO (FIFO0), which is used during write operations
                                                     to external devices.                                                      */
            uint32_t            : 4;
      __IOM uint32_t FIFORPTR   : 4;            /*!< [11..8] Current FIFO read pointer. Used to index into the incoming
                                                     FIFO (FIFO1), which is used to store read data returned
                                                     from external devices during a read operation.                            */
            uint32_t            : 20;
    } FIFOLOC_b;
  } ;

  union {
    __IOM uint32_t CLKCFG;                      /*!< (@ 0x00000118) Provides clock related controls used internal
                                                                    to the BLEIF module, and enablement of 32KHz
                                                                    clock to the BLE Core module. The internal
                                                                    clock sourced is selected via the FSEL and
                                                                    can be further divided by 3 using the DIV3
                                                                    control.This register is also used to enable
                                                                    the clock, which must be done prior to performing
                                                                    any IO transactions.                                       */

    struct {
      __IOM uint32_t IOCLKEN    : 1;            /*!< [0..0] Enable for the interface clock. Must be enabled prior
                                                     to executing any IO operations.                                           */
            uint32_t            : 7;
      __IOM uint32_t FSEL       : 3;            /*!< [10..8] Select the input clock frequency.                                 */
      __IOM uint32_t DIV3       : 1;            /*!< [11..11] Enable divide by 3 of the source IOCLK. Division by
                                                     3 is done before the DIVEN programmable divider, and if
                                                     enabledwill provide the divided by 3 clock as the source
                                                     to the programmable divider.                                              */
      __IOM uint32_t DIVEN      : 1;            /*!< [12..12] Enable clock division by TOTPER and LOWPER                       */
            uint32_t            : 3;
      __IOM uint32_t LOWPER     : 8;            /*!< [23..16] Clock low clock count minus 1. This provides the number
                                                     of clocks the divided clock will be low when the DIVEN
                                                     = 1.Only applicable when DIVEN = 1.                                       */
      __IOM uint32_t TOTPER     : 8;            /*!< [31..24] Clock total clock count minus 1. This provides the
                                                     total period of the divided clock -1 when the DIVEN is
                                                     active. Thesource clock is selected by FSEL. Only applicable
                                                     when DIVEN = 1.                                                           */
    } CLKCFG_b;
  } ;

  union {
    __IOM uint32_t SUBMODCTRL;                  /*!< (@ 0x0000011C) Provides enable for each submodule. Only a sigle
                                                                    submodule can be enabled at one time.                      */

    struct {
      __IOM uint32_t SMOD0EN    : 1;            /*!< [0..0] Submodule 0 enable (1) or disable (0)                              */
      __IOM uint32_t SMOD0TYPE  : 3;            /*!< [3..1] Submodule 0 module type. This is the SPI Master interface.         */
      __IOM uint32_t SMOD1EN    : 1;            /*!< [4..4] Submodule 1 enable (1) or disable (0)                              */
      __IOM uint32_t SMOD1TYPE  : 3;            /*!< [7..5] Submodule 1 module type. This is the I2C Master interface          */
      __IOM uint32_t SMOD2EN    : 1;            /*!< [8..8] Submodule 2 enable (1) or disable (0)                              */
      __IOM uint32_t SMOD2TYPE  : 3;            /*!< [11..9] Submodule 2 module type. This is the I2S Master/Slave
                                                     interface                                                                 */
            uint32_t            : 20;
    } SUBMODCTRL_b;
  } ;

  union {
    __IOM uint32_t CMD;                         /*!< (@ 0x00000120) Writes to this register will start an IO transaction,
                                                                    as well as set various parameters for the
                                                                    command itself. Reads will return the command
                                                                    value written to the CMD register.To read
                                                                    the number of bytes that have yet to be
                                                                    transferred, refer to the CTSIZE field within
                                                                    the CMDSTAT register.                                      */

    struct {
      __IOM uint32_t CMD        : 4;            /*!< [3..0] Command for submodule.                                             */
      __IOM uint32_t OFFSETCNT  : 3;            /*!< [6..4] Number of offset bytes to use for the command - 0, 1,
                                                     2, 3, 4, 5 are valid selections. The second (byte 1),third
                                                     (byte 2), and forth (byte 3) are read from the OFFSETHI
                                                     register, and the low order byte is pulled from this register
                                                     in the OFFSETLO field.Offset bytes are transmitted highest
                                                     byte first. EG if offsetcnt == 4, OFFSETHI[23:16] will
                                                     be transmitted first, then OFFSETHI[15:8], then OFFSETHI[7:0]
                                                     then OFFSETLO.If offsetcnt == 5, OFFSETHI[31:24] will be
                                                     transmitted, then OFFSETHI[23:0], then O                                  */
      __IOM uint32_t CONT       : 1;            /*!< [7..7] Contine to hold the bus after the current transaction
                                                     if set to a 1 with a new command issued.                                  */
      __IOM uint32_t TSIZE      : 12;           /*!< [19..8] Defines the transaction size in bytes. The offset transfer
                                                     is not included in this size.                                             */
      __IOM uint32_t CMDSEL     : 2;            /*!< [21..20] Command Specific selection information. Not used in
                                                     Master I2C. Used as CEn select for Master SPI transactions                */
            uint32_t            : 2;
      __IOM uint32_t OFFSETLO   : 8;            /*!< [31..24] This register holds the low order byte of offset to
                                                     be used in the transaction. The number of offset bytes
                                                     to use is set with bits 1:0 of the command.                               */
    } CMD_b;
  } ;

  union {
    __IOM uint32_t DCXCTRL;                     /*!< (@ 0x00000124) Enables transmission of DCX signal with SPI transactions
                                                                    and selects which CE signals will be used
                                                                    to transmit the DCX signal.                                */

    struct {
      __IOM uint32_t DCXSEL     : 4;            /*!< [3..0] Selects the CE channel used to convey the DCX function.
                                                     The select is bitwise encoded, with bit 0 = 1 enabling
                                                     CE0 for DCX transmission, bit 1 = 1 enableing CE1 for DCX
                                                     transmission, etc. If the CE used for the SPI transaction
                                                     is set, it will be ignored and used as the transaction
                                                     CE instead. Multiple CE channels can be selected at once.
                                                     To enable the DCX signal to be transmitted out of the chip,
                                                     the corresponding pin mux function must be enabled in the
                                                     GPIO logic as well.                                                       */
      __IOM uint32_t DCXEN      : 1;            /*!< [4..4] Global enable of the DCX function. Setting to 1 will
                                                     enable the generation of the DCX signal, which will assert
                                                     when sending the offset bytes of the SPI transaction.                     */
            uint32_t            : 27;
    } DCXCTRL_b;
  } ;

  union {
    __IOM uint32_t OFFSETHI;                    /*!< (@ 0x00000128) High order bytes of offset for IO transaction              */

    struct {
      __IOM uint32_t OFFSETHI   : 32;           /*!< [31..0] Holds the high order bytes of the byte addressing/offset
                                                     field to use with IO commands. The number of offset bytes
                                                     to use is specified in the command register                               */
    } OFFSETHI_b;
  } ;

  union {
    __IOM uint32_t CMDSTAT;                     /*!< (@ 0x0000012C) Provides staus on the execution of the command
                                                                    currently in progress. The fields in this
                                                                    register will reflect the real time status
                                                                    of the internal state machines and data
                                                                    transfers within the IOM.These are read
                                                                    only fields and writes to the registers
                                                                    are ignored.                                               */

    struct {
      __IOM uint32_t CCMD       : 5;            /*!< [4..0] current command that is being executed                             */
      __IOM uint32_t CMDSTAT    : 3;            /*!< [7..5] The current status of the command execution.                       */
      __IOM uint32_t CTSIZE     : 12;           /*!< [19..8] The current number of bytes still to be transferred
                                                     with this command. This field will count down to zero.                    */
            uint32_t            : 12;
    } CMDSTAT_b;
  } ;
  __IM  uint32_t  RESERVED1[52];

  union {
    __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
                                                     operation has completed. For repeated commands, this will
                                                     only be asserted when the final repeated command is completed.            */
      __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
                                                     when the number of free bytes in the write FIFO equals
                                                     or exceeds the WTHR field.For read operations, asserted
                                                     when the number of valid bytes in the read FIFO equals
                                                     of exceeds the value set in the RTHR field.                               */
      __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
                                                     tries to pop from an empty fifo.                                          */
      __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
                                                     tries to write to a full fifo. The current operation does
                                                     not stop.                                                                 */
      __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
                                                     been received on the I2C bus.                                             */
      __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
                                                     a overflow or underflow event                                             */
      __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
                                                     written when an active command is in progress.                            */
      __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
                                                     on the bus has signaled a START command.                                  */
      __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
                                                     on the bus has signaled a STOP command.                                   */
      __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
                                                     is enabled and has been lost to another master on the bus.                */
      __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
                                                     and the DMA submodule is returned into the idle state                     */
      __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
                                                     DMA command. The DMA error could occur when the memory
                                                     access specified in the DMA operation is not available
                                                     or incorrectly specified.                                                 */
      __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
                                                     in the PAUSEEN register. The interrupt is posted when the
                                                     event is enabled within the PAUSEEN register, the mask
                                                     is active in the CQIRQMASK field and the event occurs.                    */
      __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
                                                     the register address bit 0 set to 1. The low address bits
                                                     in the CQ address fields are unused and bit 0 can be used
                                                     to trigger an interrupt to indicate when this register
                                                     write is performed by the CQ operation.                                   */
      __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
            uint32_t            : 17;
    } INTEN_b;
  } ;

  union {
    __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
                                                     operation has completed. For repeated commands, this will
                                                     only be asserted when the final repeated command is completed.            */
      __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
                                                     when the number of free bytes in the write FIFO equals
                                                     or exceeds the WTHR field.For read operations, asserted
                                                     when the number of valid bytes in the read FIFO equals
                                                     of exceeds the value set in the RTHR field.                               */
      __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
                                                     tries to pop from an empty fifo.                                          */
      __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
                                                     tries to write to a full fifo. The current operation does
                                                     not stop.                                                                 */
      __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
                                                     been received on the I2C bus.                                             */
      __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
                                                     a overflow or underflow event                                             */
      __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
                                                     written when an active command is in progress.                            */
      __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
                                                     on the bus has signaled a START command.                                  */
      __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
                                                     on the bus has signaled a STOP command.                                   */
      __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
                                                     is enabled and has been lost to another master on the bus.                */
      __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
                                                     and the DMA submodule is returned into the idle state                     */
      __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
                                                     DMA command. The DMA error could occur when the memory
                                                     access specified in the DMA operation is not available
                                                     or incorrectly specified.                                                 */
      __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
                                                     in the PAUSEEN register. The interrupt is posted when the
                                                     event is enabled within the PAUSEEN register, the mask
                                                     is active in the CQIRQMASK field and the event occurs.                    */
      __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
                                                     the register address bit 0 set to 1. The low address bits
                                                     in the CQ address fields are unused and bit 0 can be used
                                                     to trigger an interrupt to indicate when this register
                                                     write is performed by the CQ operation.                                   */
      __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
            uint32_t            : 17;
    } INTSTAT_b;
  } ;

  union {
    __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
                                                     operation has completed. For repeated commands, this will
                                                     only be asserted when the final repeated command is completed.            */
      __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
                                                     when the number of free bytes in the write FIFO equals
                                                     or exceeds the WTHR field.For read operations, asserted
                                                     when the number of valid bytes in the read FIFO equals
                                                     of exceeds the value set in the RTHR field.                               */
      __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
                                                     tries to pop from an empty fifo.                                          */
      __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
                                                     tries to write to a full fifo. The current operation does
                                                     not stop.                                                                 */
      __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
                                                     been received on the I2C bus.                                             */
      __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
                                                     a overflow or underflow event                                             */
      __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
                                                     written when an active command is in progress.                            */
      __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
                                                     on the bus has signaled a START command.                                  */
      __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
                                                     on the bus has signaled a STOP command.                                   */
      __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
                                                     is enabled and has been lost to another master on the bus.                */
      __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
                                                     and the DMA submodule is returned into the idle state                     */
      __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
                                                     DMA command. The DMA error could occur when the memory
                                                     access specified in the DMA operation is not available
                                                     or incorrectly specified.                                                 */
      __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
                                                     in the PAUSEEN register. The interrupt is posted when the
                                                     event is enabled within the PAUSEEN register, the mask
                                                     is active in the CQIRQMASK field and the event occurs.                    */
      __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
                                                     the register address bit 0 set to 1. The low address bits
                                                     in the CQ address fields are unused and bit 0 can be used
                                                     to trigger an interrupt to indicate when this register
                                                     write is performed by the CQ operation.                                   */
      __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
            uint32_t            : 17;
    } INTCLR_b;
  } ;

  union {
    __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
                                                     operation has completed. For repeated commands, this will
                                                     only be asserted when the final repeated command is completed.            */
      __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
                                                     when the number of free bytes in the write FIFO equals
                                                     or exceeds the WTHR field.For read operations, asserted
                                                     when the number of valid bytes in the read FIFO equals
                                                     of exceeds the value set in the RTHR field.                               */
      __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
                                                     tries to pop from an empty fifo.                                          */
      __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
                                                     tries to write to a full fifo. The current operation does
                                                     not stop.                                                                 */
      __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
                                                     been received on the I2C bus.                                             */
      __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
                                                     a overflow or underflow event                                             */
      __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
                                                     written when an active command is in progress.                            */
      __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
                                                     on the bus has signaled a START command.                                  */
      __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
                                                     on the bus has signaled a STOP command.                                   */
      __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
                                                     is enabled and has been lost to another master on the bus.                */
      __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
                                                     and the DMA submodule is returned into the idle state                     */
      __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
                                                     DMA command. The DMA error could occur when the memory
                                                     access specified in the DMA operation is not available
                                                     or incorrectly specified.                                                 */
      __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
                                                     in the PAUSEEN register. The interrupt is posted when the
                                                     event is enabled within the PAUSEEN register, the mask
                                                     is active in the CQIRQMASK field and the event occurs.                    */
      __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
                                                     the register address bit 0 set to 1. The low address bits
                                                     in the CQ address fields are unused and bit 0 can be used
                                                     to trigger an interrupt to indicate when this register
                                                     write is performed by the CQ operation.                                   */
      __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
            uint32_t            : 17;
    } INTSET_b;
  } ;

  union {
    __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000210) Provides control on which event will trigger
                                                                    the DMA transfer after the DMA operation
                                                                    is setup and enabled. The trigger event
                                                                    will cause a number of bytes (depending
                                                                    on trigger event) to betransferred via the
                                                                    DMA operation, and can be used to adjust
                                                                    the latency of data to/from the IOM module
                                                                    to/from the dma target. DMA transfers are
                                                                    broken into smaller transfers internally
                                                                    of up to16 bytes each, and multiple trigger
                                                                    events can be used to complete the entire
                                                                    programmed DMA transfer.                                   */

    struct {
      __IOM uint32_t DCMDCMPEN  : 1;            /*!< [0..0] Trigger DMA upon command complete. Enables the trigger
                                                     of the DMA when a command is completed. When this event
                                                     is triggered, the number of words transferred will be the
                                                     lesser of the remaining TOTCOUNT bytes, or                                */
      __IOM uint32_t DTHREN     : 1;            /*!< [1..1] Trigger DMA upon THR level reached. For M2P DMA operations
                                                     (IOM writes), the trigger will assert when the write FIFO
                                                     has (WTHR/4) number of words free in the write FIFO, and
                                                     will transfer (WTHR/4) number of wordsor, if the number
                                                     of words left to transfer is less than the WTHR value,
                                                     will transfer the remaining byte count.For P2M DMA operations,
                                                     the trigger will assert when the read FIFO has (RTHR/4)
                                                     words available in the read FIFO, and will transfer (RTHR/4)
                                                     words to SRAM. This trigger will NOT asser                                */
            uint32_t            : 30;
    } DMATRIGEN_b;
  } ;

  union {
    __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000214) Provides the status of trigger events that have
                                                                    occurred for the transaction. Some of the
                                                                    bits are read only and some can be reset
                                                                    via a write of 0.                                          */

    struct {
      __IOM uint32_t DCMDCMP    : 1;            /*!< [0..0] Triggered DMA from Command complete event. Bit is read
                                                     only and can be cleared by disabling the DCMDCMP trigger
                                                     enable or by disabling DMA.                                               */
      __IOM uint32_t DTHR       : 1;            /*!< [1..1] Triggered DMA from THR event. Bit is read only and can
                                                     be cleared by disabling the DTHR trigger enable or by disabling
                                                     DMA.                                                                      */
      __IOM uint32_t DTOTCMP    : 1;            /*!< [2..2] DMA triggered when DCMDCMP = 0, and the amount of data
                                                     in the FIFO was enough to complete the DMA operation (greater
                                                     than or equal to current TOTCOUNT) when the command completed.
                                                     This trigger is default active when the DCMDCMP trigger
                                                     isdisabled and there is enough data in the FIFO to complete
                                                     the DMA operation.                                                        */
            uint32_t            : 29;
    } DMATRIGSTAT_b;
  } ;

  union {
    __IOM uint32_t DMACFG;                      /*!< (@ 0x00000218) Configuration control of the DMA process, including
                                                                    the direction of DMA, and enablement of
                                                                    DMA                                                        */

    struct {
      __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable. Setting this bit to EN will start the DMA
                                                     operation. This should be the last DMA related register
                                                     set prior to issuing the command                                          */
      __IOM uint32_t DMADIR     : 1;            /*!< [1..1] Direction                                                          */
            uint32_t            : 6;
      __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
      __IOM uint32_t DPWROFF    : 1;            /*!< [9..9] Power off module after DMA is complete. If this bit is
                                                     active, the module will request to power off the supply
                                                     it is attached to. If there are other units still requiring
                                                     power from the same domain, power down will not be performed.             */
            uint32_t            : 22;
    } DMACFG_b;
  } ;

  union {
    __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x0000021C) Contains the number of bytes to be transferred
                                                                    for this DMA transaction. This register
                                                                    is decremented as the data is transferred,
                                                                    and will be 0 at the completion of the DMA
                                                                    operation.                                                 */

    struct {
      __IOM uint32_t TOTCOUNT   : 12;           /*!< [11..0] Triggered DMA from Command complete event occured. Bit
                                                     is read only and can be cleared by disabling the DTHR trigger
                                                     enable or by disabling DMA.                                               */
            uint32_t            : 20;
    } DMATOTCOUNT_b;
  } ;

  union {
    __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x00000220) The source or destination address internal the
                                                                    SRAM for the DMA data. For write operations,
                                                                    this can only be SRAM data (ADDR bit 28
                                                                    = 1); For read operations, this can ve either
                                                                    SRAM or FLASH (ADDR bit 28 = 0)                            */

    struct {
      __IOM uint32_t TARGADDR   : 29;           /*!< [28..0] Bits [28:0] of the target byte address for source of
                                                     DMA (either read or write). The address can be any byte
                                                     alignment, and does not have to be word aligned. In cases
                                                     of non-word aligned addresses, the DMA logic will take
                                                     care for ensuring only the target bytes are read/written.                 */
            uint32_t            : 3;
    } DMATARGADDR_b;
  } ;

  union {
    __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000224) Status of the DMA operation currently in progress.         */

    struct {
      __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that
                                                     a DMA transfer is active. The DMA transfer may be waiting
                                                     on data, transferring data, or waiting for priority.All
                                                     of these will be indicated with a 1. A 0 will indicate
                                                     that the DMA is fully complete and no further transactions
                                                     will be done. This bit is read only.                                      */
      __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA
                                                     operation. This bit can be cleared by writing to 0, and
                                                     will also be cleared when a new DMA is started.                           */
      __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error. This active high bit signals an error was
                                                     encountered during the DMA operation. The bit can be cleared
                                                     by writing to 0. Once set, this bit will remain set until
                                                     cleared by software.                                                      */
            uint32_t            : 29;
    } DMASTAT_b;
  } ;

  union {
    __IOM uint32_t CQCFG;                       /*!< (@ 0x00000228) Controls parameters and options for execution
                                                                    of the command queue operation. To enable
                                                                    command queue, create this in memory, set
                                                                    the address, and enable it with a write
                                                                    to CQEN                                                    */

    struct {
      __IOM uint32_t CQEN       : 1;            /*!< [0..0] Command queue enable. When set, will enable the processing
                                                     of the command queue and fetches of address/data pairs
                                                     will proceed from the word address within the CQADDR register.
                                                     Can be disabledusing a CQ executed write to this bit as
                                                     well.                                                                     */
      __IOM uint32_t CQPRI      : 1;            /*!< [1..1] Sets the Priority of the command queue dma request                 */
      __IOM uint32_t MSPIFLGSEL : 2;            /*!< [3..2] Selects the MPSI modules used for sourcing the CQFLAG
                                                     [11:8].                                                                   */
            uint32_t            : 28;
    } CQCFG_b;
  } ;

  union {
    __IOM uint32_t CQADDR;                      /*!< (@ 0x0000022C) The SRAM address which will be fetched next execution
                                                                    of the CQ operation. This register is updated
                                                                    as the CQ operation progresses, and is the
                                                                    live version of the register. The register
                                                                    can also bewritten by the Command Queue
                                                                    operation itself, allowing the relocation
                                                                    of successive CQ fetches. In this case,
                                                                    the new CQ address will be used for the
                                                                    next CQ address/data fetch                                 */

    struct {
            uint32_t            : 2;
      __IOM uint32_t CQADDR     : 27;           /*!< [28..2] Bits 28:2 of target byte address for source of CQ .
                                                     The buffer must be aligned on a word boundary                             */
            uint32_t            : 3;
    } CQADDR_b;
  } ;

  union {
    __IOM uint32_t CQSTAT;                      /*!< (@ 0x00000230) Provides the status of the command queue operation.
                                                                    If the command queue is disabled, these
                                                                    bits will be cleared. The bits are read
                                                                    only                                                       */

    struct {
      __IOM uint32_t CQTIP      : 1;            /*!< [0..0] Command queue Transfer In Progress indicator. 1 will
                                                     indicate that a CQ transfer is active and this will remain
                                                     active even when paused waiting for external event.                       */
      __IOM uint32_t CQPAUSED   : 1;            /*!< [1..1] Command queue operation is currently paused.                       */
      __IOM uint32_t CQERR      : 1;            /*!< [2..2] Command queue processing Error. This active high bit
                                                     signals that an error was encountered during the CQ operation.            */
            uint32_t            : 29;
    } CQSTAT_b;
  } ;

  union {
    __IOM uint32_t CQFLAGS;                     /*!< (@ 0x00000234) Command Queue Flag                                         */

    struct {
      __IOM uint32_t CQFLAGS    : 16;           /*!< [15..0] Current flag status (read-only). Bits [7:0] are software
                                                     controllable and bits [15:8] are hardware status.                         */
      __IOM uint32_t CQIRQMASK  : 16;           /*!< [31..16] Mask the bits used to generate the command queue interrupt.
                                                     A '1' in the bit position will enable the pause event to
                                                     trigger the interrupt, if the CQWT_int interrupt is enabled.
                                                     Bits definitions are the same as CQPAUSE                                  */
    } CQFLAGS_b;
  } ;

  union {
    __IOM uint32_t CQSETCLEAR;                  /*!< (@ 0x00000238) Set/Clear the command queue software pause flags
                                                                    on a per-bit basis. Contains 3 fields, allowing
                                                                    for setting, clearing or toggling the value
                                                                    in the software flags. Priority when the
                                                                    same bitis enabled in each field is toggle,
                                                                    then set, then clear.                                      */

    struct {
      __IOM uint32_t CQFSET     : 8;            /*!< [7..0] Set CQFlag status bits. Will set to 1 the value of any
                                                     SWFLAG with a '1' in the corresponding bit position of
                                                     this field                                                                */
      __IOM uint32_t CQFTGL     : 8;            /*!< [15..8] Toggle the indicated bit. Will toggle the value of any
                                                     SWFLAG with a '1' in the corresponding bit position of
                                                     this field                                                                */
      __IOM uint32_t CQFCLR     : 8;            /*!< [23..16] Clear CQFlag status bits. Will clear to 0 any SWFLAG
                                                     with a '1' in the corresponding bit position of this field                */
            uint32_t            : 8;
    } CQSETCLEAR_b;
  } ;

  union {
    __IOM uint32_t CQPAUSEEN;                   /*!< (@ 0x0000023C) Enables a flag to pause an active command queue
                                                                    operation. If a bit is '1' and the corresponding
                                                                    bit in the CQFLAG register is '1', CQ processing
                                                                    will halt until either value is changed
                                                                    to '0'.                                                    */

    struct {
      __IOM uint32_t CQPEN      : 16;           /*!< [15..0] Enables the specified event to pause command processing
                                                     when active                                                               */
            uint32_t            : 16;
    } CQPAUSEEN_b;
  } ;

  union {
    __IOM uint32_t CQCURIDX;                    /*!< (@ 0x00000240) Current index value, targeted to be written by
                                                                    register write operations within the command
                                                                    queue. This is compared to the CQENDIDX
                                                                    and will stop the CQ operation if bit 15
                                                                    of the CQPAUSEEN is '1' andthis current
                                                                    index equals the CQENDIDX register value.
                                                                    This will only pause when the values are
                                                                    equal.                                                     */

    struct {
      __IOM uint32_t CQCURIDX   : 8;            /*!< [7..0] Holds 8 bits of data that will be compared with the CQENDIX
                                                     register field. If the values match, the IDXEQ pause event
                                                     will be activated, which will cause the pausing of command
                                                     quue operation if the IDXEQ bit is enabled in CQPAUSEEN.                  */
            uint32_t            : 24;
    } CQCURIDX_b;
  } ;

  union {
    __IOM uint32_t CQENDIDX;                    /*!< (@ 0x00000244) End index value, targeted to be written by software
                                                                    to indicate the last valid register pair
                                                                    contained within the command queue. rgister
                                                                    write operations within the command queue.This
                                                                    is compared to the CQCURIDX and will stop
                                                                    the CQ operation if bit 15 of the CQPAUSEEN
                                                                    is '1' andthis current index equals the
                                                                    CQCURIDX register value. This will only
                                                                    pause when the values are equal.                           */

    struct {
      __IOM uint32_t CQENDIDX   : 8;            /*!< [7..0] Holds 8 bits of data that will be compared with the CQCURIX
                                                     register field. If the values match, the IDXEQ pause event
                                                     will be activated, which will cause the pausing of command
                                                     quue operation if the IDXEQ bit is enabled in CQPAUSEEN.                  */
            uint32_t            : 24;
    } CQENDIDX_b;
  } ;

  union {
    __IOM uint32_t STATUS;                      /*!< (@ 0x00000248) IOM Module Status                                          */

    struct {
      __IOM uint32_t ERR        : 1;            /*!< [0..0] Bit has been deprecated. Please refer to the other error
                                                     indicators. This will always return 0.                                    */
      __IOM uint32_t CMDACT     : 1;            /*!< [1..1] Indicates if the active I/O Command is currently processing
                                                     a transaction, or command is complete, but the FIFO pointers
                                                     are still syncronizing internally. This bit will go high
                                                     atthe start of the transaction, and will go low when the
                                                     command is complete, and the data and pointers within the
                                                     FIFO have been syncronized.                                               */
      __IOM uint32_t IDLEST     : 1;            /*!< [2..2] indicates if the active I/O state machine is IDLE. Note
                                                     - The state machine could be in idle state due to holdoffs
                                                     from data availability, or as the command gets propagated
                                                     into the logic from the registers.                                        */
            uint32_t            : 29;
    } STATUS_b;
  } ;
  __IM  uint32_t  RESERVED2[13];

  union {
    __IOM uint32_t MSPICFG;                     /*!< (@ 0x00000280) Controls the configuration of the SPI master
                                                                    module, including POL/PHA, LSB, flow control,
                                                                    and delays for MISO and MOSI                               */

    struct {
      __IOM uint32_t SPOL       : 1;            /*!< [0..0] Selects SPI polarity.IMPORTANT NOTICE: Due to the susceptibility
                                                     of creating a clock glitch which could cause register corruption,
                                                     changing SPHA and SPOL bits should be done in separate
                                                     writes to this register.                                                  */
      __IOM uint32_t SPHA       : 1;            /*!< [1..1] Selects SPI phase.IMPORTANT NOTICE: Due to the susceptibility
                                                     of creating a clock glitch which could cause register corruption,
                                                     changing SPHA and SPOL bits should be done in separate
                                                     writes to this register.                                                  */
      __IOM uint32_t FULLDUP    : 1;            /*!< [2..2] Enables full duplex mode for Master SPI write operations.
                                                     Data will be captured simultaneously into the read fifo                   */
            uint32_t            : 13;
      __IOM uint32_t WTFC       : 1;            /*!< [16..16] enables write mode flow control.                                 */
      __IOM uint32_t RDFC       : 1;            /*!< [17..17] Enables read mode flow control.                                  */
      __IOM uint32_t MOSIINV    : 1;            /*!< [18..18] Inverts MOSI when flow control is enabled.                       */
            uint32_t            : 1;
      __IOM uint32_t WTFCIRQ    : 1;            /*!< [20..20] Selects the write mode flow control signal.                      */
      __IOM uint32_t WTFCPOL    : 1;            /*!< [21..21] selects the write flow control signal polarity. The
                                                     transfers are halted when the selected flow control signal
                                                     is OPPOSITE polarity of bit. (For example: WTFCPOL = 0
                                                     will allow a IRQ=1 to pause transfers).                                   */
      __IOM uint32_t RDFCPOL    : 1;            /*!< [22..22] Selects the read flow control signal polarity.                   */
      __IOM uint32_t SPILSB     : 1;            /*!< [23..23] Selects data transfer as MSB first (0) or LSB first
                                                     (1) for the data portion of the SPI transaction. The offset
                                                     bytes are always transmitted MSB first.                                   */
      __IOM uint32_t DINDLY     : 3;            /*!< [26..24] Delay tap to use for the input signal (MISO). This
                                                     gives more hold time on the input data.                                   */
      __IOM uint32_t DOUTDLY    : 3;            /*!< [29..27] Delay tap to use for the output signal (MOSI). This
                                                     give more hold time on the output data                                    */
      __IOM uint32_t MSPIRST    : 1;            /*!< [30..30] Not used. To reset the module, toggle the SMOD_EN for
                                                     the module                                                                */
            uint32_t            : 1;
    } MSPICFG_b;
  } ;
  __IM  uint32_t  RESERVED3[15];

  union {
    __IOM uint32_t MI2CCFG;                     /*!< (@ 0x000002C0) Controls the configuration of the I2C bus master.          */

    struct {
      __IOM uint32_t ADDRSZ     : 1;            /*!< [0..0] Sets the I2C master device address size to either 7b
                                                     (0) or 10b (1).                                                           */
      __IOM uint32_t I2CLSB     : 1;            /*!< [1..1] Direction of data transmit and receive, MSB(0) or LSB(1)
                                                     first. Default per I2C specification is MSB first. This
                                                     applies to both read and write data, and read data will
                                                     be bit                                                                    */
      __IOM uint32_t ARBEN      : 1;            /*!< [2..2] Enables multi-master arbitration for the I2C master.
                                                     If the bus is known to have only a single master, this
                                                     function can be disabled to save clock cycles on I2C transactions         */
            uint32_t            : 1;
      __IOM uint32_t SDADLY     : 2;            /*!< [5..4] Delay to enable on the SDA output. Values are 0x0-0x3.             */
      __IOM uint32_t MI2CRST    : 1;            /*!< [6..6] Not used. To reset the module, toggle the SMOD_EN for
                                                     the module                                                                */
            uint32_t            : 1;
      __IOM uint32_t SCLENDLY   : 4;            /*!< [11..8] Number of IOCLK cycles to delay the rising edge of the
                                                     SCL output en (clock will go low on this edge). Used to
                                                     allow clock shaping.                                                      */
      __IOM uint32_t SDAENDLY   : 4;            /*!< [15..12] Number of IOCLK cycles to delay the SDA output en (all
                                                     transitions affected). Used to delay data relative to clock               */
      __IOM uint32_t SMPCNT     : 8;            /*!< [23..16] Number of Base clk cycles to wait before sampling the
                                                     SCL clock to determine if a clock stretch event has occured               */
      __IOM uint32_t STRDIS     : 1;            /*!< [24..24] Disable detection of clock stretch events smaller than
                                                     1 cycle                                                                   */
            uint32_t            : 7;
    } MI2CCFG_b;
  } ;

  union {
    __IOM uint32_t DEVCFG;                      /*!< (@ 0x000002C4) Contains the I2C device address.                           */

    struct {
      __IOM uint32_t DEVADDR    : 10;           /*!< [9..0] I2C address of the device that the Master will use to
                                                     target for read/write operations. This can be either a
                                                     7b or 10b address.                                                        */
            uint32_t            : 22;
    } DEVCFG_b;
  } ;
  __IM  uint32_t  RESERVED4[48];

  union {
    __IOM uint32_t IOMDBG;                      /*!< (@ 0x00000388) Debug control                                              */

    struct {
      __IOM uint32_t DBGEN      : 1;            /*!< [0..0] Debug Enable. Setting bit will enable the update of data
                                                     within this register, otherwise it is clock gated for power
                                                     savings                                                                   */
      __IOM uint32_t IOCLKON    : 1;            /*!< [1..1] IOCLK debug clock control. Enable IO_CLK to be active
                                                     when this bit is '1'. Otherwise, the clock is controlled
                                                     with gating from the logic as needed.                                     */
      __IOM uint32_t APBCLKON   : 1;            /*!< [2..2] APBCLK debug clock control. Enable APB_CLK to be active
                                                     when this bit is '1'. Otherwise, the clock is controlled
                                                     with gating from the logic as needed.                                     */
      __IOM uint32_t DBGDATA    : 29;           /*!< [31..3] Debug control for various options. DBGDATA[1:0] is used
                                                     to select between different debug data available in the
                                                     DBG0 and DBG1 registers.                                                  */
    } IOMDBG_b;
  } ;
} IOM0_Type;                                    /*!< Size = 908 (0x38c)                                                        */



/* =========================================================================================================================== */
/* ================                                          IOSLAVE                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief I2C/SPI Slave (IOSLAVE)
  */

typedef struct {                                /*!< (@ 0x40034000) IOSLAVE Structure                                          */
  __IM  uint32_t  RESERVED[64];

  union {
    __IOM uint32_t FIFOPTR;                     /*!< (@ 0x00000100) Current FIFO Pointer                                       */

    struct {
      __IOM uint32_t FIFOPTR    : 8;            /*!< [7..0] Current FIFO pointer.                                              */
      __IOM uint32_t FIFOSIZ    : 8;            /*!< [15..8] The number of bytes currently in the hardware FIFO.               */
            uint32_t            : 16;
    } FIFOPTR_b;
  } ;

  union {
    __IOM uint32_t FIFOCFG;                     /*!< (@ 0x00000104) FIFO Configuration                                         */

    struct {
      __IOM uint32_t FIFOBASE   : 5;            /*!< [4..0] These bits hold the base address of the I/O FIFO in 8
                                                     byte segments. The IO Slave FIFO is situated in LRAM at
                                                     (FIFOBASE*8) to (FIFOMAX*8-1).                                            */
            uint32_t            : 3;
      __IOM uint32_t FIFOMAX    : 6;            /*!< [13..8] These bits hold the maximum FIFO address in 8 byte segments.
                                                     It is also the beginning of the RAM area of the LRAM. Note
                                                     that no RAM area is configured if FIFOMAX is set to 0x1F.                 */
            uint32_t            : 10;
      __IOM uint32_t ROBASE     : 6;            /*!< [29..24] Defines the read-only area. The IO Slave read-only
                                                     area is situated in LRAM at (ROBASE*8) to (FIFOBASE*8-1)                  */
            uint32_t            : 2;
    } FIFOCFG_b;
  } ;

  union {
    __IOM uint32_t FIFOTHR;                     /*!< (@ 0x00000108) FIFO Threshold Configuration                               */

    struct {
      __IOM uint32_t FIFOTHR    : 8;            /*!< [7..0] FIFO size interrupt threshold.                                     */
            uint32_t            : 24;
    } FIFOTHR_b;
  } ;

  union {
    __IOM uint32_t FUPD;                        /*!< (@ 0x0000010C) FIFO Update Status                                         */

    struct {
      __IOM uint32_t FIFOUPD    : 1;            /*!< [0..0] This bit indicates that a FIFO update is underway.                 */
      __IOM uint32_t IOREAD     : 1;            /*!< [1..1] This bitfield indicates an IO read is active.                      */
            uint32_t            : 30;
    } FUPD_b;
  } ;

  union {
    __IOM uint32_t FIFOCTR;                     /*!< (@ 0x00000110) Overall FIFO Counter                                       */

    struct {
      __IOM uint32_t FIFOCTR    : 10;           /*!< [9..0] Virtual FIFO byte count                                            */
            uint32_t            : 22;
    } FIFOCTR_b;
  } ;

  union {
    __IOM uint32_t FIFOINC;                     /*!< (@ 0x00000114) Overall FIFO Counter Increment                             */

    struct {
      __IOM uint32_t FIFOINC    : 10;           /*!< [9..0] Increment the Overall FIFO Counter by this value on a
                                                     write                                                                     */
            uint32_t            : 22;
    } FIFOINC_b;
  } ;

  union {
    __IOM uint32_t CFG;                         /*!< (@ 0x00000118) I/O Slave Configuration                                    */

    struct {
      __IOM uint32_t IFCSEL     : 1;            /*!< [0..0] This bit selects the I/O interface.                                */
      __IOM uint32_t SPOL       : 1;            /*!< [1..1] This bit selects SPI polarity.                                     */
      __IOM uint32_t LSB        : 1;            /*!< [2..2] This bit selects the transfer bit ordering.                        */
            uint32_t            : 1;
      __IOM uint32_t STARTRD    : 1;            /*!< [4..4] This bit holds the cycle to initiate an I/O RAM read.              */
            uint32_t            : 3;
      __IOM uint32_t I2CADDR    : 12;           /*!< [19..8] 7-bit or 10-bit I2C device address.                               */
      __IOM uint32_t WRAPPTR    : 1;            /*!< [20..20] Address pointer wrap mode enable.                                */
            uint32_t            : 10;
      __IOM uint32_t IFCEN      : 1;            /*!< [31..31] IOSLAVE interface enable.                                        */
    } CFG_b;
  } ;

  union {
    __IOM uint32_t PRENC;                       /*!< (@ 0x0000011C) I/O Slave Interrupt Priority Encode                        */

    struct {
      __IOM uint32_t PRENC      : 5;            /*!< [4..0] These bits hold the priority encode of the REGACC interrupts.      */
            uint32_t            : 27;
    } PRENC_b;
  } ;

  union {
    __IOM uint32_t IOINTCTL;                    /*!< (@ 0x00000120) I/O Interrupt Control                                      */

    struct {
      __IOM uint32_t IOINTEN    : 8;            /*!< [7..0] These read-only bits indicate whether the IOINT interrupts
                                                     are enabled.                                                              */
      __IOM uint32_t IOINT      : 8;            /*!< [15..8] These bits read the IOINT interrupts.                             */
      __IOM uint32_t IOINTCLR   : 1;            /*!< [16..16] This bit clears all of the IOINT interrupts when written
                                                     with a 1.                                                                 */
            uint32_t            : 7;
      __IOM uint32_t IOINTSET   : 8;            /*!< [31..24] These bits set the IOINT interrupts when written with
                                                     a 1.                                                                      */
    } IOINTCTL_b;
  } ;

  union {
    __IOM uint32_t GENADD;                      /*!< (@ 0x00000124) General Address Data                                       */

    struct {
      __IOM uint32_t GADATA     : 8;            /*!< [7..0] The data supplied on the last General Address reference.           */
            uint32_t            : 24;
    } GENADD_b;
  } ;

  union {
    __IOM uint32_t ADDPTR;                      /*!< (@ 0x00000128) Address pointer                                            */

    struct {
      __IOM uint32_t ADDPTR     : 8;            /*!< [7..0] The current value in the Address pointer.                          */
            uint32_t            : 24;
    } ADDPTR_b;
  } ;
  __IM  uint32_t  RESERVED1[53];

  union {
    __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
      __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
      __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
      __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
      __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
      __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
      __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
      __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
      __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
      __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
            uint32_t            : 22;
    } INTEN_b;
  } ;

  union {
    __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
      __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
      __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
      __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
      __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
      __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
      __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
      __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
      __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
      __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
            uint32_t            : 22;
    } INTSTAT_b;
  } ;

  union {
    __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
      __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
      __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
      __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
      __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
      __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
      __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
      __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
      __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
      __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
            uint32_t            : 22;
    } INTCLR_b;
  } ;

  union {
    __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
      __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
      __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
      __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
      __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
      __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
      __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
      __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
      __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
      __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
            uint32_t            : 22;
    } INTSET_b;
  } ;

  union {
    __IOM uint32_t REGACCINTEN;                 /*!< (@ 0x00000210) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
    } REGACCINTEN_b;
  } ;

  union {
    __IOM uint32_t REGACCINTSTAT;               /*!< (@ 0x00000214) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
    } REGACCINTSTAT_b;
  } ;

  union {
    __IOM uint32_t REGACCINTCLR;                /*!< (@ 0x00000218) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
    } REGACCINTCLR_b;
  } ;

  union {
    __IOM uint32_t REGACCINTSET;                /*!< (@ 0x0000021C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
    } REGACCINTSET_b;
  } ;
} IOSLAVE_Type;                                 /*!< Size = 544 (0x220)                                                        */



/* =========================================================================================================================== */
/* ================                                          MCUCTRL                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief MCU Miscellaneous Control Logic (MCUCTRL)
  */

typedef struct {                                /*!< (@ 0x40020000) MCUCTRL Structure                                          */

  union {
    __IOM uint32_t CHIPPN;                      /*!< (@ 0x00000000) Chip Information                                           */

    struct {
            uint32_t            : 1;
      __IOM uint32_t TEMP       : 2;            /*!< [2..1] Temperature.                                                       */
      __IOM uint32_t PINS       : 3;            /*!< [5..3] Number of pins for this package.                                   */
      __IOM uint32_t PKG        : 2;            /*!< [7..6] Package type.                                                      */
      __IOM uint32_t REVMIN     : 4;            /*!< [11..8] Minor revision.                                                   */
      __IOM uint32_t REVMAJ     : 4;            /*!< [15..12] Major revision.                                                  */
      __IOM uint32_t SRAMSIZE   : 4;            /*!< [19..16] SRAM size.                                                       */
      __IOM uint32_t MRAMSIZE   : 4;            /*!< [23..20] MRAM size.                                                       */
      __IOM uint32_t PN         : 8;            /*!< [31..24] Apollo family device type.                                       */
    } CHIPPN_b;
  } ;

  union {
    __IOM uint32_t CHIPID0;                     /*!< (@ 0x00000004) Unique Chip ID 0                                           */

    struct {
      __IOM uint32_t CHIPID0    : 32;           /*!< [31..0] Unique chip ID 0.                                                 */
    } CHIPID0_b;
  } ;

  union {
    __IOM uint32_t CHIPID1;                     /*!< (@ 0x00000008) Unique Chip ID 1                                           */

    struct {
      __IOM uint32_t CHIPID1    : 32;           /*!< [31..0] Unique chip ID 1.                                                 */
    } CHIPID1_b;
  } ;

  union {
    __IOM uint32_t CHIPREV;                     /*!< (@ 0x0000000C) Chip Revision                                              */

    struct {
      __IOM uint32_t REVMIN     : 4;            /*!< [3..0] Minor Revision ID.                                                 */
      __IOM uint32_t REVMAJ     : 4;            /*!< [7..4] Major Revision ID.                                                 */
      __IOM uint32_t SIPART     : 12;           /*!< [19..8] Silicon Part ID                                                   */
            uint32_t            : 12;
    } CHIPREV_b;
  } ;

  union {
    __IOM uint32_t VENDORID;                    /*!< (@ 0x00000010) Unique Vendor ID                                           */

    struct {
      __IOM uint32_t VENDORID   : 32;           /*!< [31..0] Unique Vendor ID                                                  */
    } VENDORID_b;
  } ;

  union {
    __IOM uint32_t SKU;                         /*!< (@ 0x00000014) Unique Chip SKU                                            */

    struct {
      __IOM uint32_t SKUSRAMSIZE : 2;           /*!< [1..0] SRAM SKU dictates the available memory for MCU. All of
                                                     the MCU TCM (384KB) and System SRAM (2MB) available by
                                                     default. Memory SU disabled                                               */
      __IOM uint32_t SKUMRAMSIZE : 2;           /*!< [3..2] MRAM size SKU. All of 2MB Available by default. Memory
                                                     SU disabled                                                               */
      __IOM uint32_t SKUDSP     : 2;            /*!< [5..4] DSP availability SKU setting. 384K available by default.
                                                     Memory SU disabled                                                        */
      __IOM uint32_t SKUTURBOSPOT : 1;          /*!< [6..6] High performance mode for MCU and DSPs.                            */
      __IOM uint32_t SKUMIPIDSI : 1;            /*!< [7..7] MIPI DSI available                                                 */
      __IOM uint32_t SKUGFX     : 1;            /*!< [8..8] GFX available                                                      */
      __IOM uint32_t SKUUSB     : 1;            /*!< [9..9] USB available                                                      */
      __IOM uint32_t SKUSECURESPOT : 1;         /*!< [10..10] Secure boot feature                                              */
            uint32_t            : 21;
    } SKU_b;
  } ;
  __IM  uint32_t  RESERVED[2];

  union {
    __IOM uint32_t DEBUGGER;                    /*!< (@ 0x00000020) Debugger Control                                           */

    struct {
      __IOM uint32_t LOCKOUT    : 32;           /*!< [31..0] Lockout of debugger (SWD).                                        */
    } DEBUGGER_b;
  } ;
  __IM  uint32_t  RESERVED1;

  union {
    __IOM uint32_t ACRG;                        /*!< (@ 0x00000028) Active Current Reference Generator Control                 */

    struct {
      __IOM uint32_t ACRGSWE    : 1;            /*!< [0..0] Software enablement for ACRG register. A value of 1 will
                                                     allow writes to the register                                              */
      __IOM uint32_t ACRGPWD    : 1;            /*!< [1..1] Power down the ACRG.                                               */
      __IOM uint32_t ACRGIBIASSEL : 1;          /*!< [2..2] Set the ACRG ibias. Note: the SWE mux select in PWRSEQ2SWE
                                                     must be set for this to take effect. The inversion of this
                                                     register is driven to analog.                                             */
      __IOM uint32_t ACRGTRIM   : 5;            /*!< [7..3] ACRG Trim value                                                    */
            uint32_t            : 24;
    } ACRG_b;
  } ;
  __IM  uint32_t  RESERVED2[6];

  union {
    __IOM uint32_t VREFGEN2;                    /*!< (@ 0x00000044) Voltage Reference Generator 2 Control                      */

    struct {
      __IOM uint32_t TVRGTEMPCOTRIM : 5;        /*!< [4..0] Calibrated Voltage Reference Generator tc trim (bottom
                                                     transistor)                                                               */
      __IOM uint32_t TVRGPWD    : 1;            /*!< [5..5] Power Down, Calibrated Voltage Reference Generator.                */
      __IOM uint32_t TVRGCURRENTTRIM : 1;       /*!< [6..6] Calibrated voltage reference current trim.                         */
      __IOM uint32_t TVRGVREFTRIM : 7;          /*!< [13..7] Calibrated voltage reference 580m trim                            */
      __IOM uint32_t TVRG2TEMPCOTRIM : 5;       /*!< [18..14] Calibrated Voltage Reference Generator tc trim (bottom
                                                     transistor)                                                               */
      __IOM uint32_t TVRG2PWD   : 1;            /*!< [19..19] Power Down, Calibrated Voltage Reference Generator.              */
      __IOM uint32_t TVRG2CURRENTTRIM : 1;      /*!< [20..20] Calibrated voltage reference current trim.                       */
      __IOM uint32_t TVRG2VREFTRIM : 7;         /*!< [27..21] Calibrated voltage reference 580m trim                           */
      __IOM uint32_t TVRGSELVREF : 1;           /*!< [28..28] TVRG SEL VREF                                                    */
      __IOM uint32_t TVRG2SELVREF : 1;          /*!< [29..29] TVRG2 SEL VREF                                                   */
            uint32_t            : 2;
    } VREFGEN2_b;
  } ;
  __IM  uint32_t  RESERVED3[6];

  union {
    __IOM uint32_t VRCTRL;                      /*!< (@ 0x00000060) Overrides for Voltage Regulators Controls                  */

    struct {
      __IOM uint32_t CORELDOOVER : 1;           /*!< [0..0] Override control for CORE LDO signals                              */
      __IOM uint32_t CORELDOPDNB : 1;           /*!< [1..1] CORE LDO PDNB control. Override for PWRCTRL going to
                                                     analog when CORELDOOVER = 1                                               */
      __IOM uint32_t CORELDOACTIVEEARLY : 1;    /*!< [2..2] CORE LDO EARLY ACTIVE control. Override for PWRCTRL going
                                                     to analog when CORELDOOVER = 1                                            */
      __IOM uint32_t CORELDOACTIVE : 1;         /*!< [3..3] CORE LDO ACTIVE control. Override for PWRCTRL going to
                                                     analog when CORELDOOVER = 1                                               */
      __IOM uint32_t CORELDOCOLDSTARTEN : 1;    /*!< [4..4] CORE LDO COLDSTART EN control. This is a shadow backed
                                                     register and no need to set CORELDOOVER.                                  */
      __IOM uint32_t MEMLDOOVER : 1;            /*!< [5..5] Override control for MEM LDO signals                               */
      __IOM uint32_t MEMLDOPDNB : 1;            /*!< [6..6] MEM LDO PDNB control. Override signal for PWRCTRL going
                                                     to analog when MEMLDOOVER = 1                                             */
      __IOM uint32_t MEMLDOACTIVEEARLY : 1;     /*!< [7..7] MEM LDO EARLY ACTIVE control. Override for PWRCTRL going
                                                     to analog when MEMLDOOVER = 1                                             */
      __IOM uint32_t MEMLDOACTIVE : 1;          /*!< [8..8] MEM LDO ACTIVE control. Override for PWRCTRL going to
                                                     analog when MEMLDOOVER = 1                                                */
      __IOM uint32_t MEMLDOCOLDSTARTEN : 1;     /*!< [9..9] MEM LDO COLDSTART EN control. This is a shadow backed
                                                     register and no need to set MEMLDOOVER.                                   */
      __IOM uint32_t MEMLPLDOOVER : 1;          /*!< [10..10] Override control for MEM LP LDO signals                          */
      __IOM uint32_t MEMLPLDOPDNB : 1;          /*!< [11..11] MEM LP LDO PDNB control. Override for PWRCTRL going
                                                     to analog when MEMLPLDOOVER = 1                                           */
      __IOM uint32_t MEMLPLDOACTIVE : 1;        /*!< [12..12] MEM LP LDO ACTVIVE control. Override for PWRCTRL going
                                                     to analog when MEMLPLDOOVER = 1                                           */
      __IOM uint32_t ANALDOOVER : 1;            /*!< [13..13] Override control for ANALDO signals                              */
      __IOM uint32_t ANALDOPDNB : 1;            /*!< [14..14] ANALDO PDNB control. Override for PWRCTRL going to
                                                     analog when ANALDOOVER = 1                                                */
      __IOM uint32_t ANALDOACTIVE : 1;          /*!< [15..15] ANALDO LDO ACTIVE control. Override for PWRCTRL going
                                                     to analog when ANALDOOVER = 1                                             */
      __IOM uint32_t SIMOBUCKOVER : 1;          /*!< [16..16] Override control for SIMO BUCK signals                           */
      __IOM uint32_t SIMOBUCKPDNB : 1;          /*!< [17..17] SIMO BUCK PDNB control. Override for PWRCTRL going
                                                     to analog when SIMOBUCKOVER = 1                                           */
      __IOM uint32_t SIMOBUCKRSTB : 1;          /*!< [18..18] SIMO BUCK RSTB control. Override for PWRCTRL going
                                                     to analog when SIMOBUCKOVER = 1                                           */
      __IOM uint32_t SIMOBUCKACTIVE : 1;        /*!< [19..19] SIMO BUCK ACTIVE control. Override for PWRCTRL going
                                                     to analog when SIMOBUCKOVER = 1                                           */
            uint32_t            : 12;
    } VRCTRL_b;
  } ;
  __IM  uint32_t  RESERVED4[7];

  union {
    __IOM uint32_t LDOREG1;                     /*!< (@ 0x00000080) CORELDO trims Reg                                          */

    struct {
      __IOM uint32_t CORELDOACTIVETRIM : 10;    /*!< [9..0] CORE LDO active trim                                               */
      __IOM uint32_t CORELDOTEMPCOTRIM : 4;     /*!< [13..10] CORE LDO TEMPCO trim                                             */
      __IOM uint32_t CORELDOLPTRIM : 6;         /*!< [19..14] CORE LDO Low Power Trim                                          */
      __IOM uint32_t CORELDOIBIASTRIM : 1;      /*!< [20..20] CORE LDO IBIAS Trim                                              */
      __IOM uint32_t CORELDOIBIASSEL : 1;       /*!< [21..21] Core LDO IBIAS sel. Note: the SWE mux select in PWRSEQ2SWE
                                                     must be set for this to take effect.                                      */
            uint32_t            : 10;
    } LDOREG1_b;
  } ;
  __IM  uint32_t  RESERVED5;

  union {
    __IOM uint32_t LDOREG2;                     /*!< (@ 0x00000088) MEMLDO and MEMLPLDO Trims                                  */

    struct {
      __IOM uint32_t MEMLDOACTIVETRIM : 6;      /*!< [5..0] MEM LDO active trim                                                */
      __IOM uint32_t MEMLDOLPTRIM : 6;          /*!< [11..6] MEM LDO LP trim                                                   */
      __IOM uint32_t MEMLDOLPALTTRIM : 6;       /*!< [17..12] MEM LDO TRIM LP ALT SET                                          */
      __IOM uint32_t MEMLPLDOTRIM : 6;          /*!< [23..18] MEM LPLDO TRIM                                                   */
      __IOM uint32_t MEMLPLDOIBIASTRIM : 1;     /*!< [24..24] Mem LPLDO IBIAS trim                                             */
      __IOM uint32_t MEMLDOIBIASSEL : 1;        /*!< [25..25] Mem LDO IBIAS sel. Note: the SWE mux select in PWRSEQ2SWE
                                                     must be set for this to take effect.                                      */
      __IOM uint32_t TRIMANALDO : 4;            /*!< [29..26] Analog LDO Trim.                                                 */
            uint32_t            : 2;
    } LDOREG2_b;
  } ;
  __IM  uint32_t  RESERVED6[14];

  union {
    __IOM uint32_t HFRC2;                       /*!< (@ 0x000000C4) HFRC2 Control                                              */

    struct {
            uint32_t            : 11;
      __IOM uint32_t HF2TUNE    : 11;           /*!< [21..11] Default HFRC2 frequency tune value                               */
            uint32_t            : 10;
    } HFRC2_b;
  } ;
  __IM  uint32_t  RESERVED7[6];

  union {
    __IOM uint32_t LFRC;                        /*!< (@ 0x000000E0) LFRC Control                                               */

    struct {
      __IOM uint32_t LFRCSWE    : 1;            /*!< [0..0] LFRC Software Override Enable.                                     */
      __IOM uint32_t TRIMTUNELFRC : 5;          /*!< [5..1] LFRC Frequency Tune trim bits                                      */
      __IOM uint32_t PWDLFRC    : 1;            /*!< [6..6] Power Down LFRC.                                                   */
      __IOM uint32_t RESETLFRC  : 1;            /*!< [7..7] LFRC Reset.                                                        */
      __IOM uint32_t LFRCITAILTRIM : 2;         /*!< [9..8] LFRC ITAIL trim                                                    */
      __IOM uint32_t LFRCSIMOCLKDIV : 3;        /*!< [12..10] SIMOBUCK LP mode clock divider                                   */
            uint32_t            : 19;
    } LFRC_b;
  } ;
  __IM  uint32_t  RESERVED8[7];

  union {
    __IOM uint32_t BODCTRL;                     /*!< (@ 0x00000100) BOD control                                                */

    struct {
      __IOM uint32_t BODLPWD    : 1;            /*!< [0..0] BODL Power Down.                                                   */
      __IOM uint32_t BODHPWD    : 1;            /*!< [1..1] BODH Power Down.                                                   */
      __IOM uint32_t BODCPWD    : 1;            /*!< [2..2] BODC Power Down.                                                   */
      __IOM uint32_t BODFPWD    : 1;            /*!< [3..3] BODF Power Down.                                                   */
      __IOM uint32_t BODSPWD    : 1;            /*!< [4..4] BODS Power Down.                                                   */
      __IOM uint32_t BODCLVPWD  : 1;            /*!< [5..5] BODC_LV Power Down.                                                */
      __IOM uint32_t BODLVREFSEL : 1;           /*!< [6..6] BODL External Reference Select. Note: the SWE mux select
                                                     in PWRSEQ2SWE must be set for this to take effect.                        */
      __IOM uint32_t BODHVREFSEL : 1;           /*!< [7..7] BODH External Reference Select. Note: the SWE mux select
                                                     in PWRSEQ2SWE must be set for this to take effect.                        */
            uint32_t            : 24;
    } BODCTRL_b;
  } ;

  union {
    __IOM uint32_t ADCPWRDLY;                   /*!< (@ 0x00000104) ADC Power Up Delay Control                                 */

    struct {
      __IOM uint32_t ADCPWR0    : 8;            /*!< [7..0] Additional delay time for ADC Reference Buffer settling
                                                     time in 64x ADC clock increments. Delay = 64*ADCPWR0*ADC_CLK.             */
      __IOM uint32_t ADCPWR1    : 8;            /*!< [15..8] Delay time for ADC Reference Buffer settling time in
                                                     64x ADC clock increments. Delay = 64*ADCPWR1*ADC_CLK                      */
            uint32_t            : 16;
    } ADCPWRDLY_b;
  } ;

  union {
    __IOM uint32_t ADCPWRCTRL;                  /*!< (@ 0x00000108) ADC Power Control                                          */

    struct {
      __IOM uint32_t ADCPWRCTRLSWE : 1;         /*!< [0..0] ADC Power Control Software Override Enable                         */
      __IOM uint32_t ADCAPSEN   : 1;            /*!< [1..1] Enable the Global ADC Power Switch on when set to 1 if
                                                     the ADCPWRCTRLSWE bit is set.                                             */
      __IOM uint32_t ADCBPSEN   : 1;            /*!< [2..2] Enable the Analog, IO and SAR Digital logic Power Switch
                                                     on when set to 1 if the ADCPWRCTRLSWE bit is set.                         */
      __IOM uint32_t BGTPEN     : 1;            /*!< [3..3] Bandgap and Temperature Sensor Power Switch Enable                 */
      __IOM uint32_t BGTLPPEN   : 1;            /*!< [4..4] Bandgap and Temperature Sensor Power Switch Enable                 */
      __IOM uint32_t REFBUFPEN  : 1;            /*!< [5..5] Reference Buffer Power Switch Enable                               */
      __IOM uint32_t REFKEEPPEN : 1;            /*!< [6..6] Reference Buffer Keeper Power Switch Enable                        */
      __IOM uint32_t VDDADCSARISOLATE : 1;      /*!< [7..7] ISOLATE signal for Power Switched SAR ( when ADCBPSEN
                                                     is switched off )                                                         */
      __IOM uint32_t VDDADCDIGISOLATE : 1;      /*!< [8..8] ISOLATE signal for ADC Digital Contoller ( when ADCAPSEN
                                                     is switched off and if the ADCPWRCTRLSWE bit is set)                      */
      __IOM uint32_t VDDADCRESETN : 1;          /*!< [9..9] RESETN signal for Power Switched SAR and Digital Controller
                                                     (when global power switch is off and if the ADCPWRCTRLSWE
                                                     bit is set)                                                               */
            uint32_t            : 1;
      __IOM uint32_t ADCVBATDIVEN : 1;          /*!< [11..11] ADC VBAT DIV Power Enable ( if the ADCPWRCTRLSWE bit
                                                     is set )                                                                  */
      __IOM uint32_t ADCINBUFSEL : 2;           /*!< [13..12] ADC input buffer mux select                                      */
      __IOM uint32_t ADCINBUFEN : 1;            /*!< [14..14] ADC Input Buffer Power Enable ( if the ADCPWRCTRLSWE
                                                     bit is set )                                                              */
      __IOM uint32_t ADCRFBUFSLWEN : 1;         /*!< [15..15] ADC reference buffer slew enable                                 */
      __IOM uint32_t ADCKEEPOUTEN : 1;          /*!< [16..16] ADC reference keeper out en                                      */
            uint32_t            : 15;
    } ADCPWRCTRL_b;
  } ;

  union {
    __IOM uint32_t ADCCAL;                      /*!< (@ 0x0000010C) ADC Calibration Control                                    */

    struct {
      __IOM uint32_t CALONPWRUP : 1;            /*!< [0..0] Run ADC Calibration on initial power up sequence                   */
      __IOM uint32_t ADCCALIBRATED : 1;         /*!< [1..1] Status for ADC Calibration                                         */
            uint32_t            : 30;
    } ADCCAL_b;
  } ;

  union {
    __IOM uint32_t ADCBATTLOAD;                 /*!< (@ 0x00000110) ADC Battery Load Enable                                    */

    struct {
      __IOM uint32_t BATTLOAD   : 1;            /*!< [0..0] Enable the ADC battery load resistor                               */
            uint32_t            : 31;
    } ADCBATTLOAD_b;
  } ;
  __IM  uint32_t  RESERVED9[3];

  union {
    __IOM uint32_t XTALCTRL;                    /*!< (@ 0x00000120) XTAL Oscillator Control                                    */

    struct {
      __IOM uint32_t XTALSWE    : 1;            /*!< [0..0] XTAL Software Override Enable.                                     */
      __IOM uint32_t XTALCOREDISFB : 1;         /*!< [1..1] XTAL Oscillator Disable Feedback.                                  */
      __IOM uint32_t XTALCOMPBYPASS : 1;        /*!< [2..2] XTAL Oscillator Bypass Comparator.                                 */
      __IOM uint32_t XTALPDNB   : 1;            /*!< [3..3] XTAL Oscillator Power Down Core.                                   */
      __IOM uint32_t XTALCOMPPDNB : 1;          /*!< [4..4] XTAL Oscillator Power Down Comparator.                             */
      __IOM uint32_t XTALIBUFTRIM : 2;          /*!< [6..5] XTAL IBUFF trim                                                    */
      __IOM uint32_t XTALICOMPTRIM : 2;         /*!< [8..7] XTAL ICOMP trim                                                    */
            uint32_t            : 23;
    } XTALCTRL_b;
  } ;

  union {
    __IOM uint32_t XTALGENCTRL;                 /*!< (@ 0x00000124) XTAL Oscillator General Control                            */

    struct {
      __IOM uint32_t ACWARMUP   : 2;            /*!< [1..0] Auto-calibration delay control                                     */
      __IOM uint32_t XTALBIASTRIM : 6;          /*!< [7..2] XTAL BIAS trim                                                     */
      __IOM uint32_t XTALKSBIASTRIM : 6;        /*!< [13..8] XTAL IBIAS Kick start trim. This trim value is used
                                                     during the startup process to enable a faster lock.                       */
            uint32_t            : 18;
    } XTALGENCTRL_b;
  } ;

  union {
    __IOM uint32_t XTALHSTRIMS;                 /*!< (@ 0x00000128) XTALHS Trims                                               */

    struct {
      __IOM uint32_t XTALHSCAP2TRIM : 6;        /*!< [5..0] xtalhs_cap2_trim                                                   */
      __IOM uint32_t XTALHSCAPTRIM : 4;         /*!< [9..6] xtalhs_cap_trim                                                    */
      __IOM uint32_t XTALHSDRIVETRIM : 2;       /*!< [11..10] xtalhs_drive_trim                                                */
      __IOM uint32_t XTALHSDRIVERSTRENGTH : 3;  /*!< [14..12] xtalhs_driver_strength                                           */
      __IOM uint32_t XTALHSIBIASCOMP2TRIM : 2;  /*!< [16..15] xtalhs_ibias_comp2_trim                                          */
      __IOM uint32_t XTALHSIBIASCOMPTRIM : 4;   /*!< [20..17] xtalhs_ibias_comp_trim                                           */
      __IOM uint32_t XTALHSIBIASTRIM : 7;       /*!< [27..21] xtalhs_ibias_trim                                                */
      __IOM uint32_t XTALHSRSTRIM : 1;          /*!< [28..28] xtalhs_rs_trim                                                   */
      __IOM uint32_t XTALHSSPARE : 1;           /*!< [29..29] xtalhs_spare                                                     */
            uint32_t            : 2;
    } XTALHSTRIMS_b;
  } ;

  union {
    __IOM uint32_t XTALHSCTRL;                  /*!< (@ 0x0000012C) XTALHS Control                                             */

    struct {
      __IOM uint32_t XTALHSPDNB : 1;            /*!< [0..0] xtalhs_pdnb                                                        */
      __IOM uint32_t XTALHSCOMPPDNB : 1;        /*!< [1..1] xtalhs_comp_pdnb                                                   */
      __IOM uint32_t XTALHSCOMPSEL : 1;         /*!< [2..2] xtalhs_comp_sel                                                    */
      __IOM uint32_t XTALHSIBSTENABLE : 1;      /*!< [3..3] xtalhs_ibst_enable                                                 */
      __IOM uint32_t XTALHSINJECTIONENABLE : 1; /*!< [4..4] xtalhs_injection_enable                                            */
      __IOM uint32_t XTALHSPDNPNIMPROVE : 1;    /*!< [5..5] xtalhs_pdn_pn_improve                                              */
      __IOM uint32_t XTALHSSELRCOM : 1;         /*!< [6..6] xtalhs_sel_rcom                                                    */
      __IOM uint32_t XTALHSPADOUTEN : 1;        /*!< [7..7] xtalhs_padout_en                                                   */
      __IOM uint32_t XTALHSEXTERNALCLOCK : 1;   /*!< [8..8] xtalhs_external_clock                                              */
            uint32_t            : 23;
    } XTALHSCTRL_b;
  } ;
  __IM  uint32_t  RESERVED10[20];

  union {
    __IOM uint32_t MRAMPWRCTRL;                 /*!< (@ 0x00000180) MRAM Power Control                                         */

    struct {
      __IOM uint32_t MRAMLPREN  : 1;            /*!< [0..0] MRAM low power mode enable                                         */
      __IOM uint32_t MRAMSLPEN  : 1;            /*!< [1..1] MRAM sleep mode enable                                             */
      __IOM uint32_t MRAMPWRCTRL : 1;           /*!< [2..2] MRAM low power mode control. When set to 1, tmc_lpr and
                                                     tmc_slp are driven by the value of MRAMLPREN and MRAMSLPEN
                                                     of this register.                                                         */
            uint32_t            : 29;
    } MRAMPWRCTRL_b;
  } ;
  __IM  uint32_t  RESERVED11[10];

  union {
    __IOM uint32_t BODISABLE;                   /*!< (@ 0x000001AC) Brownout Disable                                           */

    struct {
      __IOM uint32_t BODLRDE    : 1;            /*!< [0..0] Disable Unregulated 1.8V Brown-out reset.                          */
      __IOM uint32_t BODCREN    : 1;            /*!< [1..1] Disable VDDC Brown Out reset.                                      */
      __IOM uint32_t BODFREN    : 1;            /*!< [2..2] Disable VDDF Brown Out reset.                                      */
      __IOM uint32_t BODSREN    : 1;            /*!< [3..3] Disable VDDS Brown Out reset.                                      */
      __IOM uint32_t BODCLVREN  : 1;            /*!< [4..4] Disable VDDC_LV Brown Out reset.                                   */
            uint32_t            : 27;
    } BODISABLE_b;
  } ;
  __IM  uint32_t  RESERVED12[2];

  union {
    __IOM uint32_t BOOTLOADER;                  /*!< (@ 0x000001B8) Bootloader and secure boot functions                       */

    struct {
      __IOM uint32_t BOOTLOADERLOW : 1;         /*!< [0..0] Determines whether the bootloader code is visible at
                                                     address 0x00000000 or not. Resets to 1, write 1 to clear.                 */
      __IOM uint32_t SBRLOCK    : 1;            /*!< [1..1] Secure boot ROM lock. Always resets to 1, write 1 to
                                                     clear. Enables system visibility to bootloader until set.                 */
      __IOM uint32_t PROTLOCK   : 1;            /*!< [2..2] This field controls access to OEM keybank and restricts
                                                     further application of NVM protections via the FLASHWPROTn
                                                     and FLASHRPROTn registers. On read, 0 indicates locked,
                                                     1 indicates unlocked. Write 1 to clear the field (assert
                                                     the lock). Default value of the hardware is 1 (unlocked),
                                                     but the default value is also affected by INFOC_SECURITY->PLONEXIT.
                                                     If PLONEXIT is set, PROTLOCK is asserted by SBL and the
                                                     OEM application will see the value as 0 (locked).                         */
      __IOM uint32_t SBLLOCK    : 1;            /*!< [3..3] Secure boot loader lock. Always resets to 1, write 1
                                                     to clear. Enables system visibility to bootloader until
                                                     set.                                                                      */
            uint32_t            : 22;
      __IOM uint32_t SECBOOTFEATURE : 2;        /*!< [27..26] Indicates whether the secure boot feature is enabled.            */
      __IOM uint32_t SECBOOT    : 2;            /*!< [29..28] Indicates whether the secure boot on cold reset is
                                                     enabled                                                                   */
      __IOM uint32_t SECBOOTONRST : 2;          /*!< [31..30] Indicates whether the secure boot on warm reset is
                                                     enabled                                                                   */
    } BOOTLOADER_b;
  } ;

  union {
    __IOM uint32_t SHADOWVALID;                 /*!< (@ 0x000001BC) Register to indicate whether the shadow registers
                                                                    have been successfully loaded from the Flash
                                                                    Information Space.                                         */

    struct {
      __IOM uint32_t VALID      : 1;            /*!< [0..0] Indicates whether the shadow registers contain valid
                                                     data from the Flash Information Space.                                    */
      __IOM uint32_t BLDSLEEP   : 1;            /*!< [1..1] Indicates whether the bootloader should sleep or deep
                                                     sleep if no image loaded.                                                 */
      __IOM uint32_t INFO0VALID : 1;            /*!< [2..2] Indicates whether info0 contains valid data                        */
            uint32_t            : 29;
    } SHADOWVALID_b;
  } ;

  union {
    __IOM uint32_t SCRATCH0;                    /*!< (@ 0x000001C0) Scratch register that is not reset by any reset            */

    struct {
      __IOM uint32_t SCRATCH0   : 32;           /*!< [31..0] Scratch register 0.                                               */
    } SCRATCH0_b;
  } ;

  union {
    __IOM uint32_t SCRATCH1;                    /*!< (@ 0x000001C4) Scratch register that is not reset by any reset            */

    struct {
      __IOM uint32_t SCRATCH1   : 32;           /*!< [31..0] Scratch register 1.                                               */
    } SCRATCH1_b;
  } ;
  __IM  uint32_t  RESERVED13[14];

  union {
    __IOM uint32_t DBGR1;                       /*!< (@ 0x00000200) Read-only debug 1                                          */

    struct {
      __IOM uint32_t ONETO8     : 32;           /*!< [31..0] Read-only register for communication validation                   */
    } DBGR1_b;
  } ;

  union {
    __IOM uint32_t DBGR2;                       /*!< (@ 0x00000204) Read-only debug 2                                          */

    struct {
      __IOM uint32_t COOLCODE   : 32;           /*!< [31..0] Read-only register for communication validation                   */
    } DBGR2_b;
  } ;
  __IM  uint32_t  RESERVED14[6];

  union {
    __IOM uint32_t PMUENABLE;                   /*!< (@ 0x00000220) Control bit to enable/disable the PMU                      */

    struct {
      __IOM uint32_t ENABLE     : 1;            /*!< [0..0] PMU Enable Control bit. When set, the MCU's PMU will
                                                     place the MCU into the lowest power consuming Deep Sleep
                                                     mode upon execution of a WFI instruction (dependent on
                                                     the setting of the SLEEPDEEP bit in the ARM SCR register).
                                                     When cleared, regardless of the requested sleep mode, the
                                                     PMU will not enter the lowest power Deep Sleep mode, instead
                                                     entering the Sleep mode.                                                  */
            uint32_t            : 31;
    } PMUENABLE_b;
  } ;
  __IM  uint32_t  RESERVED15[11];

  union {
    __IOM uint32_t DBGCTRL;                     /*!< (@ 0x00000250) Debug subsystem Control. Determines the debug
                                                                    components enable and clk frequency.                       */

    struct {
      __IOM uint32_t CM4TPIUENABLE : 1;         /*!< [0..0] TPIU Enable field. When set, the ARM M4 TPIU is enabled
                                                     and data can be streamed out trace data from ARM ITM and
                                                     ETM modules through either SWO or TRACEDATA ports                         */
      __IOM uint32_t CM4CLKSEL  : 3;            /*!< [3..1] This field selects the frequency of the ARM M4 TPIU port.          */
            uint32_t            : 4;
      __IOM uint32_t DBGETBENABLE : 1;          /*!< [8..8] Debug subsystem ETB enable to store the trace data.                */
      __IOM uint32_t DBGETMTRACEEN : 1;         /*!< [9..9] Debug subsystem ETM trace enable                                   */
      __IOM uint32_t DBGDSP0TRACEEN : 1;        /*!< [10..10] Debug subsystem DSP0 trace enable                                */
      __IOM uint32_t DBGDSP1TRACEEN : 1;        /*!< [11..11] Debug subsystem DSP1 trace enable                                */
      __IOM uint32_t DBGTSCLKSEL : 3;           /*!< [14..12] This field selects the frequency of the ARM M4 dbg
                                                     ts port.                                                                  */
            uint32_t            : 1;
      __IOM uint32_t DBGDSP0OCDHALTONRST : 1;   /*!< [16..16] Debug subsystem DSP0 OCD Halt on Reset                           */
      __IOM uint32_t DBGDSP1OCDHALTONRST : 1;   /*!< [17..17] Debug subsystem DSP1 OCD Halt on Reset                           */
            uint32_t            : 14;
    } DBGCTRL_b;
  } ;
  __IM  uint32_t  RESERVED16[4];

  union {
    __IOM uint32_t OTAPOINTER;                  /*!< (@ 0x00000264) OTA (Over the Air) Update Pointer/Status. Reset
                                                                    only by POA                                                */

    struct {
      __IOM uint32_t OTAVALID   : 1;            /*!< [0..0] Indicates that an OTA update is valid                              */
      __IOM uint32_t OTASBLUPDATE : 1;          /*!< [1..1] Indicates that the sbl_init has been updated                       */
      __IOM uint32_t OTAPOINTER : 30;           /*!< [31..2] Flash page pointer with updated OTA image                         */
    } OTAPOINTER_b;
  } ;
  __IM  uint32_t  RESERVED17[6];

  union {
    __IOM uint32_t APBDMACTRL;                  /*!< (@ 0x00000280) DMA Control Register. Determines misc settings
                                                                    for DMA operation                                          */

    struct {
      __IOM uint32_t DMAENABLE  : 1;            /*!< [0..0] Enable the DMA controller. When disabled, DMA requests
                                                     will be ignored by the controller                                         */
      __IOM uint32_t DECODEABORT : 1;           /*!< [1..1] APB Decode Abort. When set, the APB bridge will issue
                                                     a data abort (bus fault) on transactions to peripherals
                                                     that are powered down. When set to 0, writes are quietly
                                                     discarded and reads return 0.                                             */
            uint32_t            : 6;
      __IOM uint32_t HYSTERESIS : 8;            /*!< [15..8] This field determines how long the DMA engine of apb/disp/gfx
                                                     will remain active during deep sleep before shutting down
                                                     and returning the system to full deep sleep. Values are
                                                     based on a 94KHz clock and are roughly 10us increments
                                                     for a range of ~10us to 2.55ms                                            */
            uint32_t            : 16;
    } APBDMACTRL_b;
  } ;
  __IM  uint32_t  RESERVED18[45];

  union {
    __IOM uint32_t KEXTCLKSEL;                  /*!< (@ 0x00000338) Locks the state of the EXTCLKSEL register from
                                                                    writes. This is done to prevent errant writes
                                                                    to the register, as this could cause the
                                                                    chip to halt. Write a value of 0x53 to unlock
                                                                    write access to the EXTCLKSEL register.
                                                                    Once unlocked, the register will read back
                                                                    a 1 to undicate this is unlocked. Writing
                                                                    the register with any other value other
                                                                    than 0x53 will enable the lock.                            */

    struct {
      __IOM uint32_t KEXTCLKSEL : 32;           /*!< [31..0] Key register value.                                               */
    } KEXTCLKSEL_b;
  } ;

  union {
    __IOM uint32_t SIMOBUCK0;                   /*!< (@ 0x0000033C) This WRITE_ONLY register controls various buck
                                                                    parameters. It will read back as 0x00000000.               */

    struct {
      __IOM uint32_t VDDCRXCOMPEN : 1;          /*!< [0..0] Enable the VDDC rail.                                              */
      __IOM uint32_t VDDFRXCOMPEN : 1;          /*!< [1..1] Enable the VDDS rail.                                              */
      __IOM uint32_t VDDSRXCOMPEN : 1;          /*!< [2..2] Enable the VDDS rail.                                              */
      __IOM uint32_t VDDCLVRXCOMPEN : 1;        /*!< [3..3] Enable the VDDC LV rail.                                           */
      __IOM uint32_t TONTOFFNODEGLITCH : 1;     /*!< [4..4] Enable the ton and toff signals no deglitch output.                */
            uint32_t            : 27;
    } SIMOBUCK0_b;
  } ;

  union {
    __IOM uint32_t SIMOBUCK1;                   /*!< (@ 0x00000340) 1. Control the even division of 3 clocks: refresh,
                                                                    low power and TONCLK. 2. Control gap bewteen
                                                                    secondary switches. 3. Debug features: control
                                                                    the amount of time TONCLK is on, and the
                                                                    time before snubber asserts for each buck
                                                                    sequence. 4. Enable or disable the observation
                                                                    bus. 5. Select the buck sequence operation
                                                                    mode. 6. Control delay between primary Pmos
                                                                    and Nmos transitions.                                      */

    struct {
            uint32_t            : 6;
      __IOM uint32_t RXCLKACTTRIM : 5;          /*!< [10..6] This divides the 5 MHz refresh clock. Even divides are
                                                     supported only. This value represents the division amount
                                                     minus 1.                                                                  */
            uint32_t            : 11;
      __IOM uint32_t TONCLKTRIM : 4;            /*!< [25..22] This divides the 100 MHz ton clock. Even divides are
                                                     supported only. This value represents the division amount
                                                     minus 1.                                                                  */
            uint32_t            : 6;
    } SIMOBUCK1_b;
  } ;

  union {
    __IOM uint32_t SIMOBUCK2;                   /*!< (@ 0x00000344) SIMO Buck Muxed VDDC Active Sequence Trim Control          */

    struct {
            uint32_t            : 11;
      __IOM uint32_t VDDCACTHIGHTONTRIM : 4;    /*!< [14..11] VDDC active high ton trim control for Buck sequence.             */
            uint32_t            : 9;
      __IOM uint32_t VDDCACTLOWTONTRIM : 5;     /*!< [28..24] VDDC active high ton trim control for Buck sequence.             */
            uint32_t            : 3;
    } SIMOBUCK2_b;
  } ;

  union {
    __IOM uint32_t SIMOBUCK3;                   /*!< (@ 0x00000348) SIMO Buck Muxed VDDC low power Sequence Trim
                                                                    Control                                                    */

    struct {
            uint32_t            : 13;
      __IOM uint32_t VDDCLPHIGHTONTRIM : 4;     /*!< [16..13] VDDC LP high ton trim control for Buck sequence.                 */
            uint32_t            : 9;
      __IOM uint32_t VDDCLPLOWTONTRIM : 4;      /*!< [29..26] VDDC LP low ton trim control for Buck sequence.                  */
            uint32_t            : 2;
    } SIMOBUCK3_b;
  } ;
  __IM  uint32_t  RESERVED19[2];

  union {
    __IOM uint32_t SIMOBUCK6;                   /*!< (@ 0x00000354) SIMO Buck Muxed VDDF Active Sequence Trim Control          */

    struct {
            uint32_t            : 17;
      __IOM uint32_t VDDFACTHIGHTONTRIM : 4;    /*!< [20..17] VDDF active high ton trim control for Buck sequence.             */
            uint32_t            : 11;
    } SIMOBUCK6_b;
  } ;

  union {
    __IOM uint32_t SIMOBUCK7;                   /*!< (@ 0x00000358) SIMO Buck Muxed VDDF active Sequence Trim Control          */

    struct {
            uint32_t            : 8;
      __IOM uint32_t VDDFACTLOWTONTRIM : 5;     /*!< [12..8] VDDF active low ton trim control for Buck sequence.               */
            uint32_t            : 5;
      __IOM uint32_t ZXCOMPZXTRIM : 5;          /*!< [22..18] Zxcomp trim. Feedthrough to analog.                              */
            uint32_t            : 9;
    } SIMOBUCK7_b;
  } ;

  union {
    __IOM uint32_t SIMOBUCK8;                   /*!< (@ 0x0000035C) SIMO Buck Muxed VDDF Low Power Sequence Trim
                                                                    Control                                                    */

    struct {
            uint32_t            : 9;
      __IOM uint32_t VDDFLPHIGHTONTRIM : 4;     /*!< [12..9] VDDF low power high ton trim control for Buck sequence.           */
            uint32_t            : 9;
      __IOM uint32_t VDDFLPLOWTONTRIM : 4;      /*!< [25..22] VDDF low power low ton trim control for Buck sequence.           */
            uint32_t            : 6;
    } SIMOBUCK8_b;
  } ;

  union {
    __IOM uint32_t SIMOBUCK9;                   /*!< (@ 0x00000360) SIMO Buck Muxed VDDS Active Sequence Trim Control          */

    struct {
            uint32_t            : 17;
      __IOM uint32_t VDDSACTHIGHTONTRIM : 4;    /*!< [20..17] VDDS active high ton trim control for Buck sequence.             */
            uint32_t            : 1;
      __IOM uint32_t VDDSACTLOWTONTRIM : 5;     /*!< [26..22] VDDS active low ton trim control for Buck sequence.              */
            uint32_t            : 5;
    } SIMOBUCK9_b;
  } ;
  __IM  uint32_t  RESERVED20[2];

  union {
    __IOM uint32_t SIMOBUCK12;                  /*!< (@ 0x0000036C) SIMO Buck Compare, Brown out, Active, Low power
                                                                    Trim Control                                               */

    struct {
            uint32_t            : 20;
      __IOM uint32_t ACTTRIMVDDF : 6;           /*!< [25..20] Active VDDF trim.                                                */
      __IOM uint32_t LPTRIMVDDF : 6;            /*!< [31..26] Low power VDDF trim.                                             */
    } SIMOBUCK12_b;
  } ;

  union {
    __IOM uint32_t SIMOBUCK13;                  /*!< (@ 0x00000370) SIMO Buck Compare, Brown out, Active, Low power
                                                                    Trim Control                                               */

    struct {
            uint32_t            : 20;
      __IOM uint32_t ACTTRIMVDDS : 6;           /*!< [25..20] Active VDDS trim.                                                */
      __IOM uint32_t LPTRIMVDDS : 6;            /*!< [31..26] Low power VDDS trim.                                             */
    } SIMOBUCK13_b;
  } ;
  __IM  uint32_t  RESERVED21;

  union {
    __IOM uint32_t SIMOBUCK15;                  /*!< (@ 0x00000378) SIMO Buck Compare, Brown out, Active and Low
                                                                    power Trim Control                                         */

    struct {
            uint32_t            : 24;
      __IOM uint32_t ZXCOMPOFFSETTRIM : 5;      /*!< [28..24] Zxcomp offset trim. Feedthrough to analog.                       */
            uint32_t            : 2;
      __IOM uint32_t TRIMLATCHOVER : 1;         /*!< [31..31] Override / Bypass the simobuck trim latch to enable
                                                     on-the-fly trimming for VDDF and VDDS active and LP trims                 */
    } SIMOBUCK15_b;
  } ;

  union {
    __IOM uint32_t PWRSW0;                      /*!< (@ 0x0000037C) PWRSW Control 0                                            */

    struct {
      __IOM uint32_t PWRSWVDDCPUDYNSEL : 2;     /*!< [1..0] override value for pwrsw_vddcpu_dynsel                             */
      __IOM uint32_t PWRSWVDDCPUPGN : 1;        /*!< [2..2] override value for pwrsw_vddcpu_pgn                                */
      __IOM uint32_t PWRSWVDDCPUOVERRIDE : 1;   /*!< [3..3] override enable for pwrsw_vddcpu_dynsel and pgn                    */
      __IOM uint32_t PWRSWVDDCAORDYNSEL : 2;    /*!< [5..4] override value for pwrsw_vddcaor_dynsel                            */
      __IOM uint32_t PWRSWVDDCAOROVERRIDE : 1;  /*!< [6..6] override enable for pwrsw_vddcaor_dynsel                           */
      __IOM uint32_t PWRSWVDDDSP0DYNSEL : 2;    /*!< [8..7] override value for pwrsw_vdddsp0_dynsel                            */
      __IOM uint32_t PWRSWVDDDSP0PGN : 1;       /*!< [9..9] override value for pwrsw_vdddsp0_pgn                               */
      __IOM uint32_t PWRSWVDDDSP0OVERRIDE : 1;  /*!< [10..10] override enable for pwrsw_vdddsp0_dynsel and pgn                 */
      __IOM uint32_t PWRSWVDDDSP1DYNSEL : 2;    /*!< [12..11] override value for pwrsw_vdddsp1_dynsel                          */
      __IOM uint32_t PWRSWVDDDSP1PGN : 1;       /*!< [13..13] override value for pwrsw_vdddsp1_pgn                             */
      __IOM uint32_t PWRSWVDDDSP1OVERRIDE : 1;  /*!< [14..14] override enable for pwrsw_vdddsp1_dynsel and pgn                 */
      __IOM uint32_t PWRSWVDDMCPUDYNSEL : 1;    /*!< [15..15] override value for pwrsw_vddmcpu_dynsel                          */
      __IOM uint32_t PWRSWVDDMCPUSTATSEL : 1;   /*!< [16..16] VDDMCPU power switch static select                               */
      __IOM uint32_t PWRSWVDDMCPUOVERRIDE : 1;  /*!< [17..17] override enable for pwrsw_vddmcpu_dynsel                         */
      __IOM uint32_t PWRSWVDDMDSP0DYNSEL : 1;   /*!< [18..18] override value for pwrsw_vddmdsp0_dynsel                         */
      __IOM uint32_t PWRSWVDDMDSP0STATSEL : 1;  /*!< [19..19] VDDMDSP0 power switch static select                              */
      __IOM uint32_t PWRSWVDDMDSP0OVERRIDE : 1; /*!< [20..20] override enable for pwrsw_vddmdsp0_dynsel                        */
      __IOM uint32_t PWRSWVDDMDSP1DYNSEL : 1;   /*!< [21..21] override value for pwrsw_vddmdsp1_dynsel                         */
      __IOM uint32_t PWRSWVDDMDSP1STATSEL : 1;  /*!< [22..22] VDDMDSP1 power switch static select                              */
      __IOM uint32_t PWRSWVDDMDSP1OVERRIDE : 1; /*!< [23..23] override enable for pwrsw_vddmdsp1_dynsel                        */
      __IOM uint32_t PWRSWVDDMLDYNSEL : 1;      /*!< [24..24] override value for pwrsw_vddml_dynsel                            */
      __IOM uint32_t PWRSWVDDMLSTATSEL : 1;     /*!< [25..25] VDDML power switch static select                                 */
      __IOM uint32_t PWRSWVDDMLOVERRIDE : 1;    /*!< [26..26] override enable for pwrsw_vddml_dynsel                           */
      __IOM uint32_t PWRSWVDDRCPUDYNSEL : 2;    /*!< [28..27] override value for pwrsw_vddrcpu_dynsel                          */
      __IOM uint32_t PWRSWVDDRCPUPGN : 1;       /*!< [29..29] override value for pwrsw_vddrcpu_pgn                             */
      __IOM uint32_t PWRSWVDDRCPUSTATSEL : 1;   /*!< [30..30] VDDRCPU power switch static select                               */
      __IOM uint32_t PWRSWVDDRCPUOVERRIDE : 1;  /*!< [31..31] override enable for pwrsw_vddrcpu_dynsel and pgn                 */
    } PWRSW0_b;
  } ;

  union {
    __IOM uint32_t PWRSW1;                      /*!< (@ 0x00000380) PWRSW Control 1                                            */

    struct {
      __IOM uint32_t PWRSWVDDRDSP0DYNSEL : 2;   /*!< [1..0] override value for pwrsw_vddrdsp0_dynsel                           */
      __IOM uint32_t PWRSWVDDRDSP0PGN : 1;      /*!< [2..2] override value for pwrsw_vddrdsp0_pgn                              */
      __IOM uint32_t PWRSWVDDRDSP0STATSEL : 1;  /*!< [3..3] VDDRDSP0 power switch static select                                */
      __IOM uint32_t PWRSWVDDRDSP0OVERRIDE : 1; /*!< [4..4] override enable for pwrsw_vddrdsp0_dynsel and pgn                  */
      __IOM uint32_t PWRSWVDDRDSP1DYNSEL : 2;   /*!< [6..5] override value for pwrsw_vddrdsp1_dynsel                           */
      __IOM uint32_t PWRSWVDDRDSP1PGN : 1;      /*!< [7..7] override value for pwrsw_vddrdsp1_pgn                              */
      __IOM uint32_t PWRSWVDDRDSP1STATSEL : 1;  /*!< [8..8] VDDRDSP1 power switch static select                                */
      __IOM uint32_t PWRSWVDDRDSP1OVERRIDE : 1; /*!< [9..9] override enable for pwrsw_vddrdsp1_dynsel and pgn                  */
      __IOM uint32_t PWRSWVDDRLDYNSEL : 1;      /*!< [10..10] override value for pwrsw_vddrl_dynsel                            */
      __IOM uint32_t PWRSWVDDRLPGN : 1;         /*!< [11..11] override value for pwrsw_vddrl_pgn                               */
      __IOM uint32_t PWRSWVDDRLSTATSEL : 1;     /*!< [12..12] VDDRL power switch static select                                 */
      __IOM uint32_t PWRSWVDDRLOVERRIDE : 1;    /*!< [13..13] override enable for pwrsw_vddrl_dynsel and pgn                   */
      __IOM uint32_t PWRSWVDDRMDYNSEL : 1;      /*!< [14..14] override value for pwrsw_vddrm_dynsel                            */
      __IOM uint32_t PWRSWVDDRMPGN : 1;         /*!< [15..15] override value for pwrsw_vddrm_pgn                               */
      __IOM uint32_t PWRSWVDDRMSTATSEL : 1;     /*!< [16..16] VDDRM power switch static select                                 */
      __IOM uint32_t PWRSWVDDRMOVERRIDE : 1;    /*!< [17..17] override enable for pwrsw_vddrm_dynsel and pgn                   */
      __IOM uint32_t PWRSWVDDLPGN : 1;          /*!< [18..18] override value for pwrsw_vddl_pgn                                */
      __IOM uint32_t PWRSWVDDLOVERRIDE : 1;     /*!< [19..19] override enable for pwrsw_vddl_pgn                               */
      __IOM uint32_t PWRSWCOMPPDNB : 1;         /*!< [20..20] pwrsw_comp_pdnb                                                  */
      __IOM uint32_t PWRSWOVRDRVEN : 1;         /*!< [21..21] pwrsw_ovrdrv_en                                                  */
      __IOM uint32_t DIGPWRSWOVRDRVEN : 1;      /*!< [22..22] digpwrsw_ovrdrv_en                                               */
      __IOM uint32_t DIGPWRSWOVRDRVSEL : 2;     /*!< [24..23] digpwrsw_ovrdrv_sel                                              */
      __IOM uint32_t USEVDDF4VDDRCPUINHP : 1;   /*!< [25..25] Setting this bit selects VDDF for VDDRCPU in when MCU
                                                     is in HP mode. This is valid for only normal operational
                                                     mode (i.e without overrides).                                             */
      __IOM uint32_t FORCEVDDRMVDDS : 1;        /*!< [26..26] Setting this bit selects VDDS for VDDRM when Flash
                                                     is off. This is valid for only normal operational mode
                                                     (i.e. without overrides).                                                 */
      __IOM uint32_t FORCEVDDRMOFF : 1;         /*!< [27..27] Setting this bit forces VDDRM to be open when Flash
                                                     is off. This is valid for only normal operational mode
                                                     (i.e. without overrides).                                                 */
      __IOM uint32_t SHORTVDDCVDDCLVOREN : 1;   /*!< [28..28] pwrsw short override select for vddc/vddclv                      */
      __IOM uint32_t SHORTVDDCVDDCLVORVAL : 1;  /*!< [29..29] pwrsw short override value for vddc/vddclv                       */
      __IOM uint32_t SHORTVDDFVDDSOREN : 1;     /*!< [30..30] pwrsw short override select for vddf/vdds                        */
      __IOM uint32_t SHORTVDDFVDDSORVAL : 1;    /*!< [31..31] pwrsw short override value for vddf/vdds                         */
    } PWRSW1_b;
  } ;
  __IM  uint32_t  RESERVED22;

  union {
    __IOM uint32_t USBRSTCTRL;                  /*!< (@ 0x00000388) USB Reset Startup Control                                  */

    struct {
      __IOM uint32_t USBRSTENABLE : 1;          /*!< [0..0] This bit enables this register control. If set to '1',
                                                     the reset release bits will be active. If set to '0', this
                                                     register is not controlling the USB override bits.                        */
      __IOM uint32_t USBPORRSTRELEASE : 1;      /*!< [1..1] Set this bit to '1' after USB power domain is up. This
                                                     will release the reset override condition                                 */
      __IOM uint32_t USBUTMIRSTRELEASE : 1;     /*!< [2..2] Set this bit to '1' after USB power domain is up. This
                                                     will release the reset override condition                                 */
            uint32_t            : 29;
    } USBRSTCTRL_b;
  } ;
  __IM  uint32_t  RESERVED23[7];

  union {
    __IOM uint32_t FLASHWPROT0;                 /*!< (@ 0x000003A8) These bits write-protect flash in 16KB chunks.             */

    struct {
      __IOM uint32_t FW0BITS    : 32;           /*!< [31..0] Write protect flash 0x00000000 - 0x0007FFFF. Each bit
                                                     provides write protection for 16KB chunks of flash data
                                                     space. Bits are cleared by writing a 1 to the bit. When
                                                     read, 0 indicates the region is protected. Bits are sticky
                                                     (can be set when PROTLOCK is 1, but only cleared by reset)                */
    } FLASHWPROT0_b;
  } ;

  union {
    __IOM uint32_t FLASHWPROT1;                 /*!< (@ 0x000003AC) These bits write-protect flash in 16KB chunks.             */

    struct {
      __IOM uint32_t FW1BITS    : 32;           /*!< [31..0] Write protect flash 0x00080000 - 0x000FFFFF. Each bit
                                                     provides write protection for 16KB chunks of flash data
                                                     space. Bits are cleared by writing a 1 to the bit. When
                                                     read, 0 indicates the region is protected. Bits are sticky
                                                     (can be set when PROTLOCK is 1, but only cleared by reset)                */
    } FLASHWPROT1_b;
  } ;

  union {
    __IOM uint32_t FLASHWPROT2;                 /*!< (@ 0x000003B0) These bits write-protect flash in 16KB chunks.             */

    struct {
      __IOM uint32_t FW2BITS    : 32;           /*!< [31..0] Write protect flash 0x00100000 - 0x0017FFFF. Each bit
                                                     provides write protection for 16KB chunks of flash data
                                                     space. Bits are cleared by writing a 1 to the bit. When
                                                     read, 0 indicates the region is protected. Bits are sticky
                                                     (can be set when PROTLOCK is 1, but only cleared by reset)                */
    } FLASHWPROT2_b;
  } ;

  union {
    __IOM uint32_t FLASHWPROT3;                 /*!< (@ 0x000003B4) These bits write-protect flash in 16KB chunks.             */

    struct {
      __IOM uint32_t FW3BITS    : 32;           /*!< [31..0] Write protect flash 0x00180000 - 0x001FFFFF. Each bit
                                                     provides write protection for 16KB chunks of flash data
                                                     space. Bits are cleared by writing a 1 to the bit. When
                                                     read, 0 indicates the region is protected. Bits are sticky
                                                     (can be set when PROTLOCK is 1, but only cleared by reset)                */
    } FLASHWPROT3_b;
  } ;

  union {
    __IOM uint32_t FLASHRPROT0;                 /*!< (@ 0x000003B8) These bits read-protect flash in 16KB chunks.              */

    struct {
      __IOM uint32_t FR0BITS    : 32;           /*!< [31..0] Copy (read) protect flash 0x00000000 - 0x0007FFFF. Each
                                                     bit provides read protection for 16KB chunks of flash.
                                                     Bits are cleared by writing a 1 to the bit. When read,
                                                     0 indicates the region is protected. Bits are sticky (can
                                                     be set when PROTLOCK is 1, but only cleared by reset)                     */
    } FLASHRPROT0_b;
  } ;

  union {
    __IOM uint32_t FLASHRPROT1;                 /*!< (@ 0x000003BC) These bits read-protect flash in 16KB chunks.              */

    struct {
      __IOM uint32_t FR1BITS    : 32;           /*!< [31..0] Copy (read) protect flash 0x00080000 - 0x000FFFFF. Each
                                                     bit provides read protection for 16KB chunks of flash.
                                                     Bits are cleared by writing a 1 to the bit. When read,
                                                     0 indicates the region is protected. Bits are sticky (can
                                                     be set when PROTLOCK is 1, but only cleared by reset)                     */
    } FLASHRPROT1_b;
  } ;

  union {
    __IOM uint32_t FLASHRPROT2;                 /*!< (@ 0x000003C0) These bits read-protect flash in 16KB chunks.              */

    struct {
      __IOM uint32_t FR2BITS    : 32;           /*!< [31..0] Copy (read) protect flash 0x00100000 - 0x0017FFFF. Each
                                                     bit provides read protection for 16KB chunks of flash.
                                                     Bits are cleared by writing a 1 to the bit. When read,
                                                     0 indicates the region is protected. Bits are sticky (can
                                                     be set when PROTLOCK is 1, but only cleared by reset)                     */
    } FLASHRPROT2_b;
  } ;

  union {
    __IOM uint32_t FLASHRPROT3;                 /*!< (@ 0x000003C4) These bits read-protect flash in 16KB chunks.              */

    struct {
      __IOM uint32_t FR3BITS    : 32;           /*!< [31..0] Copy (read) protect flash 0x00180000 - 0x001FFFFF. Each
                                                     bit provides read protection for 16KB chunks of flash.
                                                     Bits are cleared by writing a 1 to the bit. When read,
                                                     0 indicates the region is protected. Bits are sticky (can
                                                     be set when PROTLOCK is 1, but only cleared by reset)                     */
    } FLASHRPROT3_b;
  } ;

  union {
    __IOM uint32_t DMASRAMWPROT0;               /*!< (@ 0x000003C8) These bits write-protect system SRAM from DMA
                                                                    operations in 8KB chunks.                                  */

    struct {
      __IOM uint32_t DMAWPROT0  : 32;           /*!< [31..0] Write protect SRAM from DMA. Each bit provides write
                                                     protection for an 8KB region of memory. When set to 1,
                                                     the region will be protected from DMA writes, when set
                                                     to 0, DMA may write the region.                                           */
    } DMASRAMWPROT0_b;
  } ;

  union {
    __IOM uint32_t DMASRAMWPROT1;               /*!< (@ 0x000003CC) These bits write-protect system SRAM from DMA
                                                                    operations in 8KB chunks.                                  */

    struct {
      __IOM uint32_t DMAWPROT1  : 16;           /*!< [15..0] Write protect SRAM from DMA. Each bit provides write
                                                     protection for an 8KB region of memory. When set to 1,
                                                     the region will be protected from DMA writes, when set
                                                     to 0, DMA may write the region.                                           */
            uint32_t            : 16;
    } DMASRAMWPROT1_b;
  } ;

  union {
    __IOM uint32_t DMASRAMRPROT0;               /*!< (@ 0x000003D0) These bits read-protect system SRAM from DMA
                                                                    operations in 8KB chunks.                                  */

    struct {
      __IOM uint32_t DMARPROT0  : 32;           /*!< [31..0] Read protect SRAM from DMA. Each bit provides write
                                                     protection for an 8KB region of memory. When set to 1,
                                                     the region will be protected from DMA reads, when set to
                                                     0, DMA may read the region.                                               */
    } DMASRAMRPROT0_b;
  } ;

  union {
    __IOM uint32_t DMASRAMRPROT1;               /*!< (@ 0x000003D4) These bits read-protect system SRAM from DMA
                                                                    operations in 8KB chunks.                                  */

    struct {
      __IOM uint32_t DMARPROT1  : 16;           /*!< [15..0] Read protect SRAM from DMA. Each bit provides write
                                                     protection for an 8KB region of memory. When set to 1,
                                                     the region will be protected from DMA reads, when set to
                                                     0, DMA may read the region.                                               */
            uint32_t            : 16;
    } DMASRAMRPROT1_b;
  } ;
  __IM  uint32_t  RESERVED24[16];

  union {
    __IOM uint32_t USBPHYRESET;                 /*!< (@ 0x00000418) DSP0 CACHE RAM TRIM                                        */

    struct {
      __IOM uint32_t USBPHYPORRSTDIS : 1;       /*!< [0..0] De-assert USB PHY POR reset override                               */
      __IOM uint32_t USBPHYUTMIRSTDIS : 1;      /*!< [1..1] De-assert USB PHY UTMI reset override                              */
      __IOM uint32_t RESERVED01 : 3;            /*!< [4..2] DSP0 ICACHE TAG EMA                                                */
      __IOM uint32_t RESERVED02 : 1;            /*!< [5..5] DSP0 ICACHE TAG EMAS                                               */
      __IOM uint32_t RESERVED03 : 2;            /*!< [7..6] DSP0 ICACHE TAG EMAW                                               */
      __IOM uint32_t RESERVED04 : 1;            /*!< [8..8] DSP0 ICACHE TAG RAWL                                               */
      __IOM uint32_t RESERVED05 : 2;            /*!< [10..9] DSP0 ICACHE TAG RAWLM                                             */
      __IOM uint32_t RESERVED06 : 1;            /*!< [11..11] DSP0 ICACHE TAG RAM WABL - Write Assist Enable (active
                                                     high)                                                                     */
      __IOM uint32_t RESERVED07 : 3;            /*!< [14..12] DSP0 ICACHE TAG WABLM - 00=No adjust 11=increased delay,
                                                     enabled by WABL                                                           */
            uint32_t            : 1;
      __IOM uint32_t RESERVED09 : 1;            /*!< [16..16] DSP0 ICACHE DATA RET1N value                                     */
      __IOM uint32_t RESERVED10 : 1;            /*!< [17..17] Override for DSP0 ICACHE DATA RET1N override enable              */
      __IOM uint32_t RESERVED11 : 3;            /*!< [20..18] DSP0 ICACHE DATA EMA                                             */
      __IOM uint32_t RESERVED12 : 1;            /*!< [21..21] DSP0 ICACHE DATA EMAS                                            */
      __IOM uint32_t RESERVED13 : 2;            /*!< [23..22] DSP0 ICACHE DATA EMAW                                            */
      __IOM uint32_t RESERVED14 : 1;            /*!< [24..24] DSP0 ICACHE DATA RAWL                                            */
      __IOM uint32_t RESERVED15 : 2;            /*!< [26..25] DSP0 ICACHE DATA RAWLM                                           */
      __IOM uint32_t RESERVED16 : 1;            /*!< [27..27] DSP0 ICACHE DATA RAM WABL - Write Assist Enable (active
                                                     high)                                                                     */
      __IOM uint32_t RESERVED17 : 3;            /*!< [30..28] DSP0 ICACHE DATA WABLM - 00=No adjust 11=increased
                                                     delay, enabled by WABL                                                    */
      __IOM uint32_t RESERVED18 : 1;            /*!< [31..31] Self-timed override (test mode only)                             */
    } USBPHYRESET_b;
  } ;
  __IM  uint32_t  RESERVED25[4];

  union {
    __IOM uint32_t AUDADCPWRCTRL;               /*!< (@ 0x0000042C) Audio ADC Power Control                                    */

    struct {
      __IOM uint32_t AUDADCPWRCTRLSWE : 1;      /*!< [0..0] Audio ADC Power Control Software Override Enable                   */
      __IOM uint32_t AUDADCAPSEN : 1;           /*!< [1..1] Enable the Global audio ADC Power Switch on when set
                                                     to 1 if the AUDADCPWRCTRLSWE bit is set.                                  */
      __IOM uint32_t AUDADCBPSEN : 1;           /*!< [2..2] Enable the Analog, IO and SAR Digital logic Power Switch
                                                     on when set to 1 if the AUDADCPWRCTRLSWE bit is set.                      */
      __IOM uint32_t AUDBGTPEN  : 1;            /*!< [3..3] Bandgap and Temperature Sensor Power Switch Enable                 */
      __IOM uint32_t AUDREFBUFPEN : 1;          /*!< [4..4] Reference Buffer Power Switch Enable                               */
      __IOM uint32_t AUDREFKEEPPEN : 1;         /*!< [5..5] Reference Buffer Keeper Power Switch Enable                        */
            uint32_t            : 2;
      __IOM uint32_t VDDAUDADCSARISOLATE : 1;   /*!< [8..8] ISOLATE signal for Power Switched SAR ( when AUDADCBPSEN
                                                     is switched off )                                                         */
      __IOM uint32_t VDDAUDADCDIGISOLATE : 1;   /*!< [9..9] ISOLATE signal for audio ADC Digital Contoller ( when
                                                     AUDADCAPSEN is switched off and if the AUDADCPWRCTRLSWE
                                                     bit is set)                                                               */
      __IOM uint32_t VDDAUDADCRESETN : 1;       /*!< [10..10] RESETN signal for Power Switched SAR and Digital Controller
                                                     (when global power switch is off and if the AUDADCPWRCTRLSWE
                                                     bit is set)                                                               */
            uint32_t            : 1;
      __IOM uint32_t AUDADCVBATDIVEN : 1;       /*!< [12..12] Audio ADC VBAT DIV Power Enable ( if the AUDADCPWRCTRLSWE
                                                     bit is set )                                                              */
            uint32_t            : 1;
      __IOM uint32_t AUDADCINBUFSEL : 2;        /*!< [15..14] Audio ADC input buffer mux select                                */
      __IOM uint32_t AUDADCINBUFEN : 1;         /*!< [16..16] Audio ADC Input Buffer Power Enable ( if the AUDADCPWRCTRLSWE
                                                     bit is set )                                                              */
      __IOM uint32_t AUDADCRFBUFSLWEN : 1;      /*!< [17..17] Audio ADC reference buffer slew enable                           */
      __IOM uint32_t AUDADCKEEPOUTEN : 1;       /*!< [18..18] Audio ADC reference keeper out en                                */
            uint32_t            : 13;
    } AUDADCPWRCTRL_b;
  } ;

  union {
    __IOM uint32_t AUDIO1;                      /*!< (@ 0x00000430) Audio trims 1                                              */

    struct {
            uint32_t            : 6;
      __IOM uint32_t MICBIASVOLTAGETRIM : 6;    /*!< [11..6] Output voltage trim                                               */
      __IOM uint32_t MICBIASPDNB : 1;           /*!< [12..12] Power down control for the block                                 */
            uint32_t            : 19;
    } AUDIO1_b;
  } ;
  __IM  uint32_t  RESERVED26;

  union {
    __IOM uint32_t PGAADCIFCTRL;                /*!< (@ 0x00000438) PGA ADCIF control                                          */

    struct {
      __IOM uint32_t PGAADCIFCHAACTIVE : 2;     /*!< [1..0] PGAADCIF active signal for channels A0 and A1. Starts
                                                     and stops 2 clocks after demultiplexed SOC signal.                        */
      __IOM uint32_t PGAADCIFCHAPDNB : 2;       /*!< [3..2] Power down for channels A0 and A1 (0 = powered down;
                                                     1 = standby)                                                              */
      __IOM uint32_t PGAADCIFCHBACTIVE : 2;     /*!< [5..4] PGAADCIF active signal for channels B0 and B1. Starts
                                                     and stops 2 clocks after demultiplexed SOC signal.                        */
      __IOM uint32_t PGAADCIFCHBPDNB : 2;       /*!< [7..6] Power down for channels B0 and B1 (0 = powered down;
                                                     1 = standby)                                                              */
            uint32_t            : 4;
      __IOM uint32_t PGAADCIFVCOMPEN : 1;       /*!< [12..12] Enable for VCOMP output                                          */
      __IOM uint32_t PGAADCIFVCOMPSEL : 2;      /*!< [14..13] Select for VCOMP output (0: A0, 1: A1, 2: B0, 3: B1)             */
            uint32_t            : 17;
    } PGAADCIFCTRL_b;
  } ;

  union {
    __IOM uint32_t PGACTRL1;                    /*!< (@ 0x0000043C) PGA control 1                                              */

    struct {
      __IOM uint32_t PGACHA0GAIN1SEL : 3;       /*!< [2..0] Channel A0 preamp gain (0: 12dB, ..., 7: 33dB in 3 dB
                                                     steps)                                                                    */
      __IOM uint32_t PGACHA0GAIN2DIV2SEL : 1;   /*!< [3..3] Channel A0 PGA divide by two select (0: 0 dB, 1: -6dB),
                                                     needed for fully differential inputs                                      */
      __IOM uint32_t PGACHA0GAIN2SEL : 5;       /*!< [8..4] Channel A0 PGA gain (0: 0dB, ..., 23: 11.5dB in 0.5 dB
                                                     steps)                                                                    */
      __IOM uint32_t PGACHA1GAIN1SEL : 3;       /*!< [11..9] Channel A1 preamp gain (0: 12dB, ..., 7: 33dB in 3 dB
                                                     steps)                                                                    */
      __IOM uint32_t PGACHA1GAIN2DIV2SEL : 1;   /*!< [12..12] Channel A1 PGA divide by two select (0: 0 dB, 1: -6dB),
                                                     needed for fully differential inputs                                      */
      __IOM uint32_t PGACHA1GAIN2SEL : 5;       /*!< [17..13] Channel A1 PGA gain (0: 0dB, ..., 23: 11.5dB in 0.5
                                                     dB steps)                                                                 */
      __IOM uint32_t PGACHABYPASSEN : 2;        /*!< [19..18] Bypass enable for Channels A0 and A1 (1: bypass, when
                                                     gain LT 12 dB; 0: otherwise)                                              */
      __IOM uint32_t PGACHAOPAMPINPDNB : 2;     /*!< [21..20] Channels A0 and A1 input stage opamp power down (0:
                                                     powered down, 1: powered up). Must be 1 when respective
                                                     PGACHABYPASSEN = 0.                                                       */
      __IOM uint32_t PGACHAOPAMPOUTPDNB : 2;    /*!< [23..22] Channels A0 and A1 output stage opamp power down (0:
                                                     powered down, 1: powered up)                                              */
      __IOM uint32_t PGACHAVCMGENPDNB : 1;      /*!< [24..24] Channel A VCMGEN power down (0: powered down, 1: powered
                                                     up)                                                                       */
      __IOM uint32_t PGACHAVCMGENQCHARGEEN : 1; /*!< [25..25] Channel A VCMGEN quick charge enable (pulsed during
                                                     channel powerup)                                                          */
      __IOM uint32_t PGAIREFGENPDNB : 1;        /*!< [26..26] IREFGEN power down (0: powered down, 1: powered up)              */
      __IOM uint32_t PGAVREFGENPDNB : 1;        /*!< [27..27] VREFGEN power down (0: powered down, 1: powered up)              */
      __IOM uint32_t PGAVREFGENQUICKSTARTEN : 1;/*!< [28..28] VREFGEN quick start enable (pulsed during startup)               */
      __IOM uint32_t VCOMPSELPGA : 1;           /*!< [29..29] Select for VCOMP output (0: A0, 1: A1, 2: B0, 3: B1)             */
            uint32_t            : 1;
      __IOM uint32_t PGAGAINAOVRD : 1;          /*!< [31..31] Apply BYPASS and GAIN bits from this register (for
                                                     channel A) instead of automatically via audio ADC. Note
                                                     that audio ADC FIFO meta data will not reflect dB gain
                                                     as used when configuring audio ADC.                                       */
    } PGACTRL1_b;
  } ;

  union {
    __IOM uint32_t PGACTRL2;                    /*!< (@ 0x00000440) PGA control 2                                              */

    struct {
      __IOM uint32_t PGACHB0GAIN1SEL : 3;       /*!< [2..0] Channel B0 preamp gain (0: 12dB, ..., 7: 33dB in 3 dB
                                                     steps)                                                                    */
      __IOM uint32_t PGACHB0GAIN2DIV2SEL : 1;   /*!< [3..3] Channel B0 PGA divide by two select (0: 0 dB, 1: -6dB),
                                                     needed for fully differential inputs                                      */
      __IOM uint32_t PGACHB0GAIN2SEL : 5;       /*!< [8..4] Channel B0 PGA gain (0: 0dB, ..., 23: 11.5dB in 0.5 dB
                                                     steps)                                                                    */
      __IOM uint32_t PGACHB1GAIN1SEL : 3;       /*!< [11..9] Channel B1 preamp gain (0: 12dB, ..., 7: 33dB in 3 dB
                                                     steps)                                                                    */
      __IOM uint32_t PGACHB1GAIN2DIV2SEL : 1;   /*!< [12..12] Channel B1 PGA divide by two select (0: 0 dB, 1: -6dB),
                                                     needed for fully differential inputs                                      */
      __IOM uint32_t PGACHB1GAIN2SEL : 5;       /*!< [17..13] Channel B1 PGA gain (0: 0dB, ..., 23: 11.5dB in 0.5
                                                     dB steps)                                                                 */
      __IOM uint32_t PGACHBBYPASSEN : 2;        /*!< [19..18] Bypass enable for Channels B0 and B1 (1: bypass, when
                                                     gain LT 12 dB; 0: otherwise)                                              */
      __IOM uint32_t PGACHBOPAMPINPDNB : 2;     /*!< [21..20] Channels B0 and B1 input stage opamp power down (0:
                                                     powered down, 1: powered up). Must be 1 when respective
                                                     PGACHBBYPASSEN = 0.                                                       */
      __IOM uint32_t PGACHBOPAMPOUTPDNB : 2;    /*!< [23..22] Channels B0 and B1 output stage opamp power down (0:
                                                     powered down, 1: powered up)                                              */
      __IOM uint32_t PGACHBVCMGENPDNB : 1;      /*!< [24..24] Channel B VCMGEN power down (0: powered down, 1: powered
                                                     up)                                                                       */
      __IOM uint32_t PGACHBVCMGENQCHARGEEN : 1; /*!< [25..25] Channel B VCMGEN quick charge enable (pulsed during
                                                     channel powerup)                                                          */
            uint32_t            : 5;
      __IOM uint32_t PGAGAINBOVRD : 1;          /*!< [31..31] Apply BYPASS and GAIN bits from this register (for
                                                     channel B) instead of automatically via audio ADC. Note
                                                     that audio ADC FIFO meta data will not reflect dB gain
                                                     as used when configuring audio ADC.                                       */
    } PGACTRL2_b;
  } ;

  union {
    __IOM uint32_t AUDADCPWRDLY;                /*!< (@ 0x00000444) Audio ADC Power Up Delay Control                           */

    struct {
      __IOM uint32_t AUDADCPWR0 : 8;            /*!< [7..0] ADC Reference Buffer Power Enable delay in 64 ADC CLK
                                                     increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments
                                                     for ADC_CLKSEL = 0x2.                                                     */
      __IOM uint32_t AUDADCPWR1 : 8;            /*!< [15..8] ADC Reference Keeper enable delay in 16 ADC CLK increments
                                                     for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL
                                                     = 0x2.                                                                    */
            uint32_t            : 16;
    } AUDADCPWRDLY_b;
  } ;
  __IM  uint32_t  RESERVED27[2];

  union {
    __IOM uint32_t SDIOCTRL;                    /*!< (@ 0x00000450) SDIO/eMMC Control                                          */

    struct {
      __IOM uint32_t SDIOSYSCLKEN : 1;          /*!< [0..0] SDIO system clock enable.                                          */
      __IOM uint32_t SDIOXINCLKEN : 1;          /*!< [1..1] SDIO serial clock source enable.                                   */
      __IOM uint32_t SDIOITAPCHGWIN : 1;        /*!< [2..2] This is used to gate the output of the Tap Delay lines
                                                     so as to avoid glithches being propagated into the Core.
                                                     This signal should be asserted few clocks before the itapdlysel
                                                     changes and should be asserted for few clocks after.                      */
      __IOM uint32_t SDIOITAPDLYENA : 1;        /*!< [3..3] Used to enable selective Tap delay line on the Looped
                                                     back SD Clock (rxclk_in). This signal along with the itapdlysel[4:0]
                                                     selects the the amount of delay to be inserted on the line.
                                                     When Tuning is enabled (for SDR104 and optionally for SDR50),
                                                     this signal is ignored and internalcontrols are used instead.
                                                     This should not be asserted when operating in DS mode.                    */
      __IOM uint32_t SDIOITAPDLYSEL : 5;        /*!< [8..4] Selects one of the 32 Taps on the rxclk_in line. This
                                                     is effective only when itapdlyena is asserted and Tuning
                                                     is not enabled.                                                           */
      __IOM uint32_t SDIOOTAPDLYENA : 1;        /*!< [9..9] Used to enable the selective Tap delay on the sdcard_clk
                                                     so as to generate the delayed sdcard_clk. This is used
                                                     to latch the CMD/DAT outputs to generate delay on them
                                                     w.r.t CLK going out. This signal along with otapdlysel[3:0]
                                                     selects the amount of delay to be inserted on the Clock
                                                     line. This signal should not be asserted when operating
                                                     in DS mode.                                                               */
      __IOM uint32_t SDIOOTAPDLYSEL : 4;        /*!< [13..10] Selects one of the 16 Taps on the sdcard_clk. This
                                                     is effective only when otapdlyena is asserted.                            */
      __IOM uint32_t SDIOASYNCWKUPENA : 1;      /*!< [14..14] SDIO asynchronous wakeup mode. 0: Synchronous wakeup
                                                     mode, 1: Asynchronous wakeup mode                                         */
      __IOM uint32_t SDIOXINCLKSEL : 2;         /*!< [16..15] Select clock source for SDIO xin_clk.                            */
      __IOM uint32_t SDIOCMDOPENDRAINEN : 1;    /*!< [17..17] SDIO CMD line configured as open-drian. 0: Push-pull
                                                     mode, 1: Open-drain mode                                                  */
      __IOM uint32_t SDIODATOPENDRAINEN : 1;    /*!< [18..18] SDIO DAT line configured as open-drian. 0: Push-pull
                                                     mode, 1: Open-drain mode                                                  */
            uint32_t            : 13;
    } SDIOCTRL_b;
  } ;

  union {
    __IOM uint32_t PDMCTRL;                     /*!< (@ 0x00000454) PDM Control                                                */

    struct {
      __IOM uint32_t PDMGLOBALEN : 1;           /*!< [0..0] PDM global enable to allow all PDMs to have synchronized
                                                     interface clocks and FIFO sampling.                                       */
            uint32_t            : 31;
    } PDMCTRL_b;
  } ;
} MCUCTRL_Type;                                 /*!< Size = 1112 (0x458)                                                       */



/* =========================================================================================================================== */
/* ================                                           MSPI0                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Multi-bit SPI Master (MSPI0)
  */

typedef struct {                                /*!< (@ 0x40060000) MSPI0 Structure                                            */

  union {
    __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) This register is used to enable individual PIO
                                                                    based transactions to a device on the bus.
                                                                    The CFG register must be programmed properly
                                                                    for the transfer, and the ADDR and INSTR
                                                                    registers should be programmed if the SENDI
                                                                    and SENDA fields are enabled.                              */

    struct {
      __IOM uint32_t START      : 1;            /*!< [0..0] Write to 1 to initiate a PIO transaction on the bus (typically
                                                     the entire register should be written at once with this
                                                     bit set).                                                                 */
      __IOM uint32_t STATUS     : 1;            /*!< [1..1] Command status: 1 indicates command has completed. Cleared
                                                     by writing 1 to this bit or starting a new transfer.                      */
      __IOM uint32_t BUSY       : 1;            /*!< [2..2] Command status: 1 indicates controller is busy (command
                                                     in progress)                                                              */
            uint32_t            : 1;
      __IOM uint32_t PIODEV     : 1;            /*!< [4..4] Selects the Device configutation to use for PIO requests           */
      __IOM uint32_t SENDA      : 1;            /*!< [5..5] Indicates whether an address phase should be sent (see
                                                     ADDR register and ASIZE field in CFG register)                            */
      __IOM uint32_t SENDI      : 1;            /*!< [6..6] Indicates whether an instruction phase should be sent
                                                     (see INSTR field and ISIZE field in CFG register)                         */
      __IOM uint32_t TXRX       : 1;            /*!< [7..7] 1 Indicates a TX operation, 0 indicates an RX operation
                                                     of XFERBYTES                                                              */
      __IOM uint32_t BIGENDIAN  : 1;            /*!< [8..8] 1 indicates data in FIFO is in big endian format (MSB
                                                     first); 0 indicates little endian data (default, LSB first).              */
      __IOM uint32_t PIOSCRAMBLE : 1;           /*!< [9..9] Enables data scrambling for PIO opertions. This should
                                                     only be used for data operations and never for commands
                                                     to a device.                                                              */
      __IOM uint32_t ENTURN     : 1;            /*!< [10..10] Indicates whether TX->RX turnaround cycles should be
                                                     enabled for this operation (see TURNAROUND field in CFG
                                                     register).                                                                */
      __IOM uint32_t ENDCX      : 1;            /*!< [11..11] Enable DCX signal on data [1]                                    */
      __IOM uint32_t ENWLAT     : 1;            /*!< [12..12] Enable Write Latency Counter (time between address
                                                     and first data byte). Counter value is WRITELATENCY.                      */
      __IOM uint32_t HALFWORDREVERSE : 1;       /*!< [13..13] Reverse bytes in half-word. Little endian data: {[7:0],[15:8],[23:16]
                                                     [31:24]} -> {[15:8],[7:0],[31:24],[23:16]}; big endian
                                                     data: {[31:24],[23:16],[15:8],[7:0]} -> {[23:16],[31:24],[7:0],[15:8]}    */
            uint32_t            : 2;
      __IOM uint32_t XFERBYTES  : 16;           /*!< [31..16] Number of bytes to transmit or receive (based on TXRX
                                                     bit)                                                                      */
    } CTRL_b;
  } ;

  union {
    __IOM uint32_t CTRL1;                       /*!< (@ 0x00000004) These registers are used to enable individual
                                                                    PIO based transactions to a device on the
                                                                    bus. The CFG register must be programmed
                                                                    properly for the transfer, and the ADDR
                                                                    and INSTR registers should be programmed
                                                                    if the SENDI and SENDA fields are enabled.                 */

    struct {
      __IOM uint32_t PIOMIXED   : 4;            /*!< [3..0] Provides override controls for data operations where
                                                     instruction, address, and data may transfer in different
                                                     rates.                                                                    */
            uint32_t            : 28;
    } CTRL1_b;
  } ;

  union {
    __IOM uint32_t ADDR;                        /*!< (@ 0x00000008) Optional Address field to send for PIO transfers           */

    struct {
      __IOM uint32_t ADDR       : 32;           /*!< [31..0] Optional Address field to send (after optional instruction
                                                     field) - qualified by ASIZE in CMD register. NOTE: This
                                                     register is aliased to DMADEVADDR.                                        */
    } ADDR_b;
  } ;

  union {
    __IOM uint32_t INSTR;                       /*!< (@ 0x0000000C) Optional Instruction field to send for PIO transfers       */

    struct {
      __IOM uint32_t INSTR      : 16;           /*!< [15..0] Optional Instruction field to send (1st byte) - qualified
                                                     by ISEND/ISIZE                                                            */
            uint32_t            : 16;
    } INSTR_b;
  } ;

  union {
    __IOM uint32_t TXFIFO;                      /*!< (@ 0x00000010) TX Data FIFO                                               */

    struct {
      __IOM uint32_t TXFIFO     : 32;           /*!< [31..0] Data to be transmitted. Data should normally be aligned
                                                     to the LSB (pad the upper bits with zeros) unless BIGENDIAN
                                                     is set.                                                                   */
    } TXFIFO_b;
  } ;

  union {
    __IOM uint32_t RXFIFO;                      /*!< (@ 0x00000014) RX Data FIFO                                               */

    struct {
      __IOM uint32_t RXFIFO     : 32;           /*!< [31..0] Receive data. Data is aligned to the LSB (padded zeros
                                                     on upper bits) unless BIGENDIAN is set.                                   */
    } RXFIFO_b;
  } ;

  union {
    __IOM uint32_t TXENTRIES;                   /*!< (@ 0x00000018) Number of words in TX FIFO                                 */

    struct {
      __IOM uint32_t TXENTRIES  : 6;            /*!< [5..0] Number of 32-bit words/entries in TX FIFO                          */
            uint32_t            : 26;
    } TXENTRIES_b;
  } ;

  union {
    __IOM uint32_t RXENTRIES;                   /*!< (@ 0x0000001C) Number of words in RX FIFO                                 */

    struct {
      __IOM uint32_t RXENTRIES  : 6;            /*!< [5..0] Number of 32-bit words/entries in RX FIFO                          */
            uint32_t            : 26;
    } RXENTRIES_b;
  } ;

  union {
    __IOM uint32_t THRESHOLD;                   /*!< (@ 0x00000020) Threshold levels that trigger RXFull and TXEmpty
                                                                    interrupts                                                 */

    struct {
      __IOM uint32_t TXTHRESH   : 6;            /*!< [5..0] Number of entries in TX FIFO that cause TXF interrupt              */
            uint32_t            : 2;
      __IOM uint32_t RXTHRESH   : 6;            /*!< [13..8] Number of entries in TX FIFO that cause RXE interrupt             */
            uint32_t            : 18;
    } THRESHOLD_b;
  } ;
  __IM  uint32_t  RESERVED[3];

  union {
    __IOM uint32_t MSPICFG;                     /*!< (@ 0x00000030) Timing configuration bits for the MSPI module.
                                                                    PRSTN, IPRSTN, and FIFORESET can be used
                                                                    to reset portions of the MSPI interface
                                                                    in order to clear error conditions. The
                                                                    remaining bits control clock frequency and
                                                                    TX/RX capture timings.                                     */

    struct {
      __IOM uint32_t APBCLK     : 1;            /*!< [0..0] Enable continuous APB clock. For power-efficient operation,
                                                     APBCLK should be set to 0.                                                */
            uint32_t            : 3;
      __IOM uint32_t IOMSEL     : 4;            /*!< [7..4] Selects which IOM is selected for CQ handshake status.             */
            uint32_t            : 21;
      __IOM uint32_t FIFORESET  : 1;            /*!< [29..29] Reset MSPI FIFO (active high). 1=reset FIFO, 0=normal
                                                     operation. May be used to manually flush the FIFO in error
                                                     handling.                                                                 */
      __IOM uint32_t IPRSTN     : 1;            /*!< [30..30] IP block reset. Write to 0 to put the transfer module
                                                     in reset or 1 for normal operation. This may be required
                                                     after error conditions to clear the transfer on the bus.                  */
      __IOM uint32_t PRSTN      : 1;            /*!< [31..31] Peripheral reset. Master reset to the entire MSPI module
                                                     (DMA, XIP, and transfer state machines). 1=normal operation,
                                                     0=in reset.                                                               */
    } MSPICFG_b;
  } ;
  __IM  uint32_t  RESERVED1[4];

  union {
    __IOM uint32_t PADOUTEN;                    /*!< (@ 0x00000044) Enable bits for the MSPI output pads. Each active
                                                                    MSPI line should be set to 1 in the OUTEN
                                                                    field below.                                               */

    struct {
      __IOM uint32_t OUTEN      : 20;           /*!< [19..0] Output pad enable configuration. Indicates which pads
                                                     should be driven. Bits [3:0] are Quad0 data. Bits [7:4]
                                                     are Quad1 data. Bit [8] is clock. Bit [9] is BM/DQS. Bit
                                                     [10:17] are data for 16-bit. Bit[18] is BM/DQS for 16-bit.
                                                     Bit[19] is not used.                                                      */
            uint32_t            : 10;
      __IOM uint32_t PADSET1    : 1;            /*!< [30..30] Only applicable on mspi1. When set, use gpio95 .. gpio
                                                     104 as the pads. This extra set of pads is to run mspi0
                                                     on HEX and mspi1 concurrently. Note that the timing of
                                                     this extra pads may not be as good as the origianl pads.                  */
      __IOM uint32_t CLKOND4    : 1;            /*!< [31..31] Output clock on MSPI data[4]                                     */
    } PADOUTEN_b;
  } ;

  union {
    __IOM uint32_t PADOVEREN;                   /*!< (@ 0x00000048) Enables PIO-like pad override control                      */

    struct {
      __IOM uint32_t OVERRIDEEN : 20;           /*!< [19..0] Output pad override enable. Bit mask for pad outputs.
                                                     When set to 1, the values in the OVERRIDE field are driven
                                                     on the pad (output enable is implicitly set in this mode).
                                                     [7:0]=data [8]=clock [9]=DM                                               */
            uint32_t            : 12;
    } PADOVEREN_b;
  } ;

  union {
    __IOM uint32_t PADOVER;                     /*!< (@ 0x0000004C) Override data value                                        */

    struct {
      __IOM uint32_t OVERRIDE   : 20;           /*!< [19..0] Output pad override value. [7:0]=data [8]=clock [9]=DM            */
            uint32_t            : 12;
    } PADOVER_b;
  } ;
  __IM  uint32_t  RESERVED2[12];

  union {
    __IOM uint32_t DEV0AXI;                     /*!< (@ 0x00000080) Specifies the base address and aperture range
                                                                    of the device as mapped onto the AXI bus                   */

    struct {
      __IOM uint32_t SIZE0      : 4;            /*!< [3..0] Indicates the AXI aperture size                                    */
      __IOM uint32_t READONLY0  : 1;            /*!< [4..4] Indicates the AXI aperture is read-only                            */
            uint32_t            : 11;
      __IOM uint32_t BASE0      : 10;           /*!< [25..16] XIPEN has to be enabled to enable aperture. The BASE
                                                     address needs to be SIZE aligned.                                         */
            uint32_t            : 6;
    } DEV0AXI_b;
  } ;

  union {
    __IOM uint32_t DEV0CFG;                     /*!< (@ 0x00000084) Command formatting for PIO based transactions
                                                                    (initiated by writes to CTRL register)                     */

    struct {
      __IOM uint32_t DEVCFG0    : 5;            /*!< [4..0] Flash configuration for XIP and AUTO DMA operations.
                                                     Controls value for SER (Slave Enable) for XIP operations
                                                     and address generation for DMA/XIP modes. Also used to
                                                     configure SPIFRF (frame format).                                          */
      __IOM uint32_t ASIZE0     : 2;            /*!< [6..5] Address Size. Address bytes to send from ADDR register             */
      __IOM uint32_t ISIZE0     : 1;            /*!< [7..7] Instruction Size                                                   */
      __IOM uint32_t TURNAROUND0 : 6;           /*!< [13..8] Number of turnaound cycles (for TX->RX transitions).
                                                     Qualified by ENTURN bit field.                                            */
      __IOM uint32_t CPHA0      : 1;            /*!< [14..14] Serial clock phase.                                              */
      __IOM uint32_t CPOL0      : 1;            /*!< [15..15] Serial clock polarity.                                           */
      __IOM uint32_t CLKDIV0    : 6;            /*!< [21..16] Clock Divider. Allows dividing 96 MHz base clock by
                                                     integer multiples. Enumerations are provided for common
                                                     frequency, but any integer divide from 96 MHz is allowed.
                                                     Odd divide ratios will result in a 33/66 percent duty cycle
                                                     with a long low clock pulse (to allow longer round-trip
                                                     for read data).                                                           */
      __IOM uint32_t RXCAP0     : 1;            /*!< [22..22] Controls RX data capture phase. A setting of 0 (NORMAL)
                                                     captures read data at the normal capture point relative
                                                     to the internal clock launch point. However, to accomodate
                                                     chip/pad/board delays, a setting of RXCAP of 1 is expected
                                                     to be used to align the capture point with the return data
                                                     window. This bit is used in conjunction with RXNEG to provide
                                                     4 unique capture points, all about 10ns apart.                            */
      __IOM uint32_t RXNEG0     : 1;            /*!< [23..23] Adjusts the RX capture phase to the negedge of the
                                                     48MHz internal clock (~10ns early). For normal operation,
                                                     it is expected that RXNEG will be set to 0.                               */
      __IOM uint32_t TXNEG0     : 1;            /*!< [24..24] Launches TX data a half clock cycle (~10ns) early.
                                                     This should normally be programmed to zero (NORMAL).                      */
      __IOM uint32_t SEPIO0     : 1;            /*!< [25..25] Separate IO configuration. This bit should be set when
                                                     the target device has separate MOSI and MISO pins. Respective
                                                     IN/OUT bits below should be set to map pins.                              */
      __IOM uint32_t WRITELATENCY0 : 6;         /*!< [31..26] Number of write Latency cycles. Qualified by ENTURN
                                                     bit field.                                                                */
    } DEV0CFG_b;
  } ;

  union {
    __IOM uint32_t DEV0DDR;                     /*!< (@ 0x00000088) Timing configuration bits for DDR operation of
                                                                    the MSPI module.                                           */

    struct {
      __IOM uint32_t EMULATEDDR0 : 1;           /*!< [0..0] Drive external clock at 1/2 rate to emulate DDR mode               */
      __IOM uint32_t QUADDDR0   : 1;            /*!< [1..1] Deprecated. No effect on RevC.                                     */
      __IOM uint32_t ENABLEDQS0 : 1;            /*!< [2..2] In EMULATEDDR mode, enable DQS for read capture                    */
      __IOM uint32_t DQSSYNCNEG0 : 1;           /*!< [3..3] Use negative edge of clock for DDR data sync                       */
      __IOM uint32_t ENABLEFINEDELAY0 : 1;      /*!< [4..4] Enables use of delay line to provide fine control over
                                                     traditional RX capture clock.                                             */
      __IOM uint32_t TXDQSDELAY0 : 5;           /*!< [9..5] This acts as an offset to the computed value (should
                                                     be set to 0 by default)                                                   */
      __IOM uint32_t RXDQSDELAY0 : 5;           /*!< [14..10] This acts as an offset to the computed value (should
                                                     be set to 0 by default)                                                   */
      __IOM uint32_t RXDQSDELAYNEG0 : 5;        /*!< [19..15] This acts as an offset to the computed value (should
                                                     be set to 0 by default) of falling edge.                                  */
      __IOM uint32_t RXDQSDELAYNEGEN0 : 1;      /*!< [20..20] When 1, RXDQSDELAYNEG is used for falling edge of the
                                                     clock.                                                                    */
      __IOM uint32_t RXDQSDELAYHI0 : 5;         /*!< [25..21] This acts as an offset to the computed value (should
                                                     be set to 0 by default) for 2nd DQS on HEX mode.                          */
      __IOM uint32_t RXDQSDELAYNEGHI0 : 5;      /*!< [30..26] This acts as an offset to the computed value (should
                                                     be set to 0 by default) of falling edge for 2nd DQS on
                                                     HEX mode.                                                                 */
      __IOM uint32_t RXDQSDELAYHIEN0 : 1;       /*!< [31..31] When 1, RXDQSDELAYHI and RXDQSDELAYNEGHI is used for
                                                     falling edge of the clock.                                                */
    } DEV0DDR_b;
  } ;

  union {
    __IOM uint32_t DEV0CFG1;                    /*!< (@ 0x0000008C) Timing and mode configuration bits for the MSPI
                                                                    module.                                                    */

    struct {
      __IOM uint32_t SFTURN0    : 4;            /*!< [3..0] Subtract from internal counter of write latency and turnaround     */
      __IOM uint32_t RXCAPEXT0  : 1;            /*!< [4..4] Specify the number of apb_clk of RX capture phse {RXCAPEXT,
                                                     RXCAP}                                                                    */
      __IOM uint32_t SCLKRXHALT0 : 1;           /*!< [5..5] Halt sclk based on xfer_count                                      */
            uint32_t            : 1;
      __IOM uint32_t WBX0       : 1;            /*!< [7..7] Enable the support of WBX ( page boundary crossing on
                                                     write )                                                                   */
      __IOM uint32_t RBX0       : 1;            /*!< [8..8] Enable the support of RBX ( page boundary crossing on
                                                     read )                                                                    */
      __IOM uint32_t RXSMP0     : 2;            /*!< [10..9] Sampling edge based on sclk edge. No effect when div1             */
      __IOM uint32_t HYPERIO0   : 1;            /*!< [11..11] When using Windbond, set this bit to 1 to generate
                                                     CA[47:0] in hardware.                                                     */
      __IOM uint32_t TAFOURTH0  : 1;            /*!< [12..12] Add 1/4th mspi_clk in DDR to turnaround. Recommended
                                                     set this to 1 when EMULATEDDR is set in non-DQS mode (ENABLEDQS
                                                     = 0).                                                                     */
      __IOM uint32_t RXHI0      : 1;            /*!< [13..13] Force st_rx to start at clock high of mspi_clk                   */
      __IOM uint32_t DQSTURN0   : 3;            /*!< [16..14] In DQS mode, the internal cycle count to enable DQS
                                                     path.                                                                     */
            uint32_t            : 15;
    } DEV0CFG1_b;
  } ;

  union {
    __IOM uint32_t DEV0XIP;                     /*!< (@ 0x00000090) When any SPI flash is configured, this register
                                                                    must be properly programmed before XIP or
                                                                    AUTO DMA operations commence.                              */

    struct {
      __IOM uint32_t XIPEN0     : 1;            /*!< [0..0] Enable the XIP (eXecute In Place) function which effectively
                                                     enables the address decoding of the MSPI device in the
                                                     flash/cache address space at address 0x04000000-0x07FFFFFF.               */
            uint32_t            : 1;
      __IOM uint32_t XIPACK0    : 2;            /*!< [3..2] Controls transmission of Micron XIP acknowledge cycles
                                                     (Micron Flash devices only)                                               */
      __IOM uint32_t XIPBIGENDIAN0 : 1;         /*!< [4..4] Indicates whether XIP/AUTO DMA data transfers are in
                                                     big or little endian format                                               */
      __IOM uint32_t XIPENTURN0 : 1;            /*!< [5..5] Indicates whether XIP/AUTO DMA operations should enable
                                                     TX->RX turnaround cycles                                                  */
      __IOM uint32_t XIPSENDA0  : 1;            /*!< [6..6] Indicates whether XIP/AUTO DMA operations should send
                                                     an an address phase (see DMADEVADDR register and ASIZE
                                                     field in CFG)                                                             */
      __IOM uint32_t XIPSENDI0  : 1;            /*!< [7..7] Indicates whether XIP/AUTO DMA operations should send
                                                     an instruction (see READINSTR field and ISIZE field in
                                                     CFG)                                                                      */
      __IOM uint32_t XIPMIXED0  : 4;            /*!< [11..8] Provides override controls for data operations where
                                                     instruction, address, and data may transfer in different
                                                     rates.                                                                    */
      __IOM uint32_t XIPENDCX0  : 1;            /*!< [12..12] Enable DCX signal on data [1] for XIP/DMA operations             */
      __IOM uint32_t XIPENWLAT0 : 1;            /*!< [13..13] Enable Write Latency counter for XIP write transactions          */
      __IOM uint32_t XIPTURNAROUND0 : 6;        /*!< [19..14] Number of turnaound cycles (for TX->RX transitions).
                                                     Qualified by XIPENTURN bit field.                                         */
      __IOM uint32_t XIPWRITELATENCY0 : 6;      /*!< [25..20] Number of write Latency cycles. Qualified by XIPENWLAT
                                                     bit field.                                                                */
      __IOM uint32_t XIPHALFWORDREVERSE0 : 1;   /*!< [26..26] Indicates whether XIP/AUTO DMA data transfers are in
                                                     Reverse bytes in half-word format                                         */
            uint32_t            : 5;
    } DEV0XIP_b;
  } ;

  union {
    __IOM uint32_t DEV0INSTR;                   /*!< (@ 0x00000094) When any SPI flash is configured, this register
                                                                    must be properly programmed before XIP or
                                                                    AUTO DMA operations commence.                              */

    struct {
      __IOM uint32_t WRITEINSTR0 : 16;          /*!< [15..0] Write command sent for DMA operations                             */
      __IOM uint32_t READINSTR0 : 16;           /*!< [31..16] Read command sent to flash for DMA/XIP operations                */
    } DEV0INSTR_b;
  } ;

  union {
    __IOM uint32_t DEV0BOUNDARY;                /*!< (@ 0x00000098) Allows large transfers to be broken up into smaller
                                                                    ones in hardware to accommodate needs of
                                                                    external devices and allow XIP/XIPMM. Only
                                                                    applicable for memory-mapped devices (PSRAM,
                                                                    Flash, etc) where address can be retransmitted
                                                                    without side effects.                                      */

    struct {
      __IOM uint32_t DMATIMELIMIT0 : 12;        /*!< [11..0] DMA time limit. Can be used to limit the transaction
                                                     time on the MSPI bus. The count is in ~100 ns increments
                                                     for the 96 MHz clock input. A value of 0 disables the counter.            */
      __IOM uint32_t DMABOUND0  : 4;            /*!< [15..12] DMA Address boundary                                             */
            uint32_t            : 16;
    } DEV0BOUNDARY_b;
  } ;

  union {
    __IOM uint32_t DEV0SCRAMBLING;              /*!< (@ 0x0000009C) Enables data scrambling for the specified range
                                                                    external flash addresses. Scrambling does
                                                                    not impact flash access performance.                       */

    struct {
      __IOM uint32_t SCRSTART0  : 10;           /*!< [9..0] Scrambling region start address [25:16] (64K block granularity).
                                                     The START block is the FIRST block included in the scrambled
                                                     address range.                                                            */
            uint32_t            : 6;
      __IOM uint32_t SCREND0    : 10;           /*!< [25..16] Scrambling region end address [25:16] (64K block granularity).
                                                     The END block is the LAST block included in the scrambled
                                                     address range.                                                            */
            uint32_t            : 5;
      __IOM uint32_t SCRENABLE0 : 1;            /*!< [31..31] Enables Data Scrambling Region. When 1 reads and writes
                                                     to the range will be scrambled. When 0, data will be read/written
                                                     unmodified. Address range is specified in 64K granularity
                                                     and the START/END ranges are included within the range.                   */
    } DEV0SCRAMBLING_b;
  } ;

  union {
    __IOM uint32_t DEV0XIPMISC;                 /*!< (@ 0x000000A0) Miscellaneous XIP control registers for AXI logic          */

    struct {
      __IOM uint32_t CEBREAK0   : 12;           /*!< [11..0] CEBREAK0 field description needed.                                */
      __IOM uint32_t XIPODD0    : 1;            /*!< [12..12] Convert odd starting address to word-aligned starting
                                                     address with byte-enables for holes. For example, an AXI
                                                     transaction with wstrb of 0x0600 results in mspi transaction
                                                     of addr=8 and BE=0b1001 ( active low ).                                   */
      __IOM uint32_t BEPOL0     : 1;            /*!< [13..13] byte mask polarity to MSPI xfer                                  */
      __IOM uint32_t BEON0      : 1;            /*!< [14..14] Byte enable always on for all lanes                              */
      __IOM uint32_t XIPBOUNDARY0 : 1;          /*!< [15..15] Deprecated. No effect on RevC.                                   */
            uint32_t            : 5;
      __IOM uint32_t APNDODD0   : 1;            /*!< [21..21] Append dummy byte to odd number of write                         */
            uint32_t            : 10;
    } DEV0XIPMISC_b;
  } ;
  __IM  uint32_t  RESERVED3[23];

  union {
    __IOM uint32_t DMACFG;                      /*!< (@ 0x00000100) DMA Configuration                                          */

    struct {
      __IOM uint32_t DMAEN      : 2;            /*!< [1..0] DMA Enable. Setting this bit to EN will start the DMA
                                                     operation                                                                 */
      __IOM uint32_t DMADIR     : 1;            /*!< [2..2] Direction                                                          */
      __IOM uint32_t DMADEV     : 1;            /*!< [3..3] DMA Device Select                                                  */
      __IOM uint32_t DMAPRI     : 2;            /*!< [5..4] Sets the Priority of the DMA request                               */
            uint32_t            : 11;
      __IOM uint32_t DMATXEMPT  : 1;            /*!< [17..17] For DMA_M2P, only start when DMA fifo is not empty.              */
      __IOM uint32_t DMAPWROFF  : 1;            /*!< [18..18] Power off MSPI domain upon completion of DMA operation.          */
            uint32_t            : 13;
    } DMACFG_b;
  } ;

  union {
    __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000104) DMA Status                                                 */

    struct {
      __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that
                                                     a DMA transfer is active. The DMA transfer may be waiting
                                                     on data, transferring data, or waiting for priority. All
                                                     of these will be indicated with a 1. A 0 will indicate
                                                     that the DMA is fully complete and no further transactions
                                                     will be done.                                                             */
      __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA
                                                     operation.                                                                */
      __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error. This active high bit signals that an error
                                                     was encountered during the DMA operation.                                 */
      __IOM uint32_t SCRERR     : 1;            /*!< [3..3] Scrambling Access Alignment Error. This active high bit
                                                     signals that a scrambling operation was specified for a
                                                     non-word aligned DEVADDR.                                                 */
            uint32_t            : 28;
    } DMASTAT_b;
  } ;

  union {
    __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x00000108) DMA Target Address                                         */

    struct {
      __IOM uint32_t TARGADDR   : 32;           /*!< [31..0] Target byte address for source of DMA (either read or
                                                     write). In cases of non-word aligned addresses, the DMA
                                                     logic will take care for ensuring only the target bytes
                                                     are read/written.                                                         */
    } DMATARGADDR_b;
  } ;

  union {
    __IOM uint32_t DMADEVADDR;                  /*!< (@ 0x0000010C) DMA Device Address                                         */

    struct {
      __IOM uint32_t DEVADDR    : 32;           /*!< [31..0] SPI Device address for automated DMA transactions (both
                                                     read and write).                                                          */
    } DMADEVADDR_b;
  } ;

  union {
    __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000110) DMA Total Transfer Count                                   */

    struct {
      __IOM uint32_t TOTCOUNT   : 24;           /*!< [23..0] Total Transfer Count in bytes.                                    */
            uint32_t            : 8;
    } DMATOTCOUNT_b;
  } ;

  union {
    __IOM uint32_t DMABCOUNT;                   /*!< (@ 0x00000114) DMA BYTE Transfer Count                                    */

    struct {
      __IOM uint32_t BCOUNT     : 8;            /*!< [7..0] Burst transfer size in bytes. This is the number of bytes
                                                     transferred when a FIFO trigger event occurs. Recommended
                                                     value is 32.                                                              */
            uint32_t            : 24;
    } DMABCOUNT_b;
  } ;

  union {
    __IOM uint32_t DMATHRESH;                   /*!< (@ 0x00000118) Indicates FIFO level at which a DMA should be
                                                                    triggered. For most configurations, a setting
                                                                    of 8 is recommended for both read and write
                                                                    operations.                                                */

    struct {
      __IOM uint32_t DMATXTHRESH : 5;           /*!< [4..0] DMA transfer FIFO level trigger. For read operations,
                                                     DMA is triggered when the FIFO level is greater than this
                                                     value. For write operations, DMA is triggered when the
                                                     FIFO level is less than this level. Each DMA operation
                                                     will consist of BCOUNT bytes.                                             */
            uint32_t            : 3;
      __IOM uint32_t DMARXTHRESH : 5;           /*!< [12..8] DMA transfer FIFO level trigger. For read operations,
                                                     DMA is triggered when the FIFO level is greater than this
                                                     value. For write operations, DMA is triggered when the
                                                     FIFO level is less than this level. Each DMA operation
                                                     will consist of BCOUNT bytes. This value should not be
                                                     set more than ALTRXFIFOFULL.                                              */
            uint32_t            : 19;
    } DMATHRESH_b;
  } ;
  __IM  uint32_t  RESERVED4[57];

  union {
    __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
                                                     layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
      __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
      __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
                                                     a full FIFO).                                                             */
      __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
                                                     an empty FIFO)                                                            */
      __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
                                                     MSPI bus pins will stall)                                                 */
      __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
      __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
      __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
      __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
      __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
                                                     performs an operation where address bit[0] is set. Useful
                                                     for triggering CURIDX interrupts.                                         */
      __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
      __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
      __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
                                                     be aligned to word (4-byte) start address.                                */
      __IOM uint32_t APBDMAERR  : 1;            /*!< [13..13] MSPI is dma target as well as dma source, which may
                                                     result in deadlock.                                                       */
            uint32_t            : 18;
    } INTEN_b;
  } ;

  union {
    __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
                                                     layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
      __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
      __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
                                                     a full FIFO).                                                             */
      __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
                                                     an empty FIFO)                                                            */
      __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
                                                     MSPI bus pins will stall)                                                 */
      __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
      __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
      __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
      __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
      __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
                                                     performs an operation where address bit[0] is set. Useful
                                                     for triggering CURIDX interrupts.                                         */
      __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
      __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
      __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
                                                     be aligned to word (4-byte) start address.                                */
      __IOM uint32_t APBDMAERR  : 1;            /*!< [13..13] MSPI is dma target as well as dma source, which may
                                                     result in deadlock.                                                       */
            uint32_t            : 18;
    } INTSTAT_b;
  } ;

  union {
    __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
                                                     layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
      __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
      __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
                                                     a full FIFO).                                                             */
      __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
                                                     an empty FIFO)                                                            */
      __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
                                                     MSPI bus pins will stall)                                                 */
      __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
      __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
      __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
      __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
      __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
                                                     performs an operation where address bit[0] is set. Useful
                                                     for triggering CURIDX interrupts.                                         */
      __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
      __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
      __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
                                                     be aligned to word (4-byte) start address.                                */
      __IOM uint32_t APBDMAERR  : 1;            /*!< [13..13] MSPI is dma target as well as dma source, which may
                                                     result in deadlock.                                                       */
            uint32_t            : 18;
    } INTCLR_b;
  } ;

  union {
    __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
                                                     layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
      __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
      __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
                                                     a full FIFO).                                                             */
      __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
                                                     an empty FIFO)                                                            */
      __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
                                                     MSPI bus pins will stall)                                                 */
      __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
      __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
      __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
      __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
      __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
                                                     performs an operation where address bit[0] is set. Useful
                                                     for triggering CURIDX interrupts.                                         */
      __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
      __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
      __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
                                                     be aligned to word (4-byte) start address.                                */
      __IOM uint32_t APBDMAERR  : 1;            /*!< [13..13] MSPI is dma target as well as dma source, which may
                                                     result in deadlock.                                                       */
            uint32_t            : 18;
    } INTSET_b;
  } ;
  __IM  uint32_t  RESERVED5[36];

  union {
    __IOM uint32_t CQCFG;                       /*!< (@ 0x000002A0) This register controls Command Queuing (CQ) operations
                                                                    in a manner similar to the DMACFG register.                */

    struct {
      __IOM uint32_t CQEN       : 1;            /*!< [0..0] Command queue enable. When set, will enable the processing
                                                     of the command queue                                                      */
      __IOM uint32_t CQPRI      : 1;            /*!< [1..1] Sets the Priority of the command queue DMA request                 */
      __IOM uint32_t CQPWROFF   : 1;            /*!< [2..2] Power off MSPI domain upon completion of DMA operation.            */
      __IOM uint32_t CQAUTOCLEARMASK : 1;       /*!< [3..3] Enable clear of CQMASK after each pause operation. This
                                                     may be useful when using software flags to pause CQ.                      */
      __IOM uint32_t CQPAUSEOP  : 1;            /*!< [4..4] CQPAUSEOP register description needed.                             */
            uint32_t            : 27;
    } CQCFG_b;
  } ;
  __IM  uint32_t  RESERVED6;

  union {
    __IOM uint32_t CQADDR;                      /*!< (@ 0x000002A8) Location of the command queue in SRAM or flash
                                                                    memory. This register will increment as
                                                                    CQ operations commence. Software should
                                                                    only write CQADDR when CQEN is disabled,
                                                                    however the command queue script itself
                                                                    may update CQADDR in order to perform queue
                                                                    management functions (like resetting the
                                                                    pointers)                                                  */

    struct {
      __IOM uint32_t CQADDR     : 29;           /*!< [28..0] Address of command queue buffer in SRAM or flash. The
                                                     buffer address must be aligned to a word boundary.                        */
            uint32_t            : 3;
    } CQADDR_b;
  } ;

  union {
    __IOM uint32_t CQSTAT;                      /*!< (@ 0x000002AC) Command Queue Status                                       */

    struct {
      __IOM uint32_t CQTIP      : 1;            /*!< [0..0] Command queue Transfer In Progress indicator. 1 will
                                                     indicate that a CQ transfer is active and this will remain
                                                     active even when paused waiting for external event.                       */
      __IOM uint32_t CQCPL      : 1;            /*!< [1..1] Command queue operation Complete. This signals the end
                                                     of the command queue operation.                                           */
      __IOM uint32_t CQERR      : 1;            /*!< [2..2] Command queue processing Error. This active high bit
                                                     signals that an error was encountered during the CQ operation.            */
      __IOM uint32_t CQPAUSED   : 1;            /*!< [3..3] Command queue is currently paused status.                          */
            uint32_t            : 28;
    } CQSTAT_b;
  } ;

  union {
    __IOM uint32_t CQFLAGS;                     /*!< (@ 0x000002B0) Command Queue Flags                                        */

    struct {
      __IOM uint32_t CQFLAGS    : 16;           /*!< [15..0] Current flag status (read-only). Bits [7:0] are software
                                                     controllable and bits [15:8] are hardware status.                         */
            uint32_t            : 16;
    } CQFLAGS_b;
  } ;

  union {
    __IOM uint32_t CQSETCLEAR;                  /*!< (@ 0x000002B4) Command Queue Flag Set/Clear                               */

    struct {
      __IOM uint32_t CQFSET     : 8;            /*!< [7..0] Set CQFlag status bits. Set has priority over clear if
                                                     both are high.                                                            */
      __IOM uint32_t CQFTOGGLE  : 8;            /*!< [15..8] Toggle CQFlag status bits                                         */
      __IOM uint32_t CQFCLR     : 8;            /*!< [23..16] Clear CQFlag status bits.                                        */
            uint32_t            : 8;
    } CQSETCLEAR_b;
  } ;

  union {
    __IOM uint32_t CQPAUSE;                     /*!< (@ 0x000002B8) Command Queue Pause Mask                                   */

    struct {
      __IOM uint32_t CQMASK     : 16;           /*!< [15..0] CQ will pause processing when ALL specified events are
                                                     satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK.                      */
            uint32_t            : 16;
    } CQPAUSE_b;
  } ;
  __IM  uint32_t  RESERVED7;

  union {
    __IOM uint32_t CQCURIDX;                    /*!< (@ 0x000002C0) This register can be used in conjunction with
                                                                    the CQENDIDX register to manage the command
                                                                    queue. Typically software will initialize
                                                                    the CQCURIDX and CQENDIDX to the same value,
                                                                    which will cause the CQ to be paused when
                                                                    enabled. Software may then add entries to
                                                                    the command queue (in SRAM) and update CQENDIDX.
                                                                    The command queue operations will then increment
                                                                    CQCURIDX as it processes operations. Once
                                                                    CQCURIDX==CQENDIDX, the command queue hardware
                                                                    will automatically pause since no additional
                                                                    ope                                                        */

    struct {
      __IOM uint32_t CQCURIDX   : 8;            /*!< [7..0] Can be used to indicate the current position of the command
                                                     queue by having CQ operations write this field. A CQ hardware
                                                     status flag indicates when CURIDX and ENDIDX are not equal,
                                                     allowing SW to pause the CQ processing until the end index
                                                     is updated.                                                               */
            uint32_t            : 24;
    } CQCURIDX_b;
  } ;

  union {
    __IOM uint32_t CQENDIDX;                    /*!< (@ 0x000002C4) Command Queue End Index                                    */

    struct {
      __IOM uint32_t CQENDIDX   : 8;            /*!< [7..0] Can be used to indicate the end position of the command
                                                     queue. A CQ hardware status bit indices when CURIDX !=
                                                     ENDIDX so that the CQ can be paused when it reaches the
                                                     end pointer.                                                              */
            uint32_t            : 24;
    } CQENDIDX_b;
  } ;
  __IM  uint32_t  RESERVED8[18];

  union {
    __IOM uint32_t STATXIPDMA;                  /*!< (@ 0x00000310) Debug XIP DMA State                                        */

    struct {
      __IOM uint32_t FLD32      : 32;           /*!< [31..0] XIP/DMA module debug                                              */
    } STATXIPDMA_b;
  } ;
} MSPI0_Type;                                   /*!< Size = 788 (0x314)                                                        */



/* =========================================================================================================================== */
/* ================                                           PDM0                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief PDM Audio (PDM0)
  */

typedef struct {                                /*!< (@ 0x40201000) PDM0 Structure                                             */

  union {
    __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) PDM Control                                                */

    struct {
      __IOM uint32_t CLKEN      : 1;            /*!< [0..0] PDM Clock enable.If multiple clocks are enabled, priority
                                                     is HFRC2, HF XTAL, HFRC.                                                  */
      __IOM uint32_t CLKSEL     : 2;            /*!< [2..1] PDM Master Clock select (24.576MHz).0: HFRC2_192MHz div8
                                                     with HFAdj21: XTAL_HS Byapss2: HFRC_96MHz div4                            */
            uint32_t            : 1;
      __IOM uint32_t RSTB       : 1;            /*!< [4..4] Reset IP core. 0 puts the core in reset; 1 takes the
                                                     core out of reset.                                                        */
      __IOM uint32_t PCMPACK    : 1;            /*!< [5..5] Enable PCM packing. Only 24-bit unpacked mode supported.           */
      __IOM uint32_t EN         : 1;            /*!< [6..6] PDM enable register                                                */
            uint32_t            : 25;
    } CTRL_b;
  } ;

  union {
    __IOM uint32_t CORECFG0;                    /*!< (@ 0x00000004) PDM to PCM Core Configuration                              */

    struct {
      __IOM uint32_t LRSWAP     : 1;            /*!< [0..0] Left/Right channel swap when = 1                                   */
      __IOM uint32_t SOFTMUTE   : 1;            /*!< [1..1] Soft mute enable when = 1                                          */
      __IOM uint32_t SCYCLES    : 3;            /*!< [4..2] Set number of PDMA_CKO cycles during gain setting changes
                                                     or soft mute                                                              */
      __IOM uint32_t HPGAIN     : 4;            /*!< [8..5] Adjust High Pass filter coefficients                               */
      __IOM uint32_t ADCHPD     : 1;            /*!< [9..9] Disable high pass filter when = 1                                  */
      __IOM uint32_t MCLKDIV    : 4;            /*!< [13..10] PDMA_CKO frequency divisor.MCLKDIV > 0. MCLKDIV = 0
                                                     PROHIBITED.MCLKDIV = (PDM_CLK /Fsin / (DIVMCLKQ + 1)) -1                  */
      __IOM uint32_t SINCRATE   : 7;            /*!< [20..14] Sinc decimation rate.SINC_RATE = OSR /2. OSR = Fsin
                                                     / Fsout.Must be even.16 to 64 allowed.96 allowed for special
                                                     configuration.                                                            */
      __IOM uint32_t PGAL       : 5;            /*!< [25..21] Left Channel PGA Gain: +1.5dB/step, -12dB ~ +34.5dB;enum
                                                     name = M12_0DB value = 0x0 desc = Left channel PGA gain
                                                     = -12.0 dB                                                                */
      __IOM uint32_t PGAR       : 5;            /*!< [30..26] Right Channel PGA Gain:+1.5dB/step, -12dB ~ +34.5dB;             */
            uint32_t            : 1;
    } CORECFG0_b;
  } ;

  union {
    __IOM uint32_t CORECFG1;                    /*!< (@ 0x00000008) PDM to PCM Extra Configuration                             */

    struct {
      __IOM uint32_t PCMCHSET   : 2;            /*!< [1..0] PCM output chanel 0xsetting                                        */
      __IOM uint32_t DIVMCLKQ   : 2;            /*!< [3..2] Divide down ratio for generating internal master MCLKQ.DIVMCLKQ
                                                     > 0. DIVMCLKQ = 0 PROHIBITED.Recommend value of 1.Fmclkq
                                                     = Fpdmclk/(DIVMCLKQ+1).                                                   */
      __IOM uint32_t CKODLY     : 3;            /*!< [6..4] PDMA_CKO clock phase delay in terms of PDMCLK period
                                                     to internal sampler                                                       */
      __IOM uint32_t SELSTEP    : 1;            /*!< [7..7] Fine grain step size for smooth PGA or Softmute attenuation
                                                     transition0: 0.13dB1: 0.26dB                                              */
            uint32_t            : 24;
    } CORECFG1_b;
  } ;

  union {
    __IOM uint32_t CORECTRL;                    /*!< (@ 0x0000000C) PDM to PCM Control                                         */

    struct {
      __IOM uint32_t CORECTRL   : 32;           /*!< [31..0] Overall control of PDM core. Internal use only                    */
    } CORECTRL_b;
  } ;

  union {
    __IOM uint32_t FIFOCNT;                     /*!< (@ 0x00000010) FIFO count                                                 */

    struct {
      __IOM uint32_t FIFOCNT    : 6;            /*!< [5..0] Valid 32-bit entries currently in the FIFO.                        */
            uint32_t            : 26;
    } FIFOCNT_b;
  } ;

  union {
    __IOM uint32_t FIFOREAD;                    /*!< (@ 0x00000014) FIFO Read                                                  */

    struct {
      __IOM uint32_t FIFOREAD   : 32;           /*!< [31..0] FIFO read data.                                                   */
    } FIFOREAD_b;
  } ;

  union {
    __IOM uint32_t FIFOFLUSH;                   /*!< (@ 0x00000018) FIFO Flush                                                 */

    struct {
      __IOM uint32_t FIFOFLUSH  : 1;            /*!< [0..0] FIFO FLUSH.                                                        */
            uint32_t            : 31;
    } FIFOFLUSH_b;
  } ;

  union {
    __IOM uint32_t FIFOTHR;                     /*!< (@ 0x0000001C) FIFO Threshold                                             */

    struct {
      __IOM uint32_t FIFOTHR    : 5;            /*!< [4..0] FIFO Threshold value. When the FIFO count is equal to,
                                                     or larger than this value (in words), a THR interrupt is
                                                     generated (if enabled). If used for DMA purposes then only
                                                     supported values are 0x4, 0x8, 0xc, 0x10, 0x14, 0x18 and
                                                     0x1C.                                                                     */
            uint32_t            : 27;
    } FIFOTHR_b;
  } ;
  __IM  uint32_t  RESERVED[56];

  union {
    __IOM uint32_t INTEN;                       /*!< (@ 0x00000100) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
      __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
      __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
      __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
      __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error receieved                                                */
            uint32_t            : 27;
    } INTEN_b;
  } ;

  union {
    __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000104) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
      __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
      __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
      __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
      __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error receieved                                                */
            uint32_t            : 27;
    } INTSTAT_b;
  } ;

  union {
    __IOM uint32_t INTCLR;                      /*!< (@ 0x00000108) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
      __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
      __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
      __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
      __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error receieved                                                */
            uint32_t            : 27;
    } INTCLR_b;
  } ;

  union {
    __IOM uint32_t INTSET;                      /*!< (@ 0x0000010C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
      __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
      __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
      __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
      __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error receieved                                                */
            uint32_t            : 27;
    } INTSET_b;
  } ;
  __IM  uint32_t  RESERVED1[12];

  union {
    __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000140) DMA Trigger Enable                                         */

    struct {
      __IOM uint32_t DTHR       : 1;            /*!< [0..0] Trigger DMA upon when FIFO iss filled to level indicated
                                                     by the FIFO THRESHOLD,at granularity of 16 bytes only                     */
      __IOM uint32_t DTHR90     : 1;            /*!< [1..1] Trigger DMA at FIFO 90 percent full. This signal is also
                                                     used internally for AUTOHIP function                                      */
            uint32_t            : 30;
    } DMATRIGEN_b;
  } ;

  union {
    __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000144) DMA Trigger Status                                         */

    struct {
      __IOM uint32_t DTHRSTAT   : 1;            /*!< [0..0] Triggered DMA from FIFO reaching threshold                         */
      __IOM uint32_t DTHR90STAT : 1;            /*!< [1..1] Triggered DMA from FIFO reaching 90 percent full                   */
            uint32_t            : 30;
    } DMATRIGSTAT_b;
  } ;

  union {
    __IOM uint32_t DMACFG;                      /*!< (@ 0x00000148) DMA Configuration                                          */

    struct {
      __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable                                                         */
            uint32_t            : 1;
      __IOM uint32_t DMADIR     : 1;            /*!< [2..2] Direction                                                          */
            uint32_t            : 5;
      __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
      __IOM uint32_t DAUTOHIP   : 1;            /*!< [9..9] Raise priority to high on fifo full, and DMAPRI set to
                                                     low                                                                       */
      __IOM uint32_t DPWROFF    : 1;            /*!< [10..10] Power Off the ADC System upon DMACPL.                            */
            uint32_t            : 21;
    } DMACFG_b;
  } ;
  __IM  uint32_t  RESERVED2[2];

  union {
    __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x00000154) DMA Target Address                                         */

    struct {
      __IOM uint32_t LTARGADDR  : 28;           /*!< [27..0] DMA Target Address. This register is not updated with
                                                     the current address of the DMA, but will remain static
                                                     with the original address during the DMA transfer.                        */
      __IOM uint32_t UTARGADDR  : 4;            /*!< [31..28] SRAM Target                                                      */
    } DMATARGADDR_b;
  } ;

  union {
    __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000158) DMA Status                                                 */

    struct {
      __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress                                           */
      __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete                                              */
      __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error                                                          */
            uint32_t            : 29;
    } DMASTAT_b;
  } ;
  __IM  uint32_t  RESERVED3[61];

  union {
    __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000250) DMA Total Transfer Count                                   */

    struct {
      __IOM uint32_t TOTCOUNT   : 20;           /*!< [19..0] Total Transfer Count. The transfer count must be a multiple
                                                     of the THR setting to avoid DMA overruns.                                 */
            uint32_t            : 12;
    } DMATOTCOUNT_b;
  } ;
} PDM0_Type;                                    /*!< Size = 596 (0x254)                                                        */



/* =========================================================================================================================== */
/* ================                                          PWRCTRL                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief PWR Controller Register Bank (PWRCTRL)
  */

typedef struct {                                /*!< (@ 0x40021000) PWRCTRL Structure                                          */

  union {
    __IOM uint32_t MCUPERFREQ;                  /*!< (@ 0x00000000) This register provides the performance mode knobs
                                                                    for MCU. S/w should write the *PERFREQ field
                                                                    to desired mode and wait for the *PERFACK
                                                                    and check for the *PERFSTATUS. Some times
                                                                    system may not allow certain modes but *PERFACK
                                                                    should always follow *PERFREQ change.                      */

    struct {
      __IOM uint32_t MCUPERFREQ : 2;            /*!< [1..0] MCU Performance mode request                                       */
      __IOM uint32_t MCUPERFACK : 1;            /*!< [2..2] Indicates the MCU performance status indicated in STATUS
                                                     register is valid.                                                        */
      __IOM uint32_t MCUPERFSTATUS : 2;         /*!< [4..3] MCU Performance mode request                                       */
            uint32_t            : 27;
    } MCUPERFREQ_b;
  } ;

  union {
    __IOM uint32_t DEVPWREN;                    /*!< (@ 0x00000004) This enables various peripherals power domains.            */

    struct {
      __IOM uint32_t PWRENIOS   : 1;            /*!< [0..0] Power up IO Slave                                                  */
      __IOM uint32_t PWRENIOM0  : 1;            /*!< [1..1] Power up IO Master 0                                               */
      __IOM uint32_t PWRENIOM1  : 1;            /*!< [2..2] Power up IO Master 1                                               */
      __IOM uint32_t PWRENIOM2  : 1;            /*!< [3..3] Power up IO Master 2                                               */
      __IOM uint32_t PWRENIOM3  : 1;            /*!< [4..4] Power up IO Master 3                                               */
      __IOM uint32_t PWRENIOM4  : 1;            /*!< [5..5] Power up IO Master 4                                               */
      __IOM uint32_t PWRENIOM5  : 1;            /*!< [6..6] Power up IO Master 5                                               */
      __IOM uint32_t PWRENIOM6  : 1;            /*!< [7..7] Power up IO Master 6                                               */
      __IOM uint32_t PWRENIOM7  : 1;            /*!< [8..8] Power up IO Master 7                                               */
      __IOM uint32_t PWRENUART0 : 1;            /*!< [9..9] Power up UART Controller 0                                         */
      __IOM uint32_t PWRENUART1 : 1;            /*!< [10..10] Power up UART Controller 1                                       */
      __IOM uint32_t PWRENUART2 : 1;            /*!< [11..11] Power up UART Controller 2                                       */
      __IOM uint32_t PWRENUART3 : 1;            /*!< [12..12] Power up UART Controller 3                                       */
      __IOM uint32_t PWRENADC   : 1;            /*!< [13..13] Power up ADC Digital Controller                                  */
      __IOM uint32_t PWRENMSPI0 : 1;            /*!< [14..14] Power up MSPI Controller0                                        */
      __IOM uint32_t PWRENMSPI1 : 1;            /*!< [15..15] Power up MSPI Controller1                                        */
      __IOM uint32_t PWRENMSPI2 : 1;            /*!< [16..16] Power up MSPI Controller2                                        */
      __IOM uint32_t PWRENGFX   : 1;            /*!< [17..17] Power up GFX controller                                          */
            uint32_t            : 2;
      __IOM uint32_t PWRENCRYPTO : 1;           /*!< [20..20] Power up CRYPTO module                                           */
      __IOM uint32_t PWRENSDIO  : 1;            /*!< [21..21] Power up SDIO controller                                         */
            uint32_t            : 2;
      __IOM uint32_t PWRENDBG   : 1;            /*!< [24..24] Powerup DBG power domain                                         */
            uint32_t            : 7;
    } DEVPWREN_b;
  } ;

  union {
    __IOM uint32_t DEVPWRSTATUS;                /*!< (@ 0x00000008) This provides the power status for the peripheral
                                                                    device domains controlled through DEVPWREN
                                                                    register. Value of 1 means the device is
                                                                    powred up and ready to be used and 0 means
                                                                    its not powered up.                                        */

    struct {
      __IOM uint32_t PWRSTIOS   : 1;            /*!< [0..0] Power status IO Slave                                              */
      __IOM uint32_t PWRSTIOM0  : 1;            /*!< [1..1] Power status IO Master 0                                           */
      __IOM uint32_t PWRSTIOM1  : 1;            /*!< [2..2] Power status IO Master 1                                           */
      __IOM uint32_t PWRSTIOM2  : 1;            /*!< [3..3] Power status IO Master 2                                           */
      __IOM uint32_t PWRSTIOM3  : 1;            /*!< [4..4] Power status IO Master 3                                           */
      __IOM uint32_t PWRSTIOM4  : 1;            /*!< [5..5] Power status IO Master 4                                           */
      __IOM uint32_t PWRSTIOM5  : 1;            /*!< [6..6] Power Status IO Master 5                                           */
      __IOM uint32_t PWRSTIOM6  : 1;            /*!< [7..7] Power Status IO Master 6                                           */
      __IOM uint32_t PWRSTIOM7  : 1;            /*!< [8..8] Power Status IO Master 7                                           */
      __IOM uint32_t PWRSTUART0 : 1;            /*!< [9..9] Power Status UART Controller 0                                     */
      __IOM uint32_t PWRSTUART1 : 1;            /*!< [10..10] Power Status UART Controller 1                                   */
      __IOM uint32_t PWRSTUART2 : 1;            /*!< [11..11] Power Status UART Controller 2                                   */
      __IOM uint32_t PWRSTUART3 : 1;            /*!< [12..12] Power Status UART Controller 3                                   */
      __IOM uint32_t PWRSTADC   : 1;            /*!< [13..13] Power Status ADC Digital Controller                              */
      __IOM uint32_t PWRSTMSPI0 : 1;            /*!< [14..14] Power Status MSPI Controller0                                    */
      __IOM uint32_t PWRSTMSPI1 : 1;            /*!< [15..15] Power Status MSPI Controller1                                    */
      __IOM uint32_t PWRSTMSPI2 : 1;            /*!< [16..16] Power Status MSPI Controller2                                    */
      __IOM uint32_t PWRSTGFX   : 1;            /*!< [17..17] Power Status GFX controller                                      */
            uint32_t            : 2;
      __IOM uint32_t PWRSTCRYPTO : 1;           /*!< [20..20] Power Status CRYPTO module                                       */
      __IOM uint32_t PWRSTSDIO  : 1;            /*!< [21..21] Power Status SDIO controller                                     */
            uint32_t            : 2;
      __IOM uint32_t PWRSTDBG   : 1;            /*!< [24..24] Power Status DBG subsystem                                       */
            uint32_t            : 7;
    } DEVPWRSTATUS_b;
  } ;

  union {
    __IOM uint32_t AUDSSPWREN;                  /*!< (@ 0x0000000C) This enables various power domains in audio subsystem.     */

    struct {
      __IOM uint32_t PWRENAUDREC : 1;           /*!< [0..0] Power up Audio Record                                              */
      __IOM uint32_t PWRENAUDPB : 1;            /*!< [1..1] Power up Audio Playback                                            */
      __IOM uint32_t PWRENPDM0  : 1;            /*!< [2..2] Power up audio subsystem PDM0 domain                               */
            uint32_t            : 3;
      __IOM uint32_t PWRENI2S0  : 1;            /*!< [6..6] Power up audio subsystem I2S0 domain                               */
      __IOM uint32_t PWRENI2S1  : 1;            /*!< [7..7] Power up audio subsystem legacy I2S1 domain. I2S1 domain
                                                     must be disabled. I2S1 is not available in Apoll4L.                       */
            uint32_t            : 24;
    } AUDSSPWREN_b;
  } ;

  union {
    __IOM uint32_t AUDSSPWRSTATUS;              /*!< (@ 0x00000010) This provides the power status for the peripheral
                                                                    domains controlled through AUDSSPWREN register.
                                                                    Value of 1 means the device is powred up
                                                                    and ready to be used and 0 means its not
                                                                    powered up.                                                */

    struct {
      __IOM uint32_t PWRSTAUDREC : 1;           /*!< [0..0] Power Status Audio Record block                                    */
      __IOM uint32_t PWRSTAUDPB : 1;            /*!< [1..1] Power Status Audio Playback block                                  */
      __IOM uint32_t PWRSTPDM0  : 1;            /*!< [2..2] Power Status audio subsystem PDM0 domain                           */
            uint32_t            : 3;
      __IOM uint32_t PWRSTI2S0  : 1;            /*!< [6..6] Power Status audio subsystem I2S0 domain                           */
      __IOM uint32_t PWRSTI2S1  : 1;            /*!< [7..7] Power Status audio subsystem legacy I2S1 domain. I2S1
                                                     is not available in Apoll4L.                                              */
            uint32_t            : 24;
    } AUDSSPWRSTATUS_b;
  } ;

  union {
    __IOM uint32_t MEMPWREN;                    /*!< (@ 0x00000014) This register enables the individual banks for
                                                                    the memories. When set, power will be enabled
                                                                    to the banks. This register works in conjunction
                                                                    with the MEMRETCFG register. If this register
                                                                    is not set, then power will always be disabled
                                                                    to the memory bank.                                        */

    struct {
      __IOM uint32_t PWRENDTCM  : 3;            /*!< [2..0] Power up DTCM                                                      */
      __IOM uint32_t PWRENNVM0  : 1;            /*!< [3..3] Power up NVM0                                                      */
      __IOM uint32_t PWRENCACHEB0 : 1;          /*!< [4..4] Power up Cache Bank 0. This works in conjunction with
                                                     Cache enable from flash_cache module. To power up cache
                                                     bank0, cache has to be enabled and this bit has to be set.                */
      __IOM uint32_t PWRENCACHEB2 : 1;          /*!< [5..5] Power up Cache Bank 2. This works in conjunction with
                                                     Cache enable from flash_cache module. To power up cache
                                                     bank2, cache has to be enabled and this bit has to be set.                */
            uint32_t            : 26;
    } MEMPWREN_b;
  } ;

  union {
    __IOM uint32_t MEMPWRSTATUS;                /*!< (@ 0x00000018) It provides the power status for all the memory
                                                                    banks including- caches, nvm (0 and 1) and
                                                                    all the SRAM groups. The status here should
                                                                    reflect the enable provided by the MEMPWREN
                                                                    register. There may be a lag time between
                                                                    setting the bits in MEMPWREN register and
                                                                    MEMPWRSTATUS register, due to the need to
                                                                    cycle the power gate and isolation seqeunces
                                                                    to the memory banks.                                       */

    struct {
      __IOM uint32_t PWRSTDTCM  : 3;            /*!< [2..0] Power status for DTCM. Each bit corresponds to one of
                                                     the TCMs. bit0=DTCM0_0, bit1=DTCM0_1, bit2=DTCM1.                         */
      __IOM uint32_t PWRSTNVM0  : 1;            /*!< [3..3] This bit is 1 if power is supplied to NVM 0                        */
      __IOM uint32_t PWRSTCACHEB0 : 1;          /*!< [4..4] This bit is 1 if power is supplied to Cache Bank 0                 */
      __IOM uint32_t PWRSTCACHEB2 : 1;          /*!< [5..5] This bit is 1 if power is supplied to Cache Bank 2                 */
            uint32_t            : 26;
    } MEMPWRSTATUS_b;
  } ;

  union {
    __IOM uint32_t MEMRETCFG;                   /*!< (@ 0x0000001C) This controls the power down of the SRAM banks
                                                                    in deep sleep mode. If this is set, then
                                                                    the power for that SRAM bank will be gated
                                                                    when the core goes into deep sleep. Upon
                                                                    wake, the data within the SRAMs will be
                                                                    erased. If this is not set, retention voltage
                                                                    will be applied to the SRAM bank when the
                                                                    core goes into deep sleep. Upon wake, the
                                                                    data within the SRAMs are retained. Do not
                                                                    set this if the SRAM bank is used as the
                                                                    target for DMA transfer while CPU in deepsleep.            */

    struct {
      __IOM uint32_t DTCMPWDSLP : 3;            /*!< [2..0] power down DTCM in deep sleep                                      */
      __IOM uint32_t NVM0PWDSLP : 1;            /*!< [3..3] Powerdown NVM0 in deep sleep                                       */
      __IOM uint32_t CACHEPWDSLP : 1;           /*!< [4..4] power down cache in deep sleep                                     */
            uint32_t            : 27;
    } MEMRETCFG_b;
  } ;

  union {
    __IOM uint32_t SYSPWRSTATUS;                /*!< (@ 0x00000020) Power ON Status for domains that are not part
                                                                    of devpwrstatus or mempwrstatus                            */

    struct {
      __IOM uint32_t PWRSTMCUL  : 1;            /*!< [0..0] Power Domain status for MCUL                                       */
      __IOM uint32_t PWRSTMCUH  : 1;            /*!< [1..1] Power Domain status for MCUH                                       */
      __IOM uint32_t PWRSTDSP0H : 1;            /*!< [2..2] Power Domain status for DSP0H                                      */
      __IOM uint32_t PWRSTDSP1H : 1;            /*!< [3..3] Power Domain status for DSP1H                                      */
            uint32_t            : 25;
      __IOM uint32_t CORESLEEP  : 1;            /*!< [29..29] Indicates MCU entered SLEEP state since it was last
                                                     cleared. Write 1 to to clear it.                                          */
      __IOM uint32_t COREDEEPSLEEP : 1;         /*!< [30..30] Indicates MCU entered DEEPSLEEP state since it was
                                                     last cleared. Write 1 to to clear it.                                     */
      __IOM uint32_t SYSDEEPSLEEP : 1;          /*!< [31..31] Indicates all device domains powered down and MCU entered
                                                     DEEPSLEEP state since it was last cleared. Write 1 to to
                                                     clear it.                                                                 */
    } SYSPWRSTATUS_b;
  } ;

  union {
    __IOM uint32_t SSRAMPWREN;                  /*!< (@ 0x00000024) This register enables the individual banks for
                                                                    the memories. When set, power will be enabled
                                                                    to the banks. This register works in conjunction
                                                                    with the SSRAMRETCFG register. If this register
                                                                    is not set, then power will always be disabled
                                                                    to the memory bank.                                        */

    struct {
      __IOM uint32_t PWRENSSRAM : 2;            /*!< [1..0] Power up SRAM groups                                               */
            uint32_t            : 30;
    } SSRAMPWREN_b;
  } ;

  union {
    __IOM uint32_t SSRAMPWRST;                  /*!< (@ 0x00000028) It provides the power status for shared sram
                                                                    banks. The status here should reflect the
                                                                    enable provided by the SSRAMPWREN register.                */

    struct {
      __IOM uint32_t SSRAMPWRST : 2;            /*!< [1..0] Each bit corresponds to one 1M SSRAM group. Power Status-
                                                     1:ON, 0:OFF See SSRAMPWREN PWRENSSRAM for bit mapping.
                                                     For example, a value of 2 in this field would mean that
                                                     SSRAM1 is powered up and SSRAM0 is powered down.                          */
            uint32_t            : 30;
    } SSRAMPWRST_b;
  } ;

  union {
    __IOM uint32_t SSRAMRETCFG;                 /*!< (@ 0x0000002C) This controls the power down of the Shared SRAM
                                                                    banks in deep sleep mode. If this is set,
                                                                    then the power for that SRAM bank will be
                                                                    gated when the core goes into deep sleep.
                                                                    Upon wake, the data within the SRAMs will
                                                                    be erased. If this is not set, retention
                                                                    voltage will be applied to the SRAM bank
                                                                    when none of the CPU agents are in powered
                                                                    up and active mode. Do not set this if the
                                                                    SRAM bank is used as the target for DMA
                                                                    transfer while CPU in deepsleep.                           */

    struct {
      __IOM uint32_t SSRAMPWDSLP : 2;           /*!< [1..0] Selects which shared SRAM banks are powered down in deep
                                                     sleep mode, causing the contents of the bank to be lost.                  */
      __IOM uint32_t SSRAMACTMCU : 2;           /*!< [3..2] Keep the memory domain active based on MCU state. Each
                                                     bit corresponds to a domain. 1: Keep SRAM active 0: Wakeup
                                                     on demand (i.e. when MCU is powered up)                                   */
      __IOM uint32_t SSRAMACTDSP : 2;           /*!< [5..4] Keep the memory domain active based on DSP state. Each
                                                     bit corresponds to a domain. 1: Keep SRAM active 0: Powerup
                                                     on demand (i.e. when DSP is powered up)                                   */
      __IOM uint32_t SSRAMACTGFX : 2;           /*!< [7..6] Keep the memory domain active based on GFX state. Each
                                                     bit corresponds to a domain. 1: Keep SRAM active 0: Powerup
                                                     on demand (i.e. when GFX is powered up)                                   */
      __IOM uint32_t SSRAMACTDISP : 2;          /*!< [9..8] Keep the memory domain active based on DISP state. Each
                                                     bit corresponds to a domain. 1: Keep SRAM active 0: Powerup
                                                     on demand (i.e. when DISP is powered up)                                  */
            uint32_t            : 22;
    } SSRAMRETCFG_b;
  } ;

  union {
    __IOM uint32_t DEVPWREVENTEN;               /*!< (@ 0x00000030) This register controls which feature trigger
                                                                    will result in an event to the CPU. It includes
                                                                    all the power on status for the core domains.
                                                                    If any bits are set, then if the domain
                                                                    is turned on, it will result in an event
                                                                    to the ARM core.                                           */

    struct {
      __IOM uint32_t MCULEVEN   : 1;            /*!< [0..0] Control MCUL power-on status event                                 */
      __IOM uint32_t MCUHEVEN   : 1;            /*!< [1..1] Control MCUH power-on status event                                 */
      __IOM uint32_t HCPAEVEN   : 1;            /*!< [2..2] Control HCPA power-on status event                                 */
      __IOM uint32_t HCPBEVEN   : 1;            /*!< [3..3] Control HCPB power-on status event                                 */
      __IOM uint32_t HCPCEVEN   : 1;            /*!< [4..4] Control HCPC power-on status event                                 */
      __IOM uint32_t ADCEVEN    : 1;            /*!< [5..5] Control ADC power-on status event                                  */
      __IOM uint32_t MSPIEVEN   : 1;            /*!< [6..6] Control MSPI power-on status event                                 */
      __IOM uint32_t AUDEVEN    : 1;            /*!< [7..7] Control AUD power-on status event                                  */
            uint32_t            : 24;
    } DEVPWREVENTEN_b;
  } ;

  union {
    __IOM uint32_t MEMPWREVENTEN;               /*!< (@ 0x00000034) This register controls which power enable for
                                                                    the memories will result in an event to
                                                                    the CPU. It includes all the power on status
                                                                    for the memory domains. If any bits are
                                                                    set, then if the domain is turned on, it
                                                                    will result in an event to the ARM core.                   */

    struct {
      __IOM uint32_t DTCMEN     : 3;            /*!< [2..0] Enable DTCM power-on status event                                  */
      __IOM uint32_t NVM0EN     : 1;            /*!< [3..3] Control NVM power-on status event                                  */
      __IOM uint32_t CACHEB0EN  : 1;            /*!< [4..4] Control CACHE BANK 0 power-on status event                         */
      __IOM uint32_t CACHEB2EN  : 1;            /*!< [5..5] Control CACHEB2 power-on status event                              */
            uint32_t            : 26;
    } MEMPWREVENTEN_b;
  } ;
  __IM  uint32_t  RESERVED[2];

  union {
    __IOM uint32_t MMSOVERRIDE;                 /*!< (@ 0x00000040) Power domain behavior overrides related to MMS
                                                                    ( Multimedia System ).                                     */

    struct {
      __IOM uint32_t MMSOVRMCULDISP : 1;        /*!< [0..0] MMS override for MCUL on by PD_DISP setting.                       */
      __IOM uint32_t MMSOVRMCULGFX : 1;         /*!< [1..1] MMS override for MCUL on by PD_GFX setting.                        */
      __IOM uint32_t MMSOVRSSRAMDISP : 1;       /*!< [2..2] MMS override for SSRAM power state by PD_DISP power setting.       */
      __IOM uint32_t MMSOVRSSRAMGFX : 1;        /*!< [3..3] MMS override for SSRAM power state by PD_GFX power setting.        */
      __IOM uint32_t MMSOVRDSPRAMRETDISP : 2;   /*!< [5..4] If set, retention equation doesn't consider DISP. Each
                                                     bit corresponds to a domain.                                              */
      __IOM uint32_t MMSOVRDSPRAMRETGFX : 2;    /*!< [7..6] If set, retention equation doesn't consider GFX. Each
                                                     bit corresponds to a domain.                                              */
      __IOM uint32_t MMSOVRSSRAMRETDISP : 2;    /*!< [9..8] If set, retention equation doesn't consider DISP. Each
                                                     bit corresponds to a domain.                                              */
      __IOM uint32_t MMSOVRSSRAMRETGFX : 2;     /*!< [11..10] If set, retention equation doesn't consider GFX. Each
                                                     bit corresponds to a domain.                                              */
            uint32_t            : 20;
    } MMSOVERRIDE_b;
  } ;
  __IM  uint32_t  RESERVED1[3];

  union {
    __IOM uint32_t DSP0PWRCTRL;                 /*!< (@ 0x00000050) Power and RST controls for DSP0                            */

    struct {
      __IOM uint32_t DSP0PCMRSTDLY : 4;         /*!< [3..0] PCM Reset delay in number of 24MHz clocks.                         */
      __IOM uint32_t DSP0PCMRSTOR : 1;          /*!< [4..4] PCM Reset override. If this is disabled, then h/w will
                                                     handle the de-assertion of pcm reset.                                     */
            uint32_t            : 27;
    } DSP0PWRCTRL_b;
  } ;

  union {
    __IOM uint32_t DSP0PERFREQ;                 /*!< (@ 0x00000054) This register provides the performance mode knobs
                                                                    for DSP0. S/w should write the *PERFREQ
                                                                    field to desired mode and wait for the *PERFACK
                                                                    and check for the *PERFSTATUS. Some times
                                                                    system may not allow certain modes but *PERFACK
                                                                    should always follow *PERFREQ change.                      */

    struct {
      __IOM uint32_t DSP0PERFREQ : 2;           /*!< [1..0] DSP0 Performance mode request                                      */
      __IOM uint32_t DSP0PERFACK : 1;           /*!< [2..2] Indicates the DSP0 performance status indicated in STATUS
                                                     register is valid.                                                        */
      __IOM uint32_t DSP0PERFSTATUS : 2;        /*!< [4..3] DSP0 Performance mode request                                      */
            uint32_t            : 27;
    } DSP0PERFREQ_b;
  } ;

  union {
    __IOM uint32_t DSP0MEMPWREN;                /*!< (@ 0x00000058) This register enables the individual banks for
                                                                    the memories. When set, power will be enabled
                                                                    to the banks. This register works in conjunction
                                                                    with the DSP0MEMRETCFG register when DSP0
                                                                    is OFF.                                                    */

    struct {
      __IOM uint32_t PWRENDSP0RAM : 1;          /*!< [0..0] Power up DSP0 IRAM and DRAM                                        */
      __IOM uint32_t PWRENDSP0ICACHE : 1;       /*!< [1..1] Power up DSP0 ICACHE banks                                         */
            uint32_t            : 30;
    } DSP0MEMPWREN_b;
  } ;

  union {
    __IOM uint32_t DSP0MEMPWRST;                /*!< (@ 0x0000005C) It provides the power status for all the memories
                                                                    of DSP0 subsystem                                          */

    struct {
      __IOM uint32_t PWRSTDSP0RAM : 1;          /*!< [0..0] Status- 1:ON, 0:OFF                                                */
      __IOM uint32_t PWRSTDSP0ICACHE : 1;       /*!< [1..1] Power Status- 1:ON, 0:OFF                                          */
            uint32_t            : 30;
    } DSP0MEMPWRST_b;
  } ;

  union {
    __IOM uint32_t DSP0MEMRETCFG;               /*!< (@ 0x00000060) This controls the power down of the DRAM/IRAM/CACHE
                                                                    banks when DSP0 is powered off. If this
                                                                    is set, then the power for that corresponding
                                                                    SRAM bank will be gated when the DSP0 is
                                                                    powered off and data is erased. If this
                                                                    is not set, retention voltage will be applied
                                                                    when DSP0 is powered off. Do not set this
                                                                    if the SRAM bank is used as the target for
                                                                    DMA transfer while DSP0 is powered off.                    */

    struct {
      __IOM uint32_t RAMPWDDSP0OFF : 1;         /*!< [0..0] IRAM/DRAM banks are powered down when DSP0 is switched
                                                     off, causing the contents of the bank to be lost.                         */
      __IOM uint32_t DSP0RAMACTMCU : 1;         /*!< [1..1] Keep the memory domain active based on MCU state.                  */
      __IOM uint32_t ICACHEPWDDSP0OFF : 1;      /*!< [2..2] ICACHE is powered down when DSP0 is switched off, causing
                                                     the contents of the bank to be lost.                                      */
      __IOM uint32_t DSP0RAMACTDISP : 1;        /*!< [3..3] Keep the memory domain active based on DISP state.                 */
      __IOM uint32_t DSP0RAMACTGFX : 1;         /*!< [4..4] Keep the memory domain active based on GFX state.                  */
            uint32_t            : 27;
    } DSP0MEMRETCFG_b;
  } ;
  __IM  uint32_t  RESERVED2[3];

  union {
    __IOM uint32_t DSP1PWRCTRL;                 /*!< (@ 0x00000070) Power and RST controls for DSP1                            */

    struct {
      __IOM uint32_t DSP1PCMRSTDLY : 4;         /*!< [3..0] PCM Reset delay in number of 24MHz clocks.                         */
      __IOM uint32_t DSP1PCMRSTOR : 1;          /*!< [4..4] PCM Reset override. If this is disabled, then h/w will
                                                     handle the de-assertion of pcm reset.                                     */
            uint32_t            : 27;
    } DSP1PWRCTRL_b;
  } ;

  union {
    __IOM uint32_t DSP1PERFREQ;                 /*!< (@ 0x00000074) This register provides the performance mode knobs
                                                                    for DSP1. S/w should write the *PERFREQ
                                                                    field to desired mode and wait for the *PERFACK
                                                                    and check for the *PERFSTATUS. Some times
                                                                    system may not allow certain modes but *PERFACK
                                                                    should always follow *PERFREQ change.                      */

    struct {
      __IOM uint32_t DSP1PERFREQ : 2;           /*!< [1..0] DSP1 Performance mode request                                      */
      __IOM uint32_t DSP1PERFACK : 1;           /*!< [2..2] Indicates the DSP1 performance status indicated in STATUS
                                                     register is valid.                                                        */
      __IOM uint32_t DSP1PERFSTATUS : 2;        /*!< [4..3] DSP1 Performance mode request                                      */
            uint32_t            : 27;
    } DSP1PERFREQ_b;
  } ;

  union {
    __IOM uint32_t DSP1MEMPWREN;                /*!< (@ 0x00000078) This register enables the individual banks for
                                                                    the memories. When set, power will be enabled
                                                                    to the banks. This register works in conjunction
                                                                    with the DSP1MEMRETCFG register when DSP1
                                                                    is OFF.                                                    */

    struct {
      __IOM uint32_t PWRENDSP1RAM : 1;          /*!< [0..0] Power up DSP1 IRAM and DRAM                                        */
      __IOM uint32_t PWRENDSP1ICACHE : 1;       /*!< [1..1] Power up DSP1 ICACHE banks                                         */
            uint32_t            : 30;
    } DSP1MEMPWREN_b;
  } ;

  union {
    __IOM uint32_t DSP1MEMPWRST;                /*!< (@ 0x0000007C) It provides the power status for all the memories
                                                                    of DSP1 subsystem                                          */

    struct {
      __IOM uint32_t PWRSTDSP1RAM : 1;          /*!< [0..0] Status- 1:ON, 0:OFF                                                */
      __IOM uint32_t PWRSTDSP1ICACHE : 1;       /*!< [1..1] Power Status- 1:ON, 0:OFF                                          */
            uint32_t            : 30;
    } DSP1MEMPWRST_b;
  } ;

  union {
    __IOM uint32_t DSP1MEMRETCFG;               /*!< (@ 0x00000080) This controls the power down of the DRAM/IRAM/CACHE
                                                                    banks when DSP1 is powered off. If this
                                                                    is set, then the power for that corresponding
                                                                    SRAM bank will be gated when the DSP1 is
                                                                    powered off and data is erased. If this
                                                                    is not set, retention voltage will be applied
                                                                    when DSP1 is powered off. Do not set this
                                                                    if the SRAM bank is used as the target for
                                                                    DMA transfer while DSP1 is powered off.                    */

    struct {
      __IOM uint32_t RAMPWDDSP1OFF : 1;         /*!< [0..0] IRAM/DRAM banks are powered down when DSP1 is switched
                                                     off, causing the contents of the bank to be lost.                         */
      __IOM uint32_t DSP1RAMACTMCU : 1;         /*!< [1..1] Keep the memory domain active based on MCU state.                  */
      __IOM uint32_t ICACHEPWDDSP1OFF : 1;      /*!< [2..2] ICACHE is powered down when DSP1 is switched off, causing
                                                     the contents of the bank to be lost.                                      */
      __IOM uint32_t DSP1RAMACTDISP : 1;        /*!< [3..3] Keep the memory domain active based on DISP state.                 */
      __IOM uint32_t DSP1RAMACTGFX : 1;         /*!< [4..4] Keep the memory domain active based on GFX state.                  */
            uint32_t            : 27;
    } DSP1MEMRETCFG_b;
  } ;

  union {
    __IOM uint32_t PWRACKOVR;                   /*!< (@ 0x00000084) This register contains override bit fields for
                                                                    various power domain power switch acknowledge
                                                                    notification. As a part of power up sequnce,
                                                                    Power controller will look for power switch
                                                                    ack to advance power up sequence. It is
                                                                    possible for power controller to be a forever
                                                                    wait state in case of a unforeseen HW bug.
                                                                    This register defines a bit fileds to work
                                                                    around if needed in such a situation. The
                                                                    default behavior is to use HW power switch
                                                                    ack. Software can set it to override this
                                                                    feature for ea                                             */

    struct {
      __IOM uint32_t PWRACKOVERRIDEADC : 1;     /*!< [0..0] Power switch acknowledgement override from Power switch
                                                     to power control ST MC                                                    */
      __IOM uint32_t PWRACKOVERRIDEAUD : 1;     /*!< [1..1] Power switch acknowledgement override from Power switch
                                                     to power control ST MC                                                    */
      __IOM uint32_t PWRACKOVERRIDEAUDADC : 1;  /*!< [2..2] Power switch acknowledgement override from Power switch
                                                     to power control ST MC                                                    */
      __IOM uint32_t PWRACKOVERRIDECRYPTO : 1;  /*!< [3..3] Power switch acknowledgement override from Power switch
                                                     to power control ST MC                                                    */
      __IOM uint32_t PWRACKOVERRIDEDBG : 1;     /*!< [4..4] Power switch acknowledgement override from Power switch
                                                     to power control ST MC                                                    */
      __IOM uint32_t PWRACKOVERRIDEDISP : 1;    /*!< [5..5] Power switch acknowledgement override from Power switch
                                                     to power control ST MC                                                    */
      __IOM uint32_t PWRACKOVERRIDEDISPPHY : 1; /*!< [6..6] Power switch acknowledgement override from Power switch
                                                     to power control ST MC                                                    */
      __IOM uint32_t PWRACKOVERRIDEGFX : 1;     /*!< [7..7] Power switch acknowledgement override from Power switch
                                                     to power control ST MC                                                    */
      __IOM uint32_t PWRACKOVERRIDEHCPA : 1;    /*!< [8..8] Power switch acknowledgement override from Power switch
                                                     to power control ST MC                                                    */
      __IOM uint32_t PWRACKOVERRIDEHCPB : 1;    /*!< [9..9] Power switch acknowledgement override from Power switch
                                                     to power control ST MC                                                    */
      __IOM uint32_t PWRACKOVERRIDEHCPC : 1;    /*!< [10..10] Power switch acknowledgement override from Power switch
                                                     to power control ST MC                                                    */
      __IOM uint32_t PWRACKOVERRIDEIOS : 1;     /*!< [11..11] Power switch acknowledgement override from Power switch
                                                     to power control ST MC                                                    */
      __IOM uint32_t PWRACKOVERRIDEMCUL : 1;    /*!< [12..12] Power switch acknowledgement override from Power switch
                                                     to power control ST MC                                                    */
      __IOM uint32_t PWRACKOVERRIDEMSPI : 1;    /*!< [13..13] Power switch acknowledgement override from Power switch
                                                     to power control ST MC                                                    */
      __IOM uint32_t PWRACKOVERRIDESDIO : 1;    /*!< [14..14] Power switch acknowledgement override from Power switch
                                                     to power control ST MC                                                    */
      __IOM uint32_t PWRACKOVERRIDEUSB : 1;     /*!< [15..15] Power switch acknowledgement override from Power switch
                                                     to power control ST MC                                                    */
      __IOM uint32_t PWRACKOVERRIDEUSBPHY : 1;  /*!< [16..16] Power switch acknowledgement override from Power switch
                                                     to power control ST MC                                                    */
      __IOM uint32_t PWRACKOVERRIDEDSPA : 1;    /*!< [17..17] Power switch acknowledgement override from Power switch
                                                     to power control ST MC                                                    */
            uint32_t            : 14;
    } PWRACKOVR_b;
  } ;

  union {
    __IOM uint32_t PWRCNTDEFVAL;                /*!< (@ 0x00000088) This register contains programmble delay values
                                                                    for various state michines. Fields contain
                                                                    dev st machine default value, SIMOBUCK state
                                                                    machine wait delay counter etc.                            */

    struct {
      __IOM uint32_t PWRDEFVALDEVSTMC : 6;      /*!< [5..0] Default count max value for dev ST MC                              */
      __IOM uint32_t PWRACKWAITDELSIMOSTMC : 10;/*!< [15..6] Default counter max for buck ST MC                                */
            uint32_t            : 16;
    } PWRCNTDEFVAL_b;
  } ;
  __IM  uint32_t  RESERVED3[29];

  union {
    __IOM uint32_t VRCTRL;                      /*!< (@ 0x00000100) This register includes additional debug control
                                                                    bits. This is an internal Ambiq-only register.
                                                                    Customers should not attempt to change this
                                                                    or else functionality cannot be guaranteed.                */

    struct {
      __IOM uint32_t SIMOBUCKEN : 1;            /*!< [0..0] Enables and Selects the SIMO Buck as the supply for the
                                                     low-voltage power domains. It takes the initial value from
                                                     the bit set in Customer INFO space.                                       */
            uint32_t            : 31;
    } VRCTRL_b;
  } ;

  union {
    __IOM uint32_t LEGACYVRLPOVR;               /*!< (@ 0x00000104) When an override is set for a power domain, VR
                                                                    logic will ignore that power domain state
                                                                    in making a decision to go into lp state.                  */

    struct {
      __IOM uint32_t IGNOREIOS  : 1;            /*!< [0..0] Ignore IOS                                                         */
      __IOM uint32_t IGNOREHCPA : 1;            /*!< [1..1] Ignore HCPA                                                        */
      __IOM uint32_t IGNOREHCPB : 1;            /*!< [2..2] Ignore HCPB                                                        */
      __IOM uint32_t IGNOREHCPC : 1;            /*!< [3..3] Ignore HCPC                                                        */
      __IOM uint32_t IGNOREHCPD : 1;            /*!< [4..4] Ignore HCPD                                                        */
      __IOM uint32_t IGNOREHCPE : 1;            /*!< [5..5] Ignore HCPE                                                        */
      __IOM uint32_t IGNOREMSPI : 1;            /*!< [6..6] Ignore MSPI                                                        */
      __IOM uint32_t IGNOREGFX  : 1;            /*!< [7..7] Ignore GFX                                                         */
            uint32_t            : 2;
      __IOM uint32_t IGNORECRYPTO : 1;          /*!< [10..10] Ignore CRYPTO                                                    */
      __IOM uint32_t IGNORESDIO : 1;            /*!< [11..11] Ignore SDIO                                                      */
            uint32_t            : 2;
      __IOM uint32_t IGNOREAUD  : 1;            /*!< [14..14] Ignore AUD                                                       */
            uint32_t            : 3;
      __IOM uint32_t IGNOREDBG  : 1;            /*!< [18..18] Ignore DBG                                                       */
            uint32_t            : 13;
    } LEGACYVRLPOVR_b;
  } ;

  union {
    __IOM uint32_t VRSTATUS;                    /*!< (@ 0x00000108) Provides BUCK and LDOs status.                             */

    struct {
      __IOM uint32_t CORELDOST  : 2;            /*!< [1..0] Indicates CORELDO status. bit[1] indicates ON/OFF and
                                                     bit[0] indicates ACT/LP.                                                  */
      __IOM uint32_t MEMLDOST   : 2;            /*!< [3..2] Indicates MEMLDO status. bit[1] indicates ON/OFF and
                                                     bit[0] indicates ACT/LP.                                                  */
      __IOM uint32_t SIMOBUCKST : 2;            /*!< [5..4] Indicates SIMO BUCK status. bit[1] indicates ON/OFF and
                                                     bit[0] indicates ACT/LP                                                   */
            uint32_t            : 26;
    } VRSTATUS_b;
  } ;
  __IM  uint32_t  RESERVED4[33];

  union {
    __IOM uint32_t SRAMCTRL;                    /*!< (@ 0x00000190) This register provides additional fine-tune power
                                                                    management controls for the SRAMs and the
                                                                    SRAM controller. This includes enabling
                                                                    light sleep for the SRAM and TCM banks,
                                                                    and clock gating for reduced dynamic power.                */

    struct {
            uint32_t            : 1;
      __IOM uint32_t SRAMCLKGATE : 1;           /*!< [1..1] This bit is 1 if clock gating is allowed for individual
                                                     system SRAMs                                                              */
      __IOM uint32_t SRAMMASTERCLKGATE : 1;     /*!< [2..2] This bit is 1 when the master clock gate is enabled (top-level
                                                     clock gate for entire SRAM block)                                         */
            uint32_t            : 5;
      __IOM uint32_t SRAMLIGHTSLEEP : 12;       /*!< [19..8] Light Sleep enable for each TCM/SRAM bank. When 1, corresponding
                                                     bank will be put into light sleep. For optimal power, banks
                                                     should be put into light sleep while the system is active
                                                     but the bank has minimal or no accesses.                                  */
            uint32_t            : 12;
    } SRAMCTRL_b;
  } ;

  union {
    __IOM uint32_t ADCSTATUS;                   /*!< (@ 0x00000194) This provides the power status for various blocks
                                                                    within the ADC. These status comes directly
                                                                    from the ADC module and is captured through
                                                                    this interface.                                            */

    struct {
      __IOM uint32_t ADCPWD     : 1;            /*!< [0..0] This bit indicates that the ADC is powered down                    */
      __IOM uint32_t BGTPWD     : 1;            /*!< [1..1] This bit indicates that the ADC Band Gap is powered down           */
      __IOM uint32_t VPTATPWD   : 1;            /*!< [2..2] This bit indicates that the ADC temperature sensor input
                                                     buffer is powered down                                                    */
      __IOM uint32_t VBATPWD    : 1;            /*!< [3..3] This bit indicates that the ADC VBAT resistor divider
                                                     is powered down                                                           */
      __IOM uint32_t REFKEEPPWD : 1;            /*!< [4..4] This bit indicates that the ADC REFKEEP is powered down            */
      __IOM uint32_t REFBUFPWD  : 1;            /*!< [5..5] This bit indicates that the ADC REFBUF is powered down             */
            uint32_t            : 26;
    } ADCSTATUS_b;
  } ;

  union {
    __IOM uint32_t AUDADCSTATUS;                /*!< (@ 0x00000198) This provides the power status for various blocks
                                                                    within the audio ADC. These status comes
                                                                    directly from the audio ADC module and is
                                                                    captured through this interface.                           */

    struct {
      __IOM uint32_t AUDADCPWD  : 1;            /*!< [0..0] This bit indicates that the ADC is powered down                    */
      __IOM uint32_t AUDBGTPWD  : 1;            /*!< [1..1] This bit indicates that the ADC Band Gap is powered down           */
      __IOM uint32_t AUDVPTATPWD : 1;           /*!< [2..2] This bit indicates that the ADC temperature sensor input
                                                     buffer is powered down                                                    */
      __IOM uint32_t AUDVBATPWD : 1;            /*!< [3..3] This bit indicates that the ADC VBAT resistor divider
                                                     is powered down                                                           */
      __IOM uint32_t AUDREFKEEPPWD : 1;         /*!< [4..4] This bit indicates that the ADC REFKEEP is powered down            */
      __IOM uint32_t AUDREFBUFPWD : 1;          /*!< [5..5] This bit indicates that the ADC REFBUF is powered down             */
            uint32_t            : 26;
    } AUDADCSTATUS_b;
  } ;
  __IM  uint32_t  RESERVED5[25];

  union {
    __IOM uint32_t EMONCTRL;                    /*!< (@ 0x00000200) Controls each of the energy monitor conuters               */

    struct {
      __IOM uint32_t FREEZE     : 8;            /*!< [7..0] Freeze the counter. Each bit corresponds to a counter.
                                                     0: Let the counter run. 1: Stop the counter.                              */
      __IOM uint32_t CLEAR      : 8;            /*!< [15..8] Clear the counter. Each bit corresponds to a counter.
                                                     0: Let the counter run run on its input clk. 1: Clear the
                                                     counter                                                                   */
            uint32_t            : 16;
    } EMONCTRL_b;
  } ;

  union {
    __IOM uint32_t EMONCFG0;                    /*!< (@ 0x00000204) The counter increments when the counter is enabled
                                                                    and the mode selected here matches the power
                                                                    mode.                                                      */

    struct {
      __IOM uint32_t EMONSEL0   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
            uint32_t            : 24;
    } EMONCFG0_b;
  } ;

  union {
    __IOM uint32_t EMONCFG1;                    /*!< (@ 0x00000208) The counter increments when the counter is enabled
                                                                    and the mode selected here matches the power
                                                                    mode.                                                      */

    struct {
      __IOM uint32_t EMONSEL1   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
            uint32_t            : 24;
    } EMONCFG1_b;
  } ;

  union {
    __IOM uint32_t EMONCFG2;                    /*!< (@ 0x0000020C) The counter increments when the counter is enabled
                                                                    and the mode selected here matches the power
                                                                    mode.                                                      */

    struct {
      __IOM uint32_t EMONSEL2   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
            uint32_t            : 24;
    } EMONCFG2_b;
  } ;

  union {
    __IOM uint32_t EMONCFG3;                    /*!< (@ 0x00000210) The counter increments when the counter is enabled
                                                                    and the mode selected here matches the power
                                                                    mode.                                                      */

    struct {
      __IOM uint32_t EMONSEL3   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
            uint32_t            : 24;
    } EMONCFG3_b;
  } ;

  union {
    __IOM uint32_t EMONCFG4;                    /*!< (@ 0x00000214) The counter increments when the counter is enabled
                                                                    and the mode selected here matches the power
                                                                    mode.                                                      */

    struct {
      __IOM uint32_t EMONSEL4   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
            uint32_t            : 24;
    } EMONCFG4_b;
  } ;

  union {
    __IOM uint32_t EMONCFG5;                    /*!< (@ 0x00000218) The counter increments when the counter is enabled
                                                                    and the mode selected here matches the power
                                                                    mode.                                                      */

    struct {
      __IOM uint32_t EMONSEL5   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
            uint32_t            : 24;
    } EMONCFG5_b;
  } ;

  union {
    __IOM uint32_t EMONCFG6;                    /*!< (@ 0x0000021C) The counter increments when the counter is enabled
                                                                    and the mode selected here matches the power
                                                                    mode.                                                      */

    struct {
      __IOM uint32_t EMONSEL6   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
            uint32_t            : 24;
    } EMONCFG6_b;
  } ;

  union {
    __IOM uint32_t EMONCFG7;                    /*!< (@ 0x00000220) The counter increments when the counter is enabled
                                                                    and the mode selected here matches the power
                                                                    mode.                                                      */

    struct {
      __IOM uint32_t EMONSEL7   : 8;            /*!< [7..0] Power modes for incrementing the counter                           */
            uint32_t            : 24;
    } EMONCFG7_b;
  } ;
  __IM  uint32_t  RESERVED6;

  union {
    __IOM uint32_t EMONCOUNT0;                  /*!< (@ 0x00000228) Energy Monitor count value for counter 0                   */

    struct {
      __IOM uint32_t EMONCOUNT0 : 32;           /*!< [31..0] Energy Monitor count value counter 0                              */
    } EMONCOUNT0_b;
  } ;

  union {
    __IOM uint32_t EMONCOUNT1;                  /*!< (@ 0x0000022C) Energy Monitor count value for counter 1                   */

    struct {
      __IOM uint32_t EMONCOUNT1 : 32;           /*!< [31..0] Energy Monitor count value counter 1                              */
    } EMONCOUNT1_b;
  } ;

  union {
    __IOM uint32_t EMONCOUNT2;                  /*!< (@ 0x00000230) Energy Monitor count value for counter 2                   */

    struct {
      __IOM uint32_t EMONCOUNT2 : 32;           /*!< [31..0] Energy Monitor count value counter 2                              */
    } EMONCOUNT2_b;
  } ;

  union {
    __IOM uint32_t EMONCOUNT3;                  /*!< (@ 0x00000234) Energy Monitor count value for counter 3                   */

    struct {
      __IOM uint32_t EMONCOUNT3 : 32;           /*!< [31..0] Energy Monitor count value counter 3                              */
    } EMONCOUNT3_b;
  } ;

  union {
    __IOM uint32_t EMONCOUNT4;                  /*!< (@ 0x00000238) Energy Monitor count value for counter 4                   */

    struct {
      __IOM uint32_t EMONCOUNT4 : 32;           /*!< [31..0] Energy Monitor count value counter 4                              */
    } EMONCOUNT4_b;
  } ;

  union {
    __IOM uint32_t EMONCOUNT5;                  /*!< (@ 0x0000023C) Energy Monitor count value for counter 5                   */

    struct {
      __IOM uint32_t EMONCOUNT5 : 32;           /*!< [31..0] Energy Monitor count value counter 5                              */
    } EMONCOUNT5_b;
  } ;

  union {
    __IOM uint32_t EMONCOUNT6;                  /*!< (@ 0x00000240) Energy Monitor count value for counter 6                   */

    struct {
      __IOM uint32_t EMONCOUNT6 : 32;           /*!< [31..0] Energy Monitor count value counter 6                              */
    } EMONCOUNT6_b;
  } ;

  union {
    __IOM uint32_t EMONCOUNT7;                  /*!< (@ 0x00000244) Energy Monitor count value for counter 7                   */

    struct {
      __IOM uint32_t EMONCOUNT7 : 32;           /*!< [31..0] Energy Monitor count value counter 7                              */
    } EMONCOUNT7_b;
  } ;
  __IM  uint32_t  RESERVED7;

  union {
    __IOM uint32_t EMONSTATUS;                  /*!< (@ 0x0000024C) Energy Monitor status                                      */

    struct {
      __IOM uint32_t EMONOVERFLOW0 : 1;         /*!< [0..0] Energy Monitor counter0 overflow                                   */
      __IOM uint32_t EMONOVERFLOW1 : 1;         /*!< [1..1] Energy Monitor counter1 overflow                                   */
      __IOM uint32_t EMONOVERFLOW2 : 1;         /*!< [2..2] Energy Monitor counter2 overflow                                   */
      __IOM uint32_t EMONOVERFLOW3 : 1;         /*!< [3..3] Energy Monitor counter3 overflow                                   */
      __IOM uint32_t EMONOVERFLOW4 : 1;         /*!< [4..4] Energy Monitor counter4 overflow                                   */
      __IOM uint32_t EMONOVERFLOW5 : 1;         /*!< [5..5] Energy Monitor counter5 overflow                                   */
      __IOM uint32_t EMONOVERFLOW6 : 1;         /*!< [6..6] Energy Monitor counter6 overflow                                   */
      __IOM uint32_t EMONOVERFLOW7 : 1;         /*!< [7..7] Energy Monitor counter7 overflow                                   */
            uint32_t            : 24;
    } EMONSTATUS_b;
  } ;
} PWRCTRL_Type;                                 /*!< Size = 592 (0x250)                                                        */



/* =========================================================================================================================== */
/* ================                                          RSTGEN                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief MCU Reset Generator (RSTGEN)
  */

typedef struct {                                /*!< (@ 0x40000000) RSTGEN Structure                                           */

  union {
    __IOM uint32_t CFG;                         /*!< (@ 0x00000000) Reset configuration register. This controls the
                                                                    reset enables for brownout condition, choice
                                                                    of brownout method and for the expiration
                                                                    of the watch dog timer.                                    */

    struct {
      __IOM uint32_t BODHREN    : 1;            /*!< [0..0] Brown out high (2.1v) reset enable. Note - Enabling this
                                                     bit for Apollo4, which operates at 1.8v/1.9v, will cause
                                                     a continual reset loop.                                                   */
      __IOM uint32_t WDREN      : 1;            /*!< [1..1] Watchdog Timer Reset Enable. NOTE: The WDT module must
                                                     also be configured for WDT reset. This includes enabling
                                                     the RESEN bit in WDTCFG register in Watch dog timer block.                */
            uint32_t            : 30;
    } CFG_b;
  } ;

  union {
    __IOM uint32_t SWPOI;                       /*!< (@ 0x00000004) This is the software POI reset. writing the key
                                                                    value to this register will trigger a POI
                                                                    to the system. This will cause a reset to
                                                                    all blocks except for registers in clock
                                                                    gen, RTC and the stimer.                                   */

    struct {
      __IOM uint32_t SWPOIKEY   : 8;            /*!< [7..0] 0x1B generates a software POI reset. This is a write-only
                                                     register. Reading from this register will yield only all
                                                     0s.                                                                       */
            uint32_t            : 24;
    } SWPOI_b;
  } ;

  union {
    __IOM uint32_t SWPOR;                       /*!< (@ 0x00000008) This is the software POR reset. Writing the key
                                                                    value to this register will trigger a POR
                                                                    to the system. This will cause a reset to
                                                                    all blocks except for registers in clock
                                                                    gen, RTC, power management unit, the stimer,
                                                                    and the power management unit.                             */

    struct {
      __IOM uint32_t SWPORKEY   : 8;            /*!< [7..0] 0xD4 generates a software POR reset.                               */
            uint32_t            : 24;
    } SWPOR_b;
  } ;
  __IM  uint32_t  RESERVED[2];

  union {
    __IOM uint32_t SIMOBODM;                    /*!< (@ 0x00000014) This register unmasks the individual digital
                                                                    detection brownout bits into the interrupt
                                                                    block                                                      */

    struct {
      __IOM uint32_t DIGBOEC    : 1;            /*!< [0..0] Enable the gate into the interrupt block for the digital
                                                     brownout detection on VDDC. Note: The interrupt block must
                                                     also be unmasked for ISR and interrupt status to be set                   */
      __IOM uint32_t DIGBOEF    : 1;            /*!< [1..1] Enable the gate into the interrupt block for the digital
                                                     brownout detection on VDDF. Note: The interrupt block must
                                                     also be unmasked for ISR and interrupt status to be set                   */
      __IOM uint32_t DIGBOES    : 1;            /*!< [2..2] Enable the gate into the interrupt block for the digital
                                                     brownout detection on VDDS. Note: The interrupt block must
                                                     also be unmasked for ISR and interrupt status to be set                   */
      __IOM uint32_t DIGBOECLV  : 1;            /*!< [3..3] Enable the gate into the interrupt block for the digital
                                                     brownout detection on VDDC_LV. Note: The interrupt block
                                                     must also be unmasked for ISR and interrupt status to be
                                                     set                                                                       */
            uint32_t            : 28;
    } SIMOBODM_b;
  } ;
  __IM  uint32_t  RESERVED1[122];

  union {
    __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
                                                     BODH level.                                                               */
      __IOM uint32_t BODDIGC    : 1;            /*!< [1..1] Enables an interrupt that triggers when simobuck digital
                                                     detects inactivity on VDDC                                                */
      __IOM uint32_t BODDIGF    : 1;            /*!< [2..2] Enables an interrupt that triggers when simobuck digital
                                                     detects inactivity on VDDF                                                */
      __IOM uint32_t BODDIGS    : 1;            /*!< [3..3] Enables an interrupt that triggers when simobuck digital
                                                     detects inactivity on VDDS                                                */
      __IOM uint32_t BODDIGCLV  : 1;            /*!< [4..4] Enables an interrupt that triggers when simobuck digital
                                                     detects inactivity on VDDC_LV                                             */
            uint32_t            : 27;
    } INTEN_b;
  } ;

  union {
    __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
                                                     BODH level.                                                               */
      __IOM uint32_t BODDIGC    : 1;            /*!< [1..1] Enables an interrupt that triggers when simobuck digital
                                                     detects inactivity on VDDC                                                */
      __IOM uint32_t BODDIGF    : 1;            /*!< [2..2] Enables an interrupt that triggers when simobuck digital
                                                     detects inactivity on VDDF                                                */
      __IOM uint32_t BODDIGS    : 1;            /*!< [3..3] Enables an interrupt that triggers when simobuck digital
                                                     detects inactivity on VDDS                                                */
      __IOM uint32_t BODDIGCLV  : 1;            /*!< [4..4] Enables an interrupt that triggers when simobuck digital
                                                     detects inactivity on VDDC_LV                                             */
            uint32_t            : 27;
    } INTSTAT_b;
  } ;

  union {
    __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
                                                     BODH level.                                                               */
      __IOM uint32_t BODDIGC    : 1;            /*!< [1..1] Enables an interrupt that triggers when simobuck digital
                                                     detects inactivity on VDDC                                                */
      __IOM uint32_t BODDIGF    : 1;            /*!< [2..2] Enables an interrupt that triggers when simobuck digital
                                                     detects inactivity on VDDF                                                */
      __IOM uint32_t BODDIGS    : 1;            /*!< [3..3] Enables an interrupt that triggers when simobuck digital
                                                     detects inactivity on VDDS                                                */
      __IOM uint32_t BODDIGCLV  : 1;            /*!< [4..4] Enables an interrupt that triggers when simobuck digital
                                                     detects inactivity on VDDC_LV                                             */
            uint32_t            : 27;
    } INTCLR_b;
  } ;

  union {
    __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
                                                     BODH level.                                                               */
      __IOM uint32_t BODDIGC    : 1;            /*!< [1..1] Enables an interrupt that triggers when simobuck digital
                                                     detects inactivity on VDDC                                                */
      __IOM uint32_t BODDIGF    : 1;            /*!< [2..2] Enables an interrupt that triggers when simobuck digital
                                                     detects inactivity on VDDF                                                */
      __IOM uint32_t BODDIGS    : 1;            /*!< [3..3] Enables an interrupt that triggers when simobuck digital
                                                     detects inactivity on VDDS                                                */
      __IOM uint32_t BODDIGCLV  : 1;            /*!< [4..4] Enables an interrupt that triggers when simobuck digital
                                                     detects inactivity on VDDC_LV                                             */
            uint32_t            : 27;
    } INTSET_b;
  } ;
  __IM  uint32_t  RESERVED2[8595];

  union {
    __IOM uint32_t STAT;                        /*!< (@ 0x0000885C) This register contains the status for brownout
                                                                    events and the causes for resets.
                                                                    NOTE 1: All bits in this register, including
                                                                    reserved bits, are writable. Therefore care
                                                                    should be taken not to write this register.
                                                                    NOTE 2: This register is only reset by POI
                                                                    not by HRESETn. Its contents are intended
                                                                    to survive all reset level except POI and
                                                                    full power cycles.                                         */

    struct {
      __IOM uint32_t EXRSTAT    : 1;            /*!< [0..0] Reset was initiated by an External Reset.                          */
      __IOM uint32_t PORSTAT    : 1;            /*!< [1..1] Reset was initiated by a Power-On Reset.                           */
      __IOM uint32_t BORSTAT    : 1;            /*!< [2..2] Reset was initiated by a Brown-Out Reset.                          */
      __IOM uint32_t SWRSTAT    : 1;            /*!< [3..3] Reset was a initiated by SW POR or AIRCR Reset.                    */
      __IOM uint32_t POIRSTAT   : 1;            /*!< [4..4] Reset was a initiated by Software POI Reset.                       */
      __IOM uint32_t DBGRSTAT   : 1;            /*!< [5..5] Reset was a initiated by Debugger Reset.                           */
      __IOM uint32_t WDRSTAT    : 1;            /*!< [6..6] Reset was initiated by a Watchdog Timer Reset.                     */
      __IOM uint32_t BOUSTAT    : 1;            /*!< [7..7] An Unregulated Supply Brownout Event occured.                      */
      __IOM uint32_t BOCSTAT    : 1;            /*!< [8..8] VDDC Analog Brownout Event occured.                                */
      __IOM uint32_t BOFSTAT    : 1;            /*!< [9..9] VDDF Analog Brownout Event occured.                                */
      __IOM uint32_t BOSSTAT    : 1;            /*!< [10..10] VDDS Analog Brownout Event occured.                              */
            uint32_t            : 21;
    } STAT_b;
  } ;
} RSTGEN_Type;                                  /*!< Size = 34912 (0x8860)                                                     */



/* =========================================================================================================================== */
/* ================                                            RTC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Real Time Clock (RTC)
  */

typedef struct {                                /*!< (@ 0x40004800) RTC Structure                                              */

  union {
    __IOM uint32_t RTCCTL;                      /*!< (@ 0x00000000) This is the register control for the RTC module.
                                                                    It enables counter writes and sets the alarm
                                                                    repeat interval.                                           */

    struct {
      __IOM uint32_t WRTC       : 1;            /*!< [0..0] Counter write control                                              */
      __IOM uint32_t RPT        : 3;            /*!< [3..1] Alarm repeat interval                                              */
      __IOM uint32_t RSTOP      : 1;            /*!< [4..4] RTC input clock control                                            */
      __IOM uint32_t HR1224     : 1;            /*!< [5..5] Hours Counter mode Only 24HR mode supported                        */
            uint32_t            : 26;
    } RTCCTL_b;
  } ;

  union {
    __IOM uint32_t RTCSTAT;                     /*!< (@ 0x00000004) This is the register status for the RTC module.            */

    struct {
      __IOM uint32_t WRITEBUSY  : 1;            /*!< [0..0] Indicates that an RTC update (write) is still in progress.
                                                     Writes are initiated by writing the CTTLOW register - CTRUP
                                                     must be written before CTRLOW to be updated (otherwise
                                                     it will retain its current value)                                         */
            uint32_t            : 31;
    } RTCSTAT_b;
  } ;
  __IM  uint32_t  RESERVED[6];

  union {
    __IOM uint32_t CTRLOW;                      /*!< (@ 0x00000020) This counter contains the values for hour, minutes,
                                                                    seconds and 100ths of a second Counter.                    */

    struct {
      __IOM uint32_t CTR100     : 8;            /*!< [7..0] 100ths of a second Counter. Contains the current value
                                                     for hundredths of a second.                                               */
      __IOM uint32_t CTRSEC     : 7;            /*!< [14..8] Seconds Counter. Contains the current value for seconds.          */
            uint32_t            : 1;
      __IOM uint32_t CTRMIN     : 7;            /*!< [22..16] Minutes Counter. Contains the current value for minutes.         */
            uint32_t            : 1;
      __IOM uint32_t CTRHR      : 6;            /*!< [29..24] Hours Counter. Contains the current value for hour.              */
            uint32_t            : 2;
    } CTRLOW_b;
  } ;

  union {
    __IOM uint32_t CTRUP;                       /*!< (@ 0x00000024) This register contains the day, month and year
                                                                    information. It contains which day in the
                                                                    week, and the century as well. The information
                                                                    of the century can also be derived from
                                                                    the year information. The 31st bit contains
                                                                    the error bit. See description in the register
                                                                    bit for condition when error is triggered.                 */

    struct {
      __IOM uint32_t CTRDATE    : 6;            /*!< [5..0] Date Counter. Contains the current value for date.                 */
            uint32_t            : 2;
      __IOM uint32_t CTRMO      : 5;            /*!< [12..8] Months Counter. Contains the current value for months.            */
            uint32_t            : 3;
      __IOM uint32_t CTRYR      : 8;            /*!< [23..16] Years Counter. Contains the current value for year.              */
      __IOM uint32_t CTRWKDY    : 3;            /*!< [26..24] Weekdays Counter. Contains the current value for weekdays.       */
            uint32_t            : 1;
      __IOM uint32_t CB         : 1;            /*!< [28..28] Century Bit. CB == 0 assumes the century is 21xx, and
                                                     CB == 1 assumes it is 20xx.                                               */
      __IOM uint32_t CEB        : 1;            /*!< [29..29] Century Enable Bit. ERR129 - RTC cannot perform rollover.
                                                     Century Bit toggles when CEB == 1 and Year == 99 and hence
                                                     cannot handle Year rollover from xx99 -> xx00                             */
            uint32_t            : 1;
      __IOM uint32_t CTERR      : 1;            /*!< [31..31] Counter read error status. Error is triggered when
                                                     software reads the lower word of the counters, and fails
                                                     to read the upper counter within 1/100 second. This is
                                                     because when the lower counter is read, the upper counter
                                                     is held off from incrementing until it is read so that
                                                     the full time stamp can be read.                                          */
    } CTRUP_b;
  } ;
  __IM  uint32_t  RESERVED1[2];

  union {
    __IOM uint32_t ALMLOW;                      /*!< (@ 0x00000030) This register is the Alarm settings for hours,
                                                                    minutes, second and 1/100th seconds settings.              */

    struct {
      __IOM uint32_t ALM100     : 8;            /*!< [7..0] 100ths of a second Alarm. Contains the current value
                                                     for hundredths of a second.                                               */
      __IOM uint32_t ALMSEC     : 7;            /*!< [14..8] Seconds Alarm. Contains the current value for seconds.            */
            uint32_t            : 1;
      __IOM uint32_t ALMMIN     : 7;            /*!< [22..16] Minutes Alarm. Contains the current value for minutes.           */
            uint32_t            : 1;
      __IOM uint32_t ALMHR      : 6;            /*!< [29..24] Hours Alarm. Contains the current value for hour.                */
            uint32_t            : 2;
    } ALMLOW_b;
  } ;

  union {
    __IOM uint32_t ALMUP;                       /*!< (@ 0x00000034) This register is the alarm settings for week,
                                                                    month and day.                                             */

    struct {
      __IOM uint32_t ALMDATE    : 6;            /*!< [5..0] Date Alarm. Contains the current value for date alarm.             */
            uint32_t            : 2;
      __IOM uint32_t ALMMO      : 5;            /*!< [12..8] Months Alarm. Contains the current value for month alarm.         */
            uint32_t            : 3;
      __IOM uint32_t ALMWKDY    : 3;            /*!< [18..16] Weekdays Alarm. Contains the current value for weekday
                                                     alarm.                                                                    */
            uint32_t            : 13;
    } ALMUP_b;
  } ;
  __IM  uint32_t  RESERVED2[114];

  union {
    __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
            uint32_t            : 31;
    } INTEN_b;
  } ;

  union {
    __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
            uint32_t            : 31;
    } INTSTAT_b;
  } ;

  union {
    __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
            uint32_t            : 31;
    } INTCLR_b;
  } ;

  union {
    __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
            uint32_t            : 31;
    } INTSET_b;
  } ;
} RTC_Type;                                     /*!< Size = 528 (0x210)                                                        */



/* =========================================================================================================================== */
/* ================                                           SDIO                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief SDIO Control Registers (SDIO)
  */

typedef struct {                                /*!< (@ 0x40070000) SDIO Structure                                             */

  union {
    __IOM uint32_t SDMA;                        /*!< (@ 0x00000000) SDMA system address                                        */

    struct {
      __IOM uint32_t SDMASYSTEMADDRESS : 32;    /*!< [31..0] This register contains the physical system memory address
                                                     used for DMA transfers or the second argument for the Auto
                                                     CMD23. (1) SDMA System Address This register contains the
                                                     system memory address for a SDMA transfer. When the Host
                                                     Controller stops a SDMA transfer, this register shall point
                                                     to the system address of the next contiguous data position.
                                                     It can be accessed only if no transaction is executing
                                                     (i.e., after a transaction has stopped). Read operations
                                                     during transfers may return an invalid value. T                           */
    } SDMA_b;
  } ;

  union {
    __IOM uint32_t BLOCK;                       /*!< (@ 0x00000004) Block size                                                 */

    struct {
      __IOM uint32_t TRANSFERBLOCKSIZE : 12;    /*!< [11..0] This register specifies the block size for block data
                                                     transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. It
                                                     can be accessed only if no transaction is executing (i.e
                                                     after a transaction has stopped). Read operations during
                                                     transfer return an invalid value and write operations shall
                                                     be ignored.                                                               */
      __IOM uint32_t HOSTSDMABUFSZ : 3;         /*!< [14..12] To perform long DMA transfer, System Address register
                                                     shall be updated at every system boundary during DMA transfer.
                                                     These bits specify the size of contiguous buffer in the
                                                     system memory. The DMA transfer shall wait at the every
                                                     boundary specified by these fields and the HC generates
                                                     the DMA Interrupt to request the HD to update the System
                                                     Address register. These bits shall support when the DMA
                                                     Support in the Capabilities register is set to 1 and this
                                                     function is active when the DMA Enable in the Transfer
                                                                                                                               */
            uint32_t            : 1;
      __IOM uint32_t BLKCNT     : 16;           /*!< [31..16] This register is enabled when Block Count Enable in
                                                     the Transfer Mode register is set to 1 and is valid only
                                                     for multiple block transfers. The HC decrements the block
                                                     count after each block transfer and stops when the count
                                                     reaches zero. It can be accessed only if no transaction
                                                     is executing (i.e. after a transaction has stopped). Read
                                                     operations during transfer return an invalid value and
                                                     write operations shall be ignored. When saving transfer
                                                     context as a result of Suspend command, the number of blocks
                                                     y                                                                         */
    } BLOCK_b;
  } ;

  union {
    __IOM uint32_t ARGUMENT1;                   /*!< (@ 0x00000008) Argument1                                                  */

    struct {
      __IOM uint32_t CMDARG1    : 32;           /*!< [31..0] The SD Command Argument is specified as bit39-8 of Command-Format. */
    } ARGUMENT1_b;
  } ;

  union {
    __IOM uint32_t TRANSFER;                    /*!< (@ 0x0000000C) Transfer mode                                              */

    struct {
      __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA can be enabled only if DMA Support bit in the Capabilities
                                                     register is set. If this bit is set to 1, a DMA operation
                                                     shall begin when the HD writes to the upper byte of Command
                                                     register (00Fh).                                                          */
      __IOM uint32_t BLKCNTEN   : 1;            /*!< [1..1] This bit is used to enable the Block count register,
                                                     which is only relevant for multiple block transfers. When
                                                     this bit is 0, the Block Count register is disabled, which
                                                     is useful in executing an infinite transfer.                              */
      __IOM uint32_t ACMDEN     : 2;            /*!< [3..2] This field determines use of auto command functions.
                                                     There are two methods to stop Multiple-block read and write
                                                     operation. (1) Auto CMD12 Enable Multiple-block read and
                                                     write commands for memory require CMD12 to stop the operation.
                                                     When this field is set to 01b, the Host Controller issues
                                                     CMD12 automatically when last block transfer is completed.
                                                     Auto CMD12 error is indicated to the Auto CMD Error Status
                                                     register. The Host Driver shall not set this bit if the
                                                     command does not require CMD12. (2) Auto CMD23                            */
      __IOM uint32_t DXFERDIRSEL : 1;           /*!< [4..4] Data Transfer Direction Select. This bit defines the
                                                     direction of data transfers.                                              */
      __IOM uint32_t BLKSEL     : 1;            /*!< [5..5] This bit enables multiple block data transfers.                    */
            uint32_t            : 10;
      __IOM uint32_t RESPTYPESEL : 2;           /*!< [17..16] Response Type Select                                             */
            uint32_t            : 1;
      __IOM uint32_t CMDCRCCHKEN : 1;           /*!< [19..19] If this bit is set to 1, the HC shall check the CRC
                                                     field in the response. If an error is detected, it is reported
                                                     as a Command CRC Error. If this bit is set to 0, the CRC
                                                     field is not checked.                                                     */
      __IOM uint32_t CMDIDXCHKEN : 1;           /*!< [20..20] If this bit is set to 1, the HC shall check the index
                                                     field in the response to see if it has the same value as
                                                     the command index. If it is not, it is reported as a Command
                                                     Index Error. If this bit is set to 0, the Index field is
                                                     not checked.                                                              */
      __IOM uint32_t DATAPRSNTSEL : 1;          /*!< [21..21] This bit is set to 1 to indicate that data is present
                                                     and shall be transferred using the DAT line. If is set
                                                     to 0 for the following: 1. Commands using only CMD line
                                                     (ex. CMD52) 2. Commands with no data transfer but using
                                                     busy signal on DAT[0] line (R1b or R5b ex. CMD38) 3. Resume
                                                     Command                                                                   */
      __IOM uint32_t CMDTYPE    : 2;            /*!< [23..22] There are three types of special commands. Suspend,
                                                     Resume and Abort. These bits shall bet set to 00b for all
                                                     other commands. Suspend Command If the Suspend command
                                                     succeeds, the HC shall assume the SD Bus has been released
                                                     and that it is possible to issue the next command which
                                                     uses the DAT line. The HC shall de-assert Read Wait for
                                                     read transactions and stop checking busy for write transactions.
                                                     The Interrupt cycle shall start, in 4-bit mode. If the
                                                     Suspend command fails, the HC shall maintain its curren                   */
      __IOM uint32_t CMDIDX     : 6;            /*!< [29..24] This bit shall be set to the command number (CMD0-63,
                                                     ACMD063).                                                                 */
            uint32_t            : 2;
    } TRANSFER_b;
  } ;

  union {
    __IOM uint32_t RESPONSE0;                   /*!< (@ 0x00000010) Response0                                                  */

    struct {
      __IOM uint32_t CMDRESP0   : 32;           /*!< [31..0] R[] refers to a bit range within the response data as
                                                     transmitted on the SD Bus, REP[] refers to a bit range
                                                     within the Response register.                                             */
    } RESPONSE0_b;
  } ;

  union {
    __IOM uint32_t RESPONSE1;                   /*!< (@ 0x00000014) Response1                                                  */

    struct {
      __IOM uint32_t CMDRESP1   : 32;           /*!< [31..0] R[] refers to a bit range within the response data as
                                                     transmitted on the SD Bus, REP[] refers to a bit range
                                                     within the Response register.                                             */
    } RESPONSE1_b;
  } ;

  union {
    __IOM uint32_t RESPONSE2;                   /*!< (@ 0x00000018) Response2                                                  */

    struct {
      __IOM uint32_t CMDRESP2   : 32;           /*!< [31..0] R[] refers to a bit range within the response data as
                                                     transmitted on the SD Bus, REP[] refers to a bit range
                                                     within the Response register.                                             */
    } RESPONSE2_b;
  } ;

  union {
    __IOM uint32_t RESPONSE3;                   /*!< (@ 0x0000001C) Response3                                                  */

    struct {
      __IOM uint32_t CMDRESP3   : 32;           /*!< [31..0] R[] refers to a bit range within the response data as
                                                     transmitted on the SD Bus, REP[] refers to a bit range
                                                     within the Response register.                                             */
    } RESPONSE3_b;
  } ;

  union {
    __IOM uint32_t BUFFER;                      /*!< (@ 0x00000020) Buffer data port                                           */

    struct {
      __IOM uint32_t BUFFERDATA : 32;           /*!< [31..0] The Host Controller Buffer can be accessed through this
                                                     32-bit Data Port Register.                                                */
    } BUFFER_b;
  } ;

  union {
    __IOM uint32_t PRESENT;                     /*!< (@ 0x00000024) Present state                                              */

    struct {
      __IOM uint32_t CMDINHCMD  : 1;            /*!< [0..0] If this bit is 0, it indicates the CMD line is not in
                                                     use and the HC can issue a SD command using the CMD line.
                                                     This bit is set immediately after the Command register
                                                     (00Fh) is written. This bit is cleared when the command
                                                     response is received. Even if the Command Inhibit (DAT)
                                                     is set to 1, Commands using only the CMD line can be issued
                                                     if this bit is 0. Changing from 1 to 0 generates a Command
                                                     complete interrupt in the Normal Interrupt Status register.
                                                     If the HC cannot issue the command because of a comma                     */
      __IOM uint32_t CMDINHDAT  : 1;            /*!< [1..1] This status bit is generated if either the DAT Line Active
                                                     or the Read transfer Active is set to 1. If this bit is
                                                     0, it indicates the HC can issue the next SD command. Commands
                                                     with busy signal belong to Command Inhibit (DAT) (ex. R1b,
                                                     R5b type). Changing from 1 to 0 generates a Transfer Complete
                                                     interrupt in the Normal interrupt status register. Note:
                                                     The SD Host Driver can save registers in the range of 000-00Dh
                                                     for a suspend transaction after this bit has changed from
                                                     1 to 0.                                                                   */
      __IOM uint32_t DLINEACT   : 1;            /*!< [2..2] This bit indicates whether one of the DAT line on SD
                                                     bus is in use.                                                            */
      __IOM uint32_t RETUNINGREQUEST : 1;       /*!< [3..3] Re-Tuning Request Host Controller may request Host Driver
                                                     to execute re-tuning sequence by setting this bit when
                                                     the data window is shifted by temperature drift and a tuned
                                                     sampling point does not have a good margin to receive correct
                                                     data. This bit is cleared when a command is issued with
                                                     setting Execute Tuning in the Host Control 2 register.
                                                     Changing of this bit from 0 to 1 generates Re-Tuning Event.
                                                     Refer to Normal Interrupt registers for more detail. This
                                                     bit isn't set to 1 if Sampling Clock Select in                            */
            uint32_t            : 4;
      __IOM uint32_t WRXFERACT  : 1;            /*!< [8..8] This status indicates a write transfer is active. If
                                                     this bit is 0, it means no valid write data exists in the
                                                     HC. This bit is set in either of the following cases: After
                                                     the end bit of the write command. When writing a 1 to Continue
                                                     Request in the Block Gap Control register to restart a
                                                     write transfer. This bit is cleared in either of the following
                                                     cases: After getting the CRC status of the last data block
                                                     as specified by the transfer count (Single or Multiple)
                                                     After getting a CRC status of any block wher                              */
      __IOM uint32_t RDXFERACT  : 1;            /*!< [9..9] This status is used for detecting completion of a read
                                                     transfer. This bit is set to 1 for either of the following
                                                     conditions: After the end bit of the read command When
                                                     writing a 1 to continue Request in the Block Gap Control
                                                     register to restart a read transfer This bit is cleared
                                                     to 0 for either of the following conditions: When the last
                                                     data block as specified by block length is transferred
                                                     to the system. When all valid data blocks have been transferred
                                                     to the system and no current block transfers are be                       */
      __IOM uint32_t BUFWREN    : 1;            /*!< [10..10] This status is used for non-DMA write transfers. This
                                                     read only flag indicates if space is available for write
                                                     data. If this bit is 1, data can be written to the buffer.
                                                     A change of this bit from 1 to 0 occurs when all the block
                                                     data is written to the buffer. A change of this bit from
                                                     0 to 1 occurs when top of block data can be written to
                                                     the buffer and generates the Buffer Write Ready Interrupt.                */
      __IOM uint32_t BUFRDEN    : 1;            /*!< [11..11] This status is used for non-DMA read transfers. This
                                                     read only flag indicates that valid data exists in the
                                                     host side buffer status. If this bit is 1, readable data
                                                     exists in the buffer. A change of this bit from 1 to 0
                                                     occurs when all the block data is read from the buffer.
                                                     A change of this bit from 0 to 1 occurs when all the block
                                                     data is ready in the buffer and generates the Buffer Read
                                                     Ready Interrupt.                                                          */
            uint32_t            : 4;
      __IOM uint32_t CARDINSERTED : 1;          /*!< [16..16] This bit indicates whether a card has been inserted.
                                                     Changing from 0 to 1 generates a Card Insertion interrupt
                                                     in the Normal Interrupt Status register and changing from
                                                     1 to 0 generates a Card Removal Interrupt in the Normal
                                                     Interrupt Status register. The Software Reset For All in
                                                     the Software Reset register shall not affect this bit.
                                                     If a Card is removed while its power is on and its clock
                                                     is oscillating, the HC shall clear SD Bus Power in the
                                                     Power Control register and SD Clock Enable in the Clock
                                                     contro                                                                    */
      __IOM uint32_t CARDSTABLE : 1;            /*!< [17..17] This bit is used for testing. If it is 0, the Card
                                                     Detect Pin Level is not stable. If this bit is set to 1,
                                                     it means the Card Detect Pin Level is stable. The Software
                                                     Reset For All in the Software Reset Register shall not
                                                     affect this bit.                                                          */
      __IOM uint32_t CARDDET    : 1;            /*!< [18..18] This bit reflects the inverse value of the SDCD# pin.            */
      __IOM uint32_t WRPROTSW   : 1;            /*!< [19..19] The Write Protect Switch is supported for memory and
                                                     combo cards. This bit reflects the SDWP# pin.                             */
      __IOM uint32_t DAT30LINE  : 4;            /*!< [23..20] This status is used to check DAT line level to recover
                                                     from errors, and for debugging. This is especially useful
                                                     in detecting the busy signal level from DAT[0].                           */
      __IOM uint32_t CMDLINE    : 1;            /*!< [24..24] This status is used to check CMD line level to recover
                                                     from errors, and for debugging.                                           */
      __IOM uint32_t DAT74LINE  : 4;            /*!< [28..25] This status is used to check DAT line level to recover
                                                     from errors, and for debugging.                                           */
            uint32_t            : 3;
    } PRESENT_b;
  } ;

  union {
    __IOM uint32_t HOSTCTRL1;                   /*!< (@ 0x00000028) Host control 1                                             */

    struct {
      __IOM uint32_t LEDCONTROL : 1;            /*!< [0..0] This bit is used to caution the user not to remove the
                                                     card while the SD card is being accessed. If the software
                                                     is going to issue multiple SD commands, this bit can be
                                                     set during all transactions. It is not necessary to change
                                                     for each transaction.                                                     */
      __IOM uint32_t DATATRANSFERWIDTH : 1;     /*!< [1..1] (SD1 or SD4) This bit selects the data width of the HC.
                                                     The HD shall select it to match the data width of the SD
                                                     card.                                                                     */
      __IOM uint32_t HISPEEDEN  : 1;            /*!< [2..2] This bit is optional. Before setting this bit, the HD
                                                     shall check the High Speed Support in the capabilities
                                                     register. If this bit is set to 0 (default), the HC outputs
                                                     CMD line and DAT lines at the falling edge of the SD clock
                                                     (up to 25 MHz/ 20MHz for MMC). If this bit is set to 1,
                                                     the HC outputs CMD line and DAT lines at the rising edge
                                                     of the SD clock (up to 50 MHz for SD/52MHz for MMC)/ 208Mhz
                                                     (for SD3.0) If Preset Value Enable in the Host Control
                                                     2 register is set to 1, Host Driver needs to reset SD C                   */
      __IOM uint32_t DMASELECT  : 2;            /*!< [4..3] One of supported DMA modes can be selected. The host
                                                     driver shall check support of DMA modes by referring the
                                                     Capabilities register.                                                    */
      __IOM uint32_t XFERWIDTH  : 1;            /*!< [5..5] This bit controls 8-bit bus width mode for embedded device.
                                                     Support of this function is indicated in 8-bit Support
                                                     for Embedded Device in the Capabilities register. If a
                                                     device supports 8-bit bus mode, this bit may be set to
                                                     1. If this bit is 0, bus width is controlled by Data Transfer
                                                     Width in the Host Control 1 register.This bit is not effective
                                                     when multiple devices are installed on a bus slot (Slot
                                                     Type is set to 10b in the Capabilities register). In this
                                                     case, each device bus width is controlled by Bu                           */
      __IOM uint32_t TESTLEVEL  : 1;            /*!< [6..6] This bit is enabled while the Card Detect Signal Selection
                                                     is set to 1 and it indicates card inserted or not. Generates
                                                     (card ins or card removal) interrupt when the normal int
                                                     sts enable bit is set.                                                    */
      __IOM uint32_t CARDSRC    : 1;            /*!< [7..7] This bit selects source for card detection.                        */
      __IOM uint32_t SDBUSPOWER : 1;            /*!< [8..8] Before setting this bit, the SD host driver shall set
                                                     SD Bus Voltage Select. If the HC detects the No Card State,
                                                     this bit shall be cleared.                                                */
      __IOM uint32_t VOLTSELECT : 3;            /*!< [11..9] By setting these bits, the HD selects the voltage level
                                                     for the SD card. Before setting this register, the HD shall
                                                     check the voltage support bits in the capabilities register.
                                                     If an unsupported voltage is selected, the Host System
                                                     shall not supply SD bus voltage. All voltage select values
                                                     not enumerated here are reserved.                                         */
      __IOM uint32_t HWRESET    : 1;            /*!< [12..12] Hardware reset signal is generated for eMMC card when
                                                     this bit is set                                                           */
            uint32_t            : 3;
      __IOM uint32_t STOPATBLOCKGAPREQUEST : 1; /*!< [16..16] This bit is used to stop executing a transaction at
                                                     the next block gap for non- DMA,SDMA and ADMA transfers.
                                                     Until the transfer complete is set to 1, indicating a transfer
                                                     completion the HD shall leave this bit set to 1. Clearing
                                                     both the Stop At Block Gap Request and Continue Request
                                                     shall not cause the transaction to restart. Read Wait is
                                                     used to stop the read transaction at the block gap. The
                                                     HC shall honour Stop At Block Gap Request for write transfers,
                                                     but for read transfers it requires that the SD ca                         */
      __IOM uint32_t CONTREQ    : 1;            /*!< [17..17] This bit is used to restart a transaction which was
                                                     stopped using the Stop At Block Gap Request. To cancel
                                                     stop at the block gap, set Stop At block Gap Request to
                                                     0 and set this bit to restart the transfer. The HC automatically
                                                     clears this bit in either of the following cases: 1) In
                                                     the case of a read transaction, the DAT Line Active changes
                                                     from 0 to 1 as a read transaction restarts. 2) In the case
                                                     of a write transaction, the Write transfer active changes
                                                     from 0 to 1 as the write transaction restarts. The                        */
      __IOM uint32_t READWAITCTRL : 1;          /*!< [18..18] The read wait function is optional for SDIO cards.
                                                     If the card supports read wait, set this bit to enable
                                                     use of the read wait protocol to stop read data using DAT[2]
                                                     line. Otherwise the HC has to stop the SD clock to hold
                                                     read data, which restricts commands generation. When the
                                                     HD detects an SD card insertion, it shall set this bit
                                                     according to the CCCR of the SDIO card. If the card does
                                                     not support read wait, this bit shall never be set to 1
                                                     otherwise DAT line conflict may occur. If this bit is set
                                                     to 0,                                                                     */
      __IOM uint32_t GAP        : 1;            /*!< [19..19] This bit is valid only in 4-bit mode of the SDIO card
                                                     and selects a sample point in the interrupt cycle. Setting
                                                     to 1 enables interrupt detection at the block gap for a
                                                     multiple block transfer. If the SD card cannot signal an
                                                     interrupt during a multiple block transfer, this bit should
                                                     be set to 0. When the HD detects an SD card insertion,
                                                     it shall set this bit according to the CCCR of the SDIO
                                                     card.                                                                     */
      __IOM uint32_t SPIMODE    : 1;            /*!< [20..20] SPI mode enable bit.                                             */
      __IOM uint32_t BOOTEN     : 1;            /*!< [21..21] To start boot code access                                        */
      __IOM uint32_t ALTBOOTEN  : 1;            /*!< [22..22] To start boot code access in alternative mode.                   */
      __IOM uint32_t BOOTACKCHK : 1;            /*!< [23..23] To check for the boot acknowledge in boot operation.             */
      __IOM uint32_t WUENCARDINT : 1;           /*!< [24..24] This bit enables wakeup event via Card Interrupt assertion
                                                     in the Normal Interrupt Status register. This bit can be
                                                     set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1.                  */
      __IOM uint32_t WUENCARDINSERT : 1;        /*!< [25..25] This bit enables wakeup event via Card Insertion assertion
                                                     in the Normal Interrupt Status register. FN_WUS (Wake up
                                                     Support) in CIS does not affect this bit.                                 */
      __IOM uint32_t WUENCARDREMOVL : 1;        /*!< [26..26] This bit enables wakeup event via Card Removal assertion
                                                     in the Normal Interrupt Status register. FN_WUS (Wake up
                                                     Support) in CIS does not affect this bit.                                 */
            uint32_t            : 5;
    } HOSTCTRL1_b;
  } ;

  union {
    __IOM uint32_t CLOCKCTRL;                   /*!< (@ 0x0000002C) Clock control                                              */

    struct {
      __IOM uint32_t CLKEN      : 1;            /*!< [0..0] This bit is set to 0 when the HD is not using the HC
                                                     or the HC awaits a wakeup event. The HC should stop its
                                                     internal clock to go very low power state. Still, registers
                                                     shall be able to be read and written. Clock starts to oscillate
                                                     when this bit is set to 1. When clock oscillation is stable,
                                                     the HC shall set Internal Clock Stable in this register
                                                     to 1. This bit shall not affect card detection.                           */
      __IOM uint32_t CLKSTABLE  : 1;            /*!< [1..1] This bit is set to 1 when SD clock is stable after writing
                                                     to Internal Clock Enable in this register to 1. The SD
                                                     Host Driver shall wait to set SD Clock Enable until this
                                                     bit is set to 1. Note: This is useful when using PLL for
                                                     a clock oscillator that requires setup time.                              */
      __IOM uint32_t SDCLKEN    : 1;            /*!< [2..2] The HC shall stop SDCLK when writing this bit to 0. SDCLK
                                                     frequency Select can be changed when this bit is 0. Then,
                                                     the HC shall maintain the same clock frequency until SDCLK
                                                     is stopped (Stop at SDCLK = 0). If the HC detects the No
                                                     Card state, this bit shall be cleared.                                    */
            uint32_t            : 2;
      __IOM uint32_t CLKGENSEL  : 1;            /*!< [5..5] This bit is used to select the clock generator mode in
                                                     SDCLK Frequency Select. If the Programmable Clock Mode
                                                     is supported (non-zero value is set to Clock Multiplier
                                                     in the Capabilities register), this bit attribute is RW,
                                                     and if not supported, this bit attribute is RO and zero
                                                     is read. This bit depends on the setting of Preset Value
                                                     Enable in the Host Control 2 register. If the Preset Value
                                                     Enable = 0, this bit is set by Host Driver. If the Preset
                                                     Value Enable = 1, this bit is automatically set to a value                */
      __IOM uint32_t UPRCLKDIV  : 2;            /*!< [7..6] Bit 07-06 is assigned to bit 09-08 of clock divider in
                                                     SDCLK Frequency Select                                                    */
      __IOM uint32_t FREQSEL    : 8;            /*!< [15..8] This register is used to select the frequency of the
                                                     SDCLK pin. The frequency is not programmed directly; rather
                                                     this register holds the divisor of the Base Clock Frequency
                                                     For SD clock in the capabilities register. Only the following
                                                     settings are allowed. (1) 8-bit Divided Clock Mode Setting
                                                     00h specifies the highest frequency of the SD Clock. When
                                                     setting multiple bits, the most significant bit is used
                                                     as the divisor. But multiple bits should not be set. The
                                                     two default divider values can be calculated b                            */
      __IOM uint32_t TIMEOUTCNT : 4;            /*!< [19..16] This value determines the interval by which DAT line
                                                     time-outs are detected. Refer to the Data Time-out Error
                                                     in the Error Interrupt Status register for information
                                                     on factors that dictate time-out generation. Time-out clock
                                                     frequency will be generated by dividing the sdclockTMCLK
                                                     by this value. When setting this register, prevent inadvertent
                                                     time-out events by clearing the Data Time-out Error Status
                                                     Enable (in the Error Interrupt Status Enable register)
                                                     At the initialization of the HC, the HD shall set th                      */
            uint32_t            : 4;
      __IOM uint32_t SWRSTALL   : 1;            /*!< [24..24] This reset affects the entire HC except for the card
                                                     detection circuit. Register bits of type ROC, RW, RW1C,
                                                     RWAC are cleared to 0. During its initialization, the HD
                                                     shall set this bit to 1 to reset the HC. The HC shall reset
                                                     this bit to 0 when capabilities registers are valid and
                                                     the HD can read them. Additional use of Software Reset
                                                     For All may not affect the value of the Capabilities registers.
                                                     If this bit is set to 1, the SD card shall reset itself
                                                     and must be re initialized by the HD. A reset pulse is                    */
      __IOM uint32_t SWRSTCMD   : 1;            /*!< [25..25] Only part of command circuit is reset. The following
                                                     registers and bits are cleared by this bit: Present State
                                                     register Command Inhibit (CMD) Normal Interrupt Status
                                                     register Command Complete                                                 */
      __IOM uint32_t SWRSTDAT   : 1;            /*!< [26..26] Only part of data circuit is reset. The following registers
                                                     and bits are cleared by this bit: Buffer Data Port Register
                                                     Buffer is cleared and Initialized. Present State register
                                                     Buffer read Enable Buffer write Enable Read Transfer Active
                                                     Write Transfer Active DAT Line Active Command Inhibit (DAT)
                                                     Block Gap Control register Continue Request Stop At Block
                                                     Gap Request Normal Interrupt Status register Buffer Read
                                                     Ready Buffer Write Ready Block Gap Event Transfer Complete                */
            uint32_t            : 5;
    } CLOCKCTRL_b;
  } ;

  union {
    __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000030) Interrupt enable                                           */

    struct {
      __IOM uint32_t COMMANDCOMPLETE : 1;       /*!< [0..0] This bit is set when we get the end bit of the command
                                                     response (Except Auto CMD12 and Auto CMD23) Note: Command
                                                     Time-out Error has higher priority than Command Complete.
                                                     If both are set to 1, it can be considered that the response
                                                     was not received correctly.                                               */
      __IOM uint32_t TRANSFERCOMPLETE : 1;      /*!< [1..1] This bit is set when a read / write transaction is completed.
                                                     Read Transaction: This bit is set at the falling edge of
                                                     Read Transfer Active Status. There are two cases in which
                                                     the Interrupt is generated. The first is when a data transfer
                                                     is completed as specified by data length (After the last
                                                     data has been read to the Host System). The second is when
                                                     data has stopped at the block gap and completed the data
                                                     transfer by setting the Stop At Block Gap Request in the
                                                     Block Gap Control Register (After valid da                                */
      __IOM uint32_t BLOCKGAPEVENT : 1;         /*!< [2..2] If the Stop At Block Gap Request in the Block Gap Control
                                                     Register is set, this bit is set. Read Transaction: This
                                                     bit is set at the falling edge of the DAT Line Active Status
                                                     (When the transaction is stopped at SD Bus timing. The
                                                     Read Wait must be supported inorder to use this function).
                                                     Write Transaction: This bit is set at the falling edge
                                                     of Write Transfer Active Status (After getting CRC status
                                                     at SD Bus timing).                                                        */
      __IOM uint32_t DMAINTERRUPT : 1;          /*!< [3..3] This status is set if the HC detects the Host DMA Buffer
                                                     Boundary in the Block Size regiser.                                       */
      __IOM uint32_t BUFFERWRITEREADY : 1;      /*!< [4..4] This status is set if the Buffer Write Enable changes
                                                     from 0 to 1.                                                              */
      __IOM uint32_t BUFFERREADREADY : 1;       /*!< [5..5] This status is set if the Buffer Read Enable changes
                                                     from 0 to 1. Buffer Read Ready is set to 1 for every CMD19
                                                     execution in tuning procedure.                                            */
      __IOM uint32_t CARDINSERTION : 1;         /*!< [6..6] This status is set if the Card Inserted in the Present
                                                     State register changes from 0 to 1. When the HD writes
                                                     this bit to 1 to clear this status the status of the Card
                                                     Inserted in the Present State register should be confirmed.
                                                     Because the card detect may possibly be changed when the
                                                     HD clear this bit an Interrupt event may not be generated.                */
      __IOM uint32_t CARDREMOVAL : 1;           /*!< [7..7] This status is set if the Card Inserted in the Present
                                                     State register changes from 1 to 0. When the HD writes
                                                     this bit to 1 to clear this status the status of the Card
                                                     Inserted in the Present State register should be confirmed.
                                                     Because the card detect may possibly be changed when the
                                                     HD clear this bit an Interrupt event may not be generated.                */
      __IOM uint32_t CARDINTERRUPT : 1;         /*!< [8..8] Writing this bit to 1 does not clear this bit. It is
                                                     cleared by resetting the SD card interrupt factor. In 1-bit
                                                     mode, the HC shall detect the Card Interrupt without SD
                                                     Clock to support wakeup. In 4-bit mode, the card interrupt
                                                     signal is sampled during the interrupt cycle, so there
                                                     are some sample delays between the interrupt signal from
                                                     the card and the interrupt to the Host system. when this
                                                     status has been set and the HD needs to start this interrupt
                                                     service, Card Interrupt Status Enable in the Normal I                     */
      __IOM uint32_t INTA       : 1;            /*!< [9..9] This status is set if INT_A is enabled and INT_A# pin
                                                     is in low level. Writing this bit to 1 does not clear this
                                                     bit. It is cleared by resetting the INT_A interrupt factor                */
      __IOM uint32_t INTB       : 1;            /*!< [10..10] This status is set if INT_B is enabled and INT_B# pin
                                                     is in low level. Writing this bit to 1 does not clear this
                                                     bit. It is cleared by resetting the INT_B interrupt factor                */
      __IOM uint32_t INTC       : 1;            /*!< [11..11] This status is set if INT_C is enabled and INT_C# pin
                                                     is in low level. Writing this bit to 1 does not clear this
                                                     bit. It is cleared by resetting the INT_C interrupt factor                */
      __IOM uint32_t RETUNINGEVENT : 1;         /*!< [12..12] This status is set if Re-Tuning Request in the Present
                                                     State register changes from 0 to 1. Host Controller requests
                                                     Host Driver to perform re-tuning for next data transfer.
                                                     Current data transfer (not large block count) can be completed
                                                     without re-tuning.                                                        */
      __IOM uint32_t BOOTACKRCV : 1;            /*!< [13..13] This status is set if the boot acknowledge is received
                                                     from device.                                                              */
      __IOM uint32_t BOOTTERMINATE : 1;         /*!< [14..14] Interrupt This status is set if the boot operation
                                                     get terminated                                                            */
      __IOM uint32_t ERRORINTERRUPT : 1;        /*!< [15..15] If any of the bits in the Error Interrupt Status Register
                                                     are set, then this bit is set. Therefore the HD can test
                                                     for an error by checking this bit first.                                  */
      __IOM uint32_t COMMANDTIMEOUTERROR : 1;   /*!< [16..16] Command CRC Error is generated in two cases. 1. If
                                                     a response is returned and the Command Time-out Error is
                                                     set to 0, this bit is set to 1 when detecting a CRT error
                                                     in the command response 2. The HC detects a CMD line conflict
                                                     by monitoring the CMD line when a command is issued. If
                                                     the HC drives the CMD line to 1 level, but detects 0 level
                                                     on the CMD line at the next SDCLK edge, then the HC shall
                                                     abort the command (Stop driving CMD line) and set this
                                                     bit to 1. The Command Timeout Error shall also be set t                   */
      __IOM uint32_t COMMANDCRCERROR : 1;       /*!< [17..17] Occurs when detecting that the end bit of a command
                                                     response is 0.                                                            */
      __IOM uint32_t COMMANDENDBITERROR : 1;    /*!< [18..18] Occurs only if the no response is returned within 64
                                                     SDCLK cycles from the end bit of the command. If the HC
                                                     detects a CMD line conflict, in which case Command CRC
                                                     Error shall also be set. This bit shall be set without
                                                     waiting for 64 SDCLK cycles because the command will be
                                                     aborted by the HC.                                                        */
      __IOM uint32_t COMMANDINDEXERROR : 1;     /*!< [19..19] Occurs if a Command Index error occurs in the Command
                                                     Response.                                                                 */
      __IOM uint32_t DATATIMEOUTERROR : 1;      /*!< [20..20] Occurs when detecting one of following timeout conditions.
                                                     1. Busy Timeout for R1b, R5b type. 2. Busy Timeout after
                                                     Write CRC status 3. Write CRC status Timeout 4. Read Data
                                                     Timeout                                                                   */
      __IOM uint32_t DATACRCERROR : 1;          /*!< [21..21] Occurs when detecting CRC error when transferring read
                                                     data which uses the DAT line or when detecting the Write
                                                     CRC Status having a value of other than 0.                                */
      __IOM uint32_t DATAENDBITERROR : 1;       /*!< [22..22] Occurs when detecting 0 at the end bit position of
                                                     read data which uses the DAT line or the end bit position
                                                     of the CRC status.                                                        */
      __IOM uint32_t CURRENTLIMITERROR : 1;     /*!< [23..23] By setting the SD Bus Power bit in the Power Control
                                                     Register, the HC is requested to supply power for the SD
                                                     Bus. If the HC supports the Current Limit Function, it
                                                     can be protected from an Illegal card by stopping power
                                                     supply to the card in which case this bit indicates a failure
                                                     status. Reading 1 means the HC is not supplying power to
                                                     SD card due to some failure. Reading 0 means that the HC
                                                     is supplying power and no error has occurred. This bit
                                                     shall always set to be 0, if the HC does not support this
                                                     f                                                                         */
      __IOM uint32_t AUTOCMDERROR : 1;          /*!< [24..24] Auto CMD12 and Auto CMD23 use this error status. This
                                                     bit is set when detecting that one of the bits D00-D04
                                                     in Auto CMD Error Status register has changed from 0 to
                                                     1. In case of Auto CMD12, this bit is set to 1, not only
                                                     when the errors in Auto CMD12 occur but also when Auto
                                                     CMD12 is not executed due to the previous command error.                  */
      __IOM uint32_t ADMAERROR  : 1;            /*!< [25..25] This bit is set when the Host Controller detects errors
                                                     during ADMA based data transfer. The state of the ADMA
                                                     at an error occurrence is saved in the ADMA Error Status
                                                     Register.                                                                 */
            uint32_t            : 2;
      __IOM uint32_t TGTRESPERR : 1;            /*!< [28..28] Occurs when detecting error in aximst_bresp or aximst_rresp      */
      __IOM uint32_t VNDERRSTAT : 3;            /*!< [31..29] Vendor specific error status.                                    */
    } INTSTAT_b;
  } ;

  union {
    __IOM uint32_t INTENABLE;                   /*!< (@ 0x00000034) Normal interrupt status enable                             */

    struct {
      __IOM uint32_t COMMANDCOMPLETESTATUSENABLE : 1;/*!< [0..0] Description                                                   */
      __IOM uint32_t TRANSFERCOMPLETESTATUSENABLE : 1;/*!< [1..1] Description                                                  */
      __IOM uint32_t BLOCKGAPEVENTSTATUSENABLE : 1;/*!< [2..2] Description                                                     */
      __IOM uint32_t DMAINTERRUPTSTATUSENABLE : 1;/*!< [3..3] Description                                                      */
      __IOM uint32_t BUFFERWRITEREADYSTATUSENABLE : 1;/*!< [4..4] Description                                                  */
      __IOM uint32_t BUFFERREADREADYSTATUSENABLE : 1;/*!< [5..5] Description                                                   */
      __IOM uint32_t CARDINSERTIONSTATUSENABLE : 1;/*!< [6..6] Description                                                     */
      __IOM uint32_t CARDREMOVALSTATUSENABLE : 1;/*!< [7..7] Description                                                       */
      __IOM uint32_t CARDINTERRUPTSTATUSENABLE : 1;/*!< [8..8] If this bit is set to 0, the HC shall clear Interrupt
                                                     request to the System. The Card Interrupt detection is
                                                     stopped when this bit is cleared and restarted when this
                                                     bit is set to 1. The HD may clear the Card Interrupt Status
                                                     Enable before servicing the Card Interrupt and may set
                                                     this bit again after all Interrupt requests from the card
                                                     are cleared to prevent inadvertent Interrupts.                            */
      __IOM uint32_t INTASTATUSENABLE : 1;      /*!< [9..9] If this bit is set to 0, the Host Controller shall clear
                                                     the interrupt request to the System. The Host Driver may
                                                     clear this bit before servicing the INT_A and may set this
                                                     bit again after all interrupt requests to INT_A pin are
                                                     cleared to prevent inadvertent interrupts.                                */
      __IOM uint32_t INTBSTATUSENABLE : 1;      /*!< [10..10] If this bit is set to 0, the Host Controller shall
                                                     clear the interrupt request to the System. The Host Driver
                                                     may clear this bit before servicing the INT_B and may set
                                                     this bit again after all interrupt requests to INT_B pin
                                                     are cleared to prevent inadvertent interrupts.                            */
      __IOM uint32_t INTCSTATUSENABLE : 1;      /*!< [11..11] If this bit is set to 0, the Host Controller shall
                                                     clear the interrupt request to the System. The Host Driver
                                                     may clear this bit before servicing the INT_C and may set
                                                     this bit again after all interrupt requests to INT_C pin
                                                     are cleared to prevent inadvertent interrupts. Interrupt
                                                     enable                                                                    */
      __IOM uint32_t RETUNINGEVENTSTATUSENABLE : 1;/*!< [12..12] Interrupt                                                     */
      __IOM uint32_t BOOTACKRCVENABLE : 1;      /*!< [13..13] Interrupt                                                        */
      __IOM uint32_t BOOTTERMINATE : 1;         /*!< [14..14] Boot is terminated?                                              */
      __IOM uint32_t FIXEDTO0   : 1;            /*!< [15..15] The HC shall control error Interrupts using the Error
                                                     Interrupt Status Enable register.                                         */
      __IOM uint32_t COMMANDTIMEOUTERRORSTATUSENABLE : 1;/*!< [16..16] Desc                                                    */
      __IOM uint32_t COMMANDCRCERRORSTATUSENABLE : 1;/*!< [17..17] Desc                                                        */
      __IOM uint32_t COMMANDENDBITERRORSTATUSENABLE : 1;/*!< [18..18] Desc                                                     */
      __IOM uint32_t COMMANDINDEXERRORSTATUSENABLE : 1;/*!< [19..19] Desc                                                      */
      __IOM uint32_t DATATIMEOUTERRORSTATUSENABLE : 1;/*!< [20..20] Desc                                                       */
      __IOM uint32_t DATACRCERRORSTATUSENABLE : 1;/*!< [21..21] Desc                                                           */
      __IOM uint32_t DATAENDBITERRORSTATUSENABLE : 1;/*!< [22..22] Desc                                                        */
      __IOM uint32_t CURRENTLIMITERRORSTATUSENABLE : 1;/*!< [23..23] Desc                                                      */
      __IOM uint32_t AUTOCMD12ERRORSTATUSENABLE : 1;/*!< [24..24] Desc                                                         */
      __IOM uint32_t ADMAERRORSTATUSENABLE : 1; /*!< [25..25] Desc                                                             */
      __IOM uint32_t TUNINGERRORSTATUS : 1;     /*!< [26..26] enable                                                           */
            uint32_t            : 1;
      __IOM uint32_t TGTRESPERRHOSTERRSTATEN : 1;/*!< [28..28] Desc                                                            */
      __IOM uint32_t VENDORSPECIFICERRORSTATUSENABLE : 3;/*!< [31..29] Vendor-specific error status enable.                    */
    } INTENABLE_b;
  } ;

  union {
    __IOM uint32_t INTSIG;                      /*!< (@ 0x00000038) Normal interrupt signal enable                             */

    struct {
      __IOM uint32_t CMDCMPEN   : 1;            /*!< [0..0] Interrupt                                                          */
      __IOM uint32_t XFERCMPEN  : 1;            /*!< [1..1] Interrupt                                                          */
      __IOM uint32_t BLOCKGAPEN : 1;            /*!< [2..2] Interrupt                                                          */
      __IOM uint32_t DMAINTEN   : 1;            /*!< [3..3] Interrupt                                                          */
      __IOM uint32_t BUFFERWREN : 1;            /*!< [4..4] Interrupt                                                          */
      __IOM uint32_t BUFFERRDEN : 1;            /*!< [5..5] Interrupt                                                          */
      __IOM uint32_t CARDINSERTEN : 1;          /*!< [6..6] Interrupt                                                          */
      __IOM uint32_t CARDREMOVALEN : 1;         /*!< [7..7] Interrupt                                                          */
      __IOM uint32_t CARDINTEN  : 1;            /*!< [8..8] Interrupt                                                          */
      __IOM uint32_t INTAEN     : 1;            /*!< [9..9] Interrupt                                                          */
      __IOM uint32_t INTBEN     : 1;            /*!< [10..10] Interrupt                                                        */
      __IOM uint32_t INTCEN     : 1;            /*!< [11..11] Interrupt                                                        */
      __IOM uint32_t RETUNEEVENTEN : 1;         /*!< [12..12] Interrupt signal enable                                          */
      __IOM uint32_t BOOTACKEN  : 1;            /*!< [13..13] Interrupt                                                        */
      __IOM uint32_t BOOTTERM   : 1;            /*!< [14..14] Boot terminate interrupt signal enable                           */
      __IOM uint32_t FIXED0     : 1;            /*!< [15..15] Fixed to 0. The HD shall control error Interrupts using
                                                     the Error Interrupt Signal Enable register.                               */
      __IOM uint32_t CMDTOERREN : 1;            /*!< [16..16] Desc                                                             */
      __IOM uint32_t CMDCRCERREN : 1;           /*!< [17..17] Desc                                                             */
      __IOM uint32_t CMDENDBITERREN : 1;        /*!< [18..18] Desc                                                             */
      __IOM uint32_t CMDIDXERREN : 1;           /*!< [19..19] Desc                                                             */
      __IOM uint32_t DATATOERROREN : 1;         /*!< [20..20] Desc                                                             */
      __IOM uint32_t DATACRCERREN : 1;          /*!< [21..21] Desc                                                             */
      __IOM uint32_t DATAENDERREN : 1;          /*!< [22..22] Desc                                                             */
      __IOM uint32_t CURRLMTERREN : 1;          /*!< [23..23] Desc                                                             */
      __IOM uint32_t AUTOCMD12ERREN : 1;        /*!< [24..24] Desc                                                             */
      __IOM uint32_t ADMAERREN  : 1;            /*!< [25..25] Desc                                                             */
      __IOM uint32_t TUNINGERREN : 1;           /*!< [26..26] Desc                                                             */
            uint32_t            : 1;
      __IOM uint32_t TGTRESPEN  : 1;            /*!< [28..28] Interrupt                                                        */
      __IOM uint32_t VNDERREN   : 3;            /*!< [31..29] VNDERREN field description needed here.                          */
    } INTSIG_b;
  } ;

  union {
    __IOM uint32_t AUTO;                        /*!< (@ 0x0000003C) Auto CMD error status                                      */

    struct {
      __IOM uint32_t CMD12NOTEXEC : 1;          /*!< [0..0] If memory multiple block data transfer is not started
                                                     due to command error, this bit is not set because it is
                                                     not necessary to issue Auto CMD12. Setting this bit to
                                                     1 means the HC cannot issue Auto CMD12 to stop memory multiple
                                                     block transfer due to some error. If this bit is set to
                                                     1, other error status bits (D04 - D01) are meaningless.
                                                     This bit is set to 0 when Auto CMD Error is generated by
                                                     Auto CMD23                                                                */
      __IOM uint32_t CMDTOERR   : 1;            /*!< [1..1] Occurs if the no response is returned within 64 SDCLK
                                                     cycles from the end bit of the command. If this bit is
                                                     set to 1, the other error status bits (D04 - D02) are meaningless.        */
      __IOM uint32_t CMDCRCERR  : 1;            /*!< [2..2] Occurs when detecting a CRC error in the command response.         */
      __IOM uint32_t CMDENDERR  : 1;            /*!< [3..3] Occurs when detecting that the end bit of command response
                                                     is 0.                                                                     */
      __IOM uint32_t CMDIDXERR  : 1;            /*!< [4..4] Occurs if the Command Index error occurs in response
                                                     to a command.                                                             */
            uint32_t            : 2;
      __IOM uint32_t NOTAUTOCMD12ERR : 1;       /*!< [7..7] Setting this bit to 1 means CMD_wo_DAT is not executed
                                                     due to an Auto CMD12 error (D04 - D01) in this register.
                                                     This bit is set to 0 when Auto CMD Error is generated by
                                                     Auto CMD23                                                                */
            uint32_t            : 8;
      __IOM uint32_t UHSMODESEL : 3;            /*!< [18..16] This field is used to select one of UHS-I modes and
                                                     effective when 1.8V Signaling Enable is set to 1. If Preset
                                                     Value Enable in the Host Control 2 register is set to 1,
                                                     Host Controller sets SDCLK Frequency Select, Clock Generator
                                                     Select in the Clock Control register and Driver Strength
                                                     Select according to Preset Value registers. In this case,
                                                     one of preset value registers is selected by this field.
                                                     Host Driver needs to reset SD Clock Enable before changing
                                                     this field to avoid generating clock glitch. After                        */
      __IOM uint32_t SIGNALVOLT : 1;            /*!< [19..19] This bit controls voltage regulator for I/O cell. 3.3V
                                                     is supplied to the card regardless of signaling voltage.
                                                     Setting this bit from 0 to 1 starts changing signal voltage
                                                     from 3.3V to 1.8V. 1.8V regulator output shall be stable
                                                     within 5ms. Host Controller clears this bit if switching
                                                     to 1.8V signaling fails. Clearing this bit from 1 to 0
                                                     starts changing signal voltage from 1.8V to 3.3V. 3.3V
                                                     regulator output shall be stable within 5ms. Host Driver
                                                     can set this bit to 1 when Host Controller supports 1.8V
                                                     s                                                                         */
      __IOM uint32_t DRVRSTRSEL : 2;            /*!< [21..20] Host Controller output driver in 1.8V signaling is
                                                     selected by this bit. In 3.3V signaling, this field is
                                                     not effective. This field can be set depends on Driver
                                                     Type A, C and D support bits in the Capabilities register.
                                                     This bit depends on setting of Preset Value Enable. If
                                                     Preset Value Enable = 0, this field is set by Host Driver.
                                                     If Preset Value Enable = 1, this field is automatically
                                                     set by a value specified in the one of Preset Value registers.            */
      __IOM uint32_t STARTTUNING : 1;           /*!< [22..22] This bit is set to 1 to start tuning procedure and
                                                     automatically cleared when tuning procedure is completed.
                                                     The result of tuning is indicated to Sampling Clock Select.
                                                     Tuning procedure is aborted by writing 0 for more detail
                                                     about tuning procedure.                                                   */
      __IOM uint32_t SAMPLCLKSEL : 1;           /*!< [23..23] This bit is set by tuning procedure when Execute Tuning
                                                     is cleared. Writing 1 to this bit is meaningless and ignored.
                                                     Setting 1 means that tuning is completed successfully and
                                                     setting 0 means that tuning is failed. Host Controller
                                                     uses this bit to select sampling clock to receive CMD and
                                                     DAT. This bit is cleared by writing 0. Change of this bit
                                                     is not allowed while the Host Controller is receiving response
                                                     or a read data block.                                                     */
            uint32_t            : 6;
      __IOM uint32_t ASYNCINTEN : 1;            /*!< [30..30] This bit can be set to 1 if a card support asynchronous
                                                     interrupt and Asynchronous Interrupt Support is set to
                                                     1 in the Capabilities register. Asynchronous interrupt
                                                     is effective when DAT[1] interrupt is used in 4-bit SD
                                                     mode (and zero is set to Interrupt Pin Select in the Shared
                                                     Bus Control register). If this bit is set to 1, the Host
                                                     Driver can stop the SDCLK during asynchronous interrupt
                                                     period to save power. During this period, the Host Controller
                                                     continues to deliver Card Interrupt to the host when it                   */
      __IOM uint32_t PRESETEN   : 1;            /*!< [31..31] Host Controller Version 3.00 supports this bit. As
                                                     the operating SDCLK frequency and I/O driver strength depend
                                                     on the Host System implementation, it is difficult to determine
                                                     these parameters in the Standard Host Driver. When Preset
                                                     Value Enable is set to automatic. This bit enables the
                                                     functions defined in the Preset Value registers. If this
                                                     bit is set to 0, SDCLK Frequency Select, Clock Generator
                                                     Select in the Clock Control register and Driver Strength
                                                     Select in Host Control 2 register are set by Host D                       */
    } AUTO_b;
  } ;

  union {
    __IOM uint32_t CAPABILITIES0;               /*!< (@ 0x00000040) Capabilities                                               */

    struct {
      __IOM uint32_t TOCLKFREQ  : 6;            /*!< [5..0] This bit shows the base clock frequency used to detect
                                                     Data Timeout Error. Not 0 - 1Khz to 63Khz or 1Mhz to 63Mhz
                                                     Note: The Host System shall support at least one of these
                                                     voltages above. The HD sets the SD Bus Voltage Select in
                                                     Power Control register according to these support bits.
                                                     If multiple voltages are supported, select the usable lower
                                                     voltage by comparing the OCR value from the card. These
                                                     registers indicate maximum current capability for each
                                                     voltage. The value is meaningful if Voltage Support is
                                                                                                                               */
            uint32_t            : 1;
      __IOM uint32_t TOCLKUNIT  : 1;            /*!< [7..7] This bit shows the unit of base clock frequency used
                                                     to detect Data Timeout Error.                                             */
      __IOM uint32_t SDCLKFREQ  : 8;            /*!< [15..8] 6-bit Base Clock Frequency This mode is supported by
                                                     the Host Controller Version 1.00 and 2.00. Upper 2-bit
                                                     is not effective and always 0. Unit values are 1MHz. The
                                                     supported clock range is 10MHz to 63MHz. 11xx xxxxb Not
                                                     supported 0011 1111b 63MHz 0000 0010b 2MHz 0000 0001b 1MHz
                                                     0000 0000b Get information via another method (2) 8-bit
                                                     Base Clock Frequency This mode is supported by the Host
                                                     Controller Version 3.00.Unit values are 1MHz. The supported
                                                     clock range is 10MHz to 255MHz. FFh 255MHz 02h 2MHz 01h
                                                     1MH                                                                       */
      __IOM uint32_t MAXBLKLEN  : 2;            /*!< [17..16] This value indicates the maximum block size that the
                                                     HD can read and write to the buffer in the HC. The buffer
                                                     shall transfer this block size without wait cycles. Three
                                                     sizes can be defined as indicated below.                                  */
      __IOM uint32_t EXTMEDIA   : 1;            /*!< [18..18] This bit indicates whether the Host Controller is capable
                                                     of using 8-bit bus width mode. This bit is not effective
                                                     when Slot Type is set to 10b. In this case, refer to Bus
                                                     Width Preset in the Shared Bus resister. Supported                        */
      __IOM uint32_t ADMA2      : 1;            /*!< [19..19] Desc                                                             */
            uint32_t            : 1;
      __IOM uint32_t HIGHSPEED  : 1;            /*!< [21..21] This bit indicates whether the HC and the Host System
                                                     support High Speed mode and they can supply SD Clock frequency
                                                     from 25Mhz to 50 Mhz (for SD)/ 20MHz to 52MHz (for MMC).                  */
      __IOM uint32_t SDMA       : 1;            /*!< [22..22] This bit indicates whether the HC is capable of using
                                                     DMA to transfer data between system memory and the HC directly.           */
      __IOM uint32_t SUSPRES    : 1;            /*!< [23..23] This bit indicates whether the HC supports Suspend
                                                     / Resume functionality. If this bit is 0, the Suspend and
                                                     Resume mechanism are not supported and the HD shall not
                                                     issue either Suspend / Resume commands.                                   */
      __IOM uint32_t VOLT33V    : 1;            /*!< [24..24] Desc                                                             */
      __IOM uint32_t VOLT30V    : 1;            /*!< [25..25] Voltage support 3.0v                                             */
      __IOM uint32_t VOLT18V    : 1;            /*!< [26..26] Voltage support 1.8v                                             */
            uint32_t            : 1;
      __IOM uint32_t SYSBUS64   : 1;            /*!< [28..28] Desc                                                             */
      __IOM uint32_t ASYNCINT   : 1;            /*!< [29..29] Refer to SDIO Specification Version 3.00 about asynchronous
                                                     interrupt.                                                                */
      __IOM uint32_t SLOTTYPE   : 2;            /*!< [31..30] This field indicates usage of a slot by a specific
                                                     Host System. (A host controller register set is defined
                                                     per slot.) Embedded slot for one device (01b) means that
                                                     only one non-removable device is connected to a SD bus
                                                     slot. Shared Bus Slot (10b) can be set if Host Controller
                                                     supports Shared Bus Control register. The Standard Host
                                                     Driver controls only a removable card or one embedded device
                                                     is connected to a SD bus slot. If a slot is configured
                                                     for shared bus (10b), the Standard Host Driver does not
                                                     contro                                                                    */
    } CAPABILITIES0_b;
  } ;

  union {
    __IOM uint32_t CAPABILITIES1;               /*!< (@ 0x00000044) Capabilities                                               */

    struct {
      __IOM uint32_t SDR50      : 1;            /*!< [0..0] 1- SDR50 is Supported                                              */
      __IOM uint32_t SDR104     : 1;            /*!< [1..1] 1- SDR104 is Supported                                             */
      __IOM uint32_t DDR50      : 1;            /*!< [2..2] DDR50 field description needed here.                               */
            uint32_t            : 1;
      __IOM uint32_t TYPEA      : 1;            /*!< [4..4] This bit indicates support of Driver Type A for 1.8 Signaling.     */
      __IOM uint32_t TYPEC      : 1;            /*!< [5..5] This bit indicates support of Driver Type C for 1.8 Signaling.     */
      __IOM uint32_t TYPED      : 1;            /*!< [6..6] Reserved This bit indicates support of Driver Type D
                                                     for 1.8 Signaling.                                                        */
            uint32_t            : 1;
      __IOM uint32_t RETUNINGTMRCNT : 4;        /*!< [11..8] This field indicates an initial value of the Re-Tuning
                                                     Timer for Re-Tuning Mode 1 to 3. 0h - Get information via
                                                     other source.                                                             */
            uint32_t            : 1;
      __IOM uint32_t TUNINGSDR50 : 1;           /*!< [13..13] If this bit is set to 1, this Host Controller requires
                                                     tuning to operate SDR50. (Tuning is always required to
                                                     operate SDR104.)                                                          */
      __IOM uint32_t RETUNINGMODES : 2;         /*!< [15..14] This field defines the re-tuning capability of a Host
                                                     Controller and how to manage the data transfer length and
                                                     a Re-Tuning Timer by the Host Driver There are two re-tuning
                                                     timings: Re-Tuning Request and expiration of a Re-Tuning
                                                     Timer. By receiving either timing, the Host Driver executes
                                                     the re-tuning procedure just before a next command issue                  */
      __IOM uint32_t CLKMULT    : 8;            /*!< [23..16] This field indicates clock multiplier value of programmable
                                                     clock generator. Refer to Clock Control register. Setting
                                                     00h means that Host Controller does not support programmable
                                                     clock generator. The multiplier is (CLKMULT+1).                           */
      __IOM uint32_t SPIMODE    : 1;            /*!< [24..24] Spi mode                                                         */
      __IOM uint32_t SPIBLOCKMODE : 1;          /*!< [25..25] Spi block mode                                                   */
            uint32_t            : 6;
    } CAPABILITIES1_b;
  } ;

  union {
    __IOM uint32_t MAXIMUM0;                    /*!< (@ 0x00000048) Maximum current capabilities                               */

    struct {
      __IOM uint32_t ALLBITSRSVD : 32;          /*!< [31..0] The entire 32-bits of this register are reserved, do
                                                     not read or write.                                                        */
    } MAXIMUM0_b;
  } ;

  union {
    __IOM uint32_t MAXIMUM1;                    /*!< (@ 0x0000004C) Maximum current capabilities                               */

    struct {
      __IOM uint32_t MAXCURR33V : 8;            /*!< [7..0] Maximum Current for 3.3V. The current value is specified
                                                     as MAXCURR18V * 4mA. Some example enums follow:                           */
      __IOM uint32_t MAXCURR30V : 8;            /*!< [15..8] Maximum Current for 3.0V. The current value is specified
                                                     as MAXCURR18V * 4mA. Some example enums follow:                           */
      __IOM uint32_t MAXCURR18V : 8;            /*!< [23..16] Maximum Current for 1.8V. The current value is specified
                                                     as MAXCURR18V * 4mA. Some example enums follow:                           */
            uint32_t            : 8;
    } MAXIMUM1_b;
  } ;

  union {
    __IOM uint32_t FORCE;                       /*!< (@ 0x00000050) Force event register for error interrupt status            */

    struct {
      __IOM uint32_t FORCEACMD12NOT : 1;        /*!< [0..0] Description                                                        */
      __IOM uint32_t FORCEACMDTOERR : 1;        /*!< [1..1] Description                                                        */
      __IOM uint32_t FORCEACMDCRCERR : 1;       /*!< [2..2] Description                                                        */
      __IOM uint32_t FORCEACMDENDERR : 1;       /*!< [3..3] Description                                                        */
      __IOM uint32_t FORCEACMDIDXERR : 1;       /*!< [4..4] Desc                                                               */
            uint32_t            : 2;
      __IOM uint32_t FORCEACMDISSUEDERR : 1;    /*!< [7..7] 1 - Interrupt is generated                                         */
            uint32_t            : 8;
      __IOM uint32_t FORCECMDTOERR : 1;         /*!< [16..16] Force Event for Command Timeout Error                            */
      __IOM uint32_t FORCECMDCRCERR : 1;        /*!< [17..17] Force Event for Command CRC Error                                */
      __IOM uint32_t FORCECMDENDERR : 1;        /*!< [18..18] Force Event for Command End Bit Error                            */
      __IOM uint32_t FORCECMDIDXERR : 1;        /*!< [19..19] Force Event for Command Index Error                              */
      __IOM uint32_t FORCEDATATOERR : 1;        /*!< [20..20] Force Event for Data Timeout Error                               */
      __IOM uint32_t FORCEDATACRCERR : 1;       /*!< [21..21] Force Event for Data CRC Error                                   */
      __IOM uint32_t FORCEDATAENDERR : 1;       /*!< [22..22] Force Event for Data End Bit Error                               */
      __IOM uint32_t FORCECURRLIMITERR : 1;     /*!< [23..23] Force Event for Current Limit Error                              */
      __IOM uint32_t FORCEACMDERR : 1;          /*!< [24..24] Force Event for Auto CMD Error                                   */
      __IOM uint32_t FORCEADMAERR : 1;          /*!< [25..25] Force event for ADMA error                                       */
            uint32_t            : 6;
    } FORCE_b;
  } ;

  union {
    __IOM uint32_t ADMA;                        /*!< (@ 0x00000054) ADMA error status                                          */

    struct {
      __IOM uint32_t ADMAERRORSTATE : 2;        /*!< [1..0] This field indicates the state of ADMA when error is
                                                     occurred during ADMA data transfer. This field never indicates
                                                     10 because ADMA never stops in this state. D01 - D00 :
                                                     ADMA Error State when error occurred Contents of SYS_SDR
                                                     register                                                                  */
      __IOM uint32_t ADMALENMISMATCHERR : 1;    /*!< [2..2] This error occurs in the following 2 cases. While Block
                                                     Count Enable being set, the total data length specified
                                                     by the Descriptor table is different from that specified
                                                     by the Block Count and Block Length. Total data length
                                                     can not be divided by the block length.                                   */
            uint32_t            : 29;
    } ADMA_b;
  } ;

  union {
    __IOM uint32_t ADMALOWD;                    /*!< (@ 0x00000058) ADMA system address [31:0]                                 */

    struct {
      __IOM uint32_t LOWD       : 32;           /*!< [31..0] This register holds byte address of executing command
                                                     of the Descriptor table. 32-bit Address Descriptor uses
                                                     lower 32bit of this register. At the start of ADMA, the
                                                     Host Driver shall set start address of the Descriptor table.
                                                     The ADMA increments this register address, which points
                                                     to next line, when every fetching a Descriptor line. When
                                                     the ADMA Error Interrupt is generated, this register shall
                                                     hold valid Descriptor address depending on the ADMA state.
                                                     The Host Driver shall program Descriptor Table on 32                      */
    } ADMALOWD_b;
  } ;

  union {
    __IOM uint32_t ADMAHIWD;                    /*!< (@ 0x0000005C) ADMA system address [63:0]                                 */

    struct {
      __IOM uint32_t HIWD       : 32;           /*!< [31..0] This register holds byte address of executing command
                                                     of the Descriptor table. 32-bit Address Descriptor uses
                                                     lower 32bit of this register. At the start of ADMA, the
                                                     Host Driver shall set start address of the Descriptor table.
                                                     The ADMA increments this register address, which points
                                                     to next line, when every fetching a Descriptor line. When
                                                     the ADMA Error Interrupt is generated, this register shall
                                                     hold valid Descriptor address depending on the ADMA state.
                                                     The Host Driver shall program Descriptor Table on 32                      */
    } ADMAHIWD_b;
  } ;

  union {
    __IOM uint32_t PRESET0;                     /*!< (@ 0x00000060) Preset Value initialization and default speed              */

    struct {
      __IOM uint32_t HISPSDCLKFREQSEL : 10;     /*!< [9..0] 10 bit preset value to set SDCLK Frequency Select in
                                                     the Clock Control Register is described by a host system.
                                                     When Host Controller supports shared bus, a set of Preset
                                                     Value registers for each device required and the registers
                                                     location are duplicated to the offset 06Fh-060h. A set
                                                     of Preset Value registers can be accessible by selecting
                                                     Clock Pin Select in the Shared Bus Control register                       */
      __IOM uint32_t HISPCLKGENSEL : 1;         /*!< [10..10] This bit is effective when Host Controller supports
                                                     programmable clock generator.                                             */
            uint32_t            : 3;
      __IOM uint32_t HISPDRVRSTRSEL : 2;        /*!< [15..14] Driver Strength is supported by 1.8V signaling bus
                                                     speed modes. This field is meaningless for 3.3V signaling.                */
      __IOM uint32_t DEFSPSDCLKFREQSEL : 10;    /*!< [25..16] 10 bit preset value to set SDCLK Frequency Select in
                                                     the Clock Control Register is described by a host system.
                                                     When Host Controller supports shared bus, a set of Preset
                                                     Value registers for each device required and the registers
                                                     location are duplicated to the offset 06Fh-060h. A set
                                                     of Preset Value registers can be accessible by selecting
                                                     Clock Pin Select in the Shared Bus Control register                       */
      __IOM uint32_t DEFSPCLKGENSEL : 1;        /*!< [26..26] This bit is effective when Host Controller supports
                                                     programmable clock generator.                                             */
            uint32_t            : 3;
      __IOM uint32_t DEFSPDRVRSTRSEL : 2;       /*!< [31..30] Driver Strength is supported by 1.8V signaling bus
                                                     speed modes. This field is meaningless for 3.3V signaling.                */
    } PRESET0_b;
  } ;

  union {
    __IOM uint32_t PRESET1;                     /*!< (@ 0x00000064) Preset Value for high speed and SDR12                      */

    struct {
      __IOM uint32_t HSSDCLKFREQSEL : 10;       /*!< [9..0] 10 bit preset value to set SDCLK Frequency Select in
                                                     the Clock Control Register is described by a host system.
                                                     When Host Controller supports shared bus, a set of Preset
                                                     Value registers for each device required and the registers
                                                     location are duplicated to the offset 06Fh-060h. A set
                                                     of Preset Value registers can be accessible by selecting
                                                     Clock Pin Select in the Shared Bus Control register                       */
      __IOM uint32_t HSCLKGENSEL : 1;           /*!< [10..10] This bit is effective when Host Controller supports
                                                     programmable clock generator.                                             */
            uint32_t            : 3;
      __IOM uint32_t HSDRVRSTRSEL : 2;          /*!< [15..14] Driver Strength is supported by 1.8V signaling bus
                                                     speed modes. This field is meaningless for 3.3V signaling.                */
      __IOM uint32_t SDR12SDCLKFREQSEL : 10;    /*!< [25..16] 10 bit preset value to set SDCLK Frequency Select in
                                                     the Clock Control Register is described by a host system.
                                                     When Host Controller supports shared bus, a set of Preset
                                                     Value registers for each device required and the registers
                                                     location are duplicated to the offset 06Fh-060h. A set
                                                     of Preset Value registers can be accessible by selecting
                                                     Clock Pin Select in the Shared Bus Control register                       */
      __IOM uint32_t SDR12CLKGENSEL : 1;        /*!< [26..26] This bit is effective when Host Controller supports
                                                     programmable clock generator.                                             */
            uint32_t            : 3;
      __IOM uint32_t SDR12DRVRSTRSEL : 2;       /*!< [31..30] Driver Strength is supported by 1.8V signaling bus
                                                     speed modes. This field is meaningless for 3.3V signaling.                */
    } PRESET1_b;
  } ;

  union {
    __IOM uint32_t PRESET2;                     /*!< (@ 0x00000068) Preset Value for SDR25 and SDR50                           */

    struct {
      __IOM uint32_t SDR25SDCLKFREQSEL : 10;    /*!< [9..0] 10 bit preset value to set SDCLK Frequency Select in
                                                     the Clock Control Register is described by a host system.
                                                     When Host Controller supports shared bus, a set of Preset
                                                     Value registers for each device required and the registers
                                                     location are duplicated to the offset 06Fh-060h. A set
                                                     of Preset Value registers can be accessible by selecting
                                                     Clock Pin Select in the Shared Bus Control register                       */
      __IOM uint32_t SDR25CLKGENSEL : 1;        /*!< [10..10] This bit is effective when Host Controller supports
                                                     programmable clock generator.                                             */
            uint32_t            : 3;
      __IOM uint32_t SDR25DRVRSTRSEL : 2;       /*!< [15..14] Driver Strength is supported by 1.8V signaling bus
                                                     speed modes. This field is meaningless for 3.3V signaling.                */
      __IOM uint32_t SDR50SDCLKFREQSEL : 10;    /*!< [25..16] 10 bit preset value to set SDCLK Frequency Select in
                                                     the Clock Control Register is described by a host system.
                                                     When Host Controller supports shared bus, a set of Preset
                                                     Value registers for each device required and the registers
                                                     location are duplicated to the offset 06Fh-060h. A set
                                                     of Preset Value registers can be accessible by selecting
                                                     Clock Pin Select in the Shared Bus Control register                       */
      __IOM uint32_t SDR50CLKGENSEL : 1;        /*!< [26..26] This bit is effective when Host Controller supports
                                                     programmable clock generator.                                             */
            uint32_t            : 3;
      __IOM uint32_t SDR50DRVRSTRSEL : 2;       /*!< [31..30] Driver Strength is supported by 1.8V signaling bus
                                                     speed modes. This field is meaningless for 3.3V signaling.                */
    } PRESET2_b;
  } ;

  union {
    __IOM uint32_t PRESET3;                     /*!< (@ 0x0000006C) Preset Value for SDR104 and DDR50                          */

    struct {
      __IOM uint32_t SDR104SDCLKFREQSEL : 10;   /*!< [9..0] 10 bit preset value to set SDCLK Frequency Select in
                                                     the Clock Control Register is described by a host system.
                                                     When Host Controller supports shared bus, a set of Preset
                                                     Value registers for each device required and the registers
                                                     location are duplicated to the offset 06Fh-060h. A set
                                                     of Preset Value registers can be accessible by selecting
                                                     Clock Pin Select in the Shared Bus Control register                       */
      __IOM uint32_t SDR104CLKGENSEL : 1;       /*!< [10..10] This bit is effective when Host Controller supports
                                                     programmable clock generator.                                             */
            uint32_t            : 3;
      __IOM uint32_t SDR104DRVRSTRSEL : 2;      /*!< [15..14] Driver Strength is supported by 1.8V signaling bus
                                                     speed modes. This field is meaningless for 3.3V signaling.                */
      __IOM uint32_t DDR50SDCLKFREQSEL : 10;    /*!< [25..16] 10 bit preset value to set SDCLK Frequency Select in
                                                     the Clock Control Register is described by a host system.
                                                     When Host Controller supports shared bus, a set of Preset
                                                     Value registers for each device required and the registers
                                                     location are duplicated to the offset 06Fh-060h. A set
                                                     of Preset Value registers can be accessible by selecting
                                                     Clock Pin Select in the Shared Bus Control register                       */
      __IOM uint32_t DDR50CLKGENSEL : 1;        /*!< [26..26] This bit is effective when Host Controller supports
                                                     programmable clock generator.                                             */
            uint32_t            : 3;
      __IOM uint32_t DDR50DRVRSTRSEL : 2;       /*!< [31..30] Driver Strength is supported by 1.8V signaling bus
                                                     speed modes. This field is meaningless for 3.3V signaling.                */
    } PRESET3_b;
  } ;

  union {
    __IOM uint32_t BOOTTOCTRL;                  /*!< (@ 0x00000070) Boot Data Timeout control                                  */

    struct {
      __IOM uint32_t BOOTDATATO : 32;           /*!< [31..0] This value determines the interval by which DAT line
                                                     time-outs are detected during boot operation for eMMC card.
                                                     The value is in number of sd clock.                                       */
    } BOOTTOCTRL_b;
  } ;
  __IM  uint32_t  RESERVED;

  union {
    __IOM uint32_t VENDOR;                      /*!< (@ 0x00000078) Vendor                                                     */

    struct {
      __IOM uint32_t GATESDCLKEN : 1;           /*!< [0..0] If this bit is 0, SD_CLK to card will not be gated automatically,
                                                     when there is no transfer. If this bit set to 1, SD_CLK
                                                     to card will be gated automatically,when there is no transfer.            */
      __IOM uint32_t DLYDIS     : 1;            /*!< [1..1] Chicken bit added to enable/disable the rtl fix made
                                                     to delay the sampling of cmd_in and data_in.                              */
            uint32_t            : 30;
    } VENDOR_b;
  } ;
  __IM  uint32_t  RESERVED1[32];

  union {
    __IOM uint32_t SLOTSTAT;                    /*!< (@ 0x000000FC) Slot interrupt status                                      */

    struct {
      __IOM uint32_t INTSLOT0   : 1;            /*!< [0..0] This status bit indicates the OR of Interrupt signal
                                                     and Wakeup signal for slot                                                */
            uint32_t            : 15;
      __IOM uint32_t SPECVER    : 8;            /*!< [23..16] The Host Controller Version Number is set to 0x02 (SD
                                                     Host Specification Version 3.00).                                         */
      __IOM uint32_t VENDORVER  : 8;            /*!< [31..24] The Vendor Version Number is set to 0x10 (1.0)                   */
    } SLOTSTAT_b;
  } ;
} SDIO_Type;                                    /*!< Size = 256 (0x100)                                                        */



/* =========================================================================================================================== */
/* ================                                         SECURITY                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief Security Interfaces (SECURITY)
  */

typedef struct {                                /*!< (@ 0x40030000) SECURITY Structure                                         */

  union {
    __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) Control                                                    */

    struct {
      __IOM uint32_t ENABLE     : 1;            /*!< [0..0] Function Enable. Software should set the ENABLE bit to
                                                     initiate a CRC operation. Hardware will clear the ENABLE
                                                     bit upon completion.                                                      */
            uint32_t            : 3;
      __IOM uint32_t FUNCTION   : 4;            /*!< [7..4] Function Select                                                    */
            uint32_t            : 23;
      __IOM uint32_t CRCERROR   : 1;            /*!< [31..31] CRC Error Status - Set to 1 if an error occurs during
                                                     a CRC operation. Cleared when CTRL register is written
                                                     (with any value). Usually indicates an invalid address
                                                     range.                                                                    */
    } CTRL_b;
  } ;
  __IM  uint32_t  RESERVED[3];

  union {
    __IOM uint32_t SRCADDR;                     /*!< (@ 0x00000010) Source Addresss                                            */

    struct {
      __IOM uint32_t ADDR       : 32;           /*!< [31..0] Source Buffer Address. Address may be byte aligned,
                                                     but the length must be a multiple of 4 bits.                              */
    } SRCADDR_b;
  } ;
  __IM  uint32_t  RESERVED1[3];

  union {
    __IOM uint32_t LEN;                         /*!< (@ 0x00000020) Length                                                     */

    struct {
            uint32_t            : 2;
      __IOM uint32_t LEN        : 22;           /*!< [23..2] Buffer size (bottom two bits assumed to be zero to ensure
                                                     a multiple of 4 bytes)                                                    */
            uint32_t            : 8;
    } LEN_b;
  } ;
  __IM  uint32_t  RESERVED2[3];

  union {
    __IOM uint32_t RESULT;                      /*!< (@ 0x00000030) CRC Seed/Result                                            */

    struct {
      __IOM uint32_t CRC        : 32;           /*!< [31..0] CRC Seed/Result. Software must seed the CRC with 0xFFFFFFFF
                                                     before starting a CRC operation (unless the CRC is continued
                                                     from a previous operation).                                               */
    } RESULT_b;
  } ;
  __IM  uint32_t  RESERVED3[17];

  union {
    __IOM uint32_t LOCKCTRL;                    /*!< (@ 0x00000078) LOCK Control                                               */

    struct {
      __IOM uint32_t SELECT     : 8;            /*!< [7..0] LOCK Function Select register.                                     */
            uint32_t            : 24;
    } LOCKCTRL_b;
  } ;

  union {
    __IOM uint32_t LOCKSTAT;                    /*!< (@ 0x0000007C) LOCK Status                                                */

    struct {
      __IOM uint32_t STATUS     : 32;           /*!< [31..0] Lock status. Bit is high to signify it is enabled. 0:
                                                     LOCK01, 1: LOCK02, 4: LOCK11, 5: LOCK12, 30: LOCK9D, 31:
                                                     LOCK9E                                                                    */
    } LOCKSTAT_b;
  } ;

  union {
    __IOM uint32_t KEY0;                        /*!< (@ 0x00000080) Key0                                                       */

    struct {
      __IOM uint32_t KEY0       : 32;           /*!< [31..0] Bits [31:0] of the 128-bit key should be written to
                                                     this register. To protect key values, the register always
                                                     returns 0x00000000.                                                       */
    } KEY0_b;
  } ;

  union {
    __IOM uint32_t KEY1;                        /*!< (@ 0x00000084) Key1                                                       */

    struct {
      __IOM uint32_t KEY1       : 32;           /*!< [31..0] Bits [63:32] of the 128-bit key should be written to
                                                     this register. To protect key values, the register always
                                                     returns 0x00000000.                                                       */
    } KEY1_b;
  } ;

  union {
    __IOM uint32_t KEY2;                        /*!< (@ 0x00000088) Key2                                                       */

    struct {
      __IOM uint32_t KEY2       : 32;           /*!< [31..0] Bits [95:64] of the 128-bit key should be written to
                                                     this register. To protect key values, the register always
                                                     returns 0x00000000.                                                       */
    } KEY2_b;
  } ;

  union {
    __IOM uint32_t KEY3;                        /*!< (@ 0x0000008C) Key3                                                       */

    struct {
      __IOM uint32_t KEY3       : 32;           /*!< [31..0] Bits [127:96] of the 128-bit key should be written to
                                                     this register. To protect key values, the register always
                                                     returns 0x00000000.                                                       */
    } KEY3_b;
  } ;
} SECURITY_Type;                                /*!< Size = 144 (0x90)                                                         */



/* =========================================================================================================================== */
/* ================                                          STIMER                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Counter/Timer (STIMER)
  */

typedef struct {                                /*!< (@ 0x40008800) STIMER Structure                                           */

  union {
    __IOM uint32_t STCFG;                       /*!< (@ 0x00000000) The STIMER Configuration Register contains the
                                                                    software control for selecting the clock
                                                                    divider and source feeding the system timer.               */

    struct {
      __IOM uint32_t CLKSEL     : 4;            /*!< [3..0] Selects an appropriate clock source and divider to use
                                                     for the System Timer clock.                                               */
            uint32_t            : 4;
      __IOM uint32_t COMPAREAEN : 1;            /*!< [8..8] Selects whether compare is enabled for the corresponding
                                                     SCMPR register. If compare is enabled, the interrupt status
                                                     is set once the comparision is met.                                       */
      __IOM uint32_t COMPAREBEN : 1;            /*!< [9..9] Selects whether compare is enabled for the corresponding
                                                     SCMPR register. If compare is enabled, the interrupt status
                                                     is set once the comparision is met.                                       */
      __IOM uint32_t COMPARECEN : 1;            /*!< [10..10] Selects whether compare is enabled for the corresponding
                                                     SCMPR register. If compare is enabled, the interrupt status
                                                     is set once the comparision is met.                                       */
      __IOM uint32_t COMPAREDEN : 1;            /*!< [11..11] Selects whether compare is enabled for the corresponding
                                                     SCMPR register. If compare is enabled, the interrupt status
                                                     is set once the comparision is met.                                       */
      __IOM uint32_t COMPAREEEN : 1;            /*!< [12..12] Selects whether compare is enabled for the corresponding
                                                     SCMPR register. If compare is enabled, the interrupt status
                                                     is set once the comparision is met.                                       */
      __IOM uint32_t COMPAREFEN : 1;            /*!< [13..13] Selects whether compare is enabled for the corresponding
                                                     SCMPR register. If compare is enabled, the interrupt status
                                                     is set once the comparision is met.                                       */
      __IOM uint32_t COMPAREGEN : 1;            /*!< [14..14] Selects whether compare is enabled for the corresponding
                                                     SCMPR register. If compare is enabled, the interrupt status
                                                     is set once the comparision is met.                                       */
      __IOM uint32_t COMPAREHEN : 1;            /*!< [15..15] Selects whether compare is enabled for the corresponding
                                                     SCMPR register. If compare is enabled, the interrupt status
                                                     is set once the comparision is met.                                       */
            uint32_t            : 14;
      __IOM uint32_t CLEAR      : 1;            /*!< [30..30] Set this bit to one to clear the System Timer register.
                                                     If this bit is set to '1', the system timer register will
                                                     stay cleared. It needs to be set to '0' for the system
                                                     timer to start running.                                                   */
      __IOM uint32_t FREEZE     : 1;            /*!< [31..31] Set this bit to one to freeze the clock input to the
                                                     COUNTER register. Once frozen, the value can be safely
                                                     written from the MCU. Unfreeze to resume.                                 */
    } STCFG_b;
  } ;

  union {
    __IOM uint32_t STTMR;                       /*!< (@ 0x00000004) The COUNTER Register contains the running count
                                                                    of time as maintained by incrementing for
                                                                    every rising clock edge of the clock source
                                                                    selected in the configuration register.
                                                                    It is this counter value that captured in
                                                                    the capture registers and it is this counter
                                                                    value that is compared against the various
                                                                    compare registers. This register cannot
                                                                    be written, but can be cleared to 0 for
                                                                    a deterministic value. Use the FREEZE bit
                                                                    will stop this counter from incrementing.                  */

    struct {
      __IOM uint32_t STTMR      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
    } STTMR_b;
  } ;
  __IM  uint32_t  RESERVED[2];

  union {
    __IOM uint32_t SCAPCTRL0;                   /*!< (@ 0x00000010) The STIMER Capture Control Register controls
                                                                    each of the 4 capture registers. It selects
                                                                    their GPIO pin number for a trigger source,
                                                                    enables a capture operation and sets the
                                                                    input polarity for the capture. NOTE: 8-bit
                                                                    writes can control individual capture registers
                                                                    atomically.                                                */

    struct {
      __IOM uint32_t STSEL0     : 7;            /*!< [6..0] STIMER Capture 0 Select.                                           */
            uint32_t            : 1;
      __IOM uint32_t STPOL0     : 1;            /*!< [8..8] STIMER Capture 0 Polarity.                                         */
      __IOM uint32_t CAPTURE0   : 1;            /*!< [9..9] Selects whether capture 0 is enabled for the specified
                                                     capture register.                                                         */
            uint32_t            : 22;
    } SCAPCTRL0_b;
  } ;

  union {
    __IOM uint32_t SCAPCTRL1;                   /*!< (@ 0x00000014) The STIMER Capture Control Register controls
                                                                    each of the 4 capture registers. It selects
                                                                    their GPIO pin number for a trigger source,
                                                                    enables a capture operation and sets the
                                                                    input polarity for the capture. NOTE: 8-bit
                                                                    writes can control individual capture registers
                                                                    atomically.                                                */

    struct {
      __IOM uint32_t STSEL1     : 7;            /*!< [6..0] STIMER Capture 1 Select.                                           */
            uint32_t            : 1;
      __IOM uint32_t STPOL1     : 1;            /*!< [8..8] STIMER Capture 1 Polarity.                                         */
      __IOM uint32_t CAPTURE1   : 1;            /*!< [9..9] Selects whether capture 1 is enabled for the specified
                                                     capture register.                                                         */
            uint32_t            : 22;
    } SCAPCTRL1_b;
  } ;

  union {
    __IOM uint32_t SCAPCTRL2;                   /*!< (@ 0x00000018) The STIMER Capture Control Register controls
                                                                    each of the 4 capture registers. It selects
                                                                    their GPIO pin number for a trigger source,
                                                                    enables a capture operation and sets the
                                                                    input polarity for the capture. NOTE: 8-bit
                                                                    writes can control individual capture registers
                                                                    atomically.                                                */

    struct {
      __IOM uint32_t STSEL2     : 7;            /*!< [6..0] STIMER Capture 2 Select.                                           */
            uint32_t            : 1;
      __IOM uint32_t STPOL2     : 1;            /*!< [8..8] STIMER Capture 2 Polarity.                                         */
      __IOM uint32_t CAPTURE2   : 1;            /*!< [9..9] Selects whether capture 2 is enabled for the specified
                                                     capture register.                                                         */
            uint32_t            : 22;
    } SCAPCTRL2_b;
  } ;

  union {
    __IOM uint32_t SCAPCTRL3;                   /*!< (@ 0x0000001C) The STIMER Capture Control Register controls
                                                                    each of the 4 capture registers. It selects
                                                                    their GPIO pin number for a trigger source,
                                                                    enables a capture operation and sets the
                                                                    input polarity for the capture. NOTE: 8-bit
                                                                    writes can control individual capture registers
                                                                    atomically.                                                */

    struct {
      __IOM uint32_t STSEL3     : 7;            /*!< [6..0] STIMER Capture 3 Select.                                           */
            uint32_t            : 1;
      __IOM uint32_t STPOL3     : 1;            /*!< [8..8] STIMER Capture 3 Polarity.                                         */
      __IOM uint32_t CAPTURE3   : 1;            /*!< [9..9] Selects whether capture 3 is enabled for the specified
                                                     capture register.                                                         */
            uint32_t            : 22;
    } SCAPCTRL3_b;
  } ;

  union {
    __IOM uint32_t SCMPR0;                      /*!< (@ 0x00000020) The VALUE in this bit field is used to compare
                                                                    against the VALUE in the COUNTER register.
                                                                    If the match criterion in the configuration
                                                                    register is met then a corresponding interrupt
                                                                    status bit is set. The match criterion is
                                                                    defined as COUNTER equal to COMPARE. To
                                                                    establish a desired value in this COMPARE
                                                                    register, write the number of ticks in the
                                                                    future to this register to indicate when
                                                                    to interrupt. The hardware does the addition
                                                                    to the COUNTER value in the STIMER clock
                                                                    domain so that the ma                                      */

    struct {
      __IOM uint32_t SCMPR0     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
                                                     according to the match criterion, as selected in the COMPARE_A_EN
                                                     bit in the REG_CTIMER_STCFG register.                                     */
    } SCMPR0_b;
  } ;

  union {
    __IOM uint32_t SCMPR1;                      /*!< (@ 0x00000024) The VALUE in this bit field is used to compare
                                                                    against the VALUE in the COUNTER register.
                                                                    If the match criterion in the configuration
                                                                    register is met then a corresponding interrupt
                                                                    status bit is set. The match criterion is
                                                                    defined as COUNTER equal to COMPARE. To
                                                                    establish a desired value in this COMPARE
                                                                    register, write the number of ticks in the
                                                                    future to this register to indicate when
                                                                    to interrupt. The hardware does the addition
                                                                    to the COUNTER value in the STIMER clock
                                                                    domain so that the ma                                      */

    struct {
      __IOM uint32_t SCMPR1     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
                                                     according to the match criterion, as selected in the COMPARE_A_EN
                                                     bit in the REG_CTIMER_STCFG register.                                     */
    } SCMPR1_b;
  } ;

  union {
    __IOM uint32_t SCMPR2;                      /*!< (@ 0x00000028) The VALUE in this bit field is used to compare
                                                                    against the VALUE in the COUNTER register.
                                                                    If the match criterion in the configuration
                                                                    register is met then a corresponding interrupt
                                                                    status bit is set. The match criterion is
                                                                    defined as COUNTER equal to COMPARE. To
                                                                    establish a desired value in this COMPARE
                                                                    register, write the number of ticks in the
                                                                    future to this register to indicate when
                                                                    to interrupt. The hardware does the addition
                                                                    to the COUNTER value in the STIMER clock
                                                                    domain so that the ma                                      */

    struct {
      __IOM uint32_t SCMPR2     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
                                                     according to the match criterion, as selected in the COMPARE_A_EN
                                                     bit in the REG_CTIMER_STCFG register.                                     */
    } SCMPR2_b;
  } ;

  union {
    __IOM uint32_t SCMPR3;                      /*!< (@ 0x0000002C) The VALUE in this bit field is used to compare
                                                                    against the VALUE in the COUNTER register.
                                                                    If the match criterion in the configuration
                                                                    register is met then a corresponding interrupt
                                                                    status bit is set. The match criterion is
                                                                    defined as COUNTER equal to COMPARE. To
                                                                    establish a desired value in this COMPARE
                                                                    register, write the number of ticks in the
                                                                    future to this register to indicate when
                                                                    to interrupt. The hardware does the addition
                                                                    to the COUNTER value in the STIMER clock
                                                                    domain so that the ma                                      */

    struct {
      __IOM uint32_t SCMPR3     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
                                                     according to the match criterion, as selected in the COMPARE_A_EN
                                                     bit in the REG_CTIMER_STCFG register.                                     */
    } SCMPR3_b;
  } ;

  union {
    __IOM uint32_t SCMPR4;                      /*!< (@ 0x00000030) The VALUE in this bit field is used to compare
                                                                    against the VALUE in the COUNTER register.
                                                                    If the match criterion in the configuration
                                                                    register is met then a corresponding interrupt
                                                                    status bit is set. The match criterion is
                                                                    defined as COUNTER equal to COMPARE. To
                                                                    establish a desired value in this COMPARE
                                                                    register, write the number of ticks in the
                                                                    future to this register to indicate when
                                                                    to interrupt. The hardware does the addition
                                                                    to the COUNTER value in the STIMER clock
                                                                    domain so that the ma                                      */

    struct {
      __IOM uint32_t SCMPR4     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
                                                     according to the match criterion, as selected in the COMPARE_A_EN
                                                     bit in the REG_CTIMER_STCFG register.                                     */
    } SCMPR4_b;
  } ;

  union {
    __IOM uint32_t SCMPR5;                      /*!< (@ 0x00000034) The VALUE in this bit field is used to compare
                                                                    against the VALUE in the COUNTER register.
                                                                    If the match criterion in the configuration
                                                                    register is met then a corresponding interrupt
                                                                    status bit is set. The match criterion is
                                                                    defined as COUNTER equal to COMPARE. To
                                                                    establish a desired value in this COMPARE
                                                                    register, write the number of ticks in the
                                                                    future to this register to indicate when
                                                                    to interrupt. The hardware does the addition
                                                                    to the COUNTER value in the STIMER clock
                                                                    domain so that the ma                                      */

    struct {
      __IOM uint32_t SCMPR5     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
                                                     according to the match criterion, as selected in the COMPARE_A_EN
                                                     bit in the REG_CTIMER_STCFG register.                                     */
    } SCMPR5_b;
  } ;

  union {
    __IOM uint32_t SCMPR6;                      /*!< (@ 0x00000038) The VALUE in this bit field is used to compare
                                                                    against the VALUE in the COUNTER register.
                                                                    If the match criterion in the configuration
                                                                    register is met then a corresponding interrupt
                                                                    status bit is set. The match criterion is
                                                                    defined as COUNTER equal to COMPARE. To
                                                                    establish a desired value in this COMPARE
                                                                    register, write the number of ticks in the
                                                                    future to this register to indicate when
                                                                    to interrupt. The hardware does the addition
                                                                    to the COUNTER value in the STIMER clock
                                                                    domain so that the ma                                      */

    struct {
      __IOM uint32_t SCMPR6     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
                                                     according to the match criterion, as selected in the COMPARE_A_EN
                                                     bit in the REG_CTIMER_STCFG register.                                     */
    } SCMPR6_b;
  } ;

  union {
    __IOM uint32_t SCMPR7;                      /*!< (@ 0x0000003C) The VALUE in this bit field is used to compare
                                                                    against the VALUE in the COUNTER register.
                                                                    If the match criterion in the configuration
                                                                    register is met then a corresponding interrupt
                                                                    status bit is set. The match criterion is
                                                                    defined as COUNTER equal to COMPARE. To
                                                                    establish a desired value in this COMPARE
                                                                    register, write the number of ticks in the
                                                                    future to this register to indicate when
                                                                    to interrupt. The hardware does the addition
                                                                    to the COUNTER value in the STIMER clock
                                                                    domain so that the ma                                      */

    struct {
      __IOM uint32_t SCMPR7     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
                                                     according to the match criterion, as selected in the COMPARE_A_EN
                                                     bit in the REG_CTIMER_STCFG register.                                     */
    } SCMPR7_b;
  } ;

  union {
    __IOM uint32_t SCAPT0;                      /*!< (@ 0x00000040) The STIMER capture Register 0 captures the VALUE
                                                                    in the COUNTER register whenever capture
                                                                    condition (event) occurs. This register
                                                                    holds a time stamp for the event.                          */

    struct {
      __IOM uint32_t SCAPT0     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
                                                     is copied into this register and the corresponding interrupt
                                                     status bit is set.                                                        */
    } SCAPT0_b;
  } ;

  union {
    __IOM uint32_t SCAPT1;                      /*!< (@ 0x00000044) The STIMER capture Register 1 captures the VALUE
                                                                    in the COUNTER register whenever capture
                                                                    condition (event) occurs. This register
                                                                    holds a time stamp for the event.                          */

    struct {
      __IOM uint32_t SCAPT1     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
                                                     is copied into this register and the corresponding interrupt
                                                     status bit is set.                                                        */
    } SCAPT1_b;
  } ;

  union {
    __IOM uint32_t SCAPT2;                      /*!< (@ 0x00000048) The STIMER capture Register 2 captures the VALUE
                                                                    in the COUNTER register whenever capture
                                                                    condition (event) occurs. This register
                                                                    holds a time stamp for the event.                          */

    struct {
      __IOM uint32_t SCAPT2     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
                                                     is copied into this register and the corresponding interrupt
                                                     status bit is set.                                                        */
    } SCAPT2_b;
  } ;

  union {
    __IOM uint32_t SCAPT3;                      /*!< (@ 0x0000004C) The STIMER capture Register 3 captures the VALUE
                                                                    in the COUNTER register whenever capture
                                                                    condition (event) occurs. This register
                                                                    holds a time stamp for the event.                          */

    struct {
      __IOM uint32_t SCAPT3     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
                                                     is copied into this register and the corresponding interrupt
                                                     status bit is set.                                                        */
    } SCAPT3_b;
  } ;

  union {
    __IOM uint32_t SNVR0;                       /*!< (@ 0x00000050) The SNVR0 Register contains a portion of the
                                                                    stored epoch offset associated with the
                                                                    time in the COUNTER register. This register
                                                                    is only reset by POI not by HRESETn. Its
                                                                    contents are intended to survive all reset
                                                                    level except POI and full power cycles.                    */

    struct {
      __IOM uint32_t SNVR0      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
    } SNVR0_b;
  } ;

  union {
    __IOM uint32_t SNVR1;                       /*!< (@ 0x00000054) The SNVR1 Register contains a portion of the
                                                                    stored epoch offset associated with the
                                                                    time in the COUNTER register. This register
                                                                    is only reset by POI not by HRESETn. Its
                                                                    contents are intended to survive all reset
                                                                    level except POI and full power cycles.                    */

    struct {
      __IOM uint32_t SNVR1      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
    } SNVR1_b;
  } ;

  union {
    __IOM uint32_t SNVR2;                       /*!< (@ 0x00000058) The SNVR2 Register contains a portion of the
                                                                    stored epoch offset associated with the
                                                                    time in the COUNTER register. This register
                                                                    is only reset by POI not by HRESETn. Its
                                                                    contents are intended to survive all reset
                                                                    level except POI and full power cycles.                    */

    struct {
      __IOM uint32_t SNVR2      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
    } SNVR2_b;
  } ;
  __IM  uint32_t  RESERVED1[41];

  union {
    __IOM uint32_t STMINTEN;                    /*!< (@ 0x00000100) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
                                                     A.                                                                        */
      __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
                                                     B.                                                                        */
      __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
                                                     C.                                                                        */
      __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
                                                     D.                                                                        */
      __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
                                                     E.                                                                        */
      __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
                                                     F.                                                                        */
      __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
                                                     G.                                                                        */
      __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
                                                     H.                                                                        */
      __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
      __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
      __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
      __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
      __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
            uint32_t            : 19;
    } STMINTEN_b;
  } ;

  union {
    __IOM uint32_t STMINTSTAT;                  /*!< (@ 0x00000104) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
                                                     A.                                                                        */
      __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
                                                     B.                                                                        */
      __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
                                                     C.                                                                        */
      __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
                                                     D.                                                                        */
      __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
                                                     E.                                                                        */
      __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
                                                     F.                                                                        */
      __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
                                                     G.                                                                        */
      __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
                                                     H.                                                                        */
      __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
      __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
      __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
      __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
      __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
            uint32_t            : 19;
    } STMINTSTAT_b;
  } ;

  union {
    __IOM uint32_t STMINTCLR;                   /*!< (@ 0x00000108) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
                                                     A.                                                                        */
      __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
                                                     B.                                                                        */
      __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
                                                     C.                                                                        */
      __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
                                                     D.                                                                        */
      __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
                                                     E.                                                                        */
      __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
                                                     F.                                                                        */
      __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
                                                     G.                                                                        */
      __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
                                                     H.                                                                        */
      __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
      __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
      __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
      __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
      __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
            uint32_t            : 19;
    } STMINTCLR_b;
  } ;

  union {
    __IOM uint32_t STMINTSET;                   /*!< (@ 0x0000010C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
                                                     A.                                                                        */
      __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
                                                     B.                                                                        */
      __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
                                                     C.                                                                        */
      __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
                                                     D.                                                                        */
      __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
                                                     E.                                                                        */
      __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
                                                     F.                                                                        */
      __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
                                                     G.                                                                        */
      __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
                                                     H.                                                                        */
      __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
      __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
      __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
      __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
      __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
            uint32_t            : 19;
    } STMINTSET_b;
  } ;
} STIMER_Type;                                  /*!< Size = 272 (0x110)                                                        */



/* =========================================================================================================================== */
/* ================                                           TIMER                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Counter/Timer (TIMER)
  */

typedef struct {                                /*!< (@ 0x40008000) TIMER Structure                                            */

  union {
    __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) General Timer Controls                                     */

    struct {
            uint32_t            : 31;
      __IOM uint32_t RESET      : 1;            /*!< [31..31] Write to 1 to reset all timers (self-clearing)                   */
    } CTRL_b;
  } ;

  union {
    __IOM uint32_t STATUS;                      /*!< (@ 0x00000004) General Timer status                                       */

    struct {
      __IOM uint32_t ACTIVE     : 16;           /*!< [15..0] Indicates which timers are currnetly active (enabled)             */
      __IOM uint32_t NTIMERS    : 5;            /*!< [20..16] Indicates the number of timer blocks present in the
                                                     design                                                                    */
            uint32_t            : 11;
    } STATUS_b;
  } ;
  __IM  uint32_t  RESERVED[2];

  union {
    __IOM uint32_t GLOBEN;                      /*!< (@ 0x00000010) Alternate enables for all TIMERs.                          */

    struct {
      __IOM uint32_t ENB0       : 1;            /*!< [0..0] Alternate enable for timer 0                                       */
      __IOM uint32_t ENB1       : 1;            /*!< [1..1] Alternate enable for timer 1                                       */
      __IOM uint32_t ENB2       : 1;            /*!< [2..2] Alternate enable for timer 2                                       */
      __IOM uint32_t ENB3       : 1;            /*!< [3..3] Alternate enable for timer 3                                       */
      __IOM uint32_t ENB4       : 1;            /*!< [4..4] Alternate enable for timer 4                                       */
      __IOM uint32_t ENB5       : 1;            /*!< [5..5] Alternate enable for timer 5                                       */
      __IOM uint32_t ENB6       : 1;            /*!< [6..6] Alternate enable for timer 6                                       */
      __IOM uint32_t ENB7       : 1;            /*!< [7..7] Alternate enable for timer 7                                       */
      __IOM uint32_t ENB8       : 1;            /*!< [8..8] Alternate enable for timer 8                                       */
      __IOM uint32_t ENB9       : 1;            /*!< [9..9] Alternate enable for timer 9                                       */
      __IOM uint32_t ENB10      : 1;            /*!< [10..10] Alternate enable for timer 10                                    */
      __IOM uint32_t ENB11      : 1;            /*!< [11..11] Alternate enable for timer 11                                    */
      __IOM uint32_t ENB12      : 1;            /*!< [12..12] Alternate enable for timer 12                                    */
      __IOM uint32_t ENB13      : 1;            /*!< [13..13] Alternate enable for timer 13                                    */
      __IOM uint32_t ENB14      : 1;            /*!< [14..14] Alternate enable for timer 14                                    */
      __IOM uint32_t ENB15      : 1;            /*!< [15..15] Alternate enable for timer 15                                    */
            uint32_t            : 13;
      __IOM uint32_t ENABLEALLINPUTS : 1;       /*!< [29..29] Override to enable all GPIO inputs                               */
      __IOM uint32_t AUDADCEN   : 1;            /*!< [30..30] Audio ADC controls enable for timer 6                            */
      __IOM uint32_t ADCEN      : 1;            /*!< [31..31] ADC controls enable for timer 7                                  */
    } GLOBEN_b;
  } ;
  __IM  uint32_t  RESERVED1[19];

  union {
    __IOM uint32_t INTEN;                       /*!< (@ 0x00000060) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t TMR00INT   : 1;            /*!< [0..0] Counter/Timer 0 interrupt based on CMP0.                           */
      __IOM uint32_t TMR01INT   : 1;            /*!< [1..1] Counter/Timer 0 interrupt based on CMP1.                           */
      __IOM uint32_t TMR10INT   : 1;            /*!< [2..2] Counter/Timer 1 interrupt based on CMP0.                           */
      __IOM uint32_t TMR11INT   : 1;            /*!< [3..3] Counter/Timer 1 interrupt based on CMP1.                           */
      __IOM uint32_t TMR20INT   : 1;            /*!< [4..4] Counter/Timer 2 interrupt based on CMP0.                           */
      __IOM uint32_t TMR21INT   : 1;            /*!< [5..5] Counter/Timer 2 interrupt based on CMP1.                           */
      __IOM uint32_t TMR30INT   : 1;            /*!< [6..6] Counter/Timer 3 interrupt based on CMP0.                           */
      __IOM uint32_t TMR31INT   : 1;            /*!< [7..7] Counter/Timer 3 interrupt based on CMP1.                           */
      __IOM uint32_t TMR40INT   : 1;            /*!< [8..8] Counter/Timer 4 interrupt based on CMP0.                           */
      __IOM uint32_t TMR41INT   : 1;            /*!< [9..9] Counter/Timer 4 interrupt based on CMP1.                           */
      __IOM uint32_t TMR50INT   : 1;            /*!< [10..10] Counter/Timer 5 interrupt based on CMP0.                         */
      __IOM uint32_t TMR51INT   : 1;            /*!< [11..11] Counter/Timer 5 interrupt based on CMP1.                         */
      __IOM uint32_t TMR60INT   : 1;            /*!< [12..12] Counter/Timer 6 interrupt based on CMP0.                         */
      __IOM uint32_t TMR61INT   : 1;            /*!< [13..13] Counter/Timer 6 interrupt based on CMP1.                         */
      __IOM uint32_t TMR70INT   : 1;            /*!< [14..14] Counter/Timer 7 interrupt based on CMP0.                         */
      __IOM uint32_t TMR71INT   : 1;            /*!< [15..15] Counter/Timer 7 interrupt based on CMP1.                         */
      __IOM uint32_t TMR80INT   : 1;            /*!< [16..16] Counter/Timer 8 interrupt based on CMP0.                         */
      __IOM uint32_t TMR81INT   : 1;            /*!< [17..17] Counter/Timer 8 interrupt based on CMP1.                         */
      __IOM uint32_t TMR90INT   : 1;            /*!< [18..18] Counter/Timer 9 interrupt based on CMP0.                         */
      __IOM uint32_t TMR91INT   : 1;            /*!< [19..19] Counter/Timer 9 interrupt based on CMP1.                         */
      __IOM uint32_t TMR100INT  : 1;            /*!< [20..20] Counter/Timer 10 interrupt based on CMP0.                        */
      __IOM uint32_t TMR101INT  : 1;            /*!< [21..21] Counter/Timer 10 interrupt based on CMP1.                        */
      __IOM uint32_t TMR110INT  : 1;            /*!< [22..22] Counter/Timer 11 interrupt based on CMP0.                        */
      __IOM uint32_t TMR111INT  : 1;            /*!< [23..23] Counter/Timer 11 interrupt based on CMP1.                        */
      __IOM uint32_t TMR120INT  : 1;            /*!< [24..24] Counter/Timer 12 interrupt based on CMP0.                        */
      __IOM uint32_t TMR121INT  : 1;            /*!< [25..25] Counter/Timer 12 interrupt based on CMP1.                        */
      __IOM uint32_t TMR130INT  : 1;            /*!< [26..26] Counter/Timer 13 interrupt based on CMP0.                        */
      __IOM uint32_t TMR131INT  : 1;            /*!< [27..27] Counter/Timer 13 interrupt based on CMP1.                        */
      __IOM uint32_t TMR140INT  : 1;            /*!< [28..28] Counter/Timer 14 interrupt based on CMP0.                        */
      __IOM uint32_t TMR141INT  : 1;            /*!< [29..29] Counter/Timer 14 interrupt based on CMP1.                        */
      __IOM uint32_t TMR150INT  : 1;            /*!< [30..30] Counter/Timer 15 interrupt based on CMP0.                        */
      __IOM uint32_t TMR151INT  : 1;            /*!< [31..31] Counter/Timer 15 interrupt based on CMP1.                        */
    } INTEN_b;
  } ;

  union {
    __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000064) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t TMR00INT   : 1;            /*!< [0..0] Counter/Timer 0 interrupt based on CMP0.                           */
      __IOM uint32_t TMR01INT   : 1;            /*!< [1..1] Counter/Timer 0 interrupt based on CMP1.                           */
      __IOM uint32_t TMR10INT   : 1;            /*!< [2..2] Counter/Timer 1 interrupt based on CMP0.                           */
      __IOM uint32_t TMR11INT   : 1;            /*!< [3..3] Counter/Timer 1 interrupt based on CMP1.                           */
      __IOM uint32_t TMR20INT   : 1;            /*!< [4..4] Counter/Timer 2 interrupt based on CMP0.                           */
      __IOM uint32_t TMR21INT   : 1;            /*!< [5..5] Counter/Timer 2 interrupt based on CMP1.                           */
      __IOM uint32_t TMR30INT   : 1;            /*!< [6..6] Counter/Timer 3 interrupt based on CMP0.                           */
      __IOM uint32_t TMR31INT   : 1;            /*!< [7..7] Counter/Timer 3 interrupt based on CMP1.                           */
      __IOM uint32_t TMR40INT   : 1;            /*!< [8..8] Counter/Timer 4 interrupt based on CMP0.                           */
      __IOM uint32_t TMR41INT   : 1;            /*!< [9..9] Counter/Timer 4 interrupt based on CMP1.                           */
      __IOM uint32_t TMR50INT   : 1;            /*!< [10..10] Counter/Timer 5 interrupt based on CMP0.                         */
      __IOM uint32_t TMR51INT   : 1;            /*!< [11..11] Counter/Timer 5 interrupt based on CMP1.                         */
      __IOM uint32_t TMR60INT   : 1;            /*!< [12..12] Counter/Timer 6 interrupt based on CMP0.                         */
      __IOM uint32_t TMR61INT   : 1;            /*!< [13..13] Counter/Timer 6 interrupt based on CMP1.                         */
      __IOM uint32_t TMR70INT   : 1;            /*!< [14..14] Counter/Timer 7 interrupt based on CMP0.                         */
      __IOM uint32_t TMR71INT   : 1;            /*!< [15..15] Counter/Timer 7 interrupt based on CMP1.                         */
      __IOM uint32_t TMR80INT   : 1;            /*!< [16..16] Counter/Timer 8 interrupt based on CMP0.                         */
      __IOM uint32_t TMR81INT   : 1;            /*!< [17..17] Counter/Timer 8 interrupt based on CMP1.                         */
      __IOM uint32_t TMR90INT   : 1;            /*!< [18..18] Counter/Timer 9 interrupt based on CMP0.                         */
      __IOM uint32_t TMR91INT   : 1;            /*!< [19..19] Counter/Timer 9 interrupt based on CMP1.                         */
      __IOM uint32_t TMR100INT  : 1;            /*!< [20..20] Counter/Timer 10 interrupt based on CMP0.                        */
      __IOM uint32_t TMR101INT  : 1;            /*!< [21..21] Counter/Timer 10 interrupt based on CMP1.                        */
      __IOM uint32_t TMR110INT  : 1;            /*!< [22..22] Counter/Timer 11 interrupt based on CMP0.                        */
      __IOM uint32_t TMR111INT  : 1;            /*!< [23..23] Counter/Timer 11 interrupt based on CMP1.                        */
      __IOM uint32_t TMR120INT  : 1;            /*!< [24..24] Counter/Timer 12 interrupt based on CMP0.                        */
      __IOM uint32_t TMR121INT  : 1;            /*!< [25..25] Counter/Timer 12 interrupt based on CMP1.                        */
      __IOM uint32_t TMR130INT  : 1;            /*!< [26..26] Counter/Timer 13 interrupt based on CMP0.                        */
      __IOM uint32_t TMR131INT  : 1;            /*!< [27..27] Counter/Timer 13 interrupt based on CMP1.                        */
      __IOM uint32_t TMR140INT  : 1;            /*!< [28..28] Counter/Timer 14 interrupt based on CMP0.                        */
      __IOM uint32_t TMR141INT  : 1;            /*!< [29..29] Counter/Timer 14 interrupt based on CMP1.                        */
      __IOM uint32_t TMR150INT  : 1;            /*!< [30..30] Counter/Timer 15 interrupt based on CMP0.                        */
      __IOM uint32_t TMR151INT  : 1;            /*!< [31..31] Counter/Timer 15 interrupt based on CMP1.                        */
    } INTSTAT_b;
  } ;

  union {
    __IOM uint32_t INTCLR;                      /*!< (@ 0x00000068) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t TMR00INT   : 1;            /*!< [0..0] Counter/Timer 0 interrupt based on CMP0.                           */
      __IOM uint32_t TMR01INT   : 1;            /*!< [1..1] Counter/Timer 0 interrupt based on CMP1.                           */
      __IOM uint32_t TMR10INT   : 1;            /*!< [2..2] Counter/Timer 1 interrupt based on CMP0.                           */
      __IOM uint32_t TMR11INT   : 1;            /*!< [3..3] Counter/Timer 1 interrupt based on CMP1.                           */
      __IOM uint32_t TMR20INT   : 1;            /*!< [4..4] Counter/Timer 2 interrupt based on CMP0.                           */
      __IOM uint32_t TMR21INT   : 1;            /*!< [5..5] Counter/Timer 2 interrupt based on CMP1.                           */
      __IOM uint32_t TMR30INT   : 1;            /*!< [6..6] Counter/Timer 3 interrupt based on CMP0.                           */
      __IOM uint32_t TMR31INT   : 1;            /*!< [7..7] Counter/Timer 3 interrupt based on CMP1.                           */
      __IOM uint32_t TMR40INT   : 1;            /*!< [8..8] Counter/Timer 4 interrupt based on CMP0.                           */
      __IOM uint32_t TMR41INT   : 1;            /*!< [9..9] Counter/Timer 4 interrupt based on CMP1.                           */
      __IOM uint32_t TMR50INT   : 1;            /*!< [10..10] Counter/Timer 5 interrupt based on CMP0.                         */
      __IOM uint32_t TMR51INT   : 1;            /*!< [11..11] Counter/Timer 5 interrupt based on CMP1.                         */
      __IOM uint32_t TMR60INT   : 1;            /*!< [12..12] Counter/Timer 6 interrupt based on CMP0.                         */
      __IOM uint32_t TMR61INT   : 1;            /*!< [13..13] Counter/Timer 6 interrupt based on CMP1.                         */
      __IOM uint32_t TMR70INT   : 1;            /*!< [14..14] Counter/Timer 7 interrupt based on CMP0.                         */
      __IOM uint32_t TMR71INT   : 1;            /*!< [15..15] Counter/Timer 7 interrupt based on CMP1.                         */
      __IOM uint32_t TMR80INT   : 1;            /*!< [16..16] Counter/Timer 8 interrupt based on CMP0.                         */
      __IOM uint32_t TMR81INT   : 1;            /*!< [17..17] Counter/Timer 8 interrupt based on CMP1.                         */
      __IOM uint32_t TMR90INT   : 1;            /*!< [18..18] Counter/Timer 9 interrupt based on CMP0.                         */
      __IOM uint32_t TMR91INT   : 1;            /*!< [19..19] Counter/Timer 9 interrupt based on CMP1.                         */
      __IOM uint32_t TMR100INT  : 1;            /*!< [20..20] Counter/Timer 10 interrupt based on CMP0.                        */
      __IOM uint32_t TMR101INT  : 1;            /*!< [21..21] Counter/Timer 10 interrupt based on CMP1.                        */
      __IOM uint32_t TMR110INT  : 1;            /*!< [22..22] Counter/Timer 11 interrupt based on CMP0.                        */
      __IOM uint32_t TMR111INT  : 1;            /*!< [23..23] Counter/Timer 11 interrupt based on CMP1.                        */
      __IOM uint32_t TMR120INT  : 1;            /*!< [24..24] Counter/Timer 12 interrupt based on CMP0.                        */
      __IOM uint32_t TMR121INT  : 1;            /*!< [25..25] Counter/Timer 12 interrupt based on CMP1.                        */
      __IOM uint32_t TMR130INT  : 1;            /*!< [26..26] Counter/Timer 13 interrupt based on CMP0.                        */
      __IOM uint32_t TMR131INT  : 1;            /*!< [27..27] Counter/Timer 13 interrupt based on CMP1.                        */
      __IOM uint32_t TMR140INT  : 1;            /*!< [28..28] Counter/Timer 14 interrupt based on CMP0.                        */
      __IOM uint32_t TMR141INT  : 1;            /*!< [29..29] Counter/Timer 14 interrupt based on CMP1.                        */
      __IOM uint32_t TMR150INT  : 1;            /*!< [30..30] Counter/Timer 15 interrupt based on CMP0.                        */
      __IOM uint32_t TMR151INT  : 1;            /*!< [31..31] Counter/Timer 15 interrupt based on CMP1.                        */
    } INTCLR_b;
  } ;

  union {
    __IOM uint32_t INTSET;                      /*!< (@ 0x0000006C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t TMR00INT   : 1;            /*!< [0..0] Counter/Timer 0 interrupt based on CMP0.                           */
      __IOM uint32_t TMR01INT   : 1;            /*!< [1..1] Counter/Timer 0 interrupt based on CMP1.                           */
      __IOM uint32_t TMR10INT   : 1;            /*!< [2..2] Counter/Timer 1 interrupt based on CMP0.                           */
      __IOM uint32_t TMR11INT   : 1;            /*!< [3..3] Counter/Timer 1 interrupt based on CMP1.                           */
      __IOM uint32_t TMR20INT   : 1;            /*!< [4..4] Counter/Timer 2 interrupt based on CMP0.                           */
      __IOM uint32_t TMR21INT   : 1;            /*!< [5..5] Counter/Timer 2 interrupt based on CMP1.                           */
      __IOM uint32_t TMR30INT   : 1;            /*!< [6..6] Counter/Timer 3 interrupt based on CMP0.                           */
      __IOM uint32_t TMR31INT   : 1;            /*!< [7..7] Counter/Timer 3 interrupt based on CMP1.                           */
      __IOM uint32_t TMR40INT   : 1;            /*!< [8..8] Counter/Timer 4 interrupt based on CMP0.                           */
      __IOM uint32_t TMR41INT   : 1;            /*!< [9..9] Counter/Timer 4 interrupt based on CMP1.                           */
      __IOM uint32_t TMR50INT   : 1;            /*!< [10..10] Counter/Timer 5 interrupt based on CMP0.                         */
      __IOM uint32_t TMR51INT   : 1;            /*!< [11..11] Counter/Timer 5 interrupt based on CMP1.                         */
      __IOM uint32_t TMR60INT   : 1;            /*!< [12..12] Counter/Timer 6 interrupt based on CMP0.                         */
      __IOM uint32_t TMR61INT   : 1;            /*!< [13..13] Counter/Timer 6 interrupt based on CMP1.                         */
      __IOM uint32_t TMR70INT   : 1;            /*!< [14..14] Counter/Timer 7 interrupt based on CMP0.                         */
      __IOM uint32_t TMR71INT   : 1;            /*!< [15..15] Counter/Timer 7 interrupt based on CMP1.                         */
      __IOM uint32_t TMR80INT   : 1;            /*!< [16..16] Counter/Timer 8 interrupt based on CMP0.                         */
      __IOM uint32_t TMR81INT   : 1;            /*!< [17..17] Counter/Timer 8 interrupt based on CMP1.                         */
      __IOM uint32_t TMR90INT   : 1;            /*!< [18..18] Counter/Timer 9 interrupt based on CMP0.                         */
      __IOM uint32_t TMR91INT   : 1;            /*!< [19..19] Counter/Timer 9 interrupt based on CMP1.                         */
      __IOM uint32_t TMR100INT  : 1;            /*!< [20..20] Counter/Timer 10 interrupt based on CMP0.                        */
      __IOM uint32_t TMR101INT  : 1;            /*!< [21..21] Counter/Timer 10 interrupt based on CMP1.                        */
      __IOM uint32_t TMR110INT  : 1;            /*!< [22..22] Counter/Timer 11 interrupt based on CMP0.                        */
      __IOM uint32_t TMR111INT  : 1;            /*!< [23..23] Counter/Timer 11 interrupt based on CMP1.                        */
      __IOM uint32_t TMR120INT  : 1;            /*!< [24..24] Counter/Timer 12 interrupt based on CMP0.                        */
      __IOM uint32_t TMR121INT  : 1;            /*!< [25..25] Counter/Timer 12 interrupt based on CMP1.                        */
      __IOM uint32_t TMR130INT  : 1;            /*!< [26..26] Counter/Timer 13 interrupt based on CMP0.                        */
      __IOM uint32_t TMR131INT  : 1;            /*!< [27..27] Counter/Timer 13 interrupt based on CMP1.                        */
      __IOM uint32_t TMR140INT  : 1;            /*!< [28..28] Counter/Timer 14 interrupt based on CMP0.                        */
      __IOM uint32_t TMR141INT  : 1;            /*!< [29..29] Counter/Timer 14 interrupt based on CMP1.                        */
      __IOM uint32_t TMR150INT  : 1;            /*!< [30..30] Counter/Timer 15 interrupt based on CMP0.                        */
      __IOM uint32_t TMR151INT  : 1;            /*!< [31..31] Counter/Timer 15 interrupt based on CMP1.                        */
    } INTSET_b;
  } ;
  __IM  uint32_t  RESERVED2[4];

  union {
    __IOM uint32_t OUTCFG0;                     /*!< (@ 0x00000080) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG0    : 6;            /*!< [5..0] Pad output 0 configuration                                         */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG1    : 6;            /*!< [13..8] Pad output 1 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG2    : 6;            /*!< [21..16] Pad output 2 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG3    : 6;            /*!< [29..24] Pad output 3 configuration                                       */
            uint32_t            : 2;
    } OUTCFG0_b;
  } ;

  union {
    __IOM uint32_t OUTCFG1;                     /*!< (@ 0x00000084) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG4    : 6;            /*!< [5..0] Pad output 4 configuration                                         */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG5    : 6;            /*!< [13..8] Pad output 5 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG6    : 6;            /*!< [21..16] Pad output 6 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG7    : 6;            /*!< [29..24] Pad output 7 configuration                                       */
            uint32_t            : 2;
    } OUTCFG1_b;
  } ;

  union {
    __IOM uint32_t OUTCFG2;                     /*!< (@ 0x00000088) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG8    : 6;            /*!< [5..0] Pad output 8 configuration                                         */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG9    : 6;            /*!< [13..8] Pad output 9 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG10   : 6;            /*!< [21..16] Pad output 10 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG11   : 6;            /*!< [29..24] Pad output 11 configuration                                      */
            uint32_t            : 2;
    } OUTCFG2_b;
  } ;

  union {
    __IOM uint32_t OUTCFG3;                     /*!< (@ 0x0000008C) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG12   : 6;            /*!< [5..0] Pad output 12 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG13   : 6;            /*!< [13..8] Pad output 13 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG14   : 6;            /*!< [21..16] Pad output 14 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG15   : 6;            /*!< [29..24] Pad output 15 configuration                                      */
            uint32_t            : 2;
    } OUTCFG3_b;
  } ;

  union {
    __IOM uint32_t OUTCFG4;                     /*!< (@ 0x00000090) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG16   : 6;            /*!< [5..0] Pad output 16 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG17   : 6;            /*!< [13..8] Pad output 17 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG18   : 6;            /*!< [21..16] Pad output 18 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG19   : 6;            /*!< [29..24] Pad output 19 configuration                                      */
            uint32_t            : 2;
    } OUTCFG4_b;
  } ;

  union {
    __IOM uint32_t OUTCFG5;                     /*!< (@ 0x00000094) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG20   : 6;            /*!< [5..0] Pad output 20 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG21   : 6;            /*!< [13..8] Pad output 21 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG22   : 6;            /*!< [21..16] Pad output 22 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG23   : 6;            /*!< [29..24] Pad output 23 configuration                                      */
            uint32_t            : 2;
    } OUTCFG5_b;
  } ;

  union {
    __IOM uint32_t OUTCFG6;                     /*!< (@ 0x00000098) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG24   : 6;            /*!< [5..0] Pad output 24 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG25   : 6;            /*!< [13..8] Pad output 25 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG26   : 6;            /*!< [21..16] Pad output 26 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG27   : 6;            /*!< [29..24] Pad output 27 configuration                                      */
            uint32_t            : 2;
    } OUTCFG6_b;
  } ;

  union {
    __IOM uint32_t OUTCFG7;                     /*!< (@ 0x0000009C) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG28   : 6;            /*!< [5..0] Pad output 28 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG29   : 6;            /*!< [13..8] Pad output 29 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG30   : 6;            /*!< [21..16] Pad output 30 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG31   : 6;            /*!< [29..24] Pad output 31 configuration                                      */
            uint32_t            : 2;
    } OUTCFG7_b;
  } ;

  union {
    __IOM uint32_t OUTCFG8;                     /*!< (@ 0x000000A0) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG32   : 6;            /*!< [5..0] Pad output 32 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG33   : 6;            /*!< [13..8] Pad output 33 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG34   : 6;            /*!< [21..16] Pad output 34 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG35   : 6;            /*!< [29..24] Pad output 35 configuration                                      */
            uint32_t            : 2;
    } OUTCFG8_b;
  } ;

  union {
    __IOM uint32_t OUTCFG9;                     /*!< (@ 0x000000A4) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG36   : 6;            /*!< [5..0] Pad output 36 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG37   : 6;            /*!< [13..8] Pad output 37 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG38   : 6;            /*!< [21..16] Pad output 38 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG39   : 6;            /*!< [29..24] Pad output 39 configuration                                      */
            uint32_t            : 2;
    } OUTCFG9_b;
  } ;

  union {
    __IOM uint32_t OUTCFG10;                    /*!< (@ 0x000000A8) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG40   : 6;            /*!< [5..0] Pad output 40 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG41   : 6;            /*!< [13..8] Pad output 41 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG42   : 6;            /*!< [21..16] Pad output 42 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG43   : 6;            /*!< [29..24] Pad output 43 configuration                                      */
            uint32_t            : 2;
    } OUTCFG10_b;
  } ;

  union {
    __IOM uint32_t OUTCFG11;                    /*!< (@ 0x000000AC) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG44   : 6;            /*!< [5..0] Pad output 44 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG45   : 6;            /*!< [13..8] Pad output 45 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG46   : 6;            /*!< [21..16] Pad output 46 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG47   : 6;            /*!< [29..24] Pad output 47 configuration                                      */
            uint32_t            : 2;
    } OUTCFG11_b;
  } ;

  union {
    __IOM uint32_t OUTCFG12;                    /*!< (@ 0x000000B0) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG48   : 6;            /*!< [5..0] Pad output 48 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG49   : 6;            /*!< [13..8] Pad output 49 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG50   : 6;            /*!< [21..16] Pad output 50 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG51   : 6;            /*!< [29..24] Pad output 51 configuration                                      */
            uint32_t            : 2;
    } OUTCFG12_b;
  } ;

  union {
    __IOM uint32_t OUTCFG13;                    /*!< (@ 0x000000B4) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG52   : 6;            /*!< [5..0] Pad output 52 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG53   : 6;            /*!< [13..8] Pad output 53 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG54   : 6;            /*!< [21..16] Pad output 54 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG55   : 6;            /*!< [29..24] Pad output 55 configuration                                      */
            uint32_t            : 2;
    } OUTCFG13_b;
  } ;

  union {
    __IOM uint32_t OUTCFG14;                    /*!< (@ 0x000000B8) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG56   : 6;            /*!< [5..0] Pad output 56 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG57   : 6;            /*!< [13..8] Pad output 57 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG58   : 6;            /*!< [21..16] Pad output 58 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG59   : 6;            /*!< [29..24] Pad output 59 configuration                                      */
            uint32_t            : 2;
    } OUTCFG14_b;
  } ;

  union {
    __IOM uint32_t OUTCFG15;                    /*!< (@ 0x000000BC) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG60   : 6;            /*!< [5..0] Pad output 60 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG61   : 6;            /*!< [13..8] Pad output 61 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG62   : 6;            /*!< [21..16] Pad output 62 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG63   : 6;            /*!< [29..24] Pad output 63 configuration                                      */
            uint32_t            : 2;
    } OUTCFG15_b;
  } ;

  union {
    __IOM uint32_t OUTCFG16;                    /*!< (@ 0x000000C0) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG64   : 6;            /*!< [5..0] Pad output 64 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG65   : 6;            /*!< [13..8] Pad output 65 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG66   : 6;            /*!< [21..16] Pad output 66 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG67   : 6;            /*!< [29..24] Pad output 67 configuration                                      */
            uint32_t            : 2;
    } OUTCFG16_b;
  } ;

  union {
    __IOM uint32_t OUTCFG17;                    /*!< (@ 0x000000C4) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG68   : 6;            /*!< [5..0] Pad output 68 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG69   : 6;            /*!< [13..8] Pad output 69 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG70   : 6;            /*!< [21..16] Pad output 70 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG71   : 6;            /*!< [29..24] Pad output 71 configuration                                      */
            uint32_t            : 2;
    } OUTCFG17_b;
  } ;

  union {
    __IOM uint32_t OUTCFG18;                    /*!< (@ 0x000000C8) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG72   : 6;            /*!< [5..0] Pad output 72 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG73   : 6;            /*!< [13..8] Pad output 73 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG74   : 6;            /*!< [21..16] Pad output 74 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG75   : 6;            /*!< [29..24] Pad output 75 configuration                                      */
            uint32_t            : 2;
    } OUTCFG18_b;
  } ;

  union {
    __IOM uint32_t OUTCFG19;                    /*!< (@ 0x000000CC) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG76   : 6;            /*!< [5..0] Pad output 76 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG77   : 6;            /*!< [13..8] Pad output 77 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG78   : 6;            /*!< [21..16] Pad output 78 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG79   : 6;            /*!< [29..24] Pad output 79 configuration                                      */
            uint32_t            : 2;
    } OUTCFG19_b;
  } ;

  union {
    __IOM uint32_t OUTCFG20;                    /*!< (@ 0x000000D0) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG80   : 6;            /*!< [5..0] Pad output 80 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG81   : 6;            /*!< [13..8] Pad output 81 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG82   : 6;            /*!< [21..16] Pad output 82 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG83   : 6;            /*!< [29..24] Pad output 83 configuration                                      */
            uint32_t            : 2;
    } OUTCFG20_b;
  } ;

  union {
    __IOM uint32_t OUTCFG21;                    /*!< (@ 0x000000D4) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG84   : 6;            /*!< [5..0] Pad output 84 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG85   : 6;            /*!< [13..8] Pad output 85 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG86   : 6;            /*!< [21..16] Pad output 86 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG87   : 6;            /*!< [29..24] Pad output 87 configuration                                      */
            uint32_t            : 2;
    } OUTCFG21_b;
  } ;

  union {
    __IOM uint32_t OUTCFG22;                    /*!< (@ 0x000000D8) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG88   : 6;            /*!< [5..0] Pad output 88 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG89   : 6;            /*!< [13..8] Pad output 89 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG90   : 6;            /*!< [21..16] Pad output 90 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG91   : 6;            /*!< [29..24] Pad output 91 configuration                                      */
            uint32_t            : 2;
    } OUTCFG22_b;
  } ;

  union {
    __IOM uint32_t OUTCFG23;                    /*!< (@ 0x000000DC) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG92   : 6;            /*!< [5..0] Pad output 92 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG93   : 6;            /*!< [13..8] Pad output 93 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG94   : 6;            /*!< [21..16] Pad output 94 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG95   : 6;            /*!< [29..24] Pad output 95 configuration                                      */
            uint32_t            : 2;
    } OUTCFG23_b;
  } ;

  union {
    __IOM uint32_t OUTCFG24;                    /*!< (@ 0x000000E0) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG96   : 6;            /*!< [5..0] Pad output 96 configuration                                        */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG97   : 6;            /*!< [13..8] Pad output 97 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG98   : 6;            /*!< [21..16] Pad output 98 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG99   : 6;            /*!< [29..24] Pad output 99 configuration                                      */
            uint32_t            : 2;
    } OUTCFG24_b;
  } ;

  union {
    __IOM uint32_t OUTCFG25;                    /*!< (@ 0x000000E4) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG100  : 6;            /*!< [5..0] Pad output 100 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG101  : 6;            /*!< [13..8] Pad output 101 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG102  : 6;            /*!< [21..16] Pad output 102 configuration                                     */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG103  : 6;            /*!< [29..24] Pad output 103 configuration                                     */
            uint32_t            : 2;
    } OUTCFG25_b;
  } ;

  union {
    __IOM uint32_t OUTCFG26;                    /*!< (@ 0x000000E8) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG104  : 6;            /*!< [5..0] Pad output 104 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG105  : 6;            /*!< [13..8] Pad output 105 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG106  : 6;            /*!< [21..16] Pad output 106 configuration                                     */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG107  : 6;            /*!< [29..24] Pad output 107 configuration                                     */
            uint32_t            : 2;
    } OUTCFG26_b;
  } ;

  union {
    __IOM uint32_t OUTCFG27;                    /*!< (@ 0x000000EC) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG108  : 6;            /*!< [5..0] Pad output 108 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG109  : 6;            /*!< [13..8] Pad output 109 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG110  : 6;            /*!< [21..16] Pad output 110 configuration                                     */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG111  : 6;            /*!< [29..24] Pad output 111 configuration                                     */
            uint32_t            : 2;
    } OUTCFG27_b;
  } ;

  union {
    __IOM uint32_t OUTCFG28;                    /*!< (@ 0x000000F0) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG112  : 6;            /*!< [5..0] Pad output 112 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG113  : 6;            /*!< [13..8] Pad output 113 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG114  : 6;            /*!< [21..16] Pad output 114 configuration                                     */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG115  : 6;            /*!< [29..24] Pad output 115 configuration                                     */
            uint32_t            : 2;
    } OUTCFG28_b;
  } ;

  union {
    __IOM uint32_t OUTCFG29;                    /*!< (@ 0x000000F4) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG116  : 6;            /*!< [5..0] Pad output 116 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG117  : 6;            /*!< [13..8] Pad output 117 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG118  : 6;            /*!< [21..16] Pad output 118 configuration                                     */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG119  : 6;            /*!< [29..24] Pad output 119 configuration                                     */
            uint32_t            : 2;
    } OUTCFG29_b;
  } ;

  union {
    __IOM uint32_t OUTCFG30;                    /*!< (@ 0x000000F8) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG120  : 6;            /*!< [5..0] Pad output 120 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG121  : 6;            /*!< [13..8] Pad output 121 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG122  : 6;            /*!< [21..16] Pad output 122 configuration                                     */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG123  : 6;            /*!< [29..24] Pad output 123 configuration                                     */
            uint32_t            : 2;
    } OUTCFG30_b;
  } ;

  union {
    __IOM uint32_t OUTCFG31;                    /*!< (@ 0x000000FC) Pad output configuration 0.                                */

    struct {
      __IOM uint32_t OUTCFG124  : 6;            /*!< [5..0] Pad output 124 configuration                                       */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG125  : 6;            /*!< [13..8] Pad output 125 configuration                                      */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG126  : 6;            /*!< [21..16] Pad output 126 configuration                                     */
            uint32_t            : 2;
      __IOM uint32_t OUTCFG127  : 6;            /*!< [29..24] Pad output 127 configuration                                     */
            uint32_t            : 2;
    } OUTCFG31_b;
  } ;
  __IM  uint32_t  RESERVED3[64];

  union {
    __IOM uint32_t CTRL0;                       /*!< (@ 0x00000200) This includes the Control bit fields for timer
                                                                    0.                                                         */

    struct {
      __IOM uint32_t TMR0EN     : 1;            /*!< [0..0] Counter/Timer 0 Enable bit.                                        */
      __IOM uint32_t TMR0CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
      __IOM uint32_t TMR0POL0   : 1;            /*!< [2..2] Counter/Timer 0 output 0 polarity.                                 */
      __IOM uint32_t TMR0POL1   : 1;            /*!< [3..3] Counter/Timer 0 output 1 polarity.                                 */
      __IOM uint32_t TMR0FN     : 4;            /*!< [7..4] Counter/Timer 0 Function Select. For all Functions, CMP0
                                                     marks the end of timer cycle, and thus restarts the timer.                */
      __IOM uint32_t TMR0CLK    : 8;            /*!< [15..8] Counter/Timer 0 Clock Select.                                     */
      __IOM uint32_t TMR0TMODE  : 2;            /*!< [17..16] Counter/Timer 0 Trigger Mode                                     */
            uint32_t            : 6;
      __IOM uint32_t TMR0LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
                                                     0. For Single/Repeat Patterns, it indicates number of bits
                                                     to be shifted out and so, max value is 63.                                */
    } CTRL0_b;
  } ;

  union {
    __IOM uint32_t TIMER0;                      /*!< (@ 0x00000204) This register holds the running time or event
                                                                    count for timer 0.                                         */

    struct {
      __IOM uint32_t TIMER0     : 32;           /*!< [31..0] Counter/Timer 0                                                   */
    } TIMER0_b;
  } ;

  union {
    __IOM uint32_t TMR0CMP0;                    /*!< (@ 0x00000208) This contains the Compare limits for timer 0.
                                                                    This is the primary comparator that can
                                                                    be used to mark the END of a timer cycle
                                                                    (and thus restart the timer for repeat modes)              */

    struct {
      __IOM uint32_t TMR0CMP0   : 32;           /*!< [31..0] Counter/Timer 0 End Compare Register. For MEASURE mode
                                                     indicates the high phase sample count.                                    */
    } TMR0CMP0_b;
  } ;

  union {
    __IOM uint32_t TMR0CMP1;                    /*!< (@ 0x0000020C) This comparator is used as a secondary compare
                                                                    count for modes that generate pulses. For
                                                                    MEASURE mode indicates the low phase sample
                                                                    count.                                                     */

    struct {
      __IOM uint32_t TMR0CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
                                                     a PWM or generate secondary pulses. CMP0 should ALWAYS
                                                     be used first.                                                            */
    } TMR0CMP1_b;
  } ;

  union {
    __IOM uint32_t MODE0;                       /*!< (@ 0x00000210) The mode register contains optional mode controls
                                                                    for the timer                                              */

    struct {
            uint32_t            : 8;
      __IOM uint32_t TMR0TRIGSEL : 8;           /*!< [15..8] Counter/Timer 0 Trigger Source Selection                          */
            uint32_t            : 16;
    } MODE0_b;
  } ;

  union {
    __IOM uint32_t TMR0LMTVAL;                  /*!< (@ 0x00000214) This is an internal counter in the hardware that
                                                                    counts down from TMR_LMT to 1                              */

    struct {
      __IOM uint32_t TMR0LMTVAL : 8;            /*!< [7..0] Counter/Timer 0 Limit Readback                                     */
            uint32_t            : 24;
    } TMR0LMTVAL_b;
  } ;
  __IM  uint32_t  RESERVED4[2];

  union {
    __IOM uint32_t CTRL1;                       /*!< (@ 0x00000220) This includes the Control bit fields for timer
                                                                    1.                                                         */

    struct {
      __IOM uint32_t TMR1EN     : 1;            /*!< [0..0] Counter/Timer 1 Enable bit.                                        */
      __IOM uint32_t TMR1CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
      __IOM uint32_t TMR1POL0   : 1;            /*!< [2..2] Counter/Timer 1 output 0 polarity.                                 */
      __IOM uint32_t TMR1POL1   : 1;            /*!< [3..3] Counter/Timer 1 output 1 polarity.                                 */
      __IOM uint32_t TMR1FN     : 4;            /*!< [7..4] Counter/Timer 1 Function Select. For all Functions, CMP0
                                                     marks the end of timer cycle, and thus restarts the timer.                */
      __IOM uint32_t TMR1CLK    : 8;            /*!< [15..8] Counter/Timer 1 Clock Select.                                     */
      __IOM uint32_t TMR1TMODE  : 2;            /*!< [17..16] Counter/Timer 1 Trigger Mode                                     */
            uint32_t            : 6;
      __IOM uint32_t TMR1LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
                                                     1. For Single/Repeat Patterns, it indicates number of bits
                                                     to be shifted out and so, max value is 63.                                */
    } CTRL1_b;
  } ;

  union {
    __IOM uint32_t TIMER1;                      /*!< (@ 0x00000224) This register holds the running time or event
                                                                    count for timer 1.                                         */

    struct {
      __IOM uint32_t TIMER1     : 32;           /*!< [31..0] Counter/Timer 1                                                   */
    } TIMER1_b;
  } ;

  union {
    __IOM uint32_t TMR1CMP0;                    /*!< (@ 0x00000228) This contains the Compare limits for timer 1.
                                                                    This is the primary comparator that can
                                                                    be used to mark the END of a timer cycle
                                                                    (and thus restart the timer for repeat modes)              */

    struct {
      __IOM uint32_t TMR1CMP0   : 32;           /*!< [31..0] Counter/Timer 1 End Compare Register. For MEASURE mode
                                                     indicates the high phase sample count.                                    */
    } TMR1CMP0_b;
  } ;

  union {
    __IOM uint32_t TMR1CMP1;                    /*!< (@ 0x0000022C) This comparator is used as a secondary compare
                                                                    count for modes that generate pulses. For
                                                                    MEASURE mode indicates the low phase sample
                                                                    count.                                                     */

    struct {
      __IOM uint32_t TMR1CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
                                                     a PWM or generate secondary pulses. CMP0 should ALWAYS
                                                     be used first.                                                            */
    } TMR1CMP1_b;
  } ;

  union {
    __IOM uint32_t MODE1;                       /*!< (@ 0x00000230) The mode register contains optional mode controls
                                                                    for the timer                                              */

    struct {
            uint32_t            : 8;
      __IOM uint32_t TMR1TRIGSEL : 8;           /*!< [15..8] Counter/Timer 1 Trigger Source Selection                          */
            uint32_t            : 16;
    } MODE1_b;
  } ;

  union {
    __IOM uint32_t TMR1LMTVAL;                  /*!< (@ 0x00000234) This is an internal counter in the hardware that
                                                                    counts down from TMR_LMT to 1                              */

    struct {
      __IOM uint32_t TMR1LMTVAL : 8;            /*!< [7..0] Counter/Timer 1 Limit Readback                                     */
            uint32_t            : 24;
    } TMR1LMTVAL_b;
  } ;
  __IM  uint32_t  RESERVED5[2];

  union {
    __IOM uint32_t CTRL2;                       /*!< (@ 0x00000240) This includes the Control bit fields for timer
                                                                    2.                                                         */

    struct {
      __IOM uint32_t TMR2EN     : 1;            /*!< [0..0] Counter/Timer 2 Enable bit.                                        */
      __IOM uint32_t TMR2CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
      __IOM uint32_t TMR2POL0   : 1;            /*!< [2..2] Counter/Timer 2 output 0 polarity.                                 */
      __IOM uint32_t TMR2POL1   : 1;            /*!< [3..3] Counter/Timer 2 output 1 polarity.                                 */
      __IOM uint32_t TMR2FN     : 4;            /*!< [7..4] Counter/Timer 2 Function Select. For all Functions, CMP0
                                                     marks the end of timer cycle, and thus restarts the timer.                */
      __IOM uint32_t TMR2CLK    : 8;            /*!< [15..8] Counter/Timer 2 Clock Select.                                     */
      __IOM uint32_t TMR2TMODE  : 2;            /*!< [17..16] Counter/Timer 2 Trigger Mode                                     */
            uint32_t            : 6;
      __IOM uint32_t TMR2LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
                                                     2. For Single/Repeat Patterns, it indicates number of bits
                                                     to be shifted out and so, max value is 63.                                */
    } CTRL2_b;
  } ;

  union {
    __IOM uint32_t TIMER2;                      /*!< (@ 0x00000244) This register holds the running time or event
                                                                    count for timer 2.                                         */

    struct {
      __IOM uint32_t TIMER2     : 32;           /*!< [31..0] Counter/Timer 2                                                   */
    } TIMER2_b;
  } ;

  union {
    __IOM uint32_t TMR2CMP0;                    /*!< (@ 0x00000248) This contains the Compare limits for timer 2.
                                                                    This is the primary comparator that can
                                                                    be used to mark the END of a timer cycle
                                                                    (and thus restart the timer for repeat modes)              */

    struct {
      __IOM uint32_t TMR2CMP0   : 32;           /*!< [31..0] Counter/Timer 2 End Compare Register. For MEASURE mode
                                                     indicates the high phase sample count.                                    */
    } TMR2CMP0_b;
  } ;

  union {
    __IOM uint32_t TMR2CMP1;                    /*!< (@ 0x0000024C) This comparator is used as a secondary compare
                                                                    count for modes that generate pulses. For
                                                                    MEASURE mode indicates the low phase sample
                                                                    count.                                                     */

    struct {
      __IOM uint32_t TMR2CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
                                                     a PWM or generate secondary pulses. CMP0 should ALWAYS
                                                     be used first.                                                            */
    } TMR2CMP1_b;
  } ;

  union {
    __IOM uint32_t MODE2;                       /*!< (@ 0x00000250) The mode register contains optional mode controls
                                                                    for the timer                                              */

    struct {
            uint32_t            : 8;
      __IOM uint32_t TMR2TRIGSEL : 8;           /*!< [15..8] Counter/Timer 2 Trigger Source Selection                          */
            uint32_t            : 16;
    } MODE2_b;
  } ;

  union {
    __IOM uint32_t TMR2LMTVAL;                  /*!< (@ 0x00000254) This is an internal counter in the hardware that
                                                                    counts down from TMR_LMT to 1                              */

    struct {
      __IOM uint32_t TMR2LMTVAL : 8;            /*!< [7..0] Counter/Timer 2 Limit Readback                                     */
            uint32_t            : 24;
    } TMR2LMTVAL_b;
  } ;
  __IM  uint32_t  RESERVED6[2];

  union {
    __IOM uint32_t CTRL3;                       /*!< (@ 0x00000260) This includes the Control bit fields for timer
                                                                    3.                                                         */

    struct {
      __IOM uint32_t TMR3EN     : 1;            /*!< [0..0] Counter/Timer 3 Enable bit.                                        */
      __IOM uint32_t TMR3CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
      __IOM uint32_t TMR3POL0   : 1;            /*!< [2..2] Counter/Timer 3 output 0 polarity.                                 */
      __IOM uint32_t TMR3POL1   : 1;            /*!< [3..3] Counter/Timer 3 output 1 polarity.                                 */
      __IOM uint32_t TMR3FN     : 4;            /*!< [7..4] Counter/Timer 3 Function Select. For all Functions, CMP0
                                                     marks the end of timer cycle, and thus restarts the timer.                */
      __IOM uint32_t TMR3CLK    : 8;            /*!< [15..8] Counter/Timer 3 Clock Select.                                     */
      __IOM uint32_t TMR3TMODE  : 2;            /*!< [17..16] Counter/Timer 3 Trigger Mode                                     */
            uint32_t            : 6;
      __IOM uint32_t TMR3LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
                                                     3. For Single/Repeat Patterns, it indicates number of bits
                                                     to be shifted out and so, max value is 63.                                */
    } CTRL3_b;
  } ;

  union {
    __IOM uint32_t TIMER3;                      /*!< (@ 0x00000264) This register holds the running time or event
                                                                    count for timer 3.                                         */

    struct {
      __IOM uint32_t TIMER3     : 32;           /*!< [31..0] Counter/Timer 3                                                   */
    } TIMER3_b;
  } ;

  union {
    __IOM uint32_t TMR3CMP0;                    /*!< (@ 0x00000268) This contains the Compare limits for timer 3.
                                                                    This is the primary comparator that can
                                                                    be used to mark the END of a timer cycle
                                                                    (and thus restart the timer for repeat modes)              */

    struct {
      __IOM uint32_t TMR3CMP0   : 32;           /*!< [31..0] Counter/Timer 3 End Compare Register. For MEASURE mode
                                                     indicates the high phase sample count.                                    */
    } TMR3CMP0_b;
  } ;

  union {
    __IOM uint32_t TMR3CMP1;                    /*!< (@ 0x0000026C) This comparator is used as a secondary compare
                                                                    count for modes that generate pulses. For
                                                                    MEASURE mode indicates the low phase sample
                                                                    count.                                                     */

    struct {
      __IOM uint32_t TMR3CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
                                                     a PWM or generate secondary pulses. CMP0 should ALWAYS
                                                     be used first.                                                            */
    } TMR3CMP1_b;
  } ;

  union {
    __IOM uint32_t MODE3;                       /*!< (@ 0x00000270) The mode register contains optional mode controls
                                                                    for the timer                                              */

    struct {
            uint32_t            : 8;
      __IOM uint32_t TMR3TRIGSEL : 8;           /*!< [15..8] Counter/Timer 3 Trigger Source Selection                          */
            uint32_t            : 16;
    } MODE3_b;
  } ;

  union {
    __IOM uint32_t TMR3LMTVAL;                  /*!< (@ 0x00000274) This is an internal counter in the hardware that
                                                                    counts down from TMR_LMT to 1                              */

    struct {
      __IOM uint32_t TMR3LMTVAL : 8;            /*!< [7..0] Counter/Timer 3 Limit Readback                                     */
            uint32_t            : 24;
    } TMR3LMTVAL_b;
  } ;
  __IM  uint32_t  RESERVED7[2];

  union {
    __IOM uint32_t CTRL4;                       /*!< (@ 0x00000280) This includes the Control bit fields for timer
                                                                    4.                                                         */

    struct {
      __IOM uint32_t TMR4EN     : 1;            /*!< [0..0] Counter/Timer 4 Enable bit.                                        */
      __IOM uint32_t TMR4CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
      __IOM uint32_t TMR4POL0   : 1;            /*!< [2..2] Counter/Timer 4 output 0 polarity.                                 */
      __IOM uint32_t TMR4POL1   : 1;            /*!< [3..3] Counter/Timer 4 output 1 polarity.                                 */
      __IOM uint32_t TMR4FN     : 4;            /*!< [7..4] Counter/Timer 4 Function Select. For all Functions, CMP0
                                                     marks the end of timer cycle, and thus restarts the timer.                */
      __IOM uint32_t TMR4CLK    : 8;            /*!< [15..8] Counter/Timer 4 Clock Select.                                     */
      __IOM uint32_t TMR4TMODE  : 2;            /*!< [17..16] Counter/Timer 4 Trigger Mode                                     */
            uint32_t            : 6;
      __IOM uint32_t TMR4LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
                                                     4. For Single/Repeat Patterns, it indicates number of bits
                                                     to be shifted out and so, max value is 63.                                */
    } CTRL4_b;
  } ;

  union {
    __IOM uint32_t TIMER4;                      /*!< (@ 0x00000284) This register holds the running time or event
                                                                    count for timer 4.                                         */

    struct {
      __IOM uint32_t TIMER4     : 32;           /*!< [31..0] Counter/Timer 4                                                   */
    } TIMER4_b;
  } ;

  union {
    __IOM uint32_t TMR4CMP0;                    /*!< (@ 0x00000288) This contains the Compare limits for timer 4.
                                                                    This is the primary comparator that can
                                                                    be used to mark the END of a timer cycle
                                                                    (and thus restart the timer for repeat modes)              */

    struct {
      __IOM uint32_t TMR4CMP0   : 32;           /*!< [31..0] Counter/Timer 4 End Compare Register. For MEASURE mode
                                                     indicates the high phase sample count.                                    */
    } TMR4CMP0_b;
  } ;

  union {
    __IOM uint32_t TMR4CMP1;                    /*!< (@ 0x0000028C) This comparator is used as a secondary compare
                                                                    count for modes that generate pulses. For
                                                                    MEASURE mode indicates the low phase sample
                                                                    count.                                                     */

    struct {
      __IOM uint32_t TMR4CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
                                                     a PWM or generate secondary pulses. CMP0 should ALWAYS
                                                     be used first.                                                            */
    } TMR4CMP1_b;
  } ;

  union {
    __IOM uint32_t MODE4;                       /*!< (@ 0x00000290) The mode register contains optional mode controls
                                                                    for the timer                                              */

    struct {
            uint32_t            : 8;
      __IOM uint32_t TMR4TRIGSEL : 8;           /*!< [15..8] Counter/Timer 4 Trigger Source Selection                          */
            uint32_t            : 16;
    } MODE4_b;
  } ;

  union {
    __IOM uint32_t TMR4LMTVAL;                  /*!< (@ 0x00000294) This is an internal counter in the hardware that
                                                                    counts down from TMR_LMT to 1                              */

    struct {
      __IOM uint32_t TMR4LMTVAL : 8;            /*!< [7..0] Counter/Timer 4 Limit Readback                                     */
            uint32_t            : 24;
    } TMR4LMTVAL_b;
  } ;
  __IM  uint32_t  RESERVED8[2];

  union {
    __IOM uint32_t CTRL5;                       /*!< (@ 0x000002A0) This includes the Control bit fields for timer
                                                                    5.                                                         */

    struct {
      __IOM uint32_t TMR5EN     : 1;            /*!< [0..0] Counter/Timer 5 Enable bit.                                        */
      __IOM uint32_t TMR5CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
      __IOM uint32_t TMR5POL0   : 1;            /*!< [2..2] Counter/Timer 5 output 0 polarity.                                 */
      __IOM uint32_t TMR5POL1   : 1;            /*!< [3..3] Counter/Timer 5 output 1 polarity.                                 */
      __IOM uint32_t TMR5FN     : 4;            /*!< [7..4] Counter/Timer 5 Function Select. For all Functions, CMP0
                                                     marks the end of timer cycle, and thus restarts the timer.                */
      __IOM uint32_t TMR5CLK    : 8;            /*!< [15..8] Counter/Timer 5 Clock Select.                                     */
      __IOM uint32_t TMR5TMODE  : 2;            /*!< [17..16] Counter/Timer 5 Trigger Mode                                     */
            uint32_t            : 6;
      __IOM uint32_t TMR5LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
                                                     5. For Single/Repeat Patterns, it indicates number of bits
                                                     to be shifted out and so, max value is 63.                                */
    } CTRL5_b;
  } ;

  union {
    __IOM uint32_t TIMER5;                      /*!< (@ 0x000002A4) This register holds the running time or event
                                                                    count for timer 5.                                         */

    struct {
      __IOM uint32_t TIMER5     : 32;           /*!< [31..0] Counter/Timer 5                                                   */
    } TIMER5_b;
  } ;

  union {
    __IOM uint32_t TMR5CMP0;                    /*!< (@ 0x000002A8) This contains the Compare limits for timer 5.
                                                                    This is the primary comparator that can
                                                                    be used to mark the END of a timer cycle
                                                                    (and thus restart the timer for repeat modes)              */

    struct {
      __IOM uint32_t TMR5CMP0   : 32;           /*!< [31..0] Counter/Timer 5 End Compare Register. For MEASURE mode
                                                     indicates the high phase sample count.                                    */
    } TMR5CMP0_b;
  } ;

  union {
    __IOM uint32_t TMR5CMP1;                    /*!< (@ 0x000002AC) This comparator is used as a secondary compare
                                                                    count for modes that generate pulses. For
                                                                    MEASURE mode indicates the low phase sample
                                                                    count.                                                     */

    struct {
      __IOM uint32_t TMR5CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
                                                     a PWM or generate secondary pulses. CMP0 should ALWAYS
                                                     be used first.                                                            */
    } TMR5CMP1_b;
  } ;

  union {
    __IOM uint32_t MODE5;                       /*!< (@ 0x000002B0) The mode register contains optional mode controls
                                                                    for the timer                                              */

    struct {
            uint32_t            : 8;
      __IOM uint32_t TMR5TRIGSEL : 8;           /*!< [15..8] Counter/Timer 5 Trigger Source Selection                          */
            uint32_t            : 16;
    } MODE5_b;
  } ;

  union {
    __IOM uint32_t TMR5LMTVAL;                  /*!< (@ 0x000002B4) This is an internal counter in the hardware that
                                                                    counts down from TMR_LMT to 1                              */

    struct {
      __IOM uint32_t TMR5LMTVAL : 8;            /*!< [7..0] Counter/Timer 5 Limit Readback                                     */
            uint32_t            : 24;
    } TMR5LMTVAL_b;
  } ;
  __IM  uint32_t  RESERVED9[2];

  union {
    __IOM uint32_t CTRL6;                       /*!< (@ 0x000002C0) This includes the Control bit fields for timer
                                                                    6.                                                         */

    struct {
      __IOM uint32_t TMR6EN     : 1;            /*!< [0..0] Counter/Timer 6 Enable bit.                                        */
      __IOM uint32_t TMR6CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
      __IOM uint32_t TMR6POL0   : 1;            /*!< [2..2] Counter/Timer 6 output 0 polarity.                                 */
      __IOM uint32_t TMR6POL1   : 1;            /*!< [3..3] Counter/Timer 6 output 1 polarity.                                 */
      __IOM uint32_t TMR6FN     : 4;            /*!< [7..4] Counter/Timer 6 Function Select. For all Functions, CMP0
                                                     marks the end of timer cycle, and thus restarts the timer.                */
      __IOM uint32_t TMR6CLK    : 8;            /*!< [15..8] Counter/Timer 6 Clock Select.                                     */
      __IOM uint32_t TMR6TMODE  : 2;            /*!< [17..16] Counter/Timer 6 Trigger Mode                                     */
            uint32_t            : 6;
      __IOM uint32_t TMR6LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
                                                     6. For Single/Repeat Patterns, it indicates number of bits
                                                     to be shifted out and so, max value is 63.                                */
    } CTRL6_b;
  } ;

  union {
    __IOM uint32_t TIMER6;                      /*!< (@ 0x000002C4) This register holds the running time or event
                                                                    count for timer 6.                                         */

    struct {
      __IOM uint32_t TIMER6     : 32;           /*!< [31..0] Counter/Timer 6                                                   */
    } TIMER6_b;
  } ;

  union {
    __IOM uint32_t TMR6CMP0;                    /*!< (@ 0x000002C8) This contains the Compare limits for timer 6.
                                                                    This is the primary comparator that can
                                                                    be used to mark the END of a timer cycle
                                                                    (and thus restart the timer for repeat modes)              */

    struct {
      __IOM uint32_t TMR6CMP0   : 32;           /*!< [31..0] Counter/Timer 6 End Compare Register. For MEASURE mode
                                                     indicates the high phase sample count.                                    */
    } TMR6CMP0_b;
  } ;

  union {
    __IOM uint32_t TMR6CMP1;                    /*!< (@ 0x000002CC) This comparator is used as a secondary compare
                                                                    count for modes that generate pulses. For
                                                                    MEASURE mode indicates the low phase sample
                                                                    count.                                                     */

    struct {
      __IOM uint32_t TMR6CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
                                                     a PWM or generate secondary pulses. CMP0 should ALWAYS
                                                     be used first.                                                            */
    } TMR6CMP1_b;
  } ;

  union {
    __IOM uint32_t MODE6;                       /*!< (@ 0x000002D0) The mode register contains optional mode controls
                                                                    for the timer                                              */

    struct {
            uint32_t            : 8;
      __IOM uint32_t TMR6TRIGSEL : 8;           /*!< [15..8] Counter/Timer 6 Trigger Source Selection                          */
            uint32_t            : 16;
    } MODE6_b;
  } ;

  union {
    __IOM uint32_t TMR6LMTVAL;                  /*!< (@ 0x000002D4) This is an internal counter in the hardware that
                                                                    counts down from TMR_LMT to 1                              */

    struct {
      __IOM uint32_t TMR6LMTVAL : 8;            /*!< [7..0] Counter/Timer 6 Limit Readback                                     */
            uint32_t            : 24;
    } TMR6LMTVAL_b;
  } ;
  __IM  uint32_t  RESERVED10[2];

  union {
    __IOM uint32_t CTRL7;                       /*!< (@ 0x000002E0) This includes the Control bit fields for timer
                                                                    7.                                                         */

    struct {
      __IOM uint32_t TMR7EN     : 1;            /*!< [0..0] Counter/Timer 7 Enable bit.                                        */
      __IOM uint32_t TMR7CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
      __IOM uint32_t TMR7POL0   : 1;            /*!< [2..2] Counter/Timer 7 output 0 polarity.                                 */
      __IOM uint32_t TMR7POL1   : 1;            /*!< [3..3] Counter/Timer 7 output 1 polarity.                                 */
      __IOM uint32_t TMR7FN     : 4;            /*!< [7..4] Counter/Timer 7 Function Select. For all Functions, CMP0
                                                     marks the end of timer cycle, and thus restarts the timer.                */
      __IOM uint32_t TMR7CLK    : 8;            /*!< [15..8] Counter/Timer 7 Clock Select.                                     */
      __IOM uint32_t TMR7TMODE  : 2;            /*!< [17..16] Counter/Timer 7 Trigger Mode                                     */
            uint32_t            : 6;
      __IOM uint32_t TMR7LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
                                                     7. For Single/Repeat Patterns, it indicates number of bits
                                                     to be shifted out and so, max value is 63.                                */
    } CTRL7_b;
  } ;

  union {
    __IOM uint32_t TIMER7;                      /*!< (@ 0x000002E4) This register holds the running time or event
                                                                    count for timer 7.                                         */

    struct {
      __IOM uint32_t TIMER7     : 32;           /*!< [31..0] Counter/Timer 7                                                   */
    } TIMER7_b;
  } ;

  union {
    __IOM uint32_t TMR7CMP0;                    /*!< (@ 0x000002E8) This contains the Compare limits for timer 7.
                                                                    This is the primary comparator that can
                                                                    be used to mark the END of a timer cycle
                                                                    (and thus restart the timer for repeat modes)              */

    struct {
      __IOM uint32_t TMR7CMP0   : 32;           /*!< [31..0] Counter/Timer 7 End Compare Register. For MEASURE mode
                                                     indicates the high phase sample count.                                    */
    } TMR7CMP0_b;
  } ;

  union {
    __IOM uint32_t TMR7CMP1;                    /*!< (@ 0x000002EC) This comparator is used as a secondary compare
                                                                    count for modes that generate pulses. For
                                                                    MEASURE mode indicates the low phase sample
                                                                    count.                                                     */

    struct {
      __IOM uint32_t TMR7CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
                                                     a PWM or generate secondary pulses. CMP0 should ALWAYS
                                                     be used first.                                                            */
    } TMR7CMP1_b;
  } ;

  union {
    __IOM uint32_t MODE7;                       /*!< (@ 0x000002F0) The mode register contains optional mode controls
                                                                    for the timer                                              */

    struct {
            uint32_t            : 8;
      __IOM uint32_t TMR7TRIGSEL : 8;           /*!< [15..8] Counter/Timer 7 Trigger Source Selection                          */
            uint32_t            : 16;
    } MODE7_b;
  } ;

  union {
    __IOM uint32_t TMR7LMTVAL;                  /*!< (@ 0x000002F4) This is an internal counter in the hardware that
                                                                    counts down from TMR_LMT to 1                              */

    struct {
      __IOM uint32_t TMR7LMTVAL : 8;            /*!< [7..0] Counter/Timer 7 Limit Readback                                     */
            uint32_t            : 24;
    } TMR7LMTVAL_b;
  } ;
  __IM  uint32_t  RESERVED11[2];

  union {
    __IOM uint32_t CTRL8;                       /*!< (@ 0x00000300) This includes the Control bit fields for timer
                                                                    8.                                                         */

    struct {
      __IOM uint32_t TMR8EN     : 1;            /*!< [0..0] Counter/Timer 8 Enable bit.                                        */
      __IOM uint32_t TMR8CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
      __IOM uint32_t TMR8POL0   : 1;            /*!< [2..2] Counter/Timer 8 output 0 polarity.                                 */
      __IOM uint32_t TMR8POL1   : 1;            /*!< [3..3] Counter/Timer 8 output 1 polarity.                                 */
      __IOM uint32_t TMR8FN     : 4;            /*!< [7..4] Counter/Timer 8 Function Select. For all Functions, CMP0
                                                     marks the end of timer cycle, and thus restarts the timer.                */
      __IOM uint32_t TMR8CLK    : 8;            /*!< [15..8] Counter/Timer 8 Clock Select.                                     */
      __IOM uint32_t TMR8TMODE  : 2;            /*!< [17..16] Counter/Timer 8 Trigger Mode                                     */
            uint32_t            : 6;
      __IOM uint32_t TMR8LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
                                                     8. For Single/Repeat Patterns, it indicates number of bits
                                                     to be shifted out and so, max value is 63.                                */
    } CTRL8_b;
  } ;

  union {
    __IOM uint32_t TIMER8;                      /*!< (@ 0x00000304) This register holds the running time or event
                                                                    count for timer 8.                                         */

    struct {
      __IOM uint32_t TIMER8     : 32;           /*!< [31..0] Counter/Timer 8                                                   */
    } TIMER8_b;
  } ;

  union {
    __IOM uint32_t TMR8CMP0;                    /*!< (@ 0x00000308) This contains the Compare limits for timer 8.
                                                                    This is the primary comparator that can
                                                                    be used to mark the END of a timer cycle
                                                                    (and thus restart the timer for repeat modes)              */

    struct {
      __IOM uint32_t TMR8CMP0   : 32;           /*!< [31..0] Counter/Timer 8 End Compare Register. For MEASURE mode
                                                     indicates the high phase sample count.                                    */
    } TMR8CMP0_b;
  } ;

  union {
    __IOM uint32_t TMR8CMP1;                    /*!< (@ 0x0000030C) This comparator is used as a secondary compare
                                                                    count for modes that generate pulses. For
                                                                    MEASURE mode indicates the low phase sample
                                                                    count.                                                     */

    struct {
      __IOM uint32_t TMR8CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
                                                     a PWM or generate secondary pulses. CMP0 should ALWAYS
                                                     be used first.                                                            */
    } TMR8CMP1_b;
  } ;

  union {
    __IOM uint32_t MODE8;                       /*!< (@ 0x00000310) The mode register contains optional mode controls
                                                                    for the timer                                              */

    struct {
            uint32_t            : 8;
      __IOM uint32_t TMR8TRIGSEL : 8;           /*!< [15..8] Counter/Timer 8 Trigger Source Selection                          */
            uint32_t            : 16;
    } MODE8_b;
  } ;

  union {
    __IOM uint32_t TMR8LMTVAL;                  /*!< (@ 0x00000314) This is an internal counter in the hardware that
                                                                    counts down from TMR_LMT to 1                              */

    struct {
      __IOM uint32_t TMR8LMTVAL : 8;            /*!< [7..0] Counter/Timer 8 Limit Readback                                     */
            uint32_t            : 24;
    } TMR8LMTVAL_b;
  } ;
  __IM  uint32_t  RESERVED12[2];

  union {
    __IOM uint32_t CTRL9;                       /*!< (@ 0x00000320) This includes the Control bit fields for timer
                                                                    9.                                                         */

    struct {
      __IOM uint32_t TMR9EN     : 1;            /*!< [0..0] Counter/Timer 9 Enable bit.                                        */
      __IOM uint32_t TMR9CLR    : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
      __IOM uint32_t TMR9POL0   : 1;            /*!< [2..2] Counter/Timer 9 output 0 polarity.                                 */
      __IOM uint32_t TMR9POL1   : 1;            /*!< [3..3] Counter/Timer 9 output 1 polarity.                                 */
      __IOM uint32_t TMR9FN     : 4;            /*!< [7..4] Counter/Timer 9 Function Select. For all Functions, CMP0
                                                     marks the end of timer cycle, and thus restarts the timer.                */
      __IOM uint32_t TMR9CLK    : 8;            /*!< [15..8] Counter/Timer 9 Clock Select.                                     */
      __IOM uint32_t TMR9TMODE  : 2;            /*!< [17..16] Counter/Timer 9 Trigger Mode                                     */
            uint32_t            : 6;
      __IOM uint32_t TMR9LMT    : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
                                                     9. For Single/Repeat Patterns, it indicates number of bits
                                                     to be shifted out and so, max value is 63.                                */
    } CTRL9_b;
  } ;

  union {
    __IOM uint32_t TIMER9;                      /*!< (@ 0x00000324) This register holds the running time or event
                                                                    count for timer 9.                                         */

    struct {
      __IOM uint32_t TIMER9     : 32;           /*!< [31..0] Counter/Timer 9                                                   */
    } TIMER9_b;
  } ;

  union {
    __IOM uint32_t TMR9CMP0;                    /*!< (@ 0x00000328) This contains the Compare limits for timer 9.
                                                                    This is the primary comparator that can
                                                                    be used to mark the END of a timer cycle
                                                                    (and thus restart the timer for repeat modes)              */

    struct {
      __IOM uint32_t TMR9CMP0   : 32;           /*!< [31..0] Counter/Timer 9 End Compare Register. For MEASURE mode
                                                     indicates the high phase sample count.                                    */
    } TMR9CMP0_b;
  } ;

  union {
    __IOM uint32_t TMR9CMP1;                    /*!< (@ 0x0000032C) This comparator is used as a secondary compare
                                                                    count for modes that generate pulses. For
                                                                    MEASURE mode indicates the low phase sample
                                                                    count.                                                     */

    struct {
      __IOM uint32_t TMR9CMP1   : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
                                                     a PWM or generate secondary pulses. CMP0 should ALWAYS
                                                     be used first.                                                            */
    } TMR9CMP1_b;
  } ;

  union {
    __IOM uint32_t MODE9;                       /*!< (@ 0x00000330) The mode register contains optional mode controls
                                                                    for the timer                                              */

    struct {
            uint32_t            : 8;
      __IOM uint32_t TMR9TRIGSEL : 8;           /*!< [15..8] Counter/Timer 9 Trigger Source Selection                          */
            uint32_t            : 16;
    } MODE9_b;
  } ;

  union {
    __IOM uint32_t TMR9LMTVAL;                  /*!< (@ 0x00000334) This is an internal counter in the hardware that
                                                                    counts down from TMR_LMT to 1                              */

    struct {
      __IOM uint32_t TMR9LMTVAL : 8;            /*!< [7..0] Counter/Timer 9 Limit Readback                                     */
            uint32_t            : 24;
    } TMR9LMTVAL_b;
  } ;
  __IM  uint32_t  RESERVED13[2];

  union {
    __IOM uint32_t CTRL10;                      /*!< (@ 0x00000340) This includes the Control bit fields for timer
                                                                    10.                                                        */

    struct {
      __IOM uint32_t TMR10EN    : 1;            /*!< [0..0] Counter/Timer 10 Enable bit.                                       */
      __IOM uint32_t TMR10CLR   : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
      __IOM uint32_t TMR10POL0  : 1;            /*!< [2..2] Counter/Timer 10 output 0 polarity.                                */
      __IOM uint32_t TMR10POL1  : 1;            /*!< [3..3] Counter/Timer 10 output 1 polarity.                                */
      __IOM uint32_t TMR10FN    : 4;            /*!< [7..4] Counter/Timer 10 Function Select. For all Functions,
                                                     CMP0 marks the end of timer cycle, and thus restarts the
                                                     timer.                                                                    */
      __IOM uint32_t TMR10CLK   : 8;            /*!< [15..8] Counter/Timer 10 Clock Select.                                    */
      __IOM uint32_t TMR10TMODE : 2;            /*!< [17..16] Counter/Timer 10 Trigger Mode                                    */
            uint32_t            : 6;
      __IOM uint32_t TMR10LMT   : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
                                                     10. For Single/Repeat Patterns, it indicates number of
                                                     bits to be shifted out and so, max value is 63.                           */
    } CTRL10_b;
  } ;

  union {
    __IOM uint32_t TIMER10;                     /*!< (@ 0x00000344) This register holds the running time or event
                                                                    count for timer 10.                                        */

    struct {
      __IOM uint32_t TIMER10    : 32;           /*!< [31..0] Counter/Timer 10                                                  */
    } TIMER10_b;
  } ;

  union {
    __IOM uint32_t TMR10CMP0;                   /*!< (@ 0x00000348) This contains the Compare limits for timer 10.
                                                                    This is the primary comparator that can
                                                                    be used to mark the END of a timer cycle
                                                                    (and thus restart the timer for repeat modes)              */

    struct {
      __IOM uint32_t TMR10CMP0  : 32;           /*!< [31..0] Counter/Timer 10 End Compare Register. For MEASURE mode
                                                     indicates the high phase sample count.                                    */
    } TMR10CMP0_b;
  } ;

  union {
    __IOM uint32_t TMR10CMP1;                   /*!< (@ 0x0000034C) This comparator is used as a secondary compare
                                                                    count for modes that generate pulses. For
                                                                    MEASURE mode indicates the low phase sample
                                                                    count.                                                     */

    struct {
      __IOM uint32_t TMR10CMP1  : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
                                                     a PWM or generate secondary pulses. CMP0 should ALWAYS
                                                     be used first.                                                            */
    } TMR10CMP1_b;
  } ;

  union {
    __IOM uint32_t MODE10;                      /*!< (@ 0x00000350) The mode register contains optional mode controls
                                                                    for the timer                                              */

    struct {
            uint32_t            : 8;
      __IOM uint32_t TMR10TRIGSEL : 8;          /*!< [15..8] Counter/Timer 10 Trigger Source Selection                         */
            uint32_t            : 16;
    } MODE10_b;
  } ;

  union {
    __IOM uint32_t TMR10LMTVAL;                 /*!< (@ 0x00000354) This is an internal counter in the hardware that
                                                                    counts down from TMR_LMT to 1                              */

    struct {
      __IOM uint32_t TMR10LMTVAL : 8;           /*!< [7..0] Counter/Timer 10 Limit Readback                                    */
            uint32_t            : 24;
    } TMR10LMTVAL_b;
  } ;
  __IM  uint32_t  RESERVED14[2];

  union {
    __IOM uint32_t CTRL11;                      /*!< (@ 0x00000360) This includes the Control bit fields for timer
                                                                    11.                                                        */

    struct {
      __IOM uint32_t TMR11EN    : 1;            /*!< [0..0] Counter/Timer 11 Enable bit.                                       */
      __IOM uint32_t TMR11CLR   : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
      __IOM uint32_t TMR11POL0  : 1;            /*!< [2..2] Counter/Timer 11 output 0 polarity.                                */
      __IOM uint32_t TMR11POL1  : 1;            /*!< [3..3] Counter/Timer 11 output 1 polarity.                                */
      __IOM uint32_t TMR11FN    : 4;            /*!< [7..4] Counter/Timer 11 Function Select. For all Functions,
                                                     CMP0 marks the end of timer cycle, and thus restarts the
                                                     timer.                                                                    */
      __IOM uint32_t TMR11CLK   : 8;            /*!< [15..8] Counter/Timer 11 Clock Select.                                    */
      __IOM uint32_t TMR11TMODE : 2;            /*!< [17..16] Counter/Timer 11 Trigger Mode                                    */
            uint32_t            : 6;
      __IOM uint32_t TMR11LMT   : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
                                                     11. For Single/Repeat Patterns, it indicates number of
                                                     bits to be shifted out and so, max value is 63.                           */
    } CTRL11_b;
  } ;

  union {
    __IOM uint32_t TIMER11;                     /*!< (@ 0x00000364) This register holds the running time or event
                                                                    count for timer 11.                                        */

    struct {
      __IOM uint32_t TIMER11    : 32;           /*!< [31..0] Counter/Timer 11                                                  */
    } TIMER11_b;
  } ;

  union {
    __IOM uint32_t TMR11CMP0;                   /*!< (@ 0x00000368) This contains the Compare limits for timer 11.
                                                                    This is the primary comparator that can
                                                                    be used to mark the END of a timer cycle
                                                                    (and thus restart the timer for repeat modes)              */

    struct {
      __IOM uint32_t TMR11CMP0  : 32;           /*!< [31..0] Counter/Timer 11 End Compare Register. For MEASURE mode
                                                     indicates the high phase sample count.                                    */
    } TMR11CMP0_b;
  } ;

  union {
    __IOM uint32_t TMR11CMP1;                   /*!< (@ 0x0000036C) This comparator is used as a secondary compare
                                                                    count for modes that generate pulses. For
                                                                    MEASURE mode indicates the low phase sample
                                                                    count.                                                     */

    struct {
      __IOM uint32_t TMR11CMP1  : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
                                                     a PWM or generate secondary pulses. CMP0 should ALWAYS
                                                     be used first.                                                            */
    } TMR11CMP1_b;
  } ;

  union {
    __IOM uint32_t MODE11;                      /*!< (@ 0x00000370) The mode register contains optional mode controls
                                                                    for the timer                                              */

    struct {
            uint32_t            : 8;
      __IOM uint32_t TMR11TRIGSEL : 8;          /*!< [15..8] Counter/Timer 11 Trigger Source Selection                         */
            uint32_t            : 16;
    } MODE11_b;
  } ;

  union {
    __IOM uint32_t TMR11LMTVAL;                 /*!< (@ 0x00000374) This is an internal counter in the hardware that
                                                                    counts down from TMR_LMT to 1                              */

    struct {
      __IOM uint32_t TMR11LMTVAL : 8;           /*!< [7..0] Counter/Timer 11 Limit Readback                                    */
            uint32_t            : 24;
    } TMR11LMTVAL_b;
  } ;
  __IM  uint32_t  RESERVED15[2];

  union {
    __IOM uint32_t CTRL12;                      /*!< (@ 0x00000380) This includes the Control bit fields for timer
                                                                    12.                                                        */

    struct {
      __IOM uint32_t TMR12EN    : 1;            /*!< [0..0] Counter/Timer 12 Enable bit.                                       */
      __IOM uint32_t TMR12CLR   : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
      __IOM uint32_t TMR12POL0  : 1;            /*!< [2..2] Counter/Timer 12 output 0 polarity.                                */
      __IOM uint32_t TMR12POL1  : 1;            /*!< [3..3] Counter/Timer 12 output 1 polarity.                                */
      __IOM uint32_t TMR12FN    : 4;            /*!< [7..4] Counter/Timer 12 Function Select. For all Functions,
                                                     CMP0 marks the end of timer cycle, and thus restarts the
                                                     timer.                                                                    */
      __IOM uint32_t TMR12CLK   : 8;            /*!< [15..8] Counter/Timer 12 Clock Select.                                    */
      __IOM uint32_t TMR12TMODE : 2;            /*!< [17..16] Counter/Timer 12 Trigger Mode                                    */
            uint32_t            : 6;
      __IOM uint32_t TMR12LMT   : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
                                                     12. For Single/Repeat Patterns, it indicates number of
                                                     bits to be shifted out and so, max value is 63.                           */
    } CTRL12_b;
  } ;

  union {
    __IOM uint32_t TIMER12;                     /*!< (@ 0x00000384) This register holds the running time or event
                                                                    count for timer 12.                                        */

    struct {
      __IOM uint32_t TIMER12    : 32;           /*!< [31..0] Counter/Timer 12                                                  */
    } TIMER12_b;
  } ;

  union {
    __IOM uint32_t TMR12CMP0;                   /*!< (@ 0x00000388) This contains the Compare limits for timer 12.
                                                                    This is the primary comparator that can
                                                                    be used to mark the END of a timer cycle
                                                                    (and thus restart the timer for repeat modes)              */

    struct {
      __IOM uint32_t TMR12CMP0  : 32;           /*!< [31..0] Counter/Timer 12 End Compare Register. For MEASURE mode
                                                     indicates the high phase sample count.                                    */
    } TMR12CMP0_b;
  } ;

  union {
    __IOM uint32_t TMR12CMP1;                   /*!< (@ 0x0000038C) This comparator is used as a secondary compare
                                                                    count for modes that generate pulses. For
                                                                    MEASURE mode indicates the low phase sample
                                                                    count.                                                     */

    struct {
      __IOM uint32_t TMR12CMP1  : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
                                                     a PWM or generate secondary pulses. CMP0 should ALWAYS
                                                     be used first.                                                            */
    } TMR12CMP1_b;
  } ;

  union {
    __IOM uint32_t MODE12;                      /*!< (@ 0x00000390) The mode register contains optional mode controls
                                                                    for the timer                                              */

    struct {
            uint32_t            : 8;
      __IOM uint32_t TMR12TRIGSEL : 8;          /*!< [15..8] Counter/Timer 12 Trigger Source Selection                         */
            uint32_t            : 16;
    } MODE12_b;
  } ;

  union {
    __IOM uint32_t TMR12LMTVAL;                 /*!< (@ 0x00000394) This is an internal counter in the hardware that
                                                                    counts down from TMR_LMT to 1                              */

    struct {
      __IOM uint32_t TMR12LMTVAL : 8;           /*!< [7..0] Counter/Timer 12 Limit Readback                                    */
            uint32_t            : 24;
    } TMR12LMTVAL_b;
  } ;
  __IM  uint32_t  RESERVED16[2];

  union {
    __IOM uint32_t CTRL13;                      /*!< (@ 0x000003A0) This includes the Control bit fields for timer
                                                                    13.                                                        */

    struct {
      __IOM uint32_t TMR13EN    : 1;            /*!< [0..0] Counter/Timer 13 Enable bit.                                       */
      __IOM uint32_t TMR13CLR   : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
      __IOM uint32_t TMR13POL0  : 1;            /*!< [2..2] Counter/Timer 13 output 0 polarity.                                */
      __IOM uint32_t TMR13POL1  : 1;            /*!< [3..3] Counter/Timer 13 output 1 polarity.                                */
      __IOM uint32_t TMR13FN    : 4;            /*!< [7..4] Counter/Timer 13 Function Select. For all Functions,
                                                     CMP0 marks the end of timer cycle, and thus restarts the
                                                     timer.                                                                    */
      __IOM uint32_t TMR13CLK   : 8;            /*!< [15..8] Counter/Timer 13 Clock Select.                                    */
      __IOM uint32_t TMR13TMODE : 2;            /*!< [17..16] Counter/Timer 13 Trigger Mode                                    */
            uint32_t            : 6;
      __IOM uint32_t TMR13LMT   : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
                                                     13. For Single/Repeat Patterns, it indicates number of
                                                     bits to be shifted out and so, max value is 63.                           */
    } CTRL13_b;
  } ;

  union {
    __IOM uint32_t TIMER13;                     /*!< (@ 0x000003A4) This register holds the running time or event
                                                                    count for timer 13.                                        */

    struct {
      __IOM uint32_t TIMER13    : 32;           /*!< [31..0] Counter/Timer 13                                                  */
    } TIMER13_b;
  } ;

  union {
    __IOM uint32_t TMR13CMP0;                   /*!< (@ 0x000003A8) This contains the Compare limits for timer 13.
                                                                    This is the primary comparator that can
                                                                    be used to mark the END of a timer cycle
                                                                    (and thus restart the timer for repeat modes)              */

    struct {
      __IOM uint32_t TMR13CMP0  : 32;           /*!< [31..0] Counter/Timer 13 End Compare Register. For MEASURE mode
                                                     indicates the high phase sample count.                                    */
    } TMR13CMP0_b;
  } ;

  union {
    __IOM uint32_t TMR13CMP1;                   /*!< (@ 0x000003AC) This comparator is used as a secondary compare
                                                                    count for modes that generate pulses. For
                                                                    MEASURE mode indicates the low phase sample
                                                                    count.                                                     */

    struct {
      __IOM uint32_t TMR13CMP1  : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
                                                     a PWM or generate secondary pulses. CMP0 should ALWAYS
                                                     be used first.                                                            */
    } TMR13CMP1_b;
  } ;

  union {
    __IOM uint32_t MODE13;                      /*!< (@ 0x000003B0) The mode register contains optional mode controls
                                                                    for the timer                                              */

    struct {
            uint32_t            : 8;
      __IOM uint32_t TMR13TRIGSEL : 8;          /*!< [15..8] Counter/Timer 13 Trigger Source Selection                         */
            uint32_t            : 16;
    } MODE13_b;
  } ;

  union {
    __IOM uint32_t TMR13LMTVAL;                 /*!< (@ 0x000003B4) This is an internal counter in the hardware that
                                                                    counts down from TMR_LMT to 1                              */

    struct {
      __IOM uint32_t TMR13LMTVAL : 8;           /*!< [7..0] Counter/Timer 13 Limit Readback                                    */
            uint32_t            : 24;
    } TMR13LMTVAL_b;
  } ;
  __IM  uint32_t  RESERVED17[2];

  union {
    __IOM uint32_t CTRL14;                      /*!< (@ 0x000003C0) This includes the Control bit fields for timer
                                                                    14.                                                        */

    struct {
      __IOM uint32_t TMR14EN    : 1;            /*!< [0..0] Counter/Timer 14 Enable bit.                                       */
      __IOM uint32_t TMR14CLR   : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
      __IOM uint32_t TMR14POL0  : 1;            /*!< [2..2] Counter/Timer 14 output 0 polarity.                                */
      __IOM uint32_t TMR14POL1  : 1;            /*!< [3..3] Counter/Timer 14 output 1 polarity.                                */
      __IOM uint32_t TMR14FN    : 4;            /*!< [7..4] Counter/Timer 14 Function Select. For all Functions,
                                                     CMP0 marks the end of timer cycle, and thus restarts the
                                                     timer.                                                                    */
      __IOM uint32_t TMR14CLK   : 8;            /*!< [15..8] Counter/Timer 14 Clock Select.                                    */
      __IOM uint32_t TMR14TMODE : 2;            /*!< [17..16] Counter/Timer 14 Trigger Mode                                    */
            uint32_t            : 6;
      __IOM uint32_t TMR14LMT   : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
                                                     14. For Single/Repeat Patterns, it indicates number of
                                                     bits to be shifted out and so, max value is 63.                           */
    } CTRL14_b;
  } ;

  union {
    __IOM uint32_t TIMER14;                     /*!< (@ 0x000003C4) This register holds the running time or event
                                                                    count for timer 14.                                        */

    struct {
      __IOM uint32_t TIMER14    : 32;           /*!< [31..0] Counter/Timer 14                                                  */
    } TIMER14_b;
  } ;

  union {
    __IOM uint32_t TMR14CMP0;                   /*!< (@ 0x000003C8) This contains the Compare limits for timer 14.
                                                                    This is the primary comparator that can
                                                                    be used to mark the END of a timer cycle
                                                                    (and thus restart the timer for repeat modes)              */

    struct {
      __IOM uint32_t TMR14CMP0  : 32;           /*!< [31..0] Counter/Timer 14 End Compare Register. For MEASURE mode
                                                     indicates the high phase sample count.                                    */
    } TMR14CMP0_b;
  } ;

  union {
    __IOM uint32_t TMR14CMP1;                   /*!< (@ 0x000003CC) This comparator is used as a secondary compare
                                                                    count for modes that generate pulses. For
                                                                    MEASURE mode indicates the low phase sample
                                                                    count.                                                     */

    struct {
      __IOM uint32_t TMR14CMP1  : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
                                                     a PWM or generate secondary pulses. CMP0 should ALWAYS
                                                     be used first.                                                            */
    } TMR14CMP1_b;
  } ;

  union {
    __IOM uint32_t MODE14;                      /*!< (@ 0x000003D0) The mode register contains optional mode controls
                                                                    for the timer                                              */

    struct {
            uint32_t            : 8;
      __IOM uint32_t TMR14TRIGSEL : 8;          /*!< [15..8] Counter/Timer 14 Trigger Source Selection                         */
            uint32_t            : 16;
    } MODE14_b;
  } ;

  union {
    __IOM uint32_t TMR14LMTVAL;                 /*!< (@ 0x000003D4) This is an internal counter in the hardware that
                                                                    counts down from TMR_LMT to 1                              */

    struct {
      __IOM uint32_t TMR14LMTVAL : 8;           /*!< [7..0] Counter/Timer 14 Limit Readback                                    */
            uint32_t            : 24;
    } TMR14LMTVAL_b;
  } ;
  __IM  uint32_t  RESERVED18[2];

  union {
    __IOM uint32_t CTRL15;                      /*!< (@ 0x000003E0) This includes the Control bit fields for timer
                                                                    15.                                                        */

    struct {
      __IOM uint32_t TMR15EN    : 1;            /*!< [0..0] Counter/Timer 15 Enable bit.                                       */
      __IOM uint32_t TMR15CLR   : 1;            /*!< [1..1] Counter/Timer Clear bit.                                           */
      __IOM uint32_t TMR15POL0  : 1;            /*!< [2..2] Counter/Timer 15 output 0 polarity.                                */
      __IOM uint32_t TMR15POL1  : 1;            /*!< [3..3] Counter/Timer 15 output 1 polarity.                                */
      __IOM uint32_t TMR15FN    : 4;            /*!< [7..4] Counter/Timer 15 Function Select. For all Functions,
                                                     CMP0 marks the end of timer cycle, and thus restarts the
                                                     timer.                                                                    */
      __IOM uint32_t TMR15CLK   : 8;            /*!< [15..8] Counter/Timer 15 Clock Select.                                    */
      __IOM uint32_t TMR15TMODE : 2;            /*!< [17..16] Counter/Timer 15 Trigger Mode                                    */
            uint32_t            : 6;
      __IOM uint32_t TMR15LMT   : 8;            /*!< [31..24] This field decides the number of iterations of Counter/Timer
                                                     15. For Single/Repeat Patterns, it indicates number of
                                                     bits to be shifted out and so, max value is 63.                           */
    } CTRL15_b;
  } ;

  union {
    __IOM uint32_t TIMER15;                     /*!< (@ 0x000003E4) This register holds the running time or event
                                                                    count for timer 15.                                        */

    struct {
      __IOM uint32_t TIMER15    : 32;           /*!< [31..0] Counter/Timer 15                                                  */
    } TIMER15_b;
  } ;

  union {
    __IOM uint32_t TMR15CMP0;                   /*!< (@ 0x000003E8) This contains the Compare limits for timer 15.
                                                                    This is the primary comparator that can
                                                                    be used to mark the END of a timer cycle
                                                                    (and thus restart the timer for repeat modes)              */

    struct {
      __IOM uint32_t TMR15CMP0  : 32;           /*!< [31..0] Counter/Timer 15 End Compare Register. For MEASURE mode
                                                     indicates the high phase sample count.                                    */
    } TMR15CMP0_b;
  } ;

  union {
    __IOM uint32_t TMR15CMP1;                   /*!< (@ 0x000003EC) This comparator is used as a secondary compare
                                                                    count for modes that generate pulses. For
                                                                    MEASURE mode indicates the low phase sample
                                                                    count.                                                     */

    struct {
      __IOM uint32_t TMR15CMP1  : 32;           /*!< [31..0] Holds the secondary comparator that can be used to generate
                                                     a PWM or generate secondary pulses. CMP0 should ALWAYS
                                                     be used first.                                                            */
    } TMR15CMP1_b;
  } ;

  union {
    __IOM uint32_t MODE15;                      /*!< (@ 0x000003F0) The mode register contains optional mode controls
                                                                    for the timer                                              */

    struct {
            uint32_t            : 8;
      __IOM uint32_t TMR15TRIGSEL : 8;          /*!< [15..8] Counter/Timer 15 Trigger Source Selection                         */
            uint32_t            : 16;
    } MODE15_b;
  } ;

  union {
    __IOM uint32_t TMR15LMTVAL;                 /*!< (@ 0x000003F4) This is an internal counter in the hardware that
                                                                    counts down from TMR_LMT to 1                              */

    struct {
      __IOM uint32_t TMR15LMTVAL : 8;           /*!< [7..0] Counter/Timer 15 Limit Readback                                    */
            uint32_t            : 24;
    } TMR15LMTVAL_b;
  } ;

  union {
    __IOM uint32_t TIMERSPARES;                 /*!< (@ 0x000003F8) Timer Spare Regs                                           */

    struct {
      __IOM uint32_t TMRSPARES  : 32;           /*!< [31..0] Placeholer spare registes that can be used as needed
                                                     for future use                                                            */
    } TIMERSPARES_b;
  } ;
} TIMER_Type;                                   /*!< Size = 1020 (0x3fc)                                                       */



/* =========================================================================================================================== */
/* ================                                           UART0                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Serial UART (UART0)
  */

typedef struct {                                /*!< (@ 0x4001C000) UART0 Structure                                            */

  union {
    __IOM uint32_t DR;                          /*!< (@ 0x00000000) UART Data                                                  */

    struct {
      __IOM uint32_t DATA       : 8;            /*!< [7..0] Receive (read) data character. Transmit (write) data
                                                     character.                                                                */
      __IOM uint32_t FEDATA     : 1;            /*!< [8..8] Framing error. When set to 1, it indicates that the received
                                                     character did not have a valid stop bit (a valid stop bit
                                                     is 1). In FIFO mode, this error is associated with the
                                                     character at the top of the FIFO.                                         */
      __IOM uint32_t PEDATA     : 1;            /*!< [9..9] Parity error. When set to 1, it indicates that the parity
                                                     of the received data character does not match the parity
                                                     that the EPS and SPS bits in the Line Control Register,
                                                     UARTLCRH select. In FIFO mode, this error is associated
                                                     with the character at the top of the FIFO.                                */
      __IOM uint32_t BEDATA     : 1;            /*!< [10..10] Break error. This bit is set to 1 if a break condition
                                                     was detected, indicating that the received data input was
                                                     held LOW for longer than a full-word transmission time
                                                     (defined as start, data, parity and stop bits). In FIFO
                                                     mode, this error is associated with the character at the
                                                     top of the FIFO. When a break occurs, only one 0 character
                                                     is loaded into the FIFO. The next character is only enabled
                                                     after the receive data input goes to a 1 (marking state),
                                                     and the next valid start bit is received.                                 */
      __IOM uint32_t OEDATA     : 1;            /*!< [11..11] Overrun error. This bit is set to 1 if data is received
                                                     and the receive FIFO is already full. This is cleared to
                                                     0 once there is an empty space in the FIFO and a new character
                                                     can be written to it.                                                     */
            uint32_t            : 20;
    } DR_b;
  } ;

  union {
    __IOM uint32_t RSR;                         /*!< (@ 0x00000004) UART Status                                                */

    struct {
      __IOM uint32_t FESTAT     : 1;            /*!< [0..0] Framing error. When set to 1, it indicates that the received
                                                     character did not have a valid stop bit (a valid stop bit
                                                     is 1). This bit is cleared to 0 by a write to UARTECR.
                                                     In FIFO mode, this error is associated with the character
                                                     at the top of the FIFO.                                                   */
      __IOM uint32_t PESTAT     : 1;            /*!< [1..1] Parity error. When set to 1, it indicates that the parity
                                                     of the received data character does not match the parity
                                                     that the EPS and SPS bits in the Line Control Register,
                                                     UARTLCRH select. This bit is cleared to 0 by a write to
                                                     UARTECR. In FIFO mode, this error is associated with the
                                                     character at the top of the FIFO.                                         */
      __IOM uint32_t BESTAT     : 1;            /*!< [2..2] Break error. This bit is set to 1 if a break condition
                                                     was detected, indicating that the received data input was
                                                     held LOW for longer than a full-word transmission time
                                                     (defined as start, data, parity, and stop bits). This bit
                                                     is cleared to 0 after a write to UARTECR. In FIFO mode,
                                                     this error is associated with the character at the top
                                                     of the FIFO. When a break occurs, only one 0 character
                                                     is loaded into the FIFO. The next character is only enabled
                                                     after the receive data input goes to a 1 (marking state)
                                                     an                                                                        */
      __IOM uint32_t OESTAT     : 1;            /*!< [3..3] Overrun error. This bit is set to 1 if data is received
                                                     and the FIFO is already full. This bit is cleared to 0
                                                     by a write to UARTECR. The FIFO contents remain valid because
                                                     no more data is written when the FIFO is full, only the
                                                     contents of the shift register are overwritten. The CPU
                                                     must now read the data, to empty the FIFO.                                */
            uint32_t            : 28;
    } RSR_b;
  } ;
  __IM  uint32_t  RESERVED[4];

  union {
    __IOM uint32_t FR;                          /*!< (@ 0x00000018) Flags                                                      */

    struct {
      __IOM uint32_t CTS        : 1;            /*!< [0..0] Clear to send. This bit is the complement of the UART
                                                     clear to send, nUARTCTS, modem status input. That is, the
                                                     bit is 1 when nUARTCTS is LOW.                                            */
      __IOM uint32_t DSR        : 1;            /*!< [1..1] Data set ready. This bit is the complement of the UART
                                                     data set ready, nUARTDSR, modem status input. That is,
                                                     the bit is 1 when nUARTDSR is LOW.                                        */
      __IOM uint32_t DCD        : 1;            /*!< [2..2] Data carrier detect. This bit is the complement of the
                                                     UART data carrier detect, nUARTDCD, modem status input.
                                                     That is, the bit is 1 when nUARTDCD is LOW.                               */
      __IOM uint32_t BUSY       : 1;            /*!< [3..3] UART busy. If this bit is set to 1, the UART is busy
                                                     transmitting data. This bit remains set until the complete
                                                     byte, including all the stop bits, has been sent from the
                                                     shift register. This bit is set as soon as the transmit
                                                     FIFO becomes non-empty, regardless of whether the UART
                                                     is enabled or not.                                                        */
      __IOM uint32_t RXFE       : 1;            /*!< [4..4] Receive FIFO empty. The meaning of this bit depends on
                                                     the state of the FEN bit in the UARTLCRH Register. If the
                                                     FIFO is disabled, this bit is set when the receive holding
                                                     register is empty. If the FIFO is enabled, the RXFE bit
                                                     is set when the receive FIFO is empty.                                    */
      __IOM uint32_t TXFF       : 1;            /*!< [5..5] Transmit FIFO full. The meaning of this bit depends on
                                                     the state of the FEN bit in the UARTLCRH Register. If the
                                                     FIFO is disabled, this bit is set when the transmit holding
                                                     register is full. If the FIFO is enabled, the TXFF bit
                                                     is set when the transmit FIFO is full.                                    */
      __IOM uint32_t RXFF       : 1;            /*!< [6..6] Receive FIFO full. The meaning of this bit depends on
                                                     the state of the FEN bit in the UARTLCRH Register. If the
                                                     FIFO is disabled, this bit is set when the receive holding
                                                     register is full. If the FIFO is enabled, the RXFF bit
                                                     is set when the receive FIFO is full.                                     */
      __IOM uint32_t TXFE       : 1;            /*!< [7..7] Transmit FIFO empty. The meaning of this bit depends
                                                     on the state of the FEN bit in the Line Control Register,
                                                     UARTLCRH. If the FIFO is disabled, this bit is set when
                                                     the transmit holding register is empty. If the FIFO is
                                                     enabled, the TXFE bit is set when the transmit FIFO is
                                                     empty. This bit does not indicate if there is data in the
                                                     transmit shift register.                                                  */
      __IOM uint32_t TXBUSY     : 1;            /*!< [8..8] This bit holds the transmit BUSY indicator.                        */
            uint32_t            : 23;
    } FR_b;
  } ;
  __IM  uint32_t  RESERVED1;

  union {
    __IOM uint32_t ILPR;                        /*!< (@ 0x00000020) IrDA Counter                                               */

    struct {
      __IOM uint32_t ILPDVSR    : 8;            /*!< [7..0] 8-bit low-power divisor value. These bits are cleared
                                                     to 0 at reset. Programming a zero value results in no IrLPBaud16
                                                     pulses being generated.                                                   */
            uint32_t            : 24;
    } ILPR_b;
  } ;

  union {
    __IOM uint32_t IBRD;                        /*!< (@ 0x00000024) Integer Baud Rate Divisor                                  */

    struct {
      __IOM uint32_t DIVINT     : 16;           /*!< [15..0] This field holds the integer baud rate divisor. It is
                                                     set in conjunction with the DIVFRAC field in the FBRD register
                                                     and the clock rate as set in the CLKSEL field of the CR
                                                     register. The field should be set to the integer part of
                                                     the ratio: Clock Rate / (16 x intended baud rate).                        */
            uint32_t            : 16;
    } IBRD_b;
  } ;

  union {
    __IOM uint32_t FBRD;                        /*!< (@ 0x00000028) Fractional Baud Rate Divisor                               */

    struct {
      __IOM uint32_t DIVFRAC    : 6;            /*!< [5..0] This field holds the fractional baud rate divisor. It
                                                     is set in conjunction with the DIVINT field in the IBRD
                                                     register and the clock rate as set in the CLKSEL field
                                                     of the CR register. The field should be set to the rounded
                                                     value of 64 x the fractional part of the ratio: Clock Rate
                                                     / (16 x intended baud rate).                                              */
            uint32_t            : 26;
    } FBRD_b;
  } ;

  union {
    __IOM uint32_t LCRH;                        /*!< (@ 0x0000002C) Line Control High                                          */

    struct {
      __IOM uint32_t BRK        : 1;            /*!< [0..0] This bit holds the break set. If this bit is set to 1,
                                                     a low-level is continually output on the UARTTXD output,
                                                     after completing transmission of the current character.
                                                     For the proper execution of the break command, the software
                                                     must set this bit for at least two complete frames. For
                                                     normal use, this bit must be cleared to 0.                                */
      __IOM uint32_t PEN        : 1;            /*!< [1..1] This bit holds the parity enable. 0 = parity is disabled
                                                     and no parity bit added to the data frame. 1 = parity checking
                                                     and generation is enabled.                                                */
      __IOM uint32_t EPS        : 1;            /*!< [2..2] This bit holds the even parity select. Controls the type
                                                     of parity the UART uses during transmission and reception:
                                                     0 = odd parity. The UART generates or checks for an odd
                                                     number of 1s in the data and parity bits. 1 = even parity.
                                                     The UART generates or checks for an even number of 1s in
                                                     the data and parity bits. This bit has no effect when the
                                                     PEN bit disables parity checking and generation.                          */
      __IOM uint32_t STP2       : 1;            /*!< [3..3] This bit holds the two stop bits select. If this bit
                                                     is set to 1, two stop bits are transmitted at the end of
                                                     the frame. The receive logic does not check for two stop
                                                     bits being received.                                                      */
      __IOM uint32_t FEN        : 1;            /*!< [4..4] This bit holds the FIFO enable. 0 = FIFOs are disabled
                                                     (character mode) that is, the FIFOs become 1-byte-deep
                                                     holding registers. 1 = transmit and receive FIFO buffers
                                                     are enabled (FIFO mode).                                                  */
      __IOM uint32_t WLEN       : 2;            /*!< [6..5] These bits hold the write length. These bits indicate
                                                     the number of data bits transmitted or received in a frame
                                                     as follows: b11 = 8 bits, b10 = 7 bits, b01 = 6 bits, b00
                                                     = 5 bits.                                                                 */
      __IOM uint32_t SPS        : 1;            /*!< [7..7] This bit holds the stick parity select. If the EPS bit
                                                     is 0 then the parity bit is transmitted and checked as
                                                     a 1. If the EPS bit is 1 then the parity bit is transmitted
                                                     and checked as a 0. This bit has no effect when the PEN
                                                     bit disables parity checking and generation.                              */
            uint32_t            : 24;
    } LCRH_b;
  } ;

  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000030) Control                                                    */

    struct {
      __IOM uint32_t UARTEN     : 1;            /*!< [0..0] This bit is the UART enable. 0 = UART is disabled. If
                                                     the UART is disabled in the middle of transmission or reception,
                                                     it completes the current character before stopping. 1 =
                                                     the UART is enabled. Data transmission and reception occurs
                                                     for either UART signals or SIR signals depending on the
                                                     setting of the SIREN bit.                                                 */
      __IOM uint32_t SIREN      : 1;            /*!< [1..1] This bit is the SIR ENDEC enable. If this bit is set
                                                     to 1, the IrDA SIR ENDEC is enabled. This bit has no effect
                                                     if the UART is not enabled by bit 0 being set to 1. When
                                                     the IrDA SIR ENDEC is enabled, data is transmitted and
                                                     received on nSIROUT and SIRIN. UARTTXD remains in the marking
                                                     state (set to 1). Signal transitions on UARTRXD or modem
                                                     status inputs have no effect. When the IrDA SIR ENDEC is
                                                     disabled, nSIROUT remains cleared to 0 (no light pulse
                                                     generated), and signal transitions on SIRIN have no eff                   */
      __IOM uint32_t SIRLP      : 1;            /*!< [2..2] This bit is the SIR low power select. This bit selects
                                                     the IrDA encoding mode. If this bit is cleared to 0, low-level
                                                     bits are transmitted as an active high pulse with a width
                                                     of 3/16th of the bit period. If this bit is set to 1, low-level
                                                     bits are transmitted with a pulse width which is 3 times
                                                     the period of the IrLPBaud16 input signal, regardless of
                                                     the selected bit rate. Setting this bit uses less power,
                                                     but might reduce transmission distances.                                  */
      __IOM uint32_t CLKEN      : 1;            /*!< [3..3] This bit is the UART clock enable.                                 */
      __IOM uint32_t CLKSEL     : 3;            /*!< [6..4] This bitfield is the UART clock select.                            */
      __IOM uint32_t LBE        : 1;            /*!< [7..7] This bit is the loopback enable. If this bit is set to
                                                     1 and the SIREN bit is set to 1 and the SIRTEST bit in
                                                     the Test Control Register, UARTTCR is set to 1, then the
                                                     nSIROUT path is inverted, and fed through to the SIRIN
                                                     path. The SIRTEST bit in the test register must be set
                                                     to 1 to override the normal half-duplex SIR operation.
                                                     This must be the requirement for accessing the test registers
                                                     during normal operation, and SIRTEST must be cleared to
                                                     0 when loopback testing is finished. This feature reduces
                                                     the                                                                       */
      __IOM uint32_t TXE        : 1;            /*!< [8..8] This bit is the transmit enable. If this bit is set to
                                                     1, the transmit section of the UART is enabled. Data transmission
                                                     occurs for either UART signals, or SIR signals depending
                                                     on the setting of the SIREN bit. When the UART is disabled
                                                     in the middle of transmission, it completes the current
                                                     character before stopping.                                                */
      __IOM uint32_t RXE        : 1;            /*!< [9..9] This bit is the receive enable. If this bit is set to
                                                     1, the receive section of the UART is enabled. Data reception
                                                     occurs for either UART signals or SIR signals depending
                                                     on the setting of the SIREN bit. When the UART is disabled
                                                     in the middle of reception, it completes the current character
                                                     before stopping.                                                          */
      __IOM uint32_t DTR        : 1;            /*!< [10..10] This bit enables data transmit ready. This bit is the
                                                     complement of the UART data transmit ready, nUARTDTR, modem
                                                     status output. That is, when the bit is programmed to a
                                                     1 then nUARTDTR is LOW.                                                   */
      __IOM uint32_t RTS        : 1;            /*!< [11..11] This bit enables request to send. This bit is the complement
                                                     of the UART request to send, nUARTRTS, modem status output.
                                                     That is, when the bit is programmed to a 1 then nUARTRTS
                                                     is LOW.                                                                   */
      __IOM uint32_t OUT1       : 1;            /*!< [12..12] This bit is the complement of the UART Out1 (nUARTOut1)
                                                     modem status output. That is, when the bit is programmed
                                                     to a 1 the output is 0. For DTE this can be used as Data
                                                     Carrier Detect (DCD).                                                     */
      __IOM uint32_t OUT2       : 1;            /*!< [13..13] This bit is the complement of the UART Out2 (nUARTOut2)
                                                     modem status output. That is, when the bit is programmed
                                                     to a 1, the output is 0. For DTE this can be used as Ring
                                                     Indicator (RI).                                                           */
      __IOM uint32_t RTSEN      : 1;            /*!< [14..14] This bit enables RTS hardware flow control. If this
                                                     bit is set to 1, RTS hardware flow control is enabled.
                                                     Data is only requested when there is space in the receive
                                                     FIFO for it to be received.                                               */
      __IOM uint32_t CTSEN      : 1;            /*!< [15..15] This bit enables CTS hardware flow control. If this
                                                     bit is set to 1, CTS hardware flow control is enabled.
                                                     Data is only transmitted when the nUARTCTS signal is asserted.            */
            uint32_t            : 16;
    } CR_b;
  } ;

  union {
    __IOM uint32_t IFLS;                        /*!< (@ 0x00000034) FIFO Interrupt Level Select                                */

    struct {
      __IOM uint32_t TXIFLSEL   : 3;            /*!< [2..0] These bits hold the transmit FIFO interrupt level.                 */
      __IOM uint32_t RXIFLSEL   : 3;            /*!< [5..3] These bits hold the receive FIFO interrupt level.                  */
            uint32_t            : 26;
    } IFLS_b;
  } ;

  union {
    __IOM uint32_t IER;                         /*!< (@ 0x00000038) Interrupt Enable                                           */

    struct {
      __IOM uint32_t TXCMPMIM   : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt enable.                   */
      __IOM uint32_t CTSMIM     : 1;            /*!< [1..1] This bit holds the modem CTS interrupt enable.                     */
      __IOM uint32_t DCDMIM     : 1;            /*!< [2..2] This bit holds the modem DCD interrupt enable.                     */
      __IOM uint32_t DSRMIM     : 1;            /*!< [3..3] This bit holds the modem DSR interrupt enable.                     */
      __IOM uint32_t RXIM       : 1;            /*!< [4..4] This bit holds the receive interrupt enable.                       */
      __IOM uint32_t TXIM       : 1;            /*!< [5..5] This bit holds the transmit interrupt enable.                      */
      __IOM uint32_t RTIM       : 1;            /*!< [6..6] This bit holds the receive timeout interrupt enable.               */
      __IOM uint32_t FEIM       : 1;            /*!< [7..7] This bit holds the framing error interrupt enable.                 */
      __IOM uint32_t PEIM       : 1;            /*!< [8..8] This bit holds the parity error interrupt enable.                  */
      __IOM uint32_t BEIM       : 1;            /*!< [9..9] This bit holds the break error interrupt enable.                   */
      __IOM uint32_t OEIM       : 1;            /*!< [10..10] This bit holds the overflow interrupt enable.                    */
            uint32_t            : 21;
    } IER_b;
  } ;

  union {
    __IOM uint32_t IES;                         /*!< (@ 0x0000003C) Interrupt Status                                           */

    struct {
      __IOM uint32_t TXCMPMRIS  : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt status.                   */
      __IOM uint32_t CTSMRIS    : 1;            /*!< [1..1] This bit holds the nUARTCTS modem interrupt status. Returns
                                                     the raw interrupt state of the UARTCTSINTR interrupt.                     */
      __IOM uint32_t DCDMRIS    : 1;            /*!< [2..2] This bit holds the nUARTDCD modem interrupt status. Returns
                                                     the raw interrupt state of the UARTDCDINTR interrupt.                     */
      __IOM uint32_t DSRMRIS    : 1;            /*!< [3..3] This bit holds the nUARTDSR modem interrupt status. Returns
                                                     the raw interrupt state of the UARTDSRINTR interrupt.                     */
      __IOM uint32_t RXRIS      : 1;            /*!< [4..4] This bit holds the receive interrupt status. Returns
                                                     the raw interrupt state of the UARTRXINTR interrupt.                      */
      __IOM uint32_t TXRIS      : 1;            /*!< [5..5] This bit holds the transmit interrupt status. Returns
                                                     the raw interrupt state of the UARTTXINTR interrupt.                      */
      __IOM uint32_t RTRIS      : 1;            /*!< [6..6] This bit holds the receive timeout interrupt status.
                                                     Returns the raw interrupt state of the UARTRTINTR interrupt.              */
      __IOM uint32_t FERIS      : 1;            /*!< [7..7] This bit holds the framing error interrupt status. Returns
                                                     the raw interrupt state of the UARTFEINTR interrupt.                      */
      __IOM uint32_t PERIS      : 1;            /*!< [8..8] This bit holds the parity error interrupt status. Returns
                                                     the raw interrupt state of the UARTPEINTR interrupt.                      */
      __IOM uint32_t BERIS      : 1;            /*!< [9..9] This bit holds the break error interrupt status. Returns
                                                     the raw interrupt state of the UARTBEINTR interrupt.                      */
      __IOM uint32_t OERIS      : 1;            /*!< [10..10] This bit holds the overrun interrupt status. Returns
                                                     the raw interrupt state of the UARTOEINTR interrupt.                      */
            uint32_t            : 21;
    } IES_b;
  } ;

  union {
    __IOM uint32_t MIS;                         /*!< (@ 0x00000040) Masked Interrupt Status                                    */

    struct {
      __IOM uint32_t TXCMPMMIS  : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt status masked.            */
      __IOM uint32_t CTSMMIS    : 1;            /*!< [1..1] This bit holds the nUARTCTS modem masked interrupt status.
                                                     Returns the masked interrupt state of the UARTCTSINTR interrupt.          */
      __IOM uint32_t DCDMMIS    : 1;            /*!< [2..2] This bit holds the nUARTDCD modem masked interrupt status.
                                                     Returns the masked interrupt state of the UARTDCDINTR interrupt.          */
      __IOM uint32_t DSRMMIS    : 1;            /*!< [3..3] This bit holds the nUARTDSR modem masked interrupt status.
                                                     Returns the masked interrupt state of the UARTDSRINTR interrupt.          */
      __IOM uint32_t RXMIS      : 1;            /*!< [4..4] This bit holds the receive interrupt status masked. Returns
                                                     the masked interrupt state of the UARTRXINTR interrupt.                   */
      __IOM uint32_t TXMIS      : 1;            /*!< [5..5] This bit holds the transmit interrupt status masked.
                                                     Returns the masked interrupt state of the UARTTXINTR interrupt.           */
      __IOM uint32_t RTMIS      : 1;            /*!< [6..6] This bit holds the receive timeout interrupt status masked.
                                                     Returns the masked interrupt state of the UARTRTINTR interrupt.           */
      __IOM uint32_t FEMIS      : 1;            /*!< [7..7] This bit holds the framing error interrupt status masked.
                                                     Returns the masked interrupt state of the UARTFEINTR interrupt.           */
      __IOM uint32_t PEMIS      : 1;            /*!< [8..8] This bit holds the parity error interrupt status masked.
                                                     Returns the masked interrupt state of the UARTPEINTR interrupt.           */
      __IOM uint32_t BEMIS      : 1;            /*!< [9..9] This bit holds the break error interrupt status masked.
                                                     Returns the masked interrupt state of the UARTBEINTR interrupt.           */
      __IOM uint32_t OEMIS      : 1;            /*!< [10..10] This bit holds the overrun interrupt status masked.
                                                     Returns the masked interrupt state of the UARTOEINTR interrupt.           */
            uint32_t            : 21;
    } MIS_b;
  } ;

  union {
    __IOM uint32_t IEC;                         /*!< (@ 0x00000044) Interrupt Clear                                            */

    struct {
      __IOM uint32_t TXCMPMIC   : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt clear.                    */
      __IOM uint32_t CTSMIC     : 1;            /*!< [1..1] This bit holds the nUARTCTS modem interrupt clear. Clears
                                                     the UARTCTSINTR interrupt.                                                */
      __IOM uint32_t DCDMIC     : 1;            /*!< [2..2] This bit holds the nUARTDCD modem interrupt clear. Clears
                                                     the UARTDCDINTR interrupt.                                                */
      __IOM uint32_t DSRMIC     : 1;            /*!< [3..3] This bit holds the nUARTDSR modem interrupt clear. Clears
                                                     the UARTDSRINTR interrupt.                                                */
      __IOM uint32_t RXIC       : 1;            /*!< [4..4] This bit holds the receive interrupt clear. Clears the
                                                     UARTRXINTR interrupt.                                                     */
      __IOM uint32_t TXIC       : 1;            /*!< [5..5] This bit holds the transmit interrupt clear. Clears the
                                                     UARTTXINTR interrupt.                                                     */
      __IOM uint32_t RTIC       : 1;            /*!< [6..6] This bit holds the receive timeout interrupt clear. Clears
                                                     the UARTRTINTR interrupt.                                                 */
      __IOM uint32_t FEIC       : 1;            /*!< [7..7] This bit holds the framing error interrupt clear. Clears
                                                     the UARTFEINTR interrupt.                                                 */
      __IOM uint32_t PEIC       : 1;            /*!< [8..8] This bit holds the parity error interrupt clear. Clears
                                                     the UARTPEINTR interrupt.                                                 */
      __IOM uint32_t BEIC       : 1;            /*!< [9..9] This bit holds the break error interrupt clear. Clears
                                                     the UARTBEINTR interrupt.                                                 */
      __IOM uint32_t OEIC       : 1;            /*!< [10..10] This bit holds the overrun interrupt clear. Clears
                                                     the UARTOEINTR interrupt.                                                 */
            uint32_t            : 21;
    } IEC_b;
  } ;
} UART0_Type;                                   /*!< Size = 72 (0x48)                                                          */



/* =========================================================================================================================== */
/* ================                                           VCOMP                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Voltage Comparator (VCOMP)
  */

typedef struct {                                /*!< (@ 0x4000C000) VCOMP Structure                                            */

  union {
    __IOM uint32_t CFG;                         /*!< (@ 0x00000000) The Voltage Comparator Configuration Register
                                                                    contains the software control for selecting
                                                                    beween the 4 options for the positive input
                                                                    as well as the multiple options for the
                                                                    reference input.                                           */

    struct {
      __IOM uint32_t PSEL       : 2;            /*!< [1..0] This bitfield selects the positive input to the comparator.        */
            uint32_t            : 6;
      __IOM uint32_t NSEL       : 2;            /*!< [9..8] This bitfield selects the negative input to the comparator.        */
            uint32_t            : 6;
      __IOM uint32_t LVLSEL     : 4;            /*!< [19..16] When the reference input NSEL is set to NSEL_DAC, this
                                                     bitfield selects the voltage level for the negative input
                                                     to the comparator.                                                        */
            uint32_t            : 12;
    } CFG_b;
  } ;

  union {
    __IOM uint32_t STAT;                        /*!< (@ 0x00000004) Status                                                     */

    struct {
      __IOM uint32_t CMPOUT     : 1;            /*!< [0..0] This bit is 1 if the positive input of the comparator
                                                     is greater than the negative input.                                       */
      __IOM uint32_t PWDSTAT    : 1;            /*!< [1..1] This bit indicates the power down state of the voltage
                                                     comparator.                                                               */
            uint32_t            : 30;
    } STAT_b;
  } ;

  union {
    __IOM uint32_t PWDKEY;                      /*!< (@ 0x00000008) Write a value of 0x37 to unlock, write any other
                                                                    value to lock. This register also indicates
                                                                    lock status when read. When in the unlccked
                                                                    state (i.e. 0x37 has been written), it reads
                                                                    as 1. When in the locked state, it reads
                                                                    as 0.                                                      */

    struct {
      __IOM uint32_t PWDKEY     : 32;           /*!< [31..0] Key register value.                                               */
    } PWDKEY_b;
  } ;
  __IM  uint32_t  RESERVED[125];

  union {
    __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
      __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
            uint32_t            : 30;
    } INTEN_b;
  } ;

  union {
    __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
      __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
            uint32_t            : 30;
    } INTSTAT_b;
  } ;

  union {
    __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
      __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
            uint32_t            : 30;
    } INTCLR_b;
  } ;

  union {
    __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
      __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
            uint32_t            : 30;
    } INTSET_b;
  } ;
} VCOMP_Type;                                   /*!< Size = 528 (0x210)                                                        */



/* =========================================================================================================================== */
/* ================                                            WDT                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Watchdog Timer (WDT)
  */

typedef struct {                                /*!< (@ 0x40024000) WDT Structure                                              */

  union {
    __IOM uint32_t CFG;                         /*!< (@ 0x00000000) This is the configuration register for the watch
                                                                    dog timer. It controls the enable, interrupt
                                                                    set, clocks for the timer, the compare values
                                                                    for the counters to trigger a reset or interrupt.
                                                                    This register can only be written to if
                                                                    the watch dog timer is unlocked (WDTLOCK
                                                                    is not set).                                               */

    struct {
      __IOM uint32_t WDTEN      : 1;            /*!< [0..0] This bitfield enables the WDT.                                     */
      __IOM uint32_t INTEN      : 1;            /*!< [1..1] This bitfield enables the WDT interrupt. Note : This
                                                     bit must be set before the interrupt status bit will reflect
                                                     a watchdog timer expiration. The IER interrupt register
                                                     must also be enabled for a WDT interrupt to be sent to
                                                     the NVIC.                                                                 */
      __IOM uint32_t RESEN      : 1;            /*!< [2..2] This bitfield enables the WDT reset. This needs to be
                                                     set together with the WDREN bit in REG_RSTGEN_CFG register
                                                     (in reset gen) to trigger the reset.                                      */
            uint32_t            : 5;
      __IOM uint32_t RESVAL     : 8;            /*!< [15..8] This bitfield is the compare value for counter bits
                                                     7:0 to generate a watchdog reset. This will cause a software
                                                     reset.                                                                    */
      __IOM uint32_t INTVAL     : 8;            /*!< [23..16] This bitfield is the compare value for counter bits
                                                     7:0 to generate a watchdog interrupt.                                     */
      __IOM uint32_t CLKSEL     : 3;            /*!< [26..24] Select the frequency for the WDT. All values not enumerated
                                                     below are undefined.                                                      */
            uint32_t            : 5;
    } CFG_b;
  } ;

  union {
    __IOM uint32_t RSTRT;                       /*!< (@ 0x00000004) This register will Restart the watchdog timer.
                                                                    Writing a special key value into this register
                                                                    will result in the watch dog timer being
                                                                    reset, so that the count will start again.
                                                                    It is expected that the software will periodically
                                                                    write to this register to indicate that
                                                                    the system is functional. The watch dog
                                                                    timer can continue running when the system
                                                                    is in deep sleep, and the interrupt will
                                                                    trigger the wake. After the wake, the core
                                                                    can reset the watch dog timer.                             */

    struct {
      __IOM uint32_t RSTRT      : 8;            /*!< [7..0] Writing 0xB2 to WDTRSTRT restarts the watchdog timer.
                                                     This is a write only register. Reading this register will
                                                     only provide all 0.                                                       */
            uint32_t            : 24;
    } RSTRT_b;
  } ;

  union {
    __IOM uint32_t LOCK;                        /*!< (@ 0x00000008) This register locks the watch dog timer. Once
                                                                    it is locked, the configuration register
                                                                    (WDTCFG) for watch dog timer cannot be written
                                                                    to.                                                        */

    struct {
      __IOM uint32_t LOCK       : 8;            /*!< [7..0] Writing 0x3A locks the watchdog timer. Once locked, the
                                                     WDTCFG reg cannot be written and WDTEN is set.                            */
            uint32_t            : 24;
    } LOCK_b;
  } ;

  union {
    __IOM uint32_t COUNT;                       /*!< (@ 0x0000000C) This register holds the current count for the
                                                                    watch dog timer. This is a read only register.
                                                                    SW cannot set the value in the counter,
                                                                    but can reset it.                                          */

    struct {
      __IOM uint32_t COUNT      : 8;            /*!< [7..0] Read-Only current value of the WDT counter                         */
            uint32_t            : 24;
    } COUNT_b;
  } ;
  __IM  uint32_t  RESERVED[124];

  union {
    __IOM uint32_t WDTIEREN;                    /*!< (@ 0x00000200) Set bits in this register to allow this module
                                                                    to generate the corresponding interrupt.                   */

    struct {
      __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
            uint32_t            : 31;
    } WDTIEREN_b;
  } ;

  union {
    __IOM uint32_t WDTIERSTAT;                  /*!< (@ 0x00000204) Read bits from this register to discover the
                                                                    cause of a recent interrupt.                               */

    struct {
      __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
            uint32_t            : 31;
    } WDTIERSTAT_b;
  } ;

  union {
    __IOM uint32_t WDTIERCLR;                   /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
                                                                    the interrupt status associated with that
                                                                    bit.                                                       */

    struct {
      __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
            uint32_t            : 31;
    } WDTIERCLR_b;
  } ;

  union {
    __IOM uint32_t WDTIERSET;                   /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
                                                                    generate an interrupt from this module.
                                                                    (Generally used for testing purposes).                     */

    struct {
      __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
            uint32_t            : 31;
    } WDTIERSET_b;
  } ;
} WDT_Type;                                     /*!< Size = 528 (0x210)                                                        */


/** @} */ /* End of group Device_Peripheral_peripherals */


/* =========================================================================================================================== */
/* ================                          Device Specific Peripheral Address Map                           ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripheralAddr
  * @{
  */

#define ADC_BASE                    0x40038000UL
#define APBDMA_BASE                 0x40011000UL
#define CLKGEN_BASE                 0x40004000UL
#define CPU_BASE                    0x48000000UL
#define CRYPTO_BASE                 0x400C0000UL
#define DSP_BASE                    0x40100000UL
#define FPIO_BASE                   0x48001000UL
#define GPIO_BASE                   0x40010000UL
#define GPU_BASE                    0x40090000UL
#define I2S0_BASE                   0x40208000UL
#define IOM0_BASE                   0x40050000UL
#define IOM1_BASE                   0x40051000UL
#define IOM2_BASE                   0x40052000UL
#define IOM3_BASE                   0x40053000UL
#define IOM4_BASE                   0x40054000UL
#define IOM5_BASE                   0x40055000UL
#define IOM6_BASE                   0x40056000UL
#define IOM7_BASE                   0x40057000UL
#define IOSLAVE_BASE                0x40034000UL
#define MCUCTRL_BASE                0x40020000UL
#define MSPI0_BASE                  0x40060000UL
#define MSPI1_BASE                  0x40061000UL
#define MSPI2_BASE                  0x40062000UL
#define PDM0_BASE                   0x40201000UL
#define PWRCTRL_BASE                0x40021000UL
#define RSTGEN_BASE                 0x40000000UL
#define RTC_BASE                    0x40004800UL
#define SDIO_BASE                   0x40070000UL
#define SECURITY_BASE               0x40030000UL
#define STIMER_BASE                 0x40008800UL
#define TIMER_BASE                  0x40008000UL
#define UART0_BASE                  0x4001C000UL
#define UART1_BASE                  0x4001D000UL
#define UART2_BASE                  0x4001E000UL
#define UART3_BASE                  0x4001F000UL
#define VCOMP_BASE                  0x4000C000UL
#define WDT_BASE                    0x40024000UL

/** @} */ /* End of group Device_Peripheral_peripheralAddr */


/* =========================================================================================================================== */
/* ================                                  Peripheral declaration                                   ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_declaration
  * @{
  */

#define ADC                         ((ADC_Type*)               ADC_BASE)
#define APBDMA                      ((APBDMA_Type*)            APBDMA_BASE)
#define CLKGEN                      ((CLKGEN_Type*)            CLKGEN_BASE)
#define CPU                         ((CPU_Type*)               CPU_BASE)
#define CRYPTO                      ((CRYPTO_Type*)            CRYPTO_BASE)
#define DSP                         ((DSP_Type*)               DSP_BASE)
#define FPIO                        ((FPIO_Type*)              FPIO_BASE)
#define GPIO                        ((GPIO_Type*)              GPIO_BASE)
#define GPU                         ((GPU_Type*)               GPU_BASE)
#define I2S0                        ((I2S0_Type*)              I2S0_BASE)
#define IOM0                        ((IOM0_Type*)              IOM0_BASE)
#define IOM1                        ((IOM0_Type*)              IOM1_BASE)
#define IOM2                        ((IOM0_Type*)              IOM2_BASE)
#define IOM3                        ((IOM0_Type*)              IOM3_BASE)
#define IOM4                        ((IOM0_Type*)              IOM4_BASE)
#define IOM5                        ((IOM0_Type*)              IOM5_BASE)
#define IOM6                        ((IOM0_Type*)              IOM6_BASE)
#define IOM7                        ((IOM0_Type*)              IOM7_BASE)
#define IOSLAVE                     ((IOSLAVE_Type*)           IOSLAVE_BASE)
#define MCUCTRL                     ((MCUCTRL_Type*)           MCUCTRL_BASE)
#define MSPI0                       ((MSPI0_Type*)             MSPI0_BASE)
#define MSPI1                       ((MSPI0_Type*)             MSPI1_BASE)
#define MSPI2                       ((MSPI0_Type*)             MSPI2_BASE)
#define PDM0                        ((PDM0_Type*)              PDM0_BASE)
#define PWRCTRL                     ((PWRCTRL_Type*)           PWRCTRL_BASE)
#define RSTGEN                      ((RSTGEN_Type*)            RSTGEN_BASE)
#define RTC                         ((RTC_Type*)               RTC_BASE)
#define SDIO                        ((SDIO_Type*)              SDIO_BASE)
#define SECURITY                    ((SECURITY_Type*)          SECURITY_BASE)
#define STIMER                      ((STIMER_Type*)            STIMER_BASE)
#define TIMER                       ((TIMER_Type*)             TIMER_BASE)
#define UART0                       ((UART0_Type*)             UART0_BASE)
#define UART1                       ((UART0_Type*)             UART1_BASE)
#define UART2                       ((UART0_Type*)             UART2_BASE)
#define UART3                       ((UART0_Type*)             UART3_BASE)
#define VCOMP                       ((VCOMP_Type*)             VCOMP_BASE)
#define WDT                         ((WDT_Type*)               WDT_BASE)

/** @} */ /* End of group Device_Peripheral_declaration */


/* =========================================  End of section using anonymous unions  ========================================= */
#if defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#endif


/* =========================================================================================================================== */
/* ================                                Pos/Mask Peripheral Section                                ================ */
/* =========================================================================================================================== */


/** @addtogroup PosMask_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                            ADC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CFG  ========================================================== */
#define ADC_CFG_CLKSEL_Pos                (24UL)                    /*!< CLKSEL (Bit 24)                                       */
#define ADC_CFG_CLKSEL_Msk                (0x3000000UL)             /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
#define ADC_CFG_RPTTRIGSEL_Pos            (20UL)                    /*!< RPTTRIGSEL (Bit 20)                                   */
#define ADC_CFG_RPTTRIGSEL_Msk            (0x100000UL)              /*!< RPTTRIGSEL (Bitfield-Mask: 0x01)                      */
#define ADC_CFG_TRIGPOL_Pos               (19UL)                    /*!< TRIGPOL (Bit 19)                                      */
#define ADC_CFG_TRIGPOL_Msk               (0x80000UL)               /*!< TRIGPOL (Bitfield-Mask: 0x01)                         */
#define ADC_CFG_TRIGSEL_Pos               (16UL)                    /*!< TRIGSEL (Bit 16)                                      */
#define ADC_CFG_TRIGSEL_Msk               (0x70000UL)               /*!< TRIGSEL (Bitfield-Mask: 0x07)                         */
#define ADC_CFG_DFIFORDEN_Pos             (12UL)                    /*!< DFIFORDEN (Bit 12)                                    */
#define ADC_CFG_DFIFORDEN_Msk             (0x1000UL)                /*!< DFIFORDEN (Bitfield-Mask: 0x01)                       */
#define ADC_CFG_CKMODE_Pos                (4UL)                     /*!< CKMODE (Bit 4)                                        */
#define ADC_CFG_CKMODE_Msk                (0x10UL)                  /*!< CKMODE (Bitfield-Mask: 0x01)                          */
#define ADC_CFG_LPMODE_Pos                (3UL)                     /*!< LPMODE (Bit 3)                                        */
#define ADC_CFG_LPMODE_Msk                (0x8UL)                   /*!< LPMODE (Bitfield-Mask: 0x01)                          */
#define ADC_CFG_RPTEN_Pos                 (2UL)                     /*!< RPTEN (Bit 2)                                         */
#define ADC_CFG_RPTEN_Msk                 (0x4UL)                   /*!< RPTEN (Bitfield-Mask: 0x01)                           */
#define ADC_CFG_ADCEN_Pos                 (0UL)                     /*!< ADCEN (Bit 0)                                         */
#define ADC_CFG_ADCEN_Msk                 (0x1UL)                   /*!< ADCEN (Bitfield-Mask: 0x01)                           */
/* =========================================================  STAT  ========================================================== */
#define ADC_STAT_PWDSTAT_Pos              (0UL)                     /*!< PWDSTAT (Bit 0)                                       */
#define ADC_STAT_PWDSTAT_Msk              (0x1UL)                   /*!< PWDSTAT (Bitfield-Mask: 0x01)                         */
/* ==========================================================  SWT  ========================================================== */
#define ADC_SWT_SWT_Pos                   (0UL)                     /*!< SWT (Bit 0)                                           */
#define ADC_SWT_SWT_Msk                   (0xffUL)                  /*!< SWT (Bitfield-Mask: 0xff)                             */
/* ========================================================  SL0CFG  ========================================================= */
#define ADC_SL0CFG_ADSEL0_Pos             (24UL)                    /*!< ADSEL0 (Bit 24)                                       */
#define ADC_SL0CFG_ADSEL0_Msk             (0x7000000UL)             /*!< ADSEL0 (Bitfield-Mask: 0x07)                          */
#define ADC_SL0CFG_TRKCYC0_Pos            (18UL)                    /*!< TRKCYC0 (Bit 18)                                      */
#define ADC_SL0CFG_TRKCYC0_Msk            (0xfc0000UL)              /*!< TRKCYC0 (Bitfield-Mask: 0x3f)                         */
#define ADC_SL0CFG_PRMODE0_Pos            (16UL)                    /*!< PRMODE0 (Bit 16)                                      */
#define ADC_SL0CFG_PRMODE0_Msk            (0x30000UL)               /*!< PRMODE0 (Bitfield-Mask: 0x03)                         */
#define ADC_SL0CFG_CHSEL0_Pos             (8UL)                     /*!< CHSEL0 (Bit 8)                                        */
#define ADC_SL0CFG_CHSEL0_Msk             (0xf00UL)                 /*!< CHSEL0 (Bitfield-Mask: 0x0f)                          */
#define ADC_SL0CFG_WCEN0_Pos              (1UL)                     /*!< WCEN0 (Bit 1)                                         */
#define ADC_SL0CFG_WCEN0_Msk              (0x2UL)                   /*!< WCEN0 (Bitfield-Mask: 0x01)                           */
#define ADC_SL0CFG_SLEN0_Pos              (0UL)                     /*!< SLEN0 (Bit 0)                                         */
#define ADC_SL0CFG_SLEN0_Msk              (0x1UL)                   /*!< SLEN0 (Bitfield-Mask: 0x01)                           */
/* ========================================================  SL1CFG  ========================================================= */
#define ADC_SL1CFG_ADSEL1_Pos             (24UL)                    /*!< ADSEL1 (Bit 24)                                       */
#define ADC_SL1CFG_ADSEL1_Msk             (0x7000000UL)             /*!< ADSEL1 (Bitfield-Mask: 0x07)                          */
#define ADC_SL1CFG_TRKCYC1_Pos            (18UL)                    /*!< TRKCYC1 (Bit 18)                                      */
#define ADC_SL1CFG_TRKCYC1_Msk            (0xfc0000UL)              /*!< TRKCYC1 (Bitfield-Mask: 0x3f)                         */
#define ADC_SL1CFG_PRMODE1_Pos            (16UL)                    /*!< PRMODE1 (Bit 16)                                      */
#define ADC_SL1CFG_PRMODE1_Msk            (0x30000UL)               /*!< PRMODE1 (Bitfield-Mask: 0x03)                         */
#define ADC_SL1CFG_CHSEL1_Pos             (8UL)                     /*!< CHSEL1 (Bit 8)                                        */
#define ADC_SL1CFG_CHSEL1_Msk             (0xf00UL)                 /*!< CHSEL1 (Bitfield-Mask: 0x0f)                          */
#define ADC_SL1CFG_WCEN1_Pos              (1UL)                     /*!< WCEN1 (Bit 1)                                         */
#define ADC_SL1CFG_WCEN1_Msk              (0x2UL)                   /*!< WCEN1 (Bitfield-Mask: 0x01)                           */
#define ADC_SL1CFG_SLEN1_Pos              (0UL)                     /*!< SLEN1 (Bit 0)                                         */
#define ADC_SL1CFG_SLEN1_Msk              (0x1UL)                   /*!< SLEN1 (Bitfield-Mask: 0x01)                           */
/* ========================================================  SL2CFG  ========================================================= */
#define ADC_SL2CFG_ADSEL2_Pos             (24UL)                    /*!< ADSEL2 (Bit 24)                                       */
#define ADC_SL2CFG_ADSEL2_Msk             (0x7000000UL)             /*!< ADSEL2 (Bitfield-Mask: 0x07)                          */
#define ADC_SL2CFG_TRKCYC2_Pos            (18UL)                    /*!< TRKCYC2 (Bit 18)                                      */
#define ADC_SL2CFG_TRKCYC2_Msk            (0xfc0000UL)              /*!< TRKCYC2 (Bitfield-Mask: 0x3f)                         */
#define ADC_SL2CFG_PRMODE2_Pos            (16UL)                    /*!< PRMODE2 (Bit 16)                                      */
#define ADC_SL2CFG_PRMODE2_Msk            (0x30000UL)               /*!< PRMODE2 (Bitfield-Mask: 0x03)                         */
#define ADC_SL2CFG_CHSEL2_Pos             (8UL)                     /*!< CHSEL2 (Bit 8)                                        */
#define ADC_SL2CFG_CHSEL2_Msk             (0xf00UL)                 /*!< CHSEL2 (Bitfield-Mask: 0x0f)                          */
#define ADC_SL2CFG_WCEN2_Pos              (1UL)                     /*!< WCEN2 (Bit 1)                                         */
#define ADC_SL2CFG_WCEN2_Msk              (0x2UL)                   /*!< WCEN2 (Bitfield-Mask: 0x01)                           */
#define ADC_SL2CFG_SLEN2_Pos              (0UL)                     /*!< SLEN2 (Bit 0)                                         */
#define ADC_SL2CFG_SLEN2_Msk              (0x1UL)                   /*!< SLEN2 (Bitfield-Mask: 0x01)                           */
/* ========================================================  SL3CFG  ========================================================= */
#define ADC_SL3CFG_ADSEL3_Pos             (24UL)                    /*!< ADSEL3 (Bit 24)                                       */
#define ADC_SL3CFG_ADSEL3_Msk             (0x7000000UL)             /*!< ADSEL3 (Bitfield-Mask: 0x07)                          */
#define ADC_SL3CFG_TRKCYC3_Pos            (18UL)                    /*!< TRKCYC3 (Bit 18)                                      */
#define ADC_SL3CFG_TRKCYC3_Msk            (0xfc0000UL)              /*!< TRKCYC3 (Bitfield-Mask: 0x3f)                         */
#define ADC_SL3CFG_PRMODE3_Pos            (16UL)                    /*!< PRMODE3 (Bit 16)                                      */
#define ADC_SL3CFG_PRMODE3_Msk            (0x30000UL)               /*!< PRMODE3 (Bitfield-Mask: 0x03)                         */
#define ADC_SL3CFG_CHSEL3_Pos             (8UL)                     /*!< CHSEL3 (Bit 8)                                        */
#define ADC_SL3CFG_CHSEL3_Msk             (0xf00UL)                 /*!< CHSEL3 (Bitfield-Mask: 0x0f)                          */
#define ADC_SL3CFG_WCEN3_Pos              (1UL)                     /*!< WCEN3 (Bit 1)                                         */
#define ADC_SL3CFG_WCEN3_Msk              (0x2UL)                   /*!< WCEN3 (Bitfield-Mask: 0x01)                           */
#define ADC_SL3CFG_SLEN3_Pos              (0UL)                     /*!< SLEN3 (Bit 0)                                         */
#define ADC_SL3CFG_SLEN3_Msk              (0x1UL)                   /*!< SLEN3 (Bitfield-Mask: 0x01)                           */
/* ========================================================  SL4CFG  ========================================================= */
#define ADC_SL4CFG_ADSEL4_Pos             (24UL)                    /*!< ADSEL4 (Bit 24)                                       */
#define ADC_SL4CFG_ADSEL4_Msk             (0x7000000UL)             /*!< ADSEL4 (Bitfield-Mask: 0x07)                          */
#define ADC_SL4CFG_TRKCYC4_Pos            (18UL)                    /*!< TRKCYC4 (Bit 18)                                      */
#define ADC_SL4CFG_TRKCYC4_Msk            (0xfc0000UL)              /*!< TRKCYC4 (Bitfield-Mask: 0x3f)                         */
#define ADC_SL4CFG_PRMODE4_Pos            (16UL)                    /*!< PRMODE4 (Bit 16)                                      */
#define ADC_SL4CFG_PRMODE4_Msk            (0x30000UL)               /*!< PRMODE4 (Bitfield-Mask: 0x03)                         */
#define ADC_SL4CFG_CHSEL4_Pos             (8UL)                     /*!< CHSEL4 (Bit 8)                                        */
#define ADC_SL4CFG_CHSEL4_Msk             (0xf00UL)                 /*!< CHSEL4 (Bitfield-Mask: 0x0f)                          */
#define ADC_SL4CFG_WCEN4_Pos              (1UL)                     /*!< WCEN4 (Bit 1)                                         */
#define ADC_SL4CFG_WCEN4_Msk              (0x2UL)                   /*!< WCEN4 (Bitfield-Mask: 0x01)                           */
#define ADC_SL4CFG_SLEN4_Pos              (0UL)                     /*!< SLEN4 (Bit 0)                                         */
#define ADC_SL4CFG_SLEN4_Msk              (0x1UL)                   /*!< SLEN4 (Bitfield-Mask: 0x01)                           */
/* ========================================================  SL5CFG  ========================================================= */
#define ADC_SL5CFG_ADSEL5_Pos             (24UL)                    /*!< ADSEL5 (Bit 24)                                       */
#define ADC_SL5CFG_ADSEL5_Msk             (0x7000000UL)             /*!< ADSEL5 (Bitfield-Mask: 0x07)                          */
#define ADC_SL5CFG_TRKCYC5_Pos            (18UL)                    /*!< TRKCYC5 (Bit 18)                                      */
#define ADC_SL5CFG_TRKCYC5_Msk            (0xfc0000UL)              /*!< TRKCYC5 (Bitfield-Mask: 0x3f)                         */
#define ADC_SL5CFG_PRMODE5_Pos            (16UL)                    /*!< PRMODE5 (Bit 16)                                      */
#define ADC_SL5CFG_PRMODE5_Msk            (0x30000UL)               /*!< PRMODE5 (Bitfield-Mask: 0x03)                         */
#define ADC_SL5CFG_CHSEL5_Pos             (8UL)                     /*!< CHSEL5 (Bit 8)                                        */
#define ADC_SL5CFG_CHSEL5_Msk             (0xf00UL)                 /*!< CHSEL5 (Bitfield-Mask: 0x0f)                          */
#define ADC_SL5CFG_WCEN5_Pos              (1UL)                     /*!< WCEN5 (Bit 1)                                         */
#define ADC_SL5CFG_WCEN5_Msk              (0x2UL)                   /*!< WCEN5 (Bitfield-Mask: 0x01)                           */
#define ADC_SL5CFG_SLEN5_Pos              (0UL)                     /*!< SLEN5 (Bit 0)                                         */
#define ADC_SL5CFG_SLEN5_Msk              (0x1UL)                   /*!< SLEN5 (Bitfield-Mask: 0x01)                           */
/* ========================================================  SL6CFG  ========================================================= */
#define ADC_SL6CFG_ADSEL6_Pos             (24UL)                    /*!< ADSEL6 (Bit 24)                                       */
#define ADC_SL6CFG_ADSEL6_Msk             (0x7000000UL)             /*!< ADSEL6 (Bitfield-Mask: 0x07)                          */
#define ADC_SL6CFG_TRKCYC6_Pos            (18UL)                    /*!< TRKCYC6 (Bit 18)                                      */
#define ADC_SL6CFG_TRKCYC6_Msk            (0xfc0000UL)              /*!< TRKCYC6 (Bitfield-Mask: 0x3f)                         */
#define ADC_SL6CFG_PRMODE6_Pos            (16UL)                    /*!< PRMODE6 (Bit 16)                                      */
#define ADC_SL6CFG_PRMODE6_Msk            (0x30000UL)               /*!< PRMODE6 (Bitfield-Mask: 0x03)                         */
#define ADC_SL6CFG_CHSEL6_Pos             (8UL)                     /*!< CHSEL6 (Bit 8)                                        */
#define ADC_SL6CFG_CHSEL6_Msk             (0xf00UL)                 /*!< CHSEL6 (Bitfield-Mask: 0x0f)                          */
#define ADC_SL6CFG_WCEN6_Pos              (1UL)                     /*!< WCEN6 (Bit 1)                                         */
#define ADC_SL6CFG_WCEN6_Msk              (0x2UL)                   /*!< WCEN6 (Bitfield-Mask: 0x01)                           */
#define ADC_SL6CFG_SLEN6_Pos              (0UL)                     /*!< SLEN6 (Bit 0)                                         */
#define ADC_SL6CFG_SLEN6_Msk              (0x1UL)                   /*!< SLEN6 (Bitfield-Mask: 0x01)                           */
/* ========================================================  SL7CFG  ========================================================= */
#define ADC_SL7CFG_ADSEL7_Pos             (24UL)                    /*!< ADSEL7 (Bit 24)                                       */
#define ADC_SL7CFG_ADSEL7_Msk             (0x7000000UL)             /*!< ADSEL7 (Bitfield-Mask: 0x07)                          */
#define ADC_SL7CFG_TRKCYC7_Pos            (18UL)                    /*!< TRKCYC7 (Bit 18)                                      */
#define ADC_SL7CFG_TRKCYC7_Msk            (0xfc0000UL)              /*!< TRKCYC7 (Bitfield-Mask: 0x3f)                         */
#define ADC_SL7CFG_PRMODE7_Pos            (16UL)                    /*!< PRMODE7 (Bit 16)                                      */
#define ADC_SL7CFG_PRMODE7_Msk            (0x30000UL)               /*!< PRMODE7 (Bitfield-Mask: 0x03)                         */
#define ADC_SL7CFG_CHSEL7_Pos             (8UL)                     /*!< CHSEL7 (Bit 8)                                        */
#define ADC_SL7CFG_CHSEL7_Msk             (0xf00UL)                 /*!< CHSEL7 (Bitfield-Mask: 0x0f)                          */
#define ADC_SL7CFG_WCEN7_Pos              (1UL)                     /*!< WCEN7 (Bit 1)                                         */
#define ADC_SL7CFG_WCEN7_Msk              (0x2UL)                   /*!< WCEN7 (Bitfield-Mask: 0x01)                           */
#define ADC_SL7CFG_SLEN7_Pos              (0UL)                     /*!< SLEN7 (Bit 0)                                         */
#define ADC_SL7CFG_SLEN7_Msk              (0x1UL)                   /*!< SLEN7 (Bitfield-Mask: 0x01)                           */
/* =========================================================  WULIM  ========================================================= */
#define ADC_WULIM_ULIM_Pos                (0UL)                     /*!< ULIM (Bit 0)                                          */
#define ADC_WULIM_ULIM_Msk                (0xfffffUL)               /*!< ULIM (Bitfield-Mask: 0xfffff)                         */
/* =========================================================  WLLIM  ========================================================= */
#define ADC_WLLIM_LLIM_Pos                (0UL)                     /*!< LLIM (Bit 0)                                          */
#define ADC_WLLIM_LLIM_Msk                (0xfffffUL)               /*!< LLIM (Bitfield-Mask: 0xfffff)                         */
/* ========================================================  SCWLIM  ========================================================= */
#define ADC_SCWLIM_SCWLIMEN_Pos           (0UL)                     /*!< SCWLIMEN (Bit 0)                                      */
#define ADC_SCWLIM_SCWLIMEN_Msk           (0x1UL)                   /*!< SCWLIMEN (Bitfield-Mask: 0x01)                        */
/* =========================================================  FIFO  ========================================================== */
#define ADC_FIFO_RSVD_Pos                 (31UL)                    /*!< RSVD (Bit 31)                                         */
#define ADC_FIFO_RSVD_Msk                 (0x80000000UL)            /*!< RSVD (Bitfield-Mask: 0x01)                            */
#define ADC_FIFO_SLOTNUM_Pos              (28UL)                    /*!< SLOTNUM (Bit 28)                                      */
#define ADC_FIFO_SLOTNUM_Msk              (0x70000000UL)            /*!< SLOTNUM (Bitfield-Mask: 0x07)                         */
#define ADC_FIFO_COUNT_Pos                (20UL)                    /*!< COUNT (Bit 20)                                        */
#define ADC_FIFO_COUNT_Msk                (0xff00000UL)             /*!< COUNT (Bitfield-Mask: 0xff)                           */
#define ADC_FIFO_DATA_Pos                 (0UL)                     /*!< DATA (Bit 0)                                          */
#define ADC_FIFO_DATA_Msk                 (0xfffffUL)               /*!< DATA (Bitfield-Mask: 0xfffff)                         */
/* ========================================================  FIFOPR  ========================================================= */
#define ADC_FIFOPR_RSVDPR_Pos             (31UL)                    /*!< RSVDPR (Bit 31)                                       */
#define ADC_FIFOPR_RSVDPR_Msk             (0x80000000UL)            /*!< RSVDPR (Bitfield-Mask: 0x01)                          */
#define ADC_FIFOPR_SLOTNUMPR_Pos          (28UL)                    /*!< SLOTNUMPR (Bit 28)                                    */
#define ADC_FIFOPR_SLOTNUMPR_Msk          (0x70000000UL)            /*!< SLOTNUMPR (Bitfield-Mask: 0x07)                       */
#define ADC_FIFOPR_COUNT_Pos              (20UL)                    /*!< COUNT (Bit 20)                                        */
#define ADC_FIFOPR_COUNT_Msk              (0xff00000UL)             /*!< COUNT (Bitfield-Mask: 0xff)                           */
#define ADC_FIFOPR_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
#define ADC_FIFOPR_DATA_Msk               (0xfffffUL)               /*!< DATA (Bitfield-Mask: 0xfffff)                         */
/* =====================================================  INTTRIGTIMER  ====================================================== */
#define ADC_INTTRIGTIMER_TIMEREN_Pos      (31UL)                    /*!< TIMEREN (Bit 31)                                      */
#define ADC_INTTRIGTIMER_TIMEREN_Msk      (0x80000000UL)            /*!< TIMEREN (Bitfield-Mask: 0x01)                         */
#define ADC_INTTRIGTIMER_CLKDIV_Pos       (16UL)                    /*!< CLKDIV (Bit 16)                                       */
#define ADC_INTTRIGTIMER_CLKDIV_Msk       (0x70000UL)               /*!< CLKDIV (Bitfield-Mask: 0x07)                          */
#define ADC_INTTRIGTIMER_TIMERMAX_Pos     (0UL)                     /*!< TIMERMAX (Bit 0)                                      */
#define ADC_INTTRIGTIMER_TIMERMAX_Msk     (0x3ffUL)                 /*!< TIMERMAX (Bitfield-Mask: 0x3ff)                       */
/* =========================================================  ZXCFG  ========================================================= */
#define ADC_ZXCFG_ZXCHANSEL_Pos           (4UL)                     /*!< ZXCHANSEL (Bit 4)                                     */
#define ADC_ZXCFG_ZXCHANSEL_Msk           (0x10UL)                  /*!< ZXCHANSEL (Bitfield-Mask: 0x01)                       */
#define ADC_ZXCFG_ZXEN_Pos                (0UL)                     /*!< ZXEN (Bit 0)                                          */
#define ADC_ZXCFG_ZXEN_Msk                (0x1UL)                   /*!< ZXEN (Bitfield-Mask: 0x01)                            */
/* =========================================================  ZXLIM  ========================================================= */
#define ADC_ZXLIM_UZXC_Pos                (16UL)                    /*!< UZXC (Bit 16)                                         */
#define ADC_ZXLIM_UZXC_Msk                (0xfff0000UL)             /*!< UZXC (Bitfield-Mask: 0xfff)                           */
#define ADC_ZXLIM_LZXC_Pos                (0UL)                     /*!< LZXC (Bit 0)                                          */
#define ADC_ZXLIM_LZXC_Msk                (0xfffUL)                 /*!< LZXC (Bitfield-Mask: 0xfff)                           */
/* ========================================================  GAINCFG  ======================================================== */
#define ADC_GAINCFG_UPDATEMODE_Pos        (4UL)                     /*!< UPDATEMODE (Bit 4)                                    */
#define ADC_GAINCFG_UPDATEMODE_Msk        (0x10UL)                  /*!< UPDATEMODE (Bitfield-Mask: 0x01)                      */
#define ADC_GAINCFG_PGACTRLEN_Pos         (0UL)                     /*!< PGACTRLEN (Bit 0)                                     */
#define ADC_GAINCFG_PGACTRLEN_Msk         (0x1UL)                   /*!< PGACTRLEN (Bitfield-Mask: 0x01)                       */
/* =========================================================  GAIN  ========================================================== */
#define ADC_GAIN_HGBDELTA_Pos             (24UL)                    /*!< HGBDELTA (Bit 24)                                     */
#define ADC_GAIN_HGBDELTA_Msk             (0x7f000000UL)            /*!< HGBDELTA (Bitfield-Mask: 0x7f)                        */
#define ADC_GAIN_LGB_Pos                  (16UL)                    /*!< LGB (Bit 16)                                          */
#define ADC_GAIN_LGB_Msk                  (0x7f0000UL)              /*!< LGB (Bitfield-Mask: 0x7f)                             */
#define ADC_GAIN_HGADELTA_Pos             (8UL)                     /*!< HGADELTA (Bit 8)                                      */
#define ADC_GAIN_HGADELTA_Msk             (0x7f00UL)                /*!< HGADELTA (Bitfield-Mask: 0x7f)                        */
#define ADC_GAIN_LGA_Pos                  (0UL)                     /*!< LGA (Bit 0)                                           */
#define ADC_GAIN_LGA_Msk                  (0x7fUL)                  /*!< LGA (Bitfield-Mask: 0x7f)                             */
/* ========================================================  SATCFG  ========================================================= */
#define ADC_SATCFG_SATCHANSEL_Pos         (4UL)                     /*!< SATCHANSEL (Bit 4)                                    */
#define ADC_SATCFG_SATCHANSEL_Msk         (0x10UL)                  /*!< SATCHANSEL (Bitfield-Mask: 0x01)                      */
#define ADC_SATCFG_SATEN_Pos              (0UL)                     /*!< SATEN (Bit 0)                                         */
#define ADC_SATCFG_SATEN_Msk              (0x1UL)                   /*!< SATEN (Bitfield-Mask: 0x01)                           */
/* ========================================================  SATLIM  ========================================================= */
#define ADC_SATLIM_USATC_Pos              (16UL)                    /*!< USATC (Bit 16)                                        */
#define ADC_SATLIM_USATC_Msk              (0xfff0000UL)             /*!< USATC (Bitfield-Mask: 0xfff)                          */
#define ADC_SATLIM_LSATC_Pos              (0UL)                     /*!< LSATC (Bit 0)                                         */
#define ADC_SATLIM_LSATC_Msk              (0xfffUL)                 /*!< LSATC (Bitfield-Mask: 0xfff)                          */
/* ========================================================  SATMAX  ========================================================= */
#define ADC_SATMAX_SATCBMAX_Pos           (16UL)                    /*!< SATCBMAX (Bit 16)                                     */
#define ADC_SATMAX_SATCBMAX_Msk           (0xfff0000UL)             /*!< SATCBMAX (Bitfield-Mask: 0xfff)                       */
#define ADC_SATMAX_SATCAMAX_Pos           (0UL)                     /*!< SATCAMAX (Bit 0)                                      */
#define ADC_SATMAX_SATCAMAX_Msk           (0xfffUL)                 /*!< SATCAMAX (Bitfield-Mask: 0xfff)                       */
/* ========================================================  SATCLR  ========================================================= */
#define ADC_SATCLR_SATCBCLR_Pos           (1UL)                     /*!< SATCBCLR (Bit 1)                                      */
#define ADC_SATCLR_SATCBCLR_Msk           (0x2UL)                   /*!< SATCBCLR (Bitfield-Mask: 0x01)                        */
#define ADC_SATCLR_SATCACLR_Pos           (0UL)                     /*!< SATCACLR (Bit 0)                                      */
#define ADC_SATCLR_SATCACLR_Msk           (0x1UL)                   /*!< SATCACLR (Bitfield-Mask: 0x01)                        */
/* ========================================================  CALCTRL  ======================================================== */
#define ADC_CALCTRL_ISODLY_Pos            (10UL)                    /*!< ISODLY (Bit 10)                                       */
#define ADC_CALCTRL_ISODLY_Msk            (0xffc00UL)               /*!< ISODLY (Bitfield-Mask: 0x3ff)                         */
#define ADC_CALCTRL_RESETDLY_Pos          (0UL)                     /*!< RESETDLY (Bit 0)                                      */
#define ADC_CALCTRL_RESETDLY_Msk          (0x3ffUL)                 /*!< RESETDLY (Bitfield-Mask: 0x3ff)                       */
/* =========================================================  INTEN  ========================================================= */
#define ADC_INTEN_SATCB_Pos               (11UL)                    /*!< SATCB (Bit 11)                                        */
#define ADC_INTEN_SATCB_Msk               (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
#define ADC_INTEN_SATCA_Pos               (10UL)                    /*!< SATCA (Bit 10)                                        */
#define ADC_INTEN_SATCA_Msk               (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
#define ADC_INTEN_ZXCB_Pos                (9UL)                     /*!< ZXCB (Bit 9)                                          */
#define ADC_INTEN_ZXCB_Msk                (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
#define ADC_INTEN_ZXCA_Pos                (8UL)                     /*!< ZXCA (Bit 8)                                          */
#define ADC_INTEN_ZXCA_Msk                (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
#define ADC_INTEN_DERR_Pos                (7UL)                     /*!< DERR (Bit 7)                                          */
#define ADC_INTEN_DERR_Msk                (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
#define ADC_INTEN_DCMP_Pos                (6UL)                     /*!< DCMP (Bit 6)                                          */
#define ADC_INTEN_DCMP_Msk                (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
#define ADC_INTEN_WCINC_Pos               (5UL)                     /*!< WCINC (Bit 5)                                         */
#define ADC_INTEN_WCINC_Msk               (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
#define ADC_INTEN_WCEXC_Pos               (4UL)                     /*!< WCEXC (Bit 4)                                         */
#define ADC_INTEN_WCEXC_Msk               (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
#define ADC_INTEN_FIFOOVR2_Pos            (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
#define ADC_INTEN_FIFOOVR2_Msk            (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
#define ADC_INTEN_FIFOOVR1_Pos            (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
#define ADC_INTEN_FIFOOVR1_Msk            (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
#define ADC_INTEN_SCNCMP_Pos              (1UL)                     /*!< SCNCMP (Bit 1)                                        */
#define ADC_INTEN_SCNCMP_Msk              (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
#define ADC_INTEN_CNVCMP_Pos              (0UL)                     /*!< CNVCMP (Bit 0)                                        */
#define ADC_INTEN_CNVCMP_Msk              (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
/* ========================================================  INTSTAT  ======================================================== */
#define ADC_INTSTAT_SATCB_Pos             (11UL)                    /*!< SATCB (Bit 11)                                        */
#define ADC_INTSTAT_SATCB_Msk             (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
#define ADC_INTSTAT_SATCA_Pos             (10UL)                    /*!< SATCA (Bit 10)                                        */
#define ADC_INTSTAT_SATCA_Msk             (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
#define ADC_INTSTAT_ZXCB_Pos              (9UL)                     /*!< ZXCB (Bit 9)                                          */
#define ADC_INTSTAT_ZXCB_Msk              (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
#define ADC_INTSTAT_ZXCA_Pos              (8UL)                     /*!< ZXCA (Bit 8)                                          */
#define ADC_INTSTAT_ZXCA_Msk              (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
#define ADC_INTSTAT_DERR_Pos              (7UL)                     /*!< DERR (Bit 7)                                          */
#define ADC_INTSTAT_DERR_Msk              (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
#define ADC_INTSTAT_DCMP_Pos              (6UL)                     /*!< DCMP (Bit 6)                                          */
#define ADC_INTSTAT_DCMP_Msk              (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
#define ADC_INTSTAT_WCINC_Pos             (5UL)                     /*!< WCINC (Bit 5)                                         */
#define ADC_INTSTAT_WCINC_Msk             (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
#define ADC_INTSTAT_WCEXC_Pos             (4UL)                     /*!< WCEXC (Bit 4)                                         */
#define ADC_INTSTAT_WCEXC_Msk             (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
#define ADC_INTSTAT_FIFOOVR2_Pos          (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
#define ADC_INTSTAT_FIFOOVR2_Msk          (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
#define ADC_INTSTAT_FIFOOVR1_Pos          (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
#define ADC_INTSTAT_FIFOOVR1_Msk          (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
#define ADC_INTSTAT_SCNCMP_Pos            (1UL)                     /*!< SCNCMP (Bit 1)                                        */
#define ADC_INTSTAT_SCNCMP_Msk            (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
#define ADC_INTSTAT_CNVCMP_Pos            (0UL)                     /*!< CNVCMP (Bit 0)                                        */
#define ADC_INTSTAT_CNVCMP_Msk            (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
/* ========================================================  INTCLR  ========================================================= */
#define ADC_INTCLR_SATCB_Pos              (11UL)                    /*!< SATCB (Bit 11)                                        */
#define ADC_INTCLR_SATCB_Msk              (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
#define ADC_INTCLR_SATCA_Pos              (10UL)                    /*!< SATCA (Bit 10)                                        */
#define ADC_INTCLR_SATCA_Msk              (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
#define ADC_INTCLR_ZXCB_Pos               (9UL)                     /*!< ZXCB (Bit 9)                                          */
#define ADC_INTCLR_ZXCB_Msk               (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
#define ADC_INTCLR_ZXCA_Pos               (8UL)                     /*!< ZXCA (Bit 8)                                          */
#define ADC_INTCLR_ZXCA_Msk               (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
#define ADC_INTCLR_DERR_Pos               (7UL)                     /*!< DERR (Bit 7)                                          */
#define ADC_INTCLR_DERR_Msk               (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
#define ADC_INTCLR_DCMP_Pos               (6UL)                     /*!< DCMP (Bit 6)                                          */
#define ADC_INTCLR_DCMP_Msk               (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
#define ADC_INTCLR_WCINC_Pos              (5UL)                     /*!< WCINC (Bit 5)                                         */
#define ADC_INTCLR_WCINC_Msk              (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
#define ADC_INTCLR_WCEXC_Pos              (4UL)                     /*!< WCEXC (Bit 4)                                         */
#define ADC_INTCLR_WCEXC_Msk              (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
#define ADC_INTCLR_FIFOOVR2_Pos           (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
#define ADC_INTCLR_FIFOOVR2_Msk           (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
#define ADC_INTCLR_FIFOOVR1_Pos           (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
#define ADC_INTCLR_FIFOOVR1_Msk           (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
#define ADC_INTCLR_SCNCMP_Pos             (1UL)                     /*!< SCNCMP (Bit 1)                                        */
#define ADC_INTCLR_SCNCMP_Msk             (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
#define ADC_INTCLR_CNVCMP_Pos             (0UL)                     /*!< CNVCMP (Bit 0)                                        */
#define ADC_INTCLR_CNVCMP_Msk             (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
/* ========================================================  INTSET  ========================================================= */
#define ADC_INTSET_SATCB_Pos              (11UL)                    /*!< SATCB (Bit 11)                                        */
#define ADC_INTSET_SATCB_Msk              (0x800UL)                 /*!< SATCB (Bitfield-Mask: 0x01)                           */
#define ADC_INTSET_SATCA_Pos              (10UL)                    /*!< SATCA (Bit 10)                                        */
#define ADC_INTSET_SATCA_Msk              (0x400UL)                 /*!< SATCA (Bitfield-Mask: 0x01)                           */
#define ADC_INTSET_ZXCB_Pos               (9UL)                     /*!< ZXCB (Bit 9)                                          */
#define ADC_INTSET_ZXCB_Msk               (0x200UL)                 /*!< ZXCB (Bitfield-Mask: 0x01)                            */
#define ADC_INTSET_ZXCA_Pos               (8UL)                     /*!< ZXCA (Bit 8)                                          */
#define ADC_INTSET_ZXCA_Msk               (0x100UL)                 /*!< ZXCA (Bitfield-Mask: 0x01)                            */
#define ADC_INTSET_DERR_Pos               (7UL)                     /*!< DERR (Bit 7)                                          */
#define ADC_INTSET_DERR_Msk               (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
#define ADC_INTSET_DCMP_Pos               (6UL)                     /*!< DCMP (Bit 6)                                          */
#define ADC_INTSET_DCMP_Msk               (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
#define ADC_INTSET_WCINC_Pos              (5UL)                     /*!< WCINC (Bit 5)                                         */
#define ADC_INTSET_WCINC_Msk              (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
#define ADC_INTSET_WCEXC_Pos              (4UL)                     /*!< WCEXC (Bit 4)                                         */
#define ADC_INTSET_WCEXC_Msk              (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
#define ADC_INTSET_FIFOOVR2_Pos           (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
#define ADC_INTSET_FIFOOVR2_Msk           (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
#define ADC_INTSET_FIFOOVR1_Pos           (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
#define ADC_INTSET_FIFOOVR1_Msk           (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
#define ADC_INTSET_SCNCMP_Pos             (1UL)                     /*!< SCNCMP (Bit 1)                                        */
#define ADC_INTSET_SCNCMP_Msk             (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
#define ADC_INTSET_CNVCMP_Pos             (0UL)                     /*!< CNVCMP (Bit 0)                                        */
#define ADC_INTSET_CNVCMP_Msk             (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
/* =======================================================  DMATRIGEN  ======================================================= */
#define ADC_DMATRIGEN_DFIFOFULL_Pos       (1UL)                     /*!< DFIFOFULL (Bit 1)                                     */
#define ADC_DMATRIGEN_DFIFOFULL_Msk       (0x2UL)                   /*!< DFIFOFULL (Bitfield-Mask: 0x01)                       */
#define ADC_DMATRIGEN_DFIFO75_Pos         (0UL)                     /*!< DFIFO75 (Bit 0)                                       */
#define ADC_DMATRIGEN_DFIFO75_Msk         (0x1UL)                   /*!< DFIFO75 (Bitfield-Mask: 0x01)                         */
/* ======================================================  DMATRIGSTAT  ====================================================== */
#define ADC_DMATRIGSTAT_DFULLSTAT_Pos     (1UL)                     /*!< DFULLSTAT (Bit 1)                                     */
#define ADC_DMATRIGSTAT_DFULLSTAT_Msk     (0x2UL)                   /*!< DFULLSTAT (Bitfield-Mask: 0x01)                       */
#define ADC_DMATRIGSTAT_D75STAT_Pos       (0UL)                     /*!< D75STAT (Bit 0)                                       */
#define ADC_DMATRIGSTAT_D75STAT_Msk       (0x1UL)                   /*!< D75STAT (Bitfield-Mask: 0x01)                         */
/* ========================================================  DMACFG  ========================================================= */
#define ADC_DMACFG_DPWROFF_Pos            (18UL)                    /*!< DPWROFF (Bit 18)                                      */
#define ADC_DMACFG_DPWROFF_Msk            (0x40000UL)               /*!< DPWROFF (Bitfield-Mask: 0x01)                         */
#define ADC_DMACFG_DMAMSK_Pos             (17UL)                    /*!< DMAMSK (Bit 17)                                       */
#define ADC_DMACFG_DMAMSK_Msk             (0x20000UL)               /*!< DMAMSK (Bitfield-Mask: 0x01)                          */
#define ADC_DMACFG_DMADYNPRI_Pos          (9UL)                     /*!< DMADYNPRI (Bit 9)                                     */
#define ADC_DMACFG_DMADYNPRI_Msk          (0x200UL)                 /*!< DMADYNPRI (Bitfield-Mask: 0x01)                       */
#define ADC_DMACFG_DMAPRI_Pos             (8UL)                     /*!< DMAPRI (Bit 8)                                        */
#define ADC_DMACFG_DMAPRI_Msk             (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
#define ADC_DMACFG_DMADIR_Pos             (2UL)                     /*!< DMADIR (Bit 2)                                        */
#define ADC_DMACFG_DMADIR_Msk             (0x4UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
#define ADC_DMACFG_DMAEN_Pos              (0UL)                     /*!< DMAEN (Bit 0)                                         */
#define ADC_DMACFG_DMAEN_Msk              (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
/* ======================================================  DMATOTCOUNT  ====================================================== */
#define ADC_DMATOTCOUNT_TOTCOUNT_Pos      (2UL)                     /*!< TOTCOUNT (Bit 2)                                      */
#define ADC_DMATOTCOUNT_TOTCOUNT_Msk      (0x3fffcUL)               /*!< TOTCOUNT (Bitfield-Mask: 0xffff)                      */
/* ======================================================  DMATARGADDR  ====================================================== */
#define ADC_DMATARGADDR_UTARGADDR_Pos     (28UL)                    /*!< UTARGADDR (Bit 28)                                    */
#define ADC_DMATARGADDR_UTARGADDR_Msk     (0xf0000000UL)            /*!< UTARGADDR (Bitfield-Mask: 0x0f)                       */
#define ADC_DMATARGADDR_LTARGADDR_Pos     (0UL)                     /*!< LTARGADDR (Bit 0)                                     */
#define ADC_DMATARGADDR_LTARGADDR_Msk     (0xfffffffUL)             /*!< LTARGADDR (Bitfield-Mask: 0xfffffff)                  */
/* ========================================================  DMASTAT  ======================================================== */
#define ADC_DMASTAT_DMAERR_Pos            (2UL)                     /*!< DMAERR (Bit 2)                                        */
#define ADC_DMASTAT_DMAERR_Msk            (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
#define ADC_DMASTAT_DMACPL_Pos            (1UL)                     /*!< DMACPL (Bit 1)                                        */
#define ADC_DMASTAT_DMACPL_Msk            (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
#define ADC_DMASTAT_DMATIP_Pos            (0UL)                     /*!< DMATIP (Bit 0)                                        */
#define ADC_DMASTAT_DMATIP_Msk            (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */


/* =========================================================================================================================== */
/* ================                                          APBDMA                                           ================ */
/* =========================================================================================================================== */

/* ========================================================  BBVALUE  ======================================================== */
#define APBDMA_BBVALUE_PIN_Pos            (16UL)                    /*!< PIN (Bit 16)                                          */
#define APBDMA_BBVALUE_PIN_Msk            (0xff0000UL)              /*!< PIN (Bitfield-Mask: 0xff)                             */
#define APBDMA_BBVALUE_DATAOUT_Pos        (0UL)                     /*!< DATAOUT (Bit 0)                                       */
#define APBDMA_BBVALUE_DATAOUT_Msk        (0xffUL)                  /*!< DATAOUT (Bitfield-Mask: 0xff)                         */
/* ======================================================  BBSETCLEAR  ======================================================= */
#define APBDMA_BBSETCLEAR_CLEAR_Pos       (16UL)                    /*!< CLEAR (Bit 16)                                        */
#define APBDMA_BBSETCLEAR_CLEAR_Msk       (0xff0000UL)              /*!< CLEAR (Bitfield-Mask: 0xff)                           */
#define APBDMA_BBSETCLEAR_SET_Pos         (0UL)                     /*!< SET (Bit 0)                                           */
#define APBDMA_BBSETCLEAR_SET_Msk         (0xffUL)                  /*!< SET (Bitfield-Mask: 0xff)                             */
/* ========================================================  BBINPUT  ======================================================== */
#define APBDMA_BBINPUT_DATAIN_Pos         (0UL)                     /*!< DATAIN (Bit 0)                                        */
#define APBDMA_BBINPUT_DATAIN_Msk         (0xffUL)                  /*!< DATAIN (Bitfield-Mask: 0xff)                          */
/* =======================================================  DEBUGDATA  ======================================================= */
#define APBDMA_DEBUGDATA_DEBUGDATA_Pos    (0UL)                     /*!< DEBUGDATA (Bit 0)                                     */
#define APBDMA_DEBUGDATA_DEBUGDATA_Msk    (0xffffffffUL)            /*!< DEBUGDATA (Bitfield-Mask: 0xffffffff)                 */
/* =========================================================  DEBUG  ========================================================= */
#define APBDMA_DEBUG_DEBUGEN_Pos          (0UL)                     /*!< DEBUGEN (Bit 0)                                       */
#define APBDMA_DEBUG_DEBUGEN_Msk          (0xfUL)                   /*!< DEBUGEN (Bitfield-Mask: 0x0f)                         */


/* =========================================================================================================================== */
/* ================                                          CLKGEN                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  OCTRL  ========================================================= */
#define CLKGEN_OCTRL_OSEL_Pos             (7UL)                     /*!< OSEL (Bit 7)                                          */
#define CLKGEN_OCTRL_OSEL_Msk             (0x80UL)                  /*!< OSEL (Bitfield-Mask: 0x01)                            */
/* ========================================================  CLKOUT  ========================================================= */
#define CLKGEN_CLKOUT_CKEN_Pos            (7UL)                     /*!< CKEN (Bit 7)                                          */
#define CLKGEN_CLKOUT_CKEN_Msk            (0x80UL)                  /*!< CKEN (Bitfield-Mask: 0x01)                            */
#define CLKGEN_CLKOUT_CKSEL_Pos           (0UL)                     /*!< CKSEL (Bit 0)                                         */
#define CLKGEN_CLKOUT_CKSEL_Msk           (0x3fUL)                  /*!< CKSEL (Bitfield-Mask: 0x3f)                           */
/* =========================================================  HFADJ  ========================================================= */
#define CLKGEN_HFADJ_HFADJMAXDELTA_Pos    (24UL)                    /*!< HFADJMAXDELTA (Bit 24)                                */
#define CLKGEN_HFADJ_HFADJMAXDELTA_Msk    (0x1f000000UL)            /*!< HFADJMAXDELTA (Bitfield-Mask: 0x1f)                   */
#define CLKGEN_HFADJ_HFADJGAIN_Pos        (21UL)                    /*!< HFADJGAIN (Bit 21)                                    */
#define CLKGEN_HFADJ_HFADJGAIN_Msk        (0xe00000UL)              /*!< HFADJGAIN (Bitfield-Mask: 0x07)                       */
#define CLKGEN_HFADJ_HFWARMUP_Pos         (20UL)                    /*!< HFWARMUP (Bit 20)                                     */
#define CLKGEN_HFADJ_HFWARMUP_Msk         (0x100000UL)              /*!< HFWARMUP (Bitfield-Mask: 0x01)                        */
#define CLKGEN_HFADJ_HFXTADJ_Pos          (8UL)                     /*!< HFXTADJ (Bit 8)                                       */
#define CLKGEN_HFADJ_HFXTADJ_Msk          (0xfff00UL)               /*!< HFXTADJ (Bitfield-Mask: 0xfff)                        */
#define CLKGEN_HFADJ_HFADJCK_Pos          (1UL)                     /*!< HFADJCK (Bit 1)                                       */
#define CLKGEN_HFADJ_HFADJCK_Msk          (0xeUL)                   /*!< HFADJCK (Bitfield-Mask: 0x07)                         */
#define CLKGEN_HFADJ_HFADJEN_Pos          (0UL)                     /*!< HFADJEN (Bit 0)                                       */
#define CLKGEN_HFADJ_HFADJEN_Msk          (0x1UL)                   /*!< HFADJEN (Bitfield-Mask: 0x01)                         */
/* ======================================================  CLOCKENSTAT  ====================================================== */
#define CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Pos (0UL)                    /*!< CLOCKENSTAT (Bit 0)                                   */
#define CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Msk (0xffffffffUL)           /*!< CLOCKENSTAT (Bitfield-Mask: 0xffffffff)               */
/* =====================================================  CLOCKEN2STAT  ====================================================== */
#define CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Pos (0UL)                  /*!< CLOCKEN2STAT (Bit 0)                                  */
#define CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Msk (0xffffffffUL)         /*!< CLOCKEN2STAT (Bitfield-Mask: 0xffffffff)              */
/* =====================================================  CLOCKEN3STAT  ====================================================== */
#define CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Pos (0UL)                  /*!< CLOCKEN3STAT (Bit 0)                                  */
#define CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Msk (0xffffffffUL)         /*!< CLOCKEN3STAT (Bitfield-Mask: 0xffffffff)              */
/* =========================================================  MISC  ========================================================== */
#define CLKGEN_MISC_CLKGENMISCSPARE_Pos   (25UL)                    /*!< CLKGENMISCSPARE (Bit 25)                              */
#define CLKGEN_MISC_CLKGENMISCSPARE_Msk   (0x2000000UL)             /*!< CLKGENMISCSPARE (Bitfield-Mask: 0x01)                 */
#define CLKGEN_MISC_HFRC96TRUNKGATE_Pos   (24UL)                    /*!< HFRC96TRUNKGATE (Bit 24)                              */
#define CLKGEN_MISC_HFRC96TRUNKGATE_Msk   (0x1000000UL)             /*!< HFRC96TRUNKGATE (Bitfield-Mask: 0x01)                 */
#define CLKGEN_MISC_HFRCFUNCCLKGATEEN_Pos (23UL)                    /*!< HFRCFUNCCLKGATEEN (Bit 23)                            */
#define CLKGEN_MISC_HFRCFUNCCLKGATEEN_Msk (0x800000UL)              /*!< HFRCFUNCCLKGATEEN (Bitfield-Mask: 0x01)               */
#define CLKGEN_MISC_ETMTRACECLKCLKGATEEN_Pos (22UL)                 /*!< ETMTRACECLKCLKGATEEN (Bit 22)                         */
#define CLKGEN_MISC_ETMTRACECLKCLKGATEEN_Msk (0x400000UL)           /*!< ETMTRACECLKCLKGATEEN (Bitfield-Mask: 0x01)            */
#define CLKGEN_MISC_APBDMACPUCLKCLKGATEEN_Pos (21UL)                /*!< APBDMACPUCLKCLKGATEEN (Bit 21)                        */
#define CLKGEN_MISC_APBDMACPUCLKCLKGATEEN_Msk (0x200000UL)          /*!< APBDMACPUCLKCLKGATEEN (Bitfield-Mask: 0x01)           */
#define CLKGEN_MISC_GFXAXICLKCLKGATEEN_Pos (20UL)                   /*!< GFXAXICLKCLKGATEEN (Bit 20)                           */
#define CLKGEN_MISC_GFXAXICLKCLKGATEEN_Msk (0x100000UL)             /*!< GFXAXICLKCLKGATEEN (Bitfield-Mask: 0x01)              */
#define CLKGEN_MISC_GFXCLKCLKGATEEN_Pos   (19UL)                    /*!< GFXCLKCLKGATEEN (Bit 19)                              */
#define CLKGEN_MISC_GFXCLKCLKGATEEN_Msk   (0x80000UL)               /*!< GFXCLKCLKGATEEN (Bitfield-Mask: 0x01)                 */
#define CLKGEN_MISC_CM4DAXICLKGATEEN_Pos  (18UL)                    /*!< CM4DAXICLKGATEEN (Bit 18)                             */
#define CLKGEN_MISC_CM4DAXICLKGATEEN_Msk  (0x40000UL)               /*!< CM4DAXICLKGATEEN (Bitfield-Mask: 0x01)                */
#define CLKGEN_MISC_PWRONCLKENI2S1REFCLK_Pos (16UL)                 /*!< PWRONCLKENI2S1REFCLK (Bit 16)                         */
#define CLKGEN_MISC_PWRONCLKENI2S1REFCLK_Msk (0x10000UL)            /*!< PWRONCLKENI2S1REFCLK (Bitfield-Mask: 0x01)            */
#define CLKGEN_MISC_PWRONCLKENI2S0REFCLK_Pos (15UL)                 /*!< PWRONCLKENI2S0REFCLK (Bit 15)                         */
#define CLKGEN_MISC_PWRONCLKENI2S0REFCLK_Msk (0x8000UL)             /*!< PWRONCLKENI2S0REFCLK (Bitfield-Mask: 0x01)            */
#define CLKGEN_MISC_AXIXACLKENOVRRIDE_Pos (14UL)                    /*!< AXIXACLKENOVRRIDE (Bit 14)                            */
#define CLKGEN_MISC_AXIXACLKENOVRRIDE_Msk (0x4000UL)                /*!< AXIXACLKENOVRRIDE (Bitfield-Mask: 0x01)               */
#define CLKGEN_MISC_PWRONCLKENI2S1_Pos    (13UL)                    /*!< PWRONCLKENI2S1 (Bit 13)                               */
#define CLKGEN_MISC_PWRONCLKENI2S1_Msk    (0x2000UL)                /*!< PWRONCLKENI2S1 (Bitfield-Mask: 0x01)                  */
#define CLKGEN_MISC_PWRONCLKENI2S0_Pos    (12UL)                    /*!< PWRONCLKENI2S0 (Bit 12)                               */
#define CLKGEN_MISC_PWRONCLKENI2S0_Msk    (0x1000UL)                /*!< PWRONCLKENI2S0 (Bitfield-Mask: 0x01)                  */
#define CLKGEN_MISC_PWRONCLKENCRYPTO_Pos  (11UL)                    /*!< PWRONCLKENCRYPTO (Bit 11)                             */
#define CLKGEN_MISC_PWRONCLKENCRYPTO_Msk  (0x800UL)                 /*!< PWRONCLKENCRYPTO (Bitfield-Mask: 0x01)                */
#define CLKGEN_MISC_PWRONCLKENSDIO_Pos    (10UL)                    /*!< PWRONCLKENSDIO (Bit 10)                               */
#define CLKGEN_MISC_PWRONCLKENSDIO_Msk    (0x400UL)                 /*!< PWRONCLKENSDIO (Bitfield-Mask: 0x01)                  */
#define CLKGEN_MISC_PWRONCLKENGFX_Pos     (8UL)                     /*!< PWRONCLKENGFX (Bit 8)                                 */
#define CLKGEN_MISC_PWRONCLKENGFX_Msk     (0x100UL)                 /*!< PWRONCLKENGFX (Bitfield-Mask: 0x01)                   */
#define CLKGEN_MISC_FRCHFRC2_Pos          (5UL)                     /*!< FRCHFRC2 (Bit 5)                                      */
#define CLKGEN_MISC_FRCHFRC2_Msk          (0x20UL)                  /*!< FRCHFRC2 (Bitfield-Mask: 0x01)                        */
#define CLKGEN_MISC_USEHFRC2FQ192MHZ_Pos  (4UL)                     /*!< USEHFRC2FQ192MHZ (Bit 4)                              */
#define CLKGEN_MISC_USEHFRC2FQ192MHZ_Msk  (0x10UL)                  /*!< USEHFRC2FQ192MHZ (Bitfield-Mask: 0x01)                */
#define CLKGEN_MISC_USEHFRC2FQ96MHZ_Pos   (3UL)                     /*!< USEHFRC2FQ96MHZ (Bit 3)                               */
#define CLKGEN_MISC_USEHFRC2FQ96MHZ_Msk   (0x8UL)                   /*!< USEHFRC2FQ96MHZ (Bitfield-Mask: 0x01)                 */
#define CLKGEN_MISC_USEHFRC2FQ48MHZ_Pos   (2UL)                     /*!< USEHFRC2FQ48MHZ (Bit 2)                               */
#define CLKGEN_MISC_USEHFRC2FQ48MHZ_Msk   (0x4UL)                   /*!< USEHFRC2FQ48MHZ (Bitfield-Mask: 0x01)                 */
#define CLKGEN_MISC_FRCBURSTOFF_Pos       (1UL)                     /*!< FRCBURSTOFF (Bit 1)                                   */
#define CLKGEN_MISC_FRCBURSTOFF_Msk       (0x2UL)                   /*!< FRCBURSTOFF (Bitfield-Mask: 0x01)                     */
#define CLKGEN_MISC_FRCHFRC_Pos           (0UL)                     /*!< FRCHFRC (Bit 0)                                       */
#define CLKGEN_MISC_FRCHFRC_Msk           (0x1UL)                   /*!< FRCHFRC (Bitfield-Mask: 0x01)                         */
/* ========================================================  HF2ADJ0  ======================================================== */
#define CLKGEN_HF2ADJ0_HF2ADJXTHSMUXSEL_Pos (29UL)                  /*!< HF2ADJXTHSMUXSEL (Bit 29)                             */
#define CLKGEN_HF2ADJ0_HF2ADJXTHSMUXSEL_Msk (0x20000000UL)          /*!< HF2ADJXTHSMUXSEL (Bitfield-Mask: 0x01)                */
#define CLKGEN_HF2ADJ0_HF2ADJCNTINOFFSET_Pos (15UL)                 /*!< HF2ADJCNTINOFFSET (Bit 15)                            */
#define CLKGEN_HF2ADJ0_HF2ADJCNTINOFFSET_Msk (0x1fff8000UL)         /*!< HF2ADJCNTINOFFSET (Bitfield-Mask: 0x3fff)             */
#define CLKGEN_HF2ADJ0_HF2ADJFASTSTRDLY_Pos (2UL)                   /*!< HF2ADJFASTSTRDLY (Bit 2)                              */
#define CLKGEN_HF2ADJ0_HF2ADJFASTSTRDLY_Msk (0x7ffcUL)              /*!< HF2ADJFASTSTRDLY (Bitfield-Mask: 0x1fff)              */
#define CLKGEN_HF2ADJ0_HF2ADJFASTSTREN_Pos (1UL)                    /*!< HF2ADJFASTSTREN (Bit 1)                               */
#define CLKGEN_HF2ADJ0_HF2ADJFASTSTREN_Msk (0x2UL)                  /*!< HF2ADJFASTSTREN (Bitfield-Mask: 0x01)                 */
#define CLKGEN_HF2ADJ0_HF2ADJEN_Pos       (0UL)                     /*!< HF2ADJEN (Bit 0)                                      */
#define CLKGEN_HF2ADJ0_HF2ADJEN_Msk       (0x1UL)                   /*!< HF2ADJEN (Bitfield-Mask: 0x01)                        */
/* ========================================================  HF2ADJ1  ======================================================== */
#define CLKGEN_HF2ADJ1_HF2ADJTRIMOFFSET_Pos (3UL)                   /*!< HF2ADJTRIMOFFSET (Bit 3)                              */
#define CLKGEN_HF2ADJ1_HF2ADJTRIMOFFSET_Msk (0x3ff8UL)              /*!< HF2ADJTRIMOFFSET (Bitfield-Mask: 0x7ff)               */
#define CLKGEN_HF2ADJ1_HF2ADJTRIMEN_Pos   (0UL)                     /*!< HF2ADJTRIMEN (Bit 0)                                  */
#define CLKGEN_HF2ADJ1_HF2ADJTRIMEN_Msk   (0x7UL)                   /*!< HF2ADJTRIMEN (Bitfield-Mask: 0x07)                    */
/* ========================================================  HF2ADJ2  ======================================================== */
#define CLKGEN_HF2ADJ2_HF2ADJRATIO_Pos    (2UL)                     /*!< HF2ADJRATIO (Bit 2)                                   */
#define CLKGEN_HF2ADJ2_HF2ADJRATIO_Msk    (0x7ffffffcUL)            /*!< HF2ADJRATIO (Bitfield-Mask: 0x1fffffff)               */
#define CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_Pos (0UL)                 /*!< HF2ADJXTALDIVRATIO (Bit 0)                            */
#define CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_Msk (0x3UL)               /*!< HF2ADJXTALDIVRATIO (Bitfield-Mask: 0x03)              */
/* ========================================================  HF2VAL  ========================================================= */
#define CLKGEN_HF2VAL_HF2ADJTRIMOUT_Pos   (0UL)                     /*!< HF2ADJTRIMOUT (Bit 0)                                 */
#define CLKGEN_HF2VAL_HF2ADJTRIMOUT_Msk   (0x7ffUL)                 /*!< HF2ADJTRIMOUT (Bitfield-Mask: 0x7ff)                  */
/* =======================================================  LFRCCTRL  ======================================================== */
#define CLKGEN_LFRCCTRL_LFRCPWD_Pos       (1UL)                     /*!< LFRCPWD (Bit 1)                                       */
#define CLKGEN_LFRCCTRL_LFRCPWD_Msk       (0x2UL)                   /*!< LFRCPWD (Bitfield-Mask: 0x01)                         */
#define CLKGEN_LFRCCTRL_LFRCOUT_Pos       (0UL)                     /*!< LFRCOUT (Bit 0)                                       */
#define CLKGEN_LFRCCTRL_LFRCOUT_Msk       (0x1UL)                   /*!< LFRCOUT (Bitfield-Mask: 0x01)                         */
/* ======================================================  DISPCLKCTRL  ====================================================== */
#define CLKGEN_DISPCLKCTRL_DISPCLKSEL_Pos (4UL)                     /*!< DISPCLKSEL (Bit 4)                                    */
#define CLKGEN_DISPCLKCTRL_DISPCLKSEL_Msk (0x30UL)                  /*!< DISPCLKSEL (Bitfield-Mask: 0x03)                      */
#define CLKGEN_DISPCLKCTRL_PLLCLKEN_Pos   (3UL)                     /*!< PLLCLKEN (Bit 3)                                      */
#define CLKGEN_DISPCLKCTRL_PLLCLKEN_Msk   (0x8UL)                   /*!< PLLCLKEN (Bitfield-Mask: 0x01)                        */
#define CLKGEN_DISPCLKCTRL_PLLCLKSEL_Pos  (0UL)                     /*!< PLLCLKSEL (Bit 0)                                     */
#define CLKGEN_DISPCLKCTRL_PLLCLKSEL_Msk  (0x3UL)                   /*!< PLLCLKSEL (Bitfield-Mask: 0x03)                       */
/* =====================================================  CLKGENSPARES  ====================================================== */
#define CLKGEN_CLKGENSPARES_CLKGENSPARES_Pos (0UL)                  /*!< CLKGENSPARES (Bit 0)                                  */
#define CLKGEN_CLKGENSPARES_CLKGENSPARES_Msk (0xffffffffUL)         /*!< CLKGENSPARES (Bitfield-Mask: 0xffffffff)              */
/* ===================================================  HFRCIDLECOUNTERS  ==================================================== */
#define CLKGEN_HFRCIDLECOUNTERS_UPDATEENABLE_Pos (31UL)             /*!< UPDATEENABLE (Bit 31)                                 */
#define CLKGEN_HFRCIDLECOUNTERS_UPDATEENABLE_Msk (0x80000000UL)     /*!< UPDATEENABLE (Bitfield-Mask: 0x01)                    */
#define CLKGEN_HFRCIDLECOUNTERS_HFRC2CLKREQDELAY_Pos (24UL)         /*!< HFRC2CLKREQDELAY (Bit 24)                             */
#define CLKGEN_HFRCIDLECOUNTERS_HFRC2CLKREQDELAY_Msk (0x3f000000UL) /*!< HFRC2CLKREQDELAY (Bitfield-Mask: 0x3f)                */
#define CLKGEN_HFRCIDLECOUNTERS_HFRC2PWRDOWNDELAY_Pos (16UL)        /*!< HFRC2PWRDOWNDELAY (Bit 16)                            */
#define CLKGEN_HFRCIDLECOUNTERS_HFRC2PWRDOWNDELAY_Msk (0x3f0000UL)  /*!< HFRC2PWRDOWNDELAY (Bitfield-Mask: 0x3f)               */
#define CLKGEN_HFRCIDLECOUNTERS_HFRCCLKREQDELAY_Pos (8UL)           /*!< HFRCCLKREQDELAY (Bit 8)                               */
#define CLKGEN_HFRCIDLECOUNTERS_HFRCCLKREQDELAY_Msk (0x3f00UL)      /*!< HFRCCLKREQDELAY (Bitfield-Mask: 0x3f)                 */
#define CLKGEN_HFRCIDLECOUNTERS_HFRCPWRDOWNDELAY_Pos (0UL)          /*!< HFRCPWRDOWNDELAY (Bit 0)                              */
#define CLKGEN_HFRCIDLECOUNTERS_HFRCPWRDOWNDELAY_Msk (0x3fUL)       /*!< HFRCPWRDOWNDELAY (Bitfield-Mask: 0x3f)                */
/* =======================================================  INTRPTEN  ======================================================== */
#define CLKGEN_INTRPTEN_OF_Pos            (0UL)                     /*!< OF (Bit 0)                                            */
#define CLKGEN_INTRPTEN_OF_Msk            (0x1UL)                   /*!< OF (Bitfield-Mask: 0x01)                              */
/* ======================================================  INTRPTSTAT  ======================================================= */
#define CLKGEN_INTRPTSTAT_OF_Pos          (0UL)                     /*!< OF (Bit 0)                                            */
#define CLKGEN_INTRPTSTAT_OF_Msk          (0x1UL)                   /*!< OF (Bitfield-Mask: 0x01)                              */
/* =======================================================  INTRPTCLR  ======================================================= */
#define CLKGEN_INTRPTCLR_OF_Pos           (0UL)                     /*!< OF (Bit 0)                                            */
#define CLKGEN_INTRPTCLR_OF_Msk           (0x1UL)                   /*!< OF (Bitfield-Mask: 0x01)                              */
/* =======================================================  INTRPTSET  ======================================================= */
#define CLKGEN_INTRPTSET_OF_Pos           (0UL)                     /*!< OF (Bit 0)                                            */
#define CLKGEN_INTRPTSET_OF_Msk           (0x1UL)                   /*!< OF (Bitfield-Mask: 0x01)                              */


/* =========================================================================================================================== */
/* ================                                            CPU                                            ================ */
/* =========================================================================================================================== */

/* =======================================================  CACHECFG  ======================================================== */
#define CPU_CACHECFG_ENABLEMONITOR_Pos    (24UL)                    /*!< ENABLEMONITOR (Bit 24)                                */
#define CPU_CACHECFG_ENABLEMONITOR_Msk    (0x1000000UL)             /*!< ENABLEMONITOR (Bitfield-Mask: 0x01)                   */
#define CPU_CACHECFG_DATACLKGATE_Pos      (20UL)                    /*!< DATACLKGATE (Bit 20)                                  */
#define CPU_CACHECFG_DATACLKGATE_Msk      (0x100000UL)              /*!< DATACLKGATE (Bitfield-Mask: 0x01)                     */
#define CPU_CACHECFG_NC0CACHELOCK_Pos     (13UL)                    /*!< NC0CACHELOCK (Bit 13)                                 */
#define CPU_CACHECFG_NC0CACHELOCK_Msk     (0x2000UL)                /*!< NC0CACHELOCK (Bitfield-Mask: 0x01)                    */
#define CPU_CACHECFG_NC1CACHELOCK_Pos     (12UL)                    /*!< NC1CACHELOCK (Bit 12)                                 */
#define CPU_CACHECFG_NC1CACHELOCK_Msk     (0x1000UL)                /*!< NC1CACHELOCK (Bitfield-Mask: 0x01)                    */
#define CPU_CACHECFG_LS_Pos               (11UL)                    /*!< LS (Bit 11)                                           */
#define CPU_CACHECFG_LS_Msk               (0x800UL)                 /*!< LS (Bitfield-Mask: 0x01)                              */
#define CPU_CACHECFG_CLKGATE_Pos          (10UL)                    /*!< CLKGATE (Bit 10)                                      */
#define CPU_CACHECFG_CLKGATE_Msk          (0x400UL)                 /*!< CLKGATE (Bitfield-Mask: 0x01)                         */
#define CPU_CACHECFG_DENABLE_Pos          (9UL)                     /*!< DENABLE (Bit 9)                                       */
#define CPU_CACHECFG_DENABLE_Msk          (0x200UL)                 /*!< DENABLE (Bitfield-Mask: 0x01)                         */
#define CPU_CACHECFG_IENABLE_Pos          (8UL)                     /*!< IENABLE (Bit 8)                                       */
#define CPU_CACHECFG_IENABLE_Msk          (0x100UL)                 /*!< IENABLE (Bitfield-Mask: 0x01)                         */
#define CPU_CACHECFG_CONFIG_Pos           (4UL)                     /*!< CONFIG (Bit 4)                                        */
#define CPU_CACHECFG_CONFIG_Msk           (0xf0UL)                  /*!< CONFIG (Bitfield-Mask: 0x0f)                          */
#define CPU_CACHECFG_NC1ENABLE_Pos        (3UL)                     /*!< NC1ENABLE (Bit 3)                                     */
#define CPU_CACHECFG_NC1ENABLE_Msk        (0x8UL)                   /*!< NC1ENABLE (Bitfield-Mask: 0x01)                       */
#define CPU_CACHECFG_NC0ENABLE_Pos        (2UL)                     /*!< NC0ENABLE (Bit 2)                                     */
#define CPU_CACHECFG_NC0ENABLE_Msk        (0x4UL)                   /*!< NC0ENABLE (Bitfield-Mask: 0x01)                       */
#define CPU_CACHECFG_LRU_Pos              (1UL)                     /*!< LRU (Bit 1)                                           */
#define CPU_CACHECFG_LRU_Msk              (0x2UL)                   /*!< LRU (Bitfield-Mask: 0x01)                             */
#define CPU_CACHECFG_ENABLE_Pos           (0UL)                     /*!< ENABLE (Bit 0)                                        */
#define CPU_CACHECFG_ENABLE_Msk           (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
/* =======================================================  CACHECTRL  ======================================================= */
#define CPU_CACHECTRL_CACHEREADY_Pos      (2UL)                     /*!< CACHEREADY (Bit 2)                                    */
#define CPU_CACHECTRL_CACHEREADY_Msk      (0x4UL)                   /*!< CACHEREADY (Bitfield-Mask: 0x01)                      */
#define CPU_CACHECTRL_RESETSTAT_Pos       (1UL)                     /*!< RESETSTAT (Bit 1)                                     */
#define CPU_CACHECTRL_RESETSTAT_Msk       (0x2UL)                   /*!< RESETSTAT (Bitfield-Mask: 0x01)                       */
#define CPU_CACHECTRL_INVALIDATE_Pos      (0UL)                     /*!< INVALIDATE (Bit 0)                                    */
#define CPU_CACHECTRL_INVALIDATE_Msk      (0x1UL)                   /*!< INVALIDATE (Bitfield-Mask: 0x01)                      */
/* =======================================================  NCR0START  ======================================================= */
#define CPU_NCR0START_ADDR_Pos            (4UL)                     /*!< ADDR (Bit 4)                                          */
#define CPU_NCR0START_ADDR_Msk            (0x1ffffff0UL)            /*!< ADDR (Bitfield-Mask: 0x1ffffff)                       */
/* ========================================================  NCR0END  ======================================================== */
#define CPU_NCR0END_ADDR_Pos              (4UL)                     /*!< ADDR (Bit 4)                                          */
#define CPU_NCR0END_ADDR_Msk              (0x1ffffff0UL)            /*!< ADDR (Bitfield-Mask: 0x1ffffff)                       */
/* =======================================================  NCR1START  ======================================================= */
#define CPU_NCR1START_ADDR_Pos            (4UL)                     /*!< ADDR (Bit 4)                                          */
#define CPU_NCR1START_ADDR_Msk            (0x1ffffff0UL)            /*!< ADDR (Bitfield-Mask: 0x1ffffff)                       */
/* ========================================================  NCR1END  ======================================================== */
#define CPU_NCR1END_ADDR_Pos              (4UL)                     /*!< ADDR (Bit 4)                                          */
#define CPU_NCR1END_ADDR_Msk              (0x1ffffff0UL)            /*!< ADDR (Bitfield-Mask: 0x1ffffff)                       */
/* ========================================================  DAXICFG  ======================================================== */
#define CPU_DAXICFG_MRUGROUPLEVEL_Pos     (24UL)                    /*!< MRUGROUPLEVEL (Bit 24)                                */
#define CPU_DAXICFG_MRUGROUPLEVEL_Msk     (0x3000000UL)             /*!< MRUGROUPLEVEL (Bitfield-Mask: 0x03)                   */
#define CPU_DAXICFG_AGINGCOUNTER_Pos      (16UL)                    /*!< AGINGCOUNTER (Bit 16)                                 */
#define CPU_DAXICFG_AGINGCOUNTER_Msk      (0x1f0000UL)              /*!< AGINGCOUNTER (Bitfield-Mask: 0x1f)                    */
#define CPU_DAXICFG_BUFFERENABLE_Pos      (8UL)                     /*!< BUFFERENABLE (Bit 8)                                  */
#define CPU_DAXICFG_BUFFERENABLE_Msk      (0xf00UL)                 /*!< BUFFERENABLE (Bitfield-Mask: 0x0f)                    */
#define CPU_DAXICFG_DAXISTATECLKGATEEN_Pos (5UL)                    /*!< DAXISTATECLKGATEEN (Bit 5)                            */
#define CPU_DAXICFG_DAXISTATECLKGATEEN_Msk (0x20UL)                 /*!< DAXISTATECLKGATEEN (Bitfield-Mask: 0x01)              */
#define CPU_DAXICFG_DAXIDATACLKGATEEN_Pos (4UL)                     /*!< DAXIDATACLKGATEEN (Bit 4)                             */
#define CPU_DAXICFG_DAXIDATACLKGATEEN_Msk (0x10UL)                  /*!< DAXIDATACLKGATEEN (Bitfield-Mask: 0x01)               */
#define CPU_DAXICFG_DAXIBECLKGATEEN_Pos   (3UL)                     /*!< DAXIBECLKGATEEN (Bit 3)                               */
#define CPU_DAXICFG_DAXIBECLKGATEEN_Msk   (0x8UL)                   /*!< DAXIBECLKGATEEN (Bitfield-Mask: 0x01)                 */
#define CPU_DAXICFG_DAXIPASSTHROUGH_Pos   (2UL)                     /*!< DAXIPASSTHROUGH (Bit 2)                               */
#define CPU_DAXICFG_DAXIPASSTHROUGH_Msk   (0x4UL)                   /*!< DAXIPASSTHROUGH (Bitfield-Mask: 0x01)                 */
#define CPU_DAXICFG_AGINGSENABLE_Pos      (1UL)                     /*!< AGINGSENABLE (Bit 1)                                  */
#define CPU_DAXICFG_AGINGSENABLE_Msk      (0x2UL)                   /*!< AGINGSENABLE (Bitfield-Mask: 0x01)                    */
#define CPU_DAXICFG_FLUSHLEVEL_Pos        (0UL)                     /*!< FLUSHLEVEL (Bit 0)                                    */
#define CPU_DAXICFG_FLUSHLEVEL_Msk        (0x1UL)                   /*!< FLUSHLEVEL (Bitfield-Mask: 0x01)                      */
/* =======================================================  DAXICTRL  ======================================================== */
#define CPU_DAXICTRL_DAXIRAXIBUSY_Pos     (12UL)                    /*!< DAXIRAXIBUSY (Bit 12)                                 */
#define CPU_DAXICTRL_DAXIRAXIBUSY_Msk     (0x1000UL)                /*!< DAXIRAXIBUSY (Bitfield-Mask: 0x01)                    */
#define CPU_DAXICTRL_DAXIBRESPPENDING_Pos (11UL)                    /*!< DAXIBRESPPENDING (Bit 11)                             */
#define CPU_DAXICTRL_DAXIBRESPPENDING_Msk (0x800UL)                 /*!< DAXIBRESPPENDING (Bitfield-Mask: 0x01)                */
#define CPU_DAXICTRL_DAXISTORE_Pos        (10UL)                    /*!< DAXISTORE (Bit 10)                                    */
#define CPU_DAXICTRL_DAXISTORE_Msk        (0x400UL)                 /*!< DAXISTORE (Bitfield-Mask: 0x01)                       */
#define CPU_DAXICTRL_DAXIWRLOAD_Pos       (9UL)                     /*!< DAXIWRLOAD (Bit 9)                                    */
#define CPU_DAXICTRL_DAXIWRLOAD_Msk       (0x200UL)                 /*!< DAXIWRLOAD (Bitfield-Mask: 0x01)                      */
#define CPU_DAXICTRL_DAXIWALLOC_Pos       (8UL)                     /*!< DAXIWALLOC (Bit 8)                                    */
#define CPU_DAXICTRL_DAXIWALLOC_Msk       (0x100UL)                 /*!< DAXIWALLOC (Bitfield-Mask: 0x01)                      */
#define CPU_DAXICTRL_DAXIWRITE_Pos        (7UL)                     /*!< DAXIWRITE (Bit 7)                                     */
#define CPU_DAXICTRL_DAXIWRITE_Msk        (0x80UL)                  /*!< DAXIWRITE (Bitfield-Mask: 0x01)                       */
#define CPU_DAXICTRL_DAXIMODIFIED_Pos     (6UL)                     /*!< DAXIMODIFIED (Bit 6)                                  */
#define CPU_DAXICTRL_DAXIMODIFIED_Msk     (0x40UL)                  /*!< DAXIMODIFIED (Bitfield-Mask: 0x01)                    */
#define CPU_DAXICTRL_DAXISHARED_Pos       (5UL)                     /*!< DAXISHARED (Bit 5)                                    */
#define CPU_DAXICTRL_DAXISHARED_Msk       (0x20UL)                  /*!< DAXISHARED (Bitfield-Mask: 0x01)                      */
#define CPU_DAXICTRL_DAXIAHBBUSY_Pos      (4UL)                     /*!< DAXIAHBBUSY (Bit 4)                                   */
#define CPU_DAXICTRL_DAXIAHBBUSY_Msk      (0x10UL)                  /*!< DAXIAHBBUSY (Bitfield-Mask: 0x01)                     */
#define CPU_DAXICTRL_DAXIBUSY_Pos         (3UL)                     /*!< DAXIBUSY (Bit 3)                                      */
#define CPU_DAXICTRL_DAXIBUSY_Msk         (0x8UL)                   /*!< DAXIBUSY (Bitfield-Mask: 0x01)                        */
#define CPU_DAXICTRL_DAXIREADY_Pos        (2UL)                     /*!< DAXIREADY (Bit 2)                                     */
#define CPU_DAXICTRL_DAXIREADY_Msk        (0x4UL)                   /*!< DAXIREADY (Bitfield-Mask: 0x01)                       */
#define CPU_DAXICTRL_DAXIINVALIDATE_Pos   (1UL)                     /*!< DAXIINVALIDATE (Bit 1)                                */
#define CPU_DAXICTRL_DAXIINVALIDATE_Msk   (0x2UL)                   /*!< DAXIINVALIDATE (Bitfield-Mask: 0x01)                  */
#define CPU_DAXICTRL_DAXIFLUSHWRITE_Pos   (0UL)                     /*!< DAXIFLUSHWRITE (Bit 0)                                */
#define CPU_DAXICTRL_DAXIFLUSHWRITE_Msk   (0x1UL)                   /*!< DAXIFLUSHWRITE (Bitfield-Mask: 0x01)                  */
/* ====================================================  ICODEFAULTADDR  ===================================================== */
#define CPU_ICODEFAULTADDR_ICODEFAULTADDR_Pos (0UL)                 /*!< ICODEFAULTADDR (Bit 0)                                */
#define CPU_ICODEFAULTADDR_ICODEFAULTADDR_Msk (0xffffffffUL)        /*!< ICODEFAULTADDR (Bitfield-Mask: 0xffffffff)            */
/* ====================================================  DCODEFAULTADDR  ===================================================== */
#define CPU_DCODEFAULTADDR_DCODEFAULTADDR_Pos (0UL)                 /*!< DCODEFAULTADDR (Bit 0)                                */
#define CPU_DCODEFAULTADDR_DCODEFAULTADDR_Msk (0xffffffffUL)        /*!< DCODEFAULTADDR (Bitfield-Mask: 0xffffffff)            */
/* =====================================================  SYSFAULTADDR  ====================================================== */
#define CPU_SYSFAULTADDR_SYSFAULTADDR_Pos (0UL)                     /*!< SYSFAULTADDR (Bit 0)                                  */
#define CPU_SYSFAULTADDR_SYSFAULTADDR_Msk (0xffffffffUL)            /*!< SYSFAULTADDR (Bitfield-Mask: 0xffffffff)              */
/* ======================================================  FAULTSTATUS  ====================================================== */
#define CPU_FAULTSTATUS_SYSFAULT_Pos      (2UL)                     /*!< SYSFAULT (Bit 2)                                      */
#define CPU_FAULTSTATUS_SYSFAULT_Msk      (0x4UL)                   /*!< SYSFAULT (Bitfield-Mask: 0x01)                        */
#define CPU_FAULTSTATUS_DCODEFAULT_Pos    (1UL)                     /*!< DCODEFAULT (Bit 1)                                    */
#define CPU_FAULTSTATUS_DCODEFAULT_Msk    (0x2UL)                   /*!< DCODEFAULT (Bitfield-Mask: 0x01)                      */
#define CPU_FAULTSTATUS_ICODEFAULT_Pos    (0UL)                     /*!< ICODEFAULT (Bit 0)                                    */
#define CPU_FAULTSTATUS_ICODEFAULT_Msk    (0x1UL)                   /*!< ICODEFAULT (Bitfield-Mask: 0x01)                      */
/* ====================================================  FAULTCAPTUREEN  ===================================================== */
#define CPU_FAULTCAPTUREEN_FAULTCAPTUREEN_Pos (0UL)                 /*!< FAULTCAPTUREEN (Bit 0)                                */
#define CPU_FAULTCAPTUREEN_FAULTCAPTUREEN_Msk (0x1UL)               /*!< FAULTCAPTUREEN (Bitfield-Mask: 0x01)                  */
/* =========================================================  INTEN  ========================================================= */
#define CPU_INTEN_AXIWERROR_Pos           (0UL)                     /*!< AXIWERROR (Bit 0)                                     */
#define CPU_INTEN_AXIWERROR_Msk           (0x1UL)                   /*!< AXIWERROR (Bitfield-Mask: 0x01)                       */
/* ========================================================  INTSTAT  ======================================================== */
#define CPU_INTSTAT_AXIWERROR_Pos         (0UL)                     /*!< AXIWERROR (Bit 0)                                     */
#define CPU_INTSTAT_AXIWERROR_Msk         (0x1UL)                   /*!< AXIWERROR (Bitfield-Mask: 0x01)                       */
/* ========================================================  INTCLR  ========================================================= */
#define CPU_INTCLR_AXIWERROR_Pos          (0UL)                     /*!< AXIWERROR (Bit 0)                                     */
#define CPU_INTCLR_AXIWERROR_Msk          (0x1UL)                   /*!< AXIWERROR (Bitfield-Mask: 0x01)                       */
/* ========================================================  INTSET  ========================================================= */
#define CPU_INTSET_AXIWERROR_Pos          (0UL)                     /*!< AXIWERROR (Bit 0)                                     */
#define CPU_INTSET_AXIWERROR_Msk          (0x1UL)                   /*!< AXIWERROR (Bitfield-Mask: 0x01)                       */
/* =====================================================  WRITEERRADDR  ====================================================== */
#define CPU_WRITEERRADDR_WERRADDR_Pos     (0UL)                     /*!< WERRADDR (Bit 0)                                      */
#define CPU_WRITEERRADDR_WERRADDR_Msk     (0xffffffffUL)            /*!< WERRADDR (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  DMON0  ========================================================= */
#define CPU_DMON0_DACCESS_Pos             (0UL)                     /*!< DACCESS (Bit 0)                                       */
#define CPU_DMON0_DACCESS_Msk             (0xffffffffUL)            /*!< DACCESS (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  DMON1  ========================================================= */
#define CPU_DMON1_DLOOKUP_Pos             (0UL)                     /*!< DLOOKUP (Bit 0)                                       */
#define CPU_DMON1_DLOOKUP_Msk             (0xffffffffUL)            /*!< DLOOKUP (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  DMON2  ========================================================= */
#define CPU_DMON2_DHIT_Pos                (0UL)                     /*!< DHIT (Bit 0)                                          */
#define CPU_DMON2_DHIT_Msk                (0xffffffffUL)            /*!< DHIT (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  DMON3  ========================================================= */
#define CPU_DMON3_DLINE_Pos               (0UL)                     /*!< DLINE (Bit 0)                                         */
#define CPU_DMON3_DLINE_Msk               (0xffffffffUL)            /*!< DLINE (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  IMON0  ========================================================= */
#define CPU_IMON0_IACCESS_Pos             (0UL)                     /*!< IACCESS (Bit 0)                                       */
#define CPU_IMON0_IACCESS_Msk             (0xffffffffUL)            /*!< IACCESS (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  IMON1  ========================================================= */
#define CPU_IMON1_ILOOKUP_Pos             (0UL)                     /*!< ILOOKUP (Bit 0)                                       */
#define CPU_IMON1_ILOOKUP_Msk             (0xffffffffUL)            /*!< ILOOKUP (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  IMON2  ========================================================= */
#define CPU_IMON2_IHIT_Pos                (0UL)                     /*!< IHIT (Bit 0)                                          */
#define CPU_IMON2_IHIT_Msk                (0xffffffffUL)            /*!< IHIT (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  IMON3  ========================================================= */
#define CPU_IMON3_ILINE_Pos               (0UL)                     /*!< ILINE (Bit 0)                                         */
#define CPU_IMON3_ILINE_Msk               (0xffffffffUL)            /*!< ILINE (Bitfield-Mask: 0xffffffff)                     */


/* =========================================================================================================================== */
/* ================                                          CRYPTO                                           ================ */
/* =========================================================================================================================== */

/* ======================================================  MEMORYMAP0  ======================================================= */
#define CRYPTO_MEMORYMAP0_PHYSADDRMAP0_Pos (1UL)                    /*!< PHYSADDRMAP0 (Bit 1)                                  */
#define CRYPTO_MEMORYMAP0_PHYSADDRMAP0_Msk (0x7feUL)                /*!< PHYSADDRMAP0 (Bitfield-Mask: 0x3ff)                   */
/* ======================================================  MEMORYMAP1  ======================================================= */
#define CRYPTO_MEMORYMAP1_PHYSADDRMAP1_Pos (1UL)                    /*!< PHYSADDRMAP1 (Bit 1)                                  */
#define CRYPTO_MEMORYMAP1_PHYSADDRMAP1_Msk (0x7feUL)                /*!< PHYSADDRMAP1 (Bitfield-Mask: 0x3ff)                   */
/* ======================================================  MEMORYMAP2  ======================================================= */
#define CRYPTO_MEMORYMAP2_PHYSADDRMAP2_Pos (1UL)                    /*!< PHYSADDRMAP2 (Bit 1)                                  */
#define CRYPTO_MEMORYMAP2_PHYSADDRMAP2_Msk (0x7feUL)                /*!< PHYSADDRMAP2 (Bitfield-Mask: 0x3ff)                   */
/* ======================================================  MEMORYMAP3  ======================================================= */
#define CRYPTO_MEMORYMAP3_PHYSADDRMAP3_Pos (1UL)                    /*!< PHYSADDRMAP3 (Bit 1)                                  */
#define CRYPTO_MEMORYMAP3_PHYSADDRMAP3_Msk (0x7feUL)                /*!< PHYSADDRMAP3 (Bitfield-Mask: 0x3ff)                   */
/* ======================================================  MEMORYMAP4  ======================================================= */
#define CRYPTO_MEMORYMAP4_PHYSADDRMAP4_Pos (1UL)                    /*!< PHYSADDRMAP4 (Bit 1)                                  */
#define CRYPTO_MEMORYMAP4_PHYSADDRMAP4_Msk (0x7feUL)                /*!< PHYSADDRMAP4 (Bitfield-Mask: 0x3ff)                   */
/* ======================================================  MEMORYMAP5  ======================================================= */
#define CRYPTO_MEMORYMAP5_PHYSADDRMAP5_Pos (1UL)                    /*!< PHYSADDRMAP5 (Bit 1)                                  */
#define CRYPTO_MEMORYMAP5_PHYSADDRMAP5_Msk (0x7feUL)                /*!< PHYSADDRMAP5 (Bitfield-Mask: 0x3ff)                   */
/* ======================================================  MEMORYMAP6  ======================================================= */
#define CRYPTO_MEMORYMAP6_PHYSADDRMAP6_Pos (1UL)                    /*!< PHYSADDRMAP6 (Bit 1)                                  */
#define CRYPTO_MEMORYMAP6_PHYSADDRMAP6_Msk (0x7feUL)                /*!< PHYSADDRMAP6 (Bitfield-Mask: 0x3ff)                   */
/* ======================================================  MEMORYMAP7  ======================================================= */
#define CRYPTO_MEMORYMAP7_PHYSADDRMAP7_Pos (1UL)                    /*!< PHYSADDRMAP7 (Bit 1)                                  */
#define CRYPTO_MEMORYMAP7_PHYSADDRMAP7_Msk (0x7feUL)                /*!< PHYSADDRMAP7 (Bitfield-Mask: 0x3ff)                   */
/* ======================================================  MEMORYMAP8  ======================================================= */
#define CRYPTO_MEMORYMAP8_PHYSADDRMAP8_Pos (1UL)                    /*!< PHYSADDRMAP8 (Bit 1)                                  */
#define CRYPTO_MEMORYMAP8_PHYSADDRMAP8_Msk (0x7feUL)                /*!< PHYSADDRMAP8 (Bitfield-Mask: 0x3ff)                   */
/* ======================================================  MEMORYMAP9  ======================================================= */
#define CRYPTO_MEMORYMAP9_PHYSADDRMAP9_Pos (1UL)                    /*!< PHYSADDRMAP9 (Bit 1)                                  */
#define CRYPTO_MEMORYMAP9_PHYSADDRMAP9_Msk (0x7feUL)                /*!< PHYSADDRMAP9 (Bitfield-Mask: 0x3ff)                   */
/* ======================================================  MEMORYMAP10  ====================================================== */
#define CRYPTO_MEMORYMAP10_PHYSADDRMAP10_Pos (1UL)                  /*!< PHYSADDRMAP10 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP10_PHYSADDRMAP10_Msk (0x7feUL)              /*!< PHYSADDRMAP10 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP11  ====================================================== */
#define CRYPTO_MEMORYMAP11_PHYSADDRMAP11_Pos (1UL)                  /*!< PHYSADDRMAP11 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP11_PHYSADDRMAP11_Msk (0x7feUL)              /*!< PHYSADDRMAP11 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP12  ====================================================== */
#define CRYPTO_MEMORYMAP12_PHYSADDRMAP12_Pos (1UL)                  /*!< PHYSADDRMAP12 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP12_PHYSADDRMAP12_Msk (0x7feUL)              /*!< PHYSADDRMAP12 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP13  ====================================================== */
#define CRYPTO_MEMORYMAP13_PHYSADDRMAP13_Pos (1UL)                  /*!< PHYSADDRMAP13 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP13_PHYSADDRMAP13_Msk (0x7feUL)              /*!< PHYSADDRMAP13 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP14  ====================================================== */
#define CRYPTO_MEMORYMAP14_PHYSADDRMAP14_Pos (1UL)                  /*!< PHYSADDRMAP14 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP14_PHYSADDRMAP14_Msk (0x7feUL)              /*!< PHYSADDRMAP14 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP15  ====================================================== */
#define CRYPTO_MEMORYMAP15_PHYSADDRMAP15_Pos (1UL)                  /*!< PHYSADDRMAP15 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP15_PHYSADDRMAP15_Msk (0x7feUL)              /*!< PHYSADDRMAP15 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP16  ====================================================== */
#define CRYPTO_MEMORYMAP16_PHYSADDRMAP16_Pos (1UL)                  /*!< PHYSADDRMAP16 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP16_PHYSADDRMAP16_Msk (0x7feUL)              /*!< PHYSADDRMAP16 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP17  ====================================================== */
#define CRYPTO_MEMORYMAP17_PHYSADDRMAP17_Pos (1UL)                  /*!< PHYSADDRMAP17 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP17_PHYSADDRMAP17_Msk (0x7feUL)              /*!< PHYSADDRMAP17 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP18  ====================================================== */
#define CRYPTO_MEMORYMAP18_PHYSADDRMAP18_Pos (1UL)                  /*!< PHYSADDRMAP18 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP18_PHYSADDRMAP18_Msk (0x7feUL)              /*!< PHYSADDRMAP18 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP19  ====================================================== */
#define CRYPTO_MEMORYMAP19_PHYSADDRMAP19_Pos (1UL)                  /*!< PHYSADDRMAP19 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP19_PHYSADDRMAP19_Msk (0x7feUL)              /*!< PHYSADDRMAP19 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP20  ====================================================== */
#define CRYPTO_MEMORYMAP20_PHYSADDRMAP20_Pos (1UL)                  /*!< PHYSADDRMAP20 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP20_PHYSADDRMAP20_Msk (0x7feUL)              /*!< PHYSADDRMAP20 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP21  ====================================================== */
#define CRYPTO_MEMORYMAP21_PHYSADDRMAP21_Pos (1UL)                  /*!< PHYSADDRMAP21 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP21_PHYSADDRMAP21_Msk (0x7feUL)              /*!< PHYSADDRMAP21 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP22  ====================================================== */
#define CRYPTO_MEMORYMAP22_PHYSADDRMAP22_Pos (1UL)                  /*!< PHYSADDRMAP22 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP22_PHYSADDRMAP22_Msk (0x7feUL)              /*!< PHYSADDRMAP22 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP23  ====================================================== */
#define CRYPTO_MEMORYMAP23_PHYSADDRMAP23_Pos (1UL)                  /*!< PHYSADDRMAP23 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP23_PHYSADDRMAP23_Msk (0x7feUL)              /*!< PHYSADDRMAP23 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP24  ====================================================== */
#define CRYPTO_MEMORYMAP24_PHYSADDRMAP24_Pos (1UL)                  /*!< PHYSADDRMAP24 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP24_PHYSADDRMAP24_Msk (0x7feUL)              /*!< PHYSADDRMAP24 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP25  ====================================================== */
#define CRYPTO_MEMORYMAP25_PHYSADDRMAP25_Pos (1UL)                  /*!< PHYSADDRMAP25 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP25_PHYSADDRMAP25_Msk (0x7feUL)              /*!< PHYSADDRMAP25 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP26  ====================================================== */
#define CRYPTO_MEMORYMAP26_PHYSADDRMAP26_Pos (1UL)                  /*!< PHYSADDRMAP26 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP26_PHYSADDRMAP26_Msk (0x7feUL)              /*!< PHYSADDRMAP26 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP27  ====================================================== */
#define CRYPTO_MEMORYMAP27_PHYSADDRMAP27_Pos (1UL)                  /*!< PHYSADDRMAP27 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP27_PHYSADDRMAP27_Msk (0x7feUL)              /*!< PHYSADDRMAP27 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP28  ====================================================== */
#define CRYPTO_MEMORYMAP28_PHYSADDRMAP28_Pos (1UL)                  /*!< PHYSADDRMAP28 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP28_PHYSADDRMAP28_Msk (0x7feUL)              /*!< PHYSADDRMAP28 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP29  ====================================================== */
#define CRYPTO_MEMORYMAP29_PHYSADDRMAP29_Pos (1UL)                  /*!< PHYSADDRMAP29 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP29_PHYSADDRMAP29_Msk (0x7feUL)              /*!< PHYSADDRMAP29 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP30  ====================================================== */
#define CRYPTO_MEMORYMAP30_PHYSADDRMAP30_Pos (1UL)                  /*!< PHYSADDRMAP30 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP30_PHYSADDRMAP30_Msk (0x7feUL)              /*!< PHYSADDRMAP30 (Bitfield-Mask: 0x3ff)                  */
/* ======================================================  MEMORYMAP31  ====================================================== */
#define CRYPTO_MEMORYMAP31_PHYSADDRMAP31_Pos (1UL)                  /*!< PHYSADDRMAP31 (Bit 1)                                 */
#define CRYPTO_MEMORYMAP31_PHYSADDRMAP31_Msk (0x7feUL)              /*!< PHYSADDRMAP31 (Bitfield-Mask: 0x3ff)                  */
/* ========================================================  OPCODE  ========================================================= */
#define CRYPTO_OPCODE_OPCODE_Pos          (27UL)                    /*!< OPCODE (Bit 27)                                       */
#define CRYPTO_OPCODE_OPCODE_Msk          (0xf8000000UL)            /*!< OPCODE (Bitfield-Mask: 0x1f)                          */
#define CRYPTO_OPCODE_LEN_Pos             (24UL)                    /*!< LEN (Bit 24)                                          */
#define CRYPTO_OPCODE_LEN_Msk             (0x7000000UL)             /*!< LEN (Bitfield-Mask: 0x07)                             */
#define CRYPTO_OPCODE_REGA_Pos            (18UL)                    /*!< REGA (Bit 18)                                         */
#define CRYPTO_OPCODE_REGA_Msk            (0xfc0000UL)              /*!< REGA (Bitfield-Mask: 0x3f)                            */
#define CRYPTO_OPCODE_REGB_Pos            (12UL)                    /*!< REGB (Bit 12)                                         */
#define CRYPTO_OPCODE_REGB_Msk            (0x3f000UL)               /*!< REGB (Bitfield-Mask: 0x3f)                            */
#define CRYPTO_OPCODE_REGR_Pos            (6UL)                     /*!< REGR (Bit 6)                                          */
#define CRYPTO_OPCODE_REGR_Msk            (0xfc0UL)                 /*!< REGR (Bitfield-Mask: 0x3f)                            */
#define CRYPTO_OPCODE_TAG_Pos             (0UL)                     /*!< TAG (Bit 0)                                           */
#define CRYPTO_OPCODE_TAG_Msk             (0x3fUL)                  /*!< TAG (Bitfield-Mask: 0x3f)                             */
/* ======================================================  NNPT0T1ADDR  ====================================================== */
#define CRYPTO_NNPT0T1ADDR_T1VIRTUALADDR_Pos (15UL)                 /*!< T1VIRTUALADDR (Bit 15)                                */
#define CRYPTO_NNPT0T1ADDR_T1VIRTUALADDR_Msk (0xf8000UL)            /*!< T1VIRTUALADDR (Bitfield-Mask: 0x1f)                   */
#define CRYPTO_NNPT0T1ADDR_T0VIRTUALADDR_Pos (10UL)                 /*!< T0VIRTUALADDR (Bit 10)                                */
#define CRYPTO_NNPT0T1ADDR_T0VIRTUALADDR_Msk (0x7c00UL)             /*!< T0VIRTUALADDR (Bitfield-Mask: 0x1f)                   */
#define CRYPTO_NNPT0T1ADDR_NPVIRTUALADDR_Pos (5UL)                  /*!< NPVIRTUALADDR (Bit 5)                                 */
#define CRYPTO_NNPT0T1ADDR_NPVIRTUALADDR_Msk (0x3e0UL)              /*!< NPVIRTUALADDR (Bitfield-Mask: 0x1f)                   */
#define CRYPTO_NNPT0T1ADDR_NVIRTUALADDR_Pos (0UL)                   /*!< NVIRTUALADDR (Bit 0)                                  */
#define CRYPTO_NNPT0T1ADDR_NVIRTUALADDR_Msk (0x1fUL)                /*!< NVIRTUALADDR (Bitfield-Mask: 0x1f)                    */
/* =======================================================  PKASTATUS  ======================================================= */
#define CRYPTO_PKASTATUS_OPCODE_Pos       (16UL)                    /*!< OPCODE (Bit 16)                                       */
#define CRYPTO_PKASTATUS_OPCODE_Msk       (0x1f0000UL)              /*!< OPCODE (Bitfield-Mask: 0x1f)                          */
#define CRYPTO_PKASTATUS_MODINVOFZERO_Pos (15UL)                    /*!< MODINVOFZERO (Bit 15)                                 */
#define CRYPTO_PKASTATUS_MODINVOFZERO_Msk (0x8000UL)                /*!< MODINVOFZERO (Bitfield-Mask: 0x01)                    */
#define CRYPTO_PKASTATUS_DIVBYZERO_Pos    (14UL)                    /*!< DIVBYZERO (Bit 14)                                    */
#define CRYPTO_PKASTATUS_DIVBYZERO_Msk    (0x4000UL)                /*!< DIVBYZERO (Bitfield-Mask: 0x01)                       */
#define CRYPTO_PKASTATUS_ALUMODOVRFLW_Pos (13UL)                    /*!< ALUMODOVRFLW (Bit 13)                                 */
#define CRYPTO_PKASTATUS_ALUMODOVRFLW_Msk (0x2000UL)                /*!< ALUMODOVRFLW (Bitfield-Mask: 0x01)                    */
#define CRYPTO_PKASTATUS_ALUOUTZERO_Pos   (12UL)                    /*!< ALUOUTZERO (Bit 12)                                   */
#define CRYPTO_PKASTATUS_ALUOUTZERO_Msk   (0x1000UL)                /*!< ALUOUTZERO (Bitfield-Mask: 0x01)                      */
#define CRYPTO_PKASTATUS_ALUSUBISZERO_Pos (11UL)                    /*!< ALUSUBISZERO (Bit 11)                                 */
#define CRYPTO_PKASTATUS_ALUSUBISZERO_Msk (0x800UL)                 /*!< ALUSUBISZERO (Bitfield-Mask: 0x01)                    */
#define CRYPTO_PKASTATUS_ALUCARRYMOD_Pos  (10UL)                    /*!< ALUCARRYMOD (Bit 10)                                  */
#define CRYPTO_PKASTATUS_ALUCARRYMOD_Msk  (0x400UL)                 /*!< ALUCARRYMOD (Bitfield-Mask: 0x01)                     */
#define CRYPTO_PKASTATUS_ALUCARRY_Pos     (9UL)                     /*!< ALUCARRY (Bit 9)                                      */
#define CRYPTO_PKASTATUS_ALUCARRY_Msk     (0x200UL)                 /*!< ALUCARRY (Bitfield-Mask: 0x01)                        */
#define CRYPTO_PKASTATUS_ALUSIGNOUT_Pos   (8UL)                     /*!< ALUSIGNOUT (Bit 8)                                    */
#define CRYPTO_PKASTATUS_ALUSIGNOUT_Msk   (0x100UL)                 /*!< ALUSIGNOUT (Bitfield-Mask: 0x01)                      */
#define CRYPTO_PKASTATUS_ALULSB4BITS_Pos  (4UL)                     /*!< ALULSB4BITS (Bit 4)                                   */
#define CRYPTO_PKASTATUS_ALULSB4BITS_Msk  (0xf0UL)                  /*!< ALULSB4BITS (Bitfield-Mask: 0x0f)                     */
#define CRYPTO_PKASTATUS_ALUMSB4BITS_Pos  (0UL)                     /*!< ALUMSB4BITS (Bit 0)                                   */
#define CRYPTO_PKASTATUS_ALUMSB4BITS_Msk  (0xfUL)                   /*!< ALUMSB4BITS (Bitfield-Mask: 0x0f)                     */
/* ======================================================  PKASWRESET  ======================================================= */
#define CRYPTO_PKASWRESET_PKASWRESET_Pos  (0UL)                     /*!< PKASWRESET (Bit 0)                                    */
#define CRYPTO_PKASWRESET_PKASWRESET_Msk  (0x1UL)                   /*!< PKASWRESET (Bitfield-Mask: 0x01)                      */
/* =========================================================  PKAL0  ========================================================= */
#define CRYPTO_PKAL0_PKAL0_Pos            (0UL)                     /*!< PKAL0 (Bit 0)                                         */
#define CRYPTO_PKAL0_PKAL0_Msk            (0x1fffUL)                /*!< PKAL0 (Bitfield-Mask: 0x1fff)                         */
/* =========================================================  PKAL1  ========================================================= */
#define CRYPTO_PKAL1_PKAL1_Pos            (0UL)                     /*!< PKAL1 (Bit 0)                                         */
#define CRYPTO_PKAL1_PKAL1_Msk            (0x1fffUL)                /*!< PKAL1 (Bitfield-Mask: 0x1fff)                         */
/* =========================================================  PKAL2  ========================================================= */
#define CRYPTO_PKAL2_PKAL2_Pos            (0UL)                     /*!< PKAL2 (Bit 0)                                         */
#define CRYPTO_PKAL2_PKAL2_Msk            (0x1fffUL)                /*!< PKAL2 (Bitfield-Mask: 0x1fff)                         */
/* =========================================================  PKAL3  ========================================================= */
#define CRYPTO_PKAL3_PKAL3_Pos            (0UL)                     /*!< PKAL3 (Bit 0)                                         */
#define CRYPTO_PKAL3_PKAL3_Msk            (0x1fffUL)                /*!< PKAL3 (Bitfield-Mask: 0x1fff)                         */
/* =========================================================  PKAL4  ========================================================= */
#define CRYPTO_PKAL4_PKAL4_Pos            (0UL)                     /*!< PKAL4 (Bit 0)                                         */
#define CRYPTO_PKAL4_PKAL4_Msk            (0x1fffUL)                /*!< PKAL4 (Bitfield-Mask: 0x1fff)                         */
/* =========================================================  PKAL5  ========================================================= */
#define CRYPTO_PKAL5_PKAL5_Pos            (0UL)                     /*!< PKAL5 (Bit 0)                                         */
#define CRYPTO_PKAL5_PKAL5_Msk            (0x1fffUL)                /*!< PKAL5 (Bitfield-Mask: 0x1fff)                         */
/* =========================================================  PKAL6  ========================================================= */
#define CRYPTO_PKAL6_PKAL6_Pos            (0UL)                     /*!< PKAL6 (Bit 0)                                         */
#define CRYPTO_PKAL6_PKAL6_Msk            (0x1fffUL)                /*!< PKAL6 (Bitfield-Mask: 0x1fff)                         */
/* =========================================================  PKAL7  ========================================================= */
#define CRYPTO_PKAL7_PKAL7_Pos            (0UL)                     /*!< PKAL7 (Bit 0)                                         */
#define CRYPTO_PKAL7_PKAL7_Msk            (0x1fffUL)                /*!< PKAL7 (Bitfield-Mask: 0x1fff)                         */
/* ======================================================  PKAPIPERDY  ======================================================= */
#define CRYPTO_PKAPIPERDY_PKAPIPERDY_Pos  (0UL)                     /*!< PKAPIPERDY (Bit 0)                                    */
#define CRYPTO_PKAPIPERDY_PKAPIPERDY_Msk  (0x1UL)                   /*!< PKAPIPERDY (Bitfield-Mask: 0x01)                      */
/* ========================================================  PKADONE  ======================================================== */
#define CRYPTO_PKADONE_PKADONE_Pos        (0UL)                     /*!< PKADONE (Bit 0)                                       */
#define CRYPTO_PKADONE_PKADONE_Msk        (0x1UL)                   /*!< PKADONE (Bitfield-Mask: 0x01)                         */
/* =====================================================  PKAMONSELECT  ====================================================== */
#define CRYPTO_PKAMONSELECT_PKAMONSELECT_Pos (0UL)                  /*!< PKAMONSELECT (Bit 0)                                  */
#define CRYPTO_PKAMONSELECT_PKAMONSELECT_Msk (0xfUL)                /*!< PKAMONSELECT (Bitfield-Mask: 0x0f)                    */
/* ======================================================  PKAVERSION  ======================================================= */
#define CRYPTO_PKAVERSION_PKAVERSION_Pos  (0UL)                     /*!< PKAVERSION (Bit 0)                                    */
#define CRYPTO_PKAVERSION_PKAVERSION_Msk  (0xffffffffUL)            /*!< PKAVERSION (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  PKAMONREAD  ======================================================= */
#define CRYPTO_PKAMONREAD_PKAMONREAD_Pos  (0UL)                     /*!< PKAMONREAD (Bit 0)                                    */
#define CRYPTO_PKAMONREAD_PKAMONREAD_Msk  (0xffffffffUL)            /*!< PKAMONREAD (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  PKASRAMADDR  ====================================================== */
#define CRYPTO_PKASRAMADDR_PKASRAMADDR_Pos (0UL)                    /*!< PKASRAMADDR (Bit 0)                                   */
#define CRYPTO_PKASRAMADDR_PKASRAMADDR_Msk (0xffffffffUL)           /*!< PKASRAMADDR (Bitfield-Mask: 0xffffffff)               */
/* =====================================================  PKASRAMWDATA  ====================================================== */
#define CRYPTO_PKASRAMWDATA_PKASRAMWDATA_Pos (0UL)                  /*!< PKASRAMWDATA (Bit 0)                                  */
#define CRYPTO_PKASRAMWDATA_PKASRAMWDATA_Msk (0xffffffffUL)         /*!< PKASRAMWDATA (Bitfield-Mask: 0xffffffff)              */
/* =====================================================  PKASRAMRDATA  ====================================================== */
#define CRYPTO_PKASRAMRDATA_PKASRAMRDATA_Pos (0UL)                  /*!< PKASRAMRDATA (Bit 0)                                  */
#define CRYPTO_PKASRAMRDATA_PKASRAMRDATA_Msk (0xffffffffUL)         /*!< PKASRAMRDATA (Bitfield-Mask: 0xffffffff)              */
/* =====================================================  PKASRAMWRCLR  ====================================================== */
#define CRYPTO_PKASRAMWRCLR_PKASRAMWRCLR_Pos (0UL)                  /*!< PKASRAMWRCLR (Bit 0)                                  */
#define CRYPTO_PKASRAMWRCLR_PKASRAMWRCLR_Msk (0xffffffffUL)         /*!< PKASRAMWRCLR (Bitfield-Mask: 0xffffffff)              */
/* =====================================================  PKASRAMRADDR  ====================================================== */
#define CRYPTO_PKASRAMRADDR_PKASRAMRADDR_Pos (0UL)                  /*!< PKASRAMRADDR (Bit 0)                                  */
#define CRYPTO_PKASRAMRADDR_PKASRAMRADDR_Msk (0xffffffffUL)         /*!< PKASRAMRADDR (Bitfield-Mask: 0xffffffff)              */
/* =====================================================  PKAWORDACCESS  ===================================================== */
#define CRYPTO_PKAWORDACCESS_PKAWORDACCESS_Pos (0UL)                /*!< PKAWORDACCESS (Bit 0)                                 */
#define CRYPTO_PKAWORDACCESS_PKAWORDACCESS_Msk (0xffffffffUL)       /*!< PKAWORDACCESS (Bitfield-Mask: 0xffffffff)             */
/* ======================================================  PKABUFFADDR  ====================================================== */
#define CRYPTO_PKABUFFADDR_PKABUFADDR_Pos (0UL)                     /*!< PKABUFADDR (Bit 0)                                    */
#define CRYPTO_PKABUFFADDR_PKABUFADDR_Msk (0xfffUL)                 /*!< PKABUFADDR (Bitfield-Mask: 0xfff)                     */
/* ========================================================  RNGIMR  ========================================================= */
#define CRYPTO_RNGIMR_RNGDMADONEINT_Pos   (5UL)                     /*!< RNGDMADONEINT (Bit 5)                                 */
#define CRYPTO_RNGIMR_RNGDMADONEINT_Msk   (0x20UL)                  /*!< RNGDMADONEINT (Bitfield-Mask: 0x01)                   */
#define CRYPTO_RNGIMR_WATCHDOGINTMASK_Pos (4UL)                     /*!< WATCHDOGINTMASK (Bit 4)                               */
#define CRYPTO_RNGIMR_WATCHDOGINTMASK_Msk (0x10UL)                  /*!< WATCHDOGINTMASK (Bitfield-Mask: 0x01)                 */
#define CRYPTO_RNGIMR_VNERRINTMASK_Pos    (3UL)                     /*!< VNERRINTMASK (Bit 3)                                  */
#define CRYPTO_RNGIMR_VNERRINTMASK_Msk    (0x8UL)                   /*!< VNERRINTMASK (Bitfield-Mask: 0x01)                    */
#define CRYPTO_RNGIMR_CRNGTERRINTMASK_Pos (2UL)                     /*!< CRNGTERRINTMASK (Bit 2)                               */
#define CRYPTO_RNGIMR_CRNGTERRINTMASK_Msk (0x4UL)                   /*!< CRNGTERRINTMASK (Bitfield-Mask: 0x01)                 */
#define CRYPTO_RNGIMR_AUTOCORRERRINTMASK_Pos (1UL)                  /*!< AUTOCORRERRINTMASK (Bit 1)                            */
#define CRYPTO_RNGIMR_AUTOCORRERRINTMASK_Msk (0x2UL)                /*!< AUTOCORRERRINTMASK (Bitfield-Mask: 0x01)              */
#define CRYPTO_RNGIMR_EHRVALIDINTMASK_Pos (0UL)                     /*!< EHRVALIDINTMASK (Bit 0)                               */
#define CRYPTO_RNGIMR_EHRVALIDINTMASK_Msk (0x1UL)                   /*!< EHRVALIDINTMASK (Bitfield-Mask: 0x01)                 */
/* ========================================================  RNGISR  ========================================================= */
#define CRYPTO_RNGISR_WHICHKATERR_Pos     (25UL)                    /*!< WHICHKATERR (Bit 25)                                  */
#define CRYPTO_RNGISR_WHICHKATERR_Msk     (0x6000000UL)             /*!< WHICHKATERR (Bitfield-Mask: 0x03)                     */
#define CRYPTO_RNGISR_KATERR_Pos          (24UL)                    /*!< KATERR (Bit 24)                                       */
#define CRYPTO_RNGISR_KATERR_Msk          (0x1000000UL)             /*!< KATERR (Bitfield-Mask: 0x01)                          */
#define CRYPTO_RNGISR_REQSIZE_Pos         (23UL)                    /*!< REQSIZE (Bit 23)                                      */
#define CRYPTO_RNGISR_REQSIZE_Msk         (0x800000UL)              /*!< REQSIZE (Bitfield-Mask: 0x01)                         */
#define CRYPTO_RNGISR_PRNGCRNGTERR_Pos    (22UL)                    /*!< PRNGCRNGTERR (Bit 22)                                 */
#define CRYPTO_RNGISR_PRNGCRNGTERR_Msk    (0x400000UL)              /*!< PRNGCRNGTERR (Bitfield-Mask: 0x01)                    */
#define CRYPTO_RNGISR_RESEEDCNTRTOP40_Pos (21UL)                    /*!< RESEEDCNTRTOP40 (Bit 21)                              */
#define CRYPTO_RNGISR_RESEEDCNTRTOP40_Msk (0x200000UL)              /*!< RESEEDCNTRTOP40 (Bitfield-Mask: 0x01)                 */
#define CRYPTO_RNGISR_RESEEDCNTRFULL_Pos  (20UL)                    /*!< RESEEDCNTRFULL (Bit 20)                               */
#define CRYPTO_RNGISR_RESEEDCNTRFULL_Msk  (0x100000UL)              /*!< RESEEDCNTRFULL (Bitfield-Mask: 0x01)                  */
#define CRYPTO_RNGISR_OUTPUTREADY_Pos     (19UL)                    /*!< OUTPUTREADY (Bit 19)                                  */
#define CRYPTO_RNGISR_OUTPUTREADY_Msk     (0x80000UL)               /*!< OUTPUTREADY (Bitfield-Mask: 0x01)                     */
#define CRYPTO_RNGISR_FINALUPDATEDONE_Pos (18UL)                    /*!< FINALUPDATEDONE (Bit 18)                              */
#define CRYPTO_RNGISR_FINALUPDATEDONE_Msk (0x40000UL)               /*!< FINALUPDATEDONE (Bitfield-Mask: 0x01)                 */
#define CRYPTO_RNGISR_INSTANTIATIONDONE_Pos (17UL)                  /*!< INSTANTIATIONDONE (Bit 17)                            */
#define CRYPTO_RNGISR_INSTANTIATIONDONE_Msk (0x20000UL)             /*!< INSTANTIATIONDONE (Bitfield-Mask: 0x01)               */
#define CRYPTO_RNGISR_RESEEDINGDONE_Pos   (16UL)                    /*!< RESEEDINGDONE (Bit 16)                                */
#define CRYPTO_RNGISR_RESEEDINGDONE_Msk   (0x10000UL)               /*!< RESEEDINGDONE (Bitfield-Mask: 0x01)                   */
#define CRYPTO_RNGISR_RNGDMADONE_Pos      (5UL)                     /*!< RNGDMADONE (Bit 5)                                    */
#define CRYPTO_RNGISR_RNGDMADONE_Msk      (0x20UL)                  /*!< RNGDMADONE (Bitfield-Mask: 0x01)                      */
#define CRYPTO_RNGISR_VNERR_Pos           (3UL)                     /*!< VNERR (Bit 3)                                         */
#define CRYPTO_RNGISR_VNERR_Msk           (0x8UL)                   /*!< VNERR (Bitfield-Mask: 0x01)                           */
#define CRYPTO_RNGISR_CRNGTERR_Pos        (2UL)                     /*!< CRNGTERR (Bit 2)                                      */
#define CRYPTO_RNGISR_CRNGTERR_Msk        (0x4UL)                   /*!< CRNGTERR (Bitfield-Mask: 0x01)                        */
#define CRYPTO_RNGISR_AUTOCORRERR_Pos     (1UL)                     /*!< AUTOCORRERR (Bit 1)                                   */
#define CRYPTO_RNGISR_AUTOCORRERR_Msk     (0x2UL)                   /*!< AUTOCORRERR (Bitfield-Mask: 0x01)                     */
#define CRYPTO_RNGISR_EHRVALID_Pos        (0UL)                     /*!< EHRVALID (Bit 0)                                      */
#define CRYPTO_RNGISR_EHRVALID_Msk        (0x1UL)                   /*!< EHRVALID (Bitfield-Mask: 0x01)                        */
/* ========================================================  RNGICR  ========================================================= */
#define CRYPTO_RNGICR_WHICHKATERR_Pos     (25UL)                    /*!< WHICHKATERR (Bit 25)                                  */
#define CRYPTO_RNGICR_WHICHKATERR_Msk     (0x6000000UL)             /*!< WHICHKATERR (Bitfield-Mask: 0x03)                     */
#define CRYPTO_RNGICR_KATERR_Pos          (24UL)                    /*!< KATERR (Bit 24)                                       */
#define CRYPTO_RNGICR_KATERR_Msk          (0x1000000UL)             /*!< KATERR (Bitfield-Mask: 0x01)                          */
#define CRYPTO_RNGICR_REQSIZE_Pos         (23UL)                    /*!< REQSIZE (Bit 23)                                      */
#define CRYPTO_RNGICR_REQSIZE_Msk         (0x800000UL)              /*!< REQSIZE (Bitfield-Mask: 0x01)                         */
#define CRYPTO_RNGICR_PRNGCRNGTERR_Pos    (22UL)                    /*!< PRNGCRNGTERR (Bit 22)                                 */
#define CRYPTO_RNGICR_PRNGCRNGTERR_Msk    (0x400000UL)              /*!< PRNGCRNGTERR (Bitfield-Mask: 0x01)                    */
#define CRYPTO_RNGICR_RESEEDCNTRTOP40_Pos (21UL)                    /*!< RESEEDCNTRTOP40 (Bit 21)                              */
#define CRYPTO_RNGICR_RESEEDCNTRTOP40_Msk (0x200000UL)              /*!< RESEEDCNTRTOP40 (Bitfield-Mask: 0x01)                 */
#define CRYPTO_RNGICR_RESEEDCNTRFULL_Pos  (20UL)                    /*!< RESEEDCNTRFULL (Bit 20)                               */
#define CRYPTO_RNGICR_RESEEDCNTRFULL_Msk  (0x100000UL)              /*!< RESEEDCNTRFULL (Bitfield-Mask: 0x01)                  */
#define CRYPTO_RNGICR_OUTPUTREADY_Pos     (19UL)                    /*!< OUTPUTREADY (Bit 19)                                  */
#define CRYPTO_RNGICR_OUTPUTREADY_Msk     (0x80000UL)               /*!< OUTPUTREADY (Bitfield-Mask: 0x01)                     */
#define CRYPTO_RNGICR_FINALUPDATEDONE_Pos (18UL)                    /*!< FINALUPDATEDONE (Bit 18)                              */
#define CRYPTO_RNGICR_FINALUPDATEDONE_Msk (0x40000UL)               /*!< FINALUPDATEDONE (Bitfield-Mask: 0x01)                 */
#define CRYPTO_RNGICR_INSTANTIATIONDONE_Pos (17UL)                  /*!< INSTANTIATIONDONE (Bit 17)                            */
#define CRYPTO_RNGICR_INSTANTIATIONDONE_Msk (0x20000UL)             /*!< INSTANTIATIONDONE (Bitfield-Mask: 0x01)               */
#define CRYPTO_RNGICR_RESEEDINGDONE_Pos   (16UL)                    /*!< RESEEDINGDONE (Bit 16)                                */
#define CRYPTO_RNGICR_RESEEDINGDONE_Msk   (0x10000UL)               /*!< RESEEDINGDONE (Bitfield-Mask: 0x01)                   */
#define CRYPTO_RNGICR_RNGDMADONE_Pos      (5UL)                     /*!< RNGDMADONE (Bit 5)                                    */
#define CRYPTO_RNGICR_RNGDMADONE_Msk      (0x20UL)                  /*!< RNGDMADONE (Bitfield-Mask: 0x01)                      */
#define CRYPTO_RNGICR_RNGWATCHDOG_Pos     (4UL)                     /*!< RNGWATCHDOG (Bit 4)                                   */
#define CRYPTO_RNGICR_RNGWATCHDOG_Msk     (0x10UL)                  /*!< RNGWATCHDOG (Bitfield-Mask: 0x01)                     */
#define CRYPTO_RNGICR_VNERR_Pos           (3UL)                     /*!< VNERR (Bit 3)                                         */
#define CRYPTO_RNGICR_VNERR_Msk           (0x8UL)                   /*!< VNERR (Bitfield-Mask: 0x01)                           */
#define CRYPTO_RNGICR_CRNGTERR_Pos        (2UL)                     /*!< CRNGTERR (Bit 2)                                      */
#define CRYPTO_RNGICR_CRNGTERR_Msk        (0x4UL)                   /*!< CRNGTERR (Bitfield-Mask: 0x01)                        */
#define CRYPTO_RNGICR_AUTOCORRERR_Pos     (1UL)                     /*!< AUTOCORRERR (Bit 1)                                   */
#define CRYPTO_RNGICR_AUTOCORRERR_Msk     (0x2UL)                   /*!< AUTOCORRERR (Bitfield-Mask: 0x01)                     */
#define CRYPTO_RNGICR_EHRVALID_Pos        (0UL)                     /*!< EHRVALID (Bit 0)                                      */
#define CRYPTO_RNGICR_EHRVALID_Msk        (0x1UL)                   /*!< EHRVALID (Bitfield-Mask: 0x01)                        */
/* ======================================================  TRNGCONFIG  ======================================================= */
#define CRYPTO_TRNGCONFIG_SOPSEL_Pos      (2UL)                     /*!< SOPSEL (Bit 2)                                        */
#define CRYPTO_TRNGCONFIG_SOPSEL_Msk      (0x4UL)                   /*!< SOPSEL (Bitfield-Mask: 0x01)                          */
#define CRYPTO_TRNGCONFIG_RNDSRCSEL_Pos   (0UL)                     /*!< RNDSRCSEL (Bit 0)                                     */
#define CRYPTO_TRNGCONFIG_RNDSRCSEL_Msk   (0x3UL)                   /*!< RNDSRCSEL (Bitfield-Mask: 0x03)                       */
/* =======================================================  TRNGVALID  ======================================================= */
#define CRYPTO_TRNGVALID_EHRVALID_Pos     (0UL)                     /*!< EHRVALID (Bit 0)                                      */
#define CRYPTO_TRNGVALID_EHRVALID_Msk     (0x1UL)                   /*!< EHRVALID (Bitfield-Mask: 0x01)                        */
/* =======================================================  EHRDATA0  ======================================================== */
#define CRYPTO_EHRDATA0_EHRDATA_Pos       (0UL)                     /*!< EHRDATA (Bit 0)                                       */
#define CRYPTO_EHRDATA0_EHRDATA_Msk       (0xffffffffUL)            /*!< EHRDATA (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  EHRDATA1  ======================================================== */
#define CRYPTO_EHRDATA1_EHRDATA_Pos       (0UL)                     /*!< EHRDATA (Bit 0)                                       */
#define CRYPTO_EHRDATA1_EHRDATA_Msk       (0xffffffffUL)            /*!< EHRDATA (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  EHRDATA2  ======================================================== */
#define CRYPTO_EHRDATA2_EHRDATA_Pos       (0UL)                     /*!< EHRDATA (Bit 0)                                       */
#define CRYPTO_EHRDATA2_EHRDATA_Msk       (0xffffffffUL)            /*!< EHRDATA (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  EHRDATA3  ======================================================== */
#define CRYPTO_EHRDATA3_EHRDATA_Pos       (0UL)                     /*!< EHRDATA (Bit 0)                                       */
#define CRYPTO_EHRDATA3_EHRDATA_Msk       (0xffffffffUL)            /*!< EHRDATA (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  EHRDATA4  ======================================================== */
#define CRYPTO_EHRDATA4_EHRDATA_Pos       (0UL)                     /*!< EHRDATA (Bit 0)                                       */
#define CRYPTO_EHRDATA4_EHRDATA_Msk       (0xffffffffUL)            /*!< EHRDATA (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  EHRDATA5  ======================================================== */
#define CRYPTO_EHRDATA5_EHRDATA_Pos       (0UL)                     /*!< EHRDATA (Bit 0)                                       */
#define CRYPTO_EHRDATA5_EHRDATA_Msk       (0xffffffffUL)            /*!< EHRDATA (Bitfield-Mask: 0xffffffff)                   */
/* ====================================================  RNDSOURCEENABLE  ==================================================== */
#define CRYPTO_RNDSOURCEENABLE_RNDSRCEN_Pos (0UL)                   /*!< RNDSRCEN (Bit 0)                                      */
#define CRYPTO_RNDSOURCEENABLE_RNDSRCEN_Msk (0x1UL)                 /*!< RNDSRCEN (Bitfield-Mask: 0x01)                        */
/* ======================================================  SAMPLECNT1  ======================================================= */
#define CRYPTO_SAMPLECNT1_SAMPLECNTR1_Pos (0UL)                     /*!< SAMPLECNTR1 (Bit 0)                                   */
#define CRYPTO_SAMPLECNT1_SAMPLECNTR1_Msk (0xffffffffUL)            /*!< SAMPLECNTR1 (Bitfield-Mask: 0xffffffff)               */
/* ===================================================  AUTOCORRSTATISTIC  =================================================== */
#define CRYPTO_AUTOCORRSTATISTIC_AUTOCORRFAILS_Pos (14UL)           /*!< AUTOCORRFAILS (Bit 14)                                */
#define CRYPTO_AUTOCORRSTATISTIC_AUTOCORRFAILS_Msk (0x3fc000UL)     /*!< AUTOCORRFAILS (Bitfield-Mask: 0xff)                   */
#define CRYPTO_AUTOCORRSTATISTIC_AUTOCORRTRYS_Pos (0UL)             /*!< AUTOCORRTRYS (Bit 0)                                  */
#define CRYPTO_AUTOCORRSTATISTIC_AUTOCORRTRYS_Msk (0x3fffUL)        /*!< AUTOCORRTRYS (Bitfield-Mask: 0x3fff)                  */
/* ===================================================  TRNGDEBUGCONTROL  ==================================================== */
#define CRYPTO_TRNGDEBUGCONTROL_AUTOCORRELATEBYPASS_Pos (3UL)       /*!< AUTOCORRELATEBYPASS (Bit 3)                           */
#define CRYPTO_TRNGDEBUGCONTROL_AUTOCORRELATEBYPASS_Msk (0x8UL)     /*!< AUTOCORRELATEBYPASS (Bitfield-Mask: 0x01)             */
#define CRYPTO_TRNGDEBUGCONTROL_TRNGCRNGTBYPASS_Pos (2UL)           /*!< TRNGCRNGTBYPASS (Bit 2)                               */
#define CRYPTO_TRNGDEBUGCONTROL_TRNGCRNGTBYPASS_Msk (0x4UL)         /*!< TRNGCRNGTBYPASS (Bitfield-Mask: 0x01)                 */
#define CRYPTO_TRNGDEBUGCONTROL_VNCBYPASS_Pos (1UL)                 /*!< VNCBYPASS (Bit 1)                                     */
#define CRYPTO_TRNGDEBUGCONTROL_VNCBYPASS_Msk (0x2UL)               /*!< VNCBYPASS (Bitfield-Mask: 0x01)                       */
/* ======================================================  RNGSWRESET  ======================================================= */
#define CRYPTO_RNGSWRESET_RNGSWRESET_Pos  (0UL)                     /*!< RNGSWRESET (Bit 0)                                    */
#define CRYPTO_RNGSWRESET_RNGSWRESET_Msk  (0x1UL)                   /*!< RNGSWRESET (Bitfield-Mask: 0x01)                      */
/* ====================================================  RNGDEBUGENINPUT  ==================================================== */
#define CRYPTO_RNGDEBUGENINPUT_RNGDEBUGEN_Pos (0UL)                 /*!< RNGDEBUGEN (Bit 0)                                    */
#define CRYPTO_RNGDEBUGENINPUT_RNGDEBUGEN_Msk (0x1UL)               /*!< RNGDEBUGEN (Bitfield-Mask: 0x01)                      */
/* ========================================================  RNGBUSY  ======================================================== */
#define CRYPTO_RNGBUSY_PRNGBUSY_Pos       (2UL)                     /*!< PRNGBUSY (Bit 2)                                      */
#define CRYPTO_RNGBUSY_PRNGBUSY_Msk       (0x4UL)                   /*!< PRNGBUSY (Bitfield-Mask: 0x01)                        */
#define CRYPTO_RNGBUSY_TRNGBUSY_Pos       (1UL)                     /*!< TRNGBUSY (Bit 1)                                      */
#define CRYPTO_RNGBUSY_TRNGBUSY_Msk       (0x2UL)                   /*!< TRNGBUSY (Bitfield-Mask: 0x01)                        */
#define CRYPTO_RNGBUSY_RNGBUSY_Pos        (0UL)                     /*!< RNGBUSY (Bit 0)                                       */
#define CRYPTO_RNGBUSY_RNGBUSY_Msk        (0x1UL)                   /*!< RNGBUSY (Bitfield-Mask: 0x01)                         */
/* ====================================================  RSTBITSCOUNTER  ===================================================== */
#define CRYPTO_RSTBITSCOUNTER_RSTBITSCOUNTER_Pos (0UL)              /*!< RSTBITSCOUNTER (Bit 0)                                */
#define CRYPTO_RSTBITSCOUNTER_RSTBITSCOUNTER_Msk (0x1UL)            /*!< RSTBITSCOUNTER (Bitfield-Mask: 0x01)                  */
/* ======================================================  RNGVERSION  ======================================================= */
#define CRYPTO_RNGVERSION_RNGUSE5SBOXES_Pos (7UL)                   /*!< RNGUSE5SBOXES (Bit 7)                                 */
#define CRYPTO_RNGVERSION_RNGUSE5SBOXES_Msk (0x80UL)                /*!< RNGUSE5SBOXES (Bitfield-Mask: 0x01)                   */
#define CRYPTO_RNGVERSION_RESEEDINGEXISTS_Pos (6UL)                 /*!< RESEEDINGEXISTS (Bit 6)                               */
#define CRYPTO_RNGVERSION_RESEEDINGEXISTS_Msk (0x40UL)              /*!< RESEEDINGEXISTS (Bitfield-Mask: 0x01)                 */
#define CRYPTO_RNGVERSION_KATEXISTS_Pos   (5UL)                     /*!< KATEXISTS (Bit 5)                                     */
#define CRYPTO_RNGVERSION_KATEXISTS_Msk   (0x20UL)                  /*!< KATEXISTS (Bitfield-Mask: 0x01)                       */
#define CRYPTO_RNGVERSION_PRNGEXISTS_Pos  (4UL)                     /*!< PRNGEXISTS (Bit 4)                                    */
#define CRYPTO_RNGVERSION_PRNGEXISTS_Msk  (0x10UL)                  /*!< PRNGEXISTS (Bitfield-Mask: 0x01)                      */
#define CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN_Pos (3UL)               /*!< TRNGTESTSBYPASSEN (Bit 3)                             */
#define CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN_Msk (0x8UL)             /*!< TRNGTESTSBYPASSEN (Bitfield-Mask: 0x01)               */
#define CRYPTO_RNGVERSION_AUTOCORREXISTS_Pos (2UL)                  /*!< AUTOCORREXISTS (Bit 2)                                */
#define CRYPTO_RNGVERSION_AUTOCORREXISTS_Msk (0x4UL)                /*!< AUTOCORREXISTS (Bitfield-Mask: 0x01)                  */
#define CRYPTO_RNGVERSION_CRNGTEXISTS_Pos (1UL)                     /*!< CRNGTEXISTS (Bit 1)                                   */
#define CRYPTO_RNGVERSION_CRNGTEXISTS_Msk (0x2UL)                   /*!< CRNGTEXISTS (Bitfield-Mask: 0x01)                     */
#define CRYPTO_RNGVERSION_EHRWIDTH192_Pos (0UL)                     /*!< EHRWIDTH192 (Bit 0)                                   */
#define CRYPTO_RNGVERSION_EHRWIDTH192_Msk (0x1UL)                   /*!< EHRWIDTH192 (Bitfield-Mask: 0x01)                     */
/* =====================================================  RNGCLKENABLE  ====================================================== */
#define CRYPTO_RNGCLKENABLE_EN_Pos        (0UL)                     /*!< EN (Bit 0)                                            */
#define CRYPTO_RNGCLKENABLE_EN_Msk        (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =====================================================  RNGDMAENABLE  ====================================================== */
#define CRYPTO_RNGDMAENABLE_EN_Pos        (0UL)                     /*!< EN (Bit 0)                                            */
#define CRYPTO_RNGDMAENABLE_EN_Msk        (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =====================================================  RNGDMASRCMASK  ===================================================== */
#define CRYPTO_RNGDMASRCMASK_ENSRCSEL3_Pos (3UL)                    /*!< ENSRCSEL3 (Bit 3)                                     */
#define CRYPTO_RNGDMASRCMASK_ENSRCSEL3_Msk (0x8UL)                  /*!< ENSRCSEL3 (Bitfield-Mask: 0x01)                       */
#define CRYPTO_RNGDMASRCMASK_ENSRCSEL2_Pos (2UL)                    /*!< ENSRCSEL2 (Bit 2)                                     */
#define CRYPTO_RNGDMASRCMASK_ENSRCSEL2_Msk (0x4UL)                  /*!< ENSRCSEL2 (Bitfield-Mask: 0x01)                       */
#define CRYPTO_RNGDMASRCMASK_ENSRCSEL1_Pos (1UL)                    /*!< ENSRCSEL1 (Bit 1)                                     */
#define CRYPTO_RNGDMASRCMASK_ENSRCSEL1_Msk (0x2UL)                  /*!< ENSRCSEL1 (Bitfield-Mask: 0x01)                       */
#define CRYPTO_RNGDMASRCMASK_ENSRCSEL0_Pos (0UL)                    /*!< ENSRCSEL0 (Bit 0)                                     */
#define CRYPTO_RNGDMASRCMASK_ENSRCSEL0_Msk (0x1UL)                  /*!< ENSRCSEL0 (Bitfield-Mask: 0x01)                       */
/* ====================================================  RNGDMASRAMADDR  ===================================================== */
#define CRYPTO_RNGDMASRAMADDR_RNGSRAMDMAADDR_Pos (0UL)              /*!< RNGSRAMDMAADDR (Bit 0)                                */
#define CRYPTO_RNGDMASRAMADDR_RNGSRAMDMAADDR_Msk (0x7ffUL)          /*!< RNGSRAMDMAADDR (Bitfield-Mask: 0x7ff)                 */
/* ====================================================  RNGWATCHDOGVAL  ===================================================== */
#define CRYPTO_RNGWATCHDOGVAL_RNGWATCHDOGVAL_Pos (0UL)              /*!< RNGWATCHDOGVAL (Bit 0)                                */
#define CRYPTO_RNGWATCHDOGVAL_RNGWATCHDOGVAL_Msk (0xffffffffUL)     /*!< RNGWATCHDOGVAL (Bitfield-Mask: 0xffffffff)            */
/* =====================================================  RNGDMASTATUS  ====================================================== */
#define CRYPTO_RNGDMASTATUS_NUMOFSAMPLES_Pos (3UL)                  /*!< NUMOFSAMPLES (Bit 3)                                  */
#define CRYPTO_RNGDMASTATUS_NUMOFSAMPLES_Msk (0x7f8UL)              /*!< NUMOFSAMPLES (Bitfield-Mask: 0xff)                    */
#define CRYPTO_RNGDMASTATUS_DMASRCSEL_Pos (1UL)                     /*!< DMASRCSEL (Bit 1)                                     */
#define CRYPTO_RNGDMASTATUS_DMASRCSEL_Msk (0x6UL)                   /*!< DMASRCSEL (Bitfield-Mask: 0x03)                       */
#define CRYPTO_RNGDMASTATUS_RNGDMABUSY_Pos (0UL)                    /*!< RNGDMABUSY (Bit 0)                                    */
#define CRYPTO_RNGDMASTATUS_RNGDMABUSY_Msk (0x1UL)                  /*!< RNGDMABUSY (Bitfield-Mask: 0x01)                      */
/* ===================================================  CHACHACONTROLREG  ==================================================== */
#define CRYPTO_CHACHACONTROLREG_USEIV96BIT_Pos (10UL)               /*!< USEIV96BIT (Bit 10)                                   */
#define CRYPTO_CHACHACONTROLREG_USEIV96BIT_Msk (0x400UL)            /*!< USEIV96BIT (Bitfield-Mask: 0x01)                      */
#define CRYPTO_CHACHACONTROLREG_RESETBLOCKCNT_Pos (9UL)             /*!< RESETBLOCKCNT (Bit 9)                                 */
#define CRYPTO_CHACHACONTROLREG_RESETBLOCKCNT_Msk (0x200UL)         /*!< RESETBLOCKCNT (Bitfield-Mask: 0x01)                   */
#define CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_Pos (4UL)               /*!< NUMOFROUNDS (Bit 4)                                   */
#define CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_Msk (0x30UL)            /*!< NUMOFROUNDS (Bitfield-Mask: 0x03)                     */
#define CRYPTO_CHACHACONTROLREG_KEYLEN_Pos (3UL)                    /*!< KEYLEN (Bit 3)                                        */
#define CRYPTO_CHACHACONTROLREG_KEYLEN_Msk (0x8UL)                  /*!< KEYLEN (Bitfield-Mask: 0x01)                          */
#define CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305_Pos (2UL)        /*!< CALCKEYFORPOLY1305 (Bit 2)                            */
#define CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305_Msk (0x4UL)      /*!< CALCKEYFORPOLY1305 (Bitfield-Mask: 0x01)              */
#define CRYPTO_CHACHACONTROLREG_INITFROMHOST_Pos (1UL)              /*!< INITFROMHOST (Bit 1)                                  */
#define CRYPTO_CHACHACONTROLREG_INITFROMHOST_Msk (0x2UL)            /*!< INITFROMHOST (Bitfield-Mask: 0x01)                    */
#define CRYPTO_CHACHACONTROLREG_CHACHAORSALSA_Pos (0UL)             /*!< CHACHAORSALSA (Bit 0)                                 */
#define CRYPTO_CHACHACONTROLREG_CHACHAORSALSA_Msk (0x1UL)           /*!< CHACHAORSALSA (Bitfield-Mask: 0x01)                   */
/* =====================================================  CHACHAVERSION  ===================================================== */
#define CRYPTO_CHACHAVERSION_CHACHAVERSION_Pos (0UL)                /*!< CHACHAVERSION (Bit 0)                                 */
#define CRYPTO_CHACHAVERSION_CHACHAVERSION_Msk (0xffffffffUL)       /*!< CHACHAVERSION (Bitfield-Mask: 0xffffffff)             */
/* ======================================================  CHACHAKEY0  ======================================================= */
#define CRYPTO_CHACHAKEY0_CHACHAKEY0_Pos  (0UL)                     /*!< CHACHAKEY0 (Bit 0)                                    */
#define CRYPTO_CHACHAKEY0_CHACHAKEY0_Msk  (0xffffffffUL)            /*!< CHACHAKEY0 (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  CHACHAKEY1  ======================================================= */
#define CRYPTO_CHACHAKEY1_CHACHAKEY1_Pos  (0UL)                     /*!< CHACHAKEY1 (Bit 0)                                    */
#define CRYPTO_CHACHAKEY1_CHACHAKEY1_Msk  (0xffffffffUL)            /*!< CHACHAKEY1 (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  CHACHAKEY2  ======================================================= */
#define CRYPTO_CHACHAKEY2_CHACHAKEY2_Pos  (0UL)                     /*!< CHACHAKEY2 (Bit 0)                                    */
#define CRYPTO_CHACHAKEY2_CHACHAKEY2_Msk  (0xffffffffUL)            /*!< CHACHAKEY2 (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  CHACHAKEY3  ======================================================= */
#define CRYPTO_CHACHAKEY3_CHACHAKEY3_Pos  (0UL)                     /*!< CHACHAKEY3 (Bit 0)                                    */
#define CRYPTO_CHACHAKEY3_CHACHAKEY3_Msk  (0xffffffffUL)            /*!< CHACHAKEY3 (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  CHACHAKEY4  ======================================================= */
#define CRYPTO_CHACHAKEY4_CHACHAKEY4_Pos  (0UL)                     /*!< CHACHAKEY4 (Bit 0)                                    */
#define CRYPTO_CHACHAKEY4_CHACHAKEY4_Msk  (0xffffffffUL)            /*!< CHACHAKEY4 (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  CHACHAKEY5  ======================================================= */
#define CRYPTO_CHACHAKEY5_CHACHAKEY5_Pos  (0UL)                     /*!< CHACHAKEY5 (Bit 0)                                    */
#define CRYPTO_CHACHAKEY5_CHACHAKEY5_Msk  (0xffffffffUL)            /*!< CHACHAKEY5 (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  CHACHAKEY6  ======================================================= */
#define CRYPTO_CHACHAKEY6_CHACHAKEY6_Pos  (0UL)                     /*!< CHACHAKEY6 (Bit 0)                                    */
#define CRYPTO_CHACHAKEY6_CHACHAKEY6_Msk  (0xffffffffUL)            /*!< CHACHAKEY6 (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  CHACHAKEY7  ======================================================= */
#define CRYPTO_CHACHAKEY7_CHACHAKEY7_Pos  (0UL)                     /*!< CHACHAKEY7 (Bit 0)                                    */
#define CRYPTO_CHACHAKEY7_CHACHAKEY7_Msk  (0xffffffffUL)            /*!< CHACHAKEY7 (Bitfield-Mask: 0xffffffff)                */
/* =======================================================  CHACHAIV0  ======================================================= */
#define CRYPTO_CHACHAIV0_CHACHAIV0_Pos    (0UL)                     /*!< CHACHAIV0 (Bit 0)                                     */
#define CRYPTO_CHACHAIV0_CHACHAIV0_Msk    (0xffffffffUL)            /*!< CHACHAIV0 (Bitfield-Mask: 0xffffffff)                 */
/* =======================================================  CHACHAIV1  ======================================================= */
#define CRYPTO_CHACHAIV1_CHACHAIV1_Pos    (0UL)                     /*!< CHACHAIV1 (Bit 0)                                     */
#define CRYPTO_CHACHAIV1_CHACHAIV1_Msk    (0xffffffffUL)            /*!< CHACHAIV1 (Bitfield-Mask: 0xffffffff)                 */
/* ======================================================  CHACHABUSY  ======================================================= */
#define CRYPTO_CHACHABUSY_CHACHABUSY_Pos  (0UL)                     /*!< CHACHABUSY (Bit 0)                                    */
#define CRYPTO_CHACHABUSY_CHACHABUSY_Msk  (0x1UL)                   /*!< CHACHABUSY (Bitfield-Mask: 0x01)                      */
/* =====================================================  CHACHAHWFLAGS  ===================================================== */
#define CRYPTO_CHACHAHWFLAGS_FASTCHACHA_Pos (2UL)                   /*!< FASTCHACHA (Bit 2)                                    */
#define CRYPTO_CHACHAHWFLAGS_FASTCHACHA_Msk (0x4UL)                 /*!< FASTCHACHA (Bitfield-Mask: 0x01)                      */
#define CRYPTO_CHACHAHWFLAGS_SALSAEXISTS_Pos (1UL)                  /*!< SALSAEXISTS (Bit 1)                                   */
#define CRYPTO_CHACHAHWFLAGS_SALSAEXISTS_Msk (0x2UL)                /*!< SALSAEXISTS (Bitfield-Mask: 0x01)                     */
#define CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS_Pos (0UL)                 /*!< CHACHAEXISTS (Bit 0)                                  */
#define CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS_Msk (0x1UL)               /*!< CHACHAEXISTS (Bitfield-Mask: 0x01)                    */
/* ===================================================  CHACHABLOCKCNTLSB  =================================================== */
#define CRYPTO_CHACHABLOCKCNTLSB_CHACHABLOCKCNTLSB_Pos (0UL)        /*!< CHACHABLOCKCNTLSB (Bit 0)                             */
#define CRYPTO_CHACHABLOCKCNTLSB_CHACHABLOCKCNTLSB_Msk (0xffffffffUL) /*!< CHACHABLOCKCNTLSB (Bitfield-Mask: 0xffffffff)       */
/* ===================================================  CHACHABLOCKCNTMSB  =================================================== */
#define CRYPTO_CHACHABLOCKCNTMSB_CHACHABLOCKCNTMSB_Pos (0UL)        /*!< CHACHABLOCKCNTMSB (Bit 0)                             */
#define CRYPTO_CHACHABLOCKCNTMSB_CHACHABLOCKCNTMSB_Msk (0xffffffffUL) /*!< CHACHABLOCKCNTMSB (Bitfield-Mask: 0xffffffff)       */
/* =====================================================  CHACHASWRESET  ===================================================== */
#define CRYPTO_CHACHASWRESET_CHACHSWRESET_Pos (0UL)                 /*!< CHACHSWRESET (Bit 0)                                  */
#define CRYPTO_CHACHASWRESET_CHACHSWRESET_Msk (0x1UL)               /*!< CHACHSWRESET (Bitfield-Mask: 0x01)                    */
/* ===================================================  CHACHAFORPOLYKEY0  =================================================== */
#define CRYPTO_CHACHAFORPOLYKEY0_CHACHAFORPOLYKEY0_Pos (0UL)        /*!< CHACHAFORPOLYKEY0 (Bit 0)                             */
#define CRYPTO_CHACHAFORPOLYKEY0_CHACHAFORPOLYKEY0_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY0 (Bitfield-Mask: 0xffffffff)       */
/* ===================================================  CHACHAFORPOLYKEY1  =================================================== */
#define CRYPTO_CHACHAFORPOLYKEY1_CHACHAFORPOLYKEY1_Pos (0UL)        /*!< CHACHAFORPOLYKEY1 (Bit 0)                             */
#define CRYPTO_CHACHAFORPOLYKEY1_CHACHAFORPOLYKEY1_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY1 (Bitfield-Mask: 0xffffffff)       */
/* ===================================================  CHACHAFORPOLYKEY2  =================================================== */
#define CRYPTO_CHACHAFORPOLYKEY2_CHACHAFORPOLYKEY2_Pos (0UL)        /*!< CHACHAFORPOLYKEY2 (Bit 0)                             */
#define CRYPTO_CHACHAFORPOLYKEY2_CHACHAFORPOLYKEY2_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY2 (Bitfield-Mask: 0xffffffff)       */
/* ===================================================  CHACHAFORPOLYKEY3  =================================================== */
#define CRYPTO_CHACHAFORPOLYKEY3_CHACHAFORPOLYKEY3_Pos (0UL)        /*!< CHACHAFORPOLYKEY3 (Bit 0)                             */
#define CRYPTO_CHACHAFORPOLYKEY3_CHACHAFORPOLYKEY3_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY3 (Bitfield-Mask: 0xffffffff)       */
/* ===================================================  CHACHAFORPOLYKEY4  =================================================== */
#define CRYPTO_CHACHAFORPOLYKEY4_CHACHAFORPOLYKEY4_Pos (0UL)        /*!< CHACHAFORPOLYKEY4 (Bit 0)                             */
#define CRYPTO_CHACHAFORPOLYKEY4_CHACHAFORPOLYKEY4_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY4 (Bitfield-Mask: 0xffffffff)       */
/* ===================================================  CHACHAFORPOLYKEY5  =================================================== */
#define CRYPTO_CHACHAFORPOLYKEY5_CHACHAFORPOLYKEY5_Pos (0UL)        /*!< CHACHAFORPOLYKEY5 (Bit 0)                             */
#define CRYPTO_CHACHAFORPOLYKEY5_CHACHAFORPOLYKEY5_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY5 (Bitfield-Mask: 0xffffffff)       */
/* ===================================================  CHACHAFORPOLYKEY6  =================================================== */
#define CRYPTO_CHACHAFORPOLYKEY6_CHACHAFORPOLYKEY6_Pos (0UL)        /*!< CHACHAFORPOLYKEY6 (Bit 0)                             */
#define CRYPTO_CHACHAFORPOLYKEY6_CHACHAFORPOLYKEY6_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY6 (Bitfield-Mask: 0xffffffff)       */
/* ===================================================  CHACHAFORPOLYKEY7  =================================================== */
#define CRYPTO_CHACHAFORPOLYKEY7_CHACHAFORPOLYKEY7_Pos (0UL)        /*!< CHACHAFORPOLYKEY7 (Bit 0)                             */
#define CRYPTO_CHACHAFORPOLYKEY7_CHACHAFORPOLYKEY7_Msk (0xffffffffUL) /*!< CHACHAFORPOLYKEY7 (Bitfield-Mask: 0xffffffff)       */
/* ==============================================  CHACHABYTEWORDORDERCNTLREG  =============================================== */
#define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER_Pos (4UL) /*!< CHACHADOUTBYTEORDER (Bit 4)                       */
#define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER_Msk (0x10UL) /*!< CHACHADOUTBYTEORDER (Bitfield-Mask: 0x01)      */
#define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER_Pos (3UL) /*!< CHACHADOUTWORDORDER (Bit 3)                       */
#define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER_Msk (0x8UL) /*!< CHACHADOUTWORDORDER (Bitfield-Mask: 0x01)       */
#define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER_Pos (2UL) /*!< CHACHACOREMATRIXLBEORDER (Bit 2)             */
#define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER_Msk (0x4UL) /*!< CHACHACOREMATRIXLBEORDER (Bitfield-Mask: 0x01) */
#define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER_Pos (1UL) /*!< CHACHADINBYTEORDER (Bit 1)                         */
#define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER_Msk (0x2UL) /*!< CHACHADINBYTEORDER (Bitfield-Mask: 0x01)         */
#define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER_Pos (0UL) /*!< CHACHADINWORDORDER (Bit 0)                         */
#define CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER_Msk (0x1UL) /*!< CHACHADINWORDORDER (Bitfield-Mask: 0x01)         */
/* ====================================================  CHACHADEBUGREG  ===================================================== */
#define CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE_Pos (0UL)         /*!< CHACHADEBUGFSMSTATE (Bit 0)                           */
#define CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE_Msk (0x3UL)       /*!< CHACHADEBUGFSMSTATE (Bitfield-Mask: 0x03)             */
/* =======================================================  AESKEY00  ======================================================== */
#define CRYPTO_AESKEY00_AESKEY00_Pos      (0UL)                     /*!< AESKEY00 (Bit 0)                                      */
#define CRYPTO_AESKEY00_AESKEY00_Msk      (0xffffffffUL)            /*!< AESKEY00 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  AESKEY01  ======================================================== */
#define CRYPTO_AESKEY01_AESKEY01_Pos      (0UL)                     /*!< AESKEY01 (Bit 0)                                      */
#define CRYPTO_AESKEY01_AESKEY01_Msk      (0xffffffffUL)            /*!< AESKEY01 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  AESKEY02  ======================================================== */
#define CRYPTO_AESKEY02_AESKEY02_Pos      (0UL)                     /*!< AESKEY02 (Bit 0)                                      */
#define CRYPTO_AESKEY02_AESKEY02_Msk      (0xffffffffUL)            /*!< AESKEY02 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  AESKEY03  ======================================================== */
#define CRYPTO_AESKEY03_AESKEY03_Pos      (0UL)                     /*!< AESKEY03 (Bit 0)                                      */
#define CRYPTO_AESKEY03_AESKEY03_Msk      (0xffffffffUL)            /*!< AESKEY03 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  AESKEY04  ======================================================== */
#define CRYPTO_AESKEY04_AESKEY04_Pos      (0UL)                     /*!< AESKEY04 (Bit 0)                                      */
#define CRYPTO_AESKEY04_AESKEY04_Msk      (0xffffffffUL)            /*!< AESKEY04 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  AESKEY05  ======================================================== */
#define CRYPTO_AESKEY05_AESKEY05_Pos      (0UL)                     /*!< AESKEY05 (Bit 0)                                      */
#define CRYPTO_AESKEY05_AESKEY05_Msk      (0xffffffffUL)            /*!< AESKEY05 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  AESKEY06  ======================================================== */
#define CRYPTO_AESKEY06_AESKEY06_Pos      (0UL)                     /*!< AESKEY06 (Bit 0)                                      */
#define CRYPTO_AESKEY06_AESKEY06_Msk      (0xffffffffUL)            /*!< AESKEY06 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  AESKEY07  ======================================================== */
#define CRYPTO_AESKEY07_AESKEY07_Pos      (0UL)                     /*!< AESKEY07 (Bit 0)                                      */
#define CRYPTO_AESKEY07_AESKEY07_Msk      (0xffffffffUL)            /*!< AESKEY07 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  AESKEY10  ======================================================== */
#define CRYPTO_AESKEY10_AESKEY10_Pos      (0UL)                     /*!< AESKEY10 (Bit 0)                                      */
#define CRYPTO_AESKEY10_AESKEY10_Msk      (0xffffffffUL)            /*!< AESKEY10 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  AESKEY11  ======================================================== */
#define CRYPTO_AESKEY11_AESKEY11_Pos      (0UL)                     /*!< AESKEY11 (Bit 0)                                      */
#define CRYPTO_AESKEY11_AESKEY11_Msk      (0xffffffffUL)            /*!< AESKEY11 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  AESKEY12  ======================================================== */
#define CRYPTO_AESKEY12_AESKEY12_Pos      (0UL)                     /*!< AESKEY12 (Bit 0)                                      */
#define CRYPTO_AESKEY12_AESKEY12_Msk      (0xffffffffUL)            /*!< AESKEY12 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  AESKEY13  ======================================================== */
#define CRYPTO_AESKEY13_AESKEY13_Pos      (0UL)                     /*!< AESKEY13 (Bit 0)                                      */
#define CRYPTO_AESKEY13_AESKEY13_Msk      (0xffffffffUL)            /*!< AESKEY13 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  AESKEY14  ======================================================== */
#define CRYPTO_AESKEY14_AESKEY14_Pos      (0UL)                     /*!< AESKEY14 (Bit 0)                                      */
#define CRYPTO_AESKEY14_AESKEY14_Msk      (0xffffffffUL)            /*!< AESKEY14 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  AESKEY15  ======================================================== */
#define CRYPTO_AESKEY15_AESKEY15_Pos      (0UL)                     /*!< AESKEY15 (Bit 0)                                      */
#define CRYPTO_AESKEY15_AESKEY15_Msk      (0xffffffffUL)            /*!< AESKEY15 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  AESKEY16  ======================================================== */
#define CRYPTO_AESKEY16_AESKEY16_Pos      (0UL)                     /*!< AESKEY16 (Bit 0)                                      */
#define CRYPTO_AESKEY16_AESKEY16_Msk      (0xffffffffUL)            /*!< AESKEY16 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  AESKEY17  ======================================================== */
#define CRYPTO_AESKEY17_AESKEY17_Pos      (0UL)                     /*!< AESKEY17 (Bit 0)                                      */
#define CRYPTO_AESKEY17_AESKEY17_Msk      (0xffffffffUL)            /*!< AESKEY17 (Bitfield-Mask: 0xffffffff)                  */
/* ========================================================  AESIV00  ======================================================== */
#define CRYPTO_AESIV00_AESIV00_Pos        (0UL)                     /*!< AESIV00 (Bit 0)                                       */
#define CRYPTO_AESIV00_AESIV00_Msk        (0xffffffffUL)            /*!< AESIV00 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  AESIV01  ======================================================== */
#define CRYPTO_AESIV01_AESIV01_Pos        (0UL)                     /*!< AESIV01 (Bit 0)                                       */
#define CRYPTO_AESIV01_AESIV01_Msk        (0xffffffffUL)            /*!< AESIV01 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  AESIV02  ======================================================== */
#define CRYPTO_AESIV02_AESIV02_Pos        (0UL)                     /*!< AESIV02 (Bit 0)                                       */
#define CRYPTO_AESIV02_AESIV02_Msk        (0xffffffffUL)            /*!< AESIV02 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  AESIV03  ======================================================== */
#define CRYPTO_AESIV03_AESIV03_Pos        (0UL)                     /*!< AESIV03 (Bit 0)                                       */
#define CRYPTO_AESIV03_AESIV03_Msk        (0xffffffffUL)            /*!< AESIV03 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  AESIV10  ======================================================== */
#define CRYPTO_AESIV10_AESIV10_Pos        (0UL)                     /*!< AESIV10 (Bit 0)                                       */
#define CRYPTO_AESIV10_AESIV10_Msk        (0xffffffffUL)            /*!< AESIV10 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  AESIV11  ======================================================== */
#define CRYPTO_AESIV11_AESIV11_Pos        (0UL)                     /*!< AESIV11 (Bit 0)                                       */
#define CRYPTO_AESIV11_AESIV11_Msk        (0xffffffffUL)            /*!< AESIV11 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  AESIV12  ======================================================== */
#define CRYPTO_AESIV12_AESIV12_Pos        (0UL)                     /*!< AESIV12 (Bit 0)                                       */
#define CRYPTO_AESIV12_AESIV12_Msk        (0xffffffffUL)            /*!< AESIV12 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  AESIV13  ======================================================== */
#define CRYPTO_AESIV13_AESIV13_Pos        (0UL)                     /*!< AESIV13 (Bit 0)                                       */
#define CRYPTO_AESIV13_AESIV13_Msk        (0xffffffffUL)            /*!< AESIV13 (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  AESCTR00  ======================================================== */
#define CRYPTO_AESCTR00_AESCTR00_Pos      (0UL)                     /*!< AESCTR00 (Bit 0)                                      */
#define CRYPTO_AESCTR00_AESCTR00_Msk      (0xffffffffUL)            /*!< AESCTR00 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  AESCTR01  ======================================================== */
#define CRYPTO_AESCTR01_AESCTR01_Pos      (0UL)                     /*!< AESCTR01 (Bit 0)                                      */
#define CRYPTO_AESCTR01_AESCTR01_Msk      (0xffffffffUL)            /*!< AESCTR01 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  AESCTR02  ======================================================== */
#define CRYPTO_AESCTR02_AESCTR02_Pos      (0UL)                     /*!< AESCTR02 (Bit 0)                                      */
#define CRYPTO_AESCTR02_AESCTR02_Msk      (0xffffffffUL)            /*!< AESCTR02 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  AESCTR03  ======================================================== */
#define CRYPTO_AESCTR03_AESCTR03_Pos      (0UL)                     /*!< AESCTR03 (Bit 0)                                      */
#define CRYPTO_AESCTR03_AESCTR03_Msk      (0xffffffffUL)            /*!< AESCTR03 (Bitfield-Mask: 0xffffffff)                  */
/* ========================================================  AESBUSY  ======================================================== */
#define CRYPTO_AESBUSY_AESBUSY_Pos        (0UL)                     /*!< AESBUSY (Bit 0)                                       */
#define CRYPTO_AESBUSY_AESBUSY_Msk        (0x1UL)                   /*!< AESBUSY (Bitfield-Mask: 0x01)                         */
/* =========================================================  AESSK  ========================================================= */
#define CRYPTO_AESSK_AESSK_Pos            (0UL)                     /*!< AESSK (Bit 0)                                         */
#define CRYPTO_AESSK_AESSK_Msk            (0x1UL)                   /*!< AESSK (Bitfield-Mask: 0x01)                           */
/* ======================================================  AESCMACINIT  ====================================================== */
#define CRYPTO_AESCMACINIT_AESCMACINIT_Pos (0UL)                    /*!< AESCMACINIT (Bit 0)                                   */
#define CRYPTO_AESCMACINIT_AESCMACINIT_Msk (0x1UL)                  /*!< AESCMACINIT (Bitfield-Mask: 0x01)                     */
/* ========================================================  AESSK1  ========================================================= */
#define CRYPTO_AESSK1_AESSK1_Pos          (0UL)                     /*!< AESSK1 (Bit 0)                                        */
#define CRYPTO_AESSK1_AESSK1_Msk          (0x1UL)                   /*!< AESSK1 (Bitfield-Mask: 0x01)                          */
/* ===================================================  AESREMAININGBYTES  =================================================== */
#define CRYPTO_AESREMAININGBYTES_AESREMAININGBYTES_Pos (0UL)        /*!< AESREMAININGBYTES (Bit 0)                             */
#define CRYPTO_AESREMAININGBYTES_AESREMAININGBYTES_Msk (0xffffffffUL) /*!< AESREMAININGBYTES (Bitfield-Mask: 0xffffffff)       */
/* ======================================================  AESCONTROL  ======================================================= */
#define CRYPTO_AESCONTROL_DIRECTACCESS_Pos (31UL)                   /*!< DIRECTACCESS (Bit 31)                                 */
#define CRYPTO_AESCONTROL_DIRECTACCESS_Msk (0x80000000UL)           /*!< DIRECTACCESS (Bitfield-Mask: 0x01)                    */
#define CRYPTO_AESCONTROL_AESXORCRYPTOKEY_Pos (29UL)                /*!< AESXORCRYPTOKEY (Bit 29)                              */
#define CRYPTO_AESCONTROL_AESXORCRYPTOKEY_Msk (0x20000000UL)        /*!< AESXORCRYPTOKEY (Bitfield-Mask: 0x01)                 */
#define CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH_Pos (28UL)             /*!< AESOUTMIDTUNTOHASH (Bit 28)                           */
#define CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH_Msk (0x10000000UL)     /*!< AESOUTMIDTUNTOHASH (Bitfield-Mask: 0x01)              */
#define CRYPTO_AESCONTROL_AESTUNNELB1PADEN_Pos (26UL)               /*!< AESTUNNELB1PADEN (Bit 26)                             */
#define CRYPTO_AESCONTROL_AESTUNNELB1PADEN_Msk (0x4000000UL)        /*!< AESTUNNELB1PADEN (Bitfield-Mask: 0x01)                */
#define CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA_Pos (25UL)         /*!< AESOUTPUTMIDTUNNELDATA (Bit 25)                       */
#define CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA_Msk (0x2000000UL)  /*!< AESOUTPUTMIDTUNNELDATA (Bitfield-Mask: 0x01)          */
#define CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT_Pos (24UL)              /*!< AESTUNNEL0ENCRYPT (Bit 24)                            */
#define CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT_Msk (0x1000000UL)       /*!< AESTUNNEL0ENCRYPT (Bitfield-Mask: 0x01)               */
#define CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN_Pos (23UL)       /*!< AESTUNB1USESPADDEDDATAIN (Bit 23)                     */
#define CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN_Msk (0x800000UL) /*!< AESTUNB1USESPADDEDDATAIN (Bitfield-Mask: 0x01)        */
#define CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT_Pos (22UL)              /*!< AESTUNNEL1DECRYPT (Bit 22)                            */
#define CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT_Msk (0x400000UL)        /*!< AESTUNNEL1DECRYPT (Bitfield-Mask: 0x01)               */
#define CRYPTO_AESCONTROL_NKKEY1_Pos      (14UL)                    /*!< NKKEY1 (Bit 14)                                       */
#define CRYPTO_AESCONTROL_NKKEY1_Msk      (0xc000UL)                /*!< NKKEY1 (Bitfield-Mask: 0x03)                          */
#define CRYPTO_AESCONTROL_NKKEY0_Pos      (12UL)                    /*!< NKKEY0 (Bit 12)                                       */
#define CRYPTO_AESCONTROL_NKKEY0_Msk      (0x3000UL)                /*!< NKKEY0 (Bitfield-Mask: 0x03)                          */
#define CRYPTO_AESCONTROL_CBCISBITLOCKER_Pos (11UL)                 /*!< CBCISBITLOCKER (Bit 11)                               */
#define CRYPTO_AESCONTROL_CBCISBITLOCKER_Msk (0x800UL)              /*!< CBCISBITLOCKER (Bitfield-Mask: 0x01)                  */
#define CRYPTO_AESCONTROL_AESTUNNELISON_Pos (10UL)                  /*!< AESTUNNELISON (Bit 10)                                */
#define CRYPTO_AESCONTROL_AESTUNNELISON_Msk (0x400UL)               /*!< AESTUNNELISON (Bitfield-Mask: 0x01)                   */
#define CRYPTO_AESCONTROL_CBCISESSIV_Pos  (8UL)                     /*!< CBCISESSIV (Bit 8)                                    */
#define CRYPTO_AESCONTROL_CBCISESSIV_Msk  (0x100UL)                 /*!< CBCISESSIV (Bitfield-Mask: 0x01)                      */
#define CRYPTO_AESCONTROL_MODEKEY1_Pos    (5UL)                     /*!< MODEKEY1 (Bit 5)                                      */
#define CRYPTO_AESCONTROL_MODEKEY1_Msk    (0xe0UL)                  /*!< MODEKEY1 (Bitfield-Mask: 0x07)                        */
#define CRYPTO_AESCONTROL_MODEKEY0_Pos    (2UL)                     /*!< MODEKEY0 (Bit 2)                                      */
#define CRYPTO_AESCONTROL_MODEKEY0_Msk    (0x1cUL)                  /*!< MODEKEY0 (Bitfield-Mask: 0x07)                        */
#define CRYPTO_AESCONTROL_MODE0ISCBCCTS_Pos (1UL)                   /*!< MODE0ISCBCCTS (Bit 1)                                 */
#define CRYPTO_AESCONTROL_MODE0ISCBCCTS_Msk (0x2UL)                 /*!< MODE0ISCBCCTS (Bitfield-Mask: 0x01)                   */
#define CRYPTO_AESCONTROL_DECKEY0_Pos     (0UL)                     /*!< DECKEY0 (Bit 0)                                       */
#define CRYPTO_AESCONTROL_DECKEY0_Msk     (0x1UL)                   /*!< DECKEY0 (Bitfield-Mask: 0x01)                         */
/* ======================================================  AESHWFLAGS  ======================================================= */
#define CRYPTO_AESHWFLAGS_DFACNTRMSREXIST_Pos (12UL)                /*!< DFACNTRMSREXIST (Bit 12)                              */
#define CRYPTO_AESHWFLAGS_DFACNTRMSREXIST_Msk (0x1000UL)            /*!< DFACNTRMSREXIST (Bitfield-Mask: 0x01)                 */
#define CRYPTO_AESHWFLAGS_SECONDREGSSETEXIST_Pos (11UL)             /*!< SECONDREGSSETEXIST (Bit 11)                           */
#define CRYPTO_AESHWFLAGS_SECONDREGSSETEXIST_Msk (0x800UL)          /*!< SECONDREGSSETEXIST (Bitfield-Mask: 0x01)              */
#define CRYPTO_AESHWFLAGS_aestunnelexists_Pos (10UL)                /*!< aestunnelexists (Bit 10)                              */
#define CRYPTO_AESHWFLAGS_aestunnelexists_Msk (0x400UL)             /*!< aestunnelexists (Bitfield-Mask: 0x01)                 */
#define CRYPTO_AESHWFLAGS_AESSUPPORTPREVIV_Pos (9UL)                /*!< AESSUPPORTPREVIV (Bit 9)                              */
#define CRYPTO_AESHWFLAGS_AESSUPPORTPREVIV_Msk (0x200UL)            /*!< AESSUPPORTPREVIV (Bitfield-Mask: 0x01)                */
#define CRYPTO_AESHWFLAGS_USE5SBOXES_Pos  (8UL)                     /*!< USE5SBOXES (Bit 8)                                    */
#define CRYPTO_AESHWFLAGS_USE5SBOXES_Msk  (0x100UL)                 /*!< USE5SBOXES (Bitfield-Mask: 0x01)                      */
#define CRYPTO_AESHWFLAGS_USESBOXTABLE_Pos (5UL)                    /*!< USESBOXTABLE (Bit 5)                                  */
#define CRYPTO_AESHWFLAGS_USESBOXTABLE_Msk (0x20UL)                 /*!< USESBOXTABLE (Bitfield-Mask: 0x01)                    */
#define CRYPTO_AESHWFLAGS_ONLYENCRYPT_Pos (4UL)                     /*!< ONLYENCRYPT (Bit 4)                                   */
#define CRYPTO_AESHWFLAGS_ONLYENCRYPT_Msk (0x10UL)                  /*!< ONLYENCRYPT (Bitfield-Mask: 0x01)                     */
#define CRYPTO_AESHWFLAGS_CTREXIST_Pos    (3UL)                     /*!< CTREXIST (Bit 3)                                      */
#define CRYPTO_AESHWFLAGS_CTREXIST_Msk    (0x8UL)                   /*!< CTREXIST (Bitfield-Mask: 0x01)                        */
#define CRYPTO_AESHWFLAGS_DPACNTRMSREXIST_Pos (2UL)                 /*!< DPACNTRMSREXIST (Bit 2)                               */
#define CRYPTO_AESHWFLAGS_DPACNTRMSREXIST_Msk (0x4UL)               /*!< DPACNTRMSREXIST (Bitfield-Mask: 0x01)                 */
#define CRYPTO_AESHWFLAGS_AESLARGERKEK_Pos (1UL)                    /*!< AESLARGERKEK (Bit 1)                                  */
#define CRYPTO_AESHWFLAGS_AESLARGERKEK_Msk (0x2UL)                  /*!< AESLARGERKEK (Bitfield-Mask: 0x01)                    */
#define CRYPTO_AESHWFLAGS_SUPPORT256192KEY_Pos (0UL)                /*!< SUPPORT256192KEY (Bit 0)                              */
#define CRYPTO_AESHWFLAGS_SUPPORT256192KEY_Msk (0x1UL)              /*!< SUPPORT256192KEY (Bitfield-Mask: 0x01)                */
/* ===================================================  AESCTRNOINCREMENT  =================================================== */
#define CRYPTO_AESCTRNOINCREMENT_AESCTRNOINCREMENT_Pos (0UL)        /*!< AESCTRNOINCREMENT (Bit 0)                             */
#define CRYPTO_AESCTRNOINCREMENT_AESCTRNOINCREMENT_Msk (0x1UL)      /*!< AESCTRNOINCREMENT (Bitfield-Mask: 0x01)               */
/* ======================================================  AESDFAISON  ======================================================= */
#define CRYPTO_AESDFAISON_AESDFAISON_Pos  (0UL)                     /*!< AESDFAISON (Bit 0)                                    */
#define CRYPTO_AESDFAISON_AESDFAISON_Msk  (0x1UL)                   /*!< AESDFAISON (Bitfield-Mask: 0x01)                      */
/* ====================================================  AESDFAERRSTATUS  ==================================================== */
#define CRYPTO_AESDFAERRSTATUS_AESDFAERRSTATUS_Pos (0UL)            /*!< AESDFAERRSTATUS (Bit 0)                               */
#define CRYPTO_AESDFAERRSTATUS_AESDFAERRSTATUS_Msk (0x1UL)          /*!< AESDFAERRSTATUS (Bitfield-Mask: 0x01)                 */
/* ===================================================  AESCMACSIZE0KICK  ==================================================== */
#define CRYPTO_AESCMACSIZE0KICK_AESCMACSIZE0KICK_Pos (0UL)          /*!< AESCMACSIZE0KICK (Bit 0)                              */
#define CRYPTO_AESCMACSIZE0KICK_AESCMACSIZE0KICK_Msk (0x1UL)        /*!< AESCMACSIZE0KICK (Bitfield-Mask: 0x01)                */
/* ========================================================  HASHH0  ========================================================= */
#define CRYPTO_HASHH0_HASHH0_Pos          (0UL)                     /*!< HASHH0 (Bit 0)                                        */
#define CRYPTO_HASHH0_HASHH0_Msk          (0xffffffffUL)            /*!< HASHH0 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  HASHH1  ========================================================= */
#define CRYPTO_HASHH1_HASHH1_Pos          (0UL)                     /*!< HASHH1 (Bit 0)                                        */
#define CRYPTO_HASHH1_HASHH1_Msk          (0xffffffffUL)            /*!< HASHH1 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  HASHH2  ========================================================= */
#define CRYPTO_HASHH2_HASHH2_Pos          (0UL)                     /*!< HASHH2 (Bit 0)                                        */
#define CRYPTO_HASHH2_HASHH2_Msk          (0xffffffffUL)            /*!< HASHH2 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  HASHH3  ========================================================= */
#define CRYPTO_HASHH3_HASHH3_Pos          (0UL)                     /*!< HASHH3 (Bit 0)                                        */
#define CRYPTO_HASHH3_HASHH3_Msk          (0xffffffffUL)            /*!< HASHH3 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  HASHH4  ========================================================= */
#define CRYPTO_HASHH4_HASHH4_Pos          (0UL)                     /*!< HASHH4 (Bit 0)                                        */
#define CRYPTO_HASHH4_HASHH4_Msk          (0xffffffffUL)            /*!< HASHH4 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  HASHH5  ========================================================= */
#define CRYPTO_HASHH5_HASHH5_Pos          (0UL)                     /*!< HASHH5 (Bit 0)                                        */
#define CRYPTO_HASHH5_HASHH5_Msk          (0xffffffffUL)            /*!< HASHH5 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  HASHH6  ========================================================= */
#define CRYPTO_HASHH6_HASHH6_Pos          (0UL)                     /*!< HASHH6 (Bit 0)                                        */
#define CRYPTO_HASHH6_HASHH6_Msk          (0xffffffffUL)            /*!< HASHH6 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  HASHH7  ========================================================= */
#define CRYPTO_HASHH7_HASHH7_Pos          (0UL)                     /*!< HASHH7 (Bit 0)                                        */
#define CRYPTO_HASHH7_HASHH7_Msk          (0xffffffffUL)            /*!< HASHH7 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  HASHH8  ========================================================= */
#define CRYPTO_HASHH8_HASHH8_Pos          (0UL)                     /*!< HASHH8 (Bit 0)                                        */
#define CRYPTO_HASHH8_HASHH8_Msk          (0xffffffffUL)            /*!< HASHH8 (Bitfield-Mask: 0xffffffff)                    */
/* =====================================================  AUTOHWPADDING  ===================================================== */
#define CRYPTO_AUTOHWPADDING_EN_Pos       (0UL)                     /*!< EN (Bit 0)                                            */
#define CRYPTO_AUTOHWPADDING_EN_Msk       (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ======================================================  HASHXORDIN  ======================================================= */
#define CRYPTO_HASHXORDIN_HASHXORDATA_Pos (0UL)                     /*!< HASHXORDATA (Bit 0)                                   */
#define CRYPTO_HASHXORDIN_HASHXORDATA_Msk (0xffffffffUL)            /*!< HASHXORDATA (Bitfield-Mask: 0xffffffff)               */
/* =====================================================  LOADINITSTATE  ===================================================== */
#define CRYPTO_LOADINITSTATE_LOAD_Pos     (0UL)                     /*!< LOAD (Bit 0)                                          */
#define CRYPTO_LOADINITSTATE_LOAD_Msk     (0x1UL)                   /*!< LOAD (Bitfield-Mask: 0x01)                            */
/* =====================================================  HASHSELAESMAC  ===================================================== */
#define CRYPTO_HASHSELAESMAC_GHASHSEL_Pos (1UL)                     /*!< GHASHSEL (Bit 1)                                      */
#define CRYPTO_HASHSELAESMAC_GHASHSEL_Msk (0x2UL)                   /*!< GHASHSEL (Bitfield-Mask: 0x01)                        */
#define CRYPTO_HASHSELAESMAC_HASHSELAESMAC_Pos (0UL)                /*!< HASHSELAESMAC (Bit 0)                                 */
#define CRYPTO_HASHSELAESMAC_HASHSELAESMAC_Msk (0x1UL)              /*!< HASHSELAESMAC (Bitfield-Mask: 0x01)                   */
/* ======================================================  HASHVERSION  ====================================================== */
#define CRYPTO_HASHVERSION_MAJORVERSIONNUMBER_Pos (12UL)            /*!< MAJORVERSIONNUMBER (Bit 12)                           */
#define CRYPTO_HASHVERSION_MAJORVERSIONNUMBER_Msk (0xf000UL)        /*!< MAJORVERSIONNUMBER (Bitfield-Mask: 0x0f)              */
#define CRYPTO_HASHVERSION_MINORVERSIONNUMBER_Pos (8UL)             /*!< MINORVERSIONNUMBER (Bit 8)                            */
#define CRYPTO_HASHVERSION_MINORVERSIONNUMBER_Msk (0xf00UL)         /*!< MINORVERSIONNUMBER (Bitfield-Mask: 0x0f)              */
#define CRYPTO_HASHVERSION_FIXES_Pos      (0UL)                     /*!< FIXES (Bit 0)                                         */
#define CRYPTO_HASHVERSION_FIXES_Msk      (0xffUL)                  /*!< FIXES (Bitfield-Mask: 0xff)                           */
/* ======================================================  HASHCONTROL  ====================================================== */
#define CRYPTO_HASHCONTROL_MODE3_Pos      (3UL)                     /*!< MODE3 (Bit 3)                                         */
#define CRYPTO_HASHCONTROL_MODE3_Msk      (0x8UL)                   /*!< MODE3 (Bitfield-Mask: 0x01)                           */
#define CRYPTO_HASHCONTROL_MODE01_Pos     (0UL)                     /*!< MODE01 (Bit 0)                                        */
#define CRYPTO_HASHCONTROL_MODE01_Msk     (0x3UL)                   /*!< MODE01 (Bitfield-Mask: 0x03)                          */
/* =======================================================  HASHPADEN  ======================================================= */
#define CRYPTO_HASHPADEN_EN_Pos           (0UL)                     /*!< EN (Bit 0)                                            */
#define CRYPTO_HASHPADEN_EN_Msk           (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ======================================================  HASHPADCFG  ======================================================= */
#define CRYPTO_HASHPADCFG_DOPAD_Pos       (2UL)                     /*!< DOPAD (Bit 2)                                         */
#define CRYPTO_HASHPADCFG_DOPAD_Msk       (0x4UL)                   /*!< DOPAD (Bitfield-Mask: 0x01)                           */
/* ======================================================  HASHCURLEN0  ====================================================== */
#define CRYPTO_HASHCURLEN0_Length_Pos     (0UL)                     /*!< Length (Bit 0)                                        */
#define CRYPTO_HASHCURLEN0_Length_Msk     (0xffffffffUL)            /*!< Length (Bitfield-Mask: 0xffffffff)                    */
/* ======================================================  HASHCURLEN1  ====================================================== */
#define CRYPTO_HASHCURLEN1_Length_Pos     (0UL)                     /*!< Length (Bit 0)                                        */
#define CRYPTO_HASHCURLEN1_Length_Msk     (0xffffffffUL)            /*!< Length (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  HASHPARAM  ======================================================= */
#define CRYPTO_HASHPARAM_DUMPHASHTODOUTEXISTS_Pos (18UL)            /*!< DUMPHASHTODOUTEXISTS (Bit 18)                         */
#define CRYPTO_HASHPARAM_DUMPHASHTODOUTEXISTS_Msk (0x40000UL)       /*!< DUMPHASHTODOUTEXISTS (Bitfield-Mask: 0x01)            */
#define CRYPTO_HASHPARAM_HASHCOMPAREEXISTS_Pos (17UL)               /*!< HASHCOMPAREEXISTS (Bit 17)                            */
#define CRYPTO_HASHPARAM_HASHCOMPAREEXISTS_Msk (0x20000UL)          /*!< HASHCOMPAREEXISTS (Bitfield-Mask: 0x01)               */
#define CRYPTO_HASHPARAM_SHA256EXISTS_Pos (16UL)                    /*!< SHA256EXISTS (Bit 16)                                 */
#define CRYPTO_HASHPARAM_SHA256EXISTS_Msk (0x10000UL)               /*!< SHA256EXISTS (Bitfield-Mask: 0x01)                    */
#define CRYPTO_HASHPARAM_HMACEXISTS_Pos   (15UL)                    /*!< HMACEXISTS (Bit 15)                                   */
#define CRYPTO_HASHPARAM_HMACEXISTS_Msk   (0x8000UL)                /*!< HMACEXISTS (Bitfield-Mask: 0x01)                      */
#define CRYPTO_HASHPARAM_MD5EXISTS_Pos    (14UL)                    /*!< MD5EXISTS (Bit 14)                                    */
#define CRYPTO_HASHPARAM_MD5EXISTS_Msk    (0x4000UL)                /*!< MD5EXISTS (Bitfield-Mask: 0x01)                       */
#define CRYPTO_HASHPARAM_PADEXISTS_Pos    (13UL)                    /*!< PADEXISTS (Bit 13)                                    */
#define CRYPTO_HASHPARAM_PADEXISTS_Msk    (0x2000UL)                /*!< PADEXISTS (Bitfield-Mask: 0x01)                       */
#define CRYPTO_HASHPARAM_SHA512EXISTS_Pos (12UL)                    /*!< SHA512EXISTS (Bit 12)                                 */
#define CRYPTO_HASHPARAM_SHA512EXISTS_Msk (0x1000UL)                /*!< SHA512EXISTS (Bitfield-Mask: 0x01)                    */
#define CRYPTO_HASHPARAM_DW_Pos           (8UL)                     /*!< DW (Bit 8)                                            */
#define CRYPTO_HASHPARAM_DW_Msk           (0xf00UL)                 /*!< DW (Bitfield-Mask: 0x0f)                              */
#define CRYPTO_HASHPARAM_CH_Pos           (4UL)                     /*!< CH (Bit 4)                                            */
#define CRYPTO_HASHPARAM_CH_Msk           (0xf0UL)                  /*!< CH (Bitfield-Mask: 0x0f)                              */
#define CRYPTO_HASHPARAM_CW_Pos           (0UL)                     /*!< CW (Bit 0)                                            */
#define CRYPTO_HASHPARAM_CW_Msk           (0xfUL)                   /*!< CW (Bitfield-Mask: 0x0f)                              */
/* ====================================================  HASHAESSWRESET  ===================================================== */
#define CRYPTO_HASHAESSWRESET_HASHAESSWRESET_Pos (0UL)              /*!< HASHAESSWRESET (Bit 0)                                */
#define CRYPTO_HASHAESSWRESET_HASHAESSWRESET_Msk (0x1UL)            /*!< HASHAESSWRESET (Bitfield-Mask: 0x01)                  */
/* =====================================================  HASHENDIANESS  ===================================================== */
#define CRYPTO_HASHENDIANESS_ENDIAN_Pos   (0UL)                     /*!< ENDIAN (Bit 0)                                        */
#define CRYPTO_HASHENDIANESS_ENDIAN_Msk   (0x1UL)                   /*!< ENDIAN (Bitfield-Mask: 0x01)                          */
/* =====================================================  AESCLKENABLE  ====================================================== */
#define CRYPTO_AESCLKENABLE_EN_Pos        (0UL)                     /*!< EN (Bit 0)                                            */
#define CRYPTO_AESCLKENABLE_EN_Msk        (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =====================================================  HASHCLKENABLE  ===================================================== */
#define CRYPTO_HASHCLKENABLE_EN_Pos       (0UL)                     /*!< EN (Bit 0)                                            */
#define CRYPTO_HASHCLKENABLE_EN_Msk       (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =====================================================  PKACLKENABLE  ====================================================== */
#define CRYPTO_PKACLKENABLE_EN_Pos        (0UL)                     /*!< EN (Bit 0)                                            */
#define CRYPTO_PKACLKENABLE_EN_Msk        (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =====================================================  DMACLKENABLE  ====================================================== */
#define CRYPTO_DMACLKENABLE_EN_Pos        (0UL)                     /*!< EN (Bit 0)                                            */
#define CRYPTO_DMACLKENABLE_EN_Msk        (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =======================================================  CLKSTATUS  ======================================================= */
#define CRYPTO_CLKSTATUS_DMACLKSTATUS_Pos (8UL)                     /*!< DMACLKSTATUS (Bit 8)                                  */
#define CRYPTO_CLKSTATUS_DMACLKSTATUS_Msk (0x100UL)                 /*!< DMACLKSTATUS (Bitfield-Mask: 0x01)                    */
#define CRYPTO_CLKSTATUS_CHACHACLKSTATUS_Pos (7UL)                  /*!< CHACHACLKSTATUS (Bit 7)                               */
#define CRYPTO_CLKSTATUS_CHACHACLKSTATUS_Msk (0x80UL)               /*!< CHACHACLKSTATUS (Bitfield-Mask: 0x01)                 */
#define CRYPTO_CLKSTATUS_PKACLKSTATUS_Pos (3UL)                     /*!< PKACLKSTATUS (Bit 3)                                  */
#define CRYPTO_CLKSTATUS_PKACLKSTATUS_Msk (0x8UL)                   /*!< PKACLKSTATUS (Bitfield-Mask: 0x01)                    */
#define CRYPTO_CLKSTATUS_HASHCLKSTATUS_Pos (2UL)                    /*!< HASHCLKSTATUS (Bit 2)                                 */
#define CRYPTO_CLKSTATUS_HASHCLKSTATUS_Msk (0x4UL)                  /*!< HASHCLKSTATUS (Bitfield-Mask: 0x01)                   */
#define CRYPTO_CLKSTATUS_AESCLKSTATUS_Pos (0UL)                     /*!< AESCLKSTATUS (Bit 0)                                  */
#define CRYPTO_CLKSTATUS_AESCLKSTATUS_Msk (0x1UL)                   /*!< AESCLKSTATUS (Bitfield-Mask: 0x01)                    */
/* ====================================================  CHACHACLKENABLE  ==================================================== */
#define CRYPTO_CHACHACLKENABLE_EN_Pos     (0UL)                     /*!< EN (Bit 0)                                            */
#define CRYPTO_CHACHACLKENABLE_EN_Msk     (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =======================================================  CRYPTOCTL  ======================================================= */
#define CRYPTO_CRYPTOCTL_MODE_Pos         (0UL)                     /*!< MODE (Bit 0)                                          */
#define CRYPTO_CRYPTOCTL_MODE_Msk         (0x1fUL)                  /*!< MODE (Bitfield-Mask: 0x1f)                            */
/* ======================================================  CRYPTOBUSY  ======================================================= */
#define CRYPTO_CRYPTOBUSY_CRYPTOBUSY_Pos  (0UL)                     /*!< CRYPTOBUSY (Bit 0)                                    */
#define CRYPTO_CRYPTOBUSY_CRYPTOBUSY_Msk  (0x1UL)                   /*!< CRYPTOBUSY (Bitfield-Mask: 0x01)                      */
/* =======================================================  HASHBUSY  ======================================================== */
#define CRYPTO_HASHBUSY_HASHBUSY_Pos      (0UL)                     /*!< HASHBUSY (Bit 0)                                      */
#define CRYPTO_HASHBUSY_HASHBUSY_Msk      (0x1UL)                   /*!< HASHBUSY (Bitfield-Mask: 0x01)                        */
/* =======================================================  CONTEXTID  ======================================================= */
#define CRYPTO_CONTEXTID_CONTEXTID_Pos    (0UL)                     /*!< CONTEXTID (Bit 0)                                     */
#define CRYPTO_CONTEXTID_CONTEXTID_Msk    (0xffUL)                  /*!< CONTEXTID (Bitfield-Mask: 0xff)                       */
/* =====================================================  GHASHSUBKEY00  ===================================================== */
#define CRYPTO_GHASHSUBKEY00_GHASHSUBKEY00_Pos (0UL)                /*!< GHASHSUBKEY00 (Bit 0)                                 */
#define CRYPTO_GHASHSUBKEY00_GHASHSUBKEY00_Msk (0xffffffffUL)       /*!< GHASHSUBKEY00 (Bitfield-Mask: 0xffffffff)             */
/* =====================================================  GHASHSUBKEY01  ===================================================== */
#define CRYPTO_GHASHSUBKEY01_GHASHSUBKEY01_Pos (0UL)                /*!< GHASHSUBKEY01 (Bit 0)                                 */
#define CRYPTO_GHASHSUBKEY01_GHASHSUBKEY01_Msk (0xffffffffUL)       /*!< GHASHSUBKEY01 (Bitfield-Mask: 0xffffffff)             */
/* =====================================================  GHASHSUBKEY02  ===================================================== */
#define CRYPTO_GHASHSUBKEY02_GHASHSUBKEY02_Pos (0UL)                /*!< GHASHSUBKEY02 (Bit 0)                                 */
#define CRYPTO_GHASHSUBKEY02_GHASHSUBKEY02_Msk (0xffffffffUL)       /*!< GHASHSUBKEY02 (Bitfield-Mask: 0xffffffff)             */
/* =====================================================  GHASHSUBKEY03  ===================================================== */
#define CRYPTO_GHASHSUBKEY03_GHASHSUBKEY03_Pos (0UL)                /*!< GHASHSUBKEY03 (Bit 0)                                 */
#define CRYPTO_GHASHSUBKEY03_GHASHSUBKEY03_Msk (0xffffffffUL)       /*!< GHASHSUBKEY03 (Bitfield-Mask: 0xffffffff)             */
/* =======================================================  GHASHIV00  ======================================================= */
#define CRYPTO_GHASHIV00_GHASHIV00_Pos    (0UL)                     /*!< GHASHIV00 (Bit 0)                                     */
#define CRYPTO_GHASHIV00_GHASHIV00_Msk    (0xffffffffUL)            /*!< GHASHIV00 (Bitfield-Mask: 0xffffffff)                 */
/* =======================================================  GHASHIV01  ======================================================= */
#define CRYPTO_GHASHIV01_GHASHIV01_Pos    (0UL)                     /*!< GHASHIV01 (Bit 0)                                     */
#define CRYPTO_GHASHIV01_GHASHIV01_Msk    (0xffffffffUL)            /*!< GHASHIV01 (Bitfield-Mask: 0xffffffff)                 */
/* =======================================================  GHASHIV02  ======================================================= */
#define CRYPTO_GHASHIV02_GHASHIV02_Pos    (0UL)                     /*!< GHASHIV02 (Bit 0)                                     */
#define CRYPTO_GHASHIV02_GHASHIV02_Msk    (0xffffffffUL)            /*!< GHASHIV02 (Bitfield-Mask: 0xffffffff)                 */
/* =======================================================  GHASHIV03  ======================================================= */
#define CRYPTO_GHASHIV03_GHASHIV03_Pos    (0UL)                     /*!< GHASHIV03 (Bit 0)                                     */
#define CRYPTO_GHASHIV03_GHASHIV03_Msk    (0xffffffffUL)            /*!< GHASHIV03 (Bitfield-Mask: 0xffffffff)                 */
/* =======================================================  GHASHBUSY  ======================================================= */
#define CRYPTO_GHASHBUSY_GHASHBUSY_Pos    (0UL)                     /*!< GHASHBUSY (Bit 0)                                     */
#define CRYPTO_GHASHBUSY_GHASHBUSY_Msk    (0x1UL)                   /*!< GHASHBUSY (Bitfield-Mask: 0x01)                       */
/* =======================================================  GHASHINIT  ======================================================= */
#define CRYPTO_GHASHINIT_GHASHINIT_Pos    (0UL)                     /*!< GHASHINIT (Bit 0)                                     */
#define CRYPTO_GHASHINIT_GHASHINIT_Msk    (0x1UL)                   /*!< GHASHINIT (Bitfield-Mask: 0x01)                       */
/* ======================================================  HOSTRGFIRR  ======================================================= */
#define CRYPTO_HOSTRGFIRR_SYMDMACOMPLETED_Pos (11UL)                /*!< SYMDMACOMPLETED (Bit 11)                              */
#define CRYPTO_HOSTRGFIRR_SYMDMACOMPLETED_Msk (0x800UL)             /*!< SYMDMACOMPLETED (Bitfield-Mask: 0x01)                 */
#define CRYPTO_HOSTRGFIRR_RNGINT_Pos      (10UL)                    /*!< RNGINT (Bit 10)                                       */
#define CRYPTO_HOSTRGFIRR_RNGINT_Msk      (0x400UL)                 /*!< RNGINT (Bitfield-Mask: 0x01)                          */
#define CRYPTO_HOSTRGFIRR_PKAEXPINT_Pos   (9UL)                     /*!< PKAEXPINT (Bit 9)                                     */
#define CRYPTO_HOSTRGFIRR_PKAEXPINT_Msk   (0x200UL)                 /*!< PKAEXPINT (Bitfield-Mask: 0x01)                       */
#define CRYPTO_HOSTRGFIRR_AHBERRINT_Pos   (8UL)                     /*!< AHBERRINT (Bit 8)                                     */
#define CRYPTO_HOSTRGFIRR_AHBERRINT_Msk   (0x100UL)                 /*!< AHBERRINT (Bitfield-Mask: 0x01)                       */
#define CRYPTO_HOSTRGFIRR_DOUTTOMEMINT_Pos (7UL)                    /*!< DOUTTOMEMINT (Bit 7)                                  */
#define CRYPTO_HOSTRGFIRR_DOUTTOMEMINT_Msk (0x80UL)                 /*!< DOUTTOMEMINT (Bitfield-Mask: 0x01)                    */
#define CRYPTO_HOSTRGFIRR_MEMTODININT_Pos (6UL)                     /*!< MEMTODININT (Bit 6)                                   */
#define CRYPTO_HOSTRGFIRR_MEMTODININT_Msk (0x40UL)                  /*!< MEMTODININT (Bitfield-Mask: 0x01)                     */
#define CRYPTO_HOSTRGFIRR_DOUTTOSRAMINT_Pos (5UL)                   /*!< DOUTTOSRAMINT (Bit 5)                                 */
#define CRYPTO_HOSTRGFIRR_DOUTTOSRAMINT_Msk (0x20UL)                /*!< DOUTTOSRAMINT (Bitfield-Mask: 0x01)                   */
#define CRYPTO_HOSTRGFIRR_SRAMTODININT_Pos (4UL)                    /*!< SRAMTODININT (Bit 4)                                  */
#define CRYPTO_HOSTRGFIRR_SRAMTODININT_Msk (0x10UL)                 /*!< SRAMTODININT (Bitfield-Mask: 0x01)                    */
/* ======================================================  HOSTRGFIMR  ======================================================= */
#define CRYPTO_HOSTRGFIMR_SYMDMACOMPLETEDMASK_Pos (11UL)            /*!< SYMDMACOMPLETEDMASK (Bit 11)                          */
#define CRYPTO_HOSTRGFIMR_SYMDMACOMPLETEDMASK_Msk (0x800UL)         /*!< SYMDMACOMPLETEDMASK (Bitfield-Mask: 0x01)             */
#define CRYPTO_HOSTRGFIMR_RNGINTMASK_Pos  (10UL)                    /*!< RNGINTMASK (Bit 10)                                   */
#define CRYPTO_HOSTRGFIMR_RNGINTMASK_Msk  (0x400UL)                 /*!< RNGINTMASK (Bitfield-Mask: 0x01)                      */
#define CRYPTO_HOSTRGFIMR_PKAEXPMASK_Pos  (9UL)                     /*!< PKAEXPMASK (Bit 9)                                    */
#define CRYPTO_HOSTRGFIMR_PKAEXPMASK_Msk  (0x200UL)                 /*!< PKAEXPMASK (Bitfield-Mask: 0x01)                      */
#define CRYPTO_HOSTRGFIMR_AXIERRMASK_Pos  (8UL)                     /*!< AXIERRMASK (Bit 8)                                    */
#define CRYPTO_HOSTRGFIMR_AXIERRMASK_Msk  (0x100UL)                 /*!< AXIERRMASK (Bitfield-Mask: 0x01)                      */
#define CRYPTO_HOSTRGFIMR_DOUTTOMEMMASK_Pos (7UL)                   /*!< DOUTTOMEMMASK (Bit 7)                                 */
#define CRYPTO_HOSTRGFIMR_DOUTTOMEMMASK_Msk (0x80UL)                /*!< DOUTTOMEMMASK (Bitfield-Mask: 0x01)                   */
#define CRYPTO_HOSTRGFIMR_MEMTODINMASK_Pos (6UL)                    /*!< MEMTODINMASK (Bit 6)                                  */
#define CRYPTO_HOSTRGFIMR_MEMTODINMASK_Msk (0x40UL)                 /*!< MEMTODINMASK (Bitfield-Mask: 0x01)                    */
#define CRYPTO_HOSTRGFIMR_DOUTTOSRAMMASK_Pos (5UL)                  /*!< DOUTTOSRAMMASK (Bit 5)                                */
#define CRYPTO_HOSTRGFIMR_DOUTTOSRAMMASK_Msk (0x20UL)               /*!< DOUTTOSRAMMASK (Bitfield-Mask: 0x01)                  */
#define CRYPTO_HOSTRGFIMR_SRAMTODINMASK_Pos (4UL)                   /*!< SRAMTODINMASK (Bit 4)                                 */
#define CRYPTO_HOSTRGFIMR_SRAMTODINMASK_Msk (0x10UL)                /*!< SRAMTODINMASK (Bitfield-Mask: 0x01)                   */
/* ======================================================  HOSTRGFICR  ======================================================= */
#define CRYPTO_HOSTRGFICR_SYMDMACOMPLETEDCLEAR_Pos (11UL)           /*!< SYMDMACOMPLETEDCLEAR (Bit 11)                         */
#define CRYPTO_HOSTRGFICR_SYMDMACOMPLETEDCLEAR_Msk (0x800UL)        /*!< SYMDMACOMPLETEDCLEAR (Bitfield-Mask: 0x01)            */
#define CRYPTO_HOSTRGFICR_RNGINTCLEAR_Pos (10UL)                    /*!< RNGINTCLEAR (Bit 10)                                  */
#define CRYPTO_HOSTRGFICR_RNGINTCLEAR_Msk (0x400UL)                 /*!< RNGINTCLEAR (Bitfield-Mask: 0x01)                     */
#define CRYPTO_HOSTRGFICR_PKAEXPCLEAR_Pos (9UL)                     /*!< PKAEXPCLEAR (Bit 9)                                   */
#define CRYPTO_HOSTRGFICR_PKAEXPCLEAR_Msk (0x200UL)                 /*!< PKAEXPCLEAR (Bitfield-Mask: 0x01)                     */
#define CRYPTO_HOSTRGFICR_AXIERRCLEAR_Pos (8UL)                     /*!< AXIERRCLEAR (Bit 8)                                   */
#define CRYPTO_HOSTRGFICR_AXIERRCLEAR_Msk (0x100UL)                 /*!< AXIERRCLEAR (Bitfield-Mask: 0x01)                     */
#define CRYPTO_HOSTRGFICR_DOUTTOMEMCLEAR_Pos (7UL)                  /*!< DOUTTOMEMCLEAR (Bit 7)                                */
#define CRYPTO_HOSTRGFICR_DOUTTOMEMCLEAR_Msk (0x80UL)               /*!< DOUTTOMEMCLEAR (Bitfield-Mask: 0x01)                  */
#define CRYPTO_HOSTRGFICR_MEMTODINCLEAR_Pos (6UL)                   /*!< MEMTODINCLEAR (Bit 6)                                 */
#define CRYPTO_HOSTRGFICR_MEMTODINCLEAR_Msk (0x40UL)                /*!< MEMTODINCLEAR (Bitfield-Mask: 0x01)                   */
#define CRYPTO_HOSTRGFICR_DOUTTOSRAMCLEAR_Pos (5UL)                 /*!< DOUTTOSRAMCLEAR (Bit 5)                               */
#define CRYPTO_HOSTRGFICR_DOUTTOSRAMCLEAR_Msk (0x20UL)              /*!< DOUTTOSRAMCLEAR (Bitfield-Mask: 0x01)                 */
#define CRYPTO_HOSTRGFICR_SRAMTODINCLEAR_Pos (4UL)                  /*!< SRAMTODINCLEAR (Bit 4)                                */
#define CRYPTO_HOSTRGFICR_SRAMTODINCLEAR_Msk (0x10UL)               /*!< SRAMTODINCLEAR (Bitfield-Mask: 0x01)                  */
/* =====================================================  HOSTRGFENDIAN  ===================================================== */
#define CRYPTO_HOSTRGFENDIAN_DINRDWBG_Pos (15UL)                    /*!< DINRDWBG (Bit 15)                                     */
#define CRYPTO_HOSTRGFENDIAN_DINRDWBG_Msk (0x8000UL)                /*!< DINRDWBG (Bitfield-Mask: 0x01)                        */
#define CRYPTO_HOSTRGFENDIAN_DOUTWRWBG_Pos (11UL)                   /*!< DOUTWRWBG (Bit 11)                                    */
#define CRYPTO_HOSTRGFENDIAN_DOUTWRWBG_Msk (0x800UL)                /*!< DOUTWRWBG (Bitfield-Mask: 0x01)                       */
#define CRYPTO_HOSTRGFENDIAN_DINRDBG_Pos  (7UL)                     /*!< DINRDBG (Bit 7)                                       */
#define CRYPTO_HOSTRGFENDIAN_DINRDBG_Msk  (0x80UL)                  /*!< DINRDBG (Bitfield-Mask: 0x01)                         */
#define CRYPTO_HOSTRGFENDIAN_DOUTWRBG_Pos (3UL)                     /*!< DOUTWRBG (Bit 3)                                      */
#define CRYPTO_HOSTRGFENDIAN_DOUTWRBG_Msk (0x8UL)                   /*!< DOUTWRBG (Bitfield-Mask: 0x01)                        */
/* ===================================================  HOSTRGFSIGNATURE  ==================================================== */
#define CRYPTO_HOSTRGFSIGNATURE_HOSTSIGNATURE_Pos (0UL)             /*!< HOSTSIGNATURE (Bit 0)                                 */
#define CRYPTO_HOSTRGFSIGNATURE_HOSTSIGNATURE_Msk (0xffffffffUL)    /*!< HOSTSIGNATURE (Bitfield-Mask: 0xffffffff)             */
/* =======================================================  HOSTBOOT  ======================================================== */
#define CRYPTO_HOSTBOOT_AESEXISTSLOCAL_Pos (30UL)                   /*!< AESEXISTSLOCAL (Bit 30)                               */
#define CRYPTO_HOSTBOOT_AESEXISTSLOCAL_Msk (0x40000000UL)           /*!< AESEXISTSLOCAL (Bitfield-Mask: 0x01)                  */
#define CRYPTO_HOSTBOOT_ONLYENCRYPTLOCAL_Pos (29UL)                 /*!< ONLYENCRYPTLOCAL (Bit 29)                             */
#define CRYPTO_HOSTBOOT_ONLYENCRYPTLOCAL_Msk (0x20000000UL)         /*!< ONLYENCRYPTLOCAL (Bitfield-Mask: 0x01)                */
#define CRYPTO_HOSTBOOT_SUPPORT256192KEYLOCAL_Pos (28UL)            /*!< SUPPORT256192KEYLOCAL (Bit 28)                        */
#define CRYPTO_HOSTBOOT_SUPPORT256192KEYLOCAL_Msk (0x10000000UL)    /*!< SUPPORT256192KEYLOCAL (Bitfield-Mask: 0x01)           */
#define CRYPTO_HOSTBOOT_TUNNELINGENBLOCAL_Pos (27UL)                /*!< TUNNELINGENBLOCAL (Bit 27)                            */
#define CRYPTO_HOSTBOOT_TUNNELINGENBLOCAL_Msk (0x8000000UL)         /*!< TUNNELINGENBLOCAL (Bitfield-Mask: 0x01)               */
#define CRYPTO_HOSTBOOT_AESDINBYTERESOLUTIONLOCAL_Pos (26UL)        /*!< AESDINBYTERESOLUTIONLOCAL (Bit 26)                    */
#define CRYPTO_HOSTBOOT_AESDINBYTERESOLUTIONLOCAL_Msk (0x4000000UL) /*!< AESDINBYTERESOLUTIONLOCAL (Bitfield-Mask: 0x01)       */
#define CRYPTO_HOSTBOOT_CTREXISTSLOCAL_Pos (25UL)                   /*!< CTREXISTSLOCAL (Bit 25)                               */
#define CRYPTO_HOSTBOOT_CTREXISTSLOCAL_Msk (0x2000000UL)            /*!< CTREXISTSLOCAL (Bitfield-Mask: 0x01)                  */
#define CRYPTO_HOSTBOOT_AESXEXEXISTSLOCAL_Pos (24UL)                /*!< AESXEXEXISTSLOCAL (Bit 24)                            */
#define CRYPTO_HOSTBOOT_AESXEXEXISTSLOCAL_Msk (0x1000000UL)         /*!< AESXEXEXISTSLOCAL (Bitfield-Mask: 0x01)               */
#define CRYPTO_HOSTBOOT_AESXEXHWTCALCLOCAL_Pos (23UL)               /*!< AESXEXHWTCALCLOCAL (Bit 23)                           */
#define CRYPTO_HOSTBOOT_AESXEXHWTCALCLOCAL_Msk (0x800000UL)         /*!< AESXEXHWTCALCLOCAL (Bitfield-Mask: 0x01)              */
#define CRYPTO_HOSTBOOT_AESCCMEXISTSLOCAL_Pos (22UL)                /*!< AESCCMEXISTSLOCAL (Bit 22)                            */
#define CRYPTO_HOSTBOOT_AESCCMEXISTSLOCAL_Msk (0x400000UL)          /*!< AESCCMEXISTSLOCAL (Bitfield-Mask: 0x01)               */
#define CRYPTO_HOSTBOOT_AESCMACEXISTSLOCAL_Pos (21UL)               /*!< AESCMACEXISTSLOCAL (Bit 21)                           */
#define CRYPTO_HOSTBOOT_AESCMACEXISTSLOCAL_Msk (0x200000UL)         /*!< AESCMACEXISTSLOCAL (Bitfield-Mask: 0x01)              */
#define CRYPTO_HOSTBOOT_AESXCBCMACEXISTSLOCAL_Pos (20UL)            /*!< AESXCBCMACEXISTSLOCAL (Bit 20)                        */
#define CRYPTO_HOSTBOOT_AESXCBCMACEXISTSLOCAL_Msk (0x100000UL)      /*!< AESXCBCMACEXISTSLOCAL (Bitfield-Mask: 0x01)           */
#define CRYPTO_HOSTBOOT_DESEXISTSLOCAL_Pos (19UL)                   /*!< DESEXISTSLOCAL (Bit 19)                               */
#define CRYPTO_HOSTBOOT_DESEXISTSLOCAL_Msk (0x80000UL)              /*!< DESEXISTSLOCAL (Bitfield-Mask: 0x01)                  */
#define CRYPTO_HOSTBOOT_C2EXISTSLOCAL_Pos (18UL)                    /*!< C2EXISTSLOCAL (Bit 18)                                */
#define CRYPTO_HOSTBOOT_C2EXISTSLOCAL_Msk (0x40000UL)               /*!< C2EXISTSLOCAL (Bitfield-Mask: 0x01)                   */
#define CRYPTO_HOSTBOOT_HASHEXISTSLOCAL_Pos (17UL)                  /*!< HASHEXISTSLOCAL (Bit 17)                              */
#define CRYPTO_HOSTBOOT_HASHEXISTSLOCAL_Msk (0x20000UL)             /*!< HASHEXISTSLOCAL (Bitfield-Mask: 0x01)                 */
#define CRYPTO_HOSTBOOT_MD5PRSNTLOCAL_Pos (16UL)                    /*!< MD5PRSNTLOCAL (Bit 16)                                */
#define CRYPTO_HOSTBOOT_MD5PRSNTLOCAL_Msk (0x10000UL)               /*!< MD5PRSNTLOCAL (Bitfield-Mask: 0x01)                   */
#define CRYPTO_HOSTBOOT_SHA256PRSNTLOCAL_Pos (15UL)                 /*!< SHA256PRSNTLOCAL (Bit 15)                             */
#define CRYPTO_HOSTBOOT_SHA256PRSNTLOCAL_Msk (0x8000UL)             /*!< SHA256PRSNTLOCAL (Bitfield-Mask: 0x01)                */
#define CRYPTO_HOSTBOOT_SHA512PRSNTLOCAL_Pos (14UL)                 /*!< SHA512PRSNTLOCAL (Bit 14)                             */
#define CRYPTO_HOSTBOOT_SHA512PRSNTLOCAL_Msk (0x4000UL)             /*!< SHA512PRSNTLOCAL (Bitfield-Mask: 0x01)                */
#define CRYPTO_HOSTBOOT_RC4EXISTSLOCAL_Pos (13UL)                   /*!< RC4EXISTSLOCAL (Bit 13)                               */
#define CRYPTO_HOSTBOOT_RC4EXISTSLOCAL_Msk (0x2000UL)               /*!< RC4EXISTSLOCAL (Bitfield-Mask: 0x01)                  */
#define CRYPTO_HOSTBOOT_PKAEXISTSLOCAL_Pos (12UL)                   /*!< PKAEXISTSLOCAL (Bit 12)                               */
#define CRYPTO_HOSTBOOT_PKAEXISTSLOCAL_Msk (0x1000UL)               /*!< PKAEXISTSLOCAL (Bitfield-Mask: 0x01)                  */
#define CRYPTO_HOSTBOOT_RNGEXISTSLOCAL_Pos (11UL)                   /*!< RNGEXISTSLOCAL (Bit 11)                               */
#define CRYPTO_HOSTBOOT_RNGEXISTSLOCAL_Msk (0x800UL)                /*!< RNGEXISTSLOCAL (Bitfield-Mask: 0x01)                  */
#define CRYPTO_HOSTBOOT_PAUEXISTSLOCAL_Pos (10UL)                   /*!< PAUEXISTSLOCAL (Bit 10)                               */
#define CRYPTO_HOSTBOOT_PAUEXISTSLOCAL_Msk (0x400UL)                /*!< PAUEXISTSLOCAL (Bitfield-Mask: 0x01)                  */
#define CRYPTO_HOSTBOOT_DSCRPTREXISTSLOCAL_Pos (9UL)                /*!< DSCRPTREXISTSLOCAL (Bit 9)                            */
#define CRYPTO_HOSTBOOT_DSCRPTREXISTSLOCAL_Msk (0x200UL)            /*!< DSCRPTREXISTSLOCAL (Bitfield-Mask: 0x01)              */
#define CRYPTO_HOSTBOOT_SRAMSIZELOCAL_Pos (6UL)                     /*!< SRAMSIZELOCAL (Bit 6)                                 */
#define CRYPTO_HOSTBOOT_SRAMSIZELOCAL_Msk (0x1c0UL)                 /*!< SRAMSIZELOCAL (Bitfield-Mask: 0x07)                   */
#define CRYPTO_HOSTBOOT_RKEKECCEXISTSLOCALN_Pos (5UL)               /*!< RKEKECCEXISTSLOCALN (Bit 5)                           */
#define CRYPTO_HOSTBOOT_RKEKECCEXISTSLOCALN_Msk (0x20UL)            /*!< RKEKECCEXISTSLOCALN (Bitfield-Mask: 0x01)             */
#define CRYPTO_HOSTBOOT_EXTMEMSECUREDLOCAL_Pos (3UL)                /*!< EXTMEMSECUREDLOCAL (Bit 3)                            */
#define CRYPTO_HOSTBOOT_EXTMEMSECUREDLOCAL_Msk (0x8UL)              /*!< EXTMEMSECUREDLOCAL (Bitfield-Mask: 0x01)              */
#define CRYPTO_HOSTBOOT_HASHINFUSESLOCAL_Pos (2UL)                  /*!< HASHINFUSESLOCAL (Bit 2)                              */
#define CRYPTO_HOSTBOOT_HASHINFUSESLOCAL_Msk (0x4UL)                /*!< HASHINFUSESLOCAL (Bitfield-Mask: 0x01)                */
#define CRYPTO_HOSTBOOT_LARGERKEKLOCAL_Pos (1UL)                    /*!< LARGERKEKLOCAL (Bit 1)                                */
#define CRYPTO_HOSTBOOT_LARGERKEKLOCAL_Msk (0x2UL)                  /*!< LARGERKEKLOCAL (Bitfield-Mask: 0x01)                  */
#define CRYPTO_HOSTBOOT_SYNTHESISCONFIG_Pos (0UL)                   /*!< SYNTHESISCONFIG (Bit 0)                               */
#define CRYPTO_HOSTBOOT_SYNTHESISCONFIG_Msk (0x1UL)                 /*!< SYNTHESISCONFIG (Bitfield-Mask: 0x01)                 */
/* ===================================================  HOSTCRYPTOKEYSEL  ==================================================== */
#define CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_Pos (0UL)              /*!< SELCRYPTOKEY (Bit 0)                                  */
#define CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_Msk (0x7UL)            /*!< SELCRYPTOKEY (Bitfield-Mask: 0x07)                    */
/* ================================================  HOSTCORECLKGATINGENABLE  ================================================ */
#define CRYPTO_HOSTCORECLKGATINGENABLE_HOSTCORECLKGATINGENABLE_Pos (0UL) /*!< HOSTCORECLKGATINGENABLE (Bit 0)                  */
#define CRYPTO_HOSTCORECLKGATINGENABLE_HOSTCORECLKGATINGENABLE_Msk (0x1UL) /*!< HOSTCORECLKGATINGENABLE (Bitfield-Mask: 0x01)  */
/* =====================================================  HOSTCCISIDLE  ====================================================== */
#define CRYPTO_HOSTCCISIDLE_CRYPTOISIDLE_Pos (9UL)                  /*!< CRYPTOISIDLE (Bit 9)                                  */
#define CRYPTO_HOSTCCISIDLE_CRYPTOISIDLE_Msk (0x200UL)              /*!< CRYPTOISIDLE (Bitfield-Mask: 0x01)                    */
#define CRYPTO_HOSTCCISIDLE_PKAISIDLE_Pos (8UL)                     /*!< PKAISIDLE (Bit 8)                                     */
#define CRYPTO_HOSTCCISIDLE_PKAISIDLE_Msk (0x100UL)                 /*!< PKAISIDLE (Bitfield-Mask: 0x01)                       */
#define CRYPTO_HOSTCCISIDLE_RNGISIDLE_Pos (7UL)                     /*!< RNGISIDLE (Bit 7)                                     */
#define CRYPTO_HOSTCCISIDLE_RNGISIDLE_Msk (0x80UL)                  /*!< RNGISIDLE (Bitfield-Mask: 0x01)                       */
#define CRYPTO_HOSTCCISIDLE_FATALWR_Pos   (6UL)                     /*!< FATALWR (Bit 6)                                       */
#define CRYPTO_HOSTCCISIDLE_FATALWR_Msk   (0x40UL)                  /*!< FATALWR (Bitfield-Mask: 0x01)                         */
#define CRYPTO_HOSTCCISIDLE_NVMISIDLE_Pos (5UL)                     /*!< NVMISIDLE (Bit 5)                                     */
#define CRYPTO_HOSTCCISIDLE_NVMISIDLE_Msk (0x20UL)                  /*!< NVMISIDLE (Bitfield-Mask: 0x01)                       */
#define CRYPTO_HOSTCCISIDLE_NVMARBISIDLE_Pos (4UL)                  /*!< NVMARBISIDLE (Bit 4)                                  */
#define CRYPTO_HOSTCCISIDLE_NVMARBISIDLE_Msk (0x10UL)               /*!< NVMARBISIDLE (Bitfield-Mask: 0x01)                    */
#define CRYPTO_HOSTCCISIDLE_AHBISIDLE_Pos (3UL)                     /*!< AHBISIDLE (Bit 3)                                     */
#define CRYPTO_HOSTCCISIDLE_AHBISIDLE_Msk (0x8UL)                   /*!< AHBISIDLE (Bitfield-Mask: 0x01)                       */
#define CRYPTO_HOSTCCISIDLE_SYMISBUSY_Pos (2UL)                     /*!< SYMISBUSY (Bit 2)                                     */
#define CRYPTO_HOSTCCISIDLE_SYMISBUSY_Msk (0x4UL)                   /*!< SYMISBUSY (Bitfield-Mask: 0x01)                       */
#define CRYPTO_HOSTCCISIDLE_HOSTCCISIDLEEVENT_Pos (1UL)             /*!< HOSTCCISIDLEEVENT (Bit 1)                             */
#define CRYPTO_HOSTCCISIDLE_HOSTCCISIDLEEVENT_Msk (0x2UL)           /*!< HOSTCCISIDLEEVENT (Bitfield-Mask: 0x01)               */
#define CRYPTO_HOSTCCISIDLE_HOSTCCISIDLE_Pos (0UL)                  /*!< HOSTCCISIDLE (Bit 0)                                  */
#define CRYPTO_HOSTCCISIDLE_HOSTCCISIDLE_Msk (0x1UL)                /*!< HOSTCCISIDLE (Bitfield-Mask: 0x01)                    */
/* =====================================================  HOSTPOWERDOWN  ===================================================== */
#define CRYPTO_HOSTPOWERDOWN_HOSTPOWERDOWN_Pos (0UL)                /*!< HOSTPOWERDOWN (Bit 0)                                 */
#define CRYPTO_HOSTPOWERDOWN_HOSTPOWERDOWN_Msk (0x1UL)              /*!< HOSTPOWERDOWN (Bitfield-Mask: 0x01)                   */
/* =================================================  HOSTREMOVEGHASHENGINE  ================================================= */
#define CRYPTO_HOSTREMOVEGHASHENGINE_HOSTREMOVEGHASHENGINE_Pos (0UL) /*!< HOSTREMOVEGHASHENGINE (Bit 0)                        */
#define CRYPTO_HOSTREMOVEGHASHENGINE_HOSTREMOVEGHASHENGINE_Msk (0x1UL) /*!< HOSTREMOVEGHASHENGINE (Bitfield-Mask: 0x01)        */
/* ================================================  HOSTREMOVECHACHAENGINE  ================================================= */
#define CRYPTO_HOSTREMOVECHACHAENGINE_HOSTREMOVECHACHAENGINE_Pos (0UL) /*!< HOSTREMOVECHACHAENGINE (Bit 0)                     */
#define CRYPTO_HOSTREMOVECHACHAENGINE_HOSTREMOVECHACHAENGINE_Msk (0x1UL) /*!< HOSTREMOVECHACHAENGINE (Bitfield-Mask: 0x01)     */
/* ======================================================  AHBMSINGLES  ====================================================== */
#define CRYPTO_AHBMSINGLES_AHBSINGLES_Pos (0UL)                     /*!< AHBSINGLES (Bit 0)                                    */
#define CRYPTO_AHBMSINGLES_AHBSINGLES_Msk (0x1UL)                   /*!< AHBSINGLES (Bitfield-Mask: 0x01)                      */
/* =======================================================  AHBMHPROT  ======================================================= */
#define CRYPTO_AHBMHPROT_AHBPROT_Pos      (0UL)                     /*!< AHBPROT (Bit 0)                                       */
#define CRYPTO_AHBMHPROT_AHBPROT_Msk      (0xfUL)                   /*!< AHBPROT (Bitfield-Mask: 0x0f)                         */
/* =====================================================  AHBMHMASTLOCK  ===================================================== */
#define CRYPTO_AHBMHMASTLOCK_AHBHMASTLOCK_Pos (0UL)                 /*!< AHBHMASTLOCK (Bit 0)                                  */
#define CRYPTO_AHBMHMASTLOCK_AHBHMASTLOCK_Msk (0x1UL)               /*!< AHBHMASTLOCK (Bitfield-Mask: 0x01)                    */
/* ======================================================  AHBMHNONSEC  ====================================================== */
#define CRYPTO_AHBMHNONSEC_AHBREADHNONSEC_Pos (1UL)                 /*!< AHBREADHNONSEC (Bit 1)                                */
#define CRYPTO_AHBMHNONSEC_AHBREADHNONSEC_Msk (0x2UL)               /*!< AHBREADHNONSEC (Bitfield-Mask: 0x01)                  */
#define CRYPTO_AHBMHNONSEC_AHBWRITEHNONSEC_Pos (0UL)                /*!< AHBWRITEHNONSEC (Bit 0)                               */
#define CRYPTO_AHBMHNONSEC_AHBWRITEHNONSEC_Msk (0x1UL)              /*!< AHBWRITEHNONSEC (Bitfield-Mask: 0x01)                 */
/* =======================================================  DINBUFFER  ======================================================= */
#define CRYPTO_DINBUFFER_DINBUFFERDATA_Pos (0UL)                    /*!< DINBUFFERDATA (Bit 0)                                 */
#define CRYPTO_DINBUFFER_DINBUFFERDATA_Msk (0xffffffffUL)           /*!< DINBUFFERDATA (Bitfield-Mask: 0xffffffff)             */
/* =====================================================  DINMEMDMABUSY  ===================================================== */
#define CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY_Pos (0UL)                /*!< DINMEMDMABUSY (Bit 0)                                 */
#define CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY_Msk (0x1UL)              /*!< DINMEMDMABUSY (Bitfield-Mask: 0x01)                   */
/* ======================================================  SRCLLIWORD0  ====================================================== */
#define CRYPTO_SRCLLIWORD0_SRCLLIWORD0_Pos (0UL)                    /*!< SRCLLIWORD0 (Bit 0)                                   */
#define CRYPTO_SRCLLIWORD0_SRCLLIWORD0_Msk (0xffffffffUL)           /*!< SRCLLIWORD0 (Bitfield-Mask: 0xffffffff)               */
/* ======================================================  SRCLLIWORD1  ====================================================== */
#define CRYPTO_SRCLLIWORD1_LAST_Pos       (31UL)                    /*!< LAST (Bit 31)                                         */
#define CRYPTO_SRCLLIWORD1_LAST_Msk       (0x80000000UL)            /*!< LAST (Bitfield-Mask: 0x01)                            */
#define CRYPTO_SRCLLIWORD1_FIRST_Pos      (30UL)                    /*!< FIRST (Bit 30)                                        */
#define CRYPTO_SRCLLIWORD1_FIRST_Msk      (0x40000000UL)            /*!< FIRST (Bitfield-Mask: 0x01)                           */
#define CRYPTO_SRCLLIWORD1_BYTESNUM_Pos   (0UL)                     /*!< BYTESNUM (Bit 0)                                      */
#define CRYPTO_SRCLLIWORD1_BYTESNUM_Msk   (0x3fffffffUL)            /*!< BYTESNUM (Bitfield-Mask: 0x3fffffff)                  */
/* ======================================================  SRAMSRCADDR  ====================================================== */
#define CRYPTO_SRAMSRCADDR_SRAMSOURCE_Pos (0UL)                     /*!< SRAMSOURCE (Bit 0)                                    */
#define CRYPTO_SRAMSRCADDR_SRAMSOURCE_Msk (0xffffffffUL)            /*!< SRAMSOURCE (Bitfield-Mask: 0xffffffff)                */
/* ====================================================  DINSRAMBYTESLEN  ==================================================== */
#define CRYPTO_DINSRAMBYTESLEN_BYTESLEN_Pos (0UL)                   /*!< BYTESLEN (Bit 0)                                      */
#define CRYPTO_DINSRAMBYTESLEN_BYTESLEN_Msk (0xffffffffUL)          /*!< BYTESLEN (Bitfield-Mask: 0xffffffff)                  */
/* ====================================================  DINSRAMDMABUSY  ===================================================== */
#define CRYPTO_DINSRAMDMABUSY_BUSY_Pos    (0UL)                     /*!< BUSY (Bit 0)                                          */
#define CRYPTO_DINSRAMDMABUSY_BUSY_Msk    (0x1UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
/* ===================================================  DINSRAMENDIANNESS  =================================================== */
#define CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS_Pos (0UL)        /*!< SRAMDINENDIANNESS (Bit 0)                             */
#define CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS_Msk (0x1UL)      /*!< SRAMDINENDIANNESS (Bitfield-Mask: 0x01)               */
/* ====================================================  DINCPUDATASIZE  ===================================================== */
#define CRYPTO_DINCPUDATASIZE_CPUDINSIZE_Pos (0UL)                  /*!< CPUDINSIZE (Bit 0)                                    */
#define CRYPTO_DINCPUDATASIZE_CPUDINSIZE_Msk (0xffffUL)             /*!< CPUDINSIZE (Bitfield-Mask: 0xffff)                    */
/* ======================================================  FIFOINEMPTY  ====================================================== */
#define CRYPTO_FIFOINEMPTY_EMPTY_Pos      (0UL)                     /*!< EMPTY (Bit 0)                                         */
#define CRYPTO_FIFOINEMPTY_EMPTY_Msk      (0x1UL)                   /*!< EMPTY (Bitfield-Mask: 0x01)                           */
/* ====================================================  DINFIFORSTPNTR  ===================================================== */
#define CRYPTO_DINFIFORSTPNTR_RST_Pos     (0UL)                     /*!< RST (Bit 0)                                           */
#define CRYPTO_DINFIFORSTPNTR_RST_Msk     (0x1UL)                   /*!< RST (Bitfield-Mask: 0x01)                             */
/* ======================================================  DOUTBUFFER  ======================================================= */
#define CRYPTO_DOUTBUFFER_DATA_Pos        (0UL)                     /*!< DATA (Bit 0)                                          */
#define CRYPTO_DOUTBUFFER_DATA_Msk        (0xffffffffUL)            /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
/* ====================================================  DOUTMEMDMABUSY  ===================================================== */
#define CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY_Pos (0UL)              /*!< DOUTMEMDMABUSY (Bit 0)                                */
#define CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY_Msk (0x1UL)            /*!< DOUTMEMDMABUSY (Bitfield-Mask: 0x01)                  */
/* ======================================================  DSTLLIWORD0  ====================================================== */
#define CRYPTO_DSTLLIWORD0_DSTLLIWORD0_Pos (0UL)                    /*!< DSTLLIWORD0 (Bit 0)                                   */
#define CRYPTO_DSTLLIWORD0_DSTLLIWORD0_Msk (0xffffffffUL)           /*!< DSTLLIWORD0 (Bitfield-Mask: 0xffffffff)               */
/* ======================================================  DSTLLIWORD1  ====================================================== */
#define CRYPTO_DSTLLIWORD1_LAST_Pos       (31UL)                    /*!< LAST (Bit 31)                                         */
#define CRYPTO_DSTLLIWORD1_LAST_Msk       (0x80000000UL)            /*!< LAST (Bitfield-Mask: 0x01)                            */
#define CRYPTO_DSTLLIWORD1_FIRST_Pos      (30UL)                    /*!< FIRST (Bit 30)                                        */
#define CRYPTO_DSTLLIWORD1_FIRST_Msk      (0x40000000UL)            /*!< FIRST (Bitfield-Mask: 0x01)                           */
#define CRYPTO_DSTLLIWORD1_BYTESNUM_Pos   (0UL)                     /*!< BYTESNUM (Bit 0)                                      */
#define CRYPTO_DSTLLIWORD1_BYTESNUM_Msk   (0x3fffffffUL)            /*!< BYTESNUM (Bitfield-Mask: 0x3fffffff)                  */
/* =====================================================  SRAMDESTADDR  ====================================================== */
#define CRYPTO_SRAMDESTADDR_SRAMDEST_Pos  (0UL)                     /*!< SRAMDEST (Bit 0)                                      */
#define CRYPTO_SRAMDESTADDR_SRAMDEST_Msk  (0xffffffffUL)            /*!< SRAMDEST (Bitfield-Mask: 0xffffffff)                  */
/* ===================================================  DOUTSRAMBYTESLEN  ==================================================== */
#define CRYPTO_DOUTSRAMBYTESLEN_BYTESLEN_Pos (0UL)                  /*!< BYTESLEN (Bit 0)                                      */
#define CRYPTO_DOUTSRAMBYTESLEN_BYTESLEN_Msk (0xffffffffUL)         /*!< BYTESLEN (Bitfield-Mask: 0xffffffff)                  */
/* ====================================================  DOUTSRAMDMABUSY  ==================================================== */
#define CRYPTO_DOUTSRAMDMABUSY_BUSY_Pos   (0UL)                     /*!< BUSY (Bit 0)                                          */
#define CRYPTO_DOUTSRAMDMABUSY_BUSY_Msk   (0x1UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
/* ==================================================  DOUTSRAMENDIANNESS  =================================================== */
#define CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS_Pos (0UL)      /*!< DOUTSRAMENDIANNESS (Bit 0)                            */
#define CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS_Msk (0x1UL)    /*!< DOUTSRAMENDIANNESS (Bitfield-Mask: 0x01)              */
/* =====================================================  READALIGNLAST  ===================================================== */
#define CRYPTO_READALIGNLAST_LAST_Pos     (0UL)                     /*!< LAST (Bit 0)                                          */
#define CRYPTO_READALIGNLAST_LAST_Msk     (0x1UL)                   /*!< LAST (Bitfield-Mask: 0x01)                            */
/* =====================================================  DOUTFIFOEMPTY  ===================================================== */
#define CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY_Pos (0UL)                /*!< DOUTFIFOEMPTY (Bit 0)                                 */
#define CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY_Msk (0x1UL)              /*!< DOUTFIFOEMPTY (Bitfield-Mask: 0x01)                   */
/* =======================================================  SRAMDATA  ======================================================== */
#define CRYPTO_SRAMDATA_SRAMDATA_Pos      (0UL)                     /*!< SRAMDATA (Bit 0)                                      */
#define CRYPTO_SRAMDATA_SRAMDATA_Msk      (0xffffffffUL)            /*!< SRAMDATA (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  SRAMADDR  ======================================================== */
#define CRYPTO_SRAMADDR_SRAMADDR_Pos      (0UL)                     /*!< SRAMADDR (Bit 0)                                      */
#define CRYPTO_SRAMADDR_SRAMADDR_Msk      (0x7fffUL)                /*!< SRAMADDR (Bitfield-Mask: 0x7fff)                      */
/* =====================================================  SRAMDATAREADY  ===================================================== */
#define CRYPTO_SRAMDATAREADY_SRAMREADY_Pos (0UL)                    /*!< SRAMREADY (Bit 0)                                     */
#define CRYPTO_SRAMDATAREADY_SRAMREADY_Msk (0x1UL)                  /*!< SRAMREADY (Bitfield-Mask: 0x01)                       */
/* =====================================================  PERIPHERALID4  ===================================================== */
#define CRYPTO_PERIPHERALID4_DES2JEP106_Pos (0UL)                   /*!< DES2JEP106 (Bit 0)                                    */
#define CRYPTO_PERIPHERALID4_DES2JEP106_Msk (0xfUL)                 /*!< DES2JEP106 (Bitfield-Mask: 0x0f)                      */
/* =====================================================  PERIPHERALID0  ===================================================== */
#define CRYPTO_PERIPHERALID0_PART0_Pos    (0UL)                     /*!< PART0 (Bit 0)                                         */
#define CRYPTO_PERIPHERALID0_PART0_Msk    (0xffUL)                  /*!< PART0 (Bitfield-Mask: 0xff)                           */
/* =====================================================  PERIPHERALID1  ===================================================== */
#define CRYPTO_PERIPHERALID1_DES0JEP106_Pos (4UL)                   /*!< DES0JEP106 (Bit 4)                                    */
#define CRYPTO_PERIPHERALID1_DES0JEP106_Msk (0xf0UL)                /*!< DES0JEP106 (Bitfield-Mask: 0x0f)                      */
#define CRYPTO_PERIPHERALID1_PART1_Pos    (0UL)                     /*!< PART1 (Bit 0)                                         */
#define CRYPTO_PERIPHERALID1_PART1_Msk    (0xfUL)                   /*!< PART1 (Bitfield-Mask: 0x0f)                           */
/* =====================================================  PERIPHERALID2  ===================================================== */
#define CRYPTO_PERIPHERALID2_REVISION_Pos (4UL)                     /*!< REVISION (Bit 4)                                      */
#define CRYPTO_PERIPHERALID2_REVISION_Msk (0xf0UL)                  /*!< REVISION (Bitfield-Mask: 0x0f)                        */
#define CRYPTO_PERIPHERALID2_JEDEC_Pos    (3UL)                     /*!< JEDEC (Bit 3)                                         */
#define CRYPTO_PERIPHERALID2_JEDEC_Msk    (0x8UL)                   /*!< JEDEC (Bitfield-Mask: 0x01)                           */
#define CRYPTO_PERIPHERALID2_DES1JEP106_Pos (0UL)                   /*!< DES1JEP106 (Bit 0)                                    */
#define CRYPTO_PERIPHERALID2_DES1JEP106_Msk (0x7UL)                 /*!< DES1JEP106 (Bitfield-Mask: 0x07)                      */
/* =====================================================  PERIPHERALID3  ===================================================== */
#define CRYPTO_PERIPHERALID3_REVAND_Pos   (4UL)                     /*!< REVAND (Bit 4)                                        */
#define CRYPTO_PERIPHERALID3_REVAND_Msk   (0xf0UL)                  /*!< REVAND (Bitfield-Mask: 0x0f)                          */
#define CRYPTO_PERIPHERALID3_CMOD_Pos     (0UL)                     /*!< CMOD (Bit 0)                                          */
#define CRYPTO_PERIPHERALID3_CMOD_Msk     (0xfUL)                   /*!< CMOD (Bitfield-Mask: 0x0f)                            */
/* =====================================================  COMPONENTID0  ====================================================== */
#define CRYPTO_COMPONENTID0_PRMBL0_Pos    (0UL)                     /*!< PRMBL0 (Bit 0)                                        */
#define CRYPTO_COMPONENTID0_PRMBL0_Msk    (0xffUL)                  /*!< PRMBL0 (Bitfield-Mask: 0xff)                          */
/* =====================================================  COMPONENTID1  ====================================================== */
#define CRYPTO_COMPONENTID1_CLASS_Pos     (4UL)                     /*!< CLASS (Bit 4)                                         */
#define CRYPTO_COMPONENTID1_CLASS_Msk     (0xf0UL)                  /*!< CLASS (Bitfield-Mask: 0x0f)                           */
#define CRYPTO_COMPONENTID1_PRMBL1_Pos    (0UL)                     /*!< PRMBL1 (Bit 0)                                        */
#define CRYPTO_COMPONENTID1_PRMBL1_Msk    (0xfUL)                   /*!< PRMBL1 (Bitfield-Mask: 0x0f)                          */
/* =====================================================  COMPONENTID2  ====================================================== */
#define CRYPTO_COMPONENTID2_PRMBL2_Pos    (0UL)                     /*!< PRMBL2 (Bit 0)                                        */
#define CRYPTO_COMPONENTID2_PRMBL2_Msk    (0xffUL)                  /*!< PRMBL2 (Bitfield-Mask: 0xff)                          */
/* =====================================================  COMPONENTID3  ====================================================== */
#define CRYPTO_COMPONENTID3_PRMBL3_Pos    (0UL)                     /*!< PRMBL3 (Bit 0)                                        */
#define CRYPTO_COMPONENTID3_PRMBL3_Msk    (0xffUL)                  /*!< PRMBL3 (Bitfield-Mask: 0xff)                          */
/* ======================================================  HOSTDCUEN0  ======================================================= */
#define CRYPTO_HOSTDCUEN0_HOSTDCUEN0_Pos  (0UL)                     /*!< HOSTDCUEN0 (Bit 0)                                    */
#define CRYPTO_HOSTDCUEN0_HOSTDCUEN0_Msk  (0xffffffffUL)            /*!< HOSTDCUEN0 (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  HOSTDCUEN1  ======================================================= */
#define CRYPTO_HOSTDCUEN1_HOSTDCUEN1_Pos  (0UL)                     /*!< HOSTDCUEN1 (Bit 0)                                    */
#define CRYPTO_HOSTDCUEN1_HOSTDCUEN1_Msk  (0xffffffffUL)            /*!< HOSTDCUEN1 (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  HOSTDCUEN2  ======================================================= */
#define CRYPTO_HOSTDCUEN2_HOSTDCUEN2_Pos  (0UL)                     /*!< HOSTDCUEN2 (Bit 0)                                    */
#define CRYPTO_HOSTDCUEN2_HOSTDCUEN2_Msk  (0xffffffffUL)            /*!< HOSTDCUEN2 (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  HOSTDCUEN3  ======================================================= */
#define CRYPTO_HOSTDCUEN3_HOSTDCUEN3_Pos  (0UL)                     /*!< HOSTDCUEN3 (Bit 0)                                    */
#define CRYPTO_HOSTDCUEN3_HOSTDCUEN3_Msk  (0xffffffffUL)            /*!< HOSTDCUEN3 (Bitfield-Mask: 0xffffffff)                */
/* =====================================================  HOSTDCULOCK0  ====================================================== */
#define CRYPTO_HOSTDCULOCK0_HOSTDCULOCK0_Pos (0UL)                  /*!< HOSTDCULOCK0 (Bit 0)                                  */
#define CRYPTO_HOSTDCULOCK0_HOSTDCULOCK0_Msk (0xffffffffUL)         /*!< HOSTDCULOCK0 (Bitfield-Mask: 0xffffffff)              */
/* =====================================================  HOSTDCULOCK1  ====================================================== */
#define CRYPTO_HOSTDCULOCK1_HOSTDCULOCK1_Pos (0UL)                  /*!< HOSTDCULOCK1 (Bit 0)                                  */
#define CRYPTO_HOSTDCULOCK1_HOSTDCULOCK1_Msk (0xffffffffUL)         /*!< HOSTDCULOCK1 (Bitfield-Mask: 0xffffffff)              */
/* =====================================================  HOSTDCULOCK2  ====================================================== */
#define CRYPTO_HOSTDCULOCK2_HOSTDCULOCK2_Pos (0UL)                  /*!< HOSTDCULOCK2 (Bit 0)                                  */
#define CRYPTO_HOSTDCULOCK2_HOSTDCULOCK2_Msk (0xffffffffUL)         /*!< HOSTDCULOCK2 (Bitfield-Mask: 0xffffffff)              */
/* =====================================================  HOSTDCULOCK3  ====================================================== */
#define CRYPTO_HOSTDCULOCK3_HOSTDCULOCK3_Pos (0UL)                  /*!< HOSTDCULOCK3 (Bit 0)                                  */
#define CRYPTO_HOSTDCULOCK3_HOSTDCULOCK3_Msk (0xffffffffUL)         /*!< HOSTDCULOCK3 (Bitfield-Mask: 0xffffffff)              */
/* ===============================================  AOICVDCURESTRICTIONMASK0  ================================================ */
#define CRYPTO_AOICVDCURESTRICTIONMASK0_AOICVDCURESTRICTIONMASK0_Pos (0UL) /*!< AOICVDCURESTRICTIONMASK0 (Bit 0)               */
#define CRYPTO_AOICVDCURESTRICTIONMASK0_AOICVDCURESTRICTIONMASK0_Msk (0xffffffffUL) /*!< AOICVDCURESTRICTIONMASK0 (Bitfield-Mask: 0xffffffff) */
/* ===============================================  AOICVDCURESTRICTIONMASK1  ================================================ */
#define CRYPTO_AOICVDCURESTRICTIONMASK1_AOICVDCURESTRICTIONMASK1_Pos (0UL) /*!< AOICVDCURESTRICTIONMASK1 (Bit 0)               */
#define CRYPTO_AOICVDCURESTRICTIONMASK1_AOICVDCURESTRICTIONMASK1_Msk (0xffffffffUL) /*!< AOICVDCURESTRICTIONMASK1 (Bitfield-Mask: 0xffffffff) */
/* ===============================================  AOICVDCURESTRICTIONMASK2  ================================================ */
#define CRYPTO_AOICVDCURESTRICTIONMASK2_AOICVDCURESTRICTIONMASK2_Pos (0UL) /*!< AOICVDCURESTRICTIONMASK2 (Bit 0)               */
#define CRYPTO_AOICVDCURESTRICTIONMASK2_AOICVDCURESTRICTIONMASK2_Msk (0xffffffffUL) /*!< AOICVDCURESTRICTIONMASK2 (Bitfield-Mask: 0xffffffff) */
/* ===============================================  AOICVDCURESTRICTIONMASK3  ================================================ */
#define CRYPTO_AOICVDCURESTRICTIONMASK3_AOICVDCURESTRICTIONMASK3_Pos (0UL) /*!< AOICVDCURESTRICTIONMASK3 (Bit 0)               */
#define CRYPTO_AOICVDCURESTRICTIONMASK3_AOICVDCURESTRICTIONMASK3_Msk (0xffffffffUL) /*!< AOICVDCURESTRICTIONMASK3 (Bitfield-Mask: 0xffffffff) */
/* ===================================================  AOCCSECDEBUGRESET  =================================================== */
#define CRYPTO_AOCCSECDEBUGRESET_AOCCSECDEBUGRESET_Pos (0UL)        /*!< AOCCSECDEBUGRESET (Bit 0)                             */
#define CRYPTO_AOCCSECDEBUGRESET_AOCCSECDEBUGRESET_Msk (0x1UL)      /*!< AOCCSECDEBUGRESET (Bitfield-Mask: 0x01)               */
/* ====================================================  HOSTAOLOCKBITS  ===================================================== */
#define CRYPTO_HOSTAOLOCKBITS_HOSTDFAENABLELOCK_Pos (8UL)           /*!< HOSTDFAENABLELOCK (Bit 8)                             */
#define CRYPTO_HOSTAOLOCKBITS_HOSTDFAENABLELOCK_Msk (0x100UL)       /*!< HOSTDFAENABLELOCK (Bitfield-Mask: 0x01)               */
#define CRYPTO_HOSTAOLOCKBITS_HOSTFORCEDFAENABLE_Pos (7UL)          /*!< HOSTFORCEDFAENABLE (Bit 7)                            */
#define CRYPTO_HOSTAOLOCKBITS_HOSTFORCEDFAENABLE_Msk (0x80UL)       /*!< HOSTFORCEDFAENABLE (Bitfield-Mask: 0x01)              */
#define CRYPTO_HOSTAOLOCKBITS_RESETUPONDEBUGDISABLE_Pos (6UL)       /*!< RESETUPONDEBUGDISABLE (Bit 6)                         */
#define CRYPTO_HOSTAOLOCKBITS_RESETUPONDEBUGDISABLE_Msk (0x40UL)    /*!< RESETUPONDEBUGDISABLE (Bitfield-Mask: 0x01)           */
#define CRYPTO_HOSTAOLOCKBITS_HOSTICVRMALOCK_Pos (5UL)              /*!< HOSTICVRMALOCK (Bit 5)                                */
#define CRYPTO_HOSTAOLOCKBITS_HOSTICVRMALOCK_Msk (0x20UL)           /*!< HOSTICVRMALOCK (Bitfield-Mask: 0x01)                  */
#define CRYPTO_HOSTAOLOCKBITS_HOSTKCELOCK_Pos (4UL)                 /*!< HOSTKCELOCK (Bit 4)                                   */
#define CRYPTO_HOSTAOLOCKBITS_HOSTKCELOCK_Msk (0x10UL)              /*!< HOSTKCELOCK (Bitfield-Mask: 0x01)                     */
#define CRYPTO_HOSTAOLOCKBITS_HOSTKCPLOCK_Pos (3UL)                 /*!< HOSTKCPLOCK (Bit 3)                                   */
#define CRYPTO_HOSTAOLOCKBITS_HOSTKCPLOCK_Msk (0x8UL)               /*!< HOSTKCPLOCK (Bitfield-Mask: 0x01)                     */
#define CRYPTO_HOSTAOLOCKBITS_HOSTKCEICVLOCK_Pos (2UL)              /*!< HOSTKCEICVLOCK (Bit 2)                                */
#define CRYPTO_HOSTAOLOCKBITS_HOSTKCEICVLOCK_Msk (0x4UL)            /*!< HOSTKCEICVLOCK (Bitfield-Mask: 0x01)                  */
#define CRYPTO_HOSTAOLOCKBITS_HOSTKPICVLOCK_Pos (1UL)               /*!< HOSTKPICVLOCK (Bit 1)                                 */
#define CRYPTO_HOSTAOLOCKBITS_HOSTKPICVLOCK_Msk (0x2UL)             /*!< HOSTKPICVLOCK (Bitfield-Mask: 0x01)                   */
#define CRYPTO_HOSTAOLOCKBITS_HOSTFATALERR_Pos (0UL)                /*!< HOSTFATALERR (Bit 0)                                  */
#define CRYPTO_HOSTAOLOCKBITS_HOSTFATALERR_Msk (0x1UL)              /*!< HOSTFATALERR (Bitfield-Mask: 0x01)                    */
/* ====================================================  AOAPBFILTERING  ===================================================== */
#define CRYPTO_AOAPBFILTERING_APBCONLYINSTACCESSALLOWLOCK_Pos (9UL) /*!< APBCONLYINSTACCESSALLOWLOCK (Bit 9)                   */
#define CRYPTO_AOAPBFILTERING_APBCONLYINSTACCESSALLOWLOCK_Msk (0x200UL) /*!< APBCONLYINSTACCESSALLOWLOCK (Bitfield-Mask: 0x01) */
#define CRYPTO_AOAPBFILTERING_APBCONLYINSTACCESSALLOW_Pos (8UL)     /*!< APBCONLYINSTACCESSALLOW (Bit 8)                       */
#define CRYPTO_AOAPBFILTERING_APBCONLYINSTACCESSALLOW_Msk (0x100UL) /*!< APBCONLYINSTACCESSALLOW (Bitfield-Mask: 0x01)         */
#define CRYPTO_AOAPBFILTERING_APBCONLYPRIVACCESSALLOWLOCK_Pos (7UL) /*!< APBCONLYPRIVACCESSALLOWLOCK (Bit 7)                   */
#define CRYPTO_AOAPBFILTERING_APBCONLYPRIVACCESSALLOWLOCK_Msk (0x80UL) /*!< APBCONLYPRIVACCESSALLOWLOCK (Bitfield-Mask: 0x01)  */
#define CRYPTO_AOAPBFILTERING_APBCONLYPRIVACCESSALLOW_Pos (6UL)     /*!< APBCONLYPRIVACCESSALLOW (Bit 6)                       */
#define CRYPTO_AOAPBFILTERING_APBCONLYPRIVACCESSALLOW_Msk (0x40UL)  /*!< APBCONLYPRIVACCESSALLOW (Bitfield-Mask: 0x01)         */
#define CRYPTO_AOAPBFILTERING_APBCONLYSECACCESSALLOWLOCK_Pos (5UL)  /*!< APBCONLYSECACCESSALLOWLOCK (Bit 5)                    */
#define CRYPTO_AOAPBFILTERING_APBCONLYSECACCESSALLOWLOCK_Msk (0x20UL) /*!< APBCONLYSECACCESSALLOWLOCK (Bitfield-Mask: 0x01)    */
#define CRYPTO_AOAPBFILTERING_APBCONLYSECACCESSALLOW_Pos (4UL)      /*!< APBCONLYSECACCESSALLOW (Bit 4)                        */
#define CRYPTO_AOAPBFILTERING_APBCONLYSECACCESSALLOW_Msk (0x10UL)   /*!< APBCONLYSECACCESSALLOW (Bitfield-Mask: 0x01)          */
#define CRYPTO_AOAPBFILTERING_ONLYPRIVACCESSALLOWLOCK_Pos (3UL)     /*!< ONLYPRIVACCESSALLOWLOCK (Bit 3)                       */
#define CRYPTO_AOAPBFILTERING_ONLYPRIVACCESSALLOWLOCK_Msk (0x8UL)   /*!< ONLYPRIVACCESSALLOWLOCK (Bitfield-Mask: 0x01)         */
#define CRYPTO_AOAPBFILTERING_ONLYPRIVACCESSALLOW_Pos (2UL)         /*!< ONLYPRIVACCESSALLOW (Bit 2)                           */
#define CRYPTO_AOAPBFILTERING_ONLYPRIVACCESSALLOW_Msk (0x4UL)       /*!< ONLYPRIVACCESSALLOW (Bitfield-Mask: 0x01)             */
#define CRYPTO_AOAPBFILTERING_ONLYSECACCESSALLOWLOCK_Pos (1UL)      /*!< ONLYSECACCESSALLOWLOCK (Bit 1)                        */
#define CRYPTO_AOAPBFILTERING_ONLYSECACCESSALLOWLOCK_Msk (0x2UL)    /*!< ONLYSECACCESSALLOWLOCK (Bitfield-Mask: 0x01)          */
#define CRYPTO_AOAPBFILTERING_ONLYSECACCESSALLOW_Pos (0UL)          /*!< ONLYSECACCESSALLOW (Bit 0)                            */
#define CRYPTO_AOAPBFILTERING_ONLYSECACCESSALLOW_Msk (0x1UL)        /*!< ONLYSECACCESSALLOW (Bitfield-Mask: 0x01)              */
/* =======================================================  AOCCGPPC  ======================================================== */
#define CRYPTO_AOCCGPPC_AOCCGPPC_Pos      (0UL)                     /*!< AOCCGPPC (Bit 0)                                      */
#define CRYPTO_AOCCGPPC_AOCCGPPC_Msk      (0xffUL)                  /*!< AOCCGPPC (Bitfield-Mask: 0xff)                        */
/* ====================================================  HOSTRGFCCSWRST  ===================================================== */
#define CRYPTO_HOSTRGFCCSWRST_HOSTRGFCCSWRST_Pos (0UL)              /*!< HOSTRGFCCSWRST (Bit 0)                                */
#define CRYPTO_HOSTRGFCCSWRST_HOSTRGFCCSWRST_Msk (0x1UL)            /*!< HOSTRGFCCSWRST (Bitfield-Mask: 0x01)                  */
/* =================================================  AIBFUSEPROGCOMPLETED  ================================================== */
#define CRYPTO_AIBFUSEPROGCOMPLETED_AIBFUSEPROGCOMPLETED_Pos (0UL)  /*!< AIBFUSEPROGCOMPLETED (Bit 0)                          */
#define CRYPTO_AIBFUSEPROGCOMPLETED_AIBFUSEPROGCOMPLETED_Msk (0x1UL) /*!< AIBFUSEPROGCOMPLETED (Bitfield-Mask: 0x01)           */
/* ====================================================  NVMDEBUGSTATUS  ===================================================== */
#define CRYPTO_NVMDEBUGSTATUS_NVMSM_Pos   (1UL)                     /*!< NVMSM (Bit 1)                                         */
#define CRYPTO_NVMDEBUGSTATUS_NVMSM_Msk   (0xeUL)                   /*!< NVMSM (Bitfield-Mask: 0x07)                           */
/* ======================================================  LCSISVALID  ======================================================= */
#define CRYPTO_LCSISVALID_LCSISVALIDREG_Pos (0UL)                   /*!< LCSISVALIDREG (Bit 0)                                 */
#define CRYPTO_LCSISVALID_LCSISVALIDREG_Msk (0x1UL)                 /*!< LCSISVALIDREG (Bitfield-Mask: 0x01)                   */
/* =======================================================  NVMISIDLE  ======================================================= */
#define CRYPTO_NVMISIDLE_NVMISIDLEREG_Pos (0UL)                     /*!< NVMISIDLEREG (Bit 0)                                  */
#define CRYPTO_NVMISIDLE_NVMISIDLEREG_Msk (0x1UL)                   /*!< NVMISIDLEREG (Bitfield-Mask: 0x01)                    */
/* ========================================================  LCSREG  ========================================================= */
#define CRYPTO_LCSREG_ERRORKCEICVZEROCNT_Pos (12UL)                 /*!< ERRORKCEICVZEROCNT (Bit 12)                           */
#define CRYPTO_LCSREG_ERRORKCEICVZEROCNT_Msk (0x1000UL)             /*!< ERRORKCEICVZEROCNT (Bitfield-Mask: 0x01)              */
#define CRYPTO_LCSREG_ERRORKPICVZEROCNT_Pos (11UL)                  /*!< ERRORKPICVZEROCNT (Bit 11)                            */
#define CRYPTO_LCSREG_ERRORKPICVZEROCNT_Msk (0x800UL)               /*!< ERRORKPICVZEROCNT (Bitfield-Mask: 0x01)               */
#define CRYPTO_LCSREG_ERRORKCEZEROCNT_Pos (10UL)                    /*!< ERRORKCEZEROCNT (Bit 10)                              */
#define CRYPTO_LCSREG_ERRORKCEZEROCNT_Msk (0x400UL)                 /*!< ERRORKCEZEROCNT (Bitfield-Mask: 0x01)                 */
#define CRYPTO_LCSREG_ERRORPROVZEROCNT_Pos (9UL)                    /*!< ERRORPROVZEROCNT (Bit 9)                              */
#define CRYPTO_LCSREG_ERRORPROVZEROCNT_Msk (0x200UL)                /*!< ERRORPROVZEROCNT (Bitfield-Mask: 0x01)                */
#define CRYPTO_LCSREG_ERRORKDRZEROCNT_Pos (8UL)                     /*!< ERRORKDRZEROCNT (Bit 8)                               */
#define CRYPTO_LCSREG_ERRORKDRZEROCNT_Msk (0x100UL)                 /*!< ERRORKDRZEROCNT (Bitfield-Mask: 0x01)                 */
#define CRYPTO_LCSREG_LCSREG_Pos          (0UL)                     /*!< LCSREG (Bit 0)                                        */
#define CRYPTO_LCSREG_LCSREG_Msk          (0x7UL)                   /*!< LCSREG (Bitfield-Mask: 0x07)                          */
/* ===================================================  HOSTSHADOWKDRREG  ==================================================== */
#define CRYPTO_HOSTSHADOWKDRREG_HOSTSHADOWKDRREG_Pos (0UL)          /*!< HOSTSHADOWKDRREG (Bit 0)                              */
#define CRYPTO_HOSTSHADOWKDRREG_HOSTSHADOWKDRREG_Msk (0x1UL)        /*!< HOSTSHADOWKDRREG (Bitfield-Mask: 0x01)                */
/* ===================================================  HOSTSHADOWKCPREG  ==================================================== */
#define CRYPTO_HOSTSHADOWKCPREG_HOSTSHADOWKCPREG_Pos (0UL)          /*!< HOSTSHADOWKCPREG (Bit 0)                              */
#define CRYPTO_HOSTSHADOWKCPREG_HOSTSHADOWKCPREG_Msk (0x1UL)        /*!< HOSTSHADOWKCPREG (Bitfield-Mask: 0x01)                */
/* ===================================================  HOSTSHADOWKCEREG  ==================================================== */
#define CRYPTO_HOSTSHADOWKCEREG_HOSTSHADOWKCEREG_Pos (0UL)          /*!< HOSTSHADOWKCEREG (Bit 0)                              */
#define CRYPTO_HOSTSHADOWKCEREG_HOSTSHADOWKCEREG_Msk (0x1UL)        /*!< HOSTSHADOWKCEREG (Bitfield-Mask: 0x01)                */
/* ==================================================  HOSTSHADOWKPICVREG  =================================================== */
#define CRYPTO_HOSTSHADOWKPICVREG_HOSTSHADOWKPICVREG_Pos (0UL)      /*!< HOSTSHADOWKPICVREG (Bit 0)                            */
#define CRYPTO_HOSTSHADOWKPICVREG_HOSTSHADOWKPICVREG_Msk (0x1UL)    /*!< HOSTSHADOWKPICVREG (Bitfield-Mask: 0x01)              */
/* ==================================================  HOSTSHADOWKCEICVREG  ================================================== */
#define CRYPTO_HOSTSHADOWKCEICVREG_HOSTSHADOWKCEICVREG_Pos (0UL)    /*!< HOSTSHADOWKCEICVREG (Bit 0)                           */
#define CRYPTO_HOSTSHADOWKCEICVREG_HOSTSHADOWKCEICVREG_Msk (0x1UL)  /*!< HOSTSHADOWKCEICVREG (Bitfield-Mask: 0x01)             */
/* ====================================================  OTPADDRWIDTHDEF  ==================================================== */
#define CRYPTO_OTPADDRWIDTHDEF_OTPADDRWIDTHDEF_Pos (0UL)            /*!< OTPADDRWIDTHDEF (Bit 0)                               */
#define CRYPTO_OTPADDRWIDTHDEF_OTPADDRWIDTHDEF_Msk (0xfUL)          /*!< OTPADDRWIDTHDEF (Bitfield-Mask: 0x0f)                 */


/* =========================================================================================================================== */
/* ================                                            DSP                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  MUTEX0  ========================================================= */
#define DSP_MUTEX0_MUTEX0_Pos             (0UL)                     /*!< MUTEX0 (Bit 0)                                        */
#define DSP_MUTEX0_MUTEX0_Msk             (0x7UL)                   /*!< MUTEX0 (Bitfield-Mask: 0x07)                          */
/* ========================================================  MUTEX1  ========================================================= */
#define DSP_MUTEX1_MUTEX1_Pos             (0UL)                     /*!< MUTEX1 (Bit 0)                                        */
#define DSP_MUTEX1_MUTEX1_Msk             (0x7UL)                   /*!< MUTEX1 (Bitfield-Mask: 0x07)                          */
/* ========================================================  MUTEX2  ========================================================= */
#define DSP_MUTEX2_MUTEX2_Pos             (0UL)                     /*!< MUTEX2 (Bit 0)                                        */
#define DSP_MUTEX2_MUTEX2_Msk             (0x7UL)                   /*!< MUTEX2 (Bitfield-Mask: 0x07)                          */
/* ========================================================  MUTEX3  ========================================================= */
#define DSP_MUTEX3_MUTEX3_Pos             (0UL)                     /*!< MUTEX3 (Bit 0)                                        */
#define DSP_MUTEX3_MUTEX3_Msk             (0x7UL)                   /*!< MUTEX3 (Bitfield-Mask: 0x07)                          */
/* ========================================================  MUTEX4  ========================================================= */
#define DSP_MUTEX4_MUTEX4_Pos             (0UL)                     /*!< MUTEX4 (Bit 0)                                        */
#define DSP_MUTEX4_MUTEX4_Msk             (0x7UL)                   /*!< MUTEX4 (Bitfield-Mask: 0x07)                          */
/* ========================================================  MUTEX5  ========================================================= */
#define DSP_MUTEX5_MUTEX5_Pos             (0UL)                     /*!< MUTEX5 (Bit 0)                                        */
#define DSP_MUTEX5_MUTEX5_Msk             (0x7UL)                   /*!< MUTEX5 (Bitfield-Mask: 0x07)                          */
/* ========================================================  MUTEX6  ========================================================= */
#define DSP_MUTEX6_MUTEX6_Pos             (0UL)                     /*!< MUTEX6 (Bit 0)                                        */
#define DSP_MUTEX6_MUTEX6_Msk             (0x7UL)                   /*!< MUTEX6 (Bitfield-Mask: 0x07)                          */
/* ========================================================  MUTEX7  ========================================================= */
#define DSP_MUTEX7_MUTEX7_Pos             (0UL)                     /*!< MUTEX7 (Bit 0)                                        */
#define DSP_MUTEX7_MUTEX7_Msk             (0x7UL)                   /*!< MUTEX7 (Bitfield-Mask: 0x07)                          */
/* ======================================================  CPUMBINTSET  ====================================================== */
#define DSP_CPUMBINTSET_CPUMBINTSET_Pos   (0UL)                     /*!< CPUMBINTSET (Bit 0)                                   */
#define DSP_CPUMBINTSET_CPUMBINTSET_Msk   (0xffffffffUL)            /*!< CPUMBINTSET (Bitfield-Mask: 0xffffffff)               */
/* ======================================================  CPUMBINTCLR  ====================================================== */
#define DSP_CPUMBINTCLR_CPUMBINTCLR_Pos   (0UL)                     /*!< CPUMBINTCLR (Bit 0)                                   */
#define DSP_CPUMBINTCLR_CPUMBINTCLR_Msk   (0xffffffffUL)            /*!< CPUMBINTCLR (Bitfield-Mask: 0xffffffff)               */
/* =====================================================  CPUMBINTSTAT  ====================================================== */
#define DSP_CPUMBINTSTAT_CPUMBINTSTAT_Pos (0UL)                     /*!< CPUMBINTSTAT (Bit 0)                                  */
#define DSP_CPUMBINTSTAT_CPUMBINTSTAT_Msk (0xffffffffUL)            /*!< CPUMBINTSTAT (Bitfield-Mask: 0xffffffff)              */
/* =====================================================  CPUCPUMBDATA  ====================================================== */
#define DSP_CPUCPUMBDATA_CPUCPUMBDATA_Pos (0UL)                     /*!< CPUCPUMBDATA (Bit 0)                                  */
#define DSP_CPUCPUMBDATA_CPUCPUMBDATA_Msk (0xffffffffUL)            /*!< CPUCPUMBDATA (Bitfield-Mask: 0xffffffff)              */
/* =====================================================  DSP0CPUMBDATA  ===================================================== */
#define DSP_DSP0CPUMBDATA_DSP0CPUMBDATA_Pos (0UL)                   /*!< DSP0CPUMBDATA (Bit 0)                                 */
#define DSP_DSP0CPUMBDATA_DSP0CPUMBDATA_Msk (0xffffffffUL)          /*!< DSP0CPUMBDATA (Bitfield-Mask: 0xffffffff)             */
/* =====================================================  DSP1CPUMBDATA  ===================================================== */
#define DSP_DSP1CPUMBDATA_DSP1CPUMBDATA_Pos (0UL)                   /*!< DSP1CPUMBDATA (Bit 0)                                 */
#define DSP_DSP1CPUMBDATA_DSP1CPUMBDATA_Msk (0xffffffffUL)          /*!< DSP1CPUMBDATA (Bitfield-Mask: 0xffffffff)             */
/* =====================================================  DSP0MBINTSET  ====================================================== */
#define DSP_DSP0MBINTSET_DSP0MBINTSET_Pos (0UL)                     /*!< DSP0MBINTSET (Bit 0)                                  */
#define DSP_DSP0MBINTSET_DSP0MBINTSET_Msk (0xffffffffUL)            /*!< DSP0MBINTSET (Bitfield-Mask: 0xffffffff)              */
/* =====================================================  DSP0MBINTCLR  ====================================================== */
#define DSP_DSP0MBINTCLR_DSP0MBINTCLR_Pos (0UL)                     /*!< DSP0MBINTCLR (Bit 0)                                  */
#define DSP_DSP0MBINTCLR_DSP0MBINTCLR_Msk (0xffffffffUL)            /*!< DSP0MBINTCLR (Bitfield-Mask: 0xffffffff)              */
/* =====================================================  DSP0MBINTSTAT  ===================================================== */
#define DSP_DSP0MBINTSTAT_DSP0MBINTSTAT_Pos (0UL)                   /*!< DSP0MBINTSTAT (Bit 0)                                 */
#define DSP_DSP0MBINTSTAT_DSP0MBINTSTAT_Msk (0xffffffffUL)          /*!< DSP0MBINTSTAT (Bitfield-Mask: 0xffffffff)             */
/* =====================================================  CPUDSP0MBDATA  ===================================================== */
#define DSP_CPUDSP0MBDATA_CPUDSP0MBDATA_Pos (0UL)                   /*!< CPUDSP0MBDATA (Bit 0)                                 */
#define DSP_CPUDSP0MBDATA_CPUDSP0MBDATA_Msk (0xffffffffUL)          /*!< CPUDSP0MBDATA (Bitfield-Mask: 0xffffffff)             */
/* ====================================================  DSP0DSP0MBDATA  ===================================================== */
#define DSP_DSP0DSP0MBDATA_DSP0DSP0MBDATA_Pos (0UL)                 /*!< DSP0DSP0MBDATA (Bit 0)                                */
#define DSP_DSP0DSP0MBDATA_DSP0DSP0MBDATA_Msk (0xffffffffUL)        /*!< DSP0DSP0MBDATA (Bitfield-Mask: 0xffffffff)            */
/* ====================================================  DSP1DSP0MBDATA  ===================================================== */
#define DSP_DSP1DSP0MBDATA_DSP1DSP0MBDATA_Pos (0UL)                 /*!< DSP1DSP0MBDATA (Bit 0)                                */
#define DSP_DSP1DSP0MBDATA_DSP1DSP0MBDATA_Msk (0xffffffffUL)        /*!< DSP1DSP0MBDATA (Bitfield-Mask: 0xffffffff)            */
/* =====================================================  DSP1MBINTSET  ====================================================== */
#define DSP_DSP1MBINTSET_DSP1MBINTSET_Pos (0UL)                     /*!< DSP1MBINTSET (Bit 0)                                  */
#define DSP_DSP1MBINTSET_DSP1MBINTSET_Msk (0xffffffffUL)            /*!< DSP1MBINTSET (Bitfield-Mask: 0xffffffff)              */
/* =====================================================  DSP1MBINTCLR  ====================================================== */
#define DSP_DSP1MBINTCLR_DSP1MBINTCLR_Pos (0UL)                     /*!< DSP1MBINTCLR (Bit 0)                                  */
#define DSP_DSP1MBINTCLR_DSP1MBINTCLR_Msk (0xffffffffUL)            /*!< DSP1MBINTCLR (Bitfield-Mask: 0xffffffff)              */
/* =====================================================  DSP1MBINTSTAT  ===================================================== */
#define DSP_DSP1MBINTSTAT_DSP1MBINTSTAT_Pos (0UL)                   /*!< DSP1MBINTSTAT (Bit 0)                                 */
#define DSP_DSP1MBINTSTAT_DSP1MBINTSTAT_Msk (0xffffffffUL)          /*!< DSP1MBINTSTAT (Bitfield-Mask: 0xffffffff)             */
/* =====================================================  CPUDSP1MBDATA  ===================================================== */
#define DSP_CPUDSP1MBDATA_CPUDSP1MBDATA_Pos (0UL)                   /*!< CPUDSP1MBDATA (Bit 0)                                 */
#define DSP_CPUDSP1MBDATA_CPUDSP1MBDATA_Msk (0xffffffffUL)          /*!< CPUDSP1MBDATA (Bitfield-Mask: 0xffffffff)             */
/* ====================================================  DSP0DSP1MBDATA  ===================================================== */
#define DSP_DSP0DSP1MBDATA_DSP0DSP1MBDATA_Pos (0UL)                 /*!< DSP0DSP1MBDATA (Bit 0)                                */
#define DSP_DSP0DSP1MBDATA_DSP0DSP1MBDATA_Msk (0xffffffffUL)        /*!< DSP0DSP1MBDATA (Bitfield-Mask: 0xffffffff)            */
/* ====================================================  DSP1DSP1MBDATA  ===================================================== */
#define DSP_DSP1DSP1MBDATA_DSP1DSP1MBDATA_Pos (0UL)                 /*!< DSP1DSP1MBDATA (Bit 0)                                */
#define DSP_DSP1DSP1MBDATA_DSP1DSP1MBDATA_Msk (0xffffffffUL)        /*!< DSP1DSP1MBDATA (Bitfield-Mask: 0xffffffff)            */
/* ======================================================  DSP0CONTROL  ====================================================== */
#define DSP_DSP0CONTROL_DSP0IDMAXTRIGSRC_Pos (8UL)                  /*!< DSP0IDMAXTRIGSRC (Bit 8)                              */
#define DSP_DSP0CONTROL_DSP0IDMAXTRIGSRC_Msk (0x7fffff00UL)         /*!< DSP0IDMAXTRIGSRC (Bitfield-Mask: 0x7fffff)            */
#define DSP_DSP0CONTROL_DSP0IDMATRIG_Pos  (4UL)                     /*!< DSP0IDMATRIG (Bit 4)                                  */
#define DSP_DSP0CONTROL_DSP0IDMATRIG_Msk  (0x30UL)                  /*!< DSP0IDMATRIG (Bitfield-Mask: 0x03)                    */
#define DSP_DSP0CONTROL_DSP0RUNSTALL_Pos  (3UL)                     /*!< DSP0RUNSTALL (Bit 3)                                  */
#define DSP_DSP0CONTROL_DSP0RUNSTALL_Msk  (0x8UL)                   /*!< DSP0RUNSTALL (Bitfield-Mask: 0x01)                    */
#define DSP_DSP0CONTROL_DSP0DRESET_Pos    (2UL)                     /*!< DSP0DRESET (Bit 2)                                    */
#define DSP_DSP0CONTROL_DSP0DRESET_Msk    (0x4UL)                   /*!< DSP0DRESET (Bitfield-Mask: 0x01)                      */
#define DSP_DSP0CONTROL_DSP0BRESET_Pos    (1UL)                     /*!< DSP0BRESET (Bit 1)                                    */
#define DSP_DSP0CONTROL_DSP0BRESET_Msk    (0x2UL)                   /*!< DSP0BRESET (Bitfield-Mask: 0x01)                      */
#define DSP_DSP0CONTROL_DSP0STATVECSEL_Pos (0UL)                    /*!< DSP0STATVECSEL (Bit 0)                                */
#define DSP_DSP0CONTROL_DSP0STATVECSEL_Msk (0x1UL)                  /*!< DSP0STATVECSEL (Bitfield-Mask: 0x01)                  */
/* =====================================================  DSP0RESETVEC  ====================================================== */
#define DSP_DSP0RESETVEC_DSP0RESETVEC_Pos (0UL)                     /*!< DSP0RESETVEC (Bit 0)                                  */
#define DSP_DSP0RESETVEC_DSP0RESETVEC_Msk (0xffffffffUL)            /*!< DSP0RESETVEC (Bitfield-Mask: 0xffffffff)              */
/* ======================================================  DSP0IRQMASK  ====================================================== */
#define DSP_DSP0IRQMASK_DSP0IRQMASK_Pos   (0UL)                     /*!< DSP0IRQMASK (Bit 0)                                   */
#define DSP_DSP0IRQMASK_DSP0IRQMASK_Msk   (0x7fffffUL)              /*!< DSP0IRQMASK (Bitfield-Mask: 0x7fffff)                 */
/* =====================================================  DSP0WAKEMASK  ====================================================== */
#define DSP_DSP0WAKEMASK_DSP0WAKEMASK_Pos (0UL)                     /*!< DSP0WAKEMASK (Bit 0)                                  */
#define DSP_DSP0WAKEMASK_DSP0WAKEMASK_Msk (0x7fffffUL)              /*!< DSP0WAKEMASK (Bitfield-Mask: 0x7fffff)                */
/* ==================================================  DSP0RAWIRQSTAT31to0  ================================================== */
#define DSP_DSP0RAWIRQSTAT31to0_DSP0RAWIRQSTAT31to0_Pos (0UL)       /*!< DSP0RAWIRQSTAT31to0 (Bit 0)                           */
#define DSP_DSP0RAWIRQSTAT31to0_DSP0RAWIRQSTAT31to0_Msk (0xffffffffUL) /*!< DSP0RAWIRQSTAT31to0 (Bitfield-Mask: 0xffffffff)    */
/* =================================================  DSP0RAWIRQSTAT63to32  ================================================== */
#define DSP_DSP0RAWIRQSTAT63to32_DSP0RAWIRQSTAT63to32_Pos (0UL)     /*!< DSP0RAWIRQSTAT63to32 (Bit 0)                          */
#define DSP_DSP0RAWIRQSTAT63to32_DSP0RAWIRQSTAT63to32_Msk (0xffffffffUL) /*!< DSP0RAWIRQSTAT63to32 (Bitfield-Mask: 0xffffffff) */
/* =================================================  DSP0RAWIRQSTAT95to64  ================================================== */
#define DSP_DSP0RAWIRQSTAT95to64_DSP0RAWIRQSTAT95to64_Pos (0UL)     /*!< DSP0RAWIRQSTAT95to64 (Bit 0)                          */
#define DSP_DSP0RAWIRQSTAT95to64_DSP0RAWIRQSTAT95to64_Msk (0xffffffffUL) /*!< DSP0RAWIRQSTAT95to64 (Bitfield-Mask: 0xffffffff) */
/* =====================================================  DSP0L2LVLINT  ====================================================== */
#define DSP_DSP0L2LVLINT_DSP0L2LVLINT_Pos (0UL)                     /*!< DSP0L2LVLINT (Bit 0)                                  */
#define DSP_DSP0L2LVLINT_DSP0L2LVLINT_Msk (0x7ffffUL)               /*!< DSP0L2LVLINT (Bitfield-Mask: 0x7ffff)                 */
/* =====================================================  DSP0L3LVLINT  ====================================================== */
#define DSP_DSP0L3LVLINT_DSP0L3LVLINT_Pos (0UL)                     /*!< DSP0L3LVLINT (Bit 0)                                  */
#define DSP_DSP0L3LVLINT_DSP0L3LVLINT_Msk (0x7ffffUL)               /*!< DSP0L3LVLINT (Bitfield-Mask: 0x7ffff)                 */
/* =====================================================  DSP0L4LVLINT  ====================================================== */
#define DSP_DSP0L4LVLINT_DSP0L4LVLINT_Pos (0UL)                     /*!< DSP0L4LVLINT (Bit 0)                                  */
#define DSP_DSP0L4LVLINT_DSP0L4LVLINT_Msk (0x7ffffUL)               /*!< DSP0L4LVLINT (Bitfield-Mask: 0x7ffff)                 */
/* =====================================================  DSP0L5LVLINT  ====================================================== */
#define DSP_DSP0L5LVLINT_DSP0L5LVLINT_Pos (0UL)                     /*!< DSP0L5LVLINT (Bit 0)                                  */
#define DSP_DSP0L5LVLINT_DSP0L5LVLINT_Msk (0x7ffffUL)               /*!< DSP0L5LVLINT (Bitfield-Mask: 0x7ffff)                 */
/* ====================================================  DSP0IDMATRIGCTL  ==================================================== */
#define DSP_DSP0IDMATRIGCTL_DSP0IDMATRIGPULSE_Pos (4UL)             /*!< DSP0IDMATRIGPULSE (Bit 4)                             */
#define DSP_DSP0IDMATRIGCTL_DSP0IDMATRIGPULSE_Msk (0x10UL)          /*!< DSP0IDMATRIGPULSE (Bitfield-Mask: 0x01)               */
#define DSP_DSP0IDMATRIGCTL_DSP0IDMATRIGSTAT_Pos (0UL)              /*!< DSP0IDMATRIGSTAT (Bit 0)                              */
#define DSP_DSP0IDMATRIGCTL_DSP0IDMATRIGSTAT_Msk (0x1UL)            /*!< DSP0IDMATRIGSTAT (Bitfield-Mask: 0x01)                */
/* ==================================================  DSP0INTORMASK31TO0A  ================================================== */
#define DSP_DSP0INTORMASK31TO0A_DSP0INTMCUIOORMASKA_Pos (0UL)       /*!< DSP0INTMCUIOORMASKA (Bit 0)                           */
#define DSP_DSP0INTORMASK31TO0A_DSP0INTMCUIOORMASKA_Msk (0xffffffffUL) /*!< DSP0INTMCUIOORMASKA (Bitfield-Mask: 0xffffffff)    */
/* =================================================  DSP0INTORMASK63TO32A  ================================================== */
#define DSP_DSP0INTORMASK63TO32A_DSP0GPIOORMASKA_Pos (24UL)         /*!< DSP0GPIOORMASKA (Bit 24)                              */
#define DSP_DSP0INTORMASK63TO32A_DSP0GPIOORMASKA_Msk (0x3f000000UL) /*!< DSP0GPIOORMASKA (Bitfield-Mask: 0x3f)                 */
#define DSP_DSP0INTORMASK63TO32A_DSP0PDMORMASKA_Pos (16UL)          /*!< DSP0PDMORMASKA (Bit 16)                               */
#define DSP_DSP0INTORMASK63TO32A_DSP0PDMORMASKA_Msk (0xf0000UL)     /*!< DSP0PDMORMASKA (Bitfield-Mask: 0x0f)                  */
#define DSP_DSP0INTORMASK63TO32A_DSP0I2SORMASKA_Pos (12UL)          /*!< DSP0I2SORMASKA (Bit 12)                               */
#define DSP_DSP0INTORMASK63TO32A_DSP0I2SORMASKA_Msk (0xf000UL)      /*!< DSP0I2SORMASKA (Bitfield-Mask: 0x0f)                  */
#define DSP_DSP0INTORMASK63TO32A_DSP0TMRORMASKA_Pos (0UL)           /*!< DSP0TMRORMASKA (Bit 0)                                */
#define DSP_DSP0INTORMASK63TO32A_DSP0TMRORMASKA_Msk (0x3ffUL)       /*!< DSP0TMRORMASKA (Bitfield-Mask: 0x3ff)                 */
/* =================================================  DSP0INTORMASK95TO64A  ================================================== */
#define DSP_DSP0INTORMASK95TO64A_DSP0MBINTORMASKA_Pos (0UL)         /*!< DSP0MBINTORMASKA (Bit 0)                              */
#define DSP_DSP0INTORMASK95TO64A_DSP0MBINTORMASKA_Msk (0xffffffffUL) /*!< DSP0MBINTORMASKA (Bitfield-Mask: 0xffffffff)         */
/* ==================================================  DSP0INTORMASK31to0B  ================================================== */
#define DSP_DSP0INTORMASK31to0B_DSP0INTMCUIOORMASKB_Pos (0UL)       /*!< DSP0INTMCUIOORMASKB (Bit 0)                           */
#define DSP_DSP0INTORMASK31to0B_DSP0INTMCUIOORMASKB_Msk (0xffffffffUL) /*!< DSP0INTMCUIOORMASKB (Bitfield-Mask: 0xffffffff)    */
/* =================================================  DSP0INTORMASK63TO32B  ================================================== */
#define DSP_DSP0INTORMASK63TO32B_DSP0GPIOORMASKB_Pos (24UL)         /*!< DSP0GPIOORMASKB (Bit 24)                              */
#define DSP_DSP0INTORMASK63TO32B_DSP0GPIOORMASKB_Msk (0x3f000000UL) /*!< DSP0GPIOORMASKB (Bitfield-Mask: 0x3f)                 */
#define DSP_DSP0INTORMASK63TO32B_DSP0PDMORMASKB_Pos (16UL)          /*!< DSP0PDMORMASKB (Bit 16)                               */
#define DSP_DSP0INTORMASK63TO32B_DSP0PDMORMASKB_Msk (0xf0000UL)     /*!< DSP0PDMORMASKB (Bitfield-Mask: 0x0f)                  */
#define DSP_DSP0INTORMASK63TO32B_DSP0I2SORMASKB_Pos (12UL)          /*!< DSP0I2SORMASKB (Bit 12)                               */
#define DSP_DSP0INTORMASK63TO32B_DSP0I2SORMASKB_Msk (0xf000UL)      /*!< DSP0I2SORMASKB (Bitfield-Mask: 0x0f)                  */
#define DSP_DSP0INTORMASK63TO32B_DSP0TMRORMASKB_Pos (0UL)           /*!< DSP0TMRORMASKB (Bit 0)                                */
#define DSP_DSP0INTORMASK63TO32B_DSP0TMRORMASKB_Msk (0x3ffUL)       /*!< DSP0TMRORMASKB (Bitfield-Mask: 0x3ff)                 */
/* =================================================  DSP0INTORMASK95TO64B  ================================================== */
#define DSP_DSP0INTORMASK95TO64B_DSP0MBINTORMASKB_Pos (0UL)         /*!< DSP0MBINTORMASKB (Bit 0)                              */
#define DSP_DSP0INTORMASK95TO64B_DSP0MBINTORMASKB_Msk (0xffffffffUL) /*!< DSP0MBINTORMASKB (Bitfield-Mask: 0xffffffff)         */
/* ===================================================  DSP0INTENIRQ31TO0  =================================================== */
#define DSP_DSP0INTENIRQ31TO0_DSP0INTENIRQ31TO0_Pos (0UL)           /*!< DSP0INTENIRQ31TO0 (Bit 0)                             */
#define DSP_DSP0INTENIRQ31TO0_DSP0INTENIRQ31TO0_Msk (0xffffffffUL)  /*!< DSP0INTENIRQ31TO0 (Bitfield-Mask: 0xffffffff)         */
/* ==================================================  DSP0INTENIRQ63TO32  =================================================== */
#define DSP_DSP0INTENIRQ63TO32_DSP0INTENIRQ63TO32_Pos (0UL)         /*!< DSP0INTENIRQ63TO32 (Bit 0)                            */
#define DSP_DSP0INTENIRQ63TO32_DSP0INTENIRQ63TO32_Msk (0xffffffffUL) /*!< DSP0INTENIRQ63TO32 (Bitfield-Mask: 0xffffffff)       */
/* ==================================================  DSP0INTENIRQ95TO64  =================================================== */
#define DSP_DSP0INTENIRQ95TO64_DSP0INTENIRQ95TO64_Pos (0UL)         /*!< DSP0INTENIRQ95TO64 (Bit 0)                            */
#define DSP_DSP0INTENIRQ95TO64_DSP0INTENIRQ95TO64_Msk (0xffffffffUL) /*!< DSP0INTENIRQ95TO64 (Bitfield-Mask: 0xffffffff)       */
/* ======================================================  DSP1CONTROL  ====================================================== */
#define DSP_DSP1CONTROL_DSP1IDMAXTRIGSRC_Pos (8UL)                  /*!< DSP1IDMAXTRIGSRC (Bit 8)                              */
#define DSP_DSP1CONTROL_DSP1IDMAXTRIGSRC_Msk (0x7fffff00UL)         /*!< DSP1IDMAXTRIGSRC (Bitfield-Mask: 0x7fffff)            */
#define DSP_DSP1CONTROL_DSP1IDMATRIG_Pos  (4UL)                     /*!< DSP1IDMATRIG (Bit 4)                                  */
#define DSP_DSP1CONTROL_DSP1IDMATRIG_Msk  (0x30UL)                  /*!< DSP1IDMATRIG (Bitfield-Mask: 0x03)                    */
#define DSP_DSP1CONTROL_DSP1RUNSTALL_Pos  (3UL)                     /*!< DSP1RUNSTALL (Bit 3)                                  */
#define DSP_DSP1CONTROL_DSP1RUNSTALL_Msk  (0x8UL)                   /*!< DSP1RUNSTALL (Bitfield-Mask: 0x01)                    */
#define DSP_DSP1CONTROL_DSP1DRESET_Pos    (2UL)                     /*!< DSP1DRESET (Bit 2)                                    */
#define DSP_DSP1CONTROL_DSP1DRESET_Msk    (0x4UL)                   /*!< DSP1DRESET (Bitfield-Mask: 0x01)                      */
#define DSP_DSP1CONTROL_DSP1BRESET_Pos    (1UL)                     /*!< DSP1BRESET (Bit 1)                                    */
#define DSP_DSP1CONTROL_DSP1BRESET_Msk    (0x2UL)                   /*!< DSP1BRESET (Bitfield-Mask: 0x01)                      */
#define DSP_DSP1CONTROL_DSP1STATVECSEL_Pos (0UL)                    /*!< DSP1STATVECSEL (Bit 0)                                */
#define DSP_DSP1CONTROL_DSP1STATVECSEL_Msk (0x1UL)                  /*!< DSP1STATVECSEL (Bitfield-Mask: 0x01)                  */
/* =====================================================  DSP1RESETVEC  ====================================================== */
#define DSP_DSP1RESETVEC_DSP1RESETVEC_Pos (0UL)                     /*!< DSP1RESETVEC (Bit 0)                                  */
#define DSP_DSP1RESETVEC_DSP1RESETVEC_Msk (0xffffffffUL)            /*!< DSP1RESETVEC (Bitfield-Mask: 0xffffffff)              */
/* ======================================================  DSP1IRQMASK  ====================================================== */
#define DSP_DSP1IRQMASK_DSP1IRQMASK_Pos   (0UL)                     /*!< DSP1IRQMASK (Bit 0)                                   */
#define DSP_DSP1IRQMASK_DSP1IRQMASK_Msk   (0x7fffffUL)              /*!< DSP1IRQMASK (Bitfield-Mask: 0x7fffff)                 */
/* =====================================================  DSP1WAKEMASK  ====================================================== */
#define DSP_DSP1WAKEMASK_DSP1WAKEMASK_Pos (0UL)                     /*!< DSP1WAKEMASK (Bit 0)                                  */
#define DSP_DSP1WAKEMASK_DSP1WAKEMASK_Msk (0x7fffffUL)              /*!< DSP1WAKEMASK (Bitfield-Mask: 0x7fffff)                */
/* ==================================================  DSP1RAWIRQSTAT31to0  ================================================== */
#define DSP_DSP1RAWIRQSTAT31to0_DSP1RAWIRQSTAT31to0_Pos (0UL)       /*!< DSP1RAWIRQSTAT31to0 (Bit 0)                           */
#define DSP_DSP1RAWIRQSTAT31to0_DSP1RAWIRQSTAT31to0_Msk (0xffffffffUL) /*!< DSP1RAWIRQSTAT31to0 (Bitfield-Mask: 0xffffffff)    */
/* =================================================  DSP1RAWIRQSTAT63to32  ================================================== */
#define DSP_DSP1RAWIRQSTAT63to32_DSP1RAWIRQSTAT63to32_Pos (0UL)     /*!< DSP1RAWIRQSTAT63to32 (Bit 0)                          */
#define DSP_DSP1RAWIRQSTAT63to32_DSP1RAWIRQSTAT63to32_Msk (0xffffffffUL) /*!< DSP1RAWIRQSTAT63to32 (Bitfield-Mask: 0xffffffff) */
/* =================================================  DSP1RAWIRQSTAT95to64  ================================================== */
#define DSP_DSP1RAWIRQSTAT95to64_DSP1RAWIRQSTAT95to64_Pos (0UL)     /*!< DSP1RAWIRQSTAT95to64 (Bit 0)                          */
#define DSP_DSP1RAWIRQSTAT95to64_DSP1RAWIRQSTAT95to64_Msk (0xffffffffUL) /*!< DSP1RAWIRQSTAT95to64 (Bitfield-Mask: 0xffffffff) */
/* =====================================================  DSP1L2LVLINT  ====================================================== */
#define DSP_DSP1L2LVLINT_DSP1L2LVLINT_Pos (0UL)                     /*!< DSP1L2LVLINT (Bit 0)                                  */
#define DSP_DSP1L2LVLINT_DSP1L2LVLINT_Msk (0x7ffffUL)               /*!< DSP1L2LVLINT (Bitfield-Mask: 0x7ffff)                 */
/* =====================================================  DSP1L3LVLINT  ====================================================== */
#define DSP_DSP1L3LVLINT_DSP1L3LVLINT_Pos (0UL)                     /*!< DSP1L3LVLINT (Bit 0)                                  */
#define DSP_DSP1L3LVLINT_DSP1L3LVLINT_Msk (0x7ffffUL)               /*!< DSP1L3LVLINT (Bitfield-Mask: 0x7ffff)                 */
/* =====================================================  DSP1L4LVLINT  ====================================================== */
#define DSP_DSP1L4LVLINT_DSP1L4LVLINT_Pos (0UL)                     /*!< DSP1L4LVLINT (Bit 0)                                  */
#define DSP_DSP1L4LVLINT_DSP1L4LVLINT_Msk (0x7ffffUL)               /*!< DSP1L4LVLINT (Bitfield-Mask: 0x7ffff)                 */
/* =====================================================  DSP1L5LVLINT  ====================================================== */
#define DSP_DSP1L5LVLINT_DSP1L5LVLINT_Pos (0UL)                     /*!< DSP1L5LVLINT (Bit 0)                                  */
#define DSP_DSP1L5LVLINT_DSP1L5LVLINT_Msk (0x7ffffUL)               /*!< DSP1L5LVLINT (Bitfield-Mask: 0x7ffff)                 */
/* ====================================================  DSP1IDMATRIGCTL  ==================================================== */
#define DSP_DSP1IDMATRIGCTL_DSP1IDMATRIGPULSE_Pos (4UL)             /*!< DSP1IDMATRIGPULSE (Bit 4)                             */
#define DSP_DSP1IDMATRIGCTL_DSP1IDMATRIGPULSE_Msk (0x10UL)          /*!< DSP1IDMATRIGPULSE (Bitfield-Mask: 0x01)               */
#define DSP_DSP1IDMATRIGCTL_DSP1IDMATRIGSTAT_Pos (0UL)              /*!< DSP1IDMATRIGSTAT (Bit 0)                              */
#define DSP_DSP1IDMATRIGCTL_DSP1IDMATRIGSTAT_Msk (0x1UL)            /*!< DSP1IDMATRIGSTAT (Bitfield-Mask: 0x01)                */
/* ==================================================  DSP1INTORMASK31TO0A  ================================================== */
#define DSP_DSP1INTORMASK31TO0A_DSP1INTMCUIOORMASKA_Pos (0UL)       /*!< DSP1INTMCUIOORMASKA (Bit 0)                           */
#define DSP_DSP1INTORMASK31TO0A_DSP1INTMCUIOORMASKA_Msk (0xffffffffUL) /*!< DSP1INTMCUIOORMASKA (Bitfield-Mask: 0xffffffff)    */
/* =================================================  DSP1INTORMASK63TO32A  ================================================== */
#define DSP_DSP1INTORMASK63TO32A_DSP1GPIOORMASKA_Pos (24UL)         /*!< DSP1GPIOORMASKA (Bit 24)                              */
#define DSP_DSP1INTORMASK63TO32A_DSP1GPIOORMASKA_Msk (0x3f000000UL) /*!< DSP1GPIOORMASKA (Bitfield-Mask: 0x3f)                 */
#define DSP_DSP1INTORMASK63TO32A_DSP1PDMORMASKA_Pos (16UL)          /*!< DSP1PDMORMASKA (Bit 16)                               */
#define DSP_DSP1INTORMASK63TO32A_DSP1PDMORMASKA_Msk (0xf0000UL)     /*!< DSP1PDMORMASKA (Bitfield-Mask: 0x0f)                  */
#define DSP_DSP1INTORMASK63TO32A_DSP1I2SORMASKA_Pos (12UL)          /*!< DSP1I2SORMASKA (Bit 12)                               */
#define DSP_DSP1INTORMASK63TO32A_DSP1I2SORMASKA_Msk (0xf000UL)      /*!< DSP1I2SORMASKA (Bitfield-Mask: 0x0f)                  */
#define DSP_DSP1INTORMASK63TO32A_DSP1TMRORMASKA_Pos (0UL)           /*!< DSP1TMRORMASKA (Bit 0)                                */
#define DSP_DSP1INTORMASK63TO32A_DSP1TMRORMASKA_Msk (0x3ffUL)       /*!< DSP1TMRORMASKA (Bitfield-Mask: 0x3ff)                 */
/* =================================================  DSP1INTORMASK95TO64A  ================================================== */
#define DSP_DSP1INTORMASK95TO64A_DSP1MBINTORMASKA_Pos (0UL)         /*!< DSP1MBINTORMASKA (Bit 0)                              */
#define DSP_DSP1INTORMASK95TO64A_DSP1MBINTORMASKA_Msk (0xffffffffUL) /*!< DSP1MBINTORMASKA (Bitfield-Mask: 0xffffffff)         */
/* ==================================================  DSP1INTORMASK31to0B  ================================================== */
#define DSP_DSP1INTORMASK31to0B_DSP1INTMCUIOORMASKB_Pos (0UL)       /*!< DSP1INTMCUIOORMASKB (Bit 0)                           */
#define DSP_DSP1INTORMASK31to0B_DSP1INTMCUIOORMASKB_Msk (0xffffffffUL) /*!< DSP1INTMCUIOORMASKB (Bitfield-Mask: 0xffffffff)    */
/* =================================================  DSP1INTORMASK63TO32B  ================================================== */
#define DSP_DSP1INTORMASK63TO32B_DSP1GPIOORMASKB_Pos (24UL)         /*!< DSP1GPIOORMASKB (Bit 24)                              */
#define DSP_DSP1INTORMASK63TO32B_DSP1GPIOORMASKB_Msk (0x3f000000UL) /*!< DSP1GPIOORMASKB (Bitfield-Mask: 0x3f)                 */
#define DSP_DSP1INTORMASK63TO32B_DSP1PDMORMASKB_Pos (16UL)          /*!< DSP1PDMORMASKB (Bit 16)                               */
#define DSP_DSP1INTORMASK63TO32B_DSP1PDMORMASKB_Msk (0xf0000UL)     /*!< DSP1PDMORMASKB (Bitfield-Mask: 0x0f)                  */
#define DSP_DSP1INTORMASK63TO32B_DSP1I2SORMASKB_Pos (12UL)          /*!< DSP1I2SORMASKB (Bit 12)                               */
#define DSP_DSP1INTORMASK63TO32B_DSP1I2SORMASKB_Msk (0xf000UL)      /*!< DSP1I2SORMASKB (Bitfield-Mask: 0x0f)                  */
#define DSP_DSP1INTORMASK63TO32B_DSP1TMRORMASKB_Pos (0UL)           /*!< DSP1TMRORMASKB (Bit 0)                                */
#define DSP_DSP1INTORMASK63TO32B_DSP1TMRORMASKB_Msk (0x3ffUL)       /*!< DSP1TMRORMASKB (Bitfield-Mask: 0x3ff)                 */
/* =================================================  DSP1INTORMASK95TO64B  ================================================== */
#define DSP_DSP1INTORMASK95TO64B_DSP1MBINTORMASKB_Pos (0UL)         /*!< DSP1MBINTORMASKB (Bit 0)                              */
#define DSP_DSP1INTORMASK95TO64B_DSP1MBINTORMASKB_Msk (0xffffffffUL) /*!< DSP1MBINTORMASKB (Bitfield-Mask: 0xffffffff)         */
/* ===================================================  DSP1INTENIRQ31TO0  =================================================== */
#define DSP_DSP1INTENIRQ31TO0_DSP1INTENIRQ31TO0_Pos (0UL)           /*!< DSP1INTENIRQ31TO0 (Bit 0)                             */
#define DSP_DSP1INTENIRQ31TO0_DSP1INTENIRQ31TO0_Msk (0xffffffffUL)  /*!< DSP1INTENIRQ31TO0 (Bitfield-Mask: 0xffffffff)         */
/* ==================================================  DSP1INTENIRQ63TO32  =================================================== */
#define DSP_DSP1INTENIRQ63TO32_DSP1INTENIRQ63TO32_Pos (0UL)         /*!< DSP1INTENIRQ63TO32 (Bit 0)                            */
#define DSP_DSP1INTENIRQ63TO32_DSP1INTENIRQ63TO32_Msk (0xffffffffUL) /*!< DSP1INTENIRQ63TO32 (Bitfield-Mask: 0xffffffff)       */
/* ==================================================  DSP1INTENIRQ95TO64  =================================================== */
#define DSP_DSP1INTENIRQ95TO64_DSP1INTENIRQ95TO64_Pos (0UL)         /*!< DSP1INTENIRQ95TO64 (Bit 0)                            */
#define DSP_DSP1INTENIRQ95TO64_DSP1INTENIRQ95TO64_Msk (0xffffffffUL) /*!< DSP1INTENIRQ95TO64 (Bitfield-Mask: 0xffffffff)       */


/* =========================================================================================================================== */
/* ================                                           FPIO                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  RD0  ========================================================== */
#define FPIO_RD0_RD0_Pos                  (0UL)                     /*!< RD0 (Bit 0)                                           */
#define FPIO_RD0_RD0_Msk                  (0xffffffffUL)            /*!< RD0 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  RD1  ========================================================== */
#define FPIO_RD1_RD1_Pos                  (0UL)                     /*!< RD1 (Bit 0)                                           */
#define FPIO_RD1_RD1_Msk                  (0xffffffffUL)            /*!< RD1 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  RD2  ========================================================== */
#define FPIO_RD2_RD2_Pos                  (0UL)                     /*!< RD2 (Bit 0)                                           */
#define FPIO_RD2_RD2_Msk                  (0xffffffffUL)            /*!< RD2 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  RD3  ========================================================== */
#define FPIO_RD3_RD3_Pos                  (0UL)                     /*!< RD3 (Bit 0)                                           */
#define FPIO_RD3_RD3_Msk                  (0xffffffffUL)            /*!< RD3 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  WT0  ========================================================== */
#define FPIO_WT0_WT0_Pos                  (0UL)                     /*!< WT0 (Bit 0)                                           */
#define FPIO_WT0_WT0_Msk                  (0xffffffffUL)            /*!< WT0 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  WT1  ========================================================== */
#define FPIO_WT1_WT1_Pos                  (0UL)                     /*!< WT1 (Bit 0)                                           */
#define FPIO_WT1_WT1_Msk                  (0xffffffffUL)            /*!< WT1 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  WT2  ========================================================== */
#define FPIO_WT2_WT2_Pos                  (0UL)                     /*!< WT2 (Bit 0)                                           */
#define FPIO_WT2_WT2_Msk                  (0xffffffffUL)            /*!< WT2 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  WT3  ========================================================== */
#define FPIO_WT3_WT3_Pos                  (0UL)                     /*!< WT3 (Bit 0)                                           */
#define FPIO_WT3_WT3_Msk                  (0xffffffffUL)            /*!< WT3 (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  WTS0  ========================================================== */
#define FPIO_WTS0_WTS0_Pos                (0UL)                     /*!< WTS0 (Bit 0)                                          */
#define FPIO_WTS0_WTS0_Msk                (0xffffffffUL)            /*!< WTS0 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  WTS1  ========================================================== */
#define FPIO_WTS1_WTS1_Pos                (0UL)                     /*!< WTS1 (Bit 0)                                          */
#define FPIO_WTS1_WTS1_Msk                (0xffffffffUL)            /*!< WTS1 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  WTS2  ========================================================== */
#define FPIO_WTS2_WTS2_Pos                (0UL)                     /*!< WTS2 (Bit 0)                                          */
#define FPIO_WTS2_WTS2_Msk                (0xffffffffUL)            /*!< WTS2 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  WTS3  ========================================================== */
#define FPIO_WTS3_WTS3_Pos                (0UL)                     /*!< WTS3 (Bit 0)                                          */
#define FPIO_WTS3_WTS3_Msk                (0xffffffffUL)            /*!< WTS3 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  WTC0  ========================================================== */
#define FPIO_WTC0_WTC0_Pos                (0UL)                     /*!< WTC0 (Bit 0)                                          */
#define FPIO_WTC0_WTC0_Msk                (0xffffffffUL)            /*!< WTC0 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  WTC1  ========================================================== */
#define FPIO_WTC1_WTC1_Pos                (0UL)                     /*!< WTC1 (Bit 0)                                          */
#define FPIO_WTC1_WTC1_Msk                (0xffffffffUL)            /*!< WTC1 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  WTC2  ========================================================== */
#define FPIO_WTC2_WTC2_Pos                (0UL)                     /*!< WTC2 (Bit 0)                                          */
#define FPIO_WTC2_WTC2_Msk                (0xffffffffUL)            /*!< WTC2 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  WTC3  ========================================================== */
#define FPIO_WTC3_WTC3_Pos                (0UL)                     /*!< WTC3 (Bit 0)                                          */
#define FPIO_WTC3_WTC3_Msk                (0xffffffffUL)            /*!< WTC3 (Bitfield-Mask: 0xffffffff)                      */
/* ==========================================================  EN0  ========================================================== */
#define FPIO_EN0_EN0_Pos                  (0UL)                     /*!< EN0 (Bit 0)                                           */
#define FPIO_EN0_EN0_Msk                  (0xffffffffUL)            /*!< EN0 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  EN1  ========================================================== */
#define FPIO_EN1_EN1_Pos                  (0UL)                     /*!< EN1 (Bit 0)                                           */
#define FPIO_EN1_EN1_Msk                  (0xffffffffUL)            /*!< EN1 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  EN2  ========================================================== */
#define FPIO_EN2_EN2_Pos                  (0UL)                     /*!< EN2 (Bit 0)                                           */
#define FPIO_EN2_EN2_Msk                  (0xffffffffUL)            /*!< EN2 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  EN3  ========================================================== */
#define FPIO_EN3_EN3_Pos                  (0UL)                     /*!< EN3 (Bit 0)                                           */
#define FPIO_EN3_EN3_Msk                  (0xffffffffUL)            /*!< EN3 (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  ENS0  ========================================================== */
#define FPIO_ENS0_ENS0_Pos                (0UL)                     /*!< ENS0 (Bit 0)                                          */
#define FPIO_ENS0_ENS0_Msk                (0xffffffffUL)            /*!< ENS0 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  ENS1  ========================================================== */
#define FPIO_ENS1_ENS1_Pos                (0UL)                     /*!< ENS1 (Bit 0)                                          */
#define FPIO_ENS1_ENS1_Msk                (0xffffffffUL)            /*!< ENS1 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  ENS2  ========================================================== */
#define FPIO_ENS2_ENS2_Pos                (0UL)                     /*!< ENS2 (Bit 0)                                          */
#define FPIO_ENS2_ENS2_Msk                (0xffffffffUL)            /*!< ENS2 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  ENS3  ========================================================== */
#define FPIO_ENS3_ENS3_Pos                (0UL)                     /*!< ENS3 (Bit 0)                                          */
#define FPIO_ENS3_ENS3_Msk                (0xffffffffUL)            /*!< ENS3 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  ENC0  ========================================================== */
#define FPIO_ENC0_ENC0_Pos                (0UL)                     /*!< ENC0 (Bit 0)                                          */
#define FPIO_ENC0_ENC0_Msk                (0xffffffffUL)            /*!< ENC0 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  ENC1  ========================================================== */
#define FPIO_ENC1_ENC1_Pos                (0UL)                     /*!< ENC1 (Bit 0)                                          */
#define FPIO_ENC1_ENC1_Msk                (0xffffffffUL)            /*!< ENC1 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  ENC2  ========================================================== */
#define FPIO_ENC2_ENC2_Pos                (0UL)                     /*!< ENC2 (Bit 0)                                          */
#define FPIO_ENC2_ENC2_Msk                (0xffffffffUL)            /*!< ENC2 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  ENC3  ========================================================== */
#define FPIO_ENC3_ENC3_Pos                (0UL)                     /*!< ENC3 (Bit 0)                                          */
#define FPIO_ENC3_ENC3_Msk                (0xffffffffUL)            /*!< ENC3 (Bitfield-Mask: 0xffffffff)                      */


/* =========================================================================================================================== */
/* ================                                           GPIO                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  PINCFG0  ======================================================== */
#define GPIO_PINCFG0_FOEN0_Pos            (27UL)                    /*!< FOEN0 (Bit 27)                                        */
#define GPIO_PINCFG0_FOEN0_Msk            (0x8000000UL)             /*!< FOEN0 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG0_FIEN0_Pos            (26UL)                    /*!< FIEN0 (Bit 26)                                        */
#define GPIO_PINCFG0_FIEN0_Msk            (0x4000000UL)             /*!< FIEN0 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG0_NCEPOL0_Pos          (22UL)                    /*!< NCEPOL0 (Bit 22)                                      */
#define GPIO_PINCFG0_NCEPOL0_Msk          (0x400000UL)              /*!< NCEPOL0 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG0_NCESRC0_Pos          (16UL)                    /*!< NCESRC0 (Bit 16)                                      */
#define GPIO_PINCFG0_NCESRC0_Msk          (0x3f0000UL)              /*!< NCESRC0 (Bitfield-Mask: 0x3f)                         */
#define GPIO_PINCFG0_PULLCFG0_Pos         (13UL)                    /*!< PULLCFG0 (Bit 13)                                     */
#define GPIO_PINCFG0_PULLCFG0_Msk         (0xe000UL)                /*!< PULLCFG0 (Bitfield-Mask: 0x07)                        */
#define GPIO_PINCFG0_SR0_Pos              (12UL)                    /*!< SR0 (Bit 12)                                          */
#define GPIO_PINCFG0_SR0_Msk              (0x1000UL)                /*!< SR0 (Bitfield-Mask: 0x01)                             */
#define GPIO_PINCFG0_DS0_Pos              (10UL)                    /*!< DS0 (Bit 10)                                          */
#define GPIO_PINCFG0_DS0_Msk              (0xc00UL)                 /*!< DS0 (Bitfield-Mask: 0x03)                             */
#define GPIO_PINCFG0_OUTCFG0_Pos          (8UL)                     /*!< OUTCFG0 (Bit 8)                                       */
#define GPIO_PINCFG0_OUTCFG0_Msk          (0x300UL)                 /*!< OUTCFG0 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG0_IRPTEN0_Pos          (6UL)                     /*!< IRPTEN0 (Bit 6)                                       */
#define GPIO_PINCFG0_IRPTEN0_Msk          (0xc0UL)                  /*!< IRPTEN0 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG0_RDZERO0_Pos          (5UL)                     /*!< RDZERO0 (Bit 5)                                       */
#define GPIO_PINCFG0_RDZERO0_Msk          (0x20UL)                  /*!< RDZERO0 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG0_INPEN0_Pos           (4UL)                     /*!< INPEN0 (Bit 4)                                        */
#define GPIO_PINCFG0_INPEN0_Msk           (0x10UL)                  /*!< INPEN0 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG0_FNCSEL0_Pos          (0UL)                     /*!< FNCSEL0 (Bit 0)                                       */
#define GPIO_PINCFG0_FNCSEL0_Msk          (0xfUL)                   /*!< FNCSEL0 (Bitfield-Mask: 0x0f)                         */
/* ========================================================  PINCFG1  ======================================================== */
#define GPIO_PINCFG1_FOEN1_Pos            (27UL)                    /*!< FOEN1 (Bit 27)                                        */
#define GPIO_PINCFG1_FOEN1_Msk            (0x8000000UL)             /*!< FOEN1 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG1_FIEN1_Pos            (26UL)                    /*!< FIEN1 (Bit 26)                                        */
#define GPIO_PINCFG1_FIEN1_Msk            (0x4000000UL)             /*!< FIEN1 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG1_NCEPOL1_Pos          (22UL)                    /*!< NCEPOL1 (Bit 22)                                      */
#define GPIO_PINCFG1_NCEPOL1_Msk          (0x400000UL)              /*!< NCEPOL1 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG1_NCESRC1_Pos          (16UL)                    /*!< NCESRC1 (Bit 16)                                      */
#define GPIO_PINCFG1_NCESRC1_Msk          (0x3f0000UL)              /*!< NCESRC1 (Bitfield-Mask: 0x3f)                         */
#define GPIO_PINCFG1_PULLCFG1_Pos         (13UL)                    /*!< PULLCFG1 (Bit 13)                                     */
#define GPIO_PINCFG1_PULLCFG1_Msk         (0xe000UL)                /*!< PULLCFG1 (Bitfield-Mask: 0x07)                        */
#define GPIO_PINCFG1_SR1_Pos              (12UL)                    /*!< SR1 (Bit 12)                                          */
#define GPIO_PINCFG1_SR1_Msk              (0x1000UL)                /*!< SR1 (Bitfield-Mask: 0x01)                             */
#define GPIO_PINCFG1_DS1_Pos              (10UL)                    /*!< DS1 (Bit 10)                                          */
#define GPIO_PINCFG1_DS1_Msk              (0xc00UL)                 /*!< DS1 (Bitfield-Mask: 0x03)                             */
#define GPIO_PINCFG1_OUTCFG1_Pos          (8UL)                     /*!< OUTCFG1 (Bit 8)                                       */
#define GPIO_PINCFG1_OUTCFG1_Msk          (0x300UL)                 /*!< OUTCFG1 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG1_IRPTEN1_Pos          (6UL)                     /*!< IRPTEN1 (Bit 6)                                       */
#define GPIO_PINCFG1_IRPTEN1_Msk          (0xc0UL)                  /*!< IRPTEN1 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG1_RDZERO1_Pos          (5UL)                     /*!< RDZERO1 (Bit 5)                                       */
#define GPIO_PINCFG1_RDZERO1_Msk          (0x20UL)                  /*!< RDZERO1 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG1_INPEN1_Pos           (4UL)                     /*!< INPEN1 (Bit 4)                                        */
#define GPIO_PINCFG1_INPEN1_Msk           (0x10UL)                  /*!< INPEN1 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG1_FNCSEL1_Pos          (0UL)                     /*!< FNCSEL1 (Bit 0)                                       */
#define GPIO_PINCFG1_FNCSEL1_Msk          (0xfUL)                   /*!< FNCSEL1 (Bitfield-Mask: 0x0f)                         */
/* ========================================================  PINCFG2  ======================================================== */
#define GPIO_PINCFG2_FOEN2_Pos            (27UL)                    /*!< FOEN2 (Bit 27)                                        */
#define GPIO_PINCFG2_FOEN2_Msk            (0x8000000UL)             /*!< FOEN2 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG2_FIEN2_Pos            (26UL)                    /*!< FIEN2 (Bit 26)                                        */
#define GPIO_PINCFG2_FIEN2_Msk            (0x4000000UL)             /*!< FIEN2 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG2_NCEPOL2_Pos          (22UL)                    /*!< NCEPOL2 (Bit 22)                                      */
#define GPIO_PINCFG2_NCEPOL2_Msk          (0x400000UL)              /*!< NCEPOL2 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG2_NCESRC2_Pos          (16UL)                    /*!< NCESRC2 (Bit 16)                                      */
#define GPIO_PINCFG2_NCESRC2_Msk          (0x3f0000UL)              /*!< NCESRC2 (Bitfield-Mask: 0x3f)                         */
#define GPIO_PINCFG2_PULLCFG2_Pos         (13UL)                    /*!< PULLCFG2 (Bit 13)                                     */
#define GPIO_PINCFG2_PULLCFG2_Msk         (0xe000UL)                /*!< PULLCFG2 (Bitfield-Mask: 0x07)                        */
#define GPIO_PINCFG2_SR2_Pos              (12UL)                    /*!< SR2 (Bit 12)                                          */
#define GPIO_PINCFG2_SR2_Msk              (0x1000UL)                /*!< SR2 (Bitfield-Mask: 0x01)                             */
#define GPIO_PINCFG2_DS2_Pos              (10UL)                    /*!< DS2 (Bit 10)                                          */
#define GPIO_PINCFG2_DS2_Msk              (0xc00UL)                 /*!< DS2 (Bitfield-Mask: 0x03)                             */
#define GPIO_PINCFG2_OUTCFG2_Pos          (8UL)                     /*!< OUTCFG2 (Bit 8)                                       */
#define GPIO_PINCFG2_OUTCFG2_Msk          (0x300UL)                 /*!< OUTCFG2 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG2_IRPTEN2_Pos          (6UL)                     /*!< IRPTEN2 (Bit 6)                                       */
#define GPIO_PINCFG2_IRPTEN2_Msk          (0xc0UL)                  /*!< IRPTEN2 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG2_RDZERO2_Pos          (5UL)                     /*!< RDZERO2 (Bit 5)                                       */
#define GPIO_PINCFG2_RDZERO2_Msk          (0x20UL)                  /*!< RDZERO2 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG2_INPEN2_Pos           (4UL)                     /*!< INPEN2 (Bit 4)                                        */
#define GPIO_PINCFG2_INPEN2_Msk           (0x10UL)                  /*!< INPEN2 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG2_FNCSEL2_Pos          (0UL)                     /*!< FNCSEL2 (Bit 0)                                       */
#define GPIO_PINCFG2_FNCSEL2_Msk          (0xfUL)                   /*!< FNCSEL2 (Bitfield-Mask: 0x0f)                         */
/* ========================================================  PINCFG3  ======================================================== */
#define GPIO_PINCFG3_FOEN3_Pos            (27UL)                    /*!< FOEN3 (Bit 27)                                        */
#define GPIO_PINCFG3_FOEN3_Msk            (0x8000000UL)             /*!< FOEN3 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG3_FIEN3_Pos            (26UL)                    /*!< FIEN3 (Bit 26)                                        */
#define GPIO_PINCFG3_FIEN3_Msk            (0x4000000UL)             /*!< FIEN3 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG3_NCEPOL3_Pos          (22UL)                    /*!< NCEPOL3 (Bit 22)                                      */
#define GPIO_PINCFG3_NCEPOL3_Msk          (0x400000UL)              /*!< NCEPOL3 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG3_NCESRC3_Pos          (16UL)                    /*!< NCESRC3 (Bit 16)                                      */
#define GPIO_PINCFG3_NCESRC3_Msk          (0x3f0000UL)              /*!< NCESRC3 (Bitfield-Mask: 0x3f)                         */
#define GPIO_PINCFG3_PULLCFG3_Pos         (13UL)                    /*!< PULLCFG3 (Bit 13)                                     */
#define GPIO_PINCFG3_PULLCFG3_Msk         (0xe000UL)                /*!< PULLCFG3 (Bitfield-Mask: 0x07)                        */
#define GPIO_PINCFG3_SR3_Pos              (12UL)                    /*!< SR3 (Bit 12)                                          */
#define GPIO_PINCFG3_SR3_Msk              (0x1000UL)                /*!< SR3 (Bitfield-Mask: 0x01)                             */
#define GPIO_PINCFG3_DS3_Pos              (10UL)                    /*!< DS3 (Bit 10)                                          */
#define GPIO_PINCFG3_DS3_Msk              (0xc00UL)                 /*!< DS3 (Bitfield-Mask: 0x03)                             */
#define GPIO_PINCFG3_OUTCFG3_Pos          (8UL)                     /*!< OUTCFG3 (Bit 8)                                       */
#define GPIO_PINCFG3_OUTCFG3_Msk          (0x300UL)                 /*!< OUTCFG3 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG3_IRPTEN3_Pos          (6UL)                     /*!< IRPTEN3 (Bit 6)                                       */
#define GPIO_PINCFG3_IRPTEN3_Msk          (0xc0UL)                  /*!< IRPTEN3 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG3_RDZERO3_Pos          (5UL)                     /*!< RDZERO3 (Bit 5)                                       */
#define GPIO_PINCFG3_RDZERO3_Msk          (0x20UL)                  /*!< RDZERO3 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG3_INPEN3_Pos           (4UL)                     /*!< INPEN3 (Bit 4)                                        */
#define GPIO_PINCFG3_INPEN3_Msk           (0x10UL)                  /*!< INPEN3 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG3_FNCSEL3_Pos          (0UL)                     /*!< FNCSEL3 (Bit 0)                                       */
#define GPIO_PINCFG3_FNCSEL3_Msk          (0xfUL)                   /*!< FNCSEL3 (Bitfield-Mask: 0x0f)                         */
/* ========================================================  PINCFG4  ======================================================== */
#define GPIO_PINCFG4_FOEN4_Pos            (27UL)                    /*!< FOEN4 (Bit 27)                                        */
#define GPIO_PINCFG4_FOEN4_Msk            (0x8000000UL)             /*!< FOEN4 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG4_FIEN4_Pos            (26UL)                    /*!< FIEN4 (Bit 26)                                        */
#define GPIO_PINCFG4_FIEN4_Msk            (0x4000000UL)             /*!< FIEN4 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG4_NCEPOL4_Pos          (22UL)                    /*!< NCEPOL4 (Bit 22)                                      */
#define GPIO_PINCFG4_NCEPOL4_Msk          (0x400000UL)              /*!< NCEPOL4 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG4_NCESRC4_Pos          (16UL)                    /*!< NCESRC4 (Bit 16)                                      */
#define GPIO_PINCFG4_NCESRC4_Msk          (0x3f0000UL)              /*!< NCESRC4 (Bitfield-Mask: 0x3f)                         */
#define GPIO_PINCFG4_PULLCFG4_Pos         (13UL)                    /*!< PULLCFG4 (Bit 13)                                     */
#define GPIO_PINCFG4_PULLCFG4_Msk         (0xe000UL)                /*!< PULLCFG4 (Bitfield-Mask: 0x07)                        */
#define GPIO_PINCFG4_SR4_Pos              (12UL)                    /*!< SR4 (Bit 12)                                          */
#define GPIO_PINCFG4_SR4_Msk              (0x1000UL)                /*!< SR4 (Bitfield-Mask: 0x01)                             */
#define GPIO_PINCFG4_DS4_Pos              (10UL)                    /*!< DS4 (Bit 10)                                          */
#define GPIO_PINCFG4_DS4_Msk              (0xc00UL)                 /*!< DS4 (Bitfield-Mask: 0x03)                             */
#define GPIO_PINCFG4_OUTCFG4_Pos          (8UL)                     /*!< OUTCFG4 (Bit 8)                                       */
#define GPIO_PINCFG4_OUTCFG4_Msk          (0x300UL)                 /*!< OUTCFG4 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG4_IRPTEN4_Pos          (6UL)                     /*!< IRPTEN4 (Bit 6)                                       */
#define GPIO_PINCFG4_IRPTEN4_Msk          (0xc0UL)                  /*!< IRPTEN4 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG4_RDZERO4_Pos          (5UL)                     /*!< RDZERO4 (Bit 5)                                       */
#define GPIO_PINCFG4_RDZERO4_Msk          (0x20UL)                  /*!< RDZERO4 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG4_INPEN4_Pos           (4UL)                     /*!< INPEN4 (Bit 4)                                        */
#define GPIO_PINCFG4_INPEN4_Msk           (0x10UL)                  /*!< INPEN4 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG4_FNCSEL4_Pos          (0UL)                     /*!< FNCSEL4 (Bit 0)                                       */
#define GPIO_PINCFG4_FNCSEL4_Msk          (0xfUL)                   /*!< FNCSEL4 (Bitfield-Mask: 0x0f)                         */
/* ========================================================  PINCFG5  ======================================================== */
#define GPIO_PINCFG5_FOEN5_Pos            (27UL)                    /*!< FOEN5 (Bit 27)                                        */
#define GPIO_PINCFG5_FOEN5_Msk            (0x8000000UL)             /*!< FOEN5 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG5_FIEN5_Pos            (26UL)                    /*!< FIEN5 (Bit 26)                                        */
#define GPIO_PINCFG5_FIEN5_Msk            (0x4000000UL)             /*!< FIEN5 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG5_NCEPOL5_Pos          (22UL)                    /*!< NCEPOL5 (Bit 22)                                      */
#define GPIO_PINCFG5_NCEPOL5_Msk          (0x400000UL)              /*!< NCEPOL5 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG5_NCESRC5_Pos          (16UL)                    /*!< NCESRC5 (Bit 16)                                      */
#define GPIO_PINCFG5_NCESRC5_Msk          (0x3f0000UL)              /*!< NCESRC5 (Bitfield-Mask: 0x3f)                         */
#define GPIO_PINCFG5_PULLCFG5_Pos         (13UL)                    /*!< PULLCFG5 (Bit 13)                                     */
#define GPIO_PINCFG5_PULLCFG5_Msk         (0xe000UL)                /*!< PULLCFG5 (Bitfield-Mask: 0x07)                        */
#define GPIO_PINCFG5_SR5_Pos              (12UL)                    /*!< SR5 (Bit 12)                                          */
#define GPIO_PINCFG5_SR5_Msk              (0x1000UL)                /*!< SR5 (Bitfield-Mask: 0x01)                             */
#define GPIO_PINCFG5_DS5_Pos              (10UL)                    /*!< DS5 (Bit 10)                                          */
#define GPIO_PINCFG5_DS5_Msk              (0xc00UL)                 /*!< DS5 (Bitfield-Mask: 0x03)                             */
#define GPIO_PINCFG5_OUTCFG5_Pos          (8UL)                     /*!< OUTCFG5 (Bit 8)                                       */
#define GPIO_PINCFG5_OUTCFG5_Msk          (0x300UL)                 /*!< OUTCFG5 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG5_IRPTEN5_Pos          (6UL)                     /*!< IRPTEN5 (Bit 6)                                       */
#define GPIO_PINCFG5_IRPTEN5_Msk          (0xc0UL)                  /*!< IRPTEN5 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG5_RDZERO5_Pos          (5UL)                     /*!< RDZERO5 (Bit 5)                                       */
#define GPIO_PINCFG5_RDZERO5_Msk          (0x20UL)                  /*!< RDZERO5 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG5_INPEN5_Pos           (4UL)                     /*!< INPEN5 (Bit 4)                                        */
#define GPIO_PINCFG5_INPEN5_Msk           (0x10UL)                  /*!< INPEN5 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG5_FNCSEL5_Pos          (0UL)                     /*!< FNCSEL5 (Bit 0)                                       */
#define GPIO_PINCFG5_FNCSEL5_Msk          (0xfUL)                   /*!< FNCSEL5 (Bitfield-Mask: 0x0f)                         */
/* ========================================================  PINCFG6  ======================================================== */
#define GPIO_PINCFG6_FOEN6_Pos            (27UL)                    /*!< FOEN6 (Bit 27)                                        */
#define GPIO_PINCFG6_FOEN6_Msk            (0x8000000UL)             /*!< FOEN6 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG6_FIEN6_Pos            (26UL)                    /*!< FIEN6 (Bit 26)                                        */
#define GPIO_PINCFG6_FIEN6_Msk            (0x4000000UL)             /*!< FIEN6 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG6_NCEPOL6_Pos          (22UL)                    /*!< NCEPOL6 (Bit 22)                                      */
#define GPIO_PINCFG6_NCEPOL6_Msk          (0x400000UL)              /*!< NCEPOL6 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG6_NCESRC6_Pos          (16UL)                    /*!< NCESRC6 (Bit 16)                                      */
#define GPIO_PINCFG6_NCESRC6_Msk          (0x3f0000UL)              /*!< NCESRC6 (Bitfield-Mask: 0x3f)                         */
#define GPIO_PINCFG6_PULLCFG6_Pos         (13UL)                    /*!< PULLCFG6 (Bit 13)                                     */
#define GPIO_PINCFG6_PULLCFG6_Msk         (0xe000UL)                /*!< PULLCFG6 (Bitfield-Mask: 0x07)                        */
#define GPIO_PINCFG6_SR6_Pos              (12UL)                    /*!< SR6 (Bit 12)                                          */
#define GPIO_PINCFG6_SR6_Msk              (0x1000UL)                /*!< SR6 (Bitfield-Mask: 0x01)                             */
#define GPIO_PINCFG6_DS6_Pos              (10UL)                    /*!< DS6 (Bit 10)                                          */
#define GPIO_PINCFG6_DS6_Msk              (0xc00UL)                 /*!< DS6 (Bitfield-Mask: 0x03)                             */
#define GPIO_PINCFG6_OUTCFG6_Pos          (8UL)                     /*!< OUTCFG6 (Bit 8)                                       */
#define GPIO_PINCFG6_OUTCFG6_Msk          (0x300UL)                 /*!< OUTCFG6 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG6_IRPTEN6_Pos          (6UL)                     /*!< IRPTEN6 (Bit 6)                                       */
#define GPIO_PINCFG6_IRPTEN6_Msk          (0xc0UL)                  /*!< IRPTEN6 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG6_RDZERO6_Pos          (5UL)                     /*!< RDZERO6 (Bit 5)                                       */
#define GPIO_PINCFG6_RDZERO6_Msk          (0x20UL)                  /*!< RDZERO6 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG6_INPEN6_Pos           (4UL)                     /*!< INPEN6 (Bit 4)                                        */
#define GPIO_PINCFG6_INPEN6_Msk           (0x10UL)                  /*!< INPEN6 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG6_FNCSEL6_Pos          (0UL)                     /*!< FNCSEL6 (Bit 0)                                       */
#define GPIO_PINCFG6_FNCSEL6_Msk          (0xfUL)                   /*!< FNCSEL6 (Bitfield-Mask: 0x0f)                         */
/* ========================================================  PINCFG7  ======================================================== */
#define GPIO_PINCFG7_FOEN7_Pos            (27UL)                    /*!< FOEN7 (Bit 27)                                        */
#define GPIO_PINCFG7_FOEN7_Msk            (0x8000000UL)             /*!< FOEN7 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG7_FIEN7_Pos            (26UL)                    /*!< FIEN7 (Bit 26)                                        */
#define GPIO_PINCFG7_FIEN7_Msk            (0x4000000UL)             /*!< FIEN7 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG7_NCEPOL7_Pos          (22UL)                    /*!< NCEPOL7 (Bit 22)                                      */
#define GPIO_PINCFG7_NCEPOL7_Msk          (0x400000UL)              /*!< NCEPOL7 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG7_NCESRC7_Pos          (16UL)                    /*!< NCESRC7 (Bit 16)                                      */
#define GPIO_PINCFG7_NCESRC7_Msk          (0x3f0000UL)              /*!< NCESRC7 (Bitfield-Mask: 0x3f)                         */
#define GPIO_PINCFG7_PULLCFG7_Pos         (13UL)                    /*!< PULLCFG7 (Bit 13)                                     */
#define GPIO_PINCFG7_PULLCFG7_Msk         (0xe000UL)                /*!< PULLCFG7 (Bitfield-Mask: 0x07)                        */
#define GPIO_PINCFG7_SR7_Pos              (12UL)                    /*!< SR7 (Bit 12)                                          */
#define GPIO_PINCFG7_SR7_Msk              (0x1000UL)                /*!< SR7 (Bitfield-Mask: 0x01)                             */
#define GPIO_PINCFG7_DS7_Pos              (10UL)                    /*!< DS7 (Bit 10)                                          */
#define GPIO_PINCFG7_DS7_Msk              (0xc00UL)                 /*!< DS7 (Bitfield-Mask: 0x03)                             */
#define GPIO_PINCFG7_OUTCFG7_Pos          (8UL)                     /*!< OUTCFG7 (Bit 8)                                       */
#define GPIO_PINCFG7_OUTCFG7_Msk          (0x300UL)                 /*!< OUTCFG7 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG7_IRPTEN7_Pos          (6UL)                     /*!< IRPTEN7 (Bit 6)                                       */
#define GPIO_PINCFG7_IRPTEN7_Msk          (0xc0UL)                  /*!< IRPTEN7 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG7_RDZERO7_Pos          (5UL)                     /*!< RDZERO7 (Bit 5)                                       */
#define GPIO_PINCFG7_RDZERO7_Msk          (0x20UL)                  /*!< RDZERO7 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG7_INPEN7_Pos           (4UL)                     /*!< INPEN7 (Bit 4)                                        */
#define GPIO_PINCFG7_INPEN7_Msk           (0x10UL)                  /*!< INPEN7 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG7_FNCSEL7_Pos          (0UL)                     /*!< FNCSEL7 (Bit 0)                                       */
#define GPIO_PINCFG7_FNCSEL7_Msk          (0xfUL)                   /*!< FNCSEL7 (Bitfield-Mask: 0x0f)                         */
/* ========================================================  PINCFG8  ======================================================== */
#define GPIO_PINCFG8_FOEN8_Pos            (27UL)                    /*!< FOEN8 (Bit 27)                                        */
#define GPIO_PINCFG8_FOEN8_Msk            (0x8000000UL)             /*!< FOEN8 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG8_FIEN8_Pos            (26UL)                    /*!< FIEN8 (Bit 26)                                        */
#define GPIO_PINCFG8_FIEN8_Msk            (0x4000000UL)             /*!< FIEN8 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG8_NCEPOL8_Pos          (22UL)                    /*!< NCEPOL8 (Bit 22)                                      */
#define GPIO_PINCFG8_NCEPOL8_Msk          (0x400000UL)              /*!< NCEPOL8 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG8_NCESRC8_Pos          (16UL)                    /*!< NCESRC8 (Bit 16)                                      */
#define GPIO_PINCFG8_NCESRC8_Msk          (0x3f0000UL)              /*!< NCESRC8 (Bitfield-Mask: 0x3f)                         */
#define GPIO_PINCFG8_PULLCFG8_Pos         (13UL)                    /*!< PULLCFG8 (Bit 13)                                     */
#define GPIO_PINCFG8_PULLCFG8_Msk         (0xe000UL)                /*!< PULLCFG8 (Bitfield-Mask: 0x07)                        */
#define GPIO_PINCFG8_SR8_Pos              (12UL)                    /*!< SR8 (Bit 12)                                          */
#define GPIO_PINCFG8_SR8_Msk              (0x1000UL)                /*!< SR8 (Bitfield-Mask: 0x01)                             */
#define GPIO_PINCFG8_DS8_Pos              (10UL)                    /*!< DS8 (Bit 10)                                          */
#define GPIO_PINCFG8_DS8_Msk              (0xc00UL)                 /*!< DS8 (Bitfield-Mask: 0x03)                             */
#define GPIO_PINCFG8_OUTCFG8_Pos          (8UL)                     /*!< OUTCFG8 (Bit 8)                                       */
#define GPIO_PINCFG8_OUTCFG8_Msk          (0x300UL)                 /*!< OUTCFG8 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG8_IRPTEN8_Pos          (6UL)                     /*!< IRPTEN8 (Bit 6)                                       */
#define GPIO_PINCFG8_IRPTEN8_Msk          (0xc0UL)                  /*!< IRPTEN8 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG8_RDZERO8_Pos          (5UL)                     /*!< RDZERO8 (Bit 5)                                       */
#define GPIO_PINCFG8_RDZERO8_Msk          (0x20UL)                  /*!< RDZERO8 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG8_INPEN8_Pos           (4UL)                     /*!< INPEN8 (Bit 4)                                        */
#define GPIO_PINCFG8_INPEN8_Msk           (0x10UL)                  /*!< INPEN8 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG8_FNCSEL8_Pos          (0UL)                     /*!< FNCSEL8 (Bit 0)                                       */
#define GPIO_PINCFG8_FNCSEL8_Msk          (0xfUL)                   /*!< FNCSEL8 (Bitfield-Mask: 0x0f)                         */
/* ========================================================  PINCFG9  ======================================================== */
#define GPIO_PINCFG9_FOEN9_Pos            (27UL)                    /*!< FOEN9 (Bit 27)                                        */
#define GPIO_PINCFG9_FOEN9_Msk            (0x8000000UL)             /*!< FOEN9 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG9_FIEN9_Pos            (26UL)                    /*!< FIEN9 (Bit 26)                                        */
#define GPIO_PINCFG9_FIEN9_Msk            (0x4000000UL)             /*!< FIEN9 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG9_NCEPOL9_Pos          (22UL)                    /*!< NCEPOL9 (Bit 22)                                      */
#define GPIO_PINCFG9_NCEPOL9_Msk          (0x400000UL)              /*!< NCEPOL9 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG9_NCESRC9_Pos          (16UL)                    /*!< NCESRC9 (Bit 16)                                      */
#define GPIO_PINCFG9_NCESRC9_Msk          (0x3f0000UL)              /*!< NCESRC9 (Bitfield-Mask: 0x3f)                         */
#define GPIO_PINCFG9_PULLCFG9_Pos         (13UL)                    /*!< PULLCFG9 (Bit 13)                                     */
#define GPIO_PINCFG9_PULLCFG9_Msk         (0xe000UL)                /*!< PULLCFG9 (Bitfield-Mask: 0x07)                        */
#define GPIO_PINCFG9_SR9_Pos              (12UL)                    /*!< SR9 (Bit 12)                                          */
#define GPIO_PINCFG9_SR9_Msk              (0x1000UL)                /*!< SR9 (Bitfield-Mask: 0x01)                             */
#define GPIO_PINCFG9_DS9_Pos              (10UL)                    /*!< DS9 (Bit 10)                                          */
#define GPIO_PINCFG9_DS9_Msk              (0xc00UL)                 /*!< DS9 (Bitfield-Mask: 0x03)                             */
#define GPIO_PINCFG9_OUTCFG9_Pos          (8UL)                     /*!< OUTCFG9 (Bit 8)                                       */
#define GPIO_PINCFG9_OUTCFG9_Msk          (0x300UL)                 /*!< OUTCFG9 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG9_IRPTEN9_Pos          (6UL)                     /*!< IRPTEN9 (Bit 6)                                       */
#define GPIO_PINCFG9_IRPTEN9_Msk          (0xc0UL)                  /*!< IRPTEN9 (Bitfield-Mask: 0x03)                         */
#define GPIO_PINCFG9_RDZERO9_Pos          (5UL)                     /*!< RDZERO9 (Bit 5)                                       */
#define GPIO_PINCFG9_RDZERO9_Msk          (0x20UL)                  /*!< RDZERO9 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG9_INPEN9_Pos           (4UL)                     /*!< INPEN9 (Bit 4)                                        */
#define GPIO_PINCFG9_INPEN9_Msk           (0x10UL)                  /*!< INPEN9 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG9_FNCSEL9_Pos          (0UL)                     /*!< FNCSEL9 (Bit 0)                                       */
#define GPIO_PINCFG9_FNCSEL9_Msk          (0xfUL)                   /*!< FNCSEL9 (Bitfield-Mask: 0x0f)                         */
/* =======================================================  PINCFG10  ======================================================== */
#define GPIO_PINCFG10_FOEN10_Pos          (27UL)                    /*!< FOEN10 (Bit 27)                                       */
#define GPIO_PINCFG10_FOEN10_Msk          (0x8000000UL)             /*!< FOEN10 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG10_FIEN10_Pos          (26UL)                    /*!< FIEN10 (Bit 26)                                       */
#define GPIO_PINCFG10_FIEN10_Msk          (0x4000000UL)             /*!< FIEN10 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG10_NCEPOL10_Pos        (22UL)                    /*!< NCEPOL10 (Bit 22)                                     */
#define GPIO_PINCFG10_NCEPOL10_Msk        (0x400000UL)              /*!< NCEPOL10 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG10_NCESRC10_Pos        (16UL)                    /*!< NCESRC10 (Bit 16)                                     */
#define GPIO_PINCFG10_NCESRC10_Msk        (0x3f0000UL)              /*!< NCESRC10 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG10_PULLCFG10_Pos       (13UL)                    /*!< PULLCFG10 (Bit 13)                                    */
#define GPIO_PINCFG10_PULLCFG10_Msk       (0xe000UL)                /*!< PULLCFG10 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG10_SR10_Pos            (12UL)                    /*!< SR10 (Bit 12)                                         */
#define GPIO_PINCFG10_SR10_Msk            (0x1000UL)                /*!< SR10 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG10_DS10_Pos            (10UL)                    /*!< DS10 (Bit 10)                                         */
#define GPIO_PINCFG10_DS10_Msk            (0xc00UL)                 /*!< DS10 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG10_OUTCFG10_Pos        (8UL)                     /*!< OUTCFG10 (Bit 8)                                      */
#define GPIO_PINCFG10_OUTCFG10_Msk        (0x300UL)                 /*!< OUTCFG10 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG10_IRPTEN10_Pos        (6UL)                     /*!< IRPTEN10 (Bit 6)                                      */
#define GPIO_PINCFG10_IRPTEN10_Msk        (0xc0UL)                  /*!< IRPTEN10 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG10_RDZERO10_Pos        (5UL)                     /*!< RDZERO10 (Bit 5)                                      */
#define GPIO_PINCFG10_RDZERO10_Msk        (0x20UL)                  /*!< RDZERO10 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG10_INPEN10_Pos         (4UL)                     /*!< INPEN10 (Bit 4)                                       */
#define GPIO_PINCFG10_INPEN10_Msk         (0x10UL)                  /*!< INPEN10 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG10_FNCSEL10_Pos        (0UL)                     /*!< FNCSEL10 (Bit 0)                                      */
#define GPIO_PINCFG10_FNCSEL10_Msk        (0xfUL)                   /*!< FNCSEL10 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG11  ======================================================== */
#define GPIO_PINCFG11_FOEN11_Pos          (27UL)                    /*!< FOEN11 (Bit 27)                                       */
#define GPIO_PINCFG11_FOEN11_Msk          (0x8000000UL)             /*!< FOEN11 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG11_FIEN11_Pos          (26UL)                    /*!< FIEN11 (Bit 26)                                       */
#define GPIO_PINCFG11_FIEN11_Msk          (0x4000000UL)             /*!< FIEN11 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG11_NCEPOL11_Pos        (22UL)                    /*!< NCEPOL11 (Bit 22)                                     */
#define GPIO_PINCFG11_NCEPOL11_Msk        (0x400000UL)              /*!< NCEPOL11 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG11_NCESRC11_Pos        (16UL)                    /*!< NCESRC11 (Bit 16)                                     */
#define GPIO_PINCFG11_NCESRC11_Msk        (0x3f0000UL)              /*!< NCESRC11 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG11_PULLCFG11_Pos       (13UL)                    /*!< PULLCFG11 (Bit 13)                                    */
#define GPIO_PINCFG11_PULLCFG11_Msk       (0xe000UL)                /*!< PULLCFG11 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG11_SR11_Pos            (12UL)                    /*!< SR11 (Bit 12)                                         */
#define GPIO_PINCFG11_SR11_Msk            (0x1000UL)                /*!< SR11 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG11_DS11_Pos            (10UL)                    /*!< DS11 (Bit 10)                                         */
#define GPIO_PINCFG11_DS11_Msk            (0xc00UL)                 /*!< DS11 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG11_OUTCFG11_Pos        (8UL)                     /*!< OUTCFG11 (Bit 8)                                      */
#define GPIO_PINCFG11_OUTCFG11_Msk        (0x300UL)                 /*!< OUTCFG11 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG11_IRPTEN11_Pos        (6UL)                     /*!< IRPTEN11 (Bit 6)                                      */
#define GPIO_PINCFG11_IRPTEN11_Msk        (0xc0UL)                  /*!< IRPTEN11 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG11_RDZERO11_Pos        (5UL)                     /*!< RDZERO11 (Bit 5)                                      */
#define GPIO_PINCFG11_RDZERO11_Msk        (0x20UL)                  /*!< RDZERO11 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG11_INPEN11_Pos         (4UL)                     /*!< INPEN11 (Bit 4)                                       */
#define GPIO_PINCFG11_INPEN11_Msk         (0x10UL)                  /*!< INPEN11 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG11_FNCSEL11_Pos        (0UL)                     /*!< FNCSEL11 (Bit 0)                                      */
#define GPIO_PINCFG11_FNCSEL11_Msk        (0xfUL)                   /*!< FNCSEL11 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG12  ======================================================== */
#define GPIO_PINCFG12_FOEN12_Pos          (27UL)                    /*!< FOEN12 (Bit 27)                                       */
#define GPIO_PINCFG12_FOEN12_Msk          (0x8000000UL)             /*!< FOEN12 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG12_FIEN12_Pos          (26UL)                    /*!< FIEN12 (Bit 26)                                       */
#define GPIO_PINCFG12_FIEN12_Msk          (0x4000000UL)             /*!< FIEN12 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG12_NCEPOL12_Pos        (22UL)                    /*!< NCEPOL12 (Bit 22)                                     */
#define GPIO_PINCFG12_NCEPOL12_Msk        (0x400000UL)              /*!< NCEPOL12 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG12_NCESRC12_Pos        (16UL)                    /*!< NCESRC12 (Bit 16)                                     */
#define GPIO_PINCFG12_NCESRC12_Msk        (0x3f0000UL)              /*!< NCESRC12 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG12_PULLCFG12_Pos       (13UL)                    /*!< PULLCFG12 (Bit 13)                                    */
#define GPIO_PINCFG12_PULLCFG12_Msk       (0xe000UL)                /*!< PULLCFG12 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG12_SR12_Pos            (12UL)                    /*!< SR12 (Bit 12)                                         */
#define GPIO_PINCFG12_SR12_Msk            (0x1000UL)                /*!< SR12 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG12_DS12_Pos            (10UL)                    /*!< DS12 (Bit 10)                                         */
#define GPIO_PINCFG12_DS12_Msk            (0xc00UL)                 /*!< DS12 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG12_OUTCFG12_Pos        (8UL)                     /*!< OUTCFG12 (Bit 8)                                      */
#define GPIO_PINCFG12_OUTCFG12_Msk        (0x300UL)                 /*!< OUTCFG12 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG12_IRPTEN12_Pos        (6UL)                     /*!< IRPTEN12 (Bit 6)                                      */
#define GPIO_PINCFG12_IRPTEN12_Msk        (0xc0UL)                  /*!< IRPTEN12 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG12_RDZERO12_Pos        (5UL)                     /*!< RDZERO12 (Bit 5)                                      */
#define GPIO_PINCFG12_RDZERO12_Msk        (0x20UL)                  /*!< RDZERO12 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG12_INPEN12_Pos         (4UL)                     /*!< INPEN12 (Bit 4)                                       */
#define GPIO_PINCFG12_INPEN12_Msk         (0x10UL)                  /*!< INPEN12 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG12_FNCSEL12_Pos        (0UL)                     /*!< FNCSEL12 (Bit 0)                                      */
#define GPIO_PINCFG12_FNCSEL12_Msk        (0xfUL)                   /*!< FNCSEL12 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG13  ======================================================== */
#define GPIO_PINCFG13_FOEN13_Pos          (27UL)                    /*!< FOEN13 (Bit 27)                                       */
#define GPIO_PINCFG13_FOEN13_Msk          (0x8000000UL)             /*!< FOEN13 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG13_FIEN13_Pos          (26UL)                    /*!< FIEN13 (Bit 26)                                       */
#define GPIO_PINCFG13_FIEN13_Msk          (0x4000000UL)             /*!< FIEN13 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG13_NCEPOL13_Pos        (22UL)                    /*!< NCEPOL13 (Bit 22)                                     */
#define GPIO_PINCFG13_NCEPOL13_Msk        (0x400000UL)              /*!< NCEPOL13 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG13_NCESRC13_Pos        (16UL)                    /*!< NCESRC13 (Bit 16)                                     */
#define GPIO_PINCFG13_NCESRC13_Msk        (0x3f0000UL)              /*!< NCESRC13 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG13_PULLCFG13_Pos       (13UL)                    /*!< PULLCFG13 (Bit 13)                                    */
#define GPIO_PINCFG13_PULLCFG13_Msk       (0xe000UL)                /*!< PULLCFG13 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG13_SR13_Pos            (12UL)                    /*!< SR13 (Bit 12)                                         */
#define GPIO_PINCFG13_SR13_Msk            (0x1000UL)                /*!< SR13 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG13_DS13_Pos            (10UL)                    /*!< DS13 (Bit 10)                                         */
#define GPIO_PINCFG13_DS13_Msk            (0xc00UL)                 /*!< DS13 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG13_OUTCFG13_Pos        (8UL)                     /*!< OUTCFG13 (Bit 8)                                      */
#define GPIO_PINCFG13_OUTCFG13_Msk        (0x300UL)                 /*!< OUTCFG13 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG13_IRPTEN13_Pos        (6UL)                     /*!< IRPTEN13 (Bit 6)                                      */
#define GPIO_PINCFG13_IRPTEN13_Msk        (0xc0UL)                  /*!< IRPTEN13 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG13_RDZERO13_Pos        (5UL)                     /*!< RDZERO13 (Bit 5)                                      */
#define GPIO_PINCFG13_RDZERO13_Msk        (0x20UL)                  /*!< RDZERO13 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG13_INPEN13_Pos         (4UL)                     /*!< INPEN13 (Bit 4)                                       */
#define GPIO_PINCFG13_INPEN13_Msk         (0x10UL)                  /*!< INPEN13 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG13_FNCSEL13_Pos        (0UL)                     /*!< FNCSEL13 (Bit 0)                                      */
#define GPIO_PINCFG13_FNCSEL13_Msk        (0xfUL)                   /*!< FNCSEL13 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG14  ======================================================== */
#define GPIO_PINCFG14_FOEN14_Pos          (27UL)                    /*!< FOEN14 (Bit 27)                                       */
#define GPIO_PINCFG14_FOEN14_Msk          (0x8000000UL)             /*!< FOEN14 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG14_FIEN14_Pos          (26UL)                    /*!< FIEN14 (Bit 26)                                       */
#define GPIO_PINCFG14_FIEN14_Msk          (0x4000000UL)             /*!< FIEN14 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG14_NCEPOL14_Pos        (22UL)                    /*!< NCEPOL14 (Bit 22)                                     */
#define GPIO_PINCFG14_NCEPOL14_Msk        (0x400000UL)              /*!< NCEPOL14 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG14_NCESRC14_Pos        (16UL)                    /*!< NCESRC14 (Bit 16)                                     */
#define GPIO_PINCFG14_NCESRC14_Msk        (0x3f0000UL)              /*!< NCESRC14 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG14_PULLCFG14_Pos       (13UL)                    /*!< PULLCFG14 (Bit 13)                                    */
#define GPIO_PINCFG14_PULLCFG14_Msk       (0xe000UL)                /*!< PULLCFG14 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG14_SR14_Pos            (12UL)                    /*!< SR14 (Bit 12)                                         */
#define GPIO_PINCFG14_SR14_Msk            (0x1000UL)                /*!< SR14 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG14_DS14_Pos            (10UL)                    /*!< DS14 (Bit 10)                                         */
#define GPIO_PINCFG14_DS14_Msk            (0xc00UL)                 /*!< DS14 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG14_OUTCFG14_Pos        (8UL)                     /*!< OUTCFG14 (Bit 8)                                      */
#define GPIO_PINCFG14_OUTCFG14_Msk        (0x300UL)                 /*!< OUTCFG14 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG14_IRPTEN14_Pos        (6UL)                     /*!< IRPTEN14 (Bit 6)                                      */
#define GPIO_PINCFG14_IRPTEN14_Msk        (0xc0UL)                  /*!< IRPTEN14 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG14_RDZERO14_Pos        (5UL)                     /*!< RDZERO14 (Bit 5)                                      */
#define GPIO_PINCFG14_RDZERO14_Msk        (0x20UL)                  /*!< RDZERO14 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG14_INPEN14_Pos         (4UL)                     /*!< INPEN14 (Bit 4)                                       */
#define GPIO_PINCFG14_INPEN14_Msk         (0x10UL)                  /*!< INPEN14 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG14_FNCSEL14_Pos        (0UL)                     /*!< FNCSEL14 (Bit 0)                                      */
#define GPIO_PINCFG14_FNCSEL14_Msk        (0xfUL)                   /*!< FNCSEL14 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG15  ======================================================== */
#define GPIO_PINCFG15_FOEN15_Pos          (27UL)                    /*!< FOEN15 (Bit 27)                                       */
#define GPIO_PINCFG15_FOEN15_Msk          (0x8000000UL)             /*!< FOEN15 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG15_FIEN15_Pos          (26UL)                    /*!< FIEN15 (Bit 26)                                       */
#define GPIO_PINCFG15_FIEN15_Msk          (0x4000000UL)             /*!< FIEN15 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG15_NCEPOL15_Pos        (22UL)                    /*!< NCEPOL15 (Bit 22)                                     */
#define GPIO_PINCFG15_NCEPOL15_Msk        (0x400000UL)              /*!< NCEPOL15 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG15_NCESRC15_Pos        (16UL)                    /*!< NCESRC15 (Bit 16)                                     */
#define GPIO_PINCFG15_NCESRC15_Msk        (0x3f0000UL)              /*!< NCESRC15 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG15_PULLCFG15_Pos       (13UL)                    /*!< PULLCFG15 (Bit 13)                                    */
#define GPIO_PINCFG15_PULLCFG15_Msk       (0xe000UL)                /*!< PULLCFG15 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG15_SR15_Pos            (12UL)                    /*!< SR15 (Bit 12)                                         */
#define GPIO_PINCFG15_SR15_Msk            (0x1000UL)                /*!< SR15 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG15_DS15_Pos            (10UL)                    /*!< DS15 (Bit 10)                                         */
#define GPIO_PINCFG15_DS15_Msk            (0xc00UL)                 /*!< DS15 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG15_OUTCFG15_Pos        (8UL)                     /*!< OUTCFG15 (Bit 8)                                      */
#define GPIO_PINCFG15_OUTCFG15_Msk        (0x300UL)                 /*!< OUTCFG15 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG15_IRPTEN15_Pos        (6UL)                     /*!< IRPTEN15 (Bit 6)                                      */
#define GPIO_PINCFG15_IRPTEN15_Msk        (0xc0UL)                  /*!< IRPTEN15 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG15_RDZERO15_Pos        (5UL)                     /*!< RDZERO15 (Bit 5)                                      */
#define GPIO_PINCFG15_RDZERO15_Msk        (0x20UL)                  /*!< RDZERO15 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG15_INPEN15_Pos         (4UL)                     /*!< INPEN15 (Bit 4)                                       */
#define GPIO_PINCFG15_INPEN15_Msk         (0x10UL)                  /*!< INPEN15 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG15_FNCSEL15_Pos        (0UL)                     /*!< FNCSEL15 (Bit 0)                                      */
#define GPIO_PINCFG15_FNCSEL15_Msk        (0xfUL)                   /*!< FNCSEL15 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG16  ======================================================== */
#define GPIO_PINCFG16_FOEN16_Pos          (27UL)                    /*!< FOEN16 (Bit 27)                                       */
#define GPIO_PINCFG16_FOEN16_Msk          (0x8000000UL)             /*!< FOEN16 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG16_FIEN16_Pos          (26UL)                    /*!< FIEN16 (Bit 26)                                       */
#define GPIO_PINCFG16_FIEN16_Msk          (0x4000000UL)             /*!< FIEN16 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG16_NCEPOL16_Pos        (22UL)                    /*!< NCEPOL16 (Bit 22)                                     */
#define GPIO_PINCFG16_NCEPOL16_Msk        (0x400000UL)              /*!< NCEPOL16 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG16_NCESRC16_Pos        (16UL)                    /*!< NCESRC16 (Bit 16)                                     */
#define GPIO_PINCFG16_NCESRC16_Msk        (0x3f0000UL)              /*!< NCESRC16 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG16_PULLCFG16_Pos       (13UL)                    /*!< PULLCFG16 (Bit 13)                                    */
#define GPIO_PINCFG16_PULLCFG16_Msk       (0xe000UL)                /*!< PULLCFG16 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG16_SR16_Pos            (12UL)                    /*!< SR16 (Bit 12)                                         */
#define GPIO_PINCFG16_SR16_Msk            (0x1000UL)                /*!< SR16 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG16_DS16_Pos            (10UL)                    /*!< DS16 (Bit 10)                                         */
#define GPIO_PINCFG16_DS16_Msk            (0xc00UL)                 /*!< DS16 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG16_OUTCFG16_Pos        (8UL)                     /*!< OUTCFG16 (Bit 8)                                      */
#define GPIO_PINCFG16_OUTCFG16_Msk        (0x300UL)                 /*!< OUTCFG16 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG16_IRPTEN16_Pos        (6UL)                     /*!< IRPTEN16 (Bit 6)                                      */
#define GPIO_PINCFG16_IRPTEN16_Msk        (0xc0UL)                  /*!< IRPTEN16 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG16_RDZERO16_Pos        (5UL)                     /*!< RDZERO16 (Bit 5)                                      */
#define GPIO_PINCFG16_RDZERO16_Msk        (0x20UL)                  /*!< RDZERO16 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG16_INPEN16_Pos         (4UL)                     /*!< INPEN16 (Bit 4)                                       */
#define GPIO_PINCFG16_INPEN16_Msk         (0x10UL)                  /*!< INPEN16 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG16_FNCSEL16_Pos        (0UL)                     /*!< FNCSEL16 (Bit 0)                                      */
#define GPIO_PINCFG16_FNCSEL16_Msk        (0xfUL)                   /*!< FNCSEL16 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG17  ======================================================== */
#define GPIO_PINCFG17_FOEN17_Pos          (27UL)                    /*!< FOEN17 (Bit 27)                                       */
#define GPIO_PINCFG17_FOEN17_Msk          (0x8000000UL)             /*!< FOEN17 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG17_FIEN17_Pos          (26UL)                    /*!< FIEN17 (Bit 26)                                       */
#define GPIO_PINCFG17_FIEN17_Msk          (0x4000000UL)             /*!< FIEN17 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG17_NCEPOL17_Pos        (22UL)                    /*!< NCEPOL17 (Bit 22)                                     */
#define GPIO_PINCFG17_NCEPOL17_Msk        (0x400000UL)              /*!< NCEPOL17 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG17_NCESRC17_Pos        (16UL)                    /*!< NCESRC17 (Bit 16)                                     */
#define GPIO_PINCFG17_NCESRC17_Msk        (0x3f0000UL)              /*!< NCESRC17 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG17_PULLCFG17_Pos       (13UL)                    /*!< PULLCFG17 (Bit 13)                                    */
#define GPIO_PINCFG17_PULLCFG17_Msk       (0xe000UL)                /*!< PULLCFG17 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG17_SR17_Pos            (12UL)                    /*!< SR17 (Bit 12)                                         */
#define GPIO_PINCFG17_SR17_Msk            (0x1000UL)                /*!< SR17 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG17_DS17_Pos            (10UL)                    /*!< DS17 (Bit 10)                                         */
#define GPIO_PINCFG17_DS17_Msk            (0xc00UL)                 /*!< DS17 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG17_OUTCFG17_Pos        (8UL)                     /*!< OUTCFG17 (Bit 8)                                      */
#define GPIO_PINCFG17_OUTCFG17_Msk        (0x300UL)                 /*!< OUTCFG17 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG17_IRPTEN17_Pos        (6UL)                     /*!< IRPTEN17 (Bit 6)                                      */
#define GPIO_PINCFG17_IRPTEN17_Msk        (0xc0UL)                  /*!< IRPTEN17 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG17_RDZERO17_Pos        (5UL)                     /*!< RDZERO17 (Bit 5)                                      */
#define GPIO_PINCFG17_RDZERO17_Msk        (0x20UL)                  /*!< RDZERO17 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG17_INPEN17_Pos         (4UL)                     /*!< INPEN17 (Bit 4)                                       */
#define GPIO_PINCFG17_INPEN17_Msk         (0x10UL)                  /*!< INPEN17 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG17_FNCSEL17_Pos        (0UL)                     /*!< FNCSEL17 (Bit 0)                                      */
#define GPIO_PINCFG17_FNCSEL17_Msk        (0xfUL)                   /*!< FNCSEL17 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG18  ======================================================== */
#define GPIO_PINCFG18_FOEN18_Pos          (27UL)                    /*!< FOEN18 (Bit 27)                                       */
#define GPIO_PINCFG18_FOEN18_Msk          (0x8000000UL)             /*!< FOEN18 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG18_FIEN18_Pos          (26UL)                    /*!< FIEN18 (Bit 26)                                       */
#define GPIO_PINCFG18_FIEN18_Msk          (0x4000000UL)             /*!< FIEN18 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG18_NCEPOL18_Pos        (22UL)                    /*!< NCEPOL18 (Bit 22)                                     */
#define GPIO_PINCFG18_NCEPOL18_Msk        (0x400000UL)              /*!< NCEPOL18 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG18_NCESRC18_Pos        (16UL)                    /*!< NCESRC18 (Bit 16)                                     */
#define GPIO_PINCFG18_NCESRC18_Msk        (0x3f0000UL)              /*!< NCESRC18 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG18_PULLCFG18_Pos       (13UL)                    /*!< PULLCFG18 (Bit 13)                                    */
#define GPIO_PINCFG18_PULLCFG18_Msk       (0xe000UL)                /*!< PULLCFG18 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG18_SR18_Pos            (12UL)                    /*!< SR18 (Bit 12)                                         */
#define GPIO_PINCFG18_SR18_Msk            (0x1000UL)                /*!< SR18 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG18_DS18_Pos            (10UL)                    /*!< DS18 (Bit 10)                                         */
#define GPIO_PINCFG18_DS18_Msk            (0xc00UL)                 /*!< DS18 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG18_OUTCFG18_Pos        (8UL)                     /*!< OUTCFG18 (Bit 8)                                      */
#define GPIO_PINCFG18_OUTCFG18_Msk        (0x300UL)                 /*!< OUTCFG18 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG18_IRPTEN18_Pos        (6UL)                     /*!< IRPTEN18 (Bit 6)                                      */
#define GPIO_PINCFG18_IRPTEN18_Msk        (0xc0UL)                  /*!< IRPTEN18 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG18_RDZERO18_Pos        (5UL)                     /*!< RDZERO18 (Bit 5)                                      */
#define GPIO_PINCFG18_RDZERO18_Msk        (0x20UL)                  /*!< RDZERO18 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG18_INPEN18_Pos         (4UL)                     /*!< INPEN18 (Bit 4)                                       */
#define GPIO_PINCFG18_INPEN18_Msk         (0x10UL)                  /*!< INPEN18 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG18_FNCSEL18_Pos        (0UL)                     /*!< FNCSEL18 (Bit 0)                                      */
#define GPIO_PINCFG18_FNCSEL18_Msk        (0xfUL)                   /*!< FNCSEL18 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG19  ======================================================== */
#define GPIO_PINCFG19_FOEN19_Pos          (27UL)                    /*!< FOEN19 (Bit 27)                                       */
#define GPIO_PINCFG19_FOEN19_Msk          (0x8000000UL)             /*!< FOEN19 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG19_FIEN19_Pos          (26UL)                    /*!< FIEN19 (Bit 26)                                       */
#define GPIO_PINCFG19_FIEN19_Msk          (0x4000000UL)             /*!< FIEN19 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG19_NCEPOL19_Pos        (22UL)                    /*!< NCEPOL19 (Bit 22)                                     */
#define GPIO_PINCFG19_NCEPOL19_Msk        (0x400000UL)              /*!< NCEPOL19 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG19_NCESRC19_Pos        (16UL)                    /*!< NCESRC19 (Bit 16)                                     */
#define GPIO_PINCFG19_NCESRC19_Msk        (0x3f0000UL)              /*!< NCESRC19 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG19_PULLCFG19_Pos       (13UL)                    /*!< PULLCFG19 (Bit 13)                                    */
#define GPIO_PINCFG19_PULLCFG19_Msk       (0xe000UL)                /*!< PULLCFG19 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG19_SR19_Pos            (12UL)                    /*!< SR19 (Bit 12)                                         */
#define GPIO_PINCFG19_SR19_Msk            (0x1000UL)                /*!< SR19 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG19_DS19_Pos            (10UL)                    /*!< DS19 (Bit 10)                                         */
#define GPIO_PINCFG19_DS19_Msk            (0xc00UL)                 /*!< DS19 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG19_OUTCFG19_Pos        (8UL)                     /*!< OUTCFG19 (Bit 8)                                      */
#define GPIO_PINCFG19_OUTCFG19_Msk        (0x300UL)                 /*!< OUTCFG19 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG19_IRPTEN19_Pos        (6UL)                     /*!< IRPTEN19 (Bit 6)                                      */
#define GPIO_PINCFG19_IRPTEN19_Msk        (0xc0UL)                  /*!< IRPTEN19 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG19_RDZERO19_Pos        (5UL)                     /*!< RDZERO19 (Bit 5)                                      */
#define GPIO_PINCFG19_RDZERO19_Msk        (0x20UL)                  /*!< RDZERO19 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG19_INPEN19_Pos         (4UL)                     /*!< INPEN19 (Bit 4)                                       */
#define GPIO_PINCFG19_INPEN19_Msk         (0x10UL)                  /*!< INPEN19 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG19_FNCSEL19_Pos        (0UL)                     /*!< FNCSEL19 (Bit 0)                                      */
#define GPIO_PINCFG19_FNCSEL19_Msk        (0xfUL)                   /*!< FNCSEL19 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG20  ======================================================== */
#define GPIO_PINCFG20_FOEN20_Pos          (27UL)                    /*!< FOEN20 (Bit 27)                                       */
#define GPIO_PINCFG20_FOEN20_Msk          (0x8000000UL)             /*!< FOEN20 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG20_FIEN20_Pos          (26UL)                    /*!< FIEN20 (Bit 26)                                       */
#define GPIO_PINCFG20_FIEN20_Msk          (0x4000000UL)             /*!< FIEN20 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG20_NCEPOL20_Pos        (22UL)                    /*!< NCEPOL20 (Bit 22)                                     */
#define GPIO_PINCFG20_NCEPOL20_Msk        (0x400000UL)              /*!< NCEPOL20 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG20_NCESRC20_Pos        (16UL)                    /*!< NCESRC20 (Bit 16)                                     */
#define GPIO_PINCFG20_NCESRC20_Msk        (0x3f0000UL)              /*!< NCESRC20 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG20_PULLCFG20_Pos       (13UL)                    /*!< PULLCFG20 (Bit 13)                                    */
#define GPIO_PINCFG20_PULLCFG20_Msk       (0xe000UL)                /*!< PULLCFG20 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG20_SR20_Pos            (12UL)                    /*!< SR20 (Bit 12)                                         */
#define GPIO_PINCFG20_SR20_Msk            (0x1000UL)                /*!< SR20 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG20_DS20_Pos            (10UL)                    /*!< DS20 (Bit 10)                                         */
#define GPIO_PINCFG20_DS20_Msk            (0xc00UL)                 /*!< DS20 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG20_OUTCFG20_Pos        (8UL)                     /*!< OUTCFG20 (Bit 8)                                      */
#define GPIO_PINCFG20_OUTCFG20_Msk        (0x300UL)                 /*!< OUTCFG20 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG20_IRPTEN20_Pos        (6UL)                     /*!< IRPTEN20 (Bit 6)                                      */
#define GPIO_PINCFG20_IRPTEN20_Msk        (0xc0UL)                  /*!< IRPTEN20 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG20_RDZERO20_Pos        (5UL)                     /*!< RDZERO20 (Bit 5)                                      */
#define GPIO_PINCFG20_RDZERO20_Msk        (0x20UL)                  /*!< RDZERO20 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG20_INPEN20_Pos         (4UL)                     /*!< INPEN20 (Bit 4)                                       */
#define GPIO_PINCFG20_INPEN20_Msk         (0x10UL)                  /*!< INPEN20 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG20_FNCSEL20_Pos        (0UL)                     /*!< FNCSEL20 (Bit 0)                                      */
#define GPIO_PINCFG20_FNCSEL20_Msk        (0xfUL)                   /*!< FNCSEL20 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG21  ======================================================== */
#define GPIO_PINCFG21_FOEN21_Pos          (27UL)                    /*!< FOEN21 (Bit 27)                                       */
#define GPIO_PINCFG21_FOEN21_Msk          (0x8000000UL)             /*!< FOEN21 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG21_FIEN21_Pos          (26UL)                    /*!< FIEN21 (Bit 26)                                       */
#define GPIO_PINCFG21_FIEN21_Msk          (0x4000000UL)             /*!< FIEN21 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG21_NCEPOL21_Pos        (22UL)                    /*!< NCEPOL21 (Bit 22)                                     */
#define GPIO_PINCFG21_NCEPOL21_Msk        (0x400000UL)              /*!< NCEPOL21 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG21_NCESRC21_Pos        (16UL)                    /*!< NCESRC21 (Bit 16)                                     */
#define GPIO_PINCFG21_NCESRC21_Msk        (0x3f0000UL)              /*!< NCESRC21 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG21_PULLCFG21_Pos       (13UL)                    /*!< PULLCFG21 (Bit 13)                                    */
#define GPIO_PINCFG21_PULLCFG21_Msk       (0xe000UL)                /*!< PULLCFG21 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG21_SR21_Pos            (12UL)                    /*!< SR21 (Bit 12)                                         */
#define GPIO_PINCFG21_SR21_Msk            (0x1000UL)                /*!< SR21 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG21_DS21_Pos            (10UL)                    /*!< DS21 (Bit 10)                                         */
#define GPIO_PINCFG21_DS21_Msk            (0xc00UL)                 /*!< DS21 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG21_OUTCFG21_Pos        (8UL)                     /*!< OUTCFG21 (Bit 8)                                      */
#define GPIO_PINCFG21_OUTCFG21_Msk        (0x300UL)                 /*!< OUTCFG21 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG21_IRPTEN21_Pos        (6UL)                     /*!< IRPTEN21 (Bit 6)                                      */
#define GPIO_PINCFG21_IRPTEN21_Msk        (0xc0UL)                  /*!< IRPTEN21 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG21_RDZERO21_Pos        (5UL)                     /*!< RDZERO21 (Bit 5)                                      */
#define GPIO_PINCFG21_RDZERO21_Msk        (0x20UL)                  /*!< RDZERO21 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG21_INPEN21_Pos         (4UL)                     /*!< INPEN21 (Bit 4)                                       */
#define GPIO_PINCFG21_INPEN21_Msk         (0x10UL)                  /*!< INPEN21 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG21_FNCSEL21_Pos        (0UL)                     /*!< FNCSEL21 (Bit 0)                                      */
#define GPIO_PINCFG21_FNCSEL21_Msk        (0xfUL)                   /*!< FNCSEL21 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG22  ======================================================== */
#define GPIO_PINCFG22_FOEN22_Pos          (27UL)                    /*!< FOEN22 (Bit 27)                                       */
#define GPIO_PINCFG22_FOEN22_Msk          (0x8000000UL)             /*!< FOEN22 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG22_FIEN22_Pos          (26UL)                    /*!< FIEN22 (Bit 26)                                       */
#define GPIO_PINCFG22_FIEN22_Msk          (0x4000000UL)             /*!< FIEN22 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG22_NCEPOL22_Pos        (22UL)                    /*!< NCEPOL22 (Bit 22)                                     */
#define GPIO_PINCFG22_NCEPOL22_Msk        (0x400000UL)              /*!< NCEPOL22 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG22_NCESRC22_Pos        (16UL)                    /*!< NCESRC22 (Bit 16)                                     */
#define GPIO_PINCFG22_NCESRC22_Msk        (0x3f0000UL)              /*!< NCESRC22 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG22_PULLCFG22_Pos       (13UL)                    /*!< PULLCFG22 (Bit 13)                                    */
#define GPIO_PINCFG22_PULLCFG22_Msk       (0xe000UL)                /*!< PULLCFG22 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG22_SR22_Pos            (12UL)                    /*!< SR22 (Bit 12)                                         */
#define GPIO_PINCFG22_SR22_Msk            (0x1000UL)                /*!< SR22 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG22_DS22_Pos            (10UL)                    /*!< DS22 (Bit 10)                                         */
#define GPIO_PINCFG22_DS22_Msk            (0xc00UL)                 /*!< DS22 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG22_OUTCFG22_Pos        (8UL)                     /*!< OUTCFG22 (Bit 8)                                      */
#define GPIO_PINCFG22_OUTCFG22_Msk        (0x300UL)                 /*!< OUTCFG22 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG22_IRPTEN22_Pos        (6UL)                     /*!< IRPTEN22 (Bit 6)                                      */
#define GPIO_PINCFG22_IRPTEN22_Msk        (0xc0UL)                  /*!< IRPTEN22 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG22_RDZERO22_Pos        (5UL)                     /*!< RDZERO22 (Bit 5)                                      */
#define GPIO_PINCFG22_RDZERO22_Msk        (0x20UL)                  /*!< RDZERO22 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG22_INPEN22_Pos         (4UL)                     /*!< INPEN22 (Bit 4)                                       */
#define GPIO_PINCFG22_INPEN22_Msk         (0x10UL)                  /*!< INPEN22 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG22_FNCSEL22_Pos        (0UL)                     /*!< FNCSEL22 (Bit 0)                                      */
#define GPIO_PINCFG22_FNCSEL22_Msk        (0xfUL)                   /*!< FNCSEL22 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG23  ======================================================== */
#define GPIO_PINCFG23_FOEN23_Pos          (27UL)                    /*!< FOEN23 (Bit 27)                                       */
#define GPIO_PINCFG23_FOEN23_Msk          (0x8000000UL)             /*!< FOEN23 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG23_FIEN23_Pos          (26UL)                    /*!< FIEN23 (Bit 26)                                       */
#define GPIO_PINCFG23_FIEN23_Msk          (0x4000000UL)             /*!< FIEN23 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG23_NCEPOL23_Pos        (22UL)                    /*!< NCEPOL23 (Bit 22)                                     */
#define GPIO_PINCFG23_NCEPOL23_Msk        (0x400000UL)              /*!< NCEPOL23 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG23_NCESRC23_Pos        (16UL)                    /*!< NCESRC23 (Bit 16)                                     */
#define GPIO_PINCFG23_NCESRC23_Msk        (0x3f0000UL)              /*!< NCESRC23 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG23_PULLCFG23_Pos       (13UL)                    /*!< PULLCFG23 (Bit 13)                                    */
#define GPIO_PINCFG23_PULLCFG23_Msk       (0xe000UL)                /*!< PULLCFG23 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG23_SR23_Pos            (12UL)                    /*!< SR23 (Bit 12)                                         */
#define GPIO_PINCFG23_SR23_Msk            (0x1000UL)                /*!< SR23 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG23_DS23_Pos            (10UL)                    /*!< DS23 (Bit 10)                                         */
#define GPIO_PINCFG23_DS23_Msk            (0xc00UL)                 /*!< DS23 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG23_OUTCFG23_Pos        (8UL)                     /*!< OUTCFG23 (Bit 8)                                      */
#define GPIO_PINCFG23_OUTCFG23_Msk        (0x300UL)                 /*!< OUTCFG23 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG23_IRPTEN23_Pos        (6UL)                     /*!< IRPTEN23 (Bit 6)                                      */
#define GPIO_PINCFG23_IRPTEN23_Msk        (0xc0UL)                  /*!< IRPTEN23 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG23_RDZERO23_Pos        (5UL)                     /*!< RDZERO23 (Bit 5)                                      */
#define GPIO_PINCFG23_RDZERO23_Msk        (0x20UL)                  /*!< RDZERO23 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG23_INPEN23_Pos         (4UL)                     /*!< INPEN23 (Bit 4)                                       */
#define GPIO_PINCFG23_INPEN23_Msk         (0x10UL)                  /*!< INPEN23 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG23_FNCSEL23_Pos        (0UL)                     /*!< FNCSEL23 (Bit 0)                                      */
#define GPIO_PINCFG23_FNCSEL23_Msk        (0xfUL)                   /*!< FNCSEL23 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG24  ======================================================== */
#define GPIO_PINCFG24_FOEN24_Pos          (27UL)                    /*!< FOEN24 (Bit 27)                                       */
#define GPIO_PINCFG24_FOEN24_Msk          (0x8000000UL)             /*!< FOEN24 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG24_FIEN24_Pos          (26UL)                    /*!< FIEN24 (Bit 26)                                       */
#define GPIO_PINCFG24_FIEN24_Msk          (0x4000000UL)             /*!< FIEN24 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG24_NCEPOL24_Pos        (22UL)                    /*!< NCEPOL24 (Bit 22)                                     */
#define GPIO_PINCFG24_NCEPOL24_Msk        (0x400000UL)              /*!< NCEPOL24 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG24_NCESRC24_Pos        (16UL)                    /*!< NCESRC24 (Bit 16)                                     */
#define GPIO_PINCFG24_NCESRC24_Msk        (0x3f0000UL)              /*!< NCESRC24 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG24_PULLCFG24_Pos       (13UL)                    /*!< PULLCFG24 (Bit 13)                                    */
#define GPIO_PINCFG24_PULLCFG24_Msk       (0xe000UL)                /*!< PULLCFG24 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG24_SR24_Pos            (12UL)                    /*!< SR24 (Bit 12)                                         */
#define GPIO_PINCFG24_SR24_Msk            (0x1000UL)                /*!< SR24 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG24_DS24_Pos            (10UL)                    /*!< DS24 (Bit 10)                                         */
#define GPIO_PINCFG24_DS24_Msk            (0xc00UL)                 /*!< DS24 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG24_OUTCFG24_Pos        (8UL)                     /*!< OUTCFG24 (Bit 8)                                      */
#define GPIO_PINCFG24_OUTCFG24_Msk        (0x300UL)                 /*!< OUTCFG24 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG24_IRPTEN24_Pos        (6UL)                     /*!< IRPTEN24 (Bit 6)                                      */
#define GPIO_PINCFG24_IRPTEN24_Msk        (0xc0UL)                  /*!< IRPTEN24 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG24_RDZERO24_Pos        (5UL)                     /*!< RDZERO24 (Bit 5)                                      */
#define GPIO_PINCFG24_RDZERO24_Msk        (0x20UL)                  /*!< RDZERO24 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG24_INPEN24_Pos         (4UL)                     /*!< INPEN24 (Bit 4)                                       */
#define GPIO_PINCFG24_INPEN24_Msk         (0x10UL)                  /*!< INPEN24 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG24_FNCSEL24_Pos        (0UL)                     /*!< FNCSEL24 (Bit 0)                                      */
#define GPIO_PINCFG24_FNCSEL24_Msk        (0xfUL)                   /*!< FNCSEL24 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG25  ======================================================== */
#define GPIO_PINCFG25_FOEN25_Pos          (27UL)                    /*!< FOEN25 (Bit 27)                                       */
#define GPIO_PINCFG25_FOEN25_Msk          (0x8000000UL)             /*!< FOEN25 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG25_FIEN25_Pos          (26UL)                    /*!< FIEN25 (Bit 26)                                       */
#define GPIO_PINCFG25_FIEN25_Msk          (0x4000000UL)             /*!< FIEN25 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG25_NCEPOL25_Pos        (22UL)                    /*!< NCEPOL25 (Bit 22)                                     */
#define GPIO_PINCFG25_NCEPOL25_Msk        (0x400000UL)              /*!< NCEPOL25 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG25_NCESRC25_Pos        (16UL)                    /*!< NCESRC25 (Bit 16)                                     */
#define GPIO_PINCFG25_NCESRC25_Msk        (0x3f0000UL)              /*!< NCESRC25 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG25_PULLCFG25_Pos       (13UL)                    /*!< PULLCFG25 (Bit 13)                                    */
#define GPIO_PINCFG25_PULLCFG25_Msk       (0xe000UL)                /*!< PULLCFG25 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG25_SR25_Pos            (12UL)                    /*!< SR25 (Bit 12)                                         */
#define GPIO_PINCFG25_SR25_Msk            (0x1000UL)                /*!< SR25 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG25_DS25_Pos            (10UL)                    /*!< DS25 (Bit 10)                                         */
#define GPIO_PINCFG25_DS25_Msk            (0xc00UL)                 /*!< DS25 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG25_OUTCFG25_Pos        (8UL)                     /*!< OUTCFG25 (Bit 8)                                      */
#define GPIO_PINCFG25_OUTCFG25_Msk        (0x300UL)                 /*!< OUTCFG25 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG25_IRPTEN25_Pos        (6UL)                     /*!< IRPTEN25 (Bit 6)                                      */
#define GPIO_PINCFG25_IRPTEN25_Msk        (0xc0UL)                  /*!< IRPTEN25 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG25_RDZERO25_Pos        (5UL)                     /*!< RDZERO25 (Bit 5)                                      */
#define GPIO_PINCFG25_RDZERO25_Msk        (0x20UL)                  /*!< RDZERO25 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG25_INPEN25_Pos         (4UL)                     /*!< INPEN25 (Bit 4)                                       */
#define GPIO_PINCFG25_INPEN25_Msk         (0x10UL)                  /*!< INPEN25 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG25_FNCSEL25_Pos        (0UL)                     /*!< FNCSEL25 (Bit 0)                                      */
#define GPIO_PINCFG25_FNCSEL25_Msk        (0xfUL)                   /*!< FNCSEL25 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG26  ======================================================== */
#define GPIO_PINCFG26_FOEN26_Pos          (27UL)                    /*!< FOEN26 (Bit 27)                                       */
#define GPIO_PINCFG26_FOEN26_Msk          (0x8000000UL)             /*!< FOEN26 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG26_FIEN26_Pos          (26UL)                    /*!< FIEN26 (Bit 26)                                       */
#define GPIO_PINCFG26_FIEN26_Msk          (0x4000000UL)             /*!< FIEN26 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG26_NCEPOL26_Pos        (22UL)                    /*!< NCEPOL26 (Bit 22)                                     */
#define GPIO_PINCFG26_NCEPOL26_Msk        (0x400000UL)              /*!< NCEPOL26 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG26_NCESRC26_Pos        (16UL)                    /*!< NCESRC26 (Bit 16)                                     */
#define GPIO_PINCFG26_NCESRC26_Msk        (0x3f0000UL)              /*!< NCESRC26 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG26_PULLCFG26_Pos       (13UL)                    /*!< PULLCFG26 (Bit 13)                                    */
#define GPIO_PINCFG26_PULLCFG26_Msk       (0xe000UL)                /*!< PULLCFG26 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG26_SR26_Pos            (12UL)                    /*!< SR26 (Bit 12)                                         */
#define GPIO_PINCFG26_SR26_Msk            (0x1000UL)                /*!< SR26 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG26_DS26_Pos            (10UL)                    /*!< DS26 (Bit 10)                                         */
#define GPIO_PINCFG26_DS26_Msk            (0xc00UL)                 /*!< DS26 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG26_OUTCFG26_Pos        (8UL)                     /*!< OUTCFG26 (Bit 8)                                      */
#define GPIO_PINCFG26_OUTCFG26_Msk        (0x300UL)                 /*!< OUTCFG26 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG26_IRPTEN26_Pos        (6UL)                     /*!< IRPTEN26 (Bit 6)                                      */
#define GPIO_PINCFG26_IRPTEN26_Msk        (0xc0UL)                  /*!< IRPTEN26 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG26_RDZERO26_Pos        (5UL)                     /*!< RDZERO26 (Bit 5)                                      */
#define GPIO_PINCFG26_RDZERO26_Msk        (0x20UL)                  /*!< RDZERO26 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG26_INPEN26_Pos         (4UL)                     /*!< INPEN26 (Bit 4)                                       */
#define GPIO_PINCFG26_INPEN26_Msk         (0x10UL)                  /*!< INPEN26 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG26_FNCSEL26_Pos        (0UL)                     /*!< FNCSEL26 (Bit 0)                                      */
#define GPIO_PINCFG26_FNCSEL26_Msk        (0xfUL)                   /*!< FNCSEL26 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG27  ======================================================== */
#define GPIO_PINCFG27_FOEN27_Pos          (27UL)                    /*!< FOEN27 (Bit 27)                                       */
#define GPIO_PINCFG27_FOEN27_Msk          (0x8000000UL)             /*!< FOEN27 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG27_FIEN27_Pos          (26UL)                    /*!< FIEN27 (Bit 26)                                       */
#define GPIO_PINCFG27_FIEN27_Msk          (0x4000000UL)             /*!< FIEN27 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG27_NCEPOL27_Pos        (22UL)                    /*!< NCEPOL27 (Bit 22)                                     */
#define GPIO_PINCFG27_NCEPOL27_Msk        (0x400000UL)              /*!< NCEPOL27 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG27_NCESRC27_Pos        (16UL)                    /*!< NCESRC27 (Bit 16)                                     */
#define GPIO_PINCFG27_NCESRC27_Msk        (0x3f0000UL)              /*!< NCESRC27 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG27_PULLCFG27_Pos       (13UL)                    /*!< PULLCFG27 (Bit 13)                                    */
#define GPIO_PINCFG27_PULLCFG27_Msk       (0xe000UL)                /*!< PULLCFG27 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG27_SR27_Pos            (12UL)                    /*!< SR27 (Bit 12)                                         */
#define GPIO_PINCFG27_SR27_Msk            (0x1000UL)                /*!< SR27 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG27_DS27_Pos            (10UL)                    /*!< DS27 (Bit 10)                                         */
#define GPIO_PINCFG27_DS27_Msk            (0xc00UL)                 /*!< DS27 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG27_OUTCFG27_Pos        (8UL)                     /*!< OUTCFG27 (Bit 8)                                      */
#define GPIO_PINCFG27_OUTCFG27_Msk        (0x300UL)                 /*!< OUTCFG27 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG27_IRPTEN27_Pos        (6UL)                     /*!< IRPTEN27 (Bit 6)                                      */
#define GPIO_PINCFG27_IRPTEN27_Msk        (0xc0UL)                  /*!< IRPTEN27 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG27_RDZERO27_Pos        (5UL)                     /*!< RDZERO27 (Bit 5)                                      */
#define GPIO_PINCFG27_RDZERO27_Msk        (0x20UL)                  /*!< RDZERO27 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG27_INPEN27_Pos         (4UL)                     /*!< INPEN27 (Bit 4)                                       */
#define GPIO_PINCFG27_INPEN27_Msk         (0x10UL)                  /*!< INPEN27 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG27_FNCSEL27_Pos        (0UL)                     /*!< FNCSEL27 (Bit 0)                                      */
#define GPIO_PINCFG27_FNCSEL27_Msk        (0xfUL)                   /*!< FNCSEL27 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG28  ======================================================== */
#define GPIO_PINCFG28_FOEN28_Pos          (27UL)                    /*!< FOEN28 (Bit 27)                                       */
#define GPIO_PINCFG28_FOEN28_Msk          (0x8000000UL)             /*!< FOEN28 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG28_FIEN28_Pos          (26UL)                    /*!< FIEN28 (Bit 26)                                       */
#define GPIO_PINCFG28_FIEN28_Msk          (0x4000000UL)             /*!< FIEN28 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG28_NCEPOL28_Pos        (22UL)                    /*!< NCEPOL28 (Bit 22)                                     */
#define GPIO_PINCFG28_NCEPOL28_Msk        (0x400000UL)              /*!< NCEPOL28 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG28_NCESRC28_Pos        (16UL)                    /*!< NCESRC28 (Bit 16)                                     */
#define GPIO_PINCFG28_NCESRC28_Msk        (0x3f0000UL)              /*!< NCESRC28 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG28_PULLCFG28_Pos       (13UL)                    /*!< PULLCFG28 (Bit 13)                                    */
#define GPIO_PINCFG28_PULLCFG28_Msk       (0xe000UL)                /*!< PULLCFG28 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG28_SR28_Pos            (12UL)                    /*!< SR28 (Bit 12)                                         */
#define GPIO_PINCFG28_SR28_Msk            (0x1000UL)                /*!< SR28 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG28_DS28_Pos            (10UL)                    /*!< DS28 (Bit 10)                                         */
#define GPIO_PINCFG28_DS28_Msk            (0xc00UL)                 /*!< DS28 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG28_OUTCFG28_Pos        (8UL)                     /*!< OUTCFG28 (Bit 8)                                      */
#define GPIO_PINCFG28_OUTCFG28_Msk        (0x300UL)                 /*!< OUTCFG28 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG28_IRPTEN28_Pos        (6UL)                     /*!< IRPTEN28 (Bit 6)                                      */
#define GPIO_PINCFG28_IRPTEN28_Msk        (0xc0UL)                  /*!< IRPTEN28 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG28_RDZERO28_Pos        (5UL)                     /*!< RDZERO28 (Bit 5)                                      */
#define GPIO_PINCFG28_RDZERO28_Msk        (0x20UL)                  /*!< RDZERO28 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG28_INPEN28_Pos         (4UL)                     /*!< INPEN28 (Bit 4)                                       */
#define GPIO_PINCFG28_INPEN28_Msk         (0x10UL)                  /*!< INPEN28 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG28_FNCSEL28_Pos        (0UL)                     /*!< FNCSEL28 (Bit 0)                                      */
#define GPIO_PINCFG28_FNCSEL28_Msk        (0xfUL)                   /*!< FNCSEL28 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG29  ======================================================== */
#define GPIO_PINCFG29_FOEN29_Pos          (27UL)                    /*!< FOEN29 (Bit 27)                                       */
#define GPIO_PINCFG29_FOEN29_Msk          (0x8000000UL)             /*!< FOEN29 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG29_FIEN29_Pos          (26UL)                    /*!< FIEN29 (Bit 26)                                       */
#define GPIO_PINCFG29_FIEN29_Msk          (0x4000000UL)             /*!< FIEN29 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG29_VSSPWRSWEN29_Pos    (25UL)                    /*!< VSSPWRSWEN29 (Bit 25)                                 */
#define GPIO_PINCFG29_VSSPWRSWEN29_Msk    (0x2000000UL)             /*!< VSSPWRSWEN29 (Bitfield-Mask: 0x01)                    */
#define GPIO_PINCFG29_NCEPOL29_Pos        (22UL)                    /*!< NCEPOL29 (Bit 22)                                     */
#define GPIO_PINCFG29_NCEPOL29_Msk        (0x400000UL)              /*!< NCEPOL29 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG29_NCESRC29_Pos        (16UL)                    /*!< NCESRC29 (Bit 16)                                     */
#define GPIO_PINCFG29_NCESRC29_Msk        (0x3f0000UL)              /*!< NCESRC29 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG29_PULLCFG29_Pos       (13UL)                    /*!< PULLCFG29 (Bit 13)                                    */
#define GPIO_PINCFG29_PULLCFG29_Msk       (0xe000UL)                /*!< PULLCFG29 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG29_SR29_Pos            (12UL)                    /*!< SR29 (Bit 12)                                         */
#define GPIO_PINCFG29_SR29_Msk            (0x1000UL)                /*!< SR29 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG29_DS29_Pos            (10UL)                    /*!< DS29 (Bit 10)                                         */
#define GPIO_PINCFG29_DS29_Msk            (0xc00UL)                 /*!< DS29 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG29_OUTCFG29_Pos        (8UL)                     /*!< OUTCFG29 (Bit 8)                                      */
#define GPIO_PINCFG29_OUTCFG29_Msk        (0x300UL)                 /*!< OUTCFG29 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG29_IRPTEN29_Pos        (6UL)                     /*!< IRPTEN29 (Bit 6)                                      */
#define GPIO_PINCFG29_IRPTEN29_Msk        (0xc0UL)                  /*!< IRPTEN29 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG29_RDZERO29_Pos        (5UL)                     /*!< RDZERO29 (Bit 5)                                      */
#define GPIO_PINCFG29_RDZERO29_Msk        (0x20UL)                  /*!< RDZERO29 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG29_INPEN29_Pos         (4UL)                     /*!< INPEN29 (Bit 4)                                       */
#define GPIO_PINCFG29_INPEN29_Msk         (0x10UL)                  /*!< INPEN29 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG29_FNCSEL29_Pos        (0UL)                     /*!< FNCSEL29 (Bit 0)                                      */
#define GPIO_PINCFG29_FNCSEL29_Msk        (0xfUL)                   /*!< FNCSEL29 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG30  ======================================================== */
#define GPIO_PINCFG30_FOEN30_Pos          (27UL)                    /*!< FOEN30 (Bit 27)                                       */
#define GPIO_PINCFG30_FOEN30_Msk          (0x8000000UL)             /*!< FOEN30 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG30_FIEN30_Pos          (26UL)                    /*!< FIEN30 (Bit 26)                                       */
#define GPIO_PINCFG30_FIEN30_Msk          (0x4000000UL)             /*!< FIEN30 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG30_VDDPWRSWEN30_Pos    (25UL)                    /*!< VDDPWRSWEN30 (Bit 25)                                 */
#define GPIO_PINCFG30_VDDPWRSWEN30_Msk    (0x2000000UL)             /*!< VDDPWRSWEN30 (Bitfield-Mask: 0x01)                    */
#define GPIO_PINCFG30_NCEPOL30_Pos        (22UL)                    /*!< NCEPOL30 (Bit 22)                                     */
#define GPIO_PINCFG30_NCEPOL30_Msk        (0x400000UL)              /*!< NCEPOL30 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG30_NCESRC30_Pos        (16UL)                    /*!< NCESRC30 (Bit 16)                                     */
#define GPIO_PINCFG30_NCESRC30_Msk        (0x3f0000UL)              /*!< NCESRC30 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG30_PULLCFG30_Pos       (13UL)                    /*!< PULLCFG30 (Bit 13)                                    */
#define GPIO_PINCFG30_PULLCFG30_Msk       (0xe000UL)                /*!< PULLCFG30 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG30_SR30_Pos            (12UL)                    /*!< SR30 (Bit 12)                                         */
#define GPIO_PINCFG30_SR30_Msk            (0x1000UL)                /*!< SR30 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG30_DS30_Pos            (10UL)                    /*!< DS30 (Bit 10)                                         */
#define GPIO_PINCFG30_DS30_Msk            (0xc00UL)                 /*!< DS30 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG30_OUTCFG30_Pos        (8UL)                     /*!< OUTCFG30 (Bit 8)                                      */
#define GPIO_PINCFG30_OUTCFG30_Msk        (0x300UL)                 /*!< OUTCFG30 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG30_IRPTEN30_Pos        (6UL)                     /*!< IRPTEN30 (Bit 6)                                      */
#define GPIO_PINCFG30_IRPTEN30_Msk        (0xc0UL)                  /*!< IRPTEN30 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG30_RDZERO30_Pos        (5UL)                     /*!< RDZERO30 (Bit 5)                                      */
#define GPIO_PINCFG30_RDZERO30_Msk        (0x20UL)                  /*!< RDZERO30 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG30_INPEN30_Pos         (4UL)                     /*!< INPEN30 (Bit 4)                                       */
#define GPIO_PINCFG30_INPEN30_Msk         (0x10UL)                  /*!< INPEN30 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG30_FNCSEL30_Pos        (0UL)                     /*!< FNCSEL30 (Bit 0)                                      */
#define GPIO_PINCFG30_FNCSEL30_Msk        (0xfUL)                   /*!< FNCSEL30 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG31  ======================================================== */
#define GPIO_PINCFG31_FOEN31_Pos          (27UL)                    /*!< FOEN31 (Bit 27)                                       */
#define GPIO_PINCFG31_FOEN31_Msk          (0x8000000UL)             /*!< FOEN31 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG31_FIEN31_Pos          (26UL)                    /*!< FIEN31 (Bit 26)                                       */
#define GPIO_PINCFG31_FIEN31_Msk          (0x4000000UL)             /*!< FIEN31 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG31_NCEPOL31_Pos        (22UL)                    /*!< NCEPOL31 (Bit 22)                                     */
#define GPIO_PINCFG31_NCEPOL31_Msk        (0x400000UL)              /*!< NCEPOL31 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG31_NCESRC31_Pos        (16UL)                    /*!< NCESRC31 (Bit 16)                                     */
#define GPIO_PINCFG31_NCESRC31_Msk        (0x3f0000UL)              /*!< NCESRC31 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG31_PULLCFG31_Pos       (13UL)                    /*!< PULLCFG31 (Bit 13)                                    */
#define GPIO_PINCFG31_PULLCFG31_Msk       (0xe000UL)                /*!< PULLCFG31 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG31_SR31_Pos            (12UL)                    /*!< SR31 (Bit 12)                                         */
#define GPIO_PINCFG31_SR31_Msk            (0x1000UL)                /*!< SR31 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG31_DS31_Pos            (10UL)                    /*!< DS31 (Bit 10)                                         */
#define GPIO_PINCFG31_DS31_Msk            (0xc00UL)                 /*!< DS31 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG31_OUTCFG31_Pos        (8UL)                     /*!< OUTCFG31 (Bit 8)                                      */
#define GPIO_PINCFG31_OUTCFG31_Msk        (0x300UL)                 /*!< OUTCFG31 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG31_IRPTEN31_Pos        (6UL)                     /*!< IRPTEN31 (Bit 6)                                      */
#define GPIO_PINCFG31_IRPTEN31_Msk        (0xc0UL)                  /*!< IRPTEN31 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG31_RDZERO31_Pos        (5UL)                     /*!< RDZERO31 (Bit 5)                                      */
#define GPIO_PINCFG31_RDZERO31_Msk        (0x20UL)                  /*!< RDZERO31 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG31_INPEN31_Pos         (4UL)                     /*!< INPEN31 (Bit 4)                                       */
#define GPIO_PINCFG31_INPEN31_Msk         (0x10UL)                  /*!< INPEN31 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG31_FNCSEL31_Pos        (0UL)                     /*!< FNCSEL31 (Bit 0)                                      */
#define GPIO_PINCFG31_FNCSEL31_Msk        (0xfUL)                   /*!< FNCSEL31 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG32  ======================================================== */
#define GPIO_PINCFG32_FOEN32_Pos          (27UL)                    /*!< FOEN32 (Bit 27)                                       */
#define GPIO_PINCFG32_FOEN32_Msk          (0x8000000UL)             /*!< FOEN32 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG32_FIEN32_Pos          (26UL)                    /*!< FIEN32 (Bit 26)                                       */
#define GPIO_PINCFG32_FIEN32_Msk          (0x4000000UL)             /*!< FIEN32 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG32_NCEPOL32_Pos        (22UL)                    /*!< NCEPOL32 (Bit 22)                                     */
#define GPIO_PINCFG32_NCEPOL32_Msk        (0x400000UL)              /*!< NCEPOL32 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG32_NCESRC32_Pos        (16UL)                    /*!< NCESRC32 (Bit 16)                                     */
#define GPIO_PINCFG32_NCESRC32_Msk        (0x3f0000UL)              /*!< NCESRC32 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG32_PULLCFG32_Pos       (13UL)                    /*!< PULLCFG32 (Bit 13)                                    */
#define GPIO_PINCFG32_PULLCFG32_Msk       (0xe000UL)                /*!< PULLCFG32 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG32_SR32_Pos            (12UL)                    /*!< SR32 (Bit 12)                                         */
#define GPIO_PINCFG32_SR32_Msk            (0x1000UL)                /*!< SR32 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG32_DS32_Pos            (10UL)                    /*!< DS32 (Bit 10)                                         */
#define GPIO_PINCFG32_DS32_Msk            (0xc00UL)                 /*!< DS32 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG32_OUTCFG32_Pos        (8UL)                     /*!< OUTCFG32 (Bit 8)                                      */
#define GPIO_PINCFG32_OUTCFG32_Msk        (0x300UL)                 /*!< OUTCFG32 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG32_IRPTEN32_Pos        (6UL)                     /*!< IRPTEN32 (Bit 6)                                      */
#define GPIO_PINCFG32_IRPTEN32_Msk        (0xc0UL)                  /*!< IRPTEN32 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG32_RDZERO32_Pos        (5UL)                     /*!< RDZERO32 (Bit 5)                                      */
#define GPIO_PINCFG32_RDZERO32_Msk        (0x20UL)                  /*!< RDZERO32 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG32_INPEN32_Pos         (4UL)                     /*!< INPEN32 (Bit 4)                                       */
#define GPIO_PINCFG32_INPEN32_Msk         (0x10UL)                  /*!< INPEN32 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG32_FNCSEL32_Pos        (0UL)                     /*!< FNCSEL32 (Bit 0)                                      */
#define GPIO_PINCFG32_FNCSEL32_Msk        (0xfUL)                   /*!< FNCSEL32 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG33  ======================================================== */
#define GPIO_PINCFG33_FOEN33_Pos          (27UL)                    /*!< FOEN33 (Bit 27)                                       */
#define GPIO_PINCFG33_FOEN33_Msk          (0x8000000UL)             /*!< FOEN33 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG33_FIEN33_Pos          (26UL)                    /*!< FIEN33 (Bit 26)                                       */
#define GPIO_PINCFG33_FIEN33_Msk          (0x4000000UL)             /*!< FIEN33 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG33_NCEPOL33_Pos        (22UL)                    /*!< NCEPOL33 (Bit 22)                                     */
#define GPIO_PINCFG33_NCEPOL33_Msk        (0x400000UL)              /*!< NCEPOL33 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG33_NCESRC33_Pos        (16UL)                    /*!< NCESRC33 (Bit 16)                                     */
#define GPIO_PINCFG33_NCESRC33_Msk        (0x3f0000UL)              /*!< NCESRC33 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG33_PULLCFG33_Pos       (13UL)                    /*!< PULLCFG33 (Bit 13)                                    */
#define GPIO_PINCFG33_PULLCFG33_Msk       (0xe000UL)                /*!< PULLCFG33 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG33_SR33_Pos            (12UL)                    /*!< SR33 (Bit 12)                                         */
#define GPIO_PINCFG33_SR33_Msk            (0x1000UL)                /*!< SR33 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG33_DS33_Pos            (10UL)                    /*!< DS33 (Bit 10)                                         */
#define GPIO_PINCFG33_DS33_Msk            (0xc00UL)                 /*!< DS33 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG33_OUTCFG33_Pos        (8UL)                     /*!< OUTCFG33 (Bit 8)                                      */
#define GPIO_PINCFG33_OUTCFG33_Msk        (0x300UL)                 /*!< OUTCFG33 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG33_IRPTEN33_Pos        (6UL)                     /*!< IRPTEN33 (Bit 6)                                      */
#define GPIO_PINCFG33_IRPTEN33_Msk        (0xc0UL)                  /*!< IRPTEN33 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG33_RDZERO33_Pos        (5UL)                     /*!< RDZERO33 (Bit 5)                                      */
#define GPIO_PINCFG33_RDZERO33_Msk        (0x20UL)                  /*!< RDZERO33 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG33_INPEN33_Pos         (4UL)                     /*!< INPEN33 (Bit 4)                                       */
#define GPIO_PINCFG33_INPEN33_Msk         (0x10UL)                  /*!< INPEN33 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG33_FNCSEL33_Pos        (0UL)                     /*!< FNCSEL33 (Bit 0)                                      */
#define GPIO_PINCFG33_FNCSEL33_Msk        (0xfUL)                   /*!< FNCSEL33 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG34  ======================================================== */
#define GPIO_PINCFG34_FOEN34_Pos          (27UL)                    /*!< FOEN34 (Bit 27)                                       */
#define GPIO_PINCFG34_FOEN34_Msk          (0x8000000UL)             /*!< FOEN34 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG34_FIEN34_Pos          (26UL)                    /*!< FIEN34 (Bit 26)                                       */
#define GPIO_PINCFG34_FIEN34_Msk          (0x4000000UL)             /*!< FIEN34 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG34_NCEPOL34_Pos        (22UL)                    /*!< NCEPOL34 (Bit 22)                                     */
#define GPIO_PINCFG34_NCEPOL34_Msk        (0x400000UL)              /*!< NCEPOL34 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG34_NCESRC34_Pos        (16UL)                    /*!< NCESRC34 (Bit 16)                                     */
#define GPIO_PINCFG34_NCESRC34_Msk        (0x3f0000UL)              /*!< NCESRC34 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG34_PULLCFG34_Pos       (13UL)                    /*!< PULLCFG34 (Bit 13)                                    */
#define GPIO_PINCFG34_PULLCFG34_Msk       (0xe000UL)                /*!< PULLCFG34 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG34_SR34_Pos            (12UL)                    /*!< SR34 (Bit 12)                                         */
#define GPIO_PINCFG34_SR34_Msk            (0x1000UL)                /*!< SR34 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG34_DS34_Pos            (10UL)                    /*!< DS34 (Bit 10)                                         */
#define GPIO_PINCFG34_DS34_Msk            (0xc00UL)                 /*!< DS34 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG34_OUTCFG34_Pos        (8UL)                     /*!< OUTCFG34 (Bit 8)                                      */
#define GPIO_PINCFG34_OUTCFG34_Msk        (0x300UL)                 /*!< OUTCFG34 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG34_IRPTEN34_Pos        (6UL)                     /*!< IRPTEN34 (Bit 6)                                      */
#define GPIO_PINCFG34_IRPTEN34_Msk        (0xc0UL)                  /*!< IRPTEN34 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG34_RDZERO34_Pos        (5UL)                     /*!< RDZERO34 (Bit 5)                                      */
#define GPIO_PINCFG34_RDZERO34_Msk        (0x20UL)                  /*!< RDZERO34 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG34_INPEN34_Pos         (4UL)                     /*!< INPEN34 (Bit 4)                                       */
#define GPIO_PINCFG34_INPEN34_Msk         (0x10UL)                  /*!< INPEN34 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG34_FNCSEL34_Pos        (0UL)                     /*!< FNCSEL34 (Bit 0)                                      */
#define GPIO_PINCFG34_FNCSEL34_Msk        (0xfUL)                   /*!< FNCSEL34 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG35  ======================================================== */
#define GPIO_PINCFG35_FOEN35_Pos          (27UL)                    /*!< FOEN35 (Bit 27)                                       */
#define GPIO_PINCFG35_FOEN35_Msk          (0x8000000UL)             /*!< FOEN35 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG35_FIEN35_Pos          (26UL)                    /*!< FIEN35 (Bit 26)                                       */
#define GPIO_PINCFG35_FIEN35_Msk          (0x4000000UL)             /*!< FIEN35 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG35_NCEPOL35_Pos        (22UL)                    /*!< NCEPOL35 (Bit 22)                                     */
#define GPIO_PINCFG35_NCEPOL35_Msk        (0x400000UL)              /*!< NCEPOL35 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG35_NCESRC35_Pos        (16UL)                    /*!< NCESRC35 (Bit 16)                                     */
#define GPIO_PINCFG35_NCESRC35_Msk        (0x3f0000UL)              /*!< NCESRC35 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG35_PULLCFG35_Pos       (13UL)                    /*!< PULLCFG35 (Bit 13)                                    */
#define GPIO_PINCFG35_PULLCFG35_Msk       (0xe000UL)                /*!< PULLCFG35 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG35_SR35_Pos            (12UL)                    /*!< SR35 (Bit 12)                                         */
#define GPIO_PINCFG35_SR35_Msk            (0x1000UL)                /*!< SR35 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG35_DS35_Pos            (10UL)                    /*!< DS35 (Bit 10)                                         */
#define GPIO_PINCFG35_DS35_Msk            (0xc00UL)                 /*!< DS35 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG35_OUTCFG35_Pos        (8UL)                     /*!< OUTCFG35 (Bit 8)                                      */
#define GPIO_PINCFG35_OUTCFG35_Msk        (0x300UL)                 /*!< OUTCFG35 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG35_IRPTEN35_Pos        (6UL)                     /*!< IRPTEN35 (Bit 6)                                      */
#define GPIO_PINCFG35_IRPTEN35_Msk        (0xc0UL)                  /*!< IRPTEN35 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG35_RDZERO35_Pos        (5UL)                     /*!< RDZERO35 (Bit 5)                                      */
#define GPIO_PINCFG35_RDZERO35_Msk        (0x20UL)                  /*!< RDZERO35 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG35_INPEN35_Pos         (4UL)                     /*!< INPEN35 (Bit 4)                                       */
#define GPIO_PINCFG35_INPEN35_Msk         (0x10UL)                  /*!< INPEN35 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG35_FNCSEL35_Pos        (0UL)                     /*!< FNCSEL35 (Bit 0)                                      */
#define GPIO_PINCFG35_FNCSEL35_Msk        (0xfUL)                   /*!< FNCSEL35 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG36  ======================================================== */
#define GPIO_PINCFG36_FOEN36_Pos          (27UL)                    /*!< FOEN36 (Bit 27)                                       */
#define GPIO_PINCFG36_FOEN36_Msk          (0x8000000UL)             /*!< FOEN36 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG36_FIEN36_Pos          (26UL)                    /*!< FIEN36 (Bit 26)                                       */
#define GPIO_PINCFG36_FIEN36_Msk          (0x4000000UL)             /*!< FIEN36 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG36_NCEPOL36_Pos        (22UL)                    /*!< NCEPOL36 (Bit 22)                                     */
#define GPIO_PINCFG36_NCEPOL36_Msk        (0x400000UL)              /*!< NCEPOL36 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG36_NCESRC36_Pos        (16UL)                    /*!< NCESRC36 (Bit 16)                                     */
#define GPIO_PINCFG36_NCESRC36_Msk        (0x3f0000UL)              /*!< NCESRC36 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG36_PULLCFG36_Pos       (13UL)                    /*!< PULLCFG36 (Bit 13)                                    */
#define GPIO_PINCFG36_PULLCFG36_Msk       (0xe000UL)                /*!< PULLCFG36 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG36_SR36_Pos            (12UL)                    /*!< SR36 (Bit 12)                                         */
#define GPIO_PINCFG36_SR36_Msk            (0x1000UL)                /*!< SR36 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG36_DS36_Pos            (10UL)                    /*!< DS36 (Bit 10)                                         */
#define GPIO_PINCFG36_DS36_Msk            (0xc00UL)                 /*!< DS36 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG36_OUTCFG36_Pos        (8UL)                     /*!< OUTCFG36 (Bit 8)                                      */
#define GPIO_PINCFG36_OUTCFG36_Msk        (0x300UL)                 /*!< OUTCFG36 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG36_IRPTEN36_Pos        (6UL)                     /*!< IRPTEN36 (Bit 6)                                      */
#define GPIO_PINCFG36_IRPTEN36_Msk        (0xc0UL)                  /*!< IRPTEN36 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG36_RDZERO36_Pos        (5UL)                     /*!< RDZERO36 (Bit 5)                                      */
#define GPIO_PINCFG36_RDZERO36_Msk        (0x20UL)                  /*!< RDZERO36 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG36_INPEN36_Pos         (4UL)                     /*!< INPEN36 (Bit 4)                                       */
#define GPIO_PINCFG36_INPEN36_Msk         (0x10UL)                  /*!< INPEN36 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG36_FNCSEL36_Pos        (0UL)                     /*!< FNCSEL36 (Bit 0)                                      */
#define GPIO_PINCFG36_FNCSEL36_Msk        (0xfUL)                   /*!< FNCSEL36 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG37  ======================================================== */
#define GPIO_PINCFG37_FOEN37_Pos          (27UL)                    /*!< FOEN37 (Bit 27)                                       */
#define GPIO_PINCFG37_FOEN37_Msk          (0x8000000UL)             /*!< FOEN37 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG37_FIEN37_Pos          (26UL)                    /*!< FIEN37 (Bit 26)                                       */
#define GPIO_PINCFG37_FIEN37_Msk          (0x4000000UL)             /*!< FIEN37 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG37_NCEPOL37_Pos        (22UL)                    /*!< NCEPOL37 (Bit 22)                                     */
#define GPIO_PINCFG37_NCEPOL37_Msk        (0x400000UL)              /*!< NCEPOL37 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG37_NCESRC37_Pos        (16UL)                    /*!< NCESRC37 (Bit 16)                                     */
#define GPIO_PINCFG37_NCESRC37_Msk        (0x3f0000UL)              /*!< NCESRC37 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG37_PULLCFG37_Pos       (13UL)                    /*!< PULLCFG37 (Bit 13)                                    */
#define GPIO_PINCFG37_PULLCFG37_Msk       (0xe000UL)                /*!< PULLCFG37 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG37_SR37_Pos            (12UL)                    /*!< SR37 (Bit 12)                                         */
#define GPIO_PINCFG37_SR37_Msk            (0x1000UL)                /*!< SR37 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG37_DS37_Pos            (10UL)                    /*!< DS37 (Bit 10)                                         */
#define GPIO_PINCFG37_DS37_Msk            (0xc00UL)                 /*!< DS37 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG37_OUTCFG37_Pos        (8UL)                     /*!< OUTCFG37 (Bit 8)                                      */
#define GPIO_PINCFG37_OUTCFG37_Msk        (0x300UL)                 /*!< OUTCFG37 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG37_IRPTEN37_Pos        (6UL)                     /*!< IRPTEN37 (Bit 6)                                      */
#define GPIO_PINCFG37_IRPTEN37_Msk        (0xc0UL)                  /*!< IRPTEN37 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG37_RDZERO37_Pos        (5UL)                     /*!< RDZERO37 (Bit 5)                                      */
#define GPIO_PINCFG37_RDZERO37_Msk        (0x20UL)                  /*!< RDZERO37 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG37_INPEN37_Pos         (4UL)                     /*!< INPEN37 (Bit 4)                                       */
#define GPIO_PINCFG37_INPEN37_Msk         (0x10UL)                  /*!< INPEN37 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG37_FNCSEL37_Pos        (0UL)                     /*!< FNCSEL37 (Bit 0)                                      */
#define GPIO_PINCFG37_FNCSEL37_Msk        (0xfUL)                   /*!< FNCSEL37 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG38  ======================================================== */
#define GPIO_PINCFG38_FOEN38_Pos          (27UL)                    /*!< FOEN38 (Bit 27)                                       */
#define GPIO_PINCFG38_FOEN38_Msk          (0x8000000UL)             /*!< FOEN38 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG38_FIEN38_Pos          (26UL)                    /*!< FIEN38 (Bit 26)                                       */
#define GPIO_PINCFG38_FIEN38_Msk          (0x4000000UL)             /*!< FIEN38 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG38_NCEPOL38_Pos        (22UL)                    /*!< NCEPOL38 (Bit 22)                                     */
#define GPIO_PINCFG38_NCEPOL38_Msk        (0x400000UL)              /*!< NCEPOL38 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG38_NCESRC38_Pos        (16UL)                    /*!< NCESRC38 (Bit 16)                                     */
#define GPIO_PINCFG38_NCESRC38_Msk        (0x3f0000UL)              /*!< NCESRC38 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG38_PULLCFG38_Pos       (13UL)                    /*!< PULLCFG38 (Bit 13)                                    */
#define GPIO_PINCFG38_PULLCFG38_Msk       (0xe000UL)                /*!< PULLCFG38 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG38_SR38_Pos            (12UL)                    /*!< SR38 (Bit 12)                                         */
#define GPIO_PINCFG38_SR38_Msk            (0x1000UL)                /*!< SR38 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG38_DS38_Pos            (10UL)                    /*!< DS38 (Bit 10)                                         */
#define GPIO_PINCFG38_DS38_Msk            (0xc00UL)                 /*!< DS38 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG38_OUTCFG38_Pos        (8UL)                     /*!< OUTCFG38 (Bit 8)                                      */
#define GPIO_PINCFG38_OUTCFG38_Msk        (0x300UL)                 /*!< OUTCFG38 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG38_IRPTEN38_Pos        (6UL)                     /*!< IRPTEN38 (Bit 6)                                      */
#define GPIO_PINCFG38_IRPTEN38_Msk        (0xc0UL)                  /*!< IRPTEN38 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG38_RDZERO38_Pos        (5UL)                     /*!< RDZERO38 (Bit 5)                                      */
#define GPIO_PINCFG38_RDZERO38_Msk        (0x20UL)                  /*!< RDZERO38 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG38_INPEN38_Pos         (4UL)                     /*!< INPEN38 (Bit 4)                                       */
#define GPIO_PINCFG38_INPEN38_Msk         (0x10UL)                  /*!< INPEN38 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG38_FNCSEL38_Pos        (0UL)                     /*!< FNCSEL38 (Bit 0)                                      */
#define GPIO_PINCFG38_FNCSEL38_Msk        (0xfUL)                   /*!< FNCSEL38 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG39  ======================================================== */
#define GPIO_PINCFG39_FOEN39_Pos          (27UL)                    /*!< FOEN39 (Bit 27)                                       */
#define GPIO_PINCFG39_FOEN39_Msk          (0x8000000UL)             /*!< FOEN39 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG39_FIEN39_Pos          (26UL)                    /*!< FIEN39 (Bit 26)                                       */
#define GPIO_PINCFG39_FIEN39_Msk          (0x4000000UL)             /*!< FIEN39 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG39_NCEPOL39_Pos        (22UL)                    /*!< NCEPOL39 (Bit 22)                                     */
#define GPIO_PINCFG39_NCEPOL39_Msk        (0x400000UL)              /*!< NCEPOL39 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG39_NCESRC39_Pos        (16UL)                    /*!< NCESRC39 (Bit 16)                                     */
#define GPIO_PINCFG39_NCESRC39_Msk        (0x3f0000UL)              /*!< NCESRC39 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG39_PULLCFG39_Pos       (13UL)                    /*!< PULLCFG39 (Bit 13)                                    */
#define GPIO_PINCFG39_PULLCFG39_Msk       (0xe000UL)                /*!< PULLCFG39 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG39_SR39_Pos            (12UL)                    /*!< SR39 (Bit 12)                                         */
#define GPIO_PINCFG39_SR39_Msk            (0x1000UL)                /*!< SR39 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG39_DS39_Pos            (10UL)                    /*!< DS39 (Bit 10)                                         */
#define GPIO_PINCFG39_DS39_Msk            (0xc00UL)                 /*!< DS39 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG39_OUTCFG39_Pos        (8UL)                     /*!< OUTCFG39 (Bit 8)                                      */
#define GPIO_PINCFG39_OUTCFG39_Msk        (0x300UL)                 /*!< OUTCFG39 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG39_IRPTEN39_Pos        (6UL)                     /*!< IRPTEN39 (Bit 6)                                      */
#define GPIO_PINCFG39_IRPTEN39_Msk        (0xc0UL)                  /*!< IRPTEN39 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG39_RDZERO39_Pos        (5UL)                     /*!< RDZERO39 (Bit 5)                                      */
#define GPIO_PINCFG39_RDZERO39_Msk        (0x20UL)                  /*!< RDZERO39 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG39_INPEN39_Pos         (4UL)                     /*!< INPEN39 (Bit 4)                                       */
#define GPIO_PINCFG39_INPEN39_Msk         (0x10UL)                  /*!< INPEN39 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG39_FNCSEL39_Pos        (0UL)                     /*!< FNCSEL39 (Bit 0)                                      */
#define GPIO_PINCFG39_FNCSEL39_Msk        (0xfUL)                   /*!< FNCSEL39 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG40  ======================================================== */
#define GPIO_PINCFG40_FOEN40_Pos          (27UL)                    /*!< FOEN40 (Bit 27)                                       */
#define GPIO_PINCFG40_FOEN40_Msk          (0x8000000UL)             /*!< FOEN40 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG40_FIEN40_Pos          (26UL)                    /*!< FIEN40 (Bit 26)                                       */
#define GPIO_PINCFG40_FIEN40_Msk          (0x4000000UL)             /*!< FIEN40 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG40_NCEPOL40_Pos        (22UL)                    /*!< NCEPOL40 (Bit 22)                                     */
#define GPIO_PINCFG40_NCEPOL40_Msk        (0x400000UL)              /*!< NCEPOL40 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG40_NCESRC40_Pos        (16UL)                    /*!< NCESRC40 (Bit 16)                                     */
#define GPIO_PINCFG40_NCESRC40_Msk        (0x3f0000UL)              /*!< NCESRC40 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG40_PULLCFG40_Pos       (13UL)                    /*!< PULLCFG40 (Bit 13)                                    */
#define GPIO_PINCFG40_PULLCFG40_Msk       (0xe000UL)                /*!< PULLCFG40 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG40_SR40_Pos            (12UL)                    /*!< SR40 (Bit 12)                                         */
#define GPIO_PINCFG40_SR40_Msk            (0x1000UL)                /*!< SR40 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG40_DS40_Pos            (10UL)                    /*!< DS40 (Bit 10)                                         */
#define GPIO_PINCFG40_DS40_Msk            (0xc00UL)                 /*!< DS40 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG40_OUTCFG40_Pos        (8UL)                     /*!< OUTCFG40 (Bit 8)                                      */
#define GPIO_PINCFG40_OUTCFG40_Msk        (0x300UL)                 /*!< OUTCFG40 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG40_IRPTEN40_Pos        (6UL)                     /*!< IRPTEN40 (Bit 6)                                      */
#define GPIO_PINCFG40_IRPTEN40_Msk        (0xc0UL)                  /*!< IRPTEN40 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG40_RDZERO40_Pos        (5UL)                     /*!< RDZERO40 (Bit 5)                                      */
#define GPIO_PINCFG40_RDZERO40_Msk        (0x20UL)                  /*!< RDZERO40 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG40_INPEN40_Pos         (4UL)                     /*!< INPEN40 (Bit 4)                                       */
#define GPIO_PINCFG40_INPEN40_Msk         (0x10UL)                  /*!< INPEN40 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG40_FNCSEL40_Pos        (0UL)                     /*!< FNCSEL40 (Bit 0)                                      */
#define GPIO_PINCFG40_FNCSEL40_Msk        (0xfUL)                   /*!< FNCSEL40 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG41  ======================================================== */
#define GPIO_PINCFG41_FOEN41_Pos          (27UL)                    /*!< FOEN41 (Bit 27)                                       */
#define GPIO_PINCFG41_FOEN41_Msk          (0x8000000UL)             /*!< FOEN41 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG41_FIEN41_Pos          (26UL)                    /*!< FIEN41 (Bit 26)                                       */
#define GPIO_PINCFG41_FIEN41_Msk          (0x4000000UL)             /*!< FIEN41 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG41_NCEPOL41_Pos        (22UL)                    /*!< NCEPOL41 (Bit 22)                                     */
#define GPIO_PINCFG41_NCEPOL41_Msk        (0x400000UL)              /*!< NCEPOL41 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG41_NCESRC41_Pos        (16UL)                    /*!< NCESRC41 (Bit 16)                                     */
#define GPIO_PINCFG41_NCESRC41_Msk        (0x3f0000UL)              /*!< NCESRC41 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG41_PULLCFG41_Pos       (13UL)                    /*!< PULLCFG41 (Bit 13)                                    */
#define GPIO_PINCFG41_PULLCFG41_Msk       (0xe000UL)                /*!< PULLCFG41 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG41_SR41_Pos            (12UL)                    /*!< SR41 (Bit 12)                                         */
#define GPIO_PINCFG41_SR41_Msk            (0x1000UL)                /*!< SR41 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG41_DS41_Pos            (10UL)                    /*!< DS41 (Bit 10)                                         */
#define GPIO_PINCFG41_DS41_Msk            (0xc00UL)                 /*!< DS41 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG41_OUTCFG41_Pos        (8UL)                     /*!< OUTCFG41 (Bit 8)                                      */
#define GPIO_PINCFG41_OUTCFG41_Msk        (0x300UL)                 /*!< OUTCFG41 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG41_IRPTEN41_Pos        (6UL)                     /*!< IRPTEN41 (Bit 6)                                      */
#define GPIO_PINCFG41_IRPTEN41_Msk        (0xc0UL)                  /*!< IRPTEN41 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG41_RDZERO41_Pos        (5UL)                     /*!< RDZERO41 (Bit 5)                                      */
#define GPIO_PINCFG41_RDZERO41_Msk        (0x20UL)                  /*!< RDZERO41 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG41_INPEN41_Pos         (4UL)                     /*!< INPEN41 (Bit 4)                                       */
#define GPIO_PINCFG41_INPEN41_Msk         (0x10UL)                  /*!< INPEN41 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG41_FNCSEL41_Pos        (0UL)                     /*!< FNCSEL41 (Bit 0)                                      */
#define GPIO_PINCFG41_FNCSEL41_Msk        (0xfUL)                   /*!< FNCSEL41 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG42  ======================================================== */
#define GPIO_PINCFG42_FOEN42_Pos          (27UL)                    /*!< FOEN42 (Bit 27)                                       */
#define GPIO_PINCFG42_FOEN42_Msk          (0x8000000UL)             /*!< FOEN42 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG42_FIEN42_Pos          (26UL)                    /*!< FIEN42 (Bit 26)                                       */
#define GPIO_PINCFG42_FIEN42_Msk          (0x4000000UL)             /*!< FIEN42 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG42_NCEPOL42_Pos        (22UL)                    /*!< NCEPOL42 (Bit 22)                                     */
#define GPIO_PINCFG42_NCEPOL42_Msk        (0x400000UL)              /*!< NCEPOL42 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG42_NCESRC42_Pos        (16UL)                    /*!< NCESRC42 (Bit 16)                                     */
#define GPIO_PINCFG42_NCESRC42_Msk        (0x3f0000UL)              /*!< NCESRC42 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG42_PULLCFG42_Pos       (13UL)                    /*!< PULLCFG42 (Bit 13)                                    */
#define GPIO_PINCFG42_PULLCFG42_Msk       (0xe000UL)                /*!< PULLCFG42 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG42_SR42_Pos            (12UL)                    /*!< SR42 (Bit 12)                                         */
#define GPIO_PINCFG42_SR42_Msk            (0x1000UL)                /*!< SR42 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG42_DS42_Pos            (10UL)                    /*!< DS42 (Bit 10)                                         */
#define GPIO_PINCFG42_DS42_Msk            (0xc00UL)                 /*!< DS42 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG42_OUTCFG42_Pos        (8UL)                     /*!< OUTCFG42 (Bit 8)                                      */
#define GPIO_PINCFG42_OUTCFG42_Msk        (0x300UL)                 /*!< OUTCFG42 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG42_IRPTEN42_Pos        (6UL)                     /*!< IRPTEN42 (Bit 6)                                      */
#define GPIO_PINCFG42_IRPTEN42_Msk        (0xc0UL)                  /*!< IRPTEN42 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG42_RDZERO42_Pos        (5UL)                     /*!< RDZERO42 (Bit 5)                                      */
#define GPIO_PINCFG42_RDZERO42_Msk        (0x20UL)                  /*!< RDZERO42 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG42_INPEN42_Pos         (4UL)                     /*!< INPEN42 (Bit 4)                                       */
#define GPIO_PINCFG42_INPEN42_Msk         (0x10UL)                  /*!< INPEN42 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG42_FNCSEL42_Pos        (0UL)                     /*!< FNCSEL42 (Bit 0)                                      */
#define GPIO_PINCFG42_FNCSEL42_Msk        (0xfUL)                   /*!< FNCSEL42 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG43  ======================================================== */
#define GPIO_PINCFG43_FOEN43_Pos          (27UL)                    /*!< FOEN43 (Bit 27)                                       */
#define GPIO_PINCFG43_FOEN43_Msk          (0x8000000UL)             /*!< FOEN43 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG43_FIEN43_Pos          (26UL)                    /*!< FIEN43 (Bit 26)                                       */
#define GPIO_PINCFG43_FIEN43_Msk          (0x4000000UL)             /*!< FIEN43 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG43_NCEPOL43_Pos        (22UL)                    /*!< NCEPOL43 (Bit 22)                                     */
#define GPIO_PINCFG43_NCEPOL43_Msk        (0x400000UL)              /*!< NCEPOL43 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG43_NCESRC43_Pos        (16UL)                    /*!< NCESRC43 (Bit 16)                                     */
#define GPIO_PINCFG43_NCESRC43_Msk        (0x3f0000UL)              /*!< NCESRC43 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG43_PULLCFG43_Pos       (13UL)                    /*!< PULLCFG43 (Bit 13)                                    */
#define GPIO_PINCFG43_PULLCFG43_Msk       (0xe000UL)                /*!< PULLCFG43 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG43_SR43_Pos            (12UL)                    /*!< SR43 (Bit 12)                                         */
#define GPIO_PINCFG43_SR43_Msk            (0x1000UL)                /*!< SR43 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG43_DS43_Pos            (10UL)                    /*!< DS43 (Bit 10)                                         */
#define GPIO_PINCFG43_DS43_Msk            (0xc00UL)                 /*!< DS43 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG43_OUTCFG43_Pos        (8UL)                     /*!< OUTCFG43 (Bit 8)                                      */
#define GPIO_PINCFG43_OUTCFG43_Msk        (0x300UL)                 /*!< OUTCFG43 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG43_IRPTEN43_Pos        (6UL)                     /*!< IRPTEN43 (Bit 6)                                      */
#define GPIO_PINCFG43_IRPTEN43_Msk        (0xc0UL)                  /*!< IRPTEN43 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG43_RDZERO43_Pos        (5UL)                     /*!< RDZERO43 (Bit 5)                                      */
#define GPIO_PINCFG43_RDZERO43_Msk        (0x20UL)                  /*!< RDZERO43 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG43_INPEN43_Pos         (4UL)                     /*!< INPEN43 (Bit 4)                                       */
#define GPIO_PINCFG43_INPEN43_Msk         (0x10UL)                  /*!< INPEN43 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG43_FNCSEL43_Pos        (0UL)                     /*!< FNCSEL43 (Bit 0)                                      */
#define GPIO_PINCFG43_FNCSEL43_Msk        (0xfUL)                   /*!< FNCSEL43 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG44  ======================================================== */
#define GPIO_PINCFG44_FOEN44_Pos          (27UL)                    /*!< FOEN44 (Bit 27)                                       */
#define GPIO_PINCFG44_FOEN44_Msk          (0x8000000UL)             /*!< FOEN44 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG44_FIEN44_Pos          (26UL)                    /*!< FIEN44 (Bit 26)                                       */
#define GPIO_PINCFG44_FIEN44_Msk          (0x4000000UL)             /*!< FIEN44 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG44_NCEPOL44_Pos        (22UL)                    /*!< NCEPOL44 (Bit 22)                                     */
#define GPIO_PINCFG44_NCEPOL44_Msk        (0x400000UL)              /*!< NCEPOL44 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG44_NCESRC44_Pos        (16UL)                    /*!< NCESRC44 (Bit 16)                                     */
#define GPIO_PINCFG44_NCESRC44_Msk        (0x3f0000UL)              /*!< NCESRC44 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG44_PULLCFG44_Pos       (13UL)                    /*!< PULLCFG44 (Bit 13)                                    */
#define GPIO_PINCFG44_PULLCFG44_Msk       (0xe000UL)                /*!< PULLCFG44 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG44_SR44_Pos            (12UL)                    /*!< SR44 (Bit 12)                                         */
#define GPIO_PINCFG44_SR44_Msk            (0x1000UL)                /*!< SR44 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG44_DS44_Pos            (10UL)                    /*!< DS44 (Bit 10)                                         */
#define GPIO_PINCFG44_DS44_Msk            (0xc00UL)                 /*!< DS44 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG44_OUTCFG44_Pos        (8UL)                     /*!< OUTCFG44 (Bit 8)                                      */
#define GPIO_PINCFG44_OUTCFG44_Msk        (0x300UL)                 /*!< OUTCFG44 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG44_IRPTEN44_Pos        (6UL)                     /*!< IRPTEN44 (Bit 6)                                      */
#define GPIO_PINCFG44_IRPTEN44_Msk        (0xc0UL)                  /*!< IRPTEN44 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG44_RDZERO44_Pos        (5UL)                     /*!< RDZERO44 (Bit 5)                                      */
#define GPIO_PINCFG44_RDZERO44_Msk        (0x20UL)                  /*!< RDZERO44 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG44_INPEN44_Pos         (4UL)                     /*!< INPEN44 (Bit 4)                                       */
#define GPIO_PINCFG44_INPEN44_Msk         (0x10UL)                  /*!< INPEN44 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG44_FNCSEL44_Pos        (0UL)                     /*!< FNCSEL44 (Bit 0)                                      */
#define GPIO_PINCFG44_FNCSEL44_Msk        (0xfUL)                   /*!< FNCSEL44 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG45  ======================================================== */
#define GPIO_PINCFG45_FOEN45_Pos          (27UL)                    /*!< FOEN45 (Bit 27)                                       */
#define GPIO_PINCFG45_FOEN45_Msk          (0x8000000UL)             /*!< FOEN45 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG45_FIEN45_Pos          (26UL)                    /*!< FIEN45 (Bit 26)                                       */
#define GPIO_PINCFG45_FIEN45_Msk          (0x4000000UL)             /*!< FIEN45 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG45_NCEPOL45_Pos        (22UL)                    /*!< NCEPOL45 (Bit 22)                                     */
#define GPIO_PINCFG45_NCEPOL45_Msk        (0x400000UL)              /*!< NCEPOL45 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG45_NCESRC45_Pos        (16UL)                    /*!< NCESRC45 (Bit 16)                                     */
#define GPIO_PINCFG45_NCESRC45_Msk        (0x3f0000UL)              /*!< NCESRC45 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG45_PULLCFG45_Pos       (13UL)                    /*!< PULLCFG45 (Bit 13)                                    */
#define GPIO_PINCFG45_PULLCFG45_Msk       (0xe000UL)                /*!< PULLCFG45 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG45_SR45_Pos            (12UL)                    /*!< SR45 (Bit 12)                                         */
#define GPIO_PINCFG45_SR45_Msk            (0x1000UL)                /*!< SR45 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG45_DS45_Pos            (10UL)                    /*!< DS45 (Bit 10)                                         */
#define GPIO_PINCFG45_DS45_Msk            (0xc00UL)                 /*!< DS45 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG45_OUTCFG45_Pos        (8UL)                     /*!< OUTCFG45 (Bit 8)                                      */
#define GPIO_PINCFG45_OUTCFG45_Msk        (0x300UL)                 /*!< OUTCFG45 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG45_IRPTEN45_Pos        (6UL)                     /*!< IRPTEN45 (Bit 6)                                      */
#define GPIO_PINCFG45_IRPTEN45_Msk        (0xc0UL)                  /*!< IRPTEN45 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG45_RDZERO45_Pos        (5UL)                     /*!< RDZERO45 (Bit 5)                                      */
#define GPIO_PINCFG45_RDZERO45_Msk        (0x20UL)                  /*!< RDZERO45 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG45_INPEN45_Pos         (4UL)                     /*!< INPEN45 (Bit 4)                                       */
#define GPIO_PINCFG45_INPEN45_Msk         (0x10UL)                  /*!< INPEN45 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG45_FNCSEL45_Pos        (0UL)                     /*!< FNCSEL45 (Bit 0)                                      */
#define GPIO_PINCFG45_FNCSEL45_Msk        (0xfUL)                   /*!< FNCSEL45 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG46  ======================================================== */
#define GPIO_PINCFG46_FOEN46_Pos          (27UL)                    /*!< FOEN46 (Bit 27)                                       */
#define GPIO_PINCFG46_FOEN46_Msk          (0x8000000UL)             /*!< FOEN46 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG46_FIEN46_Pos          (26UL)                    /*!< FIEN46 (Bit 26)                                       */
#define GPIO_PINCFG46_FIEN46_Msk          (0x4000000UL)             /*!< FIEN46 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG46_NCEPOL46_Pos        (22UL)                    /*!< NCEPOL46 (Bit 22)                                     */
#define GPIO_PINCFG46_NCEPOL46_Msk        (0x400000UL)              /*!< NCEPOL46 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG46_NCESRC46_Pos        (16UL)                    /*!< NCESRC46 (Bit 16)                                     */
#define GPIO_PINCFG46_NCESRC46_Msk        (0x3f0000UL)              /*!< NCESRC46 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG46_PULLCFG46_Pos       (13UL)                    /*!< PULLCFG46 (Bit 13)                                    */
#define GPIO_PINCFG46_PULLCFG46_Msk       (0xe000UL)                /*!< PULLCFG46 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG46_SR46_Pos            (12UL)                    /*!< SR46 (Bit 12)                                         */
#define GPIO_PINCFG46_SR46_Msk            (0x1000UL)                /*!< SR46 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG46_DS46_Pos            (10UL)                    /*!< DS46 (Bit 10)                                         */
#define GPIO_PINCFG46_DS46_Msk            (0xc00UL)                 /*!< DS46 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG46_OUTCFG46_Pos        (8UL)                     /*!< OUTCFG46 (Bit 8)                                      */
#define GPIO_PINCFG46_OUTCFG46_Msk        (0x300UL)                 /*!< OUTCFG46 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG46_IRPTEN46_Pos        (6UL)                     /*!< IRPTEN46 (Bit 6)                                      */
#define GPIO_PINCFG46_IRPTEN46_Msk        (0xc0UL)                  /*!< IRPTEN46 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG46_RDZERO46_Pos        (5UL)                     /*!< RDZERO46 (Bit 5)                                      */
#define GPIO_PINCFG46_RDZERO46_Msk        (0x20UL)                  /*!< RDZERO46 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG46_INPEN46_Pos         (4UL)                     /*!< INPEN46 (Bit 4)                                       */
#define GPIO_PINCFG46_INPEN46_Msk         (0x10UL)                  /*!< INPEN46 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG46_FNCSEL46_Pos        (0UL)                     /*!< FNCSEL46 (Bit 0)                                      */
#define GPIO_PINCFG46_FNCSEL46_Msk        (0xfUL)                   /*!< FNCSEL46 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG47  ======================================================== */
#define GPIO_PINCFG47_FOEN47_Pos          (27UL)                    /*!< FOEN47 (Bit 27)                                       */
#define GPIO_PINCFG47_FOEN47_Msk          (0x8000000UL)             /*!< FOEN47 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG47_FIEN47_Pos          (26UL)                    /*!< FIEN47 (Bit 26)                                       */
#define GPIO_PINCFG47_FIEN47_Msk          (0x4000000UL)             /*!< FIEN47 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG47_NCEPOL47_Pos        (22UL)                    /*!< NCEPOL47 (Bit 22)                                     */
#define GPIO_PINCFG47_NCEPOL47_Msk        (0x400000UL)              /*!< NCEPOL47 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG47_NCESRC47_Pos        (16UL)                    /*!< NCESRC47 (Bit 16)                                     */
#define GPIO_PINCFG47_NCESRC47_Msk        (0x3f0000UL)              /*!< NCESRC47 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG47_PULLCFG47_Pos       (13UL)                    /*!< PULLCFG47 (Bit 13)                                    */
#define GPIO_PINCFG47_PULLCFG47_Msk       (0xe000UL)                /*!< PULLCFG47 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG47_SR47_Pos            (12UL)                    /*!< SR47 (Bit 12)                                         */
#define GPIO_PINCFG47_SR47_Msk            (0x1000UL)                /*!< SR47 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG47_DS47_Pos            (10UL)                    /*!< DS47 (Bit 10)                                         */
#define GPIO_PINCFG47_DS47_Msk            (0xc00UL)                 /*!< DS47 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG47_OUTCFG47_Pos        (8UL)                     /*!< OUTCFG47 (Bit 8)                                      */
#define GPIO_PINCFG47_OUTCFG47_Msk        (0x300UL)                 /*!< OUTCFG47 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG47_IRPTEN47_Pos        (6UL)                     /*!< IRPTEN47 (Bit 6)                                      */
#define GPIO_PINCFG47_IRPTEN47_Msk        (0xc0UL)                  /*!< IRPTEN47 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG47_RDZERO47_Pos        (5UL)                     /*!< RDZERO47 (Bit 5)                                      */
#define GPIO_PINCFG47_RDZERO47_Msk        (0x20UL)                  /*!< RDZERO47 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG47_INPEN47_Pos         (4UL)                     /*!< INPEN47 (Bit 4)                                       */
#define GPIO_PINCFG47_INPEN47_Msk         (0x10UL)                  /*!< INPEN47 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG47_FNCSEL47_Pos        (0UL)                     /*!< FNCSEL47 (Bit 0)                                      */
#define GPIO_PINCFG47_FNCSEL47_Msk        (0xfUL)                   /*!< FNCSEL47 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG48  ======================================================== */
#define GPIO_PINCFG48_FOEN48_Pos          (27UL)                    /*!< FOEN48 (Bit 27)                                       */
#define GPIO_PINCFG48_FOEN48_Msk          (0x8000000UL)             /*!< FOEN48 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG48_FIEN48_Pos          (26UL)                    /*!< FIEN48 (Bit 26)                                       */
#define GPIO_PINCFG48_FIEN48_Msk          (0x4000000UL)             /*!< FIEN48 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG48_NCEPOL48_Pos        (22UL)                    /*!< NCEPOL48 (Bit 22)                                     */
#define GPIO_PINCFG48_NCEPOL48_Msk        (0x400000UL)              /*!< NCEPOL48 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG48_NCESRC48_Pos        (16UL)                    /*!< NCESRC48 (Bit 16)                                     */
#define GPIO_PINCFG48_NCESRC48_Msk        (0x3f0000UL)              /*!< NCESRC48 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG48_PULLCFG48_Pos       (13UL)                    /*!< PULLCFG48 (Bit 13)                                    */
#define GPIO_PINCFG48_PULLCFG48_Msk       (0xe000UL)                /*!< PULLCFG48 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG48_SR48_Pos            (12UL)                    /*!< SR48 (Bit 12)                                         */
#define GPIO_PINCFG48_SR48_Msk            (0x1000UL)                /*!< SR48 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG48_DS48_Pos            (10UL)                    /*!< DS48 (Bit 10)                                         */
#define GPIO_PINCFG48_DS48_Msk            (0xc00UL)                 /*!< DS48 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG48_OUTCFG48_Pos        (8UL)                     /*!< OUTCFG48 (Bit 8)                                      */
#define GPIO_PINCFG48_OUTCFG48_Msk        (0x300UL)                 /*!< OUTCFG48 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG48_IRPTEN48_Pos        (6UL)                     /*!< IRPTEN48 (Bit 6)                                      */
#define GPIO_PINCFG48_IRPTEN48_Msk        (0xc0UL)                  /*!< IRPTEN48 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG48_RDZERO48_Pos        (5UL)                     /*!< RDZERO48 (Bit 5)                                      */
#define GPIO_PINCFG48_RDZERO48_Msk        (0x20UL)                  /*!< RDZERO48 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG48_INPEN48_Pos         (4UL)                     /*!< INPEN48 (Bit 4)                                       */
#define GPIO_PINCFG48_INPEN48_Msk         (0x10UL)                  /*!< INPEN48 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG48_FNCSEL48_Pos        (0UL)                     /*!< FNCSEL48 (Bit 0)                                      */
#define GPIO_PINCFG48_FNCSEL48_Msk        (0xfUL)                   /*!< FNCSEL48 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG49  ======================================================== */
#define GPIO_PINCFG49_FOEN49_Pos          (27UL)                    /*!< FOEN49 (Bit 27)                                       */
#define GPIO_PINCFG49_FOEN49_Msk          (0x8000000UL)             /*!< FOEN49 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG49_FIEN49_Pos          (26UL)                    /*!< FIEN49 (Bit 26)                                       */
#define GPIO_PINCFG49_FIEN49_Msk          (0x4000000UL)             /*!< FIEN49 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG49_NCEPOL49_Pos        (22UL)                    /*!< NCEPOL49 (Bit 22)                                     */
#define GPIO_PINCFG49_NCEPOL49_Msk        (0x400000UL)              /*!< NCEPOL49 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG49_NCESRC49_Pos        (16UL)                    /*!< NCESRC49 (Bit 16)                                     */
#define GPIO_PINCFG49_NCESRC49_Msk        (0x3f0000UL)              /*!< NCESRC49 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG49_PULLCFG49_Pos       (13UL)                    /*!< PULLCFG49 (Bit 13)                                    */
#define GPIO_PINCFG49_PULLCFG49_Msk       (0xe000UL)                /*!< PULLCFG49 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG49_SR49_Pos            (12UL)                    /*!< SR49 (Bit 12)                                         */
#define GPIO_PINCFG49_SR49_Msk            (0x1000UL)                /*!< SR49 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG49_DS49_Pos            (10UL)                    /*!< DS49 (Bit 10)                                         */
#define GPIO_PINCFG49_DS49_Msk            (0xc00UL)                 /*!< DS49 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG49_OUTCFG49_Pos        (8UL)                     /*!< OUTCFG49 (Bit 8)                                      */
#define GPIO_PINCFG49_OUTCFG49_Msk        (0x300UL)                 /*!< OUTCFG49 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG49_IRPTEN49_Pos        (6UL)                     /*!< IRPTEN49 (Bit 6)                                      */
#define GPIO_PINCFG49_IRPTEN49_Msk        (0xc0UL)                  /*!< IRPTEN49 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG49_RDZERO49_Pos        (5UL)                     /*!< RDZERO49 (Bit 5)                                      */
#define GPIO_PINCFG49_RDZERO49_Msk        (0x20UL)                  /*!< RDZERO49 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG49_INPEN49_Pos         (4UL)                     /*!< INPEN49 (Bit 4)                                       */
#define GPIO_PINCFG49_INPEN49_Msk         (0x10UL)                  /*!< INPEN49 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG49_FNCSEL49_Pos        (0UL)                     /*!< FNCSEL49 (Bit 0)                                      */
#define GPIO_PINCFG49_FNCSEL49_Msk        (0xfUL)                   /*!< FNCSEL49 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG50  ======================================================== */
#define GPIO_PINCFG50_FOEN50_Pos          (27UL)                    /*!< FOEN50 (Bit 27)                                       */
#define GPIO_PINCFG50_FOEN50_Msk          (0x8000000UL)             /*!< FOEN50 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG50_FIEN50_Pos          (26UL)                    /*!< FIEN50 (Bit 26)                                       */
#define GPIO_PINCFG50_FIEN50_Msk          (0x4000000UL)             /*!< FIEN50 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG50_NCEPOL50_Pos        (22UL)                    /*!< NCEPOL50 (Bit 22)                                     */
#define GPIO_PINCFG50_NCEPOL50_Msk        (0x400000UL)              /*!< NCEPOL50 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG50_NCESRC50_Pos        (16UL)                    /*!< NCESRC50 (Bit 16)                                     */
#define GPIO_PINCFG50_NCESRC50_Msk        (0x3f0000UL)              /*!< NCESRC50 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG50_PULLCFG50_Pos       (13UL)                    /*!< PULLCFG50 (Bit 13)                                    */
#define GPIO_PINCFG50_PULLCFG50_Msk       (0xe000UL)                /*!< PULLCFG50 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG50_SR50_Pos            (12UL)                    /*!< SR50 (Bit 12)                                         */
#define GPIO_PINCFG50_SR50_Msk            (0x1000UL)                /*!< SR50 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG50_DS50_Pos            (10UL)                    /*!< DS50 (Bit 10)                                         */
#define GPIO_PINCFG50_DS50_Msk            (0xc00UL)                 /*!< DS50 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG50_OUTCFG50_Pos        (8UL)                     /*!< OUTCFG50 (Bit 8)                                      */
#define GPIO_PINCFG50_OUTCFG50_Msk        (0x300UL)                 /*!< OUTCFG50 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG50_IRPTEN50_Pos        (6UL)                     /*!< IRPTEN50 (Bit 6)                                      */
#define GPIO_PINCFG50_IRPTEN50_Msk        (0xc0UL)                  /*!< IRPTEN50 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG50_RDZERO50_Pos        (5UL)                     /*!< RDZERO50 (Bit 5)                                      */
#define GPIO_PINCFG50_RDZERO50_Msk        (0x20UL)                  /*!< RDZERO50 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG50_INPEN50_Pos         (4UL)                     /*!< INPEN50 (Bit 4)                                       */
#define GPIO_PINCFG50_INPEN50_Msk         (0x10UL)                  /*!< INPEN50 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG50_FNCSEL50_Pos        (0UL)                     /*!< FNCSEL50 (Bit 0)                                      */
#define GPIO_PINCFG50_FNCSEL50_Msk        (0xfUL)                   /*!< FNCSEL50 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG51  ======================================================== */
#define GPIO_PINCFG51_FOEN51_Pos          (27UL)                    /*!< FOEN51 (Bit 27)                                       */
#define GPIO_PINCFG51_FOEN51_Msk          (0x8000000UL)             /*!< FOEN51 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG51_FIEN51_Pos          (26UL)                    /*!< FIEN51 (Bit 26)                                       */
#define GPIO_PINCFG51_FIEN51_Msk          (0x4000000UL)             /*!< FIEN51 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG51_NCEPOL51_Pos        (22UL)                    /*!< NCEPOL51 (Bit 22)                                     */
#define GPIO_PINCFG51_NCEPOL51_Msk        (0x400000UL)              /*!< NCEPOL51 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG51_NCESRC51_Pos        (16UL)                    /*!< NCESRC51 (Bit 16)                                     */
#define GPIO_PINCFG51_NCESRC51_Msk        (0x3f0000UL)              /*!< NCESRC51 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG51_PULLCFG51_Pos       (13UL)                    /*!< PULLCFG51 (Bit 13)                                    */
#define GPIO_PINCFG51_PULLCFG51_Msk       (0xe000UL)                /*!< PULLCFG51 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG51_SR51_Pos            (12UL)                    /*!< SR51 (Bit 12)                                         */
#define GPIO_PINCFG51_SR51_Msk            (0x1000UL)                /*!< SR51 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG51_DS51_Pos            (10UL)                    /*!< DS51 (Bit 10)                                         */
#define GPIO_PINCFG51_DS51_Msk            (0xc00UL)                 /*!< DS51 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG51_OUTCFG51_Pos        (8UL)                     /*!< OUTCFG51 (Bit 8)                                      */
#define GPIO_PINCFG51_OUTCFG51_Msk        (0x300UL)                 /*!< OUTCFG51 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG51_IRPTEN51_Pos        (6UL)                     /*!< IRPTEN51 (Bit 6)                                      */
#define GPIO_PINCFG51_IRPTEN51_Msk        (0xc0UL)                  /*!< IRPTEN51 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG51_RDZERO51_Pos        (5UL)                     /*!< RDZERO51 (Bit 5)                                      */
#define GPIO_PINCFG51_RDZERO51_Msk        (0x20UL)                  /*!< RDZERO51 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG51_INPEN51_Pos         (4UL)                     /*!< INPEN51 (Bit 4)                                       */
#define GPIO_PINCFG51_INPEN51_Msk         (0x10UL)                  /*!< INPEN51 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG51_FNCSEL51_Pos        (0UL)                     /*!< FNCSEL51 (Bit 0)                                      */
#define GPIO_PINCFG51_FNCSEL51_Msk        (0xfUL)                   /*!< FNCSEL51 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG52  ======================================================== */
#define GPIO_PINCFG52_FOEN52_Pos          (27UL)                    /*!< FOEN52 (Bit 27)                                       */
#define GPIO_PINCFG52_FOEN52_Msk          (0x8000000UL)             /*!< FOEN52 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG52_FIEN52_Pos          (26UL)                    /*!< FIEN52 (Bit 26)                                       */
#define GPIO_PINCFG52_FIEN52_Msk          (0x4000000UL)             /*!< FIEN52 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG52_NCEPOL52_Pos        (22UL)                    /*!< NCEPOL52 (Bit 22)                                     */
#define GPIO_PINCFG52_NCEPOL52_Msk        (0x400000UL)              /*!< NCEPOL52 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG52_NCESRC52_Pos        (16UL)                    /*!< NCESRC52 (Bit 16)                                     */
#define GPIO_PINCFG52_NCESRC52_Msk        (0x3f0000UL)              /*!< NCESRC52 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG52_PULLCFG52_Pos       (13UL)                    /*!< PULLCFG52 (Bit 13)                                    */
#define GPIO_PINCFG52_PULLCFG52_Msk       (0xe000UL)                /*!< PULLCFG52 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG52_SR52_Pos            (12UL)                    /*!< SR52 (Bit 12)                                         */
#define GPIO_PINCFG52_SR52_Msk            (0x1000UL)                /*!< SR52 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG52_DS52_Pos            (10UL)                    /*!< DS52 (Bit 10)                                         */
#define GPIO_PINCFG52_DS52_Msk            (0xc00UL)                 /*!< DS52 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG52_OUTCFG52_Pos        (8UL)                     /*!< OUTCFG52 (Bit 8)                                      */
#define GPIO_PINCFG52_OUTCFG52_Msk        (0x300UL)                 /*!< OUTCFG52 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG52_IRPTEN52_Pos        (6UL)                     /*!< IRPTEN52 (Bit 6)                                      */
#define GPIO_PINCFG52_IRPTEN52_Msk        (0xc0UL)                  /*!< IRPTEN52 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG52_RDZERO52_Pos        (5UL)                     /*!< RDZERO52 (Bit 5)                                      */
#define GPIO_PINCFG52_RDZERO52_Msk        (0x20UL)                  /*!< RDZERO52 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG52_INPEN52_Pos         (4UL)                     /*!< INPEN52 (Bit 4)                                       */
#define GPIO_PINCFG52_INPEN52_Msk         (0x10UL)                  /*!< INPEN52 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG52_FNCSEL52_Pos        (0UL)                     /*!< FNCSEL52 (Bit 0)                                      */
#define GPIO_PINCFG52_FNCSEL52_Msk        (0xfUL)                   /*!< FNCSEL52 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG53  ======================================================== */
#define GPIO_PINCFG53_FOEN53_Pos          (27UL)                    /*!< FOEN53 (Bit 27)                                       */
#define GPIO_PINCFG53_FOEN53_Msk          (0x8000000UL)             /*!< FOEN53 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG53_FIEN53_Pos          (26UL)                    /*!< FIEN53 (Bit 26)                                       */
#define GPIO_PINCFG53_FIEN53_Msk          (0x4000000UL)             /*!< FIEN53 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG53_NCEPOL53_Pos        (22UL)                    /*!< NCEPOL53 (Bit 22)                                     */
#define GPIO_PINCFG53_NCEPOL53_Msk        (0x400000UL)              /*!< NCEPOL53 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG53_NCESRC53_Pos        (16UL)                    /*!< NCESRC53 (Bit 16)                                     */
#define GPIO_PINCFG53_NCESRC53_Msk        (0x3f0000UL)              /*!< NCESRC53 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG53_PULLCFG53_Pos       (13UL)                    /*!< PULLCFG53 (Bit 13)                                    */
#define GPIO_PINCFG53_PULLCFG53_Msk       (0xe000UL)                /*!< PULLCFG53 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG53_SR53_Pos            (12UL)                    /*!< SR53 (Bit 12)                                         */
#define GPIO_PINCFG53_SR53_Msk            (0x1000UL)                /*!< SR53 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG53_DS53_Pos            (10UL)                    /*!< DS53 (Bit 10)                                         */
#define GPIO_PINCFG53_DS53_Msk            (0xc00UL)                 /*!< DS53 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG53_OUTCFG53_Pos        (8UL)                     /*!< OUTCFG53 (Bit 8)                                      */
#define GPIO_PINCFG53_OUTCFG53_Msk        (0x300UL)                 /*!< OUTCFG53 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG53_IRPTEN53_Pos        (6UL)                     /*!< IRPTEN53 (Bit 6)                                      */
#define GPIO_PINCFG53_IRPTEN53_Msk        (0xc0UL)                  /*!< IRPTEN53 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG53_RDZERO53_Pos        (5UL)                     /*!< RDZERO53 (Bit 5)                                      */
#define GPIO_PINCFG53_RDZERO53_Msk        (0x20UL)                  /*!< RDZERO53 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG53_INPEN53_Pos         (4UL)                     /*!< INPEN53 (Bit 4)                                       */
#define GPIO_PINCFG53_INPEN53_Msk         (0x10UL)                  /*!< INPEN53 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG53_FNCSEL53_Pos        (0UL)                     /*!< FNCSEL53 (Bit 0)                                      */
#define GPIO_PINCFG53_FNCSEL53_Msk        (0xfUL)                   /*!< FNCSEL53 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG54  ======================================================== */
#define GPIO_PINCFG54_FOEN54_Pos          (27UL)                    /*!< FOEN54 (Bit 27)                                       */
#define GPIO_PINCFG54_FOEN54_Msk          (0x8000000UL)             /*!< FOEN54 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG54_FIEN54_Pos          (26UL)                    /*!< FIEN54 (Bit 26)                                       */
#define GPIO_PINCFG54_FIEN54_Msk          (0x4000000UL)             /*!< FIEN54 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG54_NCEPOL54_Pos        (22UL)                    /*!< NCEPOL54 (Bit 22)                                     */
#define GPIO_PINCFG54_NCEPOL54_Msk        (0x400000UL)              /*!< NCEPOL54 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG54_NCESRC54_Pos        (16UL)                    /*!< NCESRC54 (Bit 16)                                     */
#define GPIO_PINCFG54_NCESRC54_Msk        (0x3f0000UL)              /*!< NCESRC54 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG54_PULLCFG54_Pos       (13UL)                    /*!< PULLCFG54 (Bit 13)                                    */
#define GPIO_PINCFG54_PULLCFG54_Msk       (0xe000UL)                /*!< PULLCFG54 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG54_SR54_Pos            (12UL)                    /*!< SR54 (Bit 12)                                         */
#define GPIO_PINCFG54_SR54_Msk            (0x1000UL)                /*!< SR54 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG54_DS54_Pos            (10UL)                    /*!< DS54 (Bit 10)                                         */
#define GPIO_PINCFG54_DS54_Msk            (0xc00UL)                 /*!< DS54 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG54_OUTCFG54_Pos        (8UL)                     /*!< OUTCFG54 (Bit 8)                                      */
#define GPIO_PINCFG54_OUTCFG54_Msk        (0x300UL)                 /*!< OUTCFG54 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG54_IRPTEN54_Pos        (6UL)                     /*!< IRPTEN54 (Bit 6)                                      */
#define GPIO_PINCFG54_IRPTEN54_Msk        (0xc0UL)                  /*!< IRPTEN54 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG54_RDZERO54_Pos        (5UL)                     /*!< RDZERO54 (Bit 5)                                      */
#define GPIO_PINCFG54_RDZERO54_Msk        (0x20UL)                  /*!< RDZERO54 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG54_INPEN54_Pos         (4UL)                     /*!< INPEN54 (Bit 4)                                       */
#define GPIO_PINCFG54_INPEN54_Msk         (0x10UL)                  /*!< INPEN54 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG54_FNCSEL54_Pos        (0UL)                     /*!< FNCSEL54 (Bit 0)                                      */
#define GPIO_PINCFG54_FNCSEL54_Msk        (0xfUL)                   /*!< FNCSEL54 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG55  ======================================================== */
#define GPIO_PINCFG55_FOEN55_Pos          (27UL)                    /*!< FOEN55 (Bit 27)                                       */
#define GPIO_PINCFG55_FOEN55_Msk          (0x8000000UL)             /*!< FOEN55 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG55_FIEN55_Pos          (26UL)                    /*!< FIEN55 (Bit 26)                                       */
#define GPIO_PINCFG55_FIEN55_Msk          (0x4000000UL)             /*!< FIEN55 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG55_NCEPOL55_Pos        (22UL)                    /*!< NCEPOL55 (Bit 22)                                     */
#define GPIO_PINCFG55_NCEPOL55_Msk        (0x400000UL)              /*!< NCEPOL55 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG55_NCESRC55_Pos        (16UL)                    /*!< NCESRC55 (Bit 16)                                     */
#define GPIO_PINCFG55_NCESRC55_Msk        (0x3f0000UL)              /*!< NCESRC55 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG55_PULLCFG55_Pos       (13UL)                    /*!< PULLCFG55 (Bit 13)                                    */
#define GPIO_PINCFG55_PULLCFG55_Msk       (0xe000UL)                /*!< PULLCFG55 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG55_SR55_Pos            (12UL)                    /*!< SR55 (Bit 12)                                         */
#define GPIO_PINCFG55_SR55_Msk            (0x1000UL)                /*!< SR55 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG55_DS55_Pos            (10UL)                    /*!< DS55 (Bit 10)                                         */
#define GPIO_PINCFG55_DS55_Msk            (0xc00UL)                 /*!< DS55 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG55_OUTCFG55_Pos        (8UL)                     /*!< OUTCFG55 (Bit 8)                                      */
#define GPIO_PINCFG55_OUTCFG55_Msk        (0x300UL)                 /*!< OUTCFG55 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG55_IRPTEN55_Pos        (6UL)                     /*!< IRPTEN55 (Bit 6)                                      */
#define GPIO_PINCFG55_IRPTEN55_Msk        (0xc0UL)                  /*!< IRPTEN55 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG55_RDZERO55_Pos        (5UL)                     /*!< RDZERO55 (Bit 5)                                      */
#define GPIO_PINCFG55_RDZERO55_Msk        (0x20UL)                  /*!< RDZERO55 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG55_INPEN55_Pos         (4UL)                     /*!< INPEN55 (Bit 4)                                       */
#define GPIO_PINCFG55_INPEN55_Msk         (0x10UL)                  /*!< INPEN55 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG55_FNCSEL55_Pos        (0UL)                     /*!< FNCSEL55 (Bit 0)                                      */
#define GPIO_PINCFG55_FNCSEL55_Msk        (0xfUL)                   /*!< FNCSEL55 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG56  ======================================================== */
#define GPIO_PINCFG56_FOEN56_Pos          (27UL)                    /*!< FOEN56 (Bit 27)                                       */
#define GPIO_PINCFG56_FOEN56_Msk          (0x8000000UL)             /*!< FOEN56 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG56_FIEN56_Pos          (26UL)                    /*!< FIEN56 (Bit 26)                                       */
#define GPIO_PINCFG56_FIEN56_Msk          (0x4000000UL)             /*!< FIEN56 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG56_NCEPOL56_Pos        (22UL)                    /*!< NCEPOL56 (Bit 22)                                     */
#define GPIO_PINCFG56_NCEPOL56_Msk        (0x400000UL)              /*!< NCEPOL56 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG56_NCESRC56_Pos        (16UL)                    /*!< NCESRC56 (Bit 16)                                     */
#define GPIO_PINCFG56_NCESRC56_Msk        (0x3f0000UL)              /*!< NCESRC56 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG56_PULLCFG56_Pos       (13UL)                    /*!< PULLCFG56 (Bit 13)                                    */
#define GPIO_PINCFG56_PULLCFG56_Msk       (0xe000UL)                /*!< PULLCFG56 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG56_SR56_Pos            (12UL)                    /*!< SR56 (Bit 12)                                         */
#define GPIO_PINCFG56_SR56_Msk            (0x1000UL)                /*!< SR56 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG56_DS56_Pos            (10UL)                    /*!< DS56 (Bit 10)                                         */
#define GPIO_PINCFG56_DS56_Msk            (0xc00UL)                 /*!< DS56 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG56_OUTCFG56_Pos        (8UL)                     /*!< OUTCFG56 (Bit 8)                                      */
#define GPIO_PINCFG56_OUTCFG56_Msk        (0x300UL)                 /*!< OUTCFG56 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG56_IRPTEN56_Pos        (6UL)                     /*!< IRPTEN56 (Bit 6)                                      */
#define GPIO_PINCFG56_IRPTEN56_Msk        (0xc0UL)                  /*!< IRPTEN56 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG56_RDZERO56_Pos        (5UL)                     /*!< RDZERO56 (Bit 5)                                      */
#define GPIO_PINCFG56_RDZERO56_Msk        (0x20UL)                  /*!< RDZERO56 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG56_INPEN56_Pos         (4UL)                     /*!< INPEN56 (Bit 4)                                       */
#define GPIO_PINCFG56_INPEN56_Msk         (0x10UL)                  /*!< INPEN56 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG56_FNCSEL56_Pos        (0UL)                     /*!< FNCSEL56 (Bit 0)                                      */
#define GPIO_PINCFG56_FNCSEL56_Msk        (0xfUL)                   /*!< FNCSEL56 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG57  ======================================================== */
#define GPIO_PINCFG57_FOEN57_Pos          (27UL)                    /*!< FOEN57 (Bit 27)                                       */
#define GPIO_PINCFG57_FOEN57_Msk          (0x8000000UL)             /*!< FOEN57 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG57_FIEN57_Pos          (26UL)                    /*!< FIEN57 (Bit 26)                                       */
#define GPIO_PINCFG57_FIEN57_Msk          (0x4000000UL)             /*!< FIEN57 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG57_NCEPOL57_Pos        (22UL)                    /*!< NCEPOL57 (Bit 22)                                     */
#define GPIO_PINCFG57_NCEPOL57_Msk        (0x400000UL)              /*!< NCEPOL57 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG57_NCESRC57_Pos        (16UL)                    /*!< NCESRC57 (Bit 16)                                     */
#define GPIO_PINCFG57_NCESRC57_Msk        (0x3f0000UL)              /*!< NCESRC57 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG57_PULLCFG57_Pos       (13UL)                    /*!< PULLCFG57 (Bit 13)                                    */
#define GPIO_PINCFG57_PULLCFG57_Msk       (0xe000UL)                /*!< PULLCFG57 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG57_SR57_Pos            (12UL)                    /*!< SR57 (Bit 12)                                         */
#define GPIO_PINCFG57_SR57_Msk            (0x1000UL)                /*!< SR57 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG57_DS57_Pos            (10UL)                    /*!< DS57 (Bit 10)                                         */
#define GPIO_PINCFG57_DS57_Msk            (0xc00UL)                 /*!< DS57 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG57_OUTCFG57_Pos        (8UL)                     /*!< OUTCFG57 (Bit 8)                                      */
#define GPIO_PINCFG57_OUTCFG57_Msk        (0x300UL)                 /*!< OUTCFG57 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG57_IRPTEN57_Pos        (6UL)                     /*!< IRPTEN57 (Bit 6)                                      */
#define GPIO_PINCFG57_IRPTEN57_Msk        (0xc0UL)                  /*!< IRPTEN57 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG57_RDZERO57_Pos        (5UL)                     /*!< RDZERO57 (Bit 5)                                      */
#define GPIO_PINCFG57_RDZERO57_Msk        (0x20UL)                  /*!< RDZERO57 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG57_INPEN57_Pos         (4UL)                     /*!< INPEN57 (Bit 4)                                       */
#define GPIO_PINCFG57_INPEN57_Msk         (0x10UL)                  /*!< INPEN57 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG57_FNCSEL57_Pos        (0UL)                     /*!< FNCSEL57 (Bit 0)                                      */
#define GPIO_PINCFG57_FNCSEL57_Msk        (0xfUL)                   /*!< FNCSEL57 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG58  ======================================================== */
#define GPIO_PINCFG58_FOEN58_Pos          (27UL)                    /*!< FOEN58 (Bit 27)                                       */
#define GPIO_PINCFG58_FOEN58_Msk          (0x8000000UL)             /*!< FOEN58 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG58_FIEN58_Pos          (26UL)                    /*!< FIEN58 (Bit 26)                                       */
#define GPIO_PINCFG58_FIEN58_Msk          (0x4000000UL)             /*!< FIEN58 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG58_NCEPOL58_Pos        (22UL)                    /*!< NCEPOL58 (Bit 22)                                     */
#define GPIO_PINCFG58_NCEPOL58_Msk        (0x400000UL)              /*!< NCEPOL58 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG58_NCESRC58_Pos        (16UL)                    /*!< NCESRC58 (Bit 16)                                     */
#define GPIO_PINCFG58_NCESRC58_Msk        (0x3f0000UL)              /*!< NCESRC58 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG58_PULLCFG58_Pos       (13UL)                    /*!< PULLCFG58 (Bit 13)                                    */
#define GPIO_PINCFG58_PULLCFG58_Msk       (0xe000UL)                /*!< PULLCFG58 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG58_SR58_Pos            (12UL)                    /*!< SR58 (Bit 12)                                         */
#define GPIO_PINCFG58_SR58_Msk            (0x1000UL)                /*!< SR58 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG58_DS58_Pos            (10UL)                    /*!< DS58 (Bit 10)                                         */
#define GPIO_PINCFG58_DS58_Msk            (0xc00UL)                 /*!< DS58 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG58_OUTCFG58_Pos        (8UL)                     /*!< OUTCFG58 (Bit 8)                                      */
#define GPIO_PINCFG58_OUTCFG58_Msk        (0x300UL)                 /*!< OUTCFG58 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG58_IRPTEN58_Pos        (6UL)                     /*!< IRPTEN58 (Bit 6)                                      */
#define GPIO_PINCFG58_IRPTEN58_Msk        (0xc0UL)                  /*!< IRPTEN58 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG58_RDZERO58_Pos        (5UL)                     /*!< RDZERO58 (Bit 5)                                      */
#define GPIO_PINCFG58_RDZERO58_Msk        (0x20UL)                  /*!< RDZERO58 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG58_INPEN58_Pos         (4UL)                     /*!< INPEN58 (Bit 4)                                       */
#define GPIO_PINCFG58_INPEN58_Msk         (0x10UL)                  /*!< INPEN58 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG58_FNCSEL58_Pos        (0UL)                     /*!< FNCSEL58 (Bit 0)                                      */
#define GPIO_PINCFG58_FNCSEL58_Msk        (0xfUL)                   /*!< FNCSEL58 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG59  ======================================================== */
#define GPIO_PINCFG59_FOEN59_Pos          (27UL)                    /*!< FOEN59 (Bit 27)                                       */
#define GPIO_PINCFG59_FOEN59_Msk          (0x8000000UL)             /*!< FOEN59 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG59_FIEN59_Pos          (26UL)                    /*!< FIEN59 (Bit 26)                                       */
#define GPIO_PINCFG59_FIEN59_Msk          (0x4000000UL)             /*!< FIEN59 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG59_NCEPOL59_Pos        (22UL)                    /*!< NCEPOL59 (Bit 22)                                     */
#define GPIO_PINCFG59_NCEPOL59_Msk        (0x400000UL)              /*!< NCEPOL59 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG59_NCESRC59_Pos        (16UL)                    /*!< NCESRC59 (Bit 16)                                     */
#define GPIO_PINCFG59_NCESRC59_Msk        (0x3f0000UL)              /*!< NCESRC59 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG59_PULLCFG59_Pos       (13UL)                    /*!< PULLCFG59 (Bit 13)                                    */
#define GPIO_PINCFG59_PULLCFG59_Msk       (0xe000UL)                /*!< PULLCFG59 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG59_SR59_Pos            (12UL)                    /*!< SR59 (Bit 12)                                         */
#define GPIO_PINCFG59_SR59_Msk            (0x1000UL)                /*!< SR59 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG59_DS59_Pos            (10UL)                    /*!< DS59 (Bit 10)                                         */
#define GPIO_PINCFG59_DS59_Msk            (0xc00UL)                 /*!< DS59 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG59_OUTCFG59_Pos        (8UL)                     /*!< OUTCFG59 (Bit 8)                                      */
#define GPIO_PINCFG59_OUTCFG59_Msk        (0x300UL)                 /*!< OUTCFG59 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG59_IRPTEN59_Pos        (6UL)                     /*!< IRPTEN59 (Bit 6)                                      */
#define GPIO_PINCFG59_IRPTEN59_Msk        (0xc0UL)                  /*!< IRPTEN59 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG59_RDZERO59_Pos        (5UL)                     /*!< RDZERO59 (Bit 5)                                      */
#define GPIO_PINCFG59_RDZERO59_Msk        (0x20UL)                  /*!< RDZERO59 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG59_INPEN59_Pos         (4UL)                     /*!< INPEN59 (Bit 4)                                       */
#define GPIO_PINCFG59_INPEN59_Msk         (0x10UL)                  /*!< INPEN59 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG59_FNCSEL59_Pos        (0UL)                     /*!< FNCSEL59 (Bit 0)                                      */
#define GPIO_PINCFG59_FNCSEL59_Msk        (0xfUL)                   /*!< FNCSEL59 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG60  ======================================================== */
#define GPIO_PINCFG60_FOEN60_Pos          (27UL)                    /*!< FOEN60 (Bit 27)                                       */
#define GPIO_PINCFG60_FOEN60_Msk          (0x8000000UL)             /*!< FOEN60 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG60_FIEN60_Pos          (26UL)                    /*!< FIEN60 (Bit 26)                                       */
#define GPIO_PINCFG60_FIEN60_Msk          (0x4000000UL)             /*!< FIEN60 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG60_NCEPOL60_Pos        (22UL)                    /*!< NCEPOL60 (Bit 22)                                     */
#define GPIO_PINCFG60_NCEPOL60_Msk        (0x400000UL)              /*!< NCEPOL60 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG60_NCESRC60_Pos        (16UL)                    /*!< NCESRC60 (Bit 16)                                     */
#define GPIO_PINCFG60_NCESRC60_Msk        (0x3f0000UL)              /*!< NCESRC60 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG60_PULLCFG60_Pos       (13UL)                    /*!< PULLCFG60 (Bit 13)                                    */
#define GPIO_PINCFG60_PULLCFG60_Msk       (0xe000UL)                /*!< PULLCFG60 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG60_SR60_Pos            (12UL)                    /*!< SR60 (Bit 12)                                         */
#define GPIO_PINCFG60_SR60_Msk            (0x1000UL)                /*!< SR60 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG60_DS60_Pos            (10UL)                    /*!< DS60 (Bit 10)                                         */
#define GPIO_PINCFG60_DS60_Msk            (0xc00UL)                 /*!< DS60 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG60_OUTCFG60_Pos        (8UL)                     /*!< OUTCFG60 (Bit 8)                                      */
#define GPIO_PINCFG60_OUTCFG60_Msk        (0x300UL)                 /*!< OUTCFG60 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG60_IRPTEN60_Pos        (6UL)                     /*!< IRPTEN60 (Bit 6)                                      */
#define GPIO_PINCFG60_IRPTEN60_Msk        (0xc0UL)                  /*!< IRPTEN60 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG60_RDZERO60_Pos        (5UL)                     /*!< RDZERO60 (Bit 5)                                      */
#define GPIO_PINCFG60_RDZERO60_Msk        (0x20UL)                  /*!< RDZERO60 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG60_INPEN60_Pos         (4UL)                     /*!< INPEN60 (Bit 4)                                       */
#define GPIO_PINCFG60_INPEN60_Msk         (0x10UL)                  /*!< INPEN60 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG60_FNCSEL60_Pos        (0UL)                     /*!< FNCSEL60 (Bit 0)                                      */
#define GPIO_PINCFG60_FNCSEL60_Msk        (0xfUL)                   /*!< FNCSEL60 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG61  ======================================================== */
#define GPIO_PINCFG61_FOEN61_Pos          (27UL)                    /*!< FOEN61 (Bit 27)                                       */
#define GPIO_PINCFG61_FOEN61_Msk          (0x8000000UL)             /*!< FOEN61 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG61_FIEN61_Pos          (26UL)                    /*!< FIEN61 (Bit 26)                                       */
#define GPIO_PINCFG61_FIEN61_Msk          (0x4000000UL)             /*!< FIEN61 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG61_NCEPOL61_Pos        (22UL)                    /*!< NCEPOL61 (Bit 22)                                     */
#define GPIO_PINCFG61_NCEPOL61_Msk        (0x400000UL)              /*!< NCEPOL61 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG61_NCESRC61_Pos        (16UL)                    /*!< NCESRC61 (Bit 16)                                     */
#define GPIO_PINCFG61_NCESRC61_Msk        (0x3f0000UL)              /*!< NCESRC61 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG61_PULLCFG61_Pos       (13UL)                    /*!< PULLCFG61 (Bit 13)                                    */
#define GPIO_PINCFG61_PULLCFG61_Msk       (0xe000UL)                /*!< PULLCFG61 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG61_SR61_Pos            (12UL)                    /*!< SR61 (Bit 12)                                         */
#define GPIO_PINCFG61_SR61_Msk            (0x1000UL)                /*!< SR61 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG61_DS61_Pos            (10UL)                    /*!< DS61 (Bit 10)                                         */
#define GPIO_PINCFG61_DS61_Msk            (0xc00UL)                 /*!< DS61 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG61_OUTCFG61_Pos        (8UL)                     /*!< OUTCFG61 (Bit 8)                                      */
#define GPIO_PINCFG61_OUTCFG61_Msk        (0x300UL)                 /*!< OUTCFG61 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG61_IRPTEN61_Pos        (6UL)                     /*!< IRPTEN61 (Bit 6)                                      */
#define GPIO_PINCFG61_IRPTEN61_Msk        (0xc0UL)                  /*!< IRPTEN61 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG61_RDZERO61_Pos        (5UL)                     /*!< RDZERO61 (Bit 5)                                      */
#define GPIO_PINCFG61_RDZERO61_Msk        (0x20UL)                  /*!< RDZERO61 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG61_INPEN61_Pos         (4UL)                     /*!< INPEN61 (Bit 4)                                       */
#define GPIO_PINCFG61_INPEN61_Msk         (0x10UL)                  /*!< INPEN61 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG61_FNCSEL61_Pos        (0UL)                     /*!< FNCSEL61 (Bit 0)                                      */
#define GPIO_PINCFG61_FNCSEL61_Msk        (0xfUL)                   /*!< FNCSEL61 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG62  ======================================================== */
#define GPIO_PINCFG62_FOEN62_Pos          (27UL)                    /*!< FOEN62 (Bit 27)                                       */
#define GPIO_PINCFG62_FOEN62_Msk          (0x8000000UL)             /*!< FOEN62 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG62_FIEN62_Pos          (26UL)                    /*!< FIEN62 (Bit 26)                                       */
#define GPIO_PINCFG62_FIEN62_Msk          (0x4000000UL)             /*!< FIEN62 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG62_NCEPOL62_Pos        (22UL)                    /*!< NCEPOL62 (Bit 22)                                     */
#define GPIO_PINCFG62_NCEPOL62_Msk        (0x400000UL)              /*!< NCEPOL62 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG62_NCESRC62_Pos        (16UL)                    /*!< NCESRC62 (Bit 16)                                     */
#define GPIO_PINCFG62_NCESRC62_Msk        (0x3f0000UL)              /*!< NCESRC62 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG62_PULLCFG62_Pos       (13UL)                    /*!< PULLCFG62 (Bit 13)                                    */
#define GPIO_PINCFG62_PULLCFG62_Msk       (0xe000UL)                /*!< PULLCFG62 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG62_SR62_Pos            (12UL)                    /*!< SR62 (Bit 12)                                         */
#define GPIO_PINCFG62_SR62_Msk            (0x1000UL)                /*!< SR62 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG62_DS62_Pos            (10UL)                    /*!< DS62 (Bit 10)                                         */
#define GPIO_PINCFG62_DS62_Msk            (0xc00UL)                 /*!< DS62 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG62_OUTCFG62_Pos        (8UL)                     /*!< OUTCFG62 (Bit 8)                                      */
#define GPIO_PINCFG62_OUTCFG62_Msk        (0x300UL)                 /*!< OUTCFG62 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG62_IRPTEN62_Pos        (6UL)                     /*!< IRPTEN62 (Bit 6)                                      */
#define GPIO_PINCFG62_IRPTEN62_Msk        (0xc0UL)                  /*!< IRPTEN62 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG62_RDZERO62_Pos        (5UL)                     /*!< RDZERO62 (Bit 5)                                      */
#define GPIO_PINCFG62_RDZERO62_Msk        (0x20UL)                  /*!< RDZERO62 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG62_INPEN62_Pos         (4UL)                     /*!< INPEN62 (Bit 4)                                       */
#define GPIO_PINCFG62_INPEN62_Msk         (0x10UL)                  /*!< INPEN62 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG62_FNCSEL62_Pos        (0UL)                     /*!< FNCSEL62 (Bit 0)                                      */
#define GPIO_PINCFG62_FNCSEL62_Msk        (0xfUL)                   /*!< FNCSEL62 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG63  ======================================================== */
#define GPIO_PINCFG63_FOEN63_Pos          (27UL)                    /*!< FOEN63 (Bit 27)                                       */
#define GPIO_PINCFG63_FOEN63_Msk          (0x8000000UL)             /*!< FOEN63 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG63_FIEN63_Pos          (26UL)                    /*!< FIEN63 (Bit 26)                                       */
#define GPIO_PINCFG63_FIEN63_Msk          (0x4000000UL)             /*!< FIEN63 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG63_NCEPOL63_Pos        (22UL)                    /*!< NCEPOL63 (Bit 22)                                     */
#define GPIO_PINCFG63_NCEPOL63_Msk        (0x400000UL)              /*!< NCEPOL63 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG63_NCESRC63_Pos        (16UL)                    /*!< NCESRC63 (Bit 16)                                     */
#define GPIO_PINCFG63_NCESRC63_Msk        (0x3f0000UL)              /*!< NCESRC63 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG63_PULLCFG63_Pos       (13UL)                    /*!< PULLCFG63 (Bit 13)                                    */
#define GPIO_PINCFG63_PULLCFG63_Msk       (0xe000UL)                /*!< PULLCFG63 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG63_SR63_Pos            (12UL)                    /*!< SR63 (Bit 12)                                         */
#define GPIO_PINCFG63_SR63_Msk            (0x1000UL)                /*!< SR63 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG63_DS63_Pos            (10UL)                    /*!< DS63 (Bit 10)                                         */
#define GPIO_PINCFG63_DS63_Msk            (0xc00UL)                 /*!< DS63 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG63_OUTCFG63_Pos        (8UL)                     /*!< OUTCFG63 (Bit 8)                                      */
#define GPIO_PINCFG63_OUTCFG63_Msk        (0x300UL)                 /*!< OUTCFG63 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG63_IRPTEN63_Pos        (6UL)                     /*!< IRPTEN63 (Bit 6)                                      */
#define GPIO_PINCFG63_IRPTEN63_Msk        (0xc0UL)                  /*!< IRPTEN63 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG63_RDZERO63_Pos        (5UL)                     /*!< RDZERO63 (Bit 5)                                      */
#define GPIO_PINCFG63_RDZERO63_Msk        (0x20UL)                  /*!< RDZERO63 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG63_INPEN63_Pos         (4UL)                     /*!< INPEN63 (Bit 4)                                       */
#define GPIO_PINCFG63_INPEN63_Msk         (0x10UL)                  /*!< INPEN63 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG63_FNCSEL63_Pos        (0UL)                     /*!< FNCSEL63 (Bit 0)                                      */
#define GPIO_PINCFG63_FNCSEL63_Msk        (0xfUL)                   /*!< FNCSEL63 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG64  ======================================================== */
#define GPIO_PINCFG64_FOEN64_Pos          (27UL)                    /*!< FOEN64 (Bit 27)                                       */
#define GPIO_PINCFG64_FOEN64_Msk          (0x8000000UL)             /*!< FOEN64 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG64_FIEN64_Pos          (26UL)                    /*!< FIEN64 (Bit 26)                                       */
#define GPIO_PINCFG64_FIEN64_Msk          (0x4000000UL)             /*!< FIEN64 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG64_NCEPOL64_Pos        (22UL)                    /*!< NCEPOL64 (Bit 22)                                     */
#define GPIO_PINCFG64_NCEPOL64_Msk        (0x400000UL)              /*!< NCEPOL64 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG64_NCESRC64_Pos        (16UL)                    /*!< NCESRC64 (Bit 16)                                     */
#define GPIO_PINCFG64_NCESRC64_Msk        (0x3f0000UL)              /*!< NCESRC64 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG64_PULLCFG64_Pos       (13UL)                    /*!< PULLCFG64 (Bit 13)                                    */
#define GPIO_PINCFG64_PULLCFG64_Msk       (0xe000UL)                /*!< PULLCFG64 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG64_SR64_Pos            (12UL)                    /*!< SR64 (Bit 12)                                         */
#define GPIO_PINCFG64_SR64_Msk            (0x1000UL)                /*!< SR64 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG64_DS64_Pos            (10UL)                    /*!< DS64 (Bit 10)                                         */
#define GPIO_PINCFG64_DS64_Msk            (0xc00UL)                 /*!< DS64 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG64_OUTCFG64_Pos        (8UL)                     /*!< OUTCFG64 (Bit 8)                                      */
#define GPIO_PINCFG64_OUTCFG64_Msk        (0x300UL)                 /*!< OUTCFG64 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG64_IRPTEN64_Pos        (6UL)                     /*!< IRPTEN64 (Bit 6)                                      */
#define GPIO_PINCFG64_IRPTEN64_Msk        (0xc0UL)                  /*!< IRPTEN64 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG64_RDZERO64_Pos        (5UL)                     /*!< RDZERO64 (Bit 5)                                      */
#define GPIO_PINCFG64_RDZERO64_Msk        (0x20UL)                  /*!< RDZERO64 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG64_INPEN64_Pos         (4UL)                     /*!< INPEN64 (Bit 4)                                       */
#define GPIO_PINCFG64_INPEN64_Msk         (0x10UL)                  /*!< INPEN64 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG64_FNCSEL64_Pos        (0UL)                     /*!< FNCSEL64 (Bit 0)                                      */
#define GPIO_PINCFG64_FNCSEL64_Msk        (0xfUL)                   /*!< FNCSEL64 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG65  ======================================================== */
#define GPIO_PINCFG65_FOEN65_Pos          (27UL)                    /*!< FOEN65 (Bit 27)                                       */
#define GPIO_PINCFG65_FOEN65_Msk          (0x8000000UL)             /*!< FOEN65 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG65_FIEN65_Pos          (26UL)                    /*!< FIEN65 (Bit 26)                                       */
#define GPIO_PINCFG65_FIEN65_Msk          (0x4000000UL)             /*!< FIEN65 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG65_NCEPOL65_Pos        (22UL)                    /*!< NCEPOL65 (Bit 22)                                     */
#define GPIO_PINCFG65_NCEPOL65_Msk        (0x400000UL)              /*!< NCEPOL65 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG65_NCESRC65_Pos        (16UL)                    /*!< NCESRC65 (Bit 16)                                     */
#define GPIO_PINCFG65_NCESRC65_Msk        (0x3f0000UL)              /*!< NCESRC65 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG65_PULLCFG65_Pos       (13UL)                    /*!< PULLCFG65 (Bit 13)                                    */
#define GPIO_PINCFG65_PULLCFG65_Msk       (0xe000UL)                /*!< PULLCFG65 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG65_SR65_Pos            (12UL)                    /*!< SR65 (Bit 12)                                         */
#define GPIO_PINCFG65_SR65_Msk            (0x1000UL)                /*!< SR65 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG65_DS65_Pos            (10UL)                    /*!< DS65 (Bit 10)                                         */
#define GPIO_PINCFG65_DS65_Msk            (0xc00UL)                 /*!< DS65 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG65_OUTCFG65_Pos        (8UL)                     /*!< OUTCFG65 (Bit 8)                                      */
#define GPIO_PINCFG65_OUTCFG65_Msk        (0x300UL)                 /*!< OUTCFG65 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG65_IRPTEN65_Pos        (6UL)                     /*!< IRPTEN65 (Bit 6)                                      */
#define GPIO_PINCFG65_IRPTEN65_Msk        (0xc0UL)                  /*!< IRPTEN65 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG65_RDZERO65_Pos        (5UL)                     /*!< RDZERO65 (Bit 5)                                      */
#define GPIO_PINCFG65_RDZERO65_Msk        (0x20UL)                  /*!< RDZERO65 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG65_INPEN65_Pos         (4UL)                     /*!< INPEN65 (Bit 4)                                       */
#define GPIO_PINCFG65_INPEN65_Msk         (0x10UL)                  /*!< INPEN65 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG65_FNCSEL65_Pos        (0UL)                     /*!< FNCSEL65 (Bit 0)                                      */
#define GPIO_PINCFG65_FNCSEL65_Msk        (0xfUL)                   /*!< FNCSEL65 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG66  ======================================================== */
#define GPIO_PINCFG66_FOEN66_Pos          (27UL)                    /*!< FOEN66 (Bit 27)                                       */
#define GPIO_PINCFG66_FOEN66_Msk          (0x8000000UL)             /*!< FOEN66 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG66_FIEN66_Pos          (26UL)                    /*!< FIEN66 (Bit 26)                                       */
#define GPIO_PINCFG66_FIEN66_Msk          (0x4000000UL)             /*!< FIEN66 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG66_NCEPOL66_Pos        (22UL)                    /*!< NCEPOL66 (Bit 22)                                     */
#define GPIO_PINCFG66_NCEPOL66_Msk        (0x400000UL)              /*!< NCEPOL66 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG66_NCESRC66_Pos        (16UL)                    /*!< NCESRC66 (Bit 16)                                     */
#define GPIO_PINCFG66_NCESRC66_Msk        (0x3f0000UL)              /*!< NCESRC66 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG66_PULLCFG66_Pos       (13UL)                    /*!< PULLCFG66 (Bit 13)                                    */
#define GPIO_PINCFG66_PULLCFG66_Msk       (0xe000UL)                /*!< PULLCFG66 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG66_SR66_Pos            (12UL)                    /*!< SR66 (Bit 12)                                         */
#define GPIO_PINCFG66_SR66_Msk            (0x1000UL)                /*!< SR66 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG66_DS66_Pos            (10UL)                    /*!< DS66 (Bit 10)                                         */
#define GPIO_PINCFG66_DS66_Msk            (0xc00UL)                 /*!< DS66 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG66_OUTCFG66_Pos        (8UL)                     /*!< OUTCFG66 (Bit 8)                                      */
#define GPIO_PINCFG66_OUTCFG66_Msk        (0x300UL)                 /*!< OUTCFG66 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG66_IRPTEN66_Pos        (6UL)                     /*!< IRPTEN66 (Bit 6)                                      */
#define GPIO_PINCFG66_IRPTEN66_Msk        (0xc0UL)                  /*!< IRPTEN66 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG66_RDZERO66_Pos        (5UL)                     /*!< RDZERO66 (Bit 5)                                      */
#define GPIO_PINCFG66_RDZERO66_Msk        (0x20UL)                  /*!< RDZERO66 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG66_INPEN66_Pos         (4UL)                     /*!< INPEN66 (Bit 4)                                       */
#define GPIO_PINCFG66_INPEN66_Msk         (0x10UL)                  /*!< INPEN66 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG66_FNCSEL66_Pos        (0UL)                     /*!< FNCSEL66 (Bit 0)                                      */
#define GPIO_PINCFG66_FNCSEL66_Msk        (0xfUL)                   /*!< FNCSEL66 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG67  ======================================================== */
#define GPIO_PINCFG67_FOEN67_Pos          (27UL)                    /*!< FOEN67 (Bit 27)                                       */
#define GPIO_PINCFG67_FOEN67_Msk          (0x8000000UL)             /*!< FOEN67 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG67_FIEN67_Pos          (26UL)                    /*!< FIEN67 (Bit 26)                                       */
#define GPIO_PINCFG67_FIEN67_Msk          (0x4000000UL)             /*!< FIEN67 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG67_NCEPOL67_Pos        (22UL)                    /*!< NCEPOL67 (Bit 22)                                     */
#define GPIO_PINCFG67_NCEPOL67_Msk        (0x400000UL)              /*!< NCEPOL67 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG67_NCESRC67_Pos        (16UL)                    /*!< NCESRC67 (Bit 16)                                     */
#define GPIO_PINCFG67_NCESRC67_Msk        (0x3f0000UL)              /*!< NCESRC67 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG67_PULLCFG67_Pos       (13UL)                    /*!< PULLCFG67 (Bit 13)                                    */
#define GPIO_PINCFG67_PULLCFG67_Msk       (0xe000UL)                /*!< PULLCFG67 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG67_SR67_Pos            (12UL)                    /*!< SR67 (Bit 12)                                         */
#define GPIO_PINCFG67_SR67_Msk            (0x1000UL)                /*!< SR67 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG67_DS67_Pos            (10UL)                    /*!< DS67 (Bit 10)                                         */
#define GPIO_PINCFG67_DS67_Msk            (0xc00UL)                 /*!< DS67 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG67_OUTCFG67_Pos        (8UL)                     /*!< OUTCFG67 (Bit 8)                                      */
#define GPIO_PINCFG67_OUTCFG67_Msk        (0x300UL)                 /*!< OUTCFG67 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG67_IRPTEN67_Pos        (6UL)                     /*!< IRPTEN67 (Bit 6)                                      */
#define GPIO_PINCFG67_IRPTEN67_Msk        (0xc0UL)                  /*!< IRPTEN67 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG67_RDZERO67_Pos        (5UL)                     /*!< RDZERO67 (Bit 5)                                      */
#define GPIO_PINCFG67_RDZERO67_Msk        (0x20UL)                  /*!< RDZERO67 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG67_INPEN67_Pos         (4UL)                     /*!< INPEN67 (Bit 4)                                       */
#define GPIO_PINCFG67_INPEN67_Msk         (0x10UL)                  /*!< INPEN67 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG67_FNCSEL67_Pos        (0UL)                     /*!< FNCSEL67 (Bit 0)                                      */
#define GPIO_PINCFG67_FNCSEL67_Msk        (0xfUL)                   /*!< FNCSEL67 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG68  ======================================================== */
#define GPIO_PINCFG68_FOEN68_Pos          (27UL)                    /*!< FOEN68 (Bit 27)                                       */
#define GPIO_PINCFG68_FOEN68_Msk          (0x8000000UL)             /*!< FOEN68 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG68_FIEN68_Pos          (26UL)                    /*!< FIEN68 (Bit 26)                                       */
#define GPIO_PINCFG68_FIEN68_Msk          (0x4000000UL)             /*!< FIEN68 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG68_NCEPOL68_Pos        (22UL)                    /*!< NCEPOL68 (Bit 22)                                     */
#define GPIO_PINCFG68_NCEPOL68_Msk        (0x400000UL)              /*!< NCEPOL68 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG68_NCESRC68_Pos        (16UL)                    /*!< NCESRC68 (Bit 16)                                     */
#define GPIO_PINCFG68_NCESRC68_Msk        (0x3f0000UL)              /*!< NCESRC68 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG68_PULLCFG68_Pos       (13UL)                    /*!< PULLCFG68 (Bit 13)                                    */
#define GPIO_PINCFG68_PULLCFG68_Msk       (0xe000UL)                /*!< PULLCFG68 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG68_SR68_Pos            (12UL)                    /*!< SR68 (Bit 12)                                         */
#define GPIO_PINCFG68_SR68_Msk            (0x1000UL)                /*!< SR68 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG68_DS68_Pos            (10UL)                    /*!< DS68 (Bit 10)                                         */
#define GPIO_PINCFG68_DS68_Msk            (0xc00UL)                 /*!< DS68 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG68_OUTCFG68_Pos        (8UL)                     /*!< OUTCFG68 (Bit 8)                                      */
#define GPIO_PINCFG68_OUTCFG68_Msk        (0x300UL)                 /*!< OUTCFG68 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG68_IRPTEN68_Pos        (6UL)                     /*!< IRPTEN68 (Bit 6)                                      */
#define GPIO_PINCFG68_IRPTEN68_Msk        (0xc0UL)                  /*!< IRPTEN68 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG68_RDZERO68_Pos        (5UL)                     /*!< RDZERO68 (Bit 5)                                      */
#define GPIO_PINCFG68_RDZERO68_Msk        (0x20UL)                  /*!< RDZERO68 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG68_INPEN68_Pos         (4UL)                     /*!< INPEN68 (Bit 4)                                       */
#define GPIO_PINCFG68_INPEN68_Msk         (0x10UL)                  /*!< INPEN68 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG68_FNCSEL68_Pos        (0UL)                     /*!< FNCSEL68 (Bit 0)                                      */
#define GPIO_PINCFG68_FNCSEL68_Msk        (0xfUL)                   /*!< FNCSEL68 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG69  ======================================================== */
#define GPIO_PINCFG69_FOEN69_Pos          (27UL)                    /*!< FOEN69 (Bit 27)                                       */
#define GPIO_PINCFG69_FOEN69_Msk          (0x8000000UL)             /*!< FOEN69 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG69_FIEN69_Pos          (26UL)                    /*!< FIEN69 (Bit 26)                                       */
#define GPIO_PINCFG69_FIEN69_Msk          (0x4000000UL)             /*!< FIEN69 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG69_NCEPOL69_Pos        (22UL)                    /*!< NCEPOL69 (Bit 22)                                     */
#define GPIO_PINCFG69_NCEPOL69_Msk        (0x400000UL)              /*!< NCEPOL69 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG69_NCESRC69_Pos        (16UL)                    /*!< NCESRC69 (Bit 16)                                     */
#define GPIO_PINCFG69_NCESRC69_Msk        (0x3f0000UL)              /*!< NCESRC69 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG69_PULLCFG69_Pos       (13UL)                    /*!< PULLCFG69 (Bit 13)                                    */
#define GPIO_PINCFG69_PULLCFG69_Msk       (0xe000UL)                /*!< PULLCFG69 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG69_SR69_Pos            (12UL)                    /*!< SR69 (Bit 12)                                         */
#define GPIO_PINCFG69_SR69_Msk            (0x1000UL)                /*!< SR69 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG69_DS69_Pos            (10UL)                    /*!< DS69 (Bit 10)                                         */
#define GPIO_PINCFG69_DS69_Msk            (0xc00UL)                 /*!< DS69 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG69_OUTCFG69_Pos        (8UL)                     /*!< OUTCFG69 (Bit 8)                                      */
#define GPIO_PINCFG69_OUTCFG69_Msk        (0x300UL)                 /*!< OUTCFG69 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG69_IRPTEN69_Pos        (6UL)                     /*!< IRPTEN69 (Bit 6)                                      */
#define GPIO_PINCFG69_IRPTEN69_Msk        (0xc0UL)                  /*!< IRPTEN69 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG69_RDZERO69_Pos        (5UL)                     /*!< RDZERO69 (Bit 5)                                      */
#define GPIO_PINCFG69_RDZERO69_Msk        (0x20UL)                  /*!< RDZERO69 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG69_INPEN69_Pos         (4UL)                     /*!< INPEN69 (Bit 4)                                       */
#define GPIO_PINCFG69_INPEN69_Msk         (0x10UL)                  /*!< INPEN69 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG69_FNCSEL69_Pos        (0UL)                     /*!< FNCSEL69 (Bit 0)                                      */
#define GPIO_PINCFG69_FNCSEL69_Msk        (0xfUL)                   /*!< FNCSEL69 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG70  ======================================================== */
#define GPIO_PINCFG70_FOEN70_Pos          (27UL)                    /*!< FOEN70 (Bit 27)                                       */
#define GPIO_PINCFG70_FOEN70_Msk          (0x8000000UL)             /*!< FOEN70 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG70_FIEN70_Pos          (26UL)                    /*!< FIEN70 (Bit 26)                                       */
#define GPIO_PINCFG70_FIEN70_Msk          (0x4000000UL)             /*!< FIEN70 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG70_NCEPOL70_Pos        (22UL)                    /*!< NCEPOL70 (Bit 22)                                     */
#define GPIO_PINCFG70_NCEPOL70_Msk        (0x400000UL)              /*!< NCEPOL70 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG70_NCESRC70_Pos        (16UL)                    /*!< NCESRC70 (Bit 16)                                     */
#define GPIO_PINCFG70_NCESRC70_Msk        (0x3f0000UL)              /*!< NCESRC70 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG70_PULLCFG70_Pos       (13UL)                    /*!< PULLCFG70 (Bit 13)                                    */
#define GPIO_PINCFG70_PULLCFG70_Msk       (0xe000UL)                /*!< PULLCFG70 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG70_SR70_Pos            (12UL)                    /*!< SR70 (Bit 12)                                         */
#define GPIO_PINCFG70_SR70_Msk            (0x1000UL)                /*!< SR70 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG70_DS70_Pos            (10UL)                    /*!< DS70 (Bit 10)                                         */
#define GPIO_PINCFG70_DS70_Msk            (0xc00UL)                 /*!< DS70 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG70_OUTCFG70_Pos        (8UL)                     /*!< OUTCFG70 (Bit 8)                                      */
#define GPIO_PINCFG70_OUTCFG70_Msk        (0x300UL)                 /*!< OUTCFG70 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG70_IRPTEN70_Pos        (6UL)                     /*!< IRPTEN70 (Bit 6)                                      */
#define GPIO_PINCFG70_IRPTEN70_Msk        (0xc0UL)                  /*!< IRPTEN70 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG70_RDZERO70_Pos        (5UL)                     /*!< RDZERO70 (Bit 5)                                      */
#define GPIO_PINCFG70_RDZERO70_Msk        (0x20UL)                  /*!< RDZERO70 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG70_INPEN70_Pos         (4UL)                     /*!< INPEN70 (Bit 4)                                       */
#define GPIO_PINCFG70_INPEN70_Msk         (0x10UL)                  /*!< INPEN70 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG70_FNCSEL70_Pos        (0UL)                     /*!< FNCSEL70 (Bit 0)                                      */
#define GPIO_PINCFG70_FNCSEL70_Msk        (0xfUL)                   /*!< FNCSEL70 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG71  ======================================================== */
#define GPIO_PINCFG71_FOEN71_Pos          (27UL)                    /*!< FOEN71 (Bit 27)                                       */
#define GPIO_PINCFG71_FOEN71_Msk          (0x8000000UL)             /*!< FOEN71 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG71_FIEN71_Pos          (26UL)                    /*!< FIEN71 (Bit 26)                                       */
#define GPIO_PINCFG71_FIEN71_Msk          (0x4000000UL)             /*!< FIEN71 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG71_NCEPOL71_Pos        (22UL)                    /*!< NCEPOL71 (Bit 22)                                     */
#define GPIO_PINCFG71_NCEPOL71_Msk        (0x400000UL)              /*!< NCEPOL71 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG71_NCESRC71_Pos        (16UL)                    /*!< NCESRC71 (Bit 16)                                     */
#define GPIO_PINCFG71_NCESRC71_Msk        (0x3f0000UL)              /*!< NCESRC71 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG71_PULLCFG71_Pos       (13UL)                    /*!< PULLCFG71 (Bit 13)                                    */
#define GPIO_PINCFG71_PULLCFG71_Msk       (0xe000UL)                /*!< PULLCFG71 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG71_SR71_Pos            (12UL)                    /*!< SR71 (Bit 12)                                         */
#define GPIO_PINCFG71_SR71_Msk            (0x1000UL)                /*!< SR71 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG71_DS71_Pos            (10UL)                    /*!< DS71 (Bit 10)                                         */
#define GPIO_PINCFG71_DS71_Msk            (0xc00UL)                 /*!< DS71 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG71_OUTCFG71_Pos        (8UL)                     /*!< OUTCFG71 (Bit 8)                                      */
#define GPIO_PINCFG71_OUTCFG71_Msk        (0x300UL)                 /*!< OUTCFG71 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG71_IRPTEN71_Pos        (6UL)                     /*!< IRPTEN71 (Bit 6)                                      */
#define GPIO_PINCFG71_IRPTEN71_Msk        (0xc0UL)                  /*!< IRPTEN71 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG71_RDZERO71_Pos        (5UL)                     /*!< RDZERO71 (Bit 5)                                      */
#define GPIO_PINCFG71_RDZERO71_Msk        (0x20UL)                  /*!< RDZERO71 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG71_INPEN71_Pos         (4UL)                     /*!< INPEN71 (Bit 4)                                       */
#define GPIO_PINCFG71_INPEN71_Msk         (0x10UL)                  /*!< INPEN71 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG71_FNCSEL71_Pos        (0UL)                     /*!< FNCSEL71 (Bit 0)                                      */
#define GPIO_PINCFG71_FNCSEL71_Msk        (0xfUL)                   /*!< FNCSEL71 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG72  ======================================================== */
#define GPIO_PINCFG72_FOEN72_Pos          (27UL)                    /*!< FOEN72 (Bit 27)                                       */
#define GPIO_PINCFG72_FOEN72_Msk          (0x8000000UL)             /*!< FOEN72 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG72_FIEN72_Pos          (26UL)                    /*!< FIEN72 (Bit 26)                                       */
#define GPIO_PINCFG72_FIEN72_Msk          (0x4000000UL)             /*!< FIEN72 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG72_NCEPOL72_Pos        (22UL)                    /*!< NCEPOL72 (Bit 22)                                     */
#define GPIO_PINCFG72_NCEPOL72_Msk        (0x400000UL)              /*!< NCEPOL72 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG72_NCESRC72_Pos        (16UL)                    /*!< NCESRC72 (Bit 16)                                     */
#define GPIO_PINCFG72_NCESRC72_Msk        (0x3f0000UL)              /*!< NCESRC72 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG72_PULLCFG72_Pos       (13UL)                    /*!< PULLCFG72 (Bit 13)                                    */
#define GPIO_PINCFG72_PULLCFG72_Msk       (0xe000UL)                /*!< PULLCFG72 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG72_SR72_Pos            (12UL)                    /*!< SR72 (Bit 12)                                         */
#define GPIO_PINCFG72_SR72_Msk            (0x1000UL)                /*!< SR72 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG72_DS72_Pos            (10UL)                    /*!< DS72 (Bit 10)                                         */
#define GPIO_PINCFG72_DS72_Msk            (0xc00UL)                 /*!< DS72 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG72_OUTCFG72_Pos        (8UL)                     /*!< OUTCFG72 (Bit 8)                                      */
#define GPIO_PINCFG72_OUTCFG72_Msk        (0x300UL)                 /*!< OUTCFG72 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG72_IRPTEN72_Pos        (6UL)                     /*!< IRPTEN72 (Bit 6)                                      */
#define GPIO_PINCFG72_IRPTEN72_Msk        (0xc0UL)                  /*!< IRPTEN72 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG72_RDZERO72_Pos        (5UL)                     /*!< RDZERO72 (Bit 5)                                      */
#define GPIO_PINCFG72_RDZERO72_Msk        (0x20UL)                  /*!< RDZERO72 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG72_INPEN72_Pos         (4UL)                     /*!< INPEN72 (Bit 4)                                       */
#define GPIO_PINCFG72_INPEN72_Msk         (0x10UL)                  /*!< INPEN72 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG72_FNCSEL72_Pos        (0UL)                     /*!< FNCSEL72 (Bit 0)                                      */
#define GPIO_PINCFG72_FNCSEL72_Msk        (0xfUL)                   /*!< FNCSEL72 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG73  ======================================================== */
#define GPIO_PINCFG73_FOEN73_Pos          (27UL)                    /*!< FOEN73 (Bit 27)                                       */
#define GPIO_PINCFG73_FOEN73_Msk          (0x8000000UL)             /*!< FOEN73 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG73_FIEN73_Pos          (26UL)                    /*!< FIEN73 (Bit 26)                                       */
#define GPIO_PINCFG73_FIEN73_Msk          (0x4000000UL)             /*!< FIEN73 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG73_NCEPOL73_Pos        (22UL)                    /*!< NCEPOL73 (Bit 22)                                     */
#define GPIO_PINCFG73_NCEPOL73_Msk        (0x400000UL)              /*!< NCEPOL73 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG73_NCESRC73_Pos        (16UL)                    /*!< NCESRC73 (Bit 16)                                     */
#define GPIO_PINCFG73_NCESRC73_Msk        (0x3f0000UL)              /*!< NCESRC73 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG73_PULLCFG73_Pos       (13UL)                    /*!< PULLCFG73 (Bit 13)                                    */
#define GPIO_PINCFG73_PULLCFG73_Msk       (0xe000UL)                /*!< PULLCFG73 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG73_SR73_Pos            (12UL)                    /*!< SR73 (Bit 12)                                         */
#define GPIO_PINCFG73_SR73_Msk            (0x1000UL)                /*!< SR73 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG73_DS73_Pos            (10UL)                    /*!< DS73 (Bit 10)                                         */
#define GPIO_PINCFG73_DS73_Msk            (0xc00UL)                 /*!< DS73 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG73_OUTCFG73_Pos        (8UL)                     /*!< OUTCFG73 (Bit 8)                                      */
#define GPIO_PINCFG73_OUTCFG73_Msk        (0x300UL)                 /*!< OUTCFG73 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG73_IRPTEN73_Pos        (6UL)                     /*!< IRPTEN73 (Bit 6)                                      */
#define GPIO_PINCFG73_IRPTEN73_Msk        (0xc0UL)                  /*!< IRPTEN73 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG73_RDZERO73_Pos        (5UL)                     /*!< RDZERO73 (Bit 5)                                      */
#define GPIO_PINCFG73_RDZERO73_Msk        (0x20UL)                  /*!< RDZERO73 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG73_INPEN73_Pos         (4UL)                     /*!< INPEN73 (Bit 4)                                       */
#define GPIO_PINCFG73_INPEN73_Msk         (0x10UL)                  /*!< INPEN73 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG73_FNCSEL73_Pos        (0UL)                     /*!< FNCSEL73 (Bit 0)                                      */
#define GPIO_PINCFG73_FNCSEL73_Msk        (0xfUL)                   /*!< FNCSEL73 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG74  ======================================================== */
#define GPIO_PINCFG74_FOEN74_Pos          (27UL)                    /*!< FOEN74 (Bit 27)                                       */
#define GPIO_PINCFG74_FOEN74_Msk          (0x8000000UL)             /*!< FOEN74 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG74_FIEN74_Pos          (26UL)                    /*!< FIEN74 (Bit 26)                                       */
#define GPIO_PINCFG74_FIEN74_Msk          (0x4000000UL)             /*!< FIEN74 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG74_NCEPOL74_Pos        (22UL)                    /*!< NCEPOL74 (Bit 22)                                     */
#define GPIO_PINCFG74_NCEPOL74_Msk        (0x400000UL)              /*!< NCEPOL74 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG74_NCESRC74_Pos        (16UL)                    /*!< NCESRC74 (Bit 16)                                     */
#define GPIO_PINCFG74_NCESRC74_Msk        (0x3f0000UL)              /*!< NCESRC74 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG74_PULLCFG74_Pos       (13UL)                    /*!< PULLCFG74 (Bit 13)                                    */
#define GPIO_PINCFG74_PULLCFG74_Msk       (0xe000UL)                /*!< PULLCFG74 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG74_SR74_Pos            (12UL)                    /*!< SR74 (Bit 12)                                         */
#define GPIO_PINCFG74_SR74_Msk            (0x1000UL)                /*!< SR74 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG74_DS74_Pos            (10UL)                    /*!< DS74 (Bit 10)                                         */
#define GPIO_PINCFG74_DS74_Msk            (0xc00UL)                 /*!< DS74 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG74_OUTCFG74_Pos        (8UL)                     /*!< OUTCFG74 (Bit 8)                                      */
#define GPIO_PINCFG74_OUTCFG74_Msk        (0x300UL)                 /*!< OUTCFG74 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG74_IRPTEN74_Pos        (6UL)                     /*!< IRPTEN74 (Bit 6)                                      */
#define GPIO_PINCFG74_IRPTEN74_Msk        (0xc0UL)                  /*!< IRPTEN74 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG74_RDZERO74_Pos        (5UL)                     /*!< RDZERO74 (Bit 5)                                      */
#define GPIO_PINCFG74_RDZERO74_Msk        (0x20UL)                  /*!< RDZERO74 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG74_INPEN74_Pos         (4UL)                     /*!< INPEN74 (Bit 4)                                       */
#define GPIO_PINCFG74_INPEN74_Msk         (0x10UL)                  /*!< INPEN74 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG74_FNCSEL74_Pos        (0UL)                     /*!< FNCSEL74 (Bit 0)                                      */
#define GPIO_PINCFG74_FNCSEL74_Msk        (0xfUL)                   /*!< FNCSEL74 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG75  ======================================================== */
#define GPIO_PINCFG75_FOEN75_Pos          (27UL)                    /*!< FOEN75 (Bit 27)                                       */
#define GPIO_PINCFG75_FOEN75_Msk          (0x8000000UL)             /*!< FOEN75 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG75_FIEN75_Pos          (26UL)                    /*!< FIEN75 (Bit 26)                                       */
#define GPIO_PINCFG75_FIEN75_Msk          (0x4000000UL)             /*!< FIEN75 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG75_NCEPOL75_Pos        (22UL)                    /*!< NCEPOL75 (Bit 22)                                     */
#define GPIO_PINCFG75_NCEPOL75_Msk        (0x400000UL)              /*!< NCEPOL75 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG75_NCESRC75_Pos        (16UL)                    /*!< NCESRC75 (Bit 16)                                     */
#define GPIO_PINCFG75_NCESRC75_Msk        (0x3f0000UL)              /*!< NCESRC75 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG75_PULLCFG75_Pos       (13UL)                    /*!< PULLCFG75 (Bit 13)                                    */
#define GPIO_PINCFG75_PULLCFG75_Msk       (0xe000UL)                /*!< PULLCFG75 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG75_SR75_Pos            (12UL)                    /*!< SR75 (Bit 12)                                         */
#define GPIO_PINCFG75_SR75_Msk            (0x1000UL)                /*!< SR75 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG75_DS75_Pos            (10UL)                    /*!< DS75 (Bit 10)                                         */
#define GPIO_PINCFG75_DS75_Msk            (0xc00UL)                 /*!< DS75 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG75_OUTCFG75_Pos        (8UL)                     /*!< OUTCFG75 (Bit 8)                                      */
#define GPIO_PINCFG75_OUTCFG75_Msk        (0x300UL)                 /*!< OUTCFG75 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG75_IRPTEN75_Pos        (6UL)                     /*!< IRPTEN75 (Bit 6)                                      */
#define GPIO_PINCFG75_IRPTEN75_Msk        (0xc0UL)                  /*!< IRPTEN75 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG75_RDZERO75_Pos        (5UL)                     /*!< RDZERO75 (Bit 5)                                      */
#define GPIO_PINCFG75_RDZERO75_Msk        (0x20UL)                  /*!< RDZERO75 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG75_INPEN75_Pos         (4UL)                     /*!< INPEN75 (Bit 4)                                       */
#define GPIO_PINCFG75_INPEN75_Msk         (0x10UL)                  /*!< INPEN75 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG75_FNCSEL75_Pos        (0UL)                     /*!< FNCSEL75 (Bit 0)                                      */
#define GPIO_PINCFG75_FNCSEL75_Msk        (0xfUL)                   /*!< FNCSEL75 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG76  ======================================================== */
#define GPIO_PINCFG76_FOEN76_Pos          (27UL)                    /*!< FOEN76 (Bit 27)                                       */
#define GPIO_PINCFG76_FOEN76_Msk          (0x8000000UL)             /*!< FOEN76 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG76_FIEN76_Pos          (26UL)                    /*!< FIEN76 (Bit 26)                                       */
#define GPIO_PINCFG76_FIEN76_Msk          (0x4000000UL)             /*!< FIEN76 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG76_NCEPOL76_Pos        (22UL)                    /*!< NCEPOL76 (Bit 22)                                     */
#define GPIO_PINCFG76_NCEPOL76_Msk        (0x400000UL)              /*!< NCEPOL76 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG76_NCESRC76_Pos        (16UL)                    /*!< NCESRC76 (Bit 16)                                     */
#define GPIO_PINCFG76_NCESRC76_Msk        (0x3f0000UL)              /*!< NCESRC76 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG76_PULLCFG76_Pos       (13UL)                    /*!< PULLCFG76 (Bit 13)                                    */
#define GPIO_PINCFG76_PULLCFG76_Msk       (0xe000UL)                /*!< PULLCFG76 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG76_SR76_Pos            (12UL)                    /*!< SR76 (Bit 12)                                         */
#define GPIO_PINCFG76_SR76_Msk            (0x1000UL)                /*!< SR76 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG76_DS76_Pos            (10UL)                    /*!< DS76 (Bit 10)                                         */
#define GPIO_PINCFG76_DS76_Msk            (0xc00UL)                 /*!< DS76 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG76_OUTCFG76_Pos        (8UL)                     /*!< OUTCFG76 (Bit 8)                                      */
#define GPIO_PINCFG76_OUTCFG76_Msk        (0x300UL)                 /*!< OUTCFG76 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG76_IRPTEN76_Pos        (6UL)                     /*!< IRPTEN76 (Bit 6)                                      */
#define GPIO_PINCFG76_IRPTEN76_Msk        (0xc0UL)                  /*!< IRPTEN76 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG76_RDZERO76_Pos        (5UL)                     /*!< RDZERO76 (Bit 5)                                      */
#define GPIO_PINCFG76_RDZERO76_Msk        (0x20UL)                  /*!< RDZERO76 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG76_INPEN76_Pos         (4UL)                     /*!< INPEN76 (Bit 4)                                       */
#define GPIO_PINCFG76_INPEN76_Msk         (0x10UL)                  /*!< INPEN76 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG76_FNCSEL76_Pos        (0UL)                     /*!< FNCSEL76 (Bit 0)                                      */
#define GPIO_PINCFG76_FNCSEL76_Msk        (0xfUL)                   /*!< FNCSEL76 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG77  ======================================================== */
#define GPIO_PINCFG77_FOEN77_Pos          (27UL)                    /*!< FOEN77 (Bit 27)                                       */
#define GPIO_PINCFG77_FOEN77_Msk          (0x8000000UL)             /*!< FOEN77 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG77_FIEN77_Pos          (26UL)                    /*!< FIEN77 (Bit 26)                                       */
#define GPIO_PINCFG77_FIEN77_Msk          (0x4000000UL)             /*!< FIEN77 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG77_NCEPOL77_Pos        (22UL)                    /*!< NCEPOL77 (Bit 22)                                     */
#define GPIO_PINCFG77_NCEPOL77_Msk        (0x400000UL)              /*!< NCEPOL77 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG77_NCESRC77_Pos        (16UL)                    /*!< NCESRC77 (Bit 16)                                     */
#define GPIO_PINCFG77_NCESRC77_Msk        (0x3f0000UL)              /*!< NCESRC77 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG77_PULLCFG77_Pos       (13UL)                    /*!< PULLCFG77 (Bit 13)                                    */
#define GPIO_PINCFG77_PULLCFG77_Msk       (0xe000UL)                /*!< PULLCFG77 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG77_SR77_Pos            (12UL)                    /*!< SR77 (Bit 12)                                         */
#define GPIO_PINCFG77_SR77_Msk            (0x1000UL)                /*!< SR77 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG77_DS77_Pos            (10UL)                    /*!< DS77 (Bit 10)                                         */
#define GPIO_PINCFG77_DS77_Msk            (0xc00UL)                 /*!< DS77 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG77_OUTCFG77_Pos        (8UL)                     /*!< OUTCFG77 (Bit 8)                                      */
#define GPIO_PINCFG77_OUTCFG77_Msk        (0x300UL)                 /*!< OUTCFG77 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG77_IRPTEN77_Pos        (6UL)                     /*!< IRPTEN77 (Bit 6)                                      */
#define GPIO_PINCFG77_IRPTEN77_Msk        (0xc0UL)                  /*!< IRPTEN77 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG77_RDZERO77_Pos        (5UL)                     /*!< RDZERO77 (Bit 5)                                      */
#define GPIO_PINCFG77_RDZERO77_Msk        (0x20UL)                  /*!< RDZERO77 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG77_INPEN77_Pos         (4UL)                     /*!< INPEN77 (Bit 4)                                       */
#define GPIO_PINCFG77_INPEN77_Msk         (0x10UL)                  /*!< INPEN77 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG77_FNCSEL77_Pos        (0UL)                     /*!< FNCSEL77 (Bit 0)                                      */
#define GPIO_PINCFG77_FNCSEL77_Msk        (0xfUL)                   /*!< FNCSEL77 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG78  ======================================================== */
#define GPIO_PINCFG78_FOEN78_Pos          (27UL)                    /*!< FOEN78 (Bit 27)                                       */
#define GPIO_PINCFG78_FOEN78_Msk          (0x8000000UL)             /*!< FOEN78 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG78_FIEN78_Pos          (26UL)                    /*!< FIEN78 (Bit 26)                                       */
#define GPIO_PINCFG78_FIEN78_Msk          (0x4000000UL)             /*!< FIEN78 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG78_NCEPOL78_Pos        (22UL)                    /*!< NCEPOL78 (Bit 22)                                     */
#define GPIO_PINCFG78_NCEPOL78_Msk        (0x400000UL)              /*!< NCEPOL78 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG78_NCESRC78_Pos        (16UL)                    /*!< NCESRC78 (Bit 16)                                     */
#define GPIO_PINCFG78_NCESRC78_Msk        (0x3f0000UL)              /*!< NCESRC78 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG78_PULLCFG78_Pos       (13UL)                    /*!< PULLCFG78 (Bit 13)                                    */
#define GPIO_PINCFG78_PULLCFG78_Msk       (0xe000UL)                /*!< PULLCFG78 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG78_SR78_Pos            (12UL)                    /*!< SR78 (Bit 12)                                         */
#define GPIO_PINCFG78_SR78_Msk            (0x1000UL)                /*!< SR78 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG78_DS78_Pos            (10UL)                    /*!< DS78 (Bit 10)                                         */
#define GPIO_PINCFG78_DS78_Msk            (0xc00UL)                 /*!< DS78 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG78_OUTCFG78_Pos        (8UL)                     /*!< OUTCFG78 (Bit 8)                                      */
#define GPIO_PINCFG78_OUTCFG78_Msk        (0x300UL)                 /*!< OUTCFG78 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG78_IRPTEN78_Pos        (6UL)                     /*!< IRPTEN78 (Bit 6)                                      */
#define GPIO_PINCFG78_IRPTEN78_Msk        (0xc0UL)                  /*!< IRPTEN78 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG78_RDZERO78_Pos        (5UL)                     /*!< RDZERO78 (Bit 5)                                      */
#define GPIO_PINCFG78_RDZERO78_Msk        (0x20UL)                  /*!< RDZERO78 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG78_INPEN78_Pos         (4UL)                     /*!< INPEN78 (Bit 4)                                       */
#define GPIO_PINCFG78_INPEN78_Msk         (0x10UL)                  /*!< INPEN78 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG78_FNCSEL78_Pos        (0UL)                     /*!< FNCSEL78 (Bit 0)                                      */
#define GPIO_PINCFG78_FNCSEL78_Msk        (0xfUL)                   /*!< FNCSEL78 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG79  ======================================================== */
#define GPIO_PINCFG79_FOEN79_Pos          (27UL)                    /*!< FOEN79 (Bit 27)                                       */
#define GPIO_PINCFG79_FOEN79_Msk          (0x8000000UL)             /*!< FOEN79 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG79_FIEN79_Pos          (26UL)                    /*!< FIEN79 (Bit 26)                                       */
#define GPIO_PINCFG79_FIEN79_Msk          (0x4000000UL)             /*!< FIEN79 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG79_NCEPOL79_Pos        (22UL)                    /*!< NCEPOL79 (Bit 22)                                     */
#define GPIO_PINCFG79_NCEPOL79_Msk        (0x400000UL)              /*!< NCEPOL79 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG79_NCESRC79_Pos        (16UL)                    /*!< NCESRC79 (Bit 16)                                     */
#define GPIO_PINCFG79_NCESRC79_Msk        (0x3f0000UL)              /*!< NCESRC79 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG79_PULLCFG79_Pos       (13UL)                    /*!< PULLCFG79 (Bit 13)                                    */
#define GPIO_PINCFG79_PULLCFG79_Msk       (0xe000UL)                /*!< PULLCFG79 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG79_SR79_Pos            (12UL)                    /*!< SR79 (Bit 12)                                         */
#define GPIO_PINCFG79_SR79_Msk            (0x1000UL)                /*!< SR79 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG79_DS79_Pos            (10UL)                    /*!< DS79 (Bit 10)                                         */
#define GPIO_PINCFG79_DS79_Msk            (0xc00UL)                 /*!< DS79 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG79_OUTCFG79_Pos        (8UL)                     /*!< OUTCFG79 (Bit 8)                                      */
#define GPIO_PINCFG79_OUTCFG79_Msk        (0x300UL)                 /*!< OUTCFG79 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG79_IRPTEN79_Pos        (6UL)                     /*!< IRPTEN79 (Bit 6)                                      */
#define GPIO_PINCFG79_IRPTEN79_Msk        (0xc0UL)                  /*!< IRPTEN79 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG79_RDZERO79_Pos        (5UL)                     /*!< RDZERO79 (Bit 5)                                      */
#define GPIO_PINCFG79_RDZERO79_Msk        (0x20UL)                  /*!< RDZERO79 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG79_INPEN79_Pos         (4UL)                     /*!< INPEN79 (Bit 4)                                       */
#define GPIO_PINCFG79_INPEN79_Msk         (0x10UL)                  /*!< INPEN79 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG79_FNCSEL79_Pos        (0UL)                     /*!< FNCSEL79 (Bit 0)                                      */
#define GPIO_PINCFG79_FNCSEL79_Msk        (0xfUL)                   /*!< FNCSEL79 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG80  ======================================================== */
#define GPIO_PINCFG80_FOEN80_Pos          (27UL)                    /*!< FOEN80 (Bit 27)                                       */
#define GPIO_PINCFG80_FOEN80_Msk          (0x8000000UL)             /*!< FOEN80 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG80_FIEN80_Pos          (26UL)                    /*!< FIEN80 (Bit 26)                                       */
#define GPIO_PINCFG80_FIEN80_Msk          (0x4000000UL)             /*!< FIEN80 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG80_NCEPOL80_Pos        (22UL)                    /*!< NCEPOL80 (Bit 22)                                     */
#define GPIO_PINCFG80_NCEPOL80_Msk        (0x400000UL)              /*!< NCEPOL80 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG80_NCESRC80_Pos        (16UL)                    /*!< NCESRC80 (Bit 16)                                     */
#define GPIO_PINCFG80_NCESRC80_Msk        (0x3f0000UL)              /*!< NCESRC80 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG80_PULLCFG80_Pos       (13UL)                    /*!< PULLCFG80 (Bit 13)                                    */
#define GPIO_PINCFG80_PULLCFG80_Msk       (0xe000UL)                /*!< PULLCFG80 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG80_SR80_Pos            (12UL)                    /*!< SR80 (Bit 12)                                         */
#define GPIO_PINCFG80_SR80_Msk            (0x1000UL)                /*!< SR80 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG80_DS80_Pos            (10UL)                    /*!< DS80 (Bit 10)                                         */
#define GPIO_PINCFG80_DS80_Msk            (0xc00UL)                 /*!< DS80 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG80_OUTCFG80_Pos        (8UL)                     /*!< OUTCFG80 (Bit 8)                                      */
#define GPIO_PINCFG80_OUTCFG80_Msk        (0x300UL)                 /*!< OUTCFG80 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG80_IRPTEN80_Pos        (6UL)                     /*!< IRPTEN80 (Bit 6)                                      */
#define GPIO_PINCFG80_IRPTEN80_Msk        (0xc0UL)                  /*!< IRPTEN80 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG80_RDZERO80_Pos        (5UL)                     /*!< RDZERO80 (Bit 5)                                      */
#define GPIO_PINCFG80_RDZERO80_Msk        (0x20UL)                  /*!< RDZERO80 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG80_INPEN80_Pos         (4UL)                     /*!< INPEN80 (Bit 4)                                       */
#define GPIO_PINCFG80_INPEN80_Msk         (0x10UL)                  /*!< INPEN80 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG80_FNCSEL80_Pos        (0UL)                     /*!< FNCSEL80 (Bit 0)                                      */
#define GPIO_PINCFG80_FNCSEL80_Msk        (0xfUL)                   /*!< FNCSEL80 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG81  ======================================================== */
#define GPIO_PINCFG81_FOEN81_Pos          (27UL)                    /*!< FOEN81 (Bit 27)                                       */
#define GPIO_PINCFG81_FOEN81_Msk          (0x8000000UL)             /*!< FOEN81 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG81_FIEN81_Pos          (26UL)                    /*!< FIEN81 (Bit 26)                                       */
#define GPIO_PINCFG81_FIEN81_Msk          (0x4000000UL)             /*!< FIEN81 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG81_NCEPOL81_Pos        (22UL)                    /*!< NCEPOL81 (Bit 22)                                     */
#define GPIO_PINCFG81_NCEPOL81_Msk        (0x400000UL)              /*!< NCEPOL81 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG81_NCESRC81_Pos        (16UL)                    /*!< NCESRC81 (Bit 16)                                     */
#define GPIO_PINCFG81_NCESRC81_Msk        (0x3f0000UL)              /*!< NCESRC81 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG81_PULLCFG81_Pos       (13UL)                    /*!< PULLCFG81 (Bit 13)                                    */
#define GPIO_PINCFG81_PULLCFG81_Msk       (0xe000UL)                /*!< PULLCFG81 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG81_SR81_Pos            (12UL)                    /*!< SR81 (Bit 12)                                         */
#define GPIO_PINCFG81_SR81_Msk            (0x1000UL)                /*!< SR81 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG81_DS81_Pos            (10UL)                    /*!< DS81 (Bit 10)                                         */
#define GPIO_PINCFG81_DS81_Msk            (0xc00UL)                 /*!< DS81 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG81_OUTCFG81_Pos        (8UL)                     /*!< OUTCFG81 (Bit 8)                                      */
#define GPIO_PINCFG81_OUTCFG81_Msk        (0x300UL)                 /*!< OUTCFG81 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG81_IRPTEN81_Pos        (6UL)                     /*!< IRPTEN81 (Bit 6)                                      */
#define GPIO_PINCFG81_IRPTEN81_Msk        (0xc0UL)                  /*!< IRPTEN81 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG81_RDZERO81_Pos        (5UL)                     /*!< RDZERO81 (Bit 5)                                      */
#define GPIO_PINCFG81_RDZERO81_Msk        (0x20UL)                  /*!< RDZERO81 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG81_INPEN81_Pos         (4UL)                     /*!< INPEN81 (Bit 4)                                       */
#define GPIO_PINCFG81_INPEN81_Msk         (0x10UL)                  /*!< INPEN81 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG81_FNCSEL81_Pos        (0UL)                     /*!< FNCSEL81 (Bit 0)                                      */
#define GPIO_PINCFG81_FNCSEL81_Msk        (0xfUL)                   /*!< FNCSEL81 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG82  ======================================================== */
#define GPIO_PINCFG82_FOEN82_Pos          (27UL)                    /*!< FOEN82 (Bit 27)                                       */
#define GPIO_PINCFG82_FOEN82_Msk          (0x8000000UL)             /*!< FOEN82 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG82_FIEN82_Pos          (26UL)                    /*!< FIEN82 (Bit 26)                                       */
#define GPIO_PINCFG82_FIEN82_Msk          (0x4000000UL)             /*!< FIEN82 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG82_NCEPOL82_Pos        (22UL)                    /*!< NCEPOL82 (Bit 22)                                     */
#define GPIO_PINCFG82_NCEPOL82_Msk        (0x400000UL)              /*!< NCEPOL82 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG82_NCESRC82_Pos        (16UL)                    /*!< NCESRC82 (Bit 16)                                     */
#define GPIO_PINCFG82_NCESRC82_Msk        (0x3f0000UL)              /*!< NCESRC82 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG82_PULLCFG82_Pos       (13UL)                    /*!< PULLCFG82 (Bit 13)                                    */
#define GPIO_PINCFG82_PULLCFG82_Msk       (0xe000UL)                /*!< PULLCFG82 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG82_SR82_Pos            (12UL)                    /*!< SR82 (Bit 12)                                         */
#define GPIO_PINCFG82_SR82_Msk            (0x1000UL)                /*!< SR82 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG82_DS82_Pos            (10UL)                    /*!< DS82 (Bit 10)                                         */
#define GPIO_PINCFG82_DS82_Msk            (0xc00UL)                 /*!< DS82 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG82_OUTCFG82_Pos        (8UL)                     /*!< OUTCFG82 (Bit 8)                                      */
#define GPIO_PINCFG82_OUTCFG82_Msk        (0x300UL)                 /*!< OUTCFG82 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG82_IRPTEN82_Pos        (6UL)                     /*!< IRPTEN82 (Bit 6)                                      */
#define GPIO_PINCFG82_IRPTEN82_Msk        (0xc0UL)                  /*!< IRPTEN82 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG82_RDZERO82_Pos        (5UL)                     /*!< RDZERO82 (Bit 5)                                      */
#define GPIO_PINCFG82_RDZERO82_Msk        (0x20UL)                  /*!< RDZERO82 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG82_INPEN82_Pos         (4UL)                     /*!< INPEN82 (Bit 4)                                       */
#define GPIO_PINCFG82_INPEN82_Msk         (0x10UL)                  /*!< INPEN82 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG82_FNCSEL82_Pos        (0UL)                     /*!< FNCSEL82 (Bit 0)                                      */
#define GPIO_PINCFG82_FNCSEL82_Msk        (0xfUL)                   /*!< FNCSEL82 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG83  ======================================================== */
#define GPIO_PINCFG83_FOEN83_Pos          (27UL)                    /*!< FOEN83 (Bit 27)                                       */
#define GPIO_PINCFG83_FOEN83_Msk          (0x8000000UL)             /*!< FOEN83 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG83_FIEN83_Pos          (26UL)                    /*!< FIEN83 (Bit 26)                                       */
#define GPIO_PINCFG83_FIEN83_Msk          (0x4000000UL)             /*!< FIEN83 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG83_NCEPOL83_Pos        (22UL)                    /*!< NCEPOL83 (Bit 22)                                     */
#define GPIO_PINCFG83_NCEPOL83_Msk        (0x400000UL)              /*!< NCEPOL83 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG83_NCESRC83_Pos        (16UL)                    /*!< NCESRC83 (Bit 16)                                     */
#define GPIO_PINCFG83_NCESRC83_Msk        (0x3f0000UL)              /*!< NCESRC83 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG83_PULLCFG83_Pos       (13UL)                    /*!< PULLCFG83 (Bit 13)                                    */
#define GPIO_PINCFG83_PULLCFG83_Msk       (0xe000UL)                /*!< PULLCFG83 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG83_SR83_Pos            (12UL)                    /*!< SR83 (Bit 12)                                         */
#define GPIO_PINCFG83_SR83_Msk            (0x1000UL)                /*!< SR83 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG83_DS83_Pos            (10UL)                    /*!< DS83 (Bit 10)                                         */
#define GPIO_PINCFG83_DS83_Msk            (0xc00UL)                 /*!< DS83 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG83_OUTCFG83_Pos        (8UL)                     /*!< OUTCFG83 (Bit 8)                                      */
#define GPIO_PINCFG83_OUTCFG83_Msk        (0x300UL)                 /*!< OUTCFG83 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG83_IRPTEN83_Pos        (6UL)                     /*!< IRPTEN83 (Bit 6)                                      */
#define GPIO_PINCFG83_IRPTEN83_Msk        (0xc0UL)                  /*!< IRPTEN83 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG83_RDZERO83_Pos        (5UL)                     /*!< RDZERO83 (Bit 5)                                      */
#define GPIO_PINCFG83_RDZERO83_Msk        (0x20UL)                  /*!< RDZERO83 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG83_INPEN83_Pos         (4UL)                     /*!< INPEN83 (Bit 4)                                       */
#define GPIO_PINCFG83_INPEN83_Msk         (0x10UL)                  /*!< INPEN83 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG83_FNCSEL83_Pos        (0UL)                     /*!< FNCSEL83 (Bit 0)                                      */
#define GPIO_PINCFG83_FNCSEL83_Msk        (0xfUL)                   /*!< FNCSEL83 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG84  ======================================================== */
#define GPIO_PINCFG84_FOEN84_Pos          (27UL)                    /*!< FOEN84 (Bit 27)                                       */
#define GPIO_PINCFG84_FOEN84_Msk          (0x8000000UL)             /*!< FOEN84 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG84_FIEN84_Pos          (26UL)                    /*!< FIEN84 (Bit 26)                                       */
#define GPIO_PINCFG84_FIEN84_Msk          (0x4000000UL)             /*!< FIEN84 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG84_NCEPOL84_Pos        (22UL)                    /*!< NCEPOL84 (Bit 22)                                     */
#define GPIO_PINCFG84_NCEPOL84_Msk        (0x400000UL)              /*!< NCEPOL84 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG84_NCESRC84_Pos        (16UL)                    /*!< NCESRC84 (Bit 16)                                     */
#define GPIO_PINCFG84_NCESRC84_Msk        (0x3f0000UL)              /*!< NCESRC84 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG84_PULLCFG84_Pos       (13UL)                    /*!< PULLCFG84 (Bit 13)                                    */
#define GPIO_PINCFG84_PULLCFG84_Msk       (0xe000UL)                /*!< PULLCFG84 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG84_SR84_Pos            (12UL)                    /*!< SR84 (Bit 12)                                         */
#define GPIO_PINCFG84_SR84_Msk            (0x1000UL)                /*!< SR84 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG84_DS84_Pos            (10UL)                    /*!< DS84 (Bit 10)                                         */
#define GPIO_PINCFG84_DS84_Msk            (0xc00UL)                 /*!< DS84 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG84_OUTCFG84_Pos        (8UL)                     /*!< OUTCFG84 (Bit 8)                                      */
#define GPIO_PINCFG84_OUTCFG84_Msk        (0x300UL)                 /*!< OUTCFG84 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG84_IRPTEN84_Pos        (6UL)                     /*!< IRPTEN84 (Bit 6)                                      */
#define GPIO_PINCFG84_IRPTEN84_Msk        (0xc0UL)                  /*!< IRPTEN84 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG84_RDZERO84_Pos        (5UL)                     /*!< RDZERO84 (Bit 5)                                      */
#define GPIO_PINCFG84_RDZERO84_Msk        (0x20UL)                  /*!< RDZERO84 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG84_INPEN84_Pos         (4UL)                     /*!< INPEN84 (Bit 4)                                       */
#define GPIO_PINCFG84_INPEN84_Msk         (0x10UL)                  /*!< INPEN84 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG84_FNCSEL84_Pos        (0UL)                     /*!< FNCSEL84 (Bit 0)                                      */
#define GPIO_PINCFG84_FNCSEL84_Msk        (0xfUL)                   /*!< FNCSEL84 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG85  ======================================================== */
#define GPIO_PINCFG85_FOEN85_Pos          (27UL)                    /*!< FOEN85 (Bit 27)                                       */
#define GPIO_PINCFG85_FOEN85_Msk          (0x8000000UL)             /*!< FOEN85 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG85_FIEN85_Pos          (26UL)                    /*!< FIEN85 (Bit 26)                                       */
#define GPIO_PINCFG85_FIEN85_Msk          (0x4000000UL)             /*!< FIEN85 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG85_NCEPOL85_Pos        (22UL)                    /*!< NCEPOL85 (Bit 22)                                     */
#define GPIO_PINCFG85_NCEPOL85_Msk        (0x400000UL)              /*!< NCEPOL85 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG85_NCESRC85_Pos        (16UL)                    /*!< NCESRC85 (Bit 16)                                     */
#define GPIO_PINCFG85_NCESRC85_Msk        (0x3f0000UL)              /*!< NCESRC85 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG85_PULLCFG85_Pos       (13UL)                    /*!< PULLCFG85 (Bit 13)                                    */
#define GPIO_PINCFG85_PULLCFG85_Msk       (0xe000UL)                /*!< PULLCFG85 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG85_SR85_Pos            (12UL)                    /*!< SR85 (Bit 12)                                         */
#define GPIO_PINCFG85_SR85_Msk            (0x1000UL)                /*!< SR85 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG85_DS85_Pos            (10UL)                    /*!< DS85 (Bit 10)                                         */
#define GPIO_PINCFG85_DS85_Msk            (0xc00UL)                 /*!< DS85 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG85_OUTCFG85_Pos        (8UL)                     /*!< OUTCFG85 (Bit 8)                                      */
#define GPIO_PINCFG85_OUTCFG85_Msk        (0x300UL)                 /*!< OUTCFG85 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG85_IRPTEN85_Pos        (6UL)                     /*!< IRPTEN85 (Bit 6)                                      */
#define GPIO_PINCFG85_IRPTEN85_Msk        (0xc0UL)                  /*!< IRPTEN85 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG85_RDZERO85_Pos        (5UL)                     /*!< RDZERO85 (Bit 5)                                      */
#define GPIO_PINCFG85_RDZERO85_Msk        (0x20UL)                  /*!< RDZERO85 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG85_INPEN85_Pos         (4UL)                     /*!< INPEN85 (Bit 4)                                       */
#define GPIO_PINCFG85_INPEN85_Msk         (0x10UL)                  /*!< INPEN85 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG85_FNCSEL85_Pos        (0UL)                     /*!< FNCSEL85 (Bit 0)                                      */
#define GPIO_PINCFG85_FNCSEL85_Msk        (0xfUL)                   /*!< FNCSEL85 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG86  ======================================================== */
#define GPIO_PINCFG86_FOEN86_Pos          (27UL)                    /*!< FOEN86 (Bit 27)                                       */
#define GPIO_PINCFG86_FOEN86_Msk          (0x8000000UL)             /*!< FOEN86 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG86_FIEN86_Pos          (26UL)                    /*!< FIEN86 (Bit 26)                                       */
#define GPIO_PINCFG86_FIEN86_Msk          (0x4000000UL)             /*!< FIEN86 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG86_NCEPOL86_Pos        (22UL)                    /*!< NCEPOL86 (Bit 22)                                     */
#define GPIO_PINCFG86_NCEPOL86_Msk        (0x400000UL)              /*!< NCEPOL86 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG86_NCESRC86_Pos        (16UL)                    /*!< NCESRC86 (Bit 16)                                     */
#define GPIO_PINCFG86_NCESRC86_Msk        (0x3f0000UL)              /*!< NCESRC86 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG86_PULLCFG86_Pos       (13UL)                    /*!< PULLCFG86 (Bit 13)                                    */
#define GPIO_PINCFG86_PULLCFG86_Msk       (0xe000UL)                /*!< PULLCFG86 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG86_SR86_Pos            (12UL)                    /*!< SR86 (Bit 12)                                         */
#define GPIO_PINCFG86_SR86_Msk            (0x1000UL)                /*!< SR86 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG86_DS86_Pos            (10UL)                    /*!< DS86 (Bit 10)                                         */
#define GPIO_PINCFG86_DS86_Msk            (0xc00UL)                 /*!< DS86 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG86_OUTCFG86_Pos        (8UL)                     /*!< OUTCFG86 (Bit 8)                                      */
#define GPIO_PINCFG86_OUTCFG86_Msk        (0x300UL)                 /*!< OUTCFG86 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG86_IRPTEN86_Pos        (6UL)                     /*!< IRPTEN86 (Bit 6)                                      */
#define GPIO_PINCFG86_IRPTEN86_Msk        (0xc0UL)                  /*!< IRPTEN86 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG86_RDZERO86_Pos        (5UL)                     /*!< RDZERO86 (Bit 5)                                      */
#define GPIO_PINCFG86_RDZERO86_Msk        (0x20UL)                  /*!< RDZERO86 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG86_INPEN86_Pos         (4UL)                     /*!< INPEN86 (Bit 4)                                       */
#define GPIO_PINCFG86_INPEN86_Msk         (0x10UL)                  /*!< INPEN86 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG86_FNCSEL86_Pos        (0UL)                     /*!< FNCSEL86 (Bit 0)                                      */
#define GPIO_PINCFG86_FNCSEL86_Msk        (0xfUL)                   /*!< FNCSEL86 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG87  ======================================================== */
#define GPIO_PINCFG87_FOEN87_Pos          (27UL)                    /*!< FOEN87 (Bit 27)                                       */
#define GPIO_PINCFG87_FOEN87_Msk          (0x8000000UL)             /*!< FOEN87 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG87_FIEN87_Pos          (26UL)                    /*!< FIEN87 (Bit 26)                                       */
#define GPIO_PINCFG87_FIEN87_Msk          (0x4000000UL)             /*!< FIEN87 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG87_NCEPOL87_Pos        (22UL)                    /*!< NCEPOL87 (Bit 22)                                     */
#define GPIO_PINCFG87_NCEPOL87_Msk        (0x400000UL)              /*!< NCEPOL87 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG87_NCESRC87_Pos        (16UL)                    /*!< NCESRC87 (Bit 16)                                     */
#define GPIO_PINCFG87_NCESRC87_Msk        (0x3f0000UL)              /*!< NCESRC87 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG87_PULLCFG87_Pos       (13UL)                    /*!< PULLCFG87 (Bit 13)                                    */
#define GPIO_PINCFG87_PULLCFG87_Msk       (0xe000UL)                /*!< PULLCFG87 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG87_SR87_Pos            (12UL)                    /*!< SR87 (Bit 12)                                         */
#define GPIO_PINCFG87_SR87_Msk            (0x1000UL)                /*!< SR87 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG87_DS87_Pos            (10UL)                    /*!< DS87 (Bit 10)                                         */
#define GPIO_PINCFG87_DS87_Msk            (0xc00UL)                 /*!< DS87 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG87_OUTCFG87_Pos        (8UL)                     /*!< OUTCFG87 (Bit 8)                                      */
#define GPIO_PINCFG87_OUTCFG87_Msk        (0x300UL)                 /*!< OUTCFG87 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG87_IRPTEN87_Pos        (6UL)                     /*!< IRPTEN87 (Bit 6)                                      */
#define GPIO_PINCFG87_IRPTEN87_Msk        (0xc0UL)                  /*!< IRPTEN87 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG87_RDZERO87_Pos        (5UL)                     /*!< RDZERO87 (Bit 5)                                      */
#define GPIO_PINCFG87_RDZERO87_Msk        (0x20UL)                  /*!< RDZERO87 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG87_INPEN87_Pos         (4UL)                     /*!< INPEN87 (Bit 4)                                       */
#define GPIO_PINCFG87_INPEN87_Msk         (0x10UL)                  /*!< INPEN87 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG87_FNCSEL87_Pos        (0UL)                     /*!< FNCSEL87 (Bit 0)                                      */
#define GPIO_PINCFG87_FNCSEL87_Msk        (0xfUL)                   /*!< FNCSEL87 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG88  ======================================================== */
#define GPIO_PINCFG88_FOEN88_Pos          (27UL)                    /*!< FOEN88 (Bit 27)                                       */
#define GPIO_PINCFG88_FOEN88_Msk          (0x8000000UL)             /*!< FOEN88 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG88_FIEN88_Pos          (26UL)                    /*!< FIEN88 (Bit 26)                                       */
#define GPIO_PINCFG88_FIEN88_Msk          (0x4000000UL)             /*!< FIEN88 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG88_NCEPOL88_Pos        (22UL)                    /*!< NCEPOL88 (Bit 22)                                     */
#define GPIO_PINCFG88_NCEPOL88_Msk        (0x400000UL)              /*!< NCEPOL88 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG88_NCESRC88_Pos        (16UL)                    /*!< NCESRC88 (Bit 16)                                     */
#define GPIO_PINCFG88_NCESRC88_Msk        (0x3f0000UL)              /*!< NCESRC88 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG88_PULLCFG88_Pos       (13UL)                    /*!< PULLCFG88 (Bit 13)                                    */
#define GPIO_PINCFG88_PULLCFG88_Msk       (0xe000UL)                /*!< PULLCFG88 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG88_SR88_Pos            (12UL)                    /*!< SR88 (Bit 12)                                         */
#define GPIO_PINCFG88_SR88_Msk            (0x1000UL)                /*!< SR88 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG88_DS88_Pos            (10UL)                    /*!< DS88 (Bit 10)                                         */
#define GPIO_PINCFG88_DS88_Msk            (0xc00UL)                 /*!< DS88 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG88_OUTCFG88_Pos        (8UL)                     /*!< OUTCFG88 (Bit 8)                                      */
#define GPIO_PINCFG88_OUTCFG88_Msk        (0x300UL)                 /*!< OUTCFG88 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG88_IRPTEN88_Pos        (6UL)                     /*!< IRPTEN88 (Bit 6)                                      */
#define GPIO_PINCFG88_IRPTEN88_Msk        (0xc0UL)                  /*!< IRPTEN88 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG88_RDZERO88_Pos        (5UL)                     /*!< RDZERO88 (Bit 5)                                      */
#define GPIO_PINCFG88_RDZERO88_Msk        (0x20UL)                  /*!< RDZERO88 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG88_INPEN88_Pos         (4UL)                     /*!< INPEN88 (Bit 4)                                       */
#define GPIO_PINCFG88_INPEN88_Msk         (0x10UL)                  /*!< INPEN88 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG88_FNCSEL88_Pos        (0UL)                     /*!< FNCSEL88 (Bit 0)                                      */
#define GPIO_PINCFG88_FNCSEL88_Msk        (0xfUL)                   /*!< FNCSEL88 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG89  ======================================================== */
#define GPIO_PINCFG89_FOEN89_Pos          (27UL)                    /*!< FOEN89 (Bit 27)                                       */
#define GPIO_PINCFG89_FOEN89_Msk          (0x8000000UL)             /*!< FOEN89 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG89_FIEN89_Pos          (26UL)                    /*!< FIEN89 (Bit 26)                                       */
#define GPIO_PINCFG89_FIEN89_Msk          (0x4000000UL)             /*!< FIEN89 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG89_NCEPOL89_Pos        (22UL)                    /*!< NCEPOL89 (Bit 22)                                     */
#define GPIO_PINCFG89_NCEPOL89_Msk        (0x400000UL)              /*!< NCEPOL89 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG89_NCESRC89_Pos        (16UL)                    /*!< NCESRC89 (Bit 16)                                     */
#define GPIO_PINCFG89_NCESRC89_Msk        (0x3f0000UL)              /*!< NCESRC89 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG89_PULLCFG89_Pos       (13UL)                    /*!< PULLCFG89 (Bit 13)                                    */
#define GPIO_PINCFG89_PULLCFG89_Msk       (0xe000UL)                /*!< PULLCFG89 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG89_SR89_Pos            (12UL)                    /*!< SR89 (Bit 12)                                         */
#define GPIO_PINCFG89_SR89_Msk            (0x1000UL)                /*!< SR89 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG89_DS89_Pos            (10UL)                    /*!< DS89 (Bit 10)                                         */
#define GPIO_PINCFG89_DS89_Msk            (0xc00UL)                 /*!< DS89 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG89_OUTCFG89_Pos        (8UL)                     /*!< OUTCFG89 (Bit 8)                                      */
#define GPIO_PINCFG89_OUTCFG89_Msk        (0x300UL)                 /*!< OUTCFG89 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG89_IRPTEN89_Pos        (6UL)                     /*!< IRPTEN89 (Bit 6)                                      */
#define GPIO_PINCFG89_IRPTEN89_Msk        (0xc0UL)                  /*!< IRPTEN89 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG89_RDZERO89_Pos        (5UL)                     /*!< RDZERO89 (Bit 5)                                      */
#define GPIO_PINCFG89_RDZERO89_Msk        (0x20UL)                  /*!< RDZERO89 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG89_INPEN89_Pos         (4UL)                     /*!< INPEN89 (Bit 4)                                       */
#define GPIO_PINCFG89_INPEN89_Msk         (0x10UL)                  /*!< INPEN89 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG89_FNCSEL89_Pos        (0UL)                     /*!< FNCSEL89 (Bit 0)                                      */
#define GPIO_PINCFG89_FNCSEL89_Msk        (0xfUL)                   /*!< FNCSEL89 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG90  ======================================================== */
#define GPIO_PINCFG90_FOEN90_Pos          (27UL)                    /*!< FOEN90 (Bit 27)                                       */
#define GPIO_PINCFG90_FOEN90_Msk          (0x8000000UL)             /*!< FOEN90 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG90_FIEN90_Pos          (26UL)                    /*!< FIEN90 (Bit 26)                                       */
#define GPIO_PINCFG90_FIEN90_Msk          (0x4000000UL)             /*!< FIEN90 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG90_NCEPOL90_Pos        (22UL)                    /*!< NCEPOL90 (Bit 22)                                     */
#define GPIO_PINCFG90_NCEPOL90_Msk        (0x400000UL)              /*!< NCEPOL90 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG90_NCESRC90_Pos        (16UL)                    /*!< NCESRC90 (Bit 16)                                     */
#define GPIO_PINCFG90_NCESRC90_Msk        (0x3f0000UL)              /*!< NCESRC90 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG90_PULLCFG90_Pos       (13UL)                    /*!< PULLCFG90 (Bit 13)                                    */
#define GPIO_PINCFG90_PULLCFG90_Msk       (0xe000UL)                /*!< PULLCFG90 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG90_SR90_Pos            (12UL)                    /*!< SR90 (Bit 12)                                         */
#define GPIO_PINCFG90_SR90_Msk            (0x1000UL)                /*!< SR90 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG90_DS90_Pos            (10UL)                    /*!< DS90 (Bit 10)                                         */
#define GPIO_PINCFG90_DS90_Msk            (0xc00UL)                 /*!< DS90 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG90_OUTCFG90_Pos        (8UL)                     /*!< OUTCFG90 (Bit 8)                                      */
#define GPIO_PINCFG90_OUTCFG90_Msk        (0x300UL)                 /*!< OUTCFG90 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG90_IRPTEN90_Pos        (6UL)                     /*!< IRPTEN90 (Bit 6)                                      */
#define GPIO_PINCFG90_IRPTEN90_Msk        (0xc0UL)                  /*!< IRPTEN90 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG90_RDZERO90_Pos        (5UL)                     /*!< RDZERO90 (Bit 5)                                      */
#define GPIO_PINCFG90_RDZERO90_Msk        (0x20UL)                  /*!< RDZERO90 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG90_INPEN90_Pos         (4UL)                     /*!< INPEN90 (Bit 4)                                       */
#define GPIO_PINCFG90_INPEN90_Msk         (0x10UL)                  /*!< INPEN90 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG90_FNCSEL90_Pos        (0UL)                     /*!< FNCSEL90 (Bit 0)                                      */
#define GPIO_PINCFG90_FNCSEL90_Msk        (0xfUL)                   /*!< FNCSEL90 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG91  ======================================================== */
#define GPIO_PINCFG91_FOEN91_Pos          (27UL)                    /*!< FOEN91 (Bit 27)                                       */
#define GPIO_PINCFG91_FOEN91_Msk          (0x8000000UL)             /*!< FOEN91 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG91_FIEN91_Pos          (26UL)                    /*!< FIEN91 (Bit 26)                                       */
#define GPIO_PINCFG91_FIEN91_Msk          (0x4000000UL)             /*!< FIEN91 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG91_NCEPOL91_Pos        (22UL)                    /*!< NCEPOL91 (Bit 22)                                     */
#define GPIO_PINCFG91_NCEPOL91_Msk        (0x400000UL)              /*!< NCEPOL91 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG91_NCESRC91_Pos        (16UL)                    /*!< NCESRC91 (Bit 16)                                     */
#define GPIO_PINCFG91_NCESRC91_Msk        (0x3f0000UL)              /*!< NCESRC91 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG91_PULLCFG91_Pos       (13UL)                    /*!< PULLCFG91 (Bit 13)                                    */
#define GPIO_PINCFG91_PULLCFG91_Msk       (0xe000UL)                /*!< PULLCFG91 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG91_SR91_Pos            (12UL)                    /*!< SR91 (Bit 12)                                         */
#define GPIO_PINCFG91_SR91_Msk            (0x1000UL)                /*!< SR91 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG91_DS91_Pos            (10UL)                    /*!< DS91 (Bit 10)                                         */
#define GPIO_PINCFG91_DS91_Msk            (0xc00UL)                 /*!< DS91 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG91_OUTCFG91_Pos        (8UL)                     /*!< OUTCFG91 (Bit 8)                                      */
#define GPIO_PINCFG91_OUTCFG91_Msk        (0x300UL)                 /*!< OUTCFG91 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG91_IRPTEN91_Pos        (6UL)                     /*!< IRPTEN91 (Bit 6)                                      */
#define GPIO_PINCFG91_IRPTEN91_Msk        (0xc0UL)                  /*!< IRPTEN91 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG91_RDZERO91_Pos        (5UL)                     /*!< RDZERO91 (Bit 5)                                      */
#define GPIO_PINCFG91_RDZERO91_Msk        (0x20UL)                  /*!< RDZERO91 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG91_INPEN91_Pos         (4UL)                     /*!< INPEN91 (Bit 4)                                       */
#define GPIO_PINCFG91_INPEN91_Msk         (0x10UL)                  /*!< INPEN91 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG91_FNCSEL91_Pos        (0UL)                     /*!< FNCSEL91 (Bit 0)                                      */
#define GPIO_PINCFG91_FNCSEL91_Msk        (0xfUL)                   /*!< FNCSEL91 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG92  ======================================================== */
#define GPIO_PINCFG92_FOEN92_Pos          (27UL)                    /*!< FOEN92 (Bit 27)                                       */
#define GPIO_PINCFG92_FOEN92_Msk          (0x8000000UL)             /*!< FOEN92 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG92_FIEN92_Pos          (26UL)                    /*!< FIEN92 (Bit 26)                                       */
#define GPIO_PINCFG92_FIEN92_Msk          (0x4000000UL)             /*!< FIEN92 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG92_NCEPOL92_Pos        (22UL)                    /*!< NCEPOL92 (Bit 22)                                     */
#define GPIO_PINCFG92_NCEPOL92_Msk        (0x400000UL)              /*!< NCEPOL92 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG92_NCESRC92_Pos        (16UL)                    /*!< NCESRC92 (Bit 16)                                     */
#define GPIO_PINCFG92_NCESRC92_Msk        (0x3f0000UL)              /*!< NCESRC92 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG92_PULLCFG92_Pos       (13UL)                    /*!< PULLCFG92 (Bit 13)                                    */
#define GPIO_PINCFG92_PULLCFG92_Msk       (0xe000UL)                /*!< PULLCFG92 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG92_SR92_Pos            (12UL)                    /*!< SR92 (Bit 12)                                         */
#define GPIO_PINCFG92_SR92_Msk            (0x1000UL)                /*!< SR92 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG92_DS92_Pos            (10UL)                    /*!< DS92 (Bit 10)                                         */
#define GPIO_PINCFG92_DS92_Msk            (0xc00UL)                 /*!< DS92 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG92_OUTCFG92_Pos        (8UL)                     /*!< OUTCFG92 (Bit 8)                                      */
#define GPIO_PINCFG92_OUTCFG92_Msk        (0x300UL)                 /*!< OUTCFG92 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG92_IRPTEN92_Pos        (6UL)                     /*!< IRPTEN92 (Bit 6)                                      */
#define GPIO_PINCFG92_IRPTEN92_Msk        (0xc0UL)                  /*!< IRPTEN92 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG92_RDZERO92_Pos        (5UL)                     /*!< RDZERO92 (Bit 5)                                      */
#define GPIO_PINCFG92_RDZERO92_Msk        (0x20UL)                  /*!< RDZERO92 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG92_INPEN92_Pos         (4UL)                     /*!< INPEN92 (Bit 4)                                       */
#define GPIO_PINCFG92_INPEN92_Msk         (0x10UL)                  /*!< INPEN92 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG92_FNCSEL92_Pos        (0UL)                     /*!< FNCSEL92 (Bit 0)                                      */
#define GPIO_PINCFG92_FNCSEL92_Msk        (0xfUL)                   /*!< FNCSEL92 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG93  ======================================================== */
#define GPIO_PINCFG93_FOEN93_Pos          (27UL)                    /*!< FOEN93 (Bit 27)                                       */
#define GPIO_PINCFG93_FOEN93_Msk          (0x8000000UL)             /*!< FOEN93 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG93_FIEN93_Pos          (26UL)                    /*!< FIEN93 (Bit 26)                                       */
#define GPIO_PINCFG93_FIEN93_Msk          (0x4000000UL)             /*!< FIEN93 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG93_NCEPOL93_Pos        (22UL)                    /*!< NCEPOL93 (Bit 22)                                     */
#define GPIO_PINCFG93_NCEPOL93_Msk        (0x400000UL)              /*!< NCEPOL93 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG93_NCESRC93_Pos        (16UL)                    /*!< NCESRC93 (Bit 16)                                     */
#define GPIO_PINCFG93_NCESRC93_Msk        (0x3f0000UL)              /*!< NCESRC93 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG93_PULLCFG93_Pos       (13UL)                    /*!< PULLCFG93 (Bit 13)                                    */
#define GPIO_PINCFG93_PULLCFG93_Msk       (0xe000UL)                /*!< PULLCFG93 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG93_SR93_Pos            (12UL)                    /*!< SR93 (Bit 12)                                         */
#define GPIO_PINCFG93_SR93_Msk            (0x1000UL)                /*!< SR93 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG93_DS93_Pos            (10UL)                    /*!< DS93 (Bit 10)                                         */
#define GPIO_PINCFG93_DS93_Msk            (0xc00UL)                 /*!< DS93 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG93_OUTCFG93_Pos        (8UL)                     /*!< OUTCFG93 (Bit 8)                                      */
#define GPIO_PINCFG93_OUTCFG93_Msk        (0x300UL)                 /*!< OUTCFG93 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG93_IRPTEN93_Pos        (6UL)                     /*!< IRPTEN93 (Bit 6)                                      */
#define GPIO_PINCFG93_IRPTEN93_Msk        (0xc0UL)                  /*!< IRPTEN93 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG93_RDZERO93_Pos        (5UL)                     /*!< RDZERO93 (Bit 5)                                      */
#define GPIO_PINCFG93_RDZERO93_Msk        (0x20UL)                  /*!< RDZERO93 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG93_INPEN93_Pos         (4UL)                     /*!< INPEN93 (Bit 4)                                       */
#define GPIO_PINCFG93_INPEN93_Msk         (0x10UL)                  /*!< INPEN93 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG93_FNCSEL93_Pos        (0UL)                     /*!< FNCSEL93 (Bit 0)                                      */
#define GPIO_PINCFG93_FNCSEL93_Msk        (0xfUL)                   /*!< FNCSEL93 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG94  ======================================================== */
#define GPIO_PINCFG94_FOEN94_Pos          (27UL)                    /*!< FOEN94 (Bit 27)                                       */
#define GPIO_PINCFG94_FOEN94_Msk          (0x8000000UL)             /*!< FOEN94 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG94_FIEN94_Pos          (26UL)                    /*!< FIEN94 (Bit 26)                                       */
#define GPIO_PINCFG94_FIEN94_Msk          (0x4000000UL)             /*!< FIEN94 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG94_NCEPOL94_Pos        (22UL)                    /*!< NCEPOL94 (Bit 22)                                     */
#define GPIO_PINCFG94_NCEPOL94_Msk        (0x400000UL)              /*!< NCEPOL94 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG94_NCESRC94_Pos        (16UL)                    /*!< NCESRC94 (Bit 16)                                     */
#define GPIO_PINCFG94_NCESRC94_Msk        (0x3f0000UL)              /*!< NCESRC94 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG94_PULLCFG94_Pos       (13UL)                    /*!< PULLCFG94 (Bit 13)                                    */
#define GPIO_PINCFG94_PULLCFG94_Msk       (0xe000UL)                /*!< PULLCFG94 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG94_SR94_Pos            (12UL)                    /*!< SR94 (Bit 12)                                         */
#define GPIO_PINCFG94_SR94_Msk            (0x1000UL)                /*!< SR94 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG94_DS94_Pos            (10UL)                    /*!< DS94 (Bit 10)                                         */
#define GPIO_PINCFG94_DS94_Msk            (0xc00UL)                 /*!< DS94 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG94_OUTCFG94_Pos        (8UL)                     /*!< OUTCFG94 (Bit 8)                                      */
#define GPIO_PINCFG94_OUTCFG94_Msk        (0x300UL)                 /*!< OUTCFG94 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG94_IRPTEN94_Pos        (6UL)                     /*!< IRPTEN94 (Bit 6)                                      */
#define GPIO_PINCFG94_IRPTEN94_Msk        (0xc0UL)                  /*!< IRPTEN94 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG94_RDZERO94_Pos        (5UL)                     /*!< RDZERO94 (Bit 5)                                      */
#define GPIO_PINCFG94_RDZERO94_Msk        (0x20UL)                  /*!< RDZERO94 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG94_INPEN94_Pos         (4UL)                     /*!< INPEN94 (Bit 4)                                       */
#define GPIO_PINCFG94_INPEN94_Msk         (0x10UL)                  /*!< INPEN94 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG94_FNCSEL94_Pos        (0UL)                     /*!< FNCSEL94 (Bit 0)                                      */
#define GPIO_PINCFG94_FNCSEL94_Msk        (0xfUL)                   /*!< FNCSEL94 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG95  ======================================================== */
#define GPIO_PINCFG95_FOEN95_Pos          (27UL)                    /*!< FOEN95 (Bit 27)                                       */
#define GPIO_PINCFG95_FOEN95_Msk          (0x8000000UL)             /*!< FOEN95 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG95_FIEN95_Pos          (26UL)                    /*!< FIEN95 (Bit 26)                                       */
#define GPIO_PINCFG95_FIEN95_Msk          (0x4000000UL)             /*!< FIEN95 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG95_NCEPOL95_Pos        (22UL)                    /*!< NCEPOL95 (Bit 22)                                     */
#define GPIO_PINCFG95_NCEPOL95_Msk        (0x400000UL)              /*!< NCEPOL95 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG95_NCESRC95_Pos        (16UL)                    /*!< NCESRC95 (Bit 16)                                     */
#define GPIO_PINCFG95_NCESRC95_Msk        (0x3f0000UL)              /*!< NCESRC95 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG95_PULLCFG95_Pos       (13UL)                    /*!< PULLCFG95 (Bit 13)                                    */
#define GPIO_PINCFG95_PULLCFG95_Msk       (0xe000UL)                /*!< PULLCFG95 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG95_SR95_Pos            (12UL)                    /*!< SR95 (Bit 12)                                         */
#define GPIO_PINCFG95_SR95_Msk            (0x1000UL)                /*!< SR95 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG95_DS95_Pos            (10UL)                    /*!< DS95 (Bit 10)                                         */
#define GPIO_PINCFG95_DS95_Msk            (0xc00UL)                 /*!< DS95 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG95_OUTCFG95_Pos        (8UL)                     /*!< OUTCFG95 (Bit 8)                                      */
#define GPIO_PINCFG95_OUTCFG95_Msk        (0x300UL)                 /*!< OUTCFG95 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG95_IRPTEN95_Pos        (6UL)                     /*!< IRPTEN95 (Bit 6)                                      */
#define GPIO_PINCFG95_IRPTEN95_Msk        (0xc0UL)                  /*!< IRPTEN95 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG95_RDZERO95_Pos        (5UL)                     /*!< RDZERO95 (Bit 5)                                      */
#define GPIO_PINCFG95_RDZERO95_Msk        (0x20UL)                  /*!< RDZERO95 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG95_INPEN95_Pos         (4UL)                     /*!< INPEN95 (Bit 4)                                       */
#define GPIO_PINCFG95_INPEN95_Msk         (0x10UL)                  /*!< INPEN95 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG95_FNCSEL95_Pos        (0UL)                     /*!< FNCSEL95 (Bit 0)                                      */
#define GPIO_PINCFG95_FNCSEL95_Msk        (0xfUL)                   /*!< FNCSEL95 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG96  ======================================================== */
#define GPIO_PINCFG96_FOEN96_Pos          (27UL)                    /*!< FOEN96 (Bit 27)                                       */
#define GPIO_PINCFG96_FOEN96_Msk          (0x8000000UL)             /*!< FOEN96 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG96_FIEN96_Pos          (26UL)                    /*!< FIEN96 (Bit 26)                                       */
#define GPIO_PINCFG96_FIEN96_Msk          (0x4000000UL)             /*!< FIEN96 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG96_NCEPOL96_Pos        (22UL)                    /*!< NCEPOL96 (Bit 22)                                     */
#define GPIO_PINCFG96_NCEPOL96_Msk        (0x400000UL)              /*!< NCEPOL96 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG96_NCESRC96_Pos        (16UL)                    /*!< NCESRC96 (Bit 16)                                     */
#define GPIO_PINCFG96_NCESRC96_Msk        (0x3f0000UL)              /*!< NCESRC96 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG96_PULLCFG96_Pos       (13UL)                    /*!< PULLCFG96 (Bit 13)                                    */
#define GPIO_PINCFG96_PULLCFG96_Msk       (0xe000UL)                /*!< PULLCFG96 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG96_SR96_Pos            (12UL)                    /*!< SR96 (Bit 12)                                         */
#define GPIO_PINCFG96_SR96_Msk            (0x1000UL)                /*!< SR96 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG96_DS96_Pos            (10UL)                    /*!< DS96 (Bit 10)                                         */
#define GPIO_PINCFG96_DS96_Msk            (0xc00UL)                 /*!< DS96 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG96_OUTCFG96_Pos        (8UL)                     /*!< OUTCFG96 (Bit 8)                                      */
#define GPIO_PINCFG96_OUTCFG96_Msk        (0x300UL)                 /*!< OUTCFG96 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG96_IRPTEN96_Pos        (6UL)                     /*!< IRPTEN96 (Bit 6)                                      */
#define GPIO_PINCFG96_IRPTEN96_Msk        (0xc0UL)                  /*!< IRPTEN96 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG96_RDZERO96_Pos        (5UL)                     /*!< RDZERO96 (Bit 5)                                      */
#define GPIO_PINCFG96_RDZERO96_Msk        (0x20UL)                  /*!< RDZERO96 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG96_INPEN96_Pos         (4UL)                     /*!< INPEN96 (Bit 4)                                       */
#define GPIO_PINCFG96_INPEN96_Msk         (0x10UL)                  /*!< INPEN96 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG96_FNCSEL96_Pos        (0UL)                     /*!< FNCSEL96 (Bit 0)                                      */
#define GPIO_PINCFG96_FNCSEL96_Msk        (0xfUL)                   /*!< FNCSEL96 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG97  ======================================================== */
#define GPIO_PINCFG97_FOEN97_Pos          (27UL)                    /*!< FOEN97 (Bit 27)                                       */
#define GPIO_PINCFG97_FOEN97_Msk          (0x8000000UL)             /*!< FOEN97 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG97_FIEN97_Pos          (26UL)                    /*!< FIEN97 (Bit 26)                                       */
#define GPIO_PINCFG97_FIEN97_Msk          (0x4000000UL)             /*!< FIEN97 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG97_NCEPOL97_Pos        (22UL)                    /*!< NCEPOL97 (Bit 22)                                     */
#define GPIO_PINCFG97_NCEPOL97_Msk        (0x400000UL)              /*!< NCEPOL97 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG97_NCESRC97_Pos        (16UL)                    /*!< NCESRC97 (Bit 16)                                     */
#define GPIO_PINCFG97_NCESRC97_Msk        (0x3f0000UL)              /*!< NCESRC97 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG97_PULLCFG97_Pos       (13UL)                    /*!< PULLCFG97 (Bit 13)                                    */
#define GPIO_PINCFG97_PULLCFG97_Msk       (0xe000UL)                /*!< PULLCFG97 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG97_SR97_Pos            (12UL)                    /*!< SR97 (Bit 12)                                         */
#define GPIO_PINCFG97_SR97_Msk            (0x1000UL)                /*!< SR97 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG97_DS97_Pos            (10UL)                    /*!< DS97 (Bit 10)                                         */
#define GPIO_PINCFG97_DS97_Msk            (0xc00UL)                 /*!< DS97 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG97_OUTCFG97_Pos        (8UL)                     /*!< OUTCFG97 (Bit 8)                                      */
#define GPIO_PINCFG97_OUTCFG97_Msk        (0x300UL)                 /*!< OUTCFG97 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG97_IRPTEN97_Pos        (6UL)                     /*!< IRPTEN97 (Bit 6)                                      */
#define GPIO_PINCFG97_IRPTEN97_Msk        (0xc0UL)                  /*!< IRPTEN97 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG97_RDZERO97_Pos        (5UL)                     /*!< RDZERO97 (Bit 5)                                      */
#define GPIO_PINCFG97_RDZERO97_Msk        (0x20UL)                  /*!< RDZERO97 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG97_INPEN97_Pos         (4UL)                     /*!< INPEN97 (Bit 4)                                       */
#define GPIO_PINCFG97_INPEN97_Msk         (0x10UL)                  /*!< INPEN97 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG97_FNCSEL97_Pos        (0UL)                     /*!< FNCSEL97 (Bit 0)                                      */
#define GPIO_PINCFG97_FNCSEL97_Msk        (0xfUL)                   /*!< FNCSEL97 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG98  ======================================================== */
#define GPIO_PINCFG98_FOEN98_Pos          (27UL)                    /*!< FOEN98 (Bit 27)                                       */
#define GPIO_PINCFG98_FOEN98_Msk          (0x8000000UL)             /*!< FOEN98 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG98_FIEN98_Pos          (26UL)                    /*!< FIEN98 (Bit 26)                                       */
#define GPIO_PINCFG98_FIEN98_Msk          (0x4000000UL)             /*!< FIEN98 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG98_NCEPOL98_Pos        (22UL)                    /*!< NCEPOL98 (Bit 22)                                     */
#define GPIO_PINCFG98_NCEPOL98_Msk        (0x400000UL)              /*!< NCEPOL98 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG98_NCESRC98_Pos        (16UL)                    /*!< NCESRC98 (Bit 16)                                     */
#define GPIO_PINCFG98_NCESRC98_Msk        (0x3f0000UL)              /*!< NCESRC98 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG98_PULLCFG98_Pos       (13UL)                    /*!< PULLCFG98 (Bit 13)                                    */
#define GPIO_PINCFG98_PULLCFG98_Msk       (0xe000UL)                /*!< PULLCFG98 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG98_SR98_Pos            (12UL)                    /*!< SR98 (Bit 12)                                         */
#define GPIO_PINCFG98_SR98_Msk            (0x1000UL)                /*!< SR98 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG98_DS98_Pos            (10UL)                    /*!< DS98 (Bit 10)                                         */
#define GPIO_PINCFG98_DS98_Msk            (0xc00UL)                 /*!< DS98 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG98_OUTCFG98_Pos        (8UL)                     /*!< OUTCFG98 (Bit 8)                                      */
#define GPIO_PINCFG98_OUTCFG98_Msk        (0x300UL)                 /*!< OUTCFG98 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG98_IRPTEN98_Pos        (6UL)                     /*!< IRPTEN98 (Bit 6)                                      */
#define GPIO_PINCFG98_IRPTEN98_Msk        (0xc0UL)                  /*!< IRPTEN98 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG98_RDZERO98_Pos        (5UL)                     /*!< RDZERO98 (Bit 5)                                      */
#define GPIO_PINCFG98_RDZERO98_Msk        (0x20UL)                  /*!< RDZERO98 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG98_INPEN98_Pos         (4UL)                     /*!< INPEN98 (Bit 4)                                       */
#define GPIO_PINCFG98_INPEN98_Msk         (0x10UL)                  /*!< INPEN98 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG98_FNCSEL98_Pos        (0UL)                     /*!< FNCSEL98 (Bit 0)                                      */
#define GPIO_PINCFG98_FNCSEL98_Msk        (0xfUL)                   /*!< FNCSEL98 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG99  ======================================================== */
#define GPIO_PINCFG99_FOEN99_Pos          (27UL)                    /*!< FOEN99 (Bit 27)                                       */
#define GPIO_PINCFG99_FOEN99_Msk          (0x8000000UL)             /*!< FOEN99 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG99_FIEN99_Pos          (26UL)                    /*!< FIEN99 (Bit 26)                                       */
#define GPIO_PINCFG99_FIEN99_Msk          (0x4000000UL)             /*!< FIEN99 (Bitfield-Mask: 0x01)                          */
#define GPIO_PINCFG99_NCEPOL99_Pos        (22UL)                    /*!< NCEPOL99 (Bit 22)                                     */
#define GPIO_PINCFG99_NCEPOL99_Msk        (0x400000UL)              /*!< NCEPOL99 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG99_NCESRC99_Pos        (16UL)                    /*!< NCESRC99 (Bit 16)                                     */
#define GPIO_PINCFG99_NCESRC99_Msk        (0x3f0000UL)              /*!< NCESRC99 (Bitfield-Mask: 0x3f)                        */
#define GPIO_PINCFG99_PULLCFG99_Pos       (13UL)                    /*!< PULLCFG99 (Bit 13)                                    */
#define GPIO_PINCFG99_PULLCFG99_Msk       (0xe000UL)                /*!< PULLCFG99 (Bitfield-Mask: 0x07)                       */
#define GPIO_PINCFG99_SR99_Pos            (12UL)                    /*!< SR99 (Bit 12)                                         */
#define GPIO_PINCFG99_SR99_Msk            (0x1000UL)                /*!< SR99 (Bitfield-Mask: 0x01)                            */
#define GPIO_PINCFG99_DS99_Pos            (10UL)                    /*!< DS99 (Bit 10)                                         */
#define GPIO_PINCFG99_DS99_Msk            (0xc00UL)                 /*!< DS99 (Bitfield-Mask: 0x03)                            */
#define GPIO_PINCFG99_OUTCFG99_Pos        (8UL)                     /*!< OUTCFG99 (Bit 8)                                      */
#define GPIO_PINCFG99_OUTCFG99_Msk        (0x300UL)                 /*!< OUTCFG99 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG99_IRPTEN99_Pos        (6UL)                     /*!< IRPTEN99 (Bit 6)                                      */
#define GPIO_PINCFG99_IRPTEN99_Msk        (0xc0UL)                  /*!< IRPTEN99 (Bitfield-Mask: 0x03)                        */
#define GPIO_PINCFG99_RDZERO99_Pos        (5UL)                     /*!< RDZERO99 (Bit 5)                                      */
#define GPIO_PINCFG99_RDZERO99_Msk        (0x20UL)                  /*!< RDZERO99 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG99_INPEN99_Pos         (4UL)                     /*!< INPEN99 (Bit 4)                                       */
#define GPIO_PINCFG99_INPEN99_Msk         (0x10UL)                  /*!< INPEN99 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG99_FNCSEL99_Pos        (0UL)                     /*!< FNCSEL99 (Bit 0)                                      */
#define GPIO_PINCFG99_FNCSEL99_Msk        (0xfUL)                   /*!< FNCSEL99 (Bitfield-Mask: 0x0f)                        */
/* =======================================================  PINCFG100  ======================================================= */
#define GPIO_PINCFG100_FOEN100_Pos        (27UL)                    /*!< FOEN100 (Bit 27)                                      */
#define GPIO_PINCFG100_FOEN100_Msk        (0x8000000UL)             /*!< FOEN100 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG100_FIEN100_Pos        (26UL)                    /*!< FIEN100 (Bit 26)                                      */
#define GPIO_PINCFG100_FIEN100_Msk        (0x4000000UL)             /*!< FIEN100 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG100_NCEPOL100_Pos      (22UL)                    /*!< NCEPOL100 (Bit 22)                                    */
#define GPIO_PINCFG100_NCEPOL100_Msk      (0x400000UL)              /*!< NCEPOL100 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG100_NCESRC100_Pos      (16UL)                    /*!< NCESRC100 (Bit 16)                                    */
#define GPIO_PINCFG100_NCESRC100_Msk      (0x3f0000UL)              /*!< NCESRC100 (Bitfield-Mask: 0x3f)                       */
#define GPIO_PINCFG100_PULLCFG100_Pos     (13UL)                    /*!< PULLCFG100 (Bit 13)                                   */
#define GPIO_PINCFG100_PULLCFG100_Msk     (0xe000UL)                /*!< PULLCFG100 (Bitfield-Mask: 0x07)                      */
#define GPIO_PINCFG100_SR100_Pos          (12UL)                    /*!< SR100 (Bit 12)                                        */
#define GPIO_PINCFG100_SR100_Msk          (0x1000UL)                /*!< SR100 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG100_DS100_Pos          (10UL)                    /*!< DS100 (Bit 10)                                        */
#define GPIO_PINCFG100_DS100_Msk          (0xc00UL)                 /*!< DS100 (Bitfield-Mask: 0x03)                           */
#define GPIO_PINCFG100_OUTCFG100_Pos      (8UL)                     /*!< OUTCFG100 (Bit 8)                                     */
#define GPIO_PINCFG100_OUTCFG100_Msk      (0x300UL)                 /*!< OUTCFG100 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG100_IRPTEN100_Pos      (6UL)                     /*!< IRPTEN100 (Bit 6)                                     */
#define GPIO_PINCFG100_IRPTEN100_Msk      (0xc0UL)                  /*!< IRPTEN100 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG100_RDZERO100_Pos      (5UL)                     /*!< RDZERO100 (Bit 5)                                     */
#define GPIO_PINCFG100_RDZERO100_Msk      (0x20UL)                  /*!< RDZERO100 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG100_INPEN100_Pos       (4UL)                     /*!< INPEN100 (Bit 4)                                      */
#define GPIO_PINCFG100_INPEN100_Msk       (0x10UL)                  /*!< INPEN100 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG100_FNCSEL100_Pos      (0UL)                     /*!< FNCSEL100 (Bit 0)                                     */
#define GPIO_PINCFG100_FNCSEL100_Msk      (0xfUL)                   /*!< FNCSEL100 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG101  ======================================================= */
#define GPIO_PINCFG101_FOEN101_Pos        (27UL)                    /*!< FOEN101 (Bit 27)                                      */
#define GPIO_PINCFG101_FOEN101_Msk        (0x8000000UL)             /*!< FOEN101 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG101_FIEN101_Pos        (26UL)                    /*!< FIEN101 (Bit 26)                                      */
#define GPIO_PINCFG101_FIEN101_Msk        (0x4000000UL)             /*!< FIEN101 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG101_NCEPOL101_Pos      (22UL)                    /*!< NCEPOL101 (Bit 22)                                    */
#define GPIO_PINCFG101_NCEPOL101_Msk      (0x400000UL)              /*!< NCEPOL101 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG101_NCESRC101_Pos      (16UL)                    /*!< NCESRC101 (Bit 16)                                    */
#define GPIO_PINCFG101_NCESRC101_Msk      (0x3f0000UL)              /*!< NCESRC101 (Bitfield-Mask: 0x3f)                       */
#define GPIO_PINCFG101_PULLCFG101_Pos     (13UL)                    /*!< PULLCFG101 (Bit 13)                                   */
#define GPIO_PINCFG101_PULLCFG101_Msk     (0xe000UL)                /*!< PULLCFG101 (Bitfield-Mask: 0x07)                      */
#define GPIO_PINCFG101_SR101_Pos          (12UL)                    /*!< SR101 (Bit 12)                                        */
#define GPIO_PINCFG101_SR101_Msk          (0x1000UL)                /*!< SR101 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG101_DS101_Pos          (10UL)                    /*!< DS101 (Bit 10)                                        */
#define GPIO_PINCFG101_DS101_Msk          (0xc00UL)                 /*!< DS101 (Bitfield-Mask: 0x03)                           */
#define GPIO_PINCFG101_OUTCFG101_Pos      (8UL)                     /*!< OUTCFG101 (Bit 8)                                     */
#define GPIO_PINCFG101_OUTCFG101_Msk      (0x300UL)                 /*!< OUTCFG101 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG101_IRPTEN101_Pos      (6UL)                     /*!< IRPTEN101 (Bit 6)                                     */
#define GPIO_PINCFG101_IRPTEN101_Msk      (0xc0UL)                  /*!< IRPTEN101 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG101_RDZERO101_Pos      (5UL)                     /*!< RDZERO101 (Bit 5)                                     */
#define GPIO_PINCFG101_RDZERO101_Msk      (0x20UL)                  /*!< RDZERO101 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG101_INPEN101_Pos       (4UL)                     /*!< INPEN101 (Bit 4)                                      */
#define GPIO_PINCFG101_INPEN101_Msk       (0x10UL)                  /*!< INPEN101 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG101_FNCSEL101_Pos      (0UL)                     /*!< FNCSEL101 (Bit 0)                                     */
#define GPIO_PINCFG101_FNCSEL101_Msk      (0xfUL)                   /*!< FNCSEL101 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG102  ======================================================= */
#define GPIO_PINCFG102_FOEN102_Pos        (27UL)                    /*!< FOEN102 (Bit 27)                                      */
#define GPIO_PINCFG102_FOEN102_Msk        (0x8000000UL)             /*!< FOEN102 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG102_FIEN102_Pos        (26UL)                    /*!< FIEN102 (Bit 26)                                      */
#define GPIO_PINCFG102_FIEN102_Msk        (0x4000000UL)             /*!< FIEN102 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG102_NCEPOL102_Pos      (22UL)                    /*!< NCEPOL102 (Bit 22)                                    */
#define GPIO_PINCFG102_NCEPOL102_Msk      (0x400000UL)              /*!< NCEPOL102 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG102_NCESRC102_Pos      (16UL)                    /*!< NCESRC102 (Bit 16)                                    */
#define GPIO_PINCFG102_NCESRC102_Msk      (0x3f0000UL)              /*!< NCESRC102 (Bitfield-Mask: 0x3f)                       */
#define GPIO_PINCFG102_PULLCFG102_Pos     (13UL)                    /*!< PULLCFG102 (Bit 13)                                   */
#define GPIO_PINCFG102_PULLCFG102_Msk     (0xe000UL)                /*!< PULLCFG102 (Bitfield-Mask: 0x07)                      */
#define GPIO_PINCFG102_SR102_Pos          (12UL)                    /*!< SR102 (Bit 12)                                        */
#define GPIO_PINCFG102_SR102_Msk          (0x1000UL)                /*!< SR102 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG102_DS102_Pos          (10UL)                    /*!< DS102 (Bit 10)                                        */
#define GPIO_PINCFG102_DS102_Msk          (0xc00UL)                 /*!< DS102 (Bitfield-Mask: 0x03)                           */
#define GPIO_PINCFG102_OUTCFG102_Pos      (8UL)                     /*!< OUTCFG102 (Bit 8)                                     */
#define GPIO_PINCFG102_OUTCFG102_Msk      (0x300UL)                 /*!< OUTCFG102 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG102_IRPTEN102_Pos      (6UL)                     /*!< IRPTEN102 (Bit 6)                                     */
#define GPIO_PINCFG102_IRPTEN102_Msk      (0xc0UL)                  /*!< IRPTEN102 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG102_RDZERO102_Pos      (5UL)                     /*!< RDZERO102 (Bit 5)                                     */
#define GPIO_PINCFG102_RDZERO102_Msk      (0x20UL)                  /*!< RDZERO102 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG102_INPEN102_Pos       (4UL)                     /*!< INPEN102 (Bit 4)                                      */
#define GPIO_PINCFG102_INPEN102_Msk       (0x10UL)                  /*!< INPEN102 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG102_FNCSEL102_Pos      (0UL)                     /*!< FNCSEL102 (Bit 0)                                     */
#define GPIO_PINCFG102_FNCSEL102_Msk      (0xfUL)                   /*!< FNCSEL102 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG103  ======================================================= */
#define GPIO_PINCFG103_FOEN103_Pos        (27UL)                    /*!< FOEN103 (Bit 27)                                      */
#define GPIO_PINCFG103_FOEN103_Msk        (0x8000000UL)             /*!< FOEN103 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG103_FIEN103_Pos        (26UL)                    /*!< FIEN103 (Bit 26)                                      */
#define GPIO_PINCFG103_FIEN103_Msk        (0x4000000UL)             /*!< FIEN103 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG103_NCEPOL103_Pos      (22UL)                    /*!< NCEPOL103 (Bit 22)                                    */
#define GPIO_PINCFG103_NCEPOL103_Msk      (0x400000UL)              /*!< NCEPOL103 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG103_NCESRC103_Pos      (16UL)                    /*!< NCESRC103 (Bit 16)                                    */
#define GPIO_PINCFG103_NCESRC103_Msk      (0x3f0000UL)              /*!< NCESRC103 (Bitfield-Mask: 0x3f)                       */
#define GPIO_PINCFG103_PULLCFG103_Pos     (13UL)                    /*!< PULLCFG103 (Bit 13)                                   */
#define GPIO_PINCFG103_PULLCFG103_Msk     (0xe000UL)                /*!< PULLCFG103 (Bitfield-Mask: 0x07)                      */
#define GPIO_PINCFG103_SR103_Pos          (12UL)                    /*!< SR103 (Bit 12)                                        */
#define GPIO_PINCFG103_SR103_Msk          (0x1000UL)                /*!< SR103 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG103_DS103_Pos          (10UL)                    /*!< DS103 (Bit 10)                                        */
#define GPIO_PINCFG103_DS103_Msk          (0xc00UL)                 /*!< DS103 (Bitfield-Mask: 0x03)                           */
#define GPIO_PINCFG103_OUTCFG103_Pos      (8UL)                     /*!< OUTCFG103 (Bit 8)                                     */
#define GPIO_PINCFG103_OUTCFG103_Msk      (0x300UL)                 /*!< OUTCFG103 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG103_IRPTEN103_Pos      (6UL)                     /*!< IRPTEN103 (Bit 6)                                     */
#define GPIO_PINCFG103_IRPTEN103_Msk      (0xc0UL)                  /*!< IRPTEN103 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG103_RDZERO103_Pos      (5UL)                     /*!< RDZERO103 (Bit 5)                                     */
#define GPIO_PINCFG103_RDZERO103_Msk      (0x20UL)                  /*!< RDZERO103 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG103_INPEN103_Pos       (4UL)                     /*!< INPEN103 (Bit 4)                                      */
#define GPIO_PINCFG103_INPEN103_Msk       (0x10UL)                  /*!< INPEN103 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG103_FNCSEL103_Pos      (0UL)                     /*!< FNCSEL103 (Bit 0)                                     */
#define GPIO_PINCFG103_FNCSEL103_Msk      (0xfUL)                   /*!< FNCSEL103 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG104  ======================================================= */
#define GPIO_PINCFG104_FOEN104_Pos        (27UL)                    /*!< FOEN104 (Bit 27)                                      */
#define GPIO_PINCFG104_FOEN104_Msk        (0x8000000UL)             /*!< FOEN104 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG104_FIEN104_Pos        (26UL)                    /*!< FIEN104 (Bit 26)                                      */
#define GPIO_PINCFG104_FIEN104_Msk        (0x4000000UL)             /*!< FIEN104 (Bitfield-Mask: 0x01)                         */
#define GPIO_PINCFG104_NCEPOL104_Pos      (22UL)                    /*!< NCEPOL104 (Bit 22)                                    */
#define GPIO_PINCFG104_NCEPOL104_Msk      (0x400000UL)              /*!< NCEPOL104 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG104_NCESRC104_Pos      (16UL)                    /*!< NCESRC104 (Bit 16)                                    */
#define GPIO_PINCFG104_NCESRC104_Msk      (0x3f0000UL)              /*!< NCESRC104 (Bitfield-Mask: 0x3f)                       */
#define GPIO_PINCFG104_PULLCFG104_Pos     (13UL)                    /*!< PULLCFG104 (Bit 13)                                   */
#define GPIO_PINCFG104_PULLCFG104_Msk     (0xe000UL)                /*!< PULLCFG104 (Bitfield-Mask: 0x07)                      */
#define GPIO_PINCFG104_SR104_Pos          (12UL)                    /*!< SR104 (Bit 12)                                        */
#define GPIO_PINCFG104_SR104_Msk          (0x1000UL)                /*!< SR104 (Bitfield-Mask: 0x01)                           */
#define GPIO_PINCFG104_DS104_Pos          (10UL)                    /*!< DS104 (Bit 10)                                        */
#define GPIO_PINCFG104_DS104_Msk          (0xc00UL)                 /*!< DS104 (Bitfield-Mask: 0x03)                           */
#define GPIO_PINCFG104_OUTCFG104_Pos      (8UL)                     /*!< OUTCFG104 (Bit 8)                                     */
#define GPIO_PINCFG104_OUTCFG104_Msk      (0x300UL)                 /*!< OUTCFG104 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG104_IRPTEN104_Pos      (6UL)                     /*!< IRPTEN104 (Bit 6)                                     */
#define GPIO_PINCFG104_IRPTEN104_Msk      (0xc0UL)                  /*!< IRPTEN104 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG104_RDZERO104_Pos      (5UL)                     /*!< RDZERO104 (Bit 5)                                     */
#define GPIO_PINCFG104_RDZERO104_Msk      (0x20UL)                  /*!< RDZERO104 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG104_INPEN104_Pos       (4UL)                     /*!< INPEN104 (Bit 4)                                      */
#define GPIO_PINCFG104_INPEN104_Msk       (0x10UL)                  /*!< INPEN104 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG104_FNCSEL104_Pos      (0UL)                     /*!< FNCSEL104 (Bit 0)                                     */
#define GPIO_PINCFG104_FNCSEL104_Msk      (0xfUL)                   /*!< FNCSEL104 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG105  ======================================================= */
#define GPIO_PINCFG105_OUTCFG105_Pos      (8UL)                     /*!< OUTCFG105 (Bit 8)                                     */
#define GPIO_PINCFG105_OUTCFG105_Msk      (0x300UL)                 /*!< OUTCFG105 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG105_IRPTEN105_Pos      (6UL)                     /*!< IRPTEN105 (Bit 6)                                     */
#define GPIO_PINCFG105_IRPTEN105_Msk      (0xc0UL)                  /*!< IRPTEN105 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG105_RDZERO105_Pos      (5UL)                     /*!< RDZERO105 (Bit 5)                                     */
#define GPIO_PINCFG105_RDZERO105_Msk      (0x20UL)                  /*!< RDZERO105 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG105_INPEN105_Pos       (4UL)                     /*!< INPEN105 (Bit 4)                                      */
#define GPIO_PINCFG105_INPEN105_Msk       (0x10UL)                  /*!< INPEN105 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG105_FNCSEL105_Pos      (0UL)                     /*!< FNCSEL105 (Bit 0)                                     */
#define GPIO_PINCFG105_FNCSEL105_Msk      (0xfUL)                   /*!< FNCSEL105 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG106  ======================================================= */
#define GPIO_PINCFG106_OUTCFG106_Pos      (8UL)                     /*!< OUTCFG106 (Bit 8)                                     */
#define GPIO_PINCFG106_OUTCFG106_Msk      (0x300UL)                 /*!< OUTCFG106 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG106_IRPTEN106_Pos      (6UL)                     /*!< IRPTEN106 (Bit 6)                                     */
#define GPIO_PINCFG106_IRPTEN106_Msk      (0xc0UL)                  /*!< IRPTEN106 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG106_RDZERO106_Pos      (5UL)                     /*!< RDZERO106 (Bit 5)                                     */
#define GPIO_PINCFG106_RDZERO106_Msk      (0x20UL)                  /*!< RDZERO106 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG106_INPEN106_Pos       (4UL)                     /*!< INPEN106 (Bit 4)                                      */
#define GPIO_PINCFG106_INPEN106_Msk       (0x10UL)                  /*!< INPEN106 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG106_FNCSEL106_Pos      (0UL)                     /*!< FNCSEL106 (Bit 0)                                     */
#define GPIO_PINCFG106_FNCSEL106_Msk      (0xfUL)                   /*!< FNCSEL106 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG107  ======================================================= */
#define GPIO_PINCFG107_OUTCFG107_Pos      (8UL)                     /*!< OUTCFG107 (Bit 8)                                     */
#define GPIO_PINCFG107_OUTCFG107_Msk      (0x300UL)                 /*!< OUTCFG107 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG107_IRPTEN107_Pos      (6UL)                     /*!< IRPTEN107 (Bit 6)                                     */
#define GPIO_PINCFG107_IRPTEN107_Msk      (0xc0UL)                  /*!< IRPTEN107 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG107_RDZERO107_Pos      (5UL)                     /*!< RDZERO107 (Bit 5)                                     */
#define GPIO_PINCFG107_RDZERO107_Msk      (0x20UL)                  /*!< RDZERO107 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG107_INPEN107_Pos       (4UL)                     /*!< INPEN107 (Bit 4)                                      */
#define GPIO_PINCFG107_INPEN107_Msk       (0x10UL)                  /*!< INPEN107 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG107_FNCSEL107_Pos      (0UL)                     /*!< FNCSEL107 (Bit 0)                                     */
#define GPIO_PINCFG107_FNCSEL107_Msk      (0xfUL)                   /*!< FNCSEL107 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG108  ======================================================= */
#define GPIO_PINCFG108_OUTCFG108_Pos      (8UL)                     /*!< OUTCFG108 (Bit 8)                                     */
#define GPIO_PINCFG108_OUTCFG108_Msk      (0x300UL)                 /*!< OUTCFG108 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG108_IRPTEN108_Pos      (6UL)                     /*!< IRPTEN108 (Bit 6)                                     */
#define GPIO_PINCFG108_IRPTEN108_Msk      (0xc0UL)                  /*!< IRPTEN108 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG108_RDZERO108_Pos      (5UL)                     /*!< RDZERO108 (Bit 5)                                     */
#define GPIO_PINCFG108_RDZERO108_Msk      (0x20UL)                  /*!< RDZERO108 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG108_INPEN108_Pos       (4UL)                     /*!< INPEN108 (Bit 4)                                      */
#define GPIO_PINCFG108_INPEN108_Msk       (0x10UL)                  /*!< INPEN108 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG108_FNCSEL108_Pos      (0UL)                     /*!< FNCSEL108 (Bit 0)                                     */
#define GPIO_PINCFG108_FNCSEL108_Msk      (0xfUL)                   /*!< FNCSEL108 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG109  ======================================================= */
#define GPIO_PINCFG109_OUTCFG109_Pos      (8UL)                     /*!< OUTCFG109 (Bit 8)                                     */
#define GPIO_PINCFG109_OUTCFG109_Msk      (0x300UL)                 /*!< OUTCFG109 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG109_IRPTEN109_Pos      (6UL)                     /*!< IRPTEN109 (Bit 6)                                     */
#define GPIO_PINCFG109_IRPTEN109_Msk      (0xc0UL)                  /*!< IRPTEN109 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG109_RDZERO109_Pos      (5UL)                     /*!< RDZERO109 (Bit 5)                                     */
#define GPIO_PINCFG109_RDZERO109_Msk      (0x20UL)                  /*!< RDZERO109 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG109_INPEN109_Pos       (4UL)                     /*!< INPEN109 (Bit 4)                                      */
#define GPIO_PINCFG109_INPEN109_Msk       (0x10UL)                  /*!< INPEN109 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG109_FNCSEL109_Pos      (0UL)                     /*!< FNCSEL109 (Bit 0)                                     */
#define GPIO_PINCFG109_FNCSEL109_Msk      (0xfUL)                   /*!< FNCSEL109 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG110  ======================================================= */
#define GPIO_PINCFG110_OUTCFG110_Pos      (8UL)                     /*!< OUTCFG110 (Bit 8)                                     */
#define GPIO_PINCFG110_OUTCFG110_Msk      (0x300UL)                 /*!< OUTCFG110 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG110_IRPTEN110_Pos      (6UL)                     /*!< IRPTEN110 (Bit 6)                                     */
#define GPIO_PINCFG110_IRPTEN110_Msk      (0xc0UL)                  /*!< IRPTEN110 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG110_RDZERO110_Pos      (5UL)                     /*!< RDZERO110 (Bit 5)                                     */
#define GPIO_PINCFG110_RDZERO110_Msk      (0x20UL)                  /*!< RDZERO110 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG110_INPEN110_Pos       (4UL)                     /*!< INPEN110 (Bit 4)                                      */
#define GPIO_PINCFG110_INPEN110_Msk       (0x10UL)                  /*!< INPEN110 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG110_FNCSEL110_Pos      (0UL)                     /*!< FNCSEL110 (Bit 0)                                     */
#define GPIO_PINCFG110_FNCSEL110_Msk      (0xfUL)                   /*!< FNCSEL110 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG111  ======================================================= */
#define GPIO_PINCFG111_OUTCFG111_Pos      (8UL)                     /*!< OUTCFG111 (Bit 8)                                     */
#define GPIO_PINCFG111_OUTCFG111_Msk      (0x300UL)                 /*!< OUTCFG111 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG111_IRPTEN111_Pos      (6UL)                     /*!< IRPTEN111 (Bit 6)                                     */
#define GPIO_PINCFG111_IRPTEN111_Msk      (0xc0UL)                  /*!< IRPTEN111 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG111_RDZERO111_Pos      (5UL)                     /*!< RDZERO111 (Bit 5)                                     */
#define GPIO_PINCFG111_RDZERO111_Msk      (0x20UL)                  /*!< RDZERO111 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG111_INPEN111_Pos       (4UL)                     /*!< INPEN111 (Bit 4)                                      */
#define GPIO_PINCFG111_INPEN111_Msk       (0x10UL)                  /*!< INPEN111 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG111_FNCSEL111_Pos      (0UL)                     /*!< FNCSEL111 (Bit 0)                                     */
#define GPIO_PINCFG111_FNCSEL111_Msk      (0xfUL)                   /*!< FNCSEL111 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG112  ======================================================= */
#define GPIO_PINCFG112_OUTCFG112_Pos      (8UL)                     /*!< OUTCFG112 (Bit 8)                                     */
#define GPIO_PINCFG112_OUTCFG112_Msk      (0x300UL)                 /*!< OUTCFG112 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG112_IRPTEN112_Pos      (6UL)                     /*!< IRPTEN112 (Bit 6)                                     */
#define GPIO_PINCFG112_IRPTEN112_Msk      (0xc0UL)                  /*!< IRPTEN112 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG112_RDZERO112_Pos      (5UL)                     /*!< RDZERO112 (Bit 5)                                     */
#define GPIO_PINCFG112_RDZERO112_Msk      (0x20UL)                  /*!< RDZERO112 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG112_INPEN112_Pos       (4UL)                     /*!< INPEN112 (Bit 4)                                      */
#define GPIO_PINCFG112_INPEN112_Msk       (0x10UL)                  /*!< INPEN112 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG112_FNCSEL112_Pos      (0UL)                     /*!< FNCSEL112 (Bit 0)                                     */
#define GPIO_PINCFG112_FNCSEL112_Msk      (0xfUL)                   /*!< FNCSEL112 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG113  ======================================================= */
#define GPIO_PINCFG113_OUTCFG113_Pos      (8UL)                     /*!< OUTCFG113 (Bit 8)                                     */
#define GPIO_PINCFG113_OUTCFG113_Msk      (0x300UL)                 /*!< OUTCFG113 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG113_IRPTEN113_Pos      (6UL)                     /*!< IRPTEN113 (Bit 6)                                     */
#define GPIO_PINCFG113_IRPTEN113_Msk      (0xc0UL)                  /*!< IRPTEN113 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG113_RDZERO113_Pos      (5UL)                     /*!< RDZERO113 (Bit 5)                                     */
#define GPIO_PINCFG113_RDZERO113_Msk      (0x20UL)                  /*!< RDZERO113 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG113_INPEN113_Pos       (4UL)                     /*!< INPEN113 (Bit 4)                                      */
#define GPIO_PINCFG113_INPEN113_Msk       (0x10UL)                  /*!< INPEN113 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG113_FNCSEL113_Pos      (0UL)                     /*!< FNCSEL113 (Bit 0)                                     */
#define GPIO_PINCFG113_FNCSEL113_Msk      (0xfUL)                   /*!< FNCSEL113 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG114  ======================================================= */
#define GPIO_PINCFG114_OUTCFG114_Pos      (8UL)                     /*!< OUTCFG114 (Bit 8)                                     */
#define GPIO_PINCFG114_OUTCFG114_Msk      (0x300UL)                 /*!< OUTCFG114 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG114_IRPTEN114_Pos      (6UL)                     /*!< IRPTEN114 (Bit 6)                                     */
#define GPIO_PINCFG114_IRPTEN114_Msk      (0xc0UL)                  /*!< IRPTEN114 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG114_RDZERO114_Pos      (5UL)                     /*!< RDZERO114 (Bit 5)                                     */
#define GPIO_PINCFG114_RDZERO114_Msk      (0x20UL)                  /*!< RDZERO114 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG114_INPEN114_Pos       (4UL)                     /*!< INPEN114 (Bit 4)                                      */
#define GPIO_PINCFG114_INPEN114_Msk       (0x10UL)                  /*!< INPEN114 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG114_FNCSEL114_Pos      (0UL)                     /*!< FNCSEL114 (Bit 0)                                     */
#define GPIO_PINCFG114_FNCSEL114_Msk      (0xfUL)                   /*!< FNCSEL114 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG115  ======================================================= */
#define GPIO_PINCFG115_OUTCFG115_Pos      (8UL)                     /*!< OUTCFG115 (Bit 8)                                     */
#define GPIO_PINCFG115_OUTCFG115_Msk      (0x300UL)                 /*!< OUTCFG115 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG115_IRPTEN115_Pos      (6UL)                     /*!< IRPTEN115 (Bit 6)                                     */
#define GPIO_PINCFG115_IRPTEN115_Msk      (0xc0UL)                  /*!< IRPTEN115 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG115_RDZERO115_Pos      (5UL)                     /*!< RDZERO115 (Bit 5)                                     */
#define GPIO_PINCFG115_RDZERO115_Msk      (0x20UL)                  /*!< RDZERO115 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG115_INPEN115_Pos       (4UL)                     /*!< INPEN115 (Bit 4)                                      */
#define GPIO_PINCFG115_INPEN115_Msk       (0x10UL)                  /*!< INPEN115 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG115_FNCSEL115_Pos      (0UL)                     /*!< FNCSEL115 (Bit 0)                                     */
#define GPIO_PINCFG115_FNCSEL115_Msk      (0xfUL)                   /*!< FNCSEL115 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG116  ======================================================= */
#define GPIO_PINCFG116_OUTCFG116_Pos      (8UL)                     /*!< OUTCFG116 (Bit 8)                                     */
#define GPIO_PINCFG116_OUTCFG116_Msk      (0x300UL)                 /*!< OUTCFG116 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG116_IRPTEN116_Pos      (6UL)                     /*!< IRPTEN116 (Bit 6)                                     */
#define GPIO_PINCFG116_IRPTEN116_Msk      (0xc0UL)                  /*!< IRPTEN116 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG116_RDZERO116_Pos      (5UL)                     /*!< RDZERO116 (Bit 5)                                     */
#define GPIO_PINCFG116_RDZERO116_Msk      (0x20UL)                  /*!< RDZERO116 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG116_INPEN116_Pos       (4UL)                     /*!< INPEN116 (Bit 4)                                      */
#define GPIO_PINCFG116_INPEN116_Msk       (0x10UL)                  /*!< INPEN116 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG116_FNCSEL116_Pos      (0UL)                     /*!< FNCSEL116 (Bit 0)                                     */
#define GPIO_PINCFG116_FNCSEL116_Msk      (0xfUL)                   /*!< FNCSEL116 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG117  ======================================================= */
#define GPIO_PINCFG117_OUTCFG117_Pos      (8UL)                     /*!< OUTCFG117 (Bit 8)                                     */
#define GPIO_PINCFG117_OUTCFG117_Msk      (0x300UL)                 /*!< OUTCFG117 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG117_IRPTEN117_Pos      (6UL)                     /*!< IRPTEN117 (Bit 6)                                     */
#define GPIO_PINCFG117_IRPTEN117_Msk      (0xc0UL)                  /*!< IRPTEN117 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG117_RDZERO117_Pos      (5UL)                     /*!< RDZERO117 (Bit 5)                                     */
#define GPIO_PINCFG117_RDZERO117_Msk      (0x20UL)                  /*!< RDZERO117 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG117_INPEN117_Pos       (4UL)                     /*!< INPEN117 (Bit 4)                                      */
#define GPIO_PINCFG117_INPEN117_Msk       (0x10UL)                  /*!< INPEN117 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG117_FNCSEL117_Pos      (0UL)                     /*!< FNCSEL117 (Bit 0)                                     */
#define GPIO_PINCFG117_FNCSEL117_Msk      (0xfUL)                   /*!< FNCSEL117 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG118  ======================================================= */
#define GPIO_PINCFG118_OUTCFG118_Pos      (8UL)                     /*!< OUTCFG118 (Bit 8)                                     */
#define GPIO_PINCFG118_OUTCFG118_Msk      (0x300UL)                 /*!< OUTCFG118 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG118_IRPTEN118_Pos      (6UL)                     /*!< IRPTEN118 (Bit 6)                                     */
#define GPIO_PINCFG118_IRPTEN118_Msk      (0xc0UL)                  /*!< IRPTEN118 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG118_RDZERO118_Pos      (5UL)                     /*!< RDZERO118 (Bit 5)                                     */
#define GPIO_PINCFG118_RDZERO118_Msk      (0x20UL)                  /*!< RDZERO118 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG118_INPEN118_Pos       (4UL)                     /*!< INPEN118 (Bit 4)                                      */
#define GPIO_PINCFG118_INPEN118_Msk       (0x10UL)                  /*!< INPEN118 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG118_FNCSEL118_Pos      (0UL)                     /*!< FNCSEL118 (Bit 0)                                     */
#define GPIO_PINCFG118_FNCSEL118_Msk      (0xfUL)                   /*!< FNCSEL118 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG119  ======================================================= */
#define GPIO_PINCFG119_OUTCFG119_Pos      (8UL)                     /*!< OUTCFG119 (Bit 8)                                     */
#define GPIO_PINCFG119_OUTCFG119_Msk      (0x300UL)                 /*!< OUTCFG119 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG119_IRPTEN119_Pos      (6UL)                     /*!< IRPTEN119 (Bit 6)                                     */
#define GPIO_PINCFG119_IRPTEN119_Msk      (0xc0UL)                  /*!< IRPTEN119 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG119_RDZERO119_Pos      (5UL)                     /*!< RDZERO119 (Bit 5)                                     */
#define GPIO_PINCFG119_RDZERO119_Msk      (0x20UL)                  /*!< RDZERO119 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG119_INPEN119_Pos       (4UL)                     /*!< INPEN119 (Bit 4)                                      */
#define GPIO_PINCFG119_INPEN119_Msk       (0x10UL)                  /*!< INPEN119 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG119_FNCSEL119_Pos      (0UL)                     /*!< FNCSEL119 (Bit 0)                                     */
#define GPIO_PINCFG119_FNCSEL119_Msk      (0xfUL)                   /*!< FNCSEL119 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG120  ======================================================= */
#define GPIO_PINCFG120_OUTCFG120_Pos      (8UL)                     /*!< OUTCFG120 (Bit 8)                                     */
#define GPIO_PINCFG120_OUTCFG120_Msk      (0x300UL)                 /*!< OUTCFG120 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG120_IRPTEN120_Pos      (6UL)                     /*!< IRPTEN120 (Bit 6)                                     */
#define GPIO_PINCFG120_IRPTEN120_Msk      (0xc0UL)                  /*!< IRPTEN120 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG120_RDZERO120_Pos      (5UL)                     /*!< RDZERO120 (Bit 5)                                     */
#define GPIO_PINCFG120_RDZERO120_Msk      (0x20UL)                  /*!< RDZERO120 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG120_INPEN120_Pos       (4UL)                     /*!< INPEN120 (Bit 4)                                      */
#define GPIO_PINCFG120_INPEN120_Msk       (0x10UL)                  /*!< INPEN120 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG120_FNCSEL120_Pos      (0UL)                     /*!< FNCSEL120 (Bit 0)                                     */
#define GPIO_PINCFG120_FNCSEL120_Msk      (0xfUL)                   /*!< FNCSEL120 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG121  ======================================================= */
#define GPIO_PINCFG121_OUTCFG121_Pos      (8UL)                     /*!< OUTCFG121 (Bit 8)                                     */
#define GPIO_PINCFG121_OUTCFG121_Msk      (0x300UL)                 /*!< OUTCFG121 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG121_IRPTEN121_Pos      (6UL)                     /*!< IRPTEN121 (Bit 6)                                     */
#define GPIO_PINCFG121_IRPTEN121_Msk      (0xc0UL)                  /*!< IRPTEN121 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG121_RDZERO121_Pos      (5UL)                     /*!< RDZERO121 (Bit 5)                                     */
#define GPIO_PINCFG121_RDZERO121_Msk      (0x20UL)                  /*!< RDZERO121 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG121_INPEN121_Pos       (4UL)                     /*!< INPEN121 (Bit 4)                                      */
#define GPIO_PINCFG121_INPEN121_Msk       (0x10UL)                  /*!< INPEN121 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG121_FNCSEL121_Pos      (0UL)                     /*!< FNCSEL121 (Bit 0)                                     */
#define GPIO_PINCFG121_FNCSEL121_Msk      (0xfUL)                   /*!< FNCSEL121 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG122  ======================================================= */
#define GPIO_PINCFG122_OUTCFG122_Pos      (8UL)                     /*!< OUTCFG122 (Bit 8)                                     */
#define GPIO_PINCFG122_OUTCFG122_Msk      (0x300UL)                 /*!< OUTCFG122 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG122_IRPTEN122_Pos      (6UL)                     /*!< IRPTEN122 (Bit 6)                                     */
#define GPIO_PINCFG122_IRPTEN122_Msk      (0xc0UL)                  /*!< IRPTEN122 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG122_RDZERO122_Pos      (5UL)                     /*!< RDZERO122 (Bit 5)                                     */
#define GPIO_PINCFG122_RDZERO122_Msk      (0x20UL)                  /*!< RDZERO122 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG122_INPEN122_Pos       (4UL)                     /*!< INPEN122 (Bit 4)                                      */
#define GPIO_PINCFG122_INPEN122_Msk       (0x10UL)                  /*!< INPEN122 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG122_FNCSEL122_Pos      (0UL)                     /*!< FNCSEL122 (Bit 0)                                     */
#define GPIO_PINCFG122_FNCSEL122_Msk      (0xfUL)                   /*!< FNCSEL122 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG123  ======================================================= */
#define GPIO_PINCFG123_OUTCFG123_Pos      (8UL)                     /*!< OUTCFG123 (Bit 8)                                     */
#define GPIO_PINCFG123_OUTCFG123_Msk      (0x300UL)                 /*!< OUTCFG123 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG123_IRPTEN123_Pos      (6UL)                     /*!< IRPTEN123 (Bit 6)                                     */
#define GPIO_PINCFG123_IRPTEN123_Msk      (0xc0UL)                  /*!< IRPTEN123 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG123_RDZERO123_Pos      (5UL)                     /*!< RDZERO123 (Bit 5)                                     */
#define GPIO_PINCFG123_RDZERO123_Msk      (0x20UL)                  /*!< RDZERO123 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG123_INPEN123_Pos       (4UL)                     /*!< INPEN123 (Bit 4)                                      */
#define GPIO_PINCFG123_INPEN123_Msk       (0x10UL)                  /*!< INPEN123 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG123_FNCSEL123_Pos      (0UL)                     /*!< FNCSEL123 (Bit 0)                                     */
#define GPIO_PINCFG123_FNCSEL123_Msk      (0xfUL)                   /*!< FNCSEL123 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG124  ======================================================= */
#define GPIO_PINCFG124_OUTCFG124_Pos      (8UL)                     /*!< OUTCFG124 (Bit 8)                                     */
#define GPIO_PINCFG124_OUTCFG124_Msk      (0x300UL)                 /*!< OUTCFG124 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG124_IRPTEN124_Pos      (6UL)                     /*!< IRPTEN124 (Bit 6)                                     */
#define GPIO_PINCFG124_IRPTEN124_Msk      (0xc0UL)                  /*!< IRPTEN124 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG124_RDZERO124_Pos      (5UL)                     /*!< RDZERO124 (Bit 5)                                     */
#define GPIO_PINCFG124_RDZERO124_Msk      (0x20UL)                  /*!< RDZERO124 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG124_INPEN124_Pos       (4UL)                     /*!< INPEN124 (Bit 4)                                      */
#define GPIO_PINCFG124_INPEN124_Msk       (0x10UL)                  /*!< INPEN124 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG124_FNCSEL124_Pos      (0UL)                     /*!< FNCSEL124 (Bit 0)                                     */
#define GPIO_PINCFG124_FNCSEL124_Msk      (0xfUL)                   /*!< FNCSEL124 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG125  ======================================================= */
#define GPIO_PINCFG125_OUTCFG125_Pos      (8UL)                     /*!< OUTCFG125 (Bit 8)                                     */
#define GPIO_PINCFG125_OUTCFG125_Msk      (0x300UL)                 /*!< OUTCFG125 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG125_IRPTEN125_Pos      (6UL)                     /*!< IRPTEN125 (Bit 6)                                     */
#define GPIO_PINCFG125_IRPTEN125_Msk      (0xc0UL)                  /*!< IRPTEN125 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG125_RDZERO125_Pos      (5UL)                     /*!< RDZERO125 (Bit 5)                                     */
#define GPIO_PINCFG125_RDZERO125_Msk      (0x20UL)                  /*!< RDZERO125 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG125_INPEN125_Pos       (4UL)                     /*!< INPEN125 (Bit 4)                                      */
#define GPIO_PINCFG125_INPEN125_Msk       (0x10UL)                  /*!< INPEN125 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG125_FNCSEL125_Pos      (0UL)                     /*!< FNCSEL125 (Bit 0)                                     */
#define GPIO_PINCFG125_FNCSEL125_Msk      (0xfUL)                   /*!< FNCSEL125 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG126  ======================================================= */
#define GPIO_PINCFG126_OUTCFG126_Pos      (8UL)                     /*!< OUTCFG126 (Bit 8)                                     */
#define GPIO_PINCFG126_OUTCFG126_Msk      (0x300UL)                 /*!< OUTCFG126 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG126_IRPTEN126_Pos      (6UL)                     /*!< IRPTEN126 (Bit 6)                                     */
#define GPIO_PINCFG126_IRPTEN126_Msk      (0xc0UL)                  /*!< IRPTEN126 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG126_RDZERO126_Pos      (5UL)                     /*!< RDZERO126 (Bit 5)                                     */
#define GPIO_PINCFG126_RDZERO126_Msk      (0x20UL)                  /*!< RDZERO126 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG126_INPEN126_Pos       (4UL)                     /*!< INPEN126 (Bit 4)                                      */
#define GPIO_PINCFG126_INPEN126_Msk       (0x10UL)                  /*!< INPEN126 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG126_FNCSEL126_Pos      (0UL)                     /*!< FNCSEL126 (Bit 0)                                     */
#define GPIO_PINCFG126_FNCSEL126_Msk      (0xfUL)                   /*!< FNCSEL126 (Bitfield-Mask: 0x0f)                       */
/* =======================================================  PINCFG127  ======================================================= */
#define GPIO_PINCFG127_OUTCFG127_Pos      (8UL)                     /*!< OUTCFG127 (Bit 8)                                     */
#define GPIO_PINCFG127_OUTCFG127_Msk      (0x300UL)                 /*!< OUTCFG127 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG127_IRPTEN127_Pos      (6UL)                     /*!< IRPTEN127 (Bit 6)                                     */
#define GPIO_PINCFG127_IRPTEN127_Msk      (0xc0UL)                  /*!< IRPTEN127 (Bitfield-Mask: 0x03)                       */
#define GPIO_PINCFG127_RDZERO127_Pos      (5UL)                     /*!< RDZERO127 (Bit 5)                                     */
#define GPIO_PINCFG127_RDZERO127_Msk      (0x20UL)                  /*!< RDZERO127 (Bitfield-Mask: 0x01)                       */
#define GPIO_PINCFG127_INPEN127_Pos       (4UL)                     /*!< INPEN127 (Bit 4)                                      */
#define GPIO_PINCFG127_INPEN127_Msk       (0x10UL)                  /*!< INPEN127 (Bitfield-Mask: 0x01)                        */
#define GPIO_PINCFG127_FNCSEL127_Pos      (0UL)                     /*!< FNCSEL127 (Bit 0)                                     */
#define GPIO_PINCFG127_FNCSEL127_Msk      (0xfUL)                   /*!< FNCSEL127 (Bitfield-Mask: 0x0f)                       */
/* ========================================================  PADKEY  ========================================================= */
#define GPIO_PADKEY_PADKEY_Pos            (0UL)                     /*!< PADKEY (Bit 0)                                        */
#define GPIO_PADKEY_PADKEY_Msk            (0xffffffffUL)            /*!< PADKEY (Bitfield-Mask: 0xffffffff)                    */
/* ==========================================================  RD0  ========================================================== */
#define GPIO_RD0_RD0_Pos                  (0UL)                     /*!< RD0 (Bit 0)                                           */
#define GPIO_RD0_RD0_Msk                  (0xffffffffUL)            /*!< RD0 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  RD1  ========================================================== */
#define GPIO_RD1_RD1_Pos                  (0UL)                     /*!< RD1 (Bit 0)                                           */
#define GPIO_RD1_RD1_Msk                  (0xffffffffUL)            /*!< RD1 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  RD2  ========================================================== */
#define GPIO_RD2_RD2_Pos                  (0UL)                     /*!< RD2 (Bit 0)                                           */
#define GPIO_RD2_RD2_Msk                  (0xffffffffUL)            /*!< RD2 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  RD3  ========================================================== */
#define GPIO_RD3_RD3_Pos                  (0UL)                     /*!< RD3 (Bit 0)                                           */
#define GPIO_RD3_RD3_Msk                  (0xffffffffUL)            /*!< RD3 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  WT0  ========================================================== */
#define GPIO_WT0_WT0_Pos                  (0UL)                     /*!< WT0 (Bit 0)                                           */
#define GPIO_WT0_WT0_Msk                  (0xffffffffUL)            /*!< WT0 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  WT1  ========================================================== */
#define GPIO_WT1_WT1_Pos                  (0UL)                     /*!< WT1 (Bit 0)                                           */
#define GPIO_WT1_WT1_Msk                  (0xffffffffUL)            /*!< WT1 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  WT2  ========================================================== */
#define GPIO_WT2_WT2_Pos                  (0UL)                     /*!< WT2 (Bit 0)                                           */
#define GPIO_WT2_WT2_Msk                  (0xffffffffUL)            /*!< WT2 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  WT3  ========================================================== */
#define GPIO_WT3_WT3_Pos                  (0UL)                     /*!< WT3 (Bit 0)                                           */
#define GPIO_WT3_WT3_Msk                  (0xffffffffUL)            /*!< WT3 (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  WTS0  ========================================================== */
#define GPIO_WTS0_WTS0_Pos                (0UL)                     /*!< WTS0 (Bit 0)                                          */
#define GPIO_WTS0_WTS0_Msk                (0xffffffffUL)            /*!< WTS0 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  WTS1  ========================================================== */
#define GPIO_WTS1_WTS1_Pos                (0UL)                     /*!< WTS1 (Bit 0)                                          */
#define GPIO_WTS1_WTS1_Msk                (0xffffffffUL)            /*!< WTS1 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  WTS2  ========================================================== */
#define GPIO_WTS2_WTS2_Pos                (0UL)                     /*!< WTS2 (Bit 0)                                          */
#define GPIO_WTS2_WTS2_Msk                (0xffffffffUL)            /*!< WTS2 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  WTS3  ========================================================== */
#define GPIO_WTS3_WTS3_Pos                (0UL)                     /*!< WTS3 (Bit 0)                                          */
#define GPIO_WTS3_WTS3_Msk                (0xffffffffUL)            /*!< WTS3 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  WTC0  ========================================================== */
#define GPIO_WTC0_WTC0_Pos                (0UL)                     /*!< WTC0 (Bit 0)                                          */
#define GPIO_WTC0_WTC0_Msk                (0xffffffffUL)            /*!< WTC0 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  WTC1  ========================================================== */
#define GPIO_WTC1_WTC1_Pos                (0UL)                     /*!< WTC1 (Bit 0)                                          */
#define GPIO_WTC1_WTC1_Msk                (0xffffffffUL)            /*!< WTC1 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  WTC2  ========================================================== */
#define GPIO_WTC2_WTC2_Pos                (0UL)                     /*!< WTC2 (Bit 0)                                          */
#define GPIO_WTC2_WTC2_Msk                (0xffffffffUL)            /*!< WTC2 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  WTC3  ========================================================== */
#define GPIO_WTC3_WTC3_Pos                (0UL)                     /*!< WTC3 (Bit 0)                                          */
#define GPIO_WTC3_WTC3_Msk                (0xffffffffUL)            /*!< WTC3 (Bitfield-Mask: 0xffffffff)                      */
/* ==========================================================  EN0  ========================================================== */
#define GPIO_EN0_EN0_Pos                  (0UL)                     /*!< EN0 (Bit 0)                                           */
#define GPIO_EN0_EN0_Msk                  (0xffffffffUL)            /*!< EN0 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  EN1  ========================================================== */
#define GPIO_EN1_EN1_Pos                  (0UL)                     /*!< EN1 (Bit 0)                                           */
#define GPIO_EN1_EN1_Msk                  (0xffffffffUL)            /*!< EN1 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  EN2  ========================================================== */
#define GPIO_EN2_EN2_Pos                  (0UL)                     /*!< EN2 (Bit 0)                                           */
#define GPIO_EN2_EN2_Msk                  (0xffffffffUL)            /*!< EN2 (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  EN3  ========================================================== */
#define GPIO_EN3_EN3_Pos                  (0UL)                     /*!< EN3 (Bit 0)                                           */
#define GPIO_EN3_EN3_Msk                  (0xffffffffUL)            /*!< EN3 (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  ENS0  ========================================================== */
#define GPIO_ENS0_ENS0_Pos                (0UL)                     /*!< ENS0 (Bit 0)                                          */
#define GPIO_ENS0_ENS0_Msk                (0xffffffffUL)            /*!< ENS0 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  ENS1  ========================================================== */
#define GPIO_ENS1_ENS1_Pos                (0UL)                     /*!< ENS1 (Bit 0)                                          */
#define GPIO_ENS1_ENS1_Msk                (0xffffffffUL)            /*!< ENS1 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  ENS2  ========================================================== */
#define GPIO_ENS2_ENS2_Pos                (0UL)                     /*!< ENS2 (Bit 0)                                          */
#define GPIO_ENS2_ENS2_Msk                (0xffffffffUL)            /*!< ENS2 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  ENS3  ========================================================== */
#define GPIO_ENS3_ENS3_Pos                (0UL)                     /*!< ENS3 (Bit 0)                                          */
#define GPIO_ENS3_ENS3_Msk                (0xffffffffUL)            /*!< ENS3 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  ENC0  ========================================================== */
#define GPIO_ENC0_ENC0_Pos                (0UL)                     /*!< ENC0 (Bit 0)                                          */
#define GPIO_ENC0_ENC0_Msk                (0xffffffffUL)            /*!< ENC0 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  ENC1  ========================================================== */
#define GPIO_ENC1_ENC1_Pos                (0UL)                     /*!< ENC1 (Bit 0)                                          */
#define GPIO_ENC1_ENC1_Msk                (0xffffffffUL)            /*!< ENC1 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  ENC2  ========================================================== */
#define GPIO_ENC2_ENC2_Pos                (0UL)                     /*!< ENC2 (Bit 0)                                          */
#define GPIO_ENC2_ENC2_Msk                (0xffffffffUL)            /*!< ENC2 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  ENC3  ========================================================== */
#define GPIO_ENC3_ENC3_Pos                (0UL)                     /*!< ENC3 (Bit 0)                                          */
#define GPIO_ENC3_ENC3_Msk                (0xffffffffUL)            /*!< ENC3 (Bitfield-Mask: 0xffffffff)                      */
/* ========================================================  IOM0IRQ  ======================================================== */
#define GPIO_IOM0IRQ_IOM0IRQ_Pos          (0UL)                     /*!< IOM0IRQ (Bit 0)                                       */
#define GPIO_IOM0IRQ_IOM0IRQ_Msk          (0x7fUL)                  /*!< IOM0IRQ (Bitfield-Mask: 0x7f)                         */
/* ========================================================  IOM1IRQ  ======================================================== */
#define GPIO_IOM1IRQ_IOM1IRQ_Pos          (0UL)                     /*!< IOM1IRQ (Bit 0)                                       */
#define GPIO_IOM1IRQ_IOM1IRQ_Msk          (0x7fUL)                  /*!< IOM1IRQ (Bitfield-Mask: 0x7f)                         */
/* ========================================================  IOM2IRQ  ======================================================== */
#define GPIO_IOM2IRQ_IOM2IRQ_Pos          (0UL)                     /*!< IOM2IRQ (Bit 0)                                       */
#define GPIO_IOM2IRQ_IOM2IRQ_Msk          (0x7fUL)                  /*!< IOM2IRQ (Bitfield-Mask: 0x7f)                         */
/* ========================================================  IOM3IRQ  ======================================================== */
#define GPIO_IOM3IRQ_IOM3IRQ_Pos          (0UL)                     /*!< IOM3IRQ (Bit 0)                                       */
#define GPIO_IOM3IRQ_IOM3IRQ_Msk          (0x7fUL)                  /*!< IOM3IRQ (Bitfield-Mask: 0x7f)                         */
/* ========================================================  IOM4IRQ  ======================================================== */
#define GPIO_IOM4IRQ_IOM4IRQ_Pos          (0UL)                     /*!< IOM4IRQ (Bit 0)                                       */
#define GPIO_IOM4IRQ_IOM4IRQ_Msk          (0x7fUL)                  /*!< IOM4IRQ (Bitfield-Mask: 0x7f)                         */
/* ========================================================  IOM5IRQ  ======================================================== */
#define GPIO_IOM5IRQ_IOM5IRQ_Pos          (0UL)                     /*!< IOM5IRQ (Bit 0)                                       */
#define GPIO_IOM5IRQ_IOM5IRQ_Msk          (0x7fUL)                  /*!< IOM5IRQ (Bitfield-Mask: 0x7f)                         */
/* ========================================================  IOM6IRQ  ======================================================== */
#define GPIO_IOM6IRQ_IOM6IRQ_Pos          (0UL)                     /*!< IOM6IRQ (Bit 0)                                       */
#define GPIO_IOM6IRQ_IOM6IRQ_Msk          (0x7fUL)                  /*!< IOM6IRQ (Bitfield-Mask: 0x7f)                         */
/* ========================================================  IOM7IRQ  ======================================================== */
#define GPIO_IOM7IRQ_IOM7IRQ_Pos          (0UL)                     /*!< IOM7IRQ (Bit 0)                                       */
#define GPIO_IOM7IRQ_IOM7IRQ_Msk          (0x7fUL)                  /*!< IOM7IRQ (Bitfield-Mask: 0x7f)                         */
/* =======================================================  SDIFCDWP  ======================================================== */
#define GPIO_SDIFCDWP_SDIFWP_Pos          (8UL)                     /*!< SDIFWP (Bit 8)                                        */
#define GPIO_SDIFCDWP_SDIFWP_Msk          (0x7f00UL)                /*!< SDIFWP (Bitfield-Mask: 0x7f)                          */
#define GPIO_SDIFCDWP_SDIFCD_Pos          (0UL)                     /*!< SDIFCD (Bit 0)                                        */
#define GPIO_SDIFCDWP_SDIFCD_Msk          (0x7fUL)                  /*!< SDIFCD (Bitfield-Mask: 0x7f)                          */
/* ========================================================  OBSDATA  ======================================================== */
#define GPIO_OBSDATA_OBSDATA_Pos          (0UL)                     /*!< OBSDATA (Bit 0)                                       */
#define GPIO_OBSDATA_OBSDATA_Msk          (0xffffUL)                /*!< OBSDATA (Bitfield-Mask: 0xffff)                       */
/* ========================================================  IEOBS0  ========================================================= */
#define GPIO_IEOBS0_IEDATA0_Pos           (0UL)                     /*!< IEDATA0 (Bit 0)                                       */
#define GPIO_IEOBS0_IEDATA0_Msk           (0xffffffffUL)            /*!< IEDATA0 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  IEOBS1  ========================================================= */
#define GPIO_IEOBS1_IEDATA1_Pos           (0UL)                     /*!< IEDATA1 (Bit 0)                                       */
#define GPIO_IEOBS1_IEDATA1_Msk           (0xffffffffUL)            /*!< IEDATA1 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  IEOBS2  ========================================================= */
#define GPIO_IEOBS2_IEDATA2_Pos           (0UL)                     /*!< IEDATA2 (Bit 0)                                       */
#define GPIO_IEOBS2_IEDATA2_Msk           (0xffffffffUL)            /*!< IEDATA2 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  IEOBS3  ========================================================= */
#define GPIO_IEOBS3_IEDATA3_Pos           (0UL)                     /*!< IEDATA3 (Bit 0)                                       */
#define GPIO_IEOBS3_IEDATA3_Msk           (0xffffffffUL)            /*!< IEDATA3 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  OEOBS0  ========================================================= */
#define GPIO_OEOBS0_OEDATA0_Pos           (0UL)                     /*!< OEDATA0 (Bit 0)                                       */
#define GPIO_OEOBS0_OEDATA0_Msk           (0xffffffffUL)            /*!< OEDATA0 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  OEOBS1  ========================================================= */
#define GPIO_OEOBS1_OEDATA1_Pos           (0UL)                     /*!< OEDATA1 (Bit 0)                                       */
#define GPIO_OEOBS1_OEDATA1_Msk           (0xffffffffUL)            /*!< OEDATA1 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  OEOBS2  ========================================================= */
#define GPIO_OEOBS2_OEDATA2_Pos           (0UL)                     /*!< OEDATA2 (Bit 0)                                       */
#define GPIO_OEOBS2_OEDATA2_Msk           (0xffffffffUL)            /*!< OEDATA2 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  OEOBS3  ========================================================= */
#define GPIO_OEOBS3_OEDATA3_Pos           (0UL)                     /*!< OEDATA3 (Bit 0)                                       */
#define GPIO_OEOBS3_OEDATA3_Msk           (0xffffffffUL)            /*!< OEDATA3 (Bitfield-Mask: 0xffffffff)                   */
/* ======================================================  MCUN0INT0EN  ====================================================== */
#define GPIO_MCUN0INT0EN_MCUN0GPIO31_Pos  (31UL)                    /*!< MCUN0GPIO31 (Bit 31)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO31_Msk  (0x80000000UL)            /*!< MCUN0GPIO31 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO30_Pos  (30UL)                    /*!< MCUN0GPIO30 (Bit 30)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO30_Msk  (0x40000000UL)            /*!< MCUN0GPIO30 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO29_Pos  (29UL)                    /*!< MCUN0GPIO29 (Bit 29)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO29_Msk  (0x20000000UL)            /*!< MCUN0GPIO29 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO28_Pos  (28UL)                    /*!< MCUN0GPIO28 (Bit 28)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO28_Msk  (0x10000000UL)            /*!< MCUN0GPIO28 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO27_Pos  (27UL)                    /*!< MCUN0GPIO27 (Bit 27)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO27_Msk  (0x8000000UL)             /*!< MCUN0GPIO27 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO26_Pos  (26UL)                    /*!< MCUN0GPIO26 (Bit 26)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO26_Msk  (0x4000000UL)             /*!< MCUN0GPIO26 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO25_Pos  (25UL)                    /*!< MCUN0GPIO25 (Bit 25)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO25_Msk  (0x2000000UL)             /*!< MCUN0GPIO25 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO24_Pos  (24UL)                    /*!< MCUN0GPIO24 (Bit 24)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO24_Msk  (0x1000000UL)             /*!< MCUN0GPIO24 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO23_Pos  (23UL)                    /*!< MCUN0GPIO23 (Bit 23)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO23_Msk  (0x800000UL)              /*!< MCUN0GPIO23 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO22_Pos  (22UL)                    /*!< MCUN0GPIO22 (Bit 22)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO22_Msk  (0x400000UL)              /*!< MCUN0GPIO22 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO21_Pos  (21UL)                    /*!< MCUN0GPIO21 (Bit 21)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO21_Msk  (0x200000UL)              /*!< MCUN0GPIO21 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO20_Pos  (20UL)                    /*!< MCUN0GPIO20 (Bit 20)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO20_Msk  (0x100000UL)              /*!< MCUN0GPIO20 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO19_Pos  (19UL)                    /*!< MCUN0GPIO19 (Bit 19)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO19_Msk  (0x80000UL)               /*!< MCUN0GPIO19 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO18_Pos  (18UL)                    /*!< MCUN0GPIO18 (Bit 18)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO18_Msk  (0x40000UL)               /*!< MCUN0GPIO18 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO17_Pos  (17UL)                    /*!< MCUN0GPIO17 (Bit 17)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO17_Msk  (0x20000UL)               /*!< MCUN0GPIO17 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO16_Pos  (16UL)                    /*!< MCUN0GPIO16 (Bit 16)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO16_Msk  (0x10000UL)               /*!< MCUN0GPIO16 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO15_Pos  (15UL)                    /*!< MCUN0GPIO15 (Bit 15)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO15_Msk  (0x8000UL)                /*!< MCUN0GPIO15 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO14_Pos  (14UL)                    /*!< MCUN0GPIO14 (Bit 14)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO14_Msk  (0x4000UL)                /*!< MCUN0GPIO14 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO13_Pos  (13UL)                    /*!< MCUN0GPIO13 (Bit 13)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO13_Msk  (0x2000UL)                /*!< MCUN0GPIO13 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO12_Pos  (12UL)                    /*!< MCUN0GPIO12 (Bit 12)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO12_Msk  (0x1000UL)                /*!< MCUN0GPIO12 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO11_Pos  (11UL)                    /*!< MCUN0GPIO11 (Bit 11)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO11_Msk  (0x800UL)                 /*!< MCUN0GPIO11 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO10_Pos  (10UL)                    /*!< MCUN0GPIO10 (Bit 10)                                  */
#define GPIO_MCUN0INT0EN_MCUN0GPIO10_Msk  (0x400UL)                 /*!< MCUN0GPIO10 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0EN_MCUN0GPIO9_Pos   (9UL)                     /*!< MCUN0GPIO9 (Bit 9)                                    */
#define GPIO_MCUN0INT0EN_MCUN0GPIO9_Msk   (0x200UL)                 /*!< MCUN0GPIO9 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0EN_MCUN0GPIO8_Pos   (8UL)                     /*!< MCUN0GPIO8 (Bit 8)                                    */
#define GPIO_MCUN0INT0EN_MCUN0GPIO8_Msk   (0x100UL)                 /*!< MCUN0GPIO8 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0EN_MCUN0GPIO7_Pos   (7UL)                     /*!< MCUN0GPIO7 (Bit 7)                                    */
#define GPIO_MCUN0INT0EN_MCUN0GPIO7_Msk   (0x80UL)                  /*!< MCUN0GPIO7 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0EN_MCUN0GPIO6_Pos   (6UL)                     /*!< MCUN0GPIO6 (Bit 6)                                    */
#define GPIO_MCUN0INT0EN_MCUN0GPIO6_Msk   (0x40UL)                  /*!< MCUN0GPIO6 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0EN_MCUN0GPIO5_Pos   (5UL)                     /*!< MCUN0GPIO5 (Bit 5)                                    */
#define GPIO_MCUN0INT0EN_MCUN0GPIO5_Msk   (0x20UL)                  /*!< MCUN0GPIO5 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0EN_MCUN0GPIO4_Pos   (4UL)                     /*!< MCUN0GPIO4 (Bit 4)                                    */
#define GPIO_MCUN0INT0EN_MCUN0GPIO4_Msk   (0x10UL)                  /*!< MCUN0GPIO4 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0EN_MCUN0GPIO3_Pos   (3UL)                     /*!< MCUN0GPIO3 (Bit 3)                                    */
#define GPIO_MCUN0INT0EN_MCUN0GPIO3_Msk   (0x8UL)                   /*!< MCUN0GPIO3 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0EN_MCUN0GPIO2_Pos   (2UL)                     /*!< MCUN0GPIO2 (Bit 2)                                    */
#define GPIO_MCUN0INT0EN_MCUN0GPIO2_Msk   (0x4UL)                   /*!< MCUN0GPIO2 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0EN_MCUN0GPIO1_Pos   (1UL)                     /*!< MCUN0GPIO1 (Bit 1)                                    */
#define GPIO_MCUN0INT0EN_MCUN0GPIO1_Msk   (0x2UL)                   /*!< MCUN0GPIO1 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0EN_MCUN0GPIO0_Pos   (0UL)                     /*!< MCUN0GPIO0 (Bit 0)                                    */
#define GPIO_MCUN0INT0EN_MCUN0GPIO0_Msk   (0x1UL)                   /*!< MCUN0GPIO0 (Bitfield-Mask: 0x01)                      */
/* =====================================================  MCUN0INT0STAT  ===================================================== */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO31_Pos (31UL)                   /*!< MCUN0GPIO31 (Bit 31)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO31_Msk (0x80000000UL)           /*!< MCUN0GPIO31 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO30_Pos (30UL)                   /*!< MCUN0GPIO30 (Bit 30)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO30_Msk (0x40000000UL)           /*!< MCUN0GPIO30 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO29_Pos (29UL)                   /*!< MCUN0GPIO29 (Bit 29)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO29_Msk (0x20000000UL)           /*!< MCUN0GPIO29 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO28_Pos (28UL)                   /*!< MCUN0GPIO28 (Bit 28)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO28_Msk (0x10000000UL)           /*!< MCUN0GPIO28 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO27_Pos (27UL)                   /*!< MCUN0GPIO27 (Bit 27)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO27_Msk (0x8000000UL)            /*!< MCUN0GPIO27 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO26_Pos (26UL)                   /*!< MCUN0GPIO26 (Bit 26)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO26_Msk (0x4000000UL)            /*!< MCUN0GPIO26 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO25_Pos (25UL)                   /*!< MCUN0GPIO25 (Bit 25)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO25_Msk (0x2000000UL)            /*!< MCUN0GPIO25 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO24_Pos (24UL)                   /*!< MCUN0GPIO24 (Bit 24)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO24_Msk (0x1000000UL)            /*!< MCUN0GPIO24 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO23_Pos (23UL)                   /*!< MCUN0GPIO23 (Bit 23)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO23_Msk (0x800000UL)             /*!< MCUN0GPIO23 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO22_Pos (22UL)                   /*!< MCUN0GPIO22 (Bit 22)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO22_Msk (0x400000UL)             /*!< MCUN0GPIO22 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO21_Pos (21UL)                   /*!< MCUN0GPIO21 (Bit 21)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO21_Msk (0x200000UL)             /*!< MCUN0GPIO21 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO20_Pos (20UL)                   /*!< MCUN0GPIO20 (Bit 20)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO20_Msk (0x100000UL)             /*!< MCUN0GPIO20 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO19_Pos (19UL)                   /*!< MCUN0GPIO19 (Bit 19)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO19_Msk (0x80000UL)              /*!< MCUN0GPIO19 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO18_Pos (18UL)                   /*!< MCUN0GPIO18 (Bit 18)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO18_Msk (0x40000UL)              /*!< MCUN0GPIO18 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO17_Pos (17UL)                   /*!< MCUN0GPIO17 (Bit 17)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO17_Msk (0x20000UL)              /*!< MCUN0GPIO17 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO16_Pos (16UL)                   /*!< MCUN0GPIO16 (Bit 16)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO16_Msk (0x10000UL)              /*!< MCUN0GPIO16 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO15_Pos (15UL)                   /*!< MCUN0GPIO15 (Bit 15)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO15_Msk (0x8000UL)               /*!< MCUN0GPIO15 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO14_Pos (14UL)                   /*!< MCUN0GPIO14 (Bit 14)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO14_Msk (0x4000UL)               /*!< MCUN0GPIO14 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO13_Pos (13UL)                   /*!< MCUN0GPIO13 (Bit 13)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO13_Msk (0x2000UL)               /*!< MCUN0GPIO13 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO12_Pos (12UL)                   /*!< MCUN0GPIO12 (Bit 12)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO12_Msk (0x1000UL)               /*!< MCUN0GPIO12 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO11_Pos (11UL)                   /*!< MCUN0GPIO11 (Bit 11)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO11_Msk (0x800UL)                /*!< MCUN0GPIO11 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO10_Pos (10UL)                   /*!< MCUN0GPIO10 (Bit 10)                                  */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO10_Msk (0x400UL)                /*!< MCUN0GPIO10 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO9_Pos (9UL)                     /*!< MCUN0GPIO9 (Bit 9)                                    */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO9_Msk (0x200UL)                 /*!< MCUN0GPIO9 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO8_Pos (8UL)                     /*!< MCUN0GPIO8 (Bit 8)                                    */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO8_Msk (0x100UL)                 /*!< MCUN0GPIO8 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO7_Pos (7UL)                     /*!< MCUN0GPIO7 (Bit 7)                                    */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO7_Msk (0x80UL)                  /*!< MCUN0GPIO7 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO6_Pos (6UL)                     /*!< MCUN0GPIO6 (Bit 6)                                    */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO6_Msk (0x40UL)                  /*!< MCUN0GPIO6 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO5_Pos (5UL)                     /*!< MCUN0GPIO5 (Bit 5)                                    */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO5_Msk (0x20UL)                  /*!< MCUN0GPIO5 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO4_Pos (4UL)                     /*!< MCUN0GPIO4 (Bit 4)                                    */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO4_Msk (0x10UL)                  /*!< MCUN0GPIO4 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO3_Pos (3UL)                     /*!< MCUN0GPIO3 (Bit 3)                                    */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO3_Msk (0x8UL)                   /*!< MCUN0GPIO3 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO2_Pos (2UL)                     /*!< MCUN0GPIO2 (Bit 2)                                    */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO2_Msk (0x4UL)                   /*!< MCUN0GPIO2 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO1_Pos (1UL)                     /*!< MCUN0GPIO1 (Bit 1)                                    */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO1_Msk (0x2UL)                   /*!< MCUN0GPIO1 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO0_Pos (0UL)                     /*!< MCUN0GPIO0 (Bit 0)                                    */
#define GPIO_MCUN0INT0STAT_MCUN0GPIO0_Msk (0x1UL)                   /*!< MCUN0GPIO0 (Bitfield-Mask: 0x01)                      */
/* =====================================================  MCUN0INT0CLR  ====================================================== */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO31_Pos (31UL)                    /*!< MCUN0GPIO31 (Bit 31)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO31_Msk (0x80000000UL)            /*!< MCUN0GPIO31 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO30_Pos (30UL)                    /*!< MCUN0GPIO30 (Bit 30)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO30_Msk (0x40000000UL)            /*!< MCUN0GPIO30 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO29_Pos (29UL)                    /*!< MCUN0GPIO29 (Bit 29)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO29_Msk (0x20000000UL)            /*!< MCUN0GPIO29 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO28_Pos (28UL)                    /*!< MCUN0GPIO28 (Bit 28)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO28_Msk (0x10000000UL)            /*!< MCUN0GPIO28 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO27_Pos (27UL)                    /*!< MCUN0GPIO27 (Bit 27)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO27_Msk (0x8000000UL)             /*!< MCUN0GPIO27 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO26_Pos (26UL)                    /*!< MCUN0GPIO26 (Bit 26)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO26_Msk (0x4000000UL)             /*!< MCUN0GPIO26 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO25_Pos (25UL)                    /*!< MCUN0GPIO25 (Bit 25)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO25_Msk (0x2000000UL)             /*!< MCUN0GPIO25 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO24_Pos (24UL)                    /*!< MCUN0GPIO24 (Bit 24)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO24_Msk (0x1000000UL)             /*!< MCUN0GPIO24 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO23_Pos (23UL)                    /*!< MCUN0GPIO23 (Bit 23)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO23_Msk (0x800000UL)              /*!< MCUN0GPIO23 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO22_Pos (22UL)                    /*!< MCUN0GPIO22 (Bit 22)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO22_Msk (0x400000UL)              /*!< MCUN0GPIO22 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO21_Pos (21UL)                    /*!< MCUN0GPIO21 (Bit 21)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO21_Msk (0x200000UL)              /*!< MCUN0GPIO21 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO20_Pos (20UL)                    /*!< MCUN0GPIO20 (Bit 20)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO20_Msk (0x100000UL)              /*!< MCUN0GPIO20 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO19_Pos (19UL)                    /*!< MCUN0GPIO19 (Bit 19)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO19_Msk (0x80000UL)               /*!< MCUN0GPIO19 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO18_Pos (18UL)                    /*!< MCUN0GPIO18 (Bit 18)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO18_Msk (0x40000UL)               /*!< MCUN0GPIO18 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO17_Pos (17UL)                    /*!< MCUN0GPIO17 (Bit 17)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO17_Msk (0x20000UL)               /*!< MCUN0GPIO17 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO16_Pos (16UL)                    /*!< MCUN0GPIO16 (Bit 16)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO16_Msk (0x10000UL)               /*!< MCUN0GPIO16 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO15_Pos (15UL)                    /*!< MCUN0GPIO15 (Bit 15)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO15_Msk (0x8000UL)                /*!< MCUN0GPIO15 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO14_Pos (14UL)                    /*!< MCUN0GPIO14 (Bit 14)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO14_Msk (0x4000UL)                /*!< MCUN0GPIO14 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO13_Pos (13UL)                    /*!< MCUN0GPIO13 (Bit 13)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO13_Msk (0x2000UL)                /*!< MCUN0GPIO13 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO12_Pos (12UL)                    /*!< MCUN0GPIO12 (Bit 12)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO12_Msk (0x1000UL)                /*!< MCUN0GPIO12 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO11_Pos (11UL)                    /*!< MCUN0GPIO11 (Bit 11)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO11_Msk (0x800UL)                 /*!< MCUN0GPIO11 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO10_Pos (10UL)                    /*!< MCUN0GPIO10 (Bit 10)                                  */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO10_Msk (0x400UL)                 /*!< MCUN0GPIO10 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO9_Pos  (9UL)                     /*!< MCUN0GPIO9 (Bit 9)                                    */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO9_Msk  (0x200UL)                 /*!< MCUN0GPIO9 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO8_Pos  (8UL)                     /*!< MCUN0GPIO8 (Bit 8)                                    */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO8_Msk  (0x100UL)                 /*!< MCUN0GPIO8 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO7_Pos  (7UL)                     /*!< MCUN0GPIO7 (Bit 7)                                    */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO7_Msk  (0x80UL)                  /*!< MCUN0GPIO7 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO6_Pos  (6UL)                     /*!< MCUN0GPIO6 (Bit 6)                                    */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO6_Msk  (0x40UL)                  /*!< MCUN0GPIO6 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO5_Pos  (5UL)                     /*!< MCUN0GPIO5 (Bit 5)                                    */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO5_Msk  (0x20UL)                  /*!< MCUN0GPIO5 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO4_Pos  (4UL)                     /*!< MCUN0GPIO4 (Bit 4)                                    */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO4_Msk  (0x10UL)                  /*!< MCUN0GPIO4 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO3_Pos  (3UL)                     /*!< MCUN0GPIO3 (Bit 3)                                    */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO3_Msk  (0x8UL)                   /*!< MCUN0GPIO3 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO2_Pos  (2UL)                     /*!< MCUN0GPIO2 (Bit 2)                                    */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO2_Msk  (0x4UL)                   /*!< MCUN0GPIO2 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO1_Pos  (1UL)                     /*!< MCUN0GPIO1 (Bit 1)                                    */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO1_Msk  (0x2UL)                   /*!< MCUN0GPIO1 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO0_Pos  (0UL)                     /*!< MCUN0GPIO0 (Bit 0)                                    */
#define GPIO_MCUN0INT0CLR_MCUN0GPIO0_Msk  (0x1UL)                   /*!< MCUN0GPIO0 (Bitfield-Mask: 0x01)                      */
/* =====================================================  MCUN0INT0SET  ====================================================== */
#define GPIO_MCUN0INT0SET_MCUN0GPIO31_Pos (31UL)                    /*!< MCUN0GPIO31 (Bit 31)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO31_Msk (0x80000000UL)            /*!< MCUN0GPIO31 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO30_Pos (30UL)                    /*!< MCUN0GPIO30 (Bit 30)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO30_Msk (0x40000000UL)            /*!< MCUN0GPIO30 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO29_Pos (29UL)                    /*!< MCUN0GPIO29 (Bit 29)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO29_Msk (0x20000000UL)            /*!< MCUN0GPIO29 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO28_Pos (28UL)                    /*!< MCUN0GPIO28 (Bit 28)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO28_Msk (0x10000000UL)            /*!< MCUN0GPIO28 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO27_Pos (27UL)                    /*!< MCUN0GPIO27 (Bit 27)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO27_Msk (0x8000000UL)             /*!< MCUN0GPIO27 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO26_Pos (26UL)                    /*!< MCUN0GPIO26 (Bit 26)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO26_Msk (0x4000000UL)             /*!< MCUN0GPIO26 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO25_Pos (25UL)                    /*!< MCUN0GPIO25 (Bit 25)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO25_Msk (0x2000000UL)             /*!< MCUN0GPIO25 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO24_Pos (24UL)                    /*!< MCUN0GPIO24 (Bit 24)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO24_Msk (0x1000000UL)             /*!< MCUN0GPIO24 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO23_Pos (23UL)                    /*!< MCUN0GPIO23 (Bit 23)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO23_Msk (0x800000UL)              /*!< MCUN0GPIO23 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO22_Pos (22UL)                    /*!< MCUN0GPIO22 (Bit 22)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO22_Msk (0x400000UL)              /*!< MCUN0GPIO22 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO21_Pos (21UL)                    /*!< MCUN0GPIO21 (Bit 21)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO21_Msk (0x200000UL)              /*!< MCUN0GPIO21 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO20_Pos (20UL)                    /*!< MCUN0GPIO20 (Bit 20)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO20_Msk (0x100000UL)              /*!< MCUN0GPIO20 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO19_Pos (19UL)                    /*!< MCUN0GPIO19 (Bit 19)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO19_Msk (0x80000UL)               /*!< MCUN0GPIO19 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO18_Pos (18UL)                    /*!< MCUN0GPIO18 (Bit 18)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO18_Msk (0x40000UL)               /*!< MCUN0GPIO18 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO17_Pos (17UL)                    /*!< MCUN0GPIO17 (Bit 17)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO17_Msk (0x20000UL)               /*!< MCUN0GPIO17 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO16_Pos (16UL)                    /*!< MCUN0GPIO16 (Bit 16)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO16_Msk (0x10000UL)               /*!< MCUN0GPIO16 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO15_Pos (15UL)                    /*!< MCUN0GPIO15 (Bit 15)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO15_Msk (0x8000UL)                /*!< MCUN0GPIO15 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO14_Pos (14UL)                    /*!< MCUN0GPIO14 (Bit 14)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO14_Msk (0x4000UL)                /*!< MCUN0GPIO14 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO13_Pos (13UL)                    /*!< MCUN0GPIO13 (Bit 13)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO13_Msk (0x2000UL)                /*!< MCUN0GPIO13 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO12_Pos (12UL)                    /*!< MCUN0GPIO12 (Bit 12)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO12_Msk (0x1000UL)                /*!< MCUN0GPIO12 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO11_Pos (11UL)                    /*!< MCUN0GPIO11 (Bit 11)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO11_Msk (0x800UL)                 /*!< MCUN0GPIO11 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO10_Pos (10UL)                    /*!< MCUN0GPIO10 (Bit 10)                                  */
#define GPIO_MCUN0INT0SET_MCUN0GPIO10_Msk (0x400UL)                 /*!< MCUN0GPIO10 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT0SET_MCUN0GPIO9_Pos  (9UL)                     /*!< MCUN0GPIO9 (Bit 9)                                    */
#define GPIO_MCUN0INT0SET_MCUN0GPIO9_Msk  (0x200UL)                 /*!< MCUN0GPIO9 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0SET_MCUN0GPIO8_Pos  (8UL)                     /*!< MCUN0GPIO8 (Bit 8)                                    */
#define GPIO_MCUN0INT0SET_MCUN0GPIO8_Msk  (0x100UL)                 /*!< MCUN0GPIO8 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0SET_MCUN0GPIO7_Pos  (7UL)                     /*!< MCUN0GPIO7 (Bit 7)                                    */
#define GPIO_MCUN0INT0SET_MCUN0GPIO7_Msk  (0x80UL)                  /*!< MCUN0GPIO7 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0SET_MCUN0GPIO6_Pos  (6UL)                     /*!< MCUN0GPIO6 (Bit 6)                                    */
#define GPIO_MCUN0INT0SET_MCUN0GPIO6_Msk  (0x40UL)                  /*!< MCUN0GPIO6 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0SET_MCUN0GPIO5_Pos  (5UL)                     /*!< MCUN0GPIO5 (Bit 5)                                    */
#define GPIO_MCUN0INT0SET_MCUN0GPIO5_Msk  (0x20UL)                  /*!< MCUN0GPIO5 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0SET_MCUN0GPIO4_Pos  (4UL)                     /*!< MCUN0GPIO4 (Bit 4)                                    */
#define GPIO_MCUN0INT0SET_MCUN0GPIO4_Msk  (0x10UL)                  /*!< MCUN0GPIO4 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0SET_MCUN0GPIO3_Pos  (3UL)                     /*!< MCUN0GPIO3 (Bit 3)                                    */
#define GPIO_MCUN0INT0SET_MCUN0GPIO3_Msk  (0x8UL)                   /*!< MCUN0GPIO3 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0SET_MCUN0GPIO2_Pos  (2UL)                     /*!< MCUN0GPIO2 (Bit 2)                                    */
#define GPIO_MCUN0INT0SET_MCUN0GPIO2_Msk  (0x4UL)                   /*!< MCUN0GPIO2 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0SET_MCUN0GPIO1_Pos  (1UL)                     /*!< MCUN0GPIO1 (Bit 1)                                    */
#define GPIO_MCUN0INT0SET_MCUN0GPIO1_Msk  (0x2UL)                   /*!< MCUN0GPIO1 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN0INT0SET_MCUN0GPIO0_Pos  (0UL)                     /*!< MCUN0GPIO0 (Bit 0)                                    */
#define GPIO_MCUN0INT0SET_MCUN0GPIO0_Msk  (0x1UL)                   /*!< MCUN0GPIO0 (Bitfield-Mask: 0x01)                      */
/* ======================================================  MCUN0INT1EN  ====================================================== */
#define GPIO_MCUN0INT1EN_MCUN0GPIO63_Pos  (31UL)                    /*!< MCUN0GPIO63 (Bit 31)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO63_Msk  (0x80000000UL)            /*!< MCUN0GPIO63 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO62_Pos  (30UL)                    /*!< MCUN0GPIO62 (Bit 30)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO62_Msk  (0x40000000UL)            /*!< MCUN0GPIO62 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO61_Pos  (29UL)                    /*!< MCUN0GPIO61 (Bit 29)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO61_Msk  (0x20000000UL)            /*!< MCUN0GPIO61 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO60_Pos  (28UL)                    /*!< MCUN0GPIO60 (Bit 28)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO60_Msk  (0x10000000UL)            /*!< MCUN0GPIO60 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO59_Pos  (27UL)                    /*!< MCUN0GPIO59 (Bit 27)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO59_Msk  (0x8000000UL)             /*!< MCUN0GPIO59 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO58_Pos  (26UL)                    /*!< MCUN0GPIO58 (Bit 26)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO58_Msk  (0x4000000UL)             /*!< MCUN0GPIO58 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO57_Pos  (25UL)                    /*!< MCUN0GPIO57 (Bit 25)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO57_Msk  (0x2000000UL)             /*!< MCUN0GPIO57 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO56_Pos  (24UL)                    /*!< MCUN0GPIO56 (Bit 24)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO56_Msk  (0x1000000UL)             /*!< MCUN0GPIO56 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO55_Pos  (23UL)                    /*!< MCUN0GPIO55 (Bit 23)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO55_Msk  (0x800000UL)              /*!< MCUN0GPIO55 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO54_Pos  (22UL)                    /*!< MCUN0GPIO54 (Bit 22)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO54_Msk  (0x400000UL)              /*!< MCUN0GPIO54 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO53_Pos  (21UL)                    /*!< MCUN0GPIO53 (Bit 21)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO53_Msk  (0x200000UL)              /*!< MCUN0GPIO53 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO52_Pos  (20UL)                    /*!< MCUN0GPIO52 (Bit 20)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO52_Msk  (0x100000UL)              /*!< MCUN0GPIO52 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO51_Pos  (19UL)                    /*!< MCUN0GPIO51 (Bit 19)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO51_Msk  (0x80000UL)               /*!< MCUN0GPIO51 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO50_Pos  (18UL)                    /*!< MCUN0GPIO50 (Bit 18)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO50_Msk  (0x40000UL)               /*!< MCUN0GPIO50 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO49_Pos  (17UL)                    /*!< MCUN0GPIO49 (Bit 17)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO49_Msk  (0x20000UL)               /*!< MCUN0GPIO49 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO48_Pos  (16UL)                    /*!< MCUN0GPIO48 (Bit 16)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO48_Msk  (0x10000UL)               /*!< MCUN0GPIO48 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO47_Pos  (15UL)                    /*!< MCUN0GPIO47 (Bit 15)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO47_Msk  (0x8000UL)                /*!< MCUN0GPIO47 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO46_Pos  (14UL)                    /*!< MCUN0GPIO46 (Bit 14)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO46_Msk  (0x4000UL)                /*!< MCUN0GPIO46 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO45_Pos  (13UL)                    /*!< MCUN0GPIO45 (Bit 13)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO45_Msk  (0x2000UL)                /*!< MCUN0GPIO45 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO44_Pos  (12UL)                    /*!< MCUN0GPIO44 (Bit 12)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO44_Msk  (0x1000UL)                /*!< MCUN0GPIO44 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO43_Pos  (11UL)                    /*!< MCUN0GPIO43 (Bit 11)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO43_Msk  (0x800UL)                 /*!< MCUN0GPIO43 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO42_Pos  (10UL)                    /*!< MCUN0GPIO42 (Bit 10)                                  */
#define GPIO_MCUN0INT1EN_MCUN0GPIO42_Msk  (0x400UL)                 /*!< MCUN0GPIO42 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO41_Pos  (9UL)                     /*!< MCUN0GPIO41 (Bit 9)                                   */
#define GPIO_MCUN0INT1EN_MCUN0GPIO41_Msk  (0x200UL)                 /*!< MCUN0GPIO41 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO40_Pos  (8UL)                     /*!< MCUN0GPIO40 (Bit 8)                                   */
#define GPIO_MCUN0INT1EN_MCUN0GPIO40_Msk  (0x100UL)                 /*!< MCUN0GPIO40 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO39_Pos  (7UL)                     /*!< MCUN0GPIO39 (Bit 7)                                   */
#define GPIO_MCUN0INT1EN_MCUN0GPIO39_Msk  (0x80UL)                  /*!< MCUN0GPIO39 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO38_Pos  (6UL)                     /*!< MCUN0GPIO38 (Bit 6)                                   */
#define GPIO_MCUN0INT1EN_MCUN0GPIO38_Msk  (0x40UL)                  /*!< MCUN0GPIO38 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO37_Pos  (5UL)                     /*!< MCUN0GPIO37 (Bit 5)                                   */
#define GPIO_MCUN0INT1EN_MCUN0GPIO37_Msk  (0x20UL)                  /*!< MCUN0GPIO37 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO36_Pos  (4UL)                     /*!< MCUN0GPIO36 (Bit 4)                                   */
#define GPIO_MCUN0INT1EN_MCUN0GPIO36_Msk  (0x10UL)                  /*!< MCUN0GPIO36 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO35_Pos  (3UL)                     /*!< MCUN0GPIO35 (Bit 3)                                   */
#define GPIO_MCUN0INT1EN_MCUN0GPIO35_Msk  (0x8UL)                   /*!< MCUN0GPIO35 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO34_Pos  (2UL)                     /*!< MCUN0GPIO34 (Bit 2)                                   */
#define GPIO_MCUN0INT1EN_MCUN0GPIO34_Msk  (0x4UL)                   /*!< MCUN0GPIO34 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO33_Pos  (1UL)                     /*!< MCUN0GPIO33 (Bit 1)                                   */
#define GPIO_MCUN0INT1EN_MCUN0GPIO33_Msk  (0x2UL)                   /*!< MCUN0GPIO33 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1EN_MCUN0GPIO32_Pos  (0UL)                     /*!< MCUN0GPIO32 (Bit 0)                                   */
#define GPIO_MCUN0INT1EN_MCUN0GPIO32_Msk  (0x1UL)                   /*!< MCUN0GPIO32 (Bitfield-Mask: 0x01)                     */
/* =====================================================  MCUN0INT1STAT  ===================================================== */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO63_Pos (31UL)                   /*!< MCUN0GPIO63 (Bit 31)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO63_Msk (0x80000000UL)           /*!< MCUN0GPIO63 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO62_Pos (30UL)                   /*!< MCUN0GPIO62 (Bit 30)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO62_Msk (0x40000000UL)           /*!< MCUN0GPIO62 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO61_Pos (29UL)                   /*!< MCUN0GPIO61 (Bit 29)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO61_Msk (0x20000000UL)           /*!< MCUN0GPIO61 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO60_Pos (28UL)                   /*!< MCUN0GPIO60 (Bit 28)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO60_Msk (0x10000000UL)           /*!< MCUN0GPIO60 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO59_Pos (27UL)                   /*!< MCUN0GPIO59 (Bit 27)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO59_Msk (0x8000000UL)            /*!< MCUN0GPIO59 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO58_Pos (26UL)                   /*!< MCUN0GPIO58 (Bit 26)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO58_Msk (0x4000000UL)            /*!< MCUN0GPIO58 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO57_Pos (25UL)                   /*!< MCUN0GPIO57 (Bit 25)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO57_Msk (0x2000000UL)            /*!< MCUN0GPIO57 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO56_Pos (24UL)                   /*!< MCUN0GPIO56 (Bit 24)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO56_Msk (0x1000000UL)            /*!< MCUN0GPIO56 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO55_Pos (23UL)                   /*!< MCUN0GPIO55 (Bit 23)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO55_Msk (0x800000UL)             /*!< MCUN0GPIO55 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO54_Pos (22UL)                   /*!< MCUN0GPIO54 (Bit 22)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO54_Msk (0x400000UL)             /*!< MCUN0GPIO54 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO53_Pos (21UL)                   /*!< MCUN0GPIO53 (Bit 21)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO53_Msk (0x200000UL)             /*!< MCUN0GPIO53 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO52_Pos (20UL)                   /*!< MCUN0GPIO52 (Bit 20)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO52_Msk (0x100000UL)             /*!< MCUN0GPIO52 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO51_Pos (19UL)                   /*!< MCUN0GPIO51 (Bit 19)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO51_Msk (0x80000UL)              /*!< MCUN0GPIO51 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO50_Pos (18UL)                   /*!< MCUN0GPIO50 (Bit 18)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO50_Msk (0x40000UL)              /*!< MCUN0GPIO50 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO49_Pos (17UL)                   /*!< MCUN0GPIO49 (Bit 17)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO49_Msk (0x20000UL)              /*!< MCUN0GPIO49 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO48_Pos (16UL)                   /*!< MCUN0GPIO48 (Bit 16)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO48_Msk (0x10000UL)              /*!< MCUN0GPIO48 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO47_Pos (15UL)                   /*!< MCUN0GPIO47 (Bit 15)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO47_Msk (0x8000UL)               /*!< MCUN0GPIO47 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO46_Pos (14UL)                   /*!< MCUN0GPIO46 (Bit 14)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO46_Msk (0x4000UL)               /*!< MCUN0GPIO46 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO45_Pos (13UL)                   /*!< MCUN0GPIO45 (Bit 13)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO45_Msk (0x2000UL)               /*!< MCUN0GPIO45 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO44_Pos (12UL)                   /*!< MCUN0GPIO44 (Bit 12)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO44_Msk (0x1000UL)               /*!< MCUN0GPIO44 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO43_Pos (11UL)                   /*!< MCUN0GPIO43 (Bit 11)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO43_Msk (0x800UL)                /*!< MCUN0GPIO43 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO42_Pos (10UL)                   /*!< MCUN0GPIO42 (Bit 10)                                  */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO42_Msk (0x400UL)                /*!< MCUN0GPIO42 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO41_Pos (9UL)                    /*!< MCUN0GPIO41 (Bit 9)                                   */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO41_Msk (0x200UL)                /*!< MCUN0GPIO41 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO40_Pos (8UL)                    /*!< MCUN0GPIO40 (Bit 8)                                   */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO40_Msk (0x100UL)                /*!< MCUN0GPIO40 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO39_Pos (7UL)                    /*!< MCUN0GPIO39 (Bit 7)                                   */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO39_Msk (0x80UL)                 /*!< MCUN0GPIO39 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO38_Pos (6UL)                    /*!< MCUN0GPIO38 (Bit 6)                                   */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO38_Msk (0x40UL)                 /*!< MCUN0GPIO38 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO37_Pos (5UL)                    /*!< MCUN0GPIO37 (Bit 5)                                   */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO37_Msk (0x20UL)                 /*!< MCUN0GPIO37 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO36_Pos (4UL)                    /*!< MCUN0GPIO36 (Bit 4)                                   */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO36_Msk (0x10UL)                 /*!< MCUN0GPIO36 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO35_Pos (3UL)                    /*!< MCUN0GPIO35 (Bit 3)                                   */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO35_Msk (0x8UL)                  /*!< MCUN0GPIO35 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO34_Pos (2UL)                    /*!< MCUN0GPIO34 (Bit 2)                                   */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO34_Msk (0x4UL)                  /*!< MCUN0GPIO34 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO33_Pos (1UL)                    /*!< MCUN0GPIO33 (Bit 1)                                   */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO33_Msk (0x2UL)                  /*!< MCUN0GPIO33 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO32_Pos (0UL)                    /*!< MCUN0GPIO32 (Bit 0)                                   */
#define GPIO_MCUN0INT1STAT_MCUN0GPIO32_Msk (0x1UL)                  /*!< MCUN0GPIO32 (Bitfield-Mask: 0x01)                     */
/* =====================================================  MCUN0INT1CLR  ====================================================== */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO63_Pos (31UL)                    /*!< MCUN0GPIO63 (Bit 31)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO63_Msk (0x80000000UL)            /*!< MCUN0GPIO63 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO62_Pos (30UL)                    /*!< MCUN0GPIO62 (Bit 30)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO62_Msk (0x40000000UL)            /*!< MCUN0GPIO62 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO61_Pos (29UL)                    /*!< MCUN0GPIO61 (Bit 29)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO61_Msk (0x20000000UL)            /*!< MCUN0GPIO61 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO60_Pos (28UL)                    /*!< MCUN0GPIO60 (Bit 28)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO60_Msk (0x10000000UL)            /*!< MCUN0GPIO60 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO59_Pos (27UL)                    /*!< MCUN0GPIO59 (Bit 27)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO59_Msk (0x8000000UL)             /*!< MCUN0GPIO59 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO58_Pos (26UL)                    /*!< MCUN0GPIO58 (Bit 26)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO58_Msk (0x4000000UL)             /*!< MCUN0GPIO58 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO57_Pos (25UL)                    /*!< MCUN0GPIO57 (Bit 25)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO57_Msk (0x2000000UL)             /*!< MCUN0GPIO57 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO56_Pos (24UL)                    /*!< MCUN0GPIO56 (Bit 24)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO56_Msk (0x1000000UL)             /*!< MCUN0GPIO56 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO55_Pos (23UL)                    /*!< MCUN0GPIO55 (Bit 23)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO55_Msk (0x800000UL)              /*!< MCUN0GPIO55 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO54_Pos (22UL)                    /*!< MCUN0GPIO54 (Bit 22)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO54_Msk (0x400000UL)              /*!< MCUN0GPIO54 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO53_Pos (21UL)                    /*!< MCUN0GPIO53 (Bit 21)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO53_Msk (0x200000UL)              /*!< MCUN0GPIO53 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO52_Pos (20UL)                    /*!< MCUN0GPIO52 (Bit 20)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO52_Msk (0x100000UL)              /*!< MCUN0GPIO52 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO51_Pos (19UL)                    /*!< MCUN0GPIO51 (Bit 19)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO51_Msk (0x80000UL)               /*!< MCUN0GPIO51 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO50_Pos (18UL)                    /*!< MCUN0GPIO50 (Bit 18)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO50_Msk (0x40000UL)               /*!< MCUN0GPIO50 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO49_Pos (17UL)                    /*!< MCUN0GPIO49 (Bit 17)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO49_Msk (0x20000UL)               /*!< MCUN0GPIO49 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO48_Pos (16UL)                    /*!< MCUN0GPIO48 (Bit 16)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO48_Msk (0x10000UL)               /*!< MCUN0GPIO48 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO47_Pos (15UL)                    /*!< MCUN0GPIO47 (Bit 15)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO47_Msk (0x8000UL)                /*!< MCUN0GPIO47 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO46_Pos (14UL)                    /*!< MCUN0GPIO46 (Bit 14)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO46_Msk (0x4000UL)                /*!< MCUN0GPIO46 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO45_Pos (13UL)                    /*!< MCUN0GPIO45 (Bit 13)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO45_Msk (0x2000UL)                /*!< MCUN0GPIO45 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO44_Pos (12UL)                    /*!< MCUN0GPIO44 (Bit 12)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO44_Msk (0x1000UL)                /*!< MCUN0GPIO44 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO43_Pos (11UL)                    /*!< MCUN0GPIO43 (Bit 11)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO43_Msk (0x800UL)                 /*!< MCUN0GPIO43 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO42_Pos (10UL)                    /*!< MCUN0GPIO42 (Bit 10)                                  */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO42_Msk (0x400UL)                 /*!< MCUN0GPIO42 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO41_Pos (9UL)                     /*!< MCUN0GPIO41 (Bit 9)                                   */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO41_Msk (0x200UL)                 /*!< MCUN0GPIO41 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO40_Pos (8UL)                     /*!< MCUN0GPIO40 (Bit 8)                                   */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO40_Msk (0x100UL)                 /*!< MCUN0GPIO40 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO39_Pos (7UL)                     /*!< MCUN0GPIO39 (Bit 7)                                   */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO39_Msk (0x80UL)                  /*!< MCUN0GPIO39 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO38_Pos (6UL)                     /*!< MCUN0GPIO38 (Bit 6)                                   */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO38_Msk (0x40UL)                  /*!< MCUN0GPIO38 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO37_Pos (5UL)                     /*!< MCUN0GPIO37 (Bit 5)                                   */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO37_Msk (0x20UL)                  /*!< MCUN0GPIO37 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO36_Pos (4UL)                     /*!< MCUN0GPIO36 (Bit 4)                                   */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO36_Msk (0x10UL)                  /*!< MCUN0GPIO36 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO35_Pos (3UL)                     /*!< MCUN0GPIO35 (Bit 3)                                   */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO35_Msk (0x8UL)                   /*!< MCUN0GPIO35 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO34_Pos (2UL)                     /*!< MCUN0GPIO34 (Bit 2)                                   */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO34_Msk (0x4UL)                   /*!< MCUN0GPIO34 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO33_Pos (1UL)                     /*!< MCUN0GPIO33 (Bit 1)                                   */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO33_Msk (0x2UL)                   /*!< MCUN0GPIO33 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO32_Pos (0UL)                     /*!< MCUN0GPIO32 (Bit 0)                                   */
#define GPIO_MCUN0INT1CLR_MCUN0GPIO32_Msk (0x1UL)                   /*!< MCUN0GPIO32 (Bitfield-Mask: 0x01)                     */
/* =====================================================  MCUN0INT1SET  ====================================================== */
#define GPIO_MCUN0INT1SET_MCUN0GPIO63_Pos (31UL)                    /*!< MCUN0GPIO63 (Bit 31)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO63_Msk (0x80000000UL)            /*!< MCUN0GPIO63 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO62_Pos (30UL)                    /*!< MCUN0GPIO62 (Bit 30)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO62_Msk (0x40000000UL)            /*!< MCUN0GPIO62 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO61_Pos (29UL)                    /*!< MCUN0GPIO61 (Bit 29)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO61_Msk (0x20000000UL)            /*!< MCUN0GPIO61 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO60_Pos (28UL)                    /*!< MCUN0GPIO60 (Bit 28)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO60_Msk (0x10000000UL)            /*!< MCUN0GPIO60 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO59_Pos (27UL)                    /*!< MCUN0GPIO59 (Bit 27)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO59_Msk (0x8000000UL)             /*!< MCUN0GPIO59 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO58_Pos (26UL)                    /*!< MCUN0GPIO58 (Bit 26)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO58_Msk (0x4000000UL)             /*!< MCUN0GPIO58 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO57_Pos (25UL)                    /*!< MCUN0GPIO57 (Bit 25)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO57_Msk (0x2000000UL)             /*!< MCUN0GPIO57 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO56_Pos (24UL)                    /*!< MCUN0GPIO56 (Bit 24)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO56_Msk (0x1000000UL)             /*!< MCUN0GPIO56 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO55_Pos (23UL)                    /*!< MCUN0GPIO55 (Bit 23)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO55_Msk (0x800000UL)              /*!< MCUN0GPIO55 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO54_Pos (22UL)                    /*!< MCUN0GPIO54 (Bit 22)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO54_Msk (0x400000UL)              /*!< MCUN0GPIO54 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO53_Pos (21UL)                    /*!< MCUN0GPIO53 (Bit 21)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO53_Msk (0x200000UL)              /*!< MCUN0GPIO53 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO52_Pos (20UL)                    /*!< MCUN0GPIO52 (Bit 20)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO52_Msk (0x100000UL)              /*!< MCUN0GPIO52 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO51_Pos (19UL)                    /*!< MCUN0GPIO51 (Bit 19)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO51_Msk (0x80000UL)               /*!< MCUN0GPIO51 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO50_Pos (18UL)                    /*!< MCUN0GPIO50 (Bit 18)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO50_Msk (0x40000UL)               /*!< MCUN0GPIO50 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO49_Pos (17UL)                    /*!< MCUN0GPIO49 (Bit 17)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO49_Msk (0x20000UL)               /*!< MCUN0GPIO49 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO48_Pos (16UL)                    /*!< MCUN0GPIO48 (Bit 16)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO48_Msk (0x10000UL)               /*!< MCUN0GPIO48 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO47_Pos (15UL)                    /*!< MCUN0GPIO47 (Bit 15)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO47_Msk (0x8000UL)                /*!< MCUN0GPIO47 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO46_Pos (14UL)                    /*!< MCUN0GPIO46 (Bit 14)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO46_Msk (0x4000UL)                /*!< MCUN0GPIO46 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO45_Pos (13UL)                    /*!< MCUN0GPIO45 (Bit 13)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO45_Msk (0x2000UL)                /*!< MCUN0GPIO45 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO44_Pos (12UL)                    /*!< MCUN0GPIO44 (Bit 12)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO44_Msk (0x1000UL)                /*!< MCUN0GPIO44 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO43_Pos (11UL)                    /*!< MCUN0GPIO43 (Bit 11)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO43_Msk (0x800UL)                 /*!< MCUN0GPIO43 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO42_Pos (10UL)                    /*!< MCUN0GPIO42 (Bit 10)                                  */
#define GPIO_MCUN0INT1SET_MCUN0GPIO42_Msk (0x400UL)                 /*!< MCUN0GPIO42 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO41_Pos (9UL)                     /*!< MCUN0GPIO41 (Bit 9)                                   */
#define GPIO_MCUN0INT1SET_MCUN0GPIO41_Msk (0x200UL)                 /*!< MCUN0GPIO41 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO40_Pos (8UL)                     /*!< MCUN0GPIO40 (Bit 8)                                   */
#define GPIO_MCUN0INT1SET_MCUN0GPIO40_Msk (0x100UL)                 /*!< MCUN0GPIO40 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO39_Pos (7UL)                     /*!< MCUN0GPIO39 (Bit 7)                                   */
#define GPIO_MCUN0INT1SET_MCUN0GPIO39_Msk (0x80UL)                  /*!< MCUN0GPIO39 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO38_Pos (6UL)                     /*!< MCUN0GPIO38 (Bit 6)                                   */
#define GPIO_MCUN0INT1SET_MCUN0GPIO38_Msk (0x40UL)                  /*!< MCUN0GPIO38 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO37_Pos (5UL)                     /*!< MCUN0GPIO37 (Bit 5)                                   */
#define GPIO_MCUN0INT1SET_MCUN0GPIO37_Msk (0x20UL)                  /*!< MCUN0GPIO37 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO36_Pos (4UL)                     /*!< MCUN0GPIO36 (Bit 4)                                   */
#define GPIO_MCUN0INT1SET_MCUN0GPIO36_Msk (0x10UL)                  /*!< MCUN0GPIO36 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO35_Pos (3UL)                     /*!< MCUN0GPIO35 (Bit 3)                                   */
#define GPIO_MCUN0INT1SET_MCUN0GPIO35_Msk (0x8UL)                   /*!< MCUN0GPIO35 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO34_Pos (2UL)                     /*!< MCUN0GPIO34 (Bit 2)                                   */
#define GPIO_MCUN0INT1SET_MCUN0GPIO34_Msk (0x4UL)                   /*!< MCUN0GPIO34 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO33_Pos (1UL)                     /*!< MCUN0GPIO33 (Bit 1)                                   */
#define GPIO_MCUN0INT1SET_MCUN0GPIO33_Msk (0x2UL)                   /*!< MCUN0GPIO33 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT1SET_MCUN0GPIO32_Pos (0UL)                     /*!< MCUN0GPIO32 (Bit 0)                                   */
#define GPIO_MCUN0INT1SET_MCUN0GPIO32_Msk (0x1UL)                   /*!< MCUN0GPIO32 (Bitfield-Mask: 0x01)                     */
/* ======================================================  MCUN0INT2EN  ====================================================== */
#define GPIO_MCUN0INT2EN_MCUN0GPIO95_Pos  (31UL)                    /*!< MCUN0GPIO95 (Bit 31)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO95_Msk  (0x80000000UL)            /*!< MCUN0GPIO95 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO94_Pos  (30UL)                    /*!< MCUN0GPIO94 (Bit 30)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO94_Msk  (0x40000000UL)            /*!< MCUN0GPIO94 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO93_Pos  (29UL)                    /*!< MCUN0GPIO93 (Bit 29)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO93_Msk  (0x20000000UL)            /*!< MCUN0GPIO93 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO92_Pos  (28UL)                    /*!< MCUN0GPIO92 (Bit 28)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO92_Msk  (0x10000000UL)            /*!< MCUN0GPIO92 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO91_Pos  (27UL)                    /*!< MCUN0GPIO91 (Bit 27)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO91_Msk  (0x8000000UL)             /*!< MCUN0GPIO91 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO90_Pos  (26UL)                    /*!< MCUN0GPIO90 (Bit 26)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO90_Msk  (0x4000000UL)             /*!< MCUN0GPIO90 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO89_Pos  (25UL)                    /*!< MCUN0GPIO89 (Bit 25)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO89_Msk  (0x2000000UL)             /*!< MCUN0GPIO89 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO88_Pos  (24UL)                    /*!< MCUN0GPIO88 (Bit 24)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO88_Msk  (0x1000000UL)             /*!< MCUN0GPIO88 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO87_Pos  (23UL)                    /*!< MCUN0GPIO87 (Bit 23)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO87_Msk  (0x800000UL)              /*!< MCUN0GPIO87 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO86_Pos  (22UL)                    /*!< MCUN0GPIO86 (Bit 22)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO86_Msk  (0x400000UL)              /*!< MCUN0GPIO86 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO85_Pos  (21UL)                    /*!< MCUN0GPIO85 (Bit 21)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO85_Msk  (0x200000UL)              /*!< MCUN0GPIO85 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO84_Pos  (20UL)                    /*!< MCUN0GPIO84 (Bit 20)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO84_Msk  (0x100000UL)              /*!< MCUN0GPIO84 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO83_Pos  (19UL)                    /*!< MCUN0GPIO83 (Bit 19)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO83_Msk  (0x80000UL)               /*!< MCUN0GPIO83 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO82_Pos  (18UL)                    /*!< MCUN0GPIO82 (Bit 18)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO82_Msk  (0x40000UL)               /*!< MCUN0GPIO82 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO81_Pos  (17UL)                    /*!< MCUN0GPIO81 (Bit 17)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO81_Msk  (0x20000UL)               /*!< MCUN0GPIO81 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO80_Pos  (16UL)                    /*!< MCUN0GPIO80 (Bit 16)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO80_Msk  (0x10000UL)               /*!< MCUN0GPIO80 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO79_Pos  (15UL)                    /*!< MCUN0GPIO79 (Bit 15)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO79_Msk  (0x8000UL)                /*!< MCUN0GPIO79 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO78_Pos  (14UL)                    /*!< MCUN0GPIO78 (Bit 14)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO78_Msk  (0x4000UL)                /*!< MCUN0GPIO78 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO77_Pos  (13UL)                    /*!< MCUN0GPIO77 (Bit 13)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO77_Msk  (0x2000UL)                /*!< MCUN0GPIO77 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO76_Pos  (12UL)                    /*!< MCUN0GPIO76 (Bit 12)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO76_Msk  (0x1000UL)                /*!< MCUN0GPIO76 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO75_Pos  (11UL)                    /*!< MCUN0GPIO75 (Bit 11)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO75_Msk  (0x800UL)                 /*!< MCUN0GPIO75 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO74_Pos  (10UL)                    /*!< MCUN0GPIO74 (Bit 10)                                  */
#define GPIO_MCUN0INT2EN_MCUN0GPIO74_Msk  (0x400UL)                 /*!< MCUN0GPIO74 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO73_Pos  (9UL)                     /*!< MCUN0GPIO73 (Bit 9)                                   */
#define GPIO_MCUN0INT2EN_MCUN0GPIO73_Msk  (0x200UL)                 /*!< MCUN0GPIO73 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO72_Pos  (8UL)                     /*!< MCUN0GPIO72 (Bit 8)                                   */
#define GPIO_MCUN0INT2EN_MCUN0GPIO72_Msk  (0x100UL)                 /*!< MCUN0GPIO72 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO71_Pos  (7UL)                     /*!< MCUN0GPIO71 (Bit 7)                                   */
#define GPIO_MCUN0INT2EN_MCUN0GPIO71_Msk  (0x80UL)                  /*!< MCUN0GPIO71 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO70_Pos  (6UL)                     /*!< MCUN0GPIO70 (Bit 6)                                   */
#define GPIO_MCUN0INT2EN_MCUN0GPIO70_Msk  (0x40UL)                  /*!< MCUN0GPIO70 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO69_Pos  (5UL)                     /*!< MCUN0GPIO69 (Bit 5)                                   */
#define GPIO_MCUN0INT2EN_MCUN0GPIO69_Msk  (0x20UL)                  /*!< MCUN0GPIO69 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO68_Pos  (4UL)                     /*!< MCUN0GPIO68 (Bit 4)                                   */
#define GPIO_MCUN0INT2EN_MCUN0GPIO68_Msk  (0x10UL)                  /*!< MCUN0GPIO68 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO67_Pos  (3UL)                     /*!< MCUN0GPIO67 (Bit 3)                                   */
#define GPIO_MCUN0INT2EN_MCUN0GPIO67_Msk  (0x8UL)                   /*!< MCUN0GPIO67 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO66_Pos  (2UL)                     /*!< MCUN0GPIO66 (Bit 2)                                   */
#define GPIO_MCUN0INT2EN_MCUN0GPIO66_Msk  (0x4UL)                   /*!< MCUN0GPIO66 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO65_Pos  (1UL)                     /*!< MCUN0GPIO65 (Bit 1)                                   */
#define GPIO_MCUN0INT2EN_MCUN0GPIO65_Msk  (0x2UL)                   /*!< MCUN0GPIO65 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2EN_MCUN0GPIO64_Pos  (0UL)                     /*!< MCUN0GPIO64 (Bit 0)                                   */
#define GPIO_MCUN0INT2EN_MCUN0GPIO64_Msk  (0x1UL)                   /*!< MCUN0GPIO64 (Bitfield-Mask: 0x01)                     */
/* =====================================================  MCUN0INT2STAT  ===================================================== */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO95_Pos (31UL)                   /*!< MCUN0GPIO95 (Bit 31)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO95_Msk (0x80000000UL)           /*!< MCUN0GPIO95 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO94_Pos (30UL)                   /*!< MCUN0GPIO94 (Bit 30)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO94_Msk (0x40000000UL)           /*!< MCUN0GPIO94 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO93_Pos (29UL)                   /*!< MCUN0GPIO93 (Bit 29)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO93_Msk (0x20000000UL)           /*!< MCUN0GPIO93 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO92_Pos (28UL)                   /*!< MCUN0GPIO92 (Bit 28)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO92_Msk (0x10000000UL)           /*!< MCUN0GPIO92 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO91_Pos (27UL)                   /*!< MCUN0GPIO91 (Bit 27)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO91_Msk (0x8000000UL)            /*!< MCUN0GPIO91 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO90_Pos (26UL)                   /*!< MCUN0GPIO90 (Bit 26)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO90_Msk (0x4000000UL)            /*!< MCUN0GPIO90 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO89_Pos (25UL)                   /*!< MCUN0GPIO89 (Bit 25)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO89_Msk (0x2000000UL)            /*!< MCUN0GPIO89 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO88_Pos (24UL)                   /*!< MCUN0GPIO88 (Bit 24)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO88_Msk (0x1000000UL)            /*!< MCUN0GPIO88 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO87_Pos (23UL)                   /*!< MCUN0GPIO87 (Bit 23)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO87_Msk (0x800000UL)             /*!< MCUN0GPIO87 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO86_Pos (22UL)                   /*!< MCUN0GPIO86 (Bit 22)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO86_Msk (0x400000UL)             /*!< MCUN0GPIO86 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO85_Pos (21UL)                   /*!< MCUN0GPIO85 (Bit 21)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO85_Msk (0x200000UL)             /*!< MCUN0GPIO85 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO84_Pos (20UL)                   /*!< MCUN0GPIO84 (Bit 20)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO84_Msk (0x100000UL)             /*!< MCUN0GPIO84 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO83_Pos (19UL)                   /*!< MCUN0GPIO83 (Bit 19)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO83_Msk (0x80000UL)              /*!< MCUN0GPIO83 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO82_Pos (18UL)                   /*!< MCUN0GPIO82 (Bit 18)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO82_Msk (0x40000UL)              /*!< MCUN0GPIO82 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO81_Pos (17UL)                   /*!< MCUN0GPIO81 (Bit 17)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO81_Msk (0x20000UL)              /*!< MCUN0GPIO81 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO80_Pos (16UL)                   /*!< MCUN0GPIO80 (Bit 16)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO80_Msk (0x10000UL)              /*!< MCUN0GPIO80 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO79_Pos (15UL)                   /*!< MCUN0GPIO79 (Bit 15)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO79_Msk (0x8000UL)               /*!< MCUN0GPIO79 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO78_Pos (14UL)                   /*!< MCUN0GPIO78 (Bit 14)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO78_Msk (0x4000UL)               /*!< MCUN0GPIO78 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO77_Pos (13UL)                   /*!< MCUN0GPIO77 (Bit 13)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO77_Msk (0x2000UL)               /*!< MCUN0GPIO77 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO76_Pos (12UL)                   /*!< MCUN0GPIO76 (Bit 12)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO76_Msk (0x1000UL)               /*!< MCUN0GPIO76 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO75_Pos (11UL)                   /*!< MCUN0GPIO75 (Bit 11)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO75_Msk (0x800UL)                /*!< MCUN0GPIO75 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO74_Pos (10UL)                   /*!< MCUN0GPIO74 (Bit 10)                                  */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO74_Msk (0x400UL)                /*!< MCUN0GPIO74 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO73_Pos (9UL)                    /*!< MCUN0GPIO73 (Bit 9)                                   */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO73_Msk (0x200UL)                /*!< MCUN0GPIO73 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO72_Pos (8UL)                    /*!< MCUN0GPIO72 (Bit 8)                                   */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO72_Msk (0x100UL)                /*!< MCUN0GPIO72 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO71_Pos (7UL)                    /*!< MCUN0GPIO71 (Bit 7)                                   */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO71_Msk (0x80UL)                 /*!< MCUN0GPIO71 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO70_Pos (6UL)                    /*!< MCUN0GPIO70 (Bit 6)                                   */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO70_Msk (0x40UL)                 /*!< MCUN0GPIO70 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO69_Pos (5UL)                    /*!< MCUN0GPIO69 (Bit 5)                                   */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO69_Msk (0x20UL)                 /*!< MCUN0GPIO69 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO68_Pos (4UL)                    /*!< MCUN0GPIO68 (Bit 4)                                   */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO68_Msk (0x10UL)                 /*!< MCUN0GPIO68 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO67_Pos (3UL)                    /*!< MCUN0GPIO67 (Bit 3)                                   */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO67_Msk (0x8UL)                  /*!< MCUN0GPIO67 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO66_Pos (2UL)                    /*!< MCUN0GPIO66 (Bit 2)                                   */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO66_Msk (0x4UL)                  /*!< MCUN0GPIO66 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO65_Pos (1UL)                    /*!< MCUN0GPIO65 (Bit 1)                                   */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO65_Msk (0x2UL)                  /*!< MCUN0GPIO65 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO64_Pos (0UL)                    /*!< MCUN0GPIO64 (Bit 0)                                   */
#define GPIO_MCUN0INT2STAT_MCUN0GPIO64_Msk (0x1UL)                  /*!< MCUN0GPIO64 (Bitfield-Mask: 0x01)                     */
/* =====================================================  MCUN0INT2CLR  ====================================================== */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO95_Pos (31UL)                    /*!< MCUN0GPIO95 (Bit 31)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO95_Msk (0x80000000UL)            /*!< MCUN0GPIO95 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO94_Pos (30UL)                    /*!< MCUN0GPIO94 (Bit 30)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO94_Msk (0x40000000UL)            /*!< MCUN0GPIO94 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO93_Pos (29UL)                    /*!< MCUN0GPIO93 (Bit 29)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO93_Msk (0x20000000UL)            /*!< MCUN0GPIO93 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO92_Pos (28UL)                    /*!< MCUN0GPIO92 (Bit 28)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO92_Msk (0x10000000UL)            /*!< MCUN0GPIO92 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO91_Pos (27UL)                    /*!< MCUN0GPIO91 (Bit 27)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO91_Msk (0x8000000UL)             /*!< MCUN0GPIO91 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO90_Pos (26UL)                    /*!< MCUN0GPIO90 (Bit 26)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO90_Msk (0x4000000UL)             /*!< MCUN0GPIO90 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO89_Pos (25UL)                    /*!< MCUN0GPIO89 (Bit 25)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO89_Msk (0x2000000UL)             /*!< MCUN0GPIO89 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO88_Pos (24UL)                    /*!< MCUN0GPIO88 (Bit 24)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO88_Msk (0x1000000UL)             /*!< MCUN0GPIO88 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO87_Pos (23UL)                    /*!< MCUN0GPIO87 (Bit 23)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO87_Msk (0x800000UL)              /*!< MCUN0GPIO87 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO86_Pos (22UL)                    /*!< MCUN0GPIO86 (Bit 22)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO86_Msk (0x400000UL)              /*!< MCUN0GPIO86 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO85_Pos (21UL)                    /*!< MCUN0GPIO85 (Bit 21)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO85_Msk (0x200000UL)              /*!< MCUN0GPIO85 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO84_Pos (20UL)                    /*!< MCUN0GPIO84 (Bit 20)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO84_Msk (0x100000UL)              /*!< MCUN0GPIO84 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO83_Pos (19UL)                    /*!< MCUN0GPIO83 (Bit 19)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO83_Msk (0x80000UL)               /*!< MCUN0GPIO83 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO82_Pos (18UL)                    /*!< MCUN0GPIO82 (Bit 18)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO82_Msk (0x40000UL)               /*!< MCUN0GPIO82 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO81_Pos (17UL)                    /*!< MCUN0GPIO81 (Bit 17)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO81_Msk (0x20000UL)               /*!< MCUN0GPIO81 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO80_Pos (16UL)                    /*!< MCUN0GPIO80 (Bit 16)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO80_Msk (0x10000UL)               /*!< MCUN0GPIO80 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO79_Pos (15UL)                    /*!< MCUN0GPIO79 (Bit 15)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO79_Msk (0x8000UL)                /*!< MCUN0GPIO79 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO78_Pos (14UL)                    /*!< MCUN0GPIO78 (Bit 14)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO78_Msk (0x4000UL)                /*!< MCUN0GPIO78 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO77_Pos (13UL)                    /*!< MCUN0GPIO77 (Bit 13)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO77_Msk (0x2000UL)                /*!< MCUN0GPIO77 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO76_Pos (12UL)                    /*!< MCUN0GPIO76 (Bit 12)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO76_Msk (0x1000UL)                /*!< MCUN0GPIO76 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO75_Pos (11UL)                    /*!< MCUN0GPIO75 (Bit 11)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO75_Msk (0x800UL)                 /*!< MCUN0GPIO75 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO74_Pos (10UL)                    /*!< MCUN0GPIO74 (Bit 10)                                  */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO74_Msk (0x400UL)                 /*!< MCUN0GPIO74 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO73_Pos (9UL)                     /*!< MCUN0GPIO73 (Bit 9)                                   */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO73_Msk (0x200UL)                 /*!< MCUN0GPIO73 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO72_Pos (8UL)                     /*!< MCUN0GPIO72 (Bit 8)                                   */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO72_Msk (0x100UL)                 /*!< MCUN0GPIO72 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO71_Pos (7UL)                     /*!< MCUN0GPIO71 (Bit 7)                                   */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO71_Msk (0x80UL)                  /*!< MCUN0GPIO71 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO70_Pos (6UL)                     /*!< MCUN0GPIO70 (Bit 6)                                   */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO70_Msk (0x40UL)                  /*!< MCUN0GPIO70 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO69_Pos (5UL)                     /*!< MCUN0GPIO69 (Bit 5)                                   */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO69_Msk (0x20UL)                  /*!< MCUN0GPIO69 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO68_Pos (4UL)                     /*!< MCUN0GPIO68 (Bit 4)                                   */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO68_Msk (0x10UL)                  /*!< MCUN0GPIO68 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO67_Pos (3UL)                     /*!< MCUN0GPIO67 (Bit 3)                                   */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO67_Msk (0x8UL)                   /*!< MCUN0GPIO67 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO66_Pos (2UL)                     /*!< MCUN0GPIO66 (Bit 2)                                   */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO66_Msk (0x4UL)                   /*!< MCUN0GPIO66 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO65_Pos (1UL)                     /*!< MCUN0GPIO65 (Bit 1)                                   */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO65_Msk (0x2UL)                   /*!< MCUN0GPIO65 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO64_Pos (0UL)                     /*!< MCUN0GPIO64 (Bit 0)                                   */
#define GPIO_MCUN0INT2CLR_MCUN0GPIO64_Msk (0x1UL)                   /*!< MCUN0GPIO64 (Bitfield-Mask: 0x01)                     */
/* =====================================================  MCUN0INT2SET  ====================================================== */
#define GPIO_MCUN0INT2SET_MCUN0GPIO95_Pos (31UL)                    /*!< MCUN0GPIO95 (Bit 31)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO95_Msk (0x80000000UL)            /*!< MCUN0GPIO95 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO94_Pos (30UL)                    /*!< MCUN0GPIO94 (Bit 30)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO94_Msk (0x40000000UL)            /*!< MCUN0GPIO94 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO93_Pos (29UL)                    /*!< MCUN0GPIO93 (Bit 29)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO93_Msk (0x20000000UL)            /*!< MCUN0GPIO93 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO92_Pos (28UL)                    /*!< MCUN0GPIO92 (Bit 28)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO92_Msk (0x10000000UL)            /*!< MCUN0GPIO92 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO91_Pos (27UL)                    /*!< MCUN0GPIO91 (Bit 27)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO91_Msk (0x8000000UL)             /*!< MCUN0GPIO91 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO90_Pos (26UL)                    /*!< MCUN0GPIO90 (Bit 26)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO90_Msk (0x4000000UL)             /*!< MCUN0GPIO90 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO89_Pos (25UL)                    /*!< MCUN0GPIO89 (Bit 25)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO89_Msk (0x2000000UL)             /*!< MCUN0GPIO89 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO88_Pos (24UL)                    /*!< MCUN0GPIO88 (Bit 24)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO88_Msk (0x1000000UL)             /*!< MCUN0GPIO88 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO87_Pos (23UL)                    /*!< MCUN0GPIO87 (Bit 23)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO87_Msk (0x800000UL)              /*!< MCUN0GPIO87 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO86_Pos (22UL)                    /*!< MCUN0GPIO86 (Bit 22)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO86_Msk (0x400000UL)              /*!< MCUN0GPIO86 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO85_Pos (21UL)                    /*!< MCUN0GPIO85 (Bit 21)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO85_Msk (0x200000UL)              /*!< MCUN0GPIO85 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO84_Pos (20UL)                    /*!< MCUN0GPIO84 (Bit 20)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO84_Msk (0x100000UL)              /*!< MCUN0GPIO84 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO83_Pos (19UL)                    /*!< MCUN0GPIO83 (Bit 19)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO83_Msk (0x80000UL)               /*!< MCUN0GPIO83 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO82_Pos (18UL)                    /*!< MCUN0GPIO82 (Bit 18)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO82_Msk (0x40000UL)               /*!< MCUN0GPIO82 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO81_Pos (17UL)                    /*!< MCUN0GPIO81 (Bit 17)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO81_Msk (0x20000UL)               /*!< MCUN0GPIO81 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO80_Pos (16UL)                    /*!< MCUN0GPIO80 (Bit 16)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO80_Msk (0x10000UL)               /*!< MCUN0GPIO80 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO79_Pos (15UL)                    /*!< MCUN0GPIO79 (Bit 15)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO79_Msk (0x8000UL)                /*!< MCUN0GPIO79 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO78_Pos (14UL)                    /*!< MCUN0GPIO78 (Bit 14)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO78_Msk (0x4000UL)                /*!< MCUN0GPIO78 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO77_Pos (13UL)                    /*!< MCUN0GPIO77 (Bit 13)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO77_Msk (0x2000UL)                /*!< MCUN0GPIO77 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO76_Pos (12UL)                    /*!< MCUN0GPIO76 (Bit 12)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO76_Msk (0x1000UL)                /*!< MCUN0GPIO76 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO75_Pos (11UL)                    /*!< MCUN0GPIO75 (Bit 11)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO75_Msk (0x800UL)                 /*!< MCUN0GPIO75 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO74_Pos (10UL)                    /*!< MCUN0GPIO74 (Bit 10)                                  */
#define GPIO_MCUN0INT2SET_MCUN0GPIO74_Msk (0x400UL)                 /*!< MCUN0GPIO74 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO73_Pos (9UL)                     /*!< MCUN0GPIO73 (Bit 9)                                   */
#define GPIO_MCUN0INT2SET_MCUN0GPIO73_Msk (0x200UL)                 /*!< MCUN0GPIO73 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO72_Pos (8UL)                     /*!< MCUN0GPIO72 (Bit 8)                                   */
#define GPIO_MCUN0INT2SET_MCUN0GPIO72_Msk (0x100UL)                 /*!< MCUN0GPIO72 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO71_Pos (7UL)                     /*!< MCUN0GPIO71 (Bit 7)                                   */
#define GPIO_MCUN0INT2SET_MCUN0GPIO71_Msk (0x80UL)                  /*!< MCUN0GPIO71 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO70_Pos (6UL)                     /*!< MCUN0GPIO70 (Bit 6)                                   */
#define GPIO_MCUN0INT2SET_MCUN0GPIO70_Msk (0x40UL)                  /*!< MCUN0GPIO70 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO69_Pos (5UL)                     /*!< MCUN0GPIO69 (Bit 5)                                   */
#define GPIO_MCUN0INT2SET_MCUN0GPIO69_Msk (0x20UL)                  /*!< MCUN0GPIO69 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO68_Pos (4UL)                     /*!< MCUN0GPIO68 (Bit 4)                                   */
#define GPIO_MCUN0INT2SET_MCUN0GPIO68_Msk (0x10UL)                  /*!< MCUN0GPIO68 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO67_Pos (3UL)                     /*!< MCUN0GPIO67 (Bit 3)                                   */
#define GPIO_MCUN0INT2SET_MCUN0GPIO67_Msk (0x8UL)                   /*!< MCUN0GPIO67 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO66_Pos (2UL)                     /*!< MCUN0GPIO66 (Bit 2)                                   */
#define GPIO_MCUN0INT2SET_MCUN0GPIO66_Msk (0x4UL)                   /*!< MCUN0GPIO66 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO65_Pos (1UL)                     /*!< MCUN0GPIO65 (Bit 1)                                   */
#define GPIO_MCUN0INT2SET_MCUN0GPIO65_Msk (0x2UL)                   /*!< MCUN0GPIO65 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT2SET_MCUN0GPIO64_Pos (0UL)                     /*!< MCUN0GPIO64 (Bit 0)                                   */
#define GPIO_MCUN0INT2SET_MCUN0GPIO64_Msk (0x1UL)                   /*!< MCUN0GPIO64 (Bitfield-Mask: 0x01)                     */
/* ======================================================  MCUN0INT3EN  ====================================================== */
#define GPIO_MCUN0INT3EN_MCUN0GPIO127_Pos (31UL)                    /*!< MCUN0GPIO127 (Bit 31)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO127_Msk (0x80000000UL)            /*!< MCUN0GPIO127 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO126_Pos (30UL)                    /*!< MCUN0GPIO126 (Bit 30)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO126_Msk (0x40000000UL)            /*!< MCUN0GPIO126 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO125_Pos (29UL)                    /*!< MCUN0GPIO125 (Bit 29)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO125_Msk (0x20000000UL)            /*!< MCUN0GPIO125 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO124_Pos (28UL)                    /*!< MCUN0GPIO124 (Bit 28)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO124_Msk (0x10000000UL)            /*!< MCUN0GPIO124 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO123_Pos (27UL)                    /*!< MCUN0GPIO123 (Bit 27)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO123_Msk (0x8000000UL)             /*!< MCUN0GPIO123 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO122_Pos (26UL)                    /*!< MCUN0GPIO122 (Bit 26)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO122_Msk (0x4000000UL)             /*!< MCUN0GPIO122 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO121_Pos (25UL)                    /*!< MCUN0GPIO121 (Bit 25)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO121_Msk (0x2000000UL)             /*!< MCUN0GPIO121 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO120_Pos (24UL)                    /*!< MCUN0GPIO120 (Bit 24)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO120_Msk (0x1000000UL)             /*!< MCUN0GPIO120 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO119_Pos (23UL)                    /*!< MCUN0GPIO119 (Bit 23)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO119_Msk (0x800000UL)              /*!< MCUN0GPIO119 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO118_Pos (22UL)                    /*!< MCUN0GPIO118 (Bit 22)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO118_Msk (0x400000UL)              /*!< MCUN0GPIO118 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO117_Pos (21UL)                    /*!< MCUN0GPIO117 (Bit 21)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO117_Msk (0x200000UL)              /*!< MCUN0GPIO117 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO116_Pos (20UL)                    /*!< MCUN0GPIO116 (Bit 20)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO116_Msk (0x100000UL)              /*!< MCUN0GPIO116 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO115_Pos (19UL)                    /*!< MCUN0GPIO115 (Bit 19)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO115_Msk (0x80000UL)               /*!< MCUN0GPIO115 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO114_Pos (18UL)                    /*!< MCUN0GPIO114 (Bit 18)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO114_Msk (0x40000UL)               /*!< MCUN0GPIO114 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO113_Pos (17UL)                    /*!< MCUN0GPIO113 (Bit 17)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO113_Msk (0x20000UL)               /*!< MCUN0GPIO113 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO112_Pos (16UL)                    /*!< MCUN0GPIO112 (Bit 16)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO112_Msk (0x10000UL)               /*!< MCUN0GPIO112 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO111_Pos (15UL)                    /*!< MCUN0GPIO111 (Bit 15)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO111_Msk (0x8000UL)                /*!< MCUN0GPIO111 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO110_Pos (14UL)                    /*!< MCUN0GPIO110 (Bit 14)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO110_Msk (0x4000UL)                /*!< MCUN0GPIO110 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO109_Pos (13UL)                    /*!< MCUN0GPIO109 (Bit 13)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO109_Msk (0x2000UL)                /*!< MCUN0GPIO109 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO108_Pos (12UL)                    /*!< MCUN0GPIO108 (Bit 12)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO108_Msk (0x1000UL)                /*!< MCUN0GPIO108 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO107_Pos (11UL)                    /*!< MCUN0GPIO107 (Bit 11)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO107_Msk (0x800UL)                 /*!< MCUN0GPIO107 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO106_Pos (10UL)                    /*!< MCUN0GPIO106 (Bit 10)                                 */
#define GPIO_MCUN0INT3EN_MCUN0GPIO106_Msk (0x400UL)                 /*!< MCUN0GPIO106 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO105_Pos (9UL)                     /*!< MCUN0GPIO105 (Bit 9)                                  */
#define GPIO_MCUN0INT3EN_MCUN0GPIO105_Msk (0x200UL)                 /*!< MCUN0GPIO105 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO104_Pos (8UL)                     /*!< MCUN0GPIO104 (Bit 8)                                  */
#define GPIO_MCUN0INT3EN_MCUN0GPIO104_Msk (0x100UL)                 /*!< MCUN0GPIO104 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO103_Pos (7UL)                     /*!< MCUN0GPIO103 (Bit 7)                                  */
#define GPIO_MCUN0INT3EN_MCUN0GPIO103_Msk (0x80UL)                  /*!< MCUN0GPIO103 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO102_Pos (6UL)                     /*!< MCUN0GPIO102 (Bit 6)                                  */
#define GPIO_MCUN0INT3EN_MCUN0GPIO102_Msk (0x40UL)                  /*!< MCUN0GPIO102 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO101_Pos (5UL)                     /*!< MCUN0GPIO101 (Bit 5)                                  */
#define GPIO_MCUN0INT3EN_MCUN0GPIO101_Msk (0x20UL)                  /*!< MCUN0GPIO101 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO100_Pos (4UL)                     /*!< MCUN0GPIO100 (Bit 4)                                  */
#define GPIO_MCUN0INT3EN_MCUN0GPIO100_Msk (0x10UL)                  /*!< MCUN0GPIO100 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3EN_MCUN0GPIO99_Pos  (3UL)                     /*!< MCUN0GPIO99 (Bit 3)                                   */
#define GPIO_MCUN0INT3EN_MCUN0GPIO99_Msk  (0x8UL)                   /*!< MCUN0GPIO99 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT3EN_MCUN0GPIO98_Pos  (2UL)                     /*!< MCUN0GPIO98 (Bit 2)                                   */
#define GPIO_MCUN0INT3EN_MCUN0GPIO98_Msk  (0x4UL)                   /*!< MCUN0GPIO98 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT3EN_MCUN0GPIO97_Pos  (1UL)                     /*!< MCUN0GPIO97 (Bit 1)                                   */
#define GPIO_MCUN0INT3EN_MCUN0GPIO97_Msk  (0x2UL)                   /*!< MCUN0GPIO97 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT3EN_MCUN0GPIO96_Pos  (0UL)                     /*!< MCUN0GPIO96 (Bit 0)                                   */
#define GPIO_MCUN0INT3EN_MCUN0GPIO96_Msk  (0x1UL)                   /*!< MCUN0GPIO96 (Bitfield-Mask: 0x01)                     */
/* =====================================================  MCUN0INT3STAT  ===================================================== */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO127_Pos (31UL)                  /*!< MCUN0GPIO127 (Bit 31)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO127_Msk (0x80000000UL)          /*!< MCUN0GPIO127 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO126_Pos (30UL)                  /*!< MCUN0GPIO126 (Bit 30)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO126_Msk (0x40000000UL)          /*!< MCUN0GPIO126 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO125_Pos (29UL)                  /*!< MCUN0GPIO125 (Bit 29)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO125_Msk (0x20000000UL)          /*!< MCUN0GPIO125 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO124_Pos (28UL)                  /*!< MCUN0GPIO124 (Bit 28)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO124_Msk (0x10000000UL)          /*!< MCUN0GPIO124 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO123_Pos (27UL)                  /*!< MCUN0GPIO123 (Bit 27)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO123_Msk (0x8000000UL)           /*!< MCUN0GPIO123 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO122_Pos (26UL)                  /*!< MCUN0GPIO122 (Bit 26)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO122_Msk (0x4000000UL)           /*!< MCUN0GPIO122 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO121_Pos (25UL)                  /*!< MCUN0GPIO121 (Bit 25)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO121_Msk (0x2000000UL)           /*!< MCUN0GPIO121 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO120_Pos (24UL)                  /*!< MCUN0GPIO120 (Bit 24)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO120_Msk (0x1000000UL)           /*!< MCUN0GPIO120 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO119_Pos (23UL)                  /*!< MCUN0GPIO119 (Bit 23)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO119_Msk (0x800000UL)            /*!< MCUN0GPIO119 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO118_Pos (22UL)                  /*!< MCUN0GPIO118 (Bit 22)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO118_Msk (0x400000UL)            /*!< MCUN0GPIO118 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO117_Pos (21UL)                  /*!< MCUN0GPIO117 (Bit 21)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO117_Msk (0x200000UL)            /*!< MCUN0GPIO117 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO116_Pos (20UL)                  /*!< MCUN0GPIO116 (Bit 20)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO116_Msk (0x100000UL)            /*!< MCUN0GPIO116 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO115_Pos (19UL)                  /*!< MCUN0GPIO115 (Bit 19)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO115_Msk (0x80000UL)             /*!< MCUN0GPIO115 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO114_Pos (18UL)                  /*!< MCUN0GPIO114 (Bit 18)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO114_Msk (0x40000UL)             /*!< MCUN0GPIO114 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO113_Pos (17UL)                  /*!< MCUN0GPIO113 (Bit 17)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO113_Msk (0x20000UL)             /*!< MCUN0GPIO113 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO112_Pos (16UL)                  /*!< MCUN0GPIO112 (Bit 16)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO112_Msk (0x10000UL)             /*!< MCUN0GPIO112 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO111_Pos (15UL)                  /*!< MCUN0GPIO111 (Bit 15)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO111_Msk (0x8000UL)              /*!< MCUN0GPIO111 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO110_Pos (14UL)                  /*!< MCUN0GPIO110 (Bit 14)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO110_Msk (0x4000UL)              /*!< MCUN0GPIO110 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO109_Pos (13UL)                  /*!< MCUN0GPIO109 (Bit 13)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO109_Msk (0x2000UL)              /*!< MCUN0GPIO109 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO108_Pos (12UL)                  /*!< MCUN0GPIO108 (Bit 12)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO108_Msk (0x1000UL)              /*!< MCUN0GPIO108 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO107_Pos (11UL)                  /*!< MCUN0GPIO107 (Bit 11)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO107_Msk (0x800UL)               /*!< MCUN0GPIO107 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO106_Pos (10UL)                  /*!< MCUN0GPIO106 (Bit 10)                                 */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO106_Msk (0x400UL)               /*!< MCUN0GPIO106 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO105_Pos (9UL)                   /*!< MCUN0GPIO105 (Bit 9)                                  */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO105_Msk (0x200UL)               /*!< MCUN0GPIO105 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO104_Pos (8UL)                   /*!< MCUN0GPIO104 (Bit 8)                                  */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO104_Msk (0x100UL)               /*!< MCUN0GPIO104 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO103_Pos (7UL)                   /*!< MCUN0GPIO103 (Bit 7)                                  */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO103_Msk (0x80UL)                /*!< MCUN0GPIO103 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO102_Pos (6UL)                   /*!< MCUN0GPIO102 (Bit 6)                                  */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO102_Msk (0x40UL)                /*!< MCUN0GPIO102 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO101_Pos (5UL)                   /*!< MCUN0GPIO101 (Bit 5)                                  */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO101_Msk (0x20UL)                /*!< MCUN0GPIO101 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO100_Pos (4UL)                   /*!< MCUN0GPIO100 (Bit 4)                                  */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO100_Msk (0x10UL)                /*!< MCUN0GPIO100 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO99_Pos (3UL)                    /*!< MCUN0GPIO99 (Bit 3)                                   */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO99_Msk (0x8UL)                  /*!< MCUN0GPIO99 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO98_Pos (2UL)                    /*!< MCUN0GPIO98 (Bit 2)                                   */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO98_Msk (0x4UL)                  /*!< MCUN0GPIO98 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO97_Pos (1UL)                    /*!< MCUN0GPIO97 (Bit 1)                                   */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO97_Msk (0x2UL)                  /*!< MCUN0GPIO97 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO96_Pos (0UL)                    /*!< MCUN0GPIO96 (Bit 0)                                   */
#define GPIO_MCUN0INT3STAT_MCUN0GPIO96_Msk (0x1UL)                  /*!< MCUN0GPIO96 (Bitfield-Mask: 0x01)                     */
/* =====================================================  MCUN0INT3CLR  ====================================================== */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO127_Pos (31UL)                   /*!< MCUN0GPIO127 (Bit 31)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO127_Msk (0x80000000UL)           /*!< MCUN0GPIO127 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO126_Pos (30UL)                   /*!< MCUN0GPIO126 (Bit 30)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO126_Msk (0x40000000UL)           /*!< MCUN0GPIO126 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO125_Pos (29UL)                   /*!< MCUN0GPIO125 (Bit 29)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO125_Msk (0x20000000UL)           /*!< MCUN0GPIO125 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO124_Pos (28UL)                   /*!< MCUN0GPIO124 (Bit 28)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO124_Msk (0x10000000UL)           /*!< MCUN0GPIO124 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO123_Pos (27UL)                   /*!< MCUN0GPIO123 (Bit 27)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO123_Msk (0x8000000UL)            /*!< MCUN0GPIO123 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO122_Pos (26UL)                   /*!< MCUN0GPIO122 (Bit 26)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO122_Msk (0x4000000UL)            /*!< MCUN0GPIO122 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO121_Pos (25UL)                   /*!< MCUN0GPIO121 (Bit 25)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO121_Msk (0x2000000UL)            /*!< MCUN0GPIO121 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO120_Pos (24UL)                   /*!< MCUN0GPIO120 (Bit 24)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO120_Msk (0x1000000UL)            /*!< MCUN0GPIO120 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO119_Pos (23UL)                   /*!< MCUN0GPIO119 (Bit 23)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO119_Msk (0x800000UL)             /*!< MCUN0GPIO119 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO118_Pos (22UL)                   /*!< MCUN0GPIO118 (Bit 22)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO118_Msk (0x400000UL)             /*!< MCUN0GPIO118 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO117_Pos (21UL)                   /*!< MCUN0GPIO117 (Bit 21)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO117_Msk (0x200000UL)             /*!< MCUN0GPIO117 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO116_Pos (20UL)                   /*!< MCUN0GPIO116 (Bit 20)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO116_Msk (0x100000UL)             /*!< MCUN0GPIO116 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO115_Pos (19UL)                   /*!< MCUN0GPIO115 (Bit 19)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO115_Msk (0x80000UL)              /*!< MCUN0GPIO115 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO114_Pos (18UL)                   /*!< MCUN0GPIO114 (Bit 18)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO114_Msk (0x40000UL)              /*!< MCUN0GPIO114 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO113_Pos (17UL)                   /*!< MCUN0GPIO113 (Bit 17)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO113_Msk (0x20000UL)              /*!< MCUN0GPIO113 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO112_Pos (16UL)                   /*!< MCUN0GPIO112 (Bit 16)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO112_Msk (0x10000UL)              /*!< MCUN0GPIO112 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO111_Pos (15UL)                   /*!< MCUN0GPIO111 (Bit 15)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO111_Msk (0x8000UL)               /*!< MCUN0GPIO111 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO110_Pos (14UL)                   /*!< MCUN0GPIO110 (Bit 14)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO110_Msk (0x4000UL)               /*!< MCUN0GPIO110 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO109_Pos (13UL)                   /*!< MCUN0GPIO109 (Bit 13)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO109_Msk (0x2000UL)               /*!< MCUN0GPIO109 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO108_Pos (12UL)                   /*!< MCUN0GPIO108 (Bit 12)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO108_Msk (0x1000UL)               /*!< MCUN0GPIO108 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO107_Pos (11UL)                   /*!< MCUN0GPIO107 (Bit 11)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO107_Msk (0x800UL)                /*!< MCUN0GPIO107 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO106_Pos (10UL)                   /*!< MCUN0GPIO106 (Bit 10)                                 */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO106_Msk (0x400UL)                /*!< MCUN0GPIO106 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO105_Pos (9UL)                    /*!< MCUN0GPIO105 (Bit 9)                                  */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO105_Msk (0x200UL)                /*!< MCUN0GPIO105 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO104_Pos (8UL)                    /*!< MCUN0GPIO104 (Bit 8)                                  */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO104_Msk (0x100UL)                /*!< MCUN0GPIO104 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO103_Pos (7UL)                    /*!< MCUN0GPIO103 (Bit 7)                                  */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO103_Msk (0x80UL)                 /*!< MCUN0GPIO103 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO102_Pos (6UL)                    /*!< MCUN0GPIO102 (Bit 6)                                  */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO102_Msk (0x40UL)                 /*!< MCUN0GPIO102 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO101_Pos (5UL)                    /*!< MCUN0GPIO101 (Bit 5)                                  */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO101_Msk (0x20UL)                 /*!< MCUN0GPIO101 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO100_Pos (4UL)                    /*!< MCUN0GPIO100 (Bit 4)                                  */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO100_Msk (0x10UL)                 /*!< MCUN0GPIO100 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO99_Pos (3UL)                     /*!< MCUN0GPIO99 (Bit 3)                                   */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO99_Msk (0x8UL)                   /*!< MCUN0GPIO99 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO98_Pos (2UL)                     /*!< MCUN0GPIO98 (Bit 2)                                   */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO98_Msk (0x4UL)                   /*!< MCUN0GPIO98 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO97_Pos (1UL)                     /*!< MCUN0GPIO97 (Bit 1)                                   */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO97_Msk (0x2UL)                   /*!< MCUN0GPIO97 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO96_Pos (0UL)                     /*!< MCUN0GPIO96 (Bit 0)                                   */
#define GPIO_MCUN0INT3CLR_MCUN0GPIO96_Msk (0x1UL)                   /*!< MCUN0GPIO96 (Bitfield-Mask: 0x01)                     */
/* =====================================================  MCUN0INT3SET  ====================================================== */
#define GPIO_MCUN0INT3SET_MCUN0GPIO127_Pos (31UL)                   /*!< MCUN0GPIO127 (Bit 31)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO127_Msk (0x80000000UL)           /*!< MCUN0GPIO127 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO126_Pos (30UL)                   /*!< MCUN0GPIO126 (Bit 30)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO126_Msk (0x40000000UL)           /*!< MCUN0GPIO126 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO125_Pos (29UL)                   /*!< MCUN0GPIO125 (Bit 29)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO125_Msk (0x20000000UL)           /*!< MCUN0GPIO125 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO124_Pos (28UL)                   /*!< MCUN0GPIO124 (Bit 28)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO124_Msk (0x10000000UL)           /*!< MCUN0GPIO124 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO123_Pos (27UL)                   /*!< MCUN0GPIO123 (Bit 27)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO123_Msk (0x8000000UL)            /*!< MCUN0GPIO123 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO122_Pos (26UL)                   /*!< MCUN0GPIO122 (Bit 26)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO122_Msk (0x4000000UL)            /*!< MCUN0GPIO122 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO121_Pos (25UL)                   /*!< MCUN0GPIO121 (Bit 25)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO121_Msk (0x2000000UL)            /*!< MCUN0GPIO121 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO120_Pos (24UL)                   /*!< MCUN0GPIO120 (Bit 24)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO120_Msk (0x1000000UL)            /*!< MCUN0GPIO120 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO119_Pos (23UL)                   /*!< MCUN0GPIO119 (Bit 23)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO119_Msk (0x800000UL)             /*!< MCUN0GPIO119 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO118_Pos (22UL)                   /*!< MCUN0GPIO118 (Bit 22)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO118_Msk (0x400000UL)             /*!< MCUN0GPIO118 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO117_Pos (21UL)                   /*!< MCUN0GPIO117 (Bit 21)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO117_Msk (0x200000UL)             /*!< MCUN0GPIO117 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO116_Pos (20UL)                   /*!< MCUN0GPIO116 (Bit 20)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO116_Msk (0x100000UL)             /*!< MCUN0GPIO116 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO115_Pos (19UL)                   /*!< MCUN0GPIO115 (Bit 19)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO115_Msk (0x80000UL)              /*!< MCUN0GPIO115 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO114_Pos (18UL)                   /*!< MCUN0GPIO114 (Bit 18)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO114_Msk (0x40000UL)              /*!< MCUN0GPIO114 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO113_Pos (17UL)                   /*!< MCUN0GPIO113 (Bit 17)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO113_Msk (0x20000UL)              /*!< MCUN0GPIO113 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO112_Pos (16UL)                   /*!< MCUN0GPIO112 (Bit 16)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO112_Msk (0x10000UL)              /*!< MCUN0GPIO112 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO111_Pos (15UL)                   /*!< MCUN0GPIO111 (Bit 15)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO111_Msk (0x8000UL)               /*!< MCUN0GPIO111 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO110_Pos (14UL)                   /*!< MCUN0GPIO110 (Bit 14)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO110_Msk (0x4000UL)               /*!< MCUN0GPIO110 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO109_Pos (13UL)                   /*!< MCUN0GPIO109 (Bit 13)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO109_Msk (0x2000UL)               /*!< MCUN0GPIO109 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO108_Pos (12UL)                   /*!< MCUN0GPIO108 (Bit 12)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO108_Msk (0x1000UL)               /*!< MCUN0GPIO108 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO107_Pos (11UL)                   /*!< MCUN0GPIO107 (Bit 11)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO107_Msk (0x800UL)                /*!< MCUN0GPIO107 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO106_Pos (10UL)                   /*!< MCUN0GPIO106 (Bit 10)                                 */
#define GPIO_MCUN0INT3SET_MCUN0GPIO106_Msk (0x400UL)                /*!< MCUN0GPIO106 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO105_Pos (9UL)                    /*!< MCUN0GPIO105 (Bit 9)                                  */
#define GPIO_MCUN0INT3SET_MCUN0GPIO105_Msk (0x200UL)                /*!< MCUN0GPIO105 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO104_Pos (8UL)                    /*!< MCUN0GPIO104 (Bit 8)                                  */
#define GPIO_MCUN0INT3SET_MCUN0GPIO104_Msk (0x100UL)                /*!< MCUN0GPIO104 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO103_Pos (7UL)                    /*!< MCUN0GPIO103 (Bit 7)                                  */
#define GPIO_MCUN0INT3SET_MCUN0GPIO103_Msk (0x80UL)                 /*!< MCUN0GPIO103 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO102_Pos (6UL)                    /*!< MCUN0GPIO102 (Bit 6)                                  */
#define GPIO_MCUN0INT3SET_MCUN0GPIO102_Msk (0x40UL)                 /*!< MCUN0GPIO102 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO101_Pos (5UL)                    /*!< MCUN0GPIO101 (Bit 5)                                  */
#define GPIO_MCUN0INT3SET_MCUN0GPIO101_Msk (0x20UL)                 /*!< MCUN0GPIO101 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO100_Pos (4UL)                    /*!< MCUN0GPIO100 (Bit 4)                                  */
#define GPIO_MCUN0INT3SET_MCUN0GPIO100_Msk (0x10UL)                 /*!< MCUN0GPIO100 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN0INT3SET_MCUN0GPIO99_Pos (3UL)                     /*!< MCUN0GPIO99 (Bit 3)                                   */
#define GPIO_MCUN0INT3SET_MCUN0GPIO99_Msk (0x8UL)                   /*!< MCUN0GPIO99 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT3SET_MCUN0GPIO98_Pos (2UL)                     /*!< MCUN0GPIO98 (Bit 2)                                   */
#define GPIO_MCUN0INT3SET_MCUN0GPIO98_Msk (0x4UL)                   /*!< MCUN0GPIO98 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT3SET_MCUN0GPIO97_Pos (1UL)                     /*!< MCUN0GPIO97 (Bit 1)                                   */
#define GPIO_MCUN0INT3SET_MCUN0GPIO97_Msk (0x2UL)                   /*!< MCUN0GPIO97 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN0INT3SET_MCUN0GPIO96_Pos (0UL)                     /*!< MCUN0GPIO96 (Bit 0)                                   */
#define GPIO_MCUN0INT3SET_MCUN0GPIO96_Msk (0x1UL)                   /*!< MCUN0GPIO96 (Bitfield-Mask: 0x01)                     */
/* ======================================================  MCUN1INT0EN  ====================================================== */
#define GPIO_MCUN1INT0EN_MCUN1GPIO31_Pos  (31UL)                    /*!< MCUN1GPIO31 (Bit 31)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO31_Msk  (0x80000000UL)            /*!< MCUN1GPIO31 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO30_Pos  (30UL)                    /*!< MCUN1GPIO30 (Bit 30)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO30_Msk  (0x40000000UL)            /*!< MCUN1GPIO30 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO29_Pos  (29UL)                    /*!< MCUN1GPIO29 (Bit 29)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO29_Msk  (0x20000000UL)            /*!< MCUN1GPIO29 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO28_Pos  (28UL)                    /*!< MCUN1GPIO28 (Bit 28)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO28_Msk  (0x10000000UL)            /*!< MCUN1GPIO28 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO27_Pos  (27UL)                    /*!< MCUN1GPIO27 (Bit 27)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO27_Msk  (0x8000000UL)             /*!< MCUN1GPIO27 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO26_Pos  (26UL)                    /*!< MCUN1GPIO26 (Bit 26)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO26_Msk  (0x4000000UL)             /*!< MCUN1GPIO26 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO25_Pos  (25UL)                    /*!< MCUN1GPIO25 (Bit 25)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO25_Msk  (0x2000000UL)             /*!< MCUN1GPIO25 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO24_Pos  (24UL)                    /*!< MCUN1GPIO24 (Bit 24)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO24_Msk  (0x1000000UL)             /*!< MCUN1GPIO24 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO23_Pos  (23UL)                    /*!< MCUN1GPIO23 (Bit 23)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO23_Msk  (0x800000UL)              /*!< MCUN1GPIO23 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO22_Pos  (22UL)                    /*!< MCUN1GPIO22 (Bit 22)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO22_Msk  (0x400000UL)              /*!< MCUN1GPIO22 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO21_Pos  (21UL)                    /*!< MCUN1GPIO21 (Bit 21)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO21_Msk  (0x200000UL)              /*!< MCUN1GPIO21 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO20_Pos  (20UL)                    /*!< MCUN1GPIO20 (Bit 20)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO20_Msk  (0x100000UL)              /*!< MCUN1GPIO20 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO19_Pos  (19UL)                    /*!< MCUN1GPIO19 (Bit 19)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO19_Msk  (0x80000UL)               /*!< MCUN1GPIO19 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO18_Pos  (18UL)                    /*!< MCUN1GPIO18 (Bit 18)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO18_Msk  (0x40000UL)               /*!< MCUN1GPIO18 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO17_Pos  (17UL)                    /*!< MCUN1GPIO17 (Bit 17)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO17_Msk  (0x20000UL)               /*!< MCUN1GPIO17 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO16_Pos  (16UL)                    /*!< MCUN1GPIO16 (Bit 16)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO16_Msk  (0x10000UL)               /*!< MCUN1GPIO16 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO15_Pos  (15UL)                    /*!< MCUN1GPIO15 (Bit 15)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO15_Msk  (0x8000UL)                /*!< MCUN1GPIO15 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO14_Pos  (14UL)                    /*!< MCUN1GPIO14 (Bit 14)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO14_Msk  (0x4000UL)                /*!< MCUN1GPIO14 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO13_Pos  (13UL)                    /*!< MCUN1GPIO13 (Bit 13)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO13_Msk  (0x2000UL)                /*!< MCUN1GPIO13 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO12_Pos  (12UL)                    /*!< MCUN1GPIO12 (Bit 12)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO12_Msk  (0x1000UL)                /*!< MCUN1GPIO12 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO11_Pos  (11UL)                    /*!< MCUN1GPIO11 (Bit 11)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO11_Msk  (0x800UL)                 /*!< MCUN1GPIO11 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO10_Pos  (10UL)                    /*!< MCUN1GPIO10 (Bit 10)                                  */
#define GPIO_MCUN1INT0EN_MCUN1GPIO10_Msk  (0x400UL)                 /*!< MCUN1GPIO10 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0EN_MCUN1GPIO9_Pos   (9UL)                     /*!< MCUN1GPIO9 (Bit 9)                                    */
#define GPIO_MCUN1INT0EN_MCUN1GPIO9_Msk   (0x200UL)                 /*!< MCUN1GPIO9 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0EN_MCUN1GPIO8_Pos   (8UL)                     /*!< MCUN1GPIO8 (Bit 8)                                    */
#define GPIO_MCUN1INT0EN_MCUN1GPIO8_Msk   (0x100UL)                 /*!< MCUN1GPIO8 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0EN_MCUN1GPIO7_Pos   (7UL)                     /*!< MCUN1GPIO7 (Bit 7)                                    */
#define GPIO_MCUN1INT0EN_MCUN1GPIO7_Msk   (0x80UL)                  /*!< MCUN1GPIO7 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0EN_MCUN1GPIO6_Pos   (6UL)                     /*!< MCUN1GPIO6 (Bit 6)                                    */
#define GPIO_MCUN1INT0EN_MCUN1GPIO6_Msk   (0x40UL)                  /*!< MCUN1GPIO6 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0EN_MCUN1GPIO5_Pos   (5UL)                     /*!< MCUN1GPIO5 (Bit 5)                                    */
#define GPIO_MCUN1INT0EN_MCUN1GPIO5_Msk   (0x20UL)                  /*!< MCUN1GPIO5 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0EN_MCUN1GPIO4_Pos   (4UL)                     /*!< MCUN1GPIO4 (Bit 4)                                    */
#define GPIO_MCUN1INT0EN_MCUN1GPIO4_Msk   (0x10UL)                  /*!< MCUN1GPIO4 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0EN_MCUN1GPIO3_Pos   (3UL)                     /*!< MCUN1GPIO3 (Bit 3)                                    */
#define GPIO_MCUN1INT0EN_MCUN1GPIO3_Msk   (0x8UL)                   /*!< MCUN1GPIO3 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0EN_MCUN1GPIO2_Pos   (2UL)                     /*!< MCUN1GPIO2 (Bit 2)                                    */
#define GPIO_MCUN1INT0EN_MCUN1GPIO2_Msk   (0x4UL)                   /*!< MCUN1GPIO2 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0EN_MCUN1GPIO1_Pos   (1UL)                     /*!< MCUN1GPIO1 (Bit 1)                                    */
#define GPIO_MCUN1INT0EN_MCUN1GPIO1_Msk   (0x2UL)                   /*!< MCUN1GPIO1 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0EN_MCUN1GPIO0_Pos   (0UL)                     /*!< MCUN1GPIO0 (Bit 0)                                    */
#define GPIO_MCUN1INT0EN_MCUN1GPIO0_Msk   (0x1UL)                   /*!< MCUN1GPIO0 (Bitfield-Mask: 0x01)                      */
/* =====================================================  MCUN1INT0STAT  ===================================================== */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO31_Pos (31UL)                   /*!< MCUN1GPIO31 (Bit 31)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO31_Msk (0x80000000UL)           /*!< MCUN1GPIO31 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO30_Pos (30UL)                   /*!< MCUN1GPIO30 (Bit 30)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO30_Msk (0x40000000UL)           /*!< MCUN1GPIO30 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO29_Pos (29UL)                   /*!< MCUN1GPIO29 (Bit 29)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO29_Msk (0x20000000UL)           /*!< MCUN1GPIO29 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO28_Pos (28UL)                   /*!< MCUN1GPIO28 (Bit 28)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO28_Msk (0x10000000UL)           /*!< MCUN1GPIO28 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO27_Pos (27UL)                   /*!< MCUN1GPIO27 (Bit 27)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO27_Msk (0x8000000UL)            /*!< MCUN1GPIO27 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO26_Pos (26UL)                   /*!< MCUN1GPIO26 (Bit 26)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO26_Msk (0x4000000UL)            /*!< MCUN1GPIO26 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO25_Pos (25UL)                   /*!< MCUN1GPIO25 (Bit 25)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO25_Msk (0x2000000UL)            /*!< MCUN1GPIO25 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO24_Pos (24UL)                   /*!< MCUN1GPIO24 (Bit 24)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO24_Msk (0x1000000UL)            /*!< MCUN1GPIO24 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO23_Pos (23UL)                   /*!< MCUN1GPIO23 (Bit 23)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO23_Msk (0x800000UL)             /*!< MCUN1GPIO23 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO22_Pos (22UL)                   /*!< MCUN1GPIO22 (Bit 22)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO22_Msk (0x400000UL)             /*!< MCUN1GPIO22 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO21_Pos (21UL)                   /*!< MCUN1GPIO21 (Bit 21)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO21_Msk (0x200000UL)             /*!< MCUN1GPIO21 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO20_Pos (20UL)                   /*!< MCUN1GPIO20 (Bit 20)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO20_Msk (0x100000UL)             /*!< MCUN1GPIO20 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO19_Pos (19UL)                   /*!< MCUN1GPIO19 (Bit 19)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO19_Msk (0x80000UL)              /*!< MCUN1GPIO19 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO18_Pos (18UL)                   /*!< MCUN1GPIO18 (Bit 18)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO18_Msk (0x40000UL)              /*!< MCUN1GPIO18 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO17_Pos (17UL)                   /*!< MCUN1GPIO17 (Bit 17)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO17_Msk (0x20000UL)              /*!< MCUN1GPIO17 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO16_Pos (16UL)                   /*!< MCUN1GPIO16 (Bit 16)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO16_Msk (0x10000UL)              /*!< MCUN1GPIO16 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO15_Pos (15UL)                   /*!< MCUN1GPIO15 (Bit 15)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO15_Msk (0x8000UL)               /*!< MCUN1GPIO15 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO14_Pos (14UL)                   /*!< MCUN1GPIO14 (Bit 14)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO14_Msk (0x4000UL)               /*!< MCUN1GPIO14 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO13_Pos (13UL)                   /*!< MCUN1GPIO13 (Bit 13)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO13_Msk (0x2000UL)               /*!< MCUN1GPIO13 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO12_Pos (12UL)                   /*!< MCUN1GPIO12 (Bit 12)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO12_Msk (0x1000UL)               /*!< MCUN1GPIO12 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO11_Pos (11UL)                   /*!< MCUN1GPIO11 (Bit 11)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO11_Msk (0x800UL)                /*!< MCUN1GPIO11 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO10_Pos (10UL)                   /*!< MCUN1GPIO10 (Bit 10)                                  */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO10_Msk (0x400UL)                /*!< MCUN1GPIO10 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO9_Pos (9UL)                     /*!< MCUN1GPIO9 (Bit 9)                                    */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO9_Msk (0x200UL)                 /*!< MCUN1GPIO9 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO8_Pos (8UL)                     /*!< MCUN1GPIO8 (Bit 8)                                    */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO8_Msk (0x100UL)                 /*!< MCUN1GPIO8 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO7_Pos (7UL)                     /*!< MCUN1GPIO7 (Bit 7)                                    */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO7_Msk (0x80UL)                  /*!< MCUN1GPIO7 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO6_Pos (6UL)                     /*!< MCUN1GPIO6 (Bit 6)                                    */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO6_Msk (0x40UL)                  /*!< MCUN1GPIO6 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO5_Pos (5UL)                     /*!< MCUN1GPIO5 (Bit 5)                                    */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO5_Msk (0x20UL)                  /*!< MCUN1GPIO5 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO4_Pos (4UL)                     /*!< MCUN1GPIO4 (Bit 4)                                    */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO4_Msk (0x10UL)                  /*!< MCUN1GPIO4 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO3_Pos (3UL)                     /*!< MCUN1GPIO3 (Bit 3)                                    */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO3_Msk (0x8UL)                   /*!< MCUN1GPIO3 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO2_Pos (2UL)                     /*!< MCUN1GPIO2 (Bit 2)                                    */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO2_Msk (0x4UL)                   /*!< MCUN1GPIO2 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO1_Pos (1UL)                     /*!< MCUN1GPIO1 (Bit 1)                                    */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO1_Msk (0x2UL)                   /*!< MCUN1GPIO1 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO0_Pos (0UL)                     /*!< MCUN1GPIO0 (Bit 0)                                    */
#define GPIO_MCUN1INT0STAT_MCUN1GPIO0_Msk (0x1UL)                   /*!< MCUN1GPIO0 (Bitfield-Mask: 0x01)                      */
/* =====================================================  MCUN1INT0CLR  ====================================================== */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO31_Pos (31UL)                    /*!< MCUN1GPIO31 (Bit 31)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO31_Msk (0x80000000UL)            /*!< MCUN1GPIO31 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO30_Pos (30UL)                    /*!< MCUN1GPIO30 (Bit 30)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO30_Msk (0x40000000UL)            /*!< MCUN1GPIO30 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO29_Pos (29UL)                    /*!< MCUN1GPIO29 (Bit 29)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO29_Msk (0x20000000UL)            /*!< MCUN1GPIO29 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO28_Pos (28UL)                    /*!< MCUN1GPIO28 (Bit 28)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO28_Msk (0x10000000UL)            /*!< MCUN1GPIO28 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO27_Pos (27UL)                    /*!< MCUN1GPIO27 (Bit 27)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO27_Msk (0x8000000UL)             /*!< MCUN1GPIO27 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO26_Pos (26UL)                    /*!< MCUN1GPIO26 (Bit 26)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO26_Msk (0x4000000UL)             /*!< MCUN1GPIO26 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO25_Pos (25UL)                    /*!< MCUN1GPIO25 (Bit 25)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO25_Msk (0x2000000UL)             /*!< MCUN1GPIO25 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO24_Pos (24UL)                    /*!< MCUN1GPIO24 (Bit 24)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO24_Msk (0x1000000UL)             /*!< MCUN1GPIO24 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO23_Pos (23UL)                    /*!< MCUN1GPIO23 (Bit 23)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO23_Msk (0x800000UL)              /*!< MCUN1GPIO23 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO22_Pos (22UL)                    /*!< MCUN1GPIO22 (Bit 22)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO22_Msk (0x400000UL)              /*!< MCUN1GPIO22 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO21_Pos (21UL)                    /*!< MCUN1GPIO21 (Bit 21)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO21_Msk (0x200000UL)              /*!< MCUN1GPIO21 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO20_Pos (20UL)                    /*!< MCUN1GPIO20 (Bit 20)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO20_Msk (0x100000UL)              /*!< MCUN1GPIO20 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO19_Pos (19UL)                    /*!< MCUN1GPIO19 (Bit 19)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO19_Msk (0x80000UL)               /*!< MCUN1GPIO19 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO18_Pos (18UL)                    /*!< MCUN1GPIO18 (Bit 18)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO18_Msk (0x40000UL)               /*!< MCUN1GPIO18 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO17_Pos (17UL)                    /*!< MCUN1GPIO17 (Bit 17)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO17_Msk (0x20000UL)               /*!< MCUN1GPIO17 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO16_Pos (16UL)                    /*!< MCUN1GPIO16 (Bit 16)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO16_Msk (0x10000UL)               /*!< MCUN1GPIO16 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO15_Pos (15UL)                    /*!< MCUN1GPIO15 (Bit 15)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO15_Msk (0x8000UL)                /*!< MCUN1GPIO15 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO14_Pos (14UL)                    /*!< MCUN1GPIO14 (Bit 14)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO14_Msk (0x4000UL)                /*!< MCUN1GPIO14 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO13_Pos (13UL)                    /*!< MCUN1GPIO13 (Bit 13)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO13_Msk (0x2000UL)                /*!< MCUN1GPIO13 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO12_Pos (12UL)                    /*!< MCUN1GPIO12 (Bit 12)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO12_Msk (0x1000UL)                /*!< MCUN1GPIO12 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO11_Pos (11UL)                    /*!< MCUN1GPIO11 (Bit 11)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO11_Msk (0x800UL)                 /*!< MCUN1GPIO11 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO10_Pos (10UL)                    /*!< MCUN1GPIO10 (Bit 10)                                  */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO10_Msk (0x400UL)                 /*!< MCUN1GPIO10 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO9_Pos  (9UL)                     /*!< MCUN1GPIO9 (Bit 9)                                    */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO9_Msk  (0x200UL)                 /*!< MCUN1GPIO9 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO8_Pos  (8UL)                     /*!< MCUN1GPIO8 (Bit 8)                                    */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO8_Msk  (0x100UL)                 /*!< MCUN1GPIO8 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO7_Pos  (7UL)                     /*!< MCUN1GPIO7 (Bit 7)                                    */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO7_Msk  (0x80UL)                  /*!< MCUN1GPIO7 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO6_Pos  (6UL)                     /*!< MCUN1GPIO6 (Bit 6)                                    */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO6_Msk  (0x40UL)                  /*!< MCUN1GPIO6 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO5_Pos  (5UL)                     /*!< MCUN1GPIO5 (Bit 5)                                    */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO5_Msk  (0x20UL)                  /*!< MCUN1GPIO5 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO4_Pos  (4UL)                     /*!< MCUN1GPIO4 (Bit 4)                                    */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO4_Msk  (0x10UL)                  /*!< MCUN1GPIO4 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO3_Pos  (3UL)                     /*!< MCUN1GPIO3 (Bit 3)                                    */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO3_Msk  (0x8UL)                   /*!< MCUN1GPIO3 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO2_Pos  (2UL)                     /*!< MCUN1GPIO2 (Bit 2)                                    */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO2_Msk  (0x4UL)                   /*!< MCUN1GPIO2 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO1_Pos  (1UL)                     /*!< MCUN1GPIO1 (Bit 1)                                    */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO1_Msk  (0x2UL)                   /*!< MCUN1GPIO1 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO0_Pos  (0UL)                     /*!< MCUN1GPIO0 (Bit 0)                                    */
#define GPIO_MCUN1INT0CLR_MCUN1GPIO0_Msk  (0x1UL)                   /*!< MCUN1GPIO0 (Bitfield-Mask: 0x01)                      */
/* =====================================================  MCUN1INT0SET  ====================================================== */
#define GPIO_MCUN1INT0SET_MCUN1GPIO31_Pos (31UL)                    /*!< MCUN1GPIO31 (Bit 31)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO31_Msk (0x80000000UL)            /*!< MCUN1GPIO31 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO30_Pos (30UL)                    /*!< MCUN1GPIO30 (Bit 30)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO30_Msk (0x40000000UL)            /*!< MCUN1GPIO30 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO29_Pos (29UL)                    /*!< MCUN1GPIO29 (Bit 29)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO29_Msk (0x20000000UL)            /*!< MCUN1GPIO29 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO28_Pos (28UL)                    /*!< MCUN1GPIO28 (Bit 28)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO28_Msk (0x10000000UL)            /*!< MCUN1GPIO28 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO27_Pos (27UL)                    /*!< MCUN1GPIO27 (Bit 27)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO27_Msk (0x8000000UL)             /*!< MCUN1GPIO27 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO26_Pos (26UL)                    /*!< MCUN1GPIO26 (Bit 26)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO26_Msk (0x4000000UL)             /*!< MCUN1GPIO26 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO25_Pos (25UL)                    /*!< MCUN1GPIO25 (Bit 25)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO25_Msk (0x2000000UL)             /*!< MCUN1GPIO25 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO24_Pos (24UL)                    /*!< MCUN1GPIO24 (Bit 24)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO24_Msk (0x1000000UL)             /*!< MCUN1GPIO24 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO23_Pos (23UL)                    /*!< MCUN1GPIO23 (Bit 23)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO23_Msk (0x800000UL)              /*!< MCUN1GPIO23 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO22_Pos (22UL)                    /*!< MCUN1GPIO22 (Bit 22)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO22_Msk (0x400000UL)              /*!< MCUN1GPIO22 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO21_Pos (21UL)                    /*!< MCUN1GPIO21 (Bit 21)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO21_Msk (0x200000UL)              /*!< MCUN1GPIO21 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO20_Pos (20UL)                    /*!< MCUN1GPIO20 (Bit 20)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO20_Msk (0x100000UL)              /*!< MCUN1GPIO20 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO19_Pos (19UL)                    /*!< MCUN1GPIO19 (Bit 19)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO19_Msk (0x80000UL)               /*!< MCUN1GPIO19 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO18_Pos (18UL)                    /*!< MCUN1GPIO18 (Bit 18)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO18_Msk (0x40000UL)               /*!< MCUN1GPIO18 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO17_Pos (17UL)                    /*!< MCUN1GPIO17 (Bit 17)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO17_Msk (0x20000UL)               /*!< MCUN1GPIO17 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO16_Pos (16UL)                    /*!< MCUN1GPIO16 (Bit 16)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO16_Msk (0x10000UL)               /*!< MCUN1GPIO16 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO15_Pos (15UL)                    /*!< MCUN1GPIO15 (Bit 15)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO15_Msk (0x8000UL)                /*!< MCUN1GPIO15 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO14_Pos (14UL)                    /*!< MCUN1GPIO14 (Bit 14)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO14_Msk (0x4000UL)                /*!< MCUN1GPIO14 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO13_Pos (13UL)                    /*!< MCUN1GPIO13 (Bit 13)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO13_Msk (0x2000UL)                /*!< MCUN1GPIO13 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO12_Pos (12UL)                    /*!< MCUN1GPIO12 (Bit 12)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO12_Msk (0x1000UL)                /*!< MCUN1GPIO12 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO11_Pos (11UL)                    /*!< MCUN1GPIO11 (Bit 11)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO11_Msk (0x800UL)                 /*!< MCUN1GPIO11 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO10_Pos (10UL)                    /*!< MCUN1GPIO10 (Bit 10)                                  */
#define GPIO_MCUN1INT0SET_MCUN1GPIO10_Msk (0x400UL)                 /*!< MCUN1GPIO10 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT0SET_MCUN1GPIO9_Pos  (9UL)                     /*!< MCUN1GPIO9 (Bit 9)                                    */
#define GPIO_MCUN1INT0SET_MCUN1GPIO9_Msk  (0x200UL)                 /*!< MCUN1GPIO9 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0SET_MCUN1GPIO8_Pos  (8UL)                     /*!< MCUN1GPIO8 (Bit 8)                                    */
#define GPIO_MCUN1INT0SET_MCUN1GPIO8_Msk  (0x100UL)                 /*!< MCUN1GPIO8 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0SET_MCUN1GPIO7_Pos  (7UL)                     /*!< MCUN1GPIO7 (Bit 7)                                    */
#define GPIO_MCUN1INT0SET_MCUN1GPIO7_Msk  (0x80UL)                  /*!< MCUN1GPIO7 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0SET_MCUN1GPIO6_Pos  (6UL)                     /*!< MCUN1GPIO6 (Bit 6)                                    */
#define GPIO_MCUN1INT0SET_MCUN1GPIO6_Msk  (0x40UL)                  /*!< MCUN1GPIO6 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0SET_MCUN1GPIO5_Pos  (5UL)                     /*!< MCUN1GPIO5 (Bit 5)                                    */
#define GPIO_MCUN1INT0SET_MCUN1GPIO5_Msk  (0x20UL)                  /*!< MCUN1GPIO5 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0SET_MCUN1GPIO4_Pos  (4UL)                     /*!< MCUN1GPIO4 (Bit 4)                                    */
#define GPIO_MCUN1INT0SET_MCUN1GPIO4_Msk  (0x10UL)                  /*!< MCUN1GPIO4 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0SET_MCUN1GPIO3_Pos  (3UL)                     /*!< MCUN1GPIO3 (Bit 3)                                    */
#define GPIO_MCUN1INT0SET_MCUN1GPIO3_Msk  (0x8UL)                   /*!< MCUN1GPIO3 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0SET_MCUN1GPIO2_Pos  (2UL)                     /*!< MCUN1GPIO2 (Bit 2)                                    */
#define GPIO_MCUN1INT0SET_MCUN1GPIO2_Msk  (0x4UL)                   /*!< MCUN1GPIO2 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0SET_MCUN1GPIO1_Pos  (1UL)                     /*!< MCUN1GPIO1 (Bit 1)                                    */
#define GPIO_MCUN1INT0SET_MCUN1GPIO1_Msk  (0x2UL)                   /*!< MCUN1GPIO1 (Bitfield-Mask: 0x01)                      */
#define GPIO_MCUN1INT0SET_MCUN1GPIO0_Pos  (0UL)                     /*!< MCUN1GPIO0 (Bit 0)                                    */
#define GPIO_MCUN1INT0SET_MCUN1GPIO0_Msk  (0x1UL)                   /*!< MCUN1GPIO0 (Bitfield-Mask: 0x01)                      */
/* ======================================================  MCUN1INT1EN  ====================================================== */
#define GPIO_MCUN1INT1EN_MCUN1GPIO63_Pos  (31UL)                    /*!< MCUN1GPIO63 (Bit 31)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO63_Msk  (0x80000000UL)            /*!< MCUN1GPIO63 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO62_Pos  (30UL)                    /*!< MCUN1GPIO62 (Bit 30)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO62_Msk  (0x40000000UL)            /*!< MCUN1GPIO62 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO61_Pos  (29UL)                    /*!< MCUN1GPIO61 (Bit 29)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO61_Msk  (0x20000000UL)            /*!< MCUN1GPIO61 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO60_Pos  (28UL)                    /*!< MCUN1GPIO60 (Bit 28)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO60_Msk  (0x10000000UL)            /*!< MCUN1GPIO60 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO59_Pos  (27UL)                    /*!< MCUN1GPIO59 (Bit 27)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO59_Msk  (0x8000000UL)             /*!< MCUN1GPIO59 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO58_Pos  (26UL)                    /*!< MCUN1GPIO58 (Bit 26)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO58_Msk  (0x4000000UL)             /*!< MCUN1GPIO58 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO57_Pos  (25UL)                    /*!< MCUN1GPIO57 (Bit 25)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO57_Msk  (0x2000000UL)             /*!< MCUN1GPIO57 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO56_Pos  (24UL)                    /*!< MCUN1GPIO56 (Bit 24)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO56_Msk  (0x1000000UL)             /*!< MCUN1GPIO56 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO55_Pos  (23UL)                    /*!< MCUN1GPIO55 (Bit 23)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO55_Msk  (0x800000UL)              /*!< MCUN1GPIO55 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO54_Pos  (22UL)                    /*!< MCUN1GPIO54 (Bit 22)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO54_Msk  (0x400000UL)              /*!< MCUN1GPIO54 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO53_Pos  (21UL)                    /*!< MCUN1GPIO53 (Bit 21)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO53_Msk  (0x200000UL)              /*!< MCUN1GPIO53 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO52_Pos  (20UL)                    /*!< MCUN1GPIO52 (Bit 20)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO52_Msk  (0x100000UL)              /*!< MCUN1GPIO52 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO51_Pos  (19UL)                    /*!< MCUN1GPIO51 (Bit 19)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO51_Msk  (0x80000UL)               /*!< MCUN1GPIO51 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO50_Pos  (18UL)                    /*!< MCUN1GPIO50 (Bit 18)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO50_Msk  (0x40000UL)               /*!< MCUN1GPIO50 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO49_Pos  (17UL)                    /*!< MCUN1GPIO49 (Bit 17)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO49_Msk  (0x20000UL)               /*!< MCUN1GPIO49 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO48_Pos  (16UL)                    /*!< MCUN1GPIO48 (Bit 16)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO48_Msk  (0x10000UL)               /*!< MCUN1GPIO48 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO47_Pos  (15UL)                    /*!< MCUN1GPIO47 (Bit 15)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO47_Msk  (0x8000UL)                /*!< MCUN1GPIO47 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO46_Pos  (14UL)                    /*!< MCUN1GPIO46 (Bit 14)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO46_Msk  (0x4000UL)                /*!< MCUN1GPIO46 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO45_Pos  (13UL)                    /*!< MCUN1GPIO45 (Bit 13)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO45_Msk  (0x2000UL)                /*!< MCUN1GPIO45 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO44_Pos  (12UL)                    /*!< MCUN1GPIO44 (Bit 12)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO44_Msk  (0x1000UL)                /*!< MCUN1GPIO44 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO43_Pos  (11UL)                    /*!< MCUN1GPIO43 (Bit 11)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO43_Msk  (0x800UL)                 /*!< MCUN1GPIO43 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO42_Pos  (10UL)                    /*!< MCUN1GPIO42 (Bit 10)                                  */
#define GPIO_MCUN1INT1EN_MCUN1GPIO42_Msk  (0x400UL)                 /*!< MCUN1GPIO42 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO41_Pos  (9UL)                     /*!< MCUN1GPIO41 (Bit 9)                                   */
#define GPIO_MCUN1INT1EN_MCUN1GPIO41_Msk  (0x200UL)                 /*!< MCUN1GPIO41 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO40_Pos  (8UL)                     /*!< MCUN1GPIO40 (Bit 8)                                   */
#define GPIO_MCUN1INT1EN_MCUN1GPIO40_Msk  (0x100UL)                 /*!< MCUN1GPIO40 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO39_Pos  (7UL)                     /*!< MCUN1GPIO39 (Bit 7)                                   */
#define GPIO_MCUN1INT1EN_MCUN1GPIO39_Msk  (0x80UL)                  /*!< MCUN1GPIO39 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO38_Pos  (6UL)                     /*!< MCUN1GPIO38 (Bit 6)                                   */
#define GPIO_MCUN1INT1EN_MCUN1GPIO38_Msk  (0x40UL)                  /*!< MCUN1GPIO38 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO37_Pos  (5UL)                     /*!< MCUN1GPIO37 (Bit 5)                                   */
#define GPIO_MCUN1INT1EN_MCUN1GPIO37_Msk  (0x20UL)                  /*!< MCUN1GPIO37 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO36_Pos  (4UL)                     /*!< MCUN1GPIO36 (Bit 4)                                   */
#define GPIO_MCUN1INT1EN_MCUN1GPIO36_Msk  (0x10UL)                  /*!< MCUN1GPIO36 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO35_Pos  (3UL)                     /*!< MCUN1GPIO35 (Bit 3)                                   */
#define GPIO_MCUN1INT1EN_MCUN1GPIO35_Msk  (0x8UL)                   /*!< MCUN1GPIO35 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO34_Pos  (2UL)                     /*!< MCUN1GPIO34 (Bit 2)                                   */
#define GPIO_MCUN1INT1EN_MCUN1GPIO34_Msk  (0x4UL)                   /*!< MCUN1GPIO34 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO33_Pos  (1UL)                     /*!< MCUN1GPIO33 (Bit 1)                                   */
#define GPIO_MCUN1INT1EN_MCUN1GPIO33_Msk  (0x2UL)                   /*!< MCUN1GPIO33 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1EN_MCUN1GPIO32_Pos  (0UL)                     /*!< MCUN1GPIO32 (Bit 0)                                   */
#define GPIO_MCUN1INT1EN_MCUN1GPIO32_Msk  (0x1UL)                   /*!< MCUN1GPIO32 (Bitfield-Mask: 0x01)                     */
/* =====================================================  MCUN1INT1STAT  ===================================================== */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO63_Pos (31UL)                   /*!< MCUN1GPIO63 (Bit 31)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO63_Msk (0x80000000UL)           /*!< MCUN1GPIO63 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO62_Pos (30UL)                   /*!< MCUN1GPIO62 (Bit 30)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO62_Msk (0x40000000UL)           /*!< MCUN1GPIO62 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO61_Pos (29UL)                   /*!< MCUN1GPIO61 (Bit 29)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO61_Msk (0x20000000UL)           /*!< MCUN1GPIO61 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO60_Pos (28UL)                   /*!< MCUN1GPIO60 (Bit 28)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO60_Msk (0x10000000UL)           /*!< MCUN1GPIO60 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO59_Pos (27UL)                   /*!< MCUN1GPIO59 (Bit 27)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO59_Msk (0x8000000UL)            /*!< MCUN1GPIO59 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO58_Pos (26UL)                   /*!< MCUN1GPIO58 (Bit 26)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO58_Msk (0x4000000UL)            /*!< MCUN1GPIO58 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO57_Pos (25UL)                   /*!< MCUN1GPIO57 (Bit 25)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO57_Msk (0x2000000UL)            /*!< MCUN1GPIO57 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO56_Pos (24UL)                   /*!< MCUN1GPIO56 (Bit 24)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO56_Msk (0x1000000UL)            /*!< MCUN1GPIO56 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO55_Pos (23UL)                   /*!< MCUN1GPIO55 (Bit 23)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO55_Msk (0x800000UL)             /*!< MCUN1GPIO55 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO54_Pos (22UL)                   /*!< MCUN1GPIO54 (Bit 22)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO54_Msk (0x400000UL)             /*!< MCUN1GPIO54 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO53_Pos (21UL)                   /*!< MCUN1GPIO53 (Bit 21)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO53_Msk (0x200000UL)             /*!< MCUN1GPIO53 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO52_Pos (20UL)                   /*!< MCUN1GPIO52 (Bit 20)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO52_Msk (0x100000UL)             /*!< MCUN1GPIO52 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO51_Pos (19UL)                   /*!< MCUN1GPIO51 (Bit 19)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO51_Msk (0x80000UL)              /*!< MCUN1GPIO51 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO50_Pos (18UL)                   /*!< MCUN1GPIO50 (Bit 18)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO50_Msk (0x40000UL)              /*!< MCUN1GPIO50 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO49_Pos (17UL)                   /*!< MCUN1GPIO49 (Bit 17)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO49_Msk (0x20000UL)              /*!< MCUN1GPIO49 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO48_Pos (16UL)                   /*!< MCUN1GPIO48 (Bit 16)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO48_Msk (0x10000UL)              /*!< MCUN1GPIO48 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO47_Pos (15UL)                   /*!< MCUN1GPIO47 (Bit 15)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO47_Msk (0x8000UL)               /*!< MCUN1GPIO47 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO46_Pos (14UL)                   /*!< MCUN1GPIO46 (Bit 14)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO46_Msk (0x4000UL)               /*!< MCUN1GPIO46 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO45_Pos (13UL)                   /*!< MCUN1GPIO45 (Bit 13)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO45_Msk (0x2000UL)               /*!< MCUN1GPIO45 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO44_Pos (12UL)                   /*!< MCUN1GPIO44 (Bit 12)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO44_Msk (0x1000UL)               /*!< MCUN1GPIO44 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO43_Pos (11UL)                   /*!< MCUN1GPIO43 (Bit 11)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO43_Msk (0x800UL)                /*!< MCUN1GPIO43 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO42_Pos (10UL)                   /*!< MCUN1GPIO42 (Bit 10)                                  */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO42_Msk (0x400UL)                /*!< MCUN1GPIO42 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO41_Pos (9UL)                    /*!< MCUN1GPIO41 (Bit 9)                                   */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO41_Msk (0x200UL)                /*!< MCUN1GPIO41 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO40_Pos (8UL)                    /*!< MCUN1GPIO40 (Bit 8)                                   */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO40_Msk (0x100UL)                /*!< MCUN1GPIO40 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO39_Pos (7UL)                    /*!< MCUN1GPIO39 (Bit 7)                                   */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO39_Msk (0x80UL)                 /*!< MCUN1GPIO39 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO38_Pos (6UL)                    /*!< MCUN1GPIO38 (Bit 6)                                   */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO38_Msk (0x40UL)                 /*!< MCUN1GPIO38 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO37_Pos (5UL)                    /*!< MCUN1GPIO37 (Bit 5)                                   */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO37_Msk (0x20UL)                 /*!< MCUN1GPIO37 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO36_Pos (4UL)                    /*!< MCUN1GPIO36 (Bit 4)                                   */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO36_Msk (0x10UL)                 /*!< MCUN1GPIO36 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO35_Pos (3UL)                    /*!< MCUN1GPIO35 (Bit 3)                                   */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO35_Msk (0x8UL)                  /*!< MCUN1GPIO35 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO34_Pos (2UL)                    /*!< MCUN1GPIO34 (Bit 2)                                   */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO34_Msk (0x4UL)                  /*!< MCUN1GPIO34 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO33_Pos (1UL)                    /*!< MCUN1GPIO33 (Bit 1)                                   */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO33_Msk (0x2UL)                  /*!< MCUN1GPIO33 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO32_Pos (0UL)                    /*!< MCUN1GPIO32 (Bit 0)                                   */
#define GPIO_MCUN1INT1STAT_MCUN1GPIO32_Msk (0x1UL)                  /*!< MCUN1GPIO32 (Bitfield-Mask: 0x01)                     */
/* =====================================================  MCUN1INT1CLR  ====================================================== */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO63_Pos (31UL)                    /*!< MCUN1GPIO63 (Bit 31)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO63_Msk (0x80000000UL)            /*!< MCUN1GPIO63 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO62_Pos (30UL)                    /*!< MCUN1GPIO62 (Bit 30)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO62_Msk (0x40000000UL)            /*!< MCUN1GPIO62 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO61_Pos (29UL)                    /*!< MCUN1GPIO61 (Bit 29)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO61_Msk (0x20000000UL)            /*!< MCUN1GPIO61 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO60_Pos (28UL)                    /*!< MCUN1GPIO60 (Bit 28)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO60_Msk (0x10000000UL)            /*!< MCUN1GPIO60 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO59_Pos (27UL)                    /*!< MCUN1GPIO59 (Bit 27)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO59_Msk (0x8000000UL)             /*!< MCUN1GPIO59 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO58_Pos (26UL)                    /*!< MCUN1GPIO58 (Bit 26)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO58_Msk (0x4000000UL)             /*!< MCUN1GPIO58 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO57_Pos (25UL)                    /*!< MCUN1GPIO57 (Bit 25)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO57_Msk (0x2000000UL)             /*!< MCUN1GPIO57 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO56_Pos (24UL)                    /*!< MCUN1GPIO56 (Bit 24)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO56_Msk (0x1000000UL)             /*!< MCUN1GPIO56 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO55_Pos (23UL)                    /*!< MCUN1GPIO55 (Bit 23)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO55_Msk (0x800000UL)              /*!< MCUN1GPIO55 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO54_Pos (22UL)                    /*!< MCUN1GPIO54 (Bit 22)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO54_Msk (0x400000UL)              /*!< MCUN1GPIO54 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO53_Pos (21UL)                    /*!< MCUN1GPIO53 (Bit 21)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO53_Msk (0x200000UL)              /*!< MCUN1GPIO53 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO52_Pos (20UL)                    /*!< MCUN1GPIO52 (Bit 20)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO52_Msk (0x100000UL)              /*!< MCUN1GPIO52 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO51_Pos (19UL)                    /*!< MCUN1GPIO51 (Bit 19)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO51_Msk (0x80000UL)               /*!< MCUN1GPIO51 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO50_Pos (18UL)                    /*!< MCUN1GPIO50 (Bit 18)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO50_Msk (0x40000UL)               /*!< MCUN1GPIO50 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO49_Pos (17UL)                    /*!< MCUN1GPIO49 (Bit 17)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO49_Msk (0x20000UL)               /*!< MCUN1GPIO49 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO48_Pos (16UL)                    /*!< MCUN1GPIO48 (Bit 16)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO48_Msk (0x10000UL)               /*!< MCUN1GPIO48 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO47_Pos (15UL)                    /*!< MCUN1GPIO47 (Bit 15)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO47_Msk (0x8000UL)                /*!< MCUN1GPIO47 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO46_Pos (14UL)                    /*!< MCUN1GPIO46 (Bit 14)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO46_Msk (0x4000UL)                /*!< MCUN1GPIO46 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO45_Pos (13UL)                    /*!< MCUN1GPIO45 (Bit 13)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO45_Msk (0x2000UL)                /*!< MCUN1GPIO45 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO44_Pos (12UL)                    /*!< MCUN1GPIO44 (Bit 12)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO44_Msk (0x1000UL)                /*!< MCUN1GPIO44 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO43_Pos (11UL)                    /*!< MCUN1GPIO43 (Bit 11)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO43_Msk (0x800UL)                 /*!< MCUN1GPIO43 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO42_Pos (10UL)                    /*!< MCUN1GPIO42 (Bit 10)                                  */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO42_Msk (0x400UL)                 /*!< MCUN1GPIO42 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO41_Pos (9UL)                     /*!< MCUN1GPIO41 (Bit 9)                                   */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO41_Msk (0x200UL)                 /*!< MCUN1GPIO41 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO40_Pos (8UL)                     /*!< MCUN1GPIO40 (Bit 8)                                   */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO40_Msk (0x100UL)                 /*!< MCUN1GPIO40 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO39_Pos (7UL)                     /*!< MCUN1GPIO39 (Bit 7)                                   */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO39_Msk (0x80UL)                  /*!< MCUN1GPIO39 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO38_Pos (6UL)                     /*!< MCUN1GPIO38 (Bit 6)                                   */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO38_Msk (0x40UL)                  /*!< MCUN1GPIO38 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO37_Pos (5UL)                     /*!< MCUN1GPIO37 (Bit 5)                                   */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO37_Msk (0x20UL)                  /*!< MCUN1GPIO37 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO36_Pos (4UL)                     /*!< MCUN1GPIO36 (Bit 4)                                   */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO36_Msk (0x10UL)                  /*!< MCUN1GPIO36 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO35_Pos (3UL)                     /*!< MCUN1GPIO35 (Bit 3)                                   */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO35_Msk (0x8UL)                   /*!< MCUN1GPIO35 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO34_Pos (2UL)                     /*!< MCUN1GPIO34 (Bit 2)                                   */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO34_Msk (0x4UL)                   /*!< MCUN1GPIO34 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO33_Pos (1UL)                     /*!< MCUN1GPIO33 (Bit 1)                                   */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO33_Msk (0x2UL)                   /*!< MCUN1GPIO33 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO32_Pos (0UL)                     /*!< MCUN1GPIO32 (Bit 0)                                   */
#define GPIO_MCUN1INT1CLR_MCUN1GPIO32_Msk (0x1UL)                   /*!< MCUN1GPIO32 (Bitfield-Mask: 0x01)                     */
/* =====================================================  MCUN1INT1SET  ====================================================== */
#define GPIO_MCUN1INT1SET_MCUN1GPIO63_Pos (31UL)                    /*!< MCUN1GPIO63 (Bit 31)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO63_Msk (0x80000000UL)            /*!< MCUN1GPIO63 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO62_Pos (30UL)                    /*!< MCUN1GPIO62 (Bit 30)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO62_Msk (0x40000000UL)            /*!< MCUN1GPIO62 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO61_Pos (29UL)                    /*!< MCUN1GPIO61 (Bit 29)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO61_Msk (0x20000000UL)            /*!< MCUN1GPIO61 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO60_Pos (28UL)                    /*!< MCUN1GPIO60 (Bit 28)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO60_Msk (0x10000000UL)            /*!< MCUN1GPIO60 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO59_Pos (27UL)                    /*!< MCUN1GPIO59 (Bit 27)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO59_Msk (0x8000000UL)             /*!< MCUN1GPIO59 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO58_Pos (26UL)                    /*!< MCUN1GPIO58 (Bit 26)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO58_Msk (0x4000000UL)             /*!< MCUN1GPIO58 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO57_Pos (25UL)                    /*!< MCUN1GPIO57 (Bit 25)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO57_Msk (0x2000000UL)             /*!< MCUN1GPIO57 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO56_Pos (24UL)                    /*!< MCUN1GPIO56 (Bit 24)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO56_Msk (0x1000000UL)             /*!< MCUN1GPIO56 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO55_Pos (23UL)                    /*!< MCUN1GPIO55 (Bit 23)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO55_Msk (0x800000UL)              /*!< MCUN1GPIO55 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO54_Pos (22UL)                    /*!< MCUN1GPIO54 (Bit 22)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO54_Msk (0x400000UL)              /*!< MCUN1GPIO54 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO53_Pos (21UL)                    /*!< MCUN1GPIO53 (Bit 21)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO53_Msk (0x200000UL)              /*!< MCUN1GPIO53 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO52_Pos (20UL)                    /*!< MCUN1GPIO52 (Bit 20)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO52_Msk (0x100000UL)              /*!< MCUN1GPIO52 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO51_Pos (19UL)                    /*!< MCUN1GPIO51 (Bit 19)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO51_Msk (0x80000UL)               /*!< MCUN1GPIO51 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO50_Pos (18UL)                    /*!< MCUN1GPIO50 (Bit 18)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO50_Msk (0x40000UL)               /*!< MCUN1GPIO50 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO49_Pos (17UL)                    /*!< MCUN1GPIO49 (Bit 17)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO49_Msk (0x20000UL)               /*!< MCUN1GPIO49 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO48_Pos (16UL)                    /*!< MCUN1GPIO48 (Bit 16)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO48_Msk (0x10000UL)               /*!< MCUN1GPIO48 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO47_Pos (15UL)                    /*!< MCUN1GPIO47 (Bit 15)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO47_Msk (0x8000UL)                /*!< MCUN1GPIO47 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO46_Pos (14UL)                    /*!< MCUN1GPIO46 (Bit 14)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO46_Msk (0x4000UL)                /*!< MCUN1GPIO46 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO45_Pos (13UL)                    /*!< MCUN1GPIO45 (Bit 13)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO45_Msk (0x2000UL)                /*!< MCUN1GPIO45 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO44_Pos (12UL)                    /*!< MCUN1GPIO44 (Bit 12)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO44_Msk (0x1000UL)                /*!< MCUN1GPIO44 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO43_Pos (11UL)                    /*!< MCUN1GPIO43 (Bit 11)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO43_Msk (0x800UL)                 /*!< MCUN1GPIO43 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO42_Pos (10UL)                    /*!< MCUN1GPIO42 (Bit 10)                                  */
#define GPIO_MCUN1INT1SET_MCUN1GPIO42_Msk (0x400UL)                 /*!< MCUN1GPIO42 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO41_Pos (9UL)                     /*!< MCUN1GPIO41 (Bit 9)                                   */
#define GPIO_MCUN1INT1SET_MCUN1GPIO41_Msk (0x200UL)                 /*!< MCUN1GPIO41 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO40_Pos (8UL)                     /*!< MCUN1GPIO40 (Bit 8)                                   */
#define GPIO_MCUN1INT1SET_MCUN1GPIO40_Msk (0x100UL)                 /*!< MCUN1GPIO40 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO39_Pos (7UL)                     /*!< MCUN1GPIO39 (Bit 7)                                   */
#define GPIO_MCUN1INT1SET_MCUN1GPIO39_Msk (0x80UL)                  /*!< MCUN1GPIO39 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO38_Pos (6UL)                     /*!< MCUN1GPIO38 (Bit 6)                                   */
#define GPIO_MCUN1INT1SET_MCUN1GPIO38_Msk (0x40UL)                  /*!< MCUN1GPIO38 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO37_Pos (5UL)                     /*!< MCUN1GPIO37 (Bit 5)                                   */
#define GPIO_MCUN1INT1SET_MCUN1GPIO37_Msk (0x20UL)                  /*!< MCUN1GPIO37 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO36_Pos (4UL)                     /*!< MCUN1GPIO36 (Bit 4)                                   */
#define GPIO_MCUN1INT1SET_MCUN1GPIO36_Msk (0x10UL)                  /*!< MCUN1GPIO36 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO35_Pos (3UL)                     /*!< MCUN1GPIO35 (Bit 3)                                   */
#define GPIO_MCUN1INT1SET_MCUN1GPIO35_Msk (0x8UL)                   /*!< MCUN1GPIO35 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO34_Pos (2UL)                     /*!< MCUN1GPIO34 (Bit 2)                                   */
#define GPIO_MCUN1INT1SET_MCUN1GPIO34_Msk (0x4UL)                   /*!< MCUN1GPIO34 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO33_Pos (1UL)                     /*!< MCUN1GPIO33 (Bit 1)                                   */
#define GPIO_MCUN1INT1SET_MCUN1GPIO33_Msk (0x2UL)                   /*!< MCUN1GPIO33 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT1SET_MCUN1GPIO32_Pos (0UL)                     /*!< MCUN1GPIO32 (Bit 0)                                   */
#define GPIO_MCUN1INT1SET_MCUN1GPIO32_Msk (0x1UL)                   /*!< MCUN1GPIO32 (Bitfield-Mask: 0x01)                     */
/* ======================================================  MCUN1INT2EN  ====================================================== */
#define GPIO_MCUN1INT2EN_MCUN1GPIO95_Pos  (31UL)                    /*!< MCUN1GPIO95 (Bit 31)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO95_Msk  (0x80000000UL)            /*!< MCUN1GPIO95 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO94_Pos  (30UL)                    /*!< MCUN1GPIO94 (Bit 30)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO94_Msk  (0x40000000UL)            /*!< MCUN1GPIO94 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO93_Pos  (29UL)                    /*!< MCUN1GPIO93 (Bit 29)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO93_Msk  (0x20000000UL)            /*!< MCUN1GPIO93 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO92_Pos  (28UL)                    /*!< MCUN1GPIO92 (Bit 28)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO92_Msk  (0x10000000UL)            /*!< MCUN1GPIO92 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO91_Pos  (27UL)                    /*!< MCUN1GPIO91 (Bit 27)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO91_Msk  (0x8000000UL)             /*!< MCUN1GPIO91 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO90_Pos  (26UL)                    /*!< MCUN1GPIO90 (Bit 26)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO90_Msk  (0x4000000UL)             /*!< MCUN1GPIO90 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO89_Pos  (25UL)                    /*!< MCUN1GPIO89 (Bit 25)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO89_Msk  (0x2000000UL)             /*!< MCUN1GPIO89 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO88_Pos  (24UL)                    /*!< MCUN1GPIO88 (Bit 24)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO88_Msk  (0x1000000UL)             /*!< MCUN1GPIO88 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO87_Pos  (23UL)                    /*!< MCUN1GPIO87 (Bit 23)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO87_Msk  (0x800000UL)              /*!< MCUN1GPIO87 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO86_Pos  (22UL)                    /*!< MCUN1GPIO86 (Bit 22)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO86_Msk  (0x400000UL)              /*!< MCUN1GPIO86 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO85_Pos  (21UL)                    /*!< MCUN1GPIO85 (Bit 21)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO85_Msk  (0x200000UL)              /*!< MCUN1GPIO85 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO84_Pos  (20UL)                    /*!< MCUN1GPIO84 (Bit 20)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO84_Msk  (0x100000UL)              /*!< MCUN1GPIO84 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO83_Pos  (19UL)                    /*!< MCUN1GPIO83 (Bit 19)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO83_Msk  (0x80000UL)               /*!< MCUN1GPIO83 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO82_Pos  (18UL)                    /*!< MCUN1GPIO82 (Bit 18)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO82_Msk  (0x40000UL)               /*!< MCUN1GPIO82 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO81_Pos  (17UL)                    /*!< MCUN1GPIO81 (Bit 17)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO81_Msk  (0x20000UL)               /*!< MCUN1GPIO81 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO80_Pos  (16UL)                    /*!< MCUN1GPIO80 (Bit 16)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO80_Msk  (0x10000UL)               /*!< MCUN1GPIO80 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO79_Pos  (15UL)                    /*!< MCUN1GPIO79 (Bit 15)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO79_Msk  (0x8000UL)                /*!< MCUN1GPIO79 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO78_Pos  (14UL)                    /*!< MCUN1GPIO78 (Bit 14)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO78_Msk  (0x4000UL)                /*!< MCUN1GPIO78 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO77_Pos  (13UL)                    /*!< MCUN1GPIO77 (Bit 13)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO77_Msk  (0x2000UL)                /*!< MCUN1GPIO77 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO76_Pos  (12UL)                    /*!< MCUN1GPIO76 (Bit 12)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO76_Msk  (0x1000UL)                /*!< MCUN1GPIO76 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO75_Pos  (11UL)                    /*!< MCUN1GPIO75 (Bit 11)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO75_Msk  (0x800UL)                 /*!< MCUN1GPIO75 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO74_Pos  (10UL)                    /*!< MCUN1GPIO74 (Bit 10)                                  */
#define GPIO_MCUN1INT2EN_MCUN1GPIO74_Msk  (0x400UL)                 /*!< MCUN1GPIO74 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO73_Pos  (9UL)                     /*!< MCUN1GPIO73 (Bit 9)                                   */
#define GPIO_MCUN1INT2EN_MCUN1GPIO73_Msk  (0x200UL)                 /*!< MCUN1GPIO73 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO72_Pos  (8UL)                     /*!< MCUN1GPIO72 (Bit 8)                                   */
#define GPIO_MCUN1INT2EN_MCUN1GPIO72_Msk  (0x100UL)                 /*!< MCUN1GPIO72 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO71_Pos  (7UL)                     /*!< MCUN1GPIO71 (Bit 7)                                   */
#define GPIO_MCUN1INT2EN_MCUN1GPIO71_Msk  (0x80UL)                  /*!< MCUN1GPIO71 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO70_Pos  (6UL)                     /*!< MCUN1GPIO70 (Bit 6)                                   */
#define GPIO_MCUN1INT2EN_MCUN1GPIO70_Msk  (0x40UL)                  /*!< MCUN1GPIO70 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO69_Pos  (5UL)                     /*!< MCUN1GPIO69 (Bit 5)                                   */
#define GPIO_MCUN1INT2EN_MCUN1GPIO69_Msk  (0x20UL)                  /*!< MCUN1GPIO69 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO68_Pos  (4UL)                     /*!< MCUN1GPIO68 (Bit 4)                                   */
#define GPIO_MCUN1INT2EN_MCUN1GPIO68_Msk  (0x10UL)                  /*!< MCUN1GPIO68 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO67_Pos  (3UL)                     /*!< MCUN1GPIO67 (Bit 3)                                   */
#define GPIO_MCUN1INT2EN_MCUN1GPIO67_Msk  (0x8UL)                   /*!< MCUN1GPIO67 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO66_Pos  (2UL)                     /*!< MCUN1GPIO66 (Bit 2)                                   */
#define GPIO_MCUN1INT2EN_MCUN1GPIO66_Msk  (0x4UL)                   /*!< MCUN1GPIO66 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO65_Pos  (1UL)                     /*!< MCUN1GPIO65 (Bit 1)                                   */
#define GPIO_MCUN1INT2EN_MCUN1GPIO65_Msk  (0x2UL)                   /*!< MCUN1GPIO65 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2EN_MCUN1GPIO64_Pos  (0UL)                     /*!< MCUN1GPIO64 (Bit 0)                                   */
#define GPIO_MCUN1INT2EN_MCUN1GPIO64_Msk  (0x1UL)                   /*!< MCUN1GPIO64 (Bitfield-Mask: 0x01)                     */
/* =====================================================  MCUN1INT2STAT  ===================================================== */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO95_Pos (31UL)                   /*!< MCUN1GPIO95 (Bit 31)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO95_Msk (0x80000000UL)           /*!< MCUN1GPIO95 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO94_Pos (30UL)                   /*!< MCUN1GPIO94 (Bit 30)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO94_Msk (0x40000000UL)           /*!< MCUN1GPIO94 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO93_Pos (29UL)                   /*!< MCUN1GPIO93 (Bit 29)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO93_Msk (0x20000000UL)           /*!< MCUN1GPIO93 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO92_Pos (28UL)                   /*!< MCUN1GPIO92 (Bit 28)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO92_Msk (0x10000000UL)           /*!< MCUN1GPIO92 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO91_Pos (27UL)                   /*!< MCUN1GPIO91 (Bit 27)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO91_Msk (0x8000000UL)            /*!< MCUN1GPIO91 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO90_Pos (26UL)                   /*!< MCUN1GPIO90 (Bit 26)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO90_Msk (0x4000000UL)            /*!< MCUN1GPIO90 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO89_Pos (25UL)                   /*!< MCUN1GPIO89 (Bit 25)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO89_Msk (0x2000000UL)            /*!< MCUN1GPIO89 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO88_Pos (24UL)                   /*!< MCUN1GPIO88 (Bit 24)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO88_Msk (0x1000000UL)            /*!< MCUN1GPIO88 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO87_Pos (23UL)                   /*!< MCUN1GPIO87 (Bit 23)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO87_Msk (0x800000UL)             /*!< MCUN1GPIO87 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO86_Pos (22UL)                   /*!< MCUN1GPIO86 (Bit 22)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO86_Msk (0x400000UL)             /*!< MCUN1GPIO86 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO85_Pos (21UL)                   /*!< MCUN1GPIO85 (Bit 21)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO85_Msk (0x200000UL)             /*!< MCUN1GPIO85 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO84_Pos (20UL)                   /*!< MCUN1GPIO84 (Bit 20)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO84_Msk (0x100000UL)             /*!< MCUN1GPIO84 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO83_Pos (19UL)                   /*!< MCUN1GPIO83 (Bit 19)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO83_Msk (0x80000UL)              /*!< MCUN1GPIO83 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO82_Pos (18UL)                   /*!< MCUN1GPIO82 (Bit 18)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO82_Msk (0x40000UL)              /*!< MCUN1GPIO82 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO81_Pos (17UL)                   /*!< MCUN1GPIO81 (Bit 17)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO81_Msk (0x20000UL)              /*!< MCUN1GPIO81 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO80_Pos (16UL)                   /*!< MCUN1GPIO80 (Bit 16)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO80_Msk (0x10000UL)              /*!< MCUN1GPIO80 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO79_Pos (15UL)                   /*!< MCUN1GPIO79 (Bit 15)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO79_Msk (0x8000UL)               /*!< MCUN1GPIO79 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO78_Pos (14UL)                   /*!< MCUN1GPIO78 (Bit 14)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO78_Msk (0x4000UL)               /*!< MCUN1GPIO78 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO77_Pos (13UL)                   /*!< MCUN1GPIO77 (Bit 13)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO77_Msk (0x2000UL)               /*!< MCUN1GPIO77 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO76_Pos (12UL)                   /*!< MCUN1GPIO76 (Bit 12)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO76_Msk (0x1000UL)               /*!< MCUN1GPIO76 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO75_Pos (11UL)                   /*!< MCUN1GPIO75 (Bit 11)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO75_Msk (0x800UL)                /*!< MCUN1GPIO75 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO74_Pos (10UL)                   /*!< MCUN1GPIO74 (Bit 10)                                  */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO74_Msk (0x400UL)                /*!< MCUN1GPIO74 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO73_Pos (9UL)                    /*!< MCUN1GPIO73 (Bit 9)                                   */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO73_Msk (0x200UL)                /*!< MCUN1GPIO73 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO72_Pos (8UL)                    /*!< MCUN1GPIO72 (Bit 8)                                   */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO72_Msk (0x100UL)                /*!< MCUN1GPIO72 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO71_Pos (7UL)                    /*!< MCUN1GPIO71 (Bit 7)                                   */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO71_Msk (0x80UL)                 /*!< MCUN1GPIO71 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO70_Pos (6UL)                    /*!< MCUN1GPIO70 (Bit 6)                                   */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO70_Msk (0x40UL)                 /*!< MCUN1GPIO70 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO69_Pos (5UL)                    /*!< MCUN1GPIO69 (Bit 5)                                   */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO69_Msk (0x20UL)                 /*!< MCUN1GPIO69 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO68_Pos (4UL)                    /*!< MCUN1GPIO68 (Bit 4)                                   */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO68_Msk (0x10UL)                 /*!< MCUN1GPIO68 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO67_Pos (3UL)                    /*!< MCUN1GPIO67 (Bit 3)                                   */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO67_Msk (0x8UL)                  /*!< MCUN1GPIO67 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO66_Pos (2UL)                    /*!< MCUN1GPIO66 (Bit 2)                                   */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO66_Msk (0x4UL)                  /*!< MCUN1GPIO66 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO65_Pos (1UL)                    /*!< MCUN1GPIO65 (Bit 1)                                   */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO65_Msk (0x2UL)                  /*!< MCUN1GPIO65 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO64_Pos (0UL)                    /*!< MCUN1GPIO64 (Bit 0)                                   */
#define GPIO_MCUN1INT2STAT_MCUN1GPIO64_Msk (0x1UL)                  /*!< MCUN1GPIO64 (Bitfield-Mask: 0x01)                     */
/* =====================================================  MCUN1INT2CLR  ====================================================== */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO95_Pos (31UL)                    /*!< MCUN1GPIO95 (Bit 31)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO95_Msk (0x80000000UL)            /*!< MCUN1GPIO95 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO94_Pos (30UL)                    /*!< MCUN1GPIO94 (Bit 30)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO94_Msk (0x40000000UL)            /*!< MCUN1GPIO94 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO93_Pos (29UL)                    /*!< MCUN1GPIO93 (Bit 29)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO93_Msk (0x20000000UL)            /*!< MCUN1GPIO93 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO92_Pos (28UL)                    /*!< MCUN1GPIO92 (Bit 28)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO92_Msk (0x10000000UL)            /*!< MCUN1GPIO92 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO91_Pos (27UL)                    /*!< MCUN1GPIO91 (Bit 27)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO91_Msk (0x8000000UL)             /*!< MCUN1GPIO91 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO90_Pos (26UL)                    /*!< MCUN1GPIO90 (Bit 26)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO90_Msk (0x4000000UL)             /*!< MCUN1GPIO90 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO89_Pos (25UL)                    /*!< MCUN1GPIO89 (Bit 25)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO89_Msk (0x2000000UL)             /*!< MCUN1GPIO89 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO88_Pos (24UL)                    /*!< MCUN1GPIO88 (Bit 24)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO88_Msk (0x1000000UL)             /*!< MCUN1GPIO88 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO87_Pos (23UL)                    /*!< MCUN1GPIO87 (Bit 23)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO87_Msk (0x800000UL)              /*!< MCUN1GPIO87 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO86_Pos (22UL)                    /*!< MCUN1GPIO86 (Bit 22)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO86_Msk (0x400000UL)              /*!< MCUN1GPIO86 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO85_Pos (21UL)                    /*!< MCUN1GPIO85 (Bit 21)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO85_Msk (0x200000UL)              /*!< MCUN1GPIO85 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO84_Pos (20UL)                    /*!< MCUN1GPIO84 (Bit 20)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO84_Msk (0x100000UL)              /*!< MCUN1GPIO84 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO83_Pos (19UL)                    /*!< MCUN1GPIO83 (Bit 19)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO83_Msk (0x80000UL)               /*!< MCUN1GPIO83 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO82_Pos (18UL)                    /*!< MCUN1GPIO82 (Bit 18)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO82_Msk (0x40000UL)               /*!< MCUN1GPIO82 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO81_Pos (17UL)                    /*!< MCUN1GPIO81 (Bit 17)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO81_Msk (0x20000UL)               /*!< MCUN1GPIO81 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO80_Pos (16UL)                    /*!< MCUN1GPIO80 (Bit 16)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO80_Msk (0x10000UL)               /*!< MCUN1GPIO80 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO79_Pos (15UL)                    /*!< MCUN1GPIO79 (Bit 15)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO79_Msk (0x8000UL)                /*!< MCUN1GPIO79 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO78_Pos (14UL)                    /*!< MCUN1GPIO78 (Bit 14)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO78_Msk (0x4000UL)                /*!< MCUN1GPIO78 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO77_Pos (13UL)                    /*!< MCUN1GPIO77 (Bit 13)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO77_Msk (0x2000UL)                /*!< MCUN1GPIO77 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO76_Pos (12UL)                    /*!< MCUN1GPIO76 (Bit 12)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO76_Msk (0x1000UL)                /*!< MCUN1GPIO76 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO75_Pos (11UL)                    /*!< MCUN1GPIO75 (Bit 11)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO75_Msk (0x800UL)                 /*!< MCUN1GPIO75 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO74_Pos (10UL)                    /*!< MCUN1GPIO74 (Bit 10)                                  */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO74_Msk (0x400UL)                 /*!< MCUN1GPIO74 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO73_Pos (9UL)                     /*!< MCUN1GPIO73 (Bit 9)                                   */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO73_Msk (0x200UL)                 /*!< MCUN1GPIO73 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO72_Pos (8UL)                     /*!< MCUN1GPIO72 (Bit 8)                                   */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO72_Msk (0x100UL)                 /*!< MCUN1GPIO72 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO71_Pos (7UL)                     /*!< MCUN1GPIO71 (Bit 7)                                   */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO71_Msk (0x80UL)                  /*!< MCUN1GPIO71 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO70_Pos (6UL)                     /*!< MCUN1GPIO70 (Bit 6)                                   */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO70_Msk (0x40UL)                  /*!< MCUN1GPIO70 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO69_Pos (5UL)                     /*!< MCUN1GPIO69 (Bit 5)                                   */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO69_Msk (0x20UL)                  /*!< MCUN1GPIO69 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO68_Pos (4UL)                     /*!< MCUN1GPIO68 (Bit 4)                                   */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO68_Msk (0x10UL)                  /*!< MCUN1GPIO68 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO67_Pos (3UL)                     /*!< MCUN1GPIO67 (Bit 3)                                   */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO67_Msk (0x8UL)                   /*!< MCUN1GPIO67 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO66_Pos (2UL)                     /*!< MCUN1GPIO66 (Bit 2)                                   */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO66_Msk (0x4UL)                   /*!< MCUN1GPIO66 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO65_Pos (1UL)                     /*!< MCUN1GPIO65 (Bit 1)                                   */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO65_Msk (0x2UL)                   /*!< MCUN1GPIO65 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO64_Pos (0UL)                     /*!< MCUN1GPIO64 (Bit 0)                                   */
#define GPIO_MCUN1INT2CLR_MCUN1GPIO64_Msk (0x1UL)                   /*!< MCUN1GPIO64 (Bitfield-Mask: 0x01)                     */
/* =====================================================  MCUN1INT2SET  ====================================================== */
#define GPIO_MCUN1INT2SET_MCUN1GPIO95_Pos (31UL)                    /*!< MCUN1GPIO95 (Bit 31)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO95_Msk (0x80000000UL)            /*!< MCUN1GPIO95 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO94_Pos (30UL)                    /*!< MCUN1GPIO94 (Bit 30)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO94_Msk (0x40000000UL)            /*!< MCUN1GPIO94 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO93_Pos (29UL)                    /*!< MCUN1GPIO93 (Bit 29)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO93_Msk (0x20000000UL)            /*!< MCUN1GPIO93 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO92_Pos (28UL)                    /*!< MCUN1GPIO92 (Bit 28)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO92_Msk (0x10000000UL)            /*!< MCUN1GPIO92 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO91_Pos (27UL)                    /*!< MCUN1GPIO91 (Bit 27)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO91_Msk (0x8000000UL)             /*!< MCUN1GPIO91 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO90_Pos (26UL)                    /*!< MCUN1GPIO90 (Bit 26)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO90_Msk (0x4000000UL)             /*!< MCUN1GPIO90 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO89_Pos (25UL)                    /*!< MCUN1GPIO89 (Bit 25)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO89_Msk (0x2000000UL)             /*!< MCUN1GPIO89 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO88_Pos (24UL)                    /*!< MCUN1GPIO88 (Bit 24)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO88_Msk (0x1000000UL)             /*!< MCUN1GPIO88 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO87_Pos (23UL)                    /*!< MCUN1GPIO87 (Bit 23)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO87_Msk (0x800000UL)              /*!< MCUN1GPIO87 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO86_Pos (22UL)                    /*!< MCUN1GPIO86 (Bit 22)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO86_Msk (0x400000UL)              /*!< MCUN1GPIO86 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO85_Pos (21UL)                    /*!< MCUN1GPIO85 (Bit 21)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO85_Msk (0x200000UL)              /*!< MCUN1GPIO85 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO84_Pos (20UL)                    /*!< MCUN1GPIO84 (Bit 20)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO84_Msk (0x100000UL)              /*!< MCUN1GPIO84 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO83_Pos (19UL)                    /*!< MCUN1GPIO83 (Bit 19)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO83_Msk (0x80000UL)               /*!< MCUN1GPIO83 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO82_Pos (18UL)                    /*!< MCUN1GPIO82 (Bit 18)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO82_Msk (0x40000UL)               /*!< MCUN1GPIO82 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO81_Pos (17UL)                    /*!< MCUN1GPIO81 (Bit 17)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO81_Msk (0x20000UL)               /*!< MCUN1GPIO81 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO80_Pos (16UL)                    /*!< MCUN1GPIO80 (Bit 16)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO80_Msk (0x10000UL)               /*!< MCUN1GPIO80 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO79_Pos (15UL)                    /*!< MCUN1GPIO79 (Bit 15)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO79_Msk (0x8000UL)                /*!< MCUN1GPIO79 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO78_Pos (14UL)                    /*!< MCUN1GPIO78 (Bit 14)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO78_Msk (0x4000UL)                /*!< MCUN1GPIO78 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO77_Pos (13UL)                    /*!< MCUN1GPIO77 (Bit 13)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO77_Msk (0x2000UL)                /*!< MCUN1GPIO77 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO76_Pos (12UL)                    /*!< MCUN1GPIO76 (Bit 12)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO76_Msk (0x1000UL)                /*!< MCUN1GPIO76 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO75_Pos (11UL)                    /*!< MCUN1GPIO75 (Bit 11)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO75_Msk (0x800UL)                 /*!< MCUN1GPIO75 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO74_Pos (10UL)                    /*!< MCUN1GPIO74 (Bit 10)                                  */
#define GPIO_MCUN1INT2SET_MCUN1GPIO74_Msk (0x400UL)                 /*!< MCUN1GPIO74 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO73_Pos (9UL)                     /*!< MCUN1GPIO73 (Bit 9)                                   */
#define GPIO_MCUN1INT2SET_MCUN1GPIO73_Msk (0x200UL)                 /*!< MCUN1GPIO73 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO72_Pos (8UL)                     /*!< MCUN1GPIO72 (Bit 8)                                   */
#define GPIO_MCUN1INT2SET_MCUN1GPIO72_Msk (0x100UL)                 /*!< MCUN1GPIO72 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO71_Pos (7UL)                     /*!< MCUN1GPIO71 (Bit 7)                                   */
#define GPIO_MCUN1INT2SET_MCUN1GPIO71_Msk (0x80UL)                  /*!< MCUN1GPIO71 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO70_Pos (6UL)                     /*!< MCUN1GPIO70 (Bit 6)                                   */
#define GPIO_MCUN1INT2SET_MCUN1GPIO70_Msk (0x40UL)                  /*!< MCUN1GPIO70 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO69_Pos (5UL)                     /*!< MCUN1GPIO69 (Bit 5)                                   */
#define GPIO_MCUN1INT2SET_MCUN1GPIO69_Msk (0x20UL)                  /*!< MCUN1GPIO69 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO68_Pos (4UL)                     /*!< MCUN1GPIO68 (Bit 4)                                   */
#define GPIO_MCUN1INT2SET_MCUN1GPIO68_Msk (0x10UL)                  /*!< MCUN1GPIO68 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO67_Pos (3UL)                     /*!< MCUN1GPIO67 (Bit 3)                                   */
#define GPIO_MCUN1INT2SET_MCUN1GPIO67_Msk (0x8UL)                   /*!< MCUN1GPIO67 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO66_Pos (2UL)                     /*!< MCUN1GPIO66 (Bit 2)                                   */
#define GPIO_MCUN1INT2SET_MCUN1GPIO66_Msk (0x4UL)                   /*!< MCUN1GPIO66 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO65_Pos (1UL)                     /*!< MCUN1GPIO65 (Bit 1)                                   */
#define GPIO_MCUN1INT2SET_MCUN1GPIO65_Msk (0x2UL)                   /*!< MCUN1GPIO65 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT2SET_MCUN1GPIO64_Pos (0UL)                     /*!< MCUN1GPIO64 (Bit 0)                                   */
#define GPIO_MCUN1INT2SET_MCUN1GPIO64_Msk (0x1UL)                   /*!< MCUN1GPIO64 (Bitfield-Mask: 0x01)                     */
/* ======================================================  MCUN1INT3EN  ====================================================== */
#define GPIO_MCUN1INT3EN_MCUN1GPIO127_Pos (31UL)                    /*!< MCUN1GPIO127 (Bit 31)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO127_Msk (0x80000000UL)            /*!< MCUN1GPIO127 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO126_Pos (30UL)                    /*!< MCUN1GPIO126 (Bit 30)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO126_Msk (0x40000000UL)            /*!< MCUN1GPIO126 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO125_Pos (29UL)                    /*!< MCUN1GPIO125 (Bit 29)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO125_Msk (0x20000000UL)            /*!< MCUN1GPIO125 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO124_Pos (28UL)                    /*!< MCUN1GPIO124 (Bit 28)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO124_Msk (0x10000000UL)            /*!< MCUN1GPIO124 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO123_Pos (27UL)                    /*!< MCUN1GPIO123 (Bit 27)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO123_Msk (0x8000000UL)             /*!< MCUN1GPIO123 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO122_Pos (26UL)                    /*!< MCUN1GPIO122 (Bit 26)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO122_Msk (0x4000000UL)             /*!< MCUN1GPIO122 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO121_Pos (25UL)                    /*!< MCUN1GPIO121 (Bit 25)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO121_Msk (0x2000000UL)             /*!< MCUN1GPIO121 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO120_Pos (24UL)                    /*!< MCUN1GPIO120 (Bit 24)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO120_Msk (0x1000000UL)             /*!< MCUN1GPIO120 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO119_Pos (23UL)                    /*!< MCUN1GPIO119 (Bit 23)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO119_Msk (0x800000UL)              /*!< MCUN1GPIO119 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO118_Pos (22UL)                    /*!< MCUN1GPIO118 (Bit 22)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO118_Msk (0x400000UL)              /*!< MCUN1GPIO118 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO117_Pos (21UL)                    /*!< MCUN1GPIO117 (Bit 21)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO117_Msk (0x200000UL)              /*!< MCUN1GPIO117 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO116_Pos (20UL)                    /*!< MCUN1GPIO116 (Bit 20)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO116_Msk (0x100000UL)              /*!< MCUN1GPIO116 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO115_Pos (19UL)                    /*!< MCUN1GPIO115 (Bit 19)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO115_Msk (0x80000UL)               /*!< MCUN1GPIO115 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO114_Pos (18UL)                    /*!< MCUN1GPIO114 (Bit 18)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO114_Msk (0x40000UL)               /*!< MCUN1GPIO114 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO113_Pos (17UL)                    /*!< MCUN1GPIO113 (Bit 17)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO113_Msk (0x20000UL)               /*!< MCUN1GPIO113 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO112_Pos (16UL)                    /*!< MCUN1GPIO112 (Bit 16)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO112_Msk (0x10000UL)               /*!< MCUN1GPIO112 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO111_Pos (15UL)                    /*!< MCUN1GPIO111 (Bit 15)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO111_Msk (0x8000UL)                /*!< MCUN1GPIO111 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO110_Pos (14UL)                    /*!< MCUN1GPIO110 (Bit 14)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO110_Msk (0x4000UL)                /*!< MCUN1GPIO110 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO109_Pos (13UL)                    /*!< MCUN1GPIO109 (Bit 13)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO109_Msk (0x2000UL)                /*!< MCUN1GPIO109 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO108_Pos (12UL)                    /*!< MCUN1GPIO108 (Bit 12)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO108_Msk (0x1000UL)                /*!< MCUN1GPIO108 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO107_Pos (11UL)                    /*!< MCUN1GPIO107 (Bit 11)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO107_Msk (0x800UL)                 /*!< MCUN1GPIO107 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO106_Pos (10UL)                    /*!< MCUN1GPIO106 (Bit 10)                                 */
#define GPIO_MCUN1INT3EN_MCUN1GPIO106_Msk (0x400UL)                 /*!< MCUN1GPIO106 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO105_Pos (9UL)                     /*!< MCUN1GPIO105 (Bit 9)                                  */
#define GPIO_MCUN1INT3EN_MCUN1GPIO105_Msk (0x200UL)                 /*!< MCUN1GPIO105 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO104_Pos (8UL)                     /*!< MCUN1GPIO104 (Bit 8)                                  */
#define GPIO_MCUN1INT3EN_MCUN1GPIO104_Msk (0x100UL)                 /*!< MCUN1GPIO104 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO103_Pos (7UL)                     /*!< MCUN1GPIO103 (Bit 7)                                  */
#define GPIO_MCUN1INT3EN_MCUN1GPIO103_Msk (0x80UL)                  /*!< MCUN1GPIO103 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO102_Pos (6UL)                     /*!< MCUN1GPIO102 (Bit 6)                                  */
#define GPIO_MCUN1INT3EN_MCUN1GPIO102_Msk (0x40UL)                  /*!< MCUN1GPIO102 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO101_Pos (5UL)                     /*!< MCUN1GPIO101 (Bit 5)                                  */
#define GPIO_MCUN1INT3EN_MCUN1GPIO101_Msk (0x20UL)                  /*!< MCUN1GPIO101 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO100_Pos (4UL)                     /*!< MCUN1GPIO100 (Bit 4)                                  */
#define GPIO_MCUN1INT3EN_MCUN1GPIO100_Msk (0x10UL)                  /*!< MCUN1GPIO100 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3EN_MCUN1GPIO99_Pos  (3UL)                     /*!< MCUN1GPIO99 (Bit 3)                                   */
#define GPIO_MCUN1INT3EN_MCUN1GPIO99_Msk  (0x8UL)                   /*!< MCUN1GPIO99 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT3EN_MCUN1GPIO98_Pos  (2UL)                     /*!< MCUN1GPIO98 (Bit 2)                                   */
#define GPIO_MCUN1INT3EN_MCUN1GPIO98_Msk  (0x4UL)                   /*!< MCUN1GPIO98 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT3EN_MCUN1GPIO97_Pos  (1UL)                     /*!< MCUN1GPIO97 (Bit 1)                                   */
#define GPIO_MCUN1INT3EN_MCUN1GPIO97_Msk  (0x2UL)                   /*!< MCUN1GPIO97 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT3EN_MCUN1GPIO96_Pos  (0UL)                     /*!< MCUN1GPIO96 (Bit 0)                                   */
#define GPIO_MCUN1INT3EN_MCUN1GPIO96_Msk  (0x1UL)                   /*!< MCUN1GPIO96 (Bitfield-Mask: 0x01)                     */
/* =====================================================  MCUN1INT3STAT  ===================================================== */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO127_Pos (31UL)                  /*!< MCUN1GPIO127 (Bit 31)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO127_Msk (0x80000000UL)          /*!< MCUN1GPIO127 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO126_Pos (30UL)                  /*!< MCUN1GPIO126 (Bit 30)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO126_Msk (0x40000000UL)          /*!< MCUN1GPIO126 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO125_Pos (29UL)                  /*!< MCUN1GPIO125 (Bit 29)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO125_Msk (0x20000000UL)          /*!< MCUN1GPIO125 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO124_Pos (28UL)                  /*!< MCUN1GPIO124 (Bit 28)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO124_Msk (0x10000000UL)          /*!< MCUN1GPIO124 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO123_Pos (27UL)                  /*!< MCUN1GPIO123 (Bit 27)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO123_Msk (0x8000000UL)           /*!< MCUN1GPIO123 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO122_Pos (26UL)                  /*!< MCUN1GPIO122 (Bit 26)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO122_Msk (0x4000000UL)           /*!< MCUN1GPIO122 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO121_Pos (25UL)                  /*!< MCUN1GPIO121 (Bit 25)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO121_Msk (0x2000000UL)           /*!< MCUN1GPIO121 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO120_Pos (24UL)                  /*!< MCUN1GPIO120 (Bit 24)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO120_Msk (0x1000000UL)           /*!< MCUN1GPIO120 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO119_Pos (23UL)                  /*!< MCUN1GPIO119 (Bit 23)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO119_Msk (0x800000UL)            /*!< MCUN1GPIO119 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO118_Pos (22UL)                  /*!< MCUN1GPIO118 (Bit 22)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO118_Msk (0x400000UL)            /*!< MCUN1GPIO118 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO117_Pos (21UL)                  /*!< MCUN1GPIO117 (Bit 21)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO117_Msk (0x200000UL)            /*!< MCUN1GPIO117 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO116_Pos (20UL)                  /*!< MCUN1GPIO116 (Bit 20)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO116_Msk (0x100000UL)            /*!< MCUN1GPIO116 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO115_Pos (19UL)                  /*!< MCUN1GPIO115 (Bit 19)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO115_Msk (0x80000UL)             /*!< MCUN1GPIO115 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO114_Pos (18UL)                  /*!< MCUN1GPIO114 (Bit 18)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO114_Msk (0x40000UL)             /*!< MCUN1GPIO114 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO113_Pos (17UL)                  /*!< MCUN1GPIO113 (Bit 17)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO113_Msk (0x20000UL)             /*!< MCUN1GPIO113 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO112_Pos (16UL)                  /*!< MCUN1GPIO112 (Bit 16)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO112_Msk (0x10000UL)             /*!< MCUN1GPIO112 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO111_Pos (15UL)                  /*!< MCUN1GPIO111 (Bit 15)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO111_Msk (0x8000UL)              /*!< MCUN1GPIO111 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO110_Pos (14UL)                  /*!< MCUN1GPIO110 (Bit 14)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO110_Msk (0x4000UL)              /*!< MCUN1GPIO110 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO109_Pos (13UL)                  /*!< MCUN1GPIO109 (Bit 13)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO109_Msk (0x2000UL)              /*!< MCUN1GPIO109 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO108_Pos (12UL)                  /*!< MCUN1GPIO108 (Bit 12)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO108_Msk (0x1000UL)              /*!< MCUN1GPIO108 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO107_Pos (11UL)                  /*!< MCUN1GPIO107 (Bit 11)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO107_Msk (0x800UL)               /*!< MCUN1GPIO107 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO106_Pos (10UL)                  /*!< MCUN1GPIO106 (Bit 10)                                 */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO106_Msk (0x400UL)               /*!< MCUN1GPIO106 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO105_Pos (9UL)                   /*!< MCUN1GPIO105 (Bit 9)                                  */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO105_Msk (0x200UL)               /*!< MCUN1GPIO105 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO104_Pos (8UL)                   /*!< MCUN1GPIO104 (Bit 8)                                  */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO104_Msk (0x100UL)               /*!< MCUN1GPIO104 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO103_Pos (7UL)                   /*!< MCUN1GPIO103 (Bit 7)                                  */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO103_Msk (0x80UL)                /*!< MCUN1GPIO103 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO102_Pos (6UL)                   /*!< MCUN1GPIO102 (Bit 6)                                  */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO102_Msk (0x40UL)                /*!< MCUN1GPIO102 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO101_Pos (5UL)                   /*!< MCUN1GPIO101 (Bit 5)                                  */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO101_Msk (0x20UL)                /*!< MCUN1GPIO101 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO100_Pos (4UL)                   /*!< MCUN1GPIO100 (Bit 4)                                  */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO100_Msk (0x10UL)                /*!< MCUN1GPIO100 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO99_Pos (3UL)                    /*!< MCUN1GPIO99 (Bit 3)                                   */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO99_Msk (0x8UL)                  /*!< MCUN1GPIO99 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO98_Pos (2UL)                    /*!< MCUN1GPIO98 (Bit 2)                                   */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO98_Msk (0x4UL)                  /*!< MCUN1GPIO98 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO97_Pos (1UL)                    /*!< MCUN1GPIO97 (Bit 1)                                   */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO97_Msk (0x2UL)                  /*!< MCUN1GPIO97 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO96_Pos (0UL)                    /*!< MCUN1GPIO96 (Bit 0)                                   */
#define GPIO_MCUN1INT3STAT_MCUN1GPIO96_Msk (0x1UL)                  /*!< MCUN1GPIO96 (Bitfield-Mask: 0x01)                     */
/* =====================================================  MCUN1INT3CLR  ====================================================== */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO127_Pos (31UL)                   /*!< MCUN1GPIO127 (Bit 31)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO127_Msk (0x80000000UL)           /*!< MCUN1GPIO127 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO126_Pos (30UL)                   /*!< MCUN1GPIO126 (Bit 30)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO126_Msk (0x40000000UL)           /*!< MCUN1GPIO126 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO125_Pos (29UL)                   /*!< MCUN1GPIO125 (Bit 29)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO125_Msk (0x20000000UL)           /*!< MCUN1GPIO125 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO124_Pos (28UL)                   /*!< MCUN1GPIO124 (Bit 28)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO124_Msk (0x10000000UL)           /*!< MCUN1GPIO124 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO123_Pos (27UL)                   /*!< MCUN1GPIO123 (Bit 27)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO123_Msk (0x8000000UL)            /*!< MCUN1GPIO123 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO122_Pos (26UL)                   /*!< MCUN1GPIO122 (Bit 26)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO122_Msk (0x4000000UL)            /*!< MCUN1GPIO122 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO121_Pos (25UL)                   /*!< MCUN1GPIO121 (Bit 25)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO121_Msk (0x2000000UL)            /*!< MCUN1GPIO121 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO120_Pos (24UL)                   /*!< MCUN1GPIO120 (Bit 24)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO120_Msk (0x1000000UL)            /*!< MCUN1GPIO120 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO119_Pos (23UL)                   /*!< MCUN1GPIO119 (Bit 23)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO119_Msk (0x800000UL)             /*!< MCUN1GPIO119 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO118_Pos (22UL)                   /*!< MCUN1GPIO118 (Bit 22)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO118_Msk (0x400000UL)             /*!< MCUN1GPIO118 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO117_Pos (21UL)                   /*!< MCUN1GPIO117 (Bit 21)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO117_Msk (0x200000UL)             /*!< MCUN1GPIO117 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO116_Pos (20UL)                   /*!< MCUN1GPIO116 (Bit 20)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO116_Msk (0x100000UL)             /*!< MCUN1GPIO116 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO115_Pos (19UL)                   /*!< MCUN1GPIO115 (Bit 19)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO115_Msk (0x80000UL)              /*!< MCUN1GPIO115 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO114_Pos (18UL)                   /*!< MCUN1GPIO114 (Bit 18)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO114_Msk (0x40000UL)              /*!< MCUN1GPIO114 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO113_Pos (17UL)                   /*!< MCUN1GPIO113 (Bit 17)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO113_Msk (0x20000UL)              /*!< MCUN1GPIO113 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO112_Pos (16UL)                   /*!< MCUN1GPIO112 (Bit 16)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO112_Msk (0x10000UL)              /*!< MCUN1GPIO112 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO111_Pos (15UL)                   /*!< MCUN1GPIO111 (Bit 15)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO111_Msk (0x8000UL)               /*!< MCUN1GPIO111 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO110_Pos (14UL)                   /*!< MCUN1GPIO110 (Bit 14)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO110_Msk (0x4000UL)               /*!< MCUN1GPIO110 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO109_Pos (13UL)                   /*!< MCUN1GPIO109 (Bit 13)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO109_Msk (0x2000UL)               /*!< MCUN1GPIO109 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO108_Pos (12UL)                   /*!< MCUN1GPIO108 (Bit 12)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO108_Msk (0x1000UL)               /*!< MCUN1GPIO108 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO107_Pos (11UL)                   /*!< MCUN1GPIO107 (Bit 11)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO107_Msk (0x800UL)                /*!< MCUN1GPIO107 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO106_Pos (10UL)                   /*!< MCUN1GPIO106 (Bit 10)                                 */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO106_Msk (0x400UL)                /*!< MCUN1GPIO106 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO105_Pos (9UL)                    /*!< MCUN1GPIO105 (Bit 9)                                  */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO105_Msk (0x200UL)                /*!< MCUN1GPIO105 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO104_Pos (8UL)                    /*!< MCUN1GPIO104 (Bit 8)                                  */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO104_Msk (0x100UL)                /*!< MCUN1GPIO104 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO103_Pos (7UL)                    /*!< MCUN1GPIO103 (Bit 7)                                  */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO103_Msk (0x80UL)                 /*!< MCUN1GPIO103 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO102_Pos (6UL)                    /*!< MCUN1GPIO102 (Bit 6)                                  */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO102_Msk (0x40UL)                 /*!< MCUN1GPIO102 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO101_Pos (5UL)                    /*!< MCUN1GPIO101 (Bit 5)                                  */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO101_Msk (0x20UL)                 /*!< MCUN1GPIO101 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO100_Pos (4UL)                    /*!< MCUN1GPIO100 (Bit 4)                                  */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO100_Msk (0x10UL)                 /*!< MCUN1GPIO100 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO99_Pos (3UL)                     /*!< MCUN1GPIO99 (Bit 3)                                   */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO99_Msk (0x8UL)                   /*!< MCUN1GPIO99 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO98_Pos (2UL)                     /*!< MCUN1GPIO98 (Bit 2)                                   */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO98_Msk (0x4UL)                   /*!< MCUN1GPIO98 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO97_Pos (1UL)                     /*!< MCUN1GPIO97 (Bit 1)                                   */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO97_Msk (0x2UL)                   /*!< MCUN1GPIO97 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO96_Pos (0UL)                     /*!< MCUN1GPIO96 (Bit 0)                                   */
#define GPIO_MCUN1INT3CLR_MCUN1GPIO96_Msk (0x1UL)                   /*!< MCUN1GPIO96 (Bitfield-Mask: 0x01)                     */
/* =====================================================  MCUN1INT3SET  ====================================================== */
#define GPIO_MCUN1INT3SET_MCUN1GPIO127_Pos (31UL)                   /*!< MCUN1GPIO127 (Bit 31)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO127_Msk (0x80000000UL)           /*!< MCUN1GPIO127 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO126_Pos (30UL)                   /*!< MCUN1GPIO126 (Bit 30)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO126_Msk (0x40000000UL)           /*!< MCUN1GPIO126 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO125_Pos (29UL)                   /*!< MCUN1GPIO125 (Bit 29)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO125_Msk (0x20000000UL)           /*!< MCUN1GPIO125 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO124_Pos (28UL)                   /*!< MCUN1GPIO124 (Bit 28)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO124_Msk (0x10000000UL)           /*!< MCUN1GPIO124 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO123_Pos (27UL)                   /*!< MCUN1GPIO123 (Bit 27)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO123_Msk (0x8000000UL)            /*!< MCUN1GPIO123 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO122_Pos (26UL)                   /*!< MCUN1GPIO122 (Bit 26)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO122_Msk (0x4000000UL)            /*!< MCUN1GPIO122 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO121_Pos (25UL)                   /*!< MCUN1GPIO121 (Bit 25)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO121_Msk (0x2000000UL)            /*!< MCUN1GPIO121 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO120_Pos (24UL)                   /*!< MCUN1GPIO120 (Bit 24)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO120_Msk (0x1000000UL)            /*!< MCUN1GPIO120 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO119_Pos (23UL)                   /*!< MCUN1GPIO119 (Bit 23)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO119_Msk (0x800000UL)             /*!< MCUN1GPIO119 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO118_Pos (22UL)                   /*!< MCUN1GPIO118 (Bit 22)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO118_Msk (0x400000UL)             /*!< MCUN1GPIO118 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO117_Pos (21UL)                   /*!< MCUN1GPIO117 (Bit 21)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO117_Msk (0x200000UL)             /*!< MCUN1GPIO117 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO116_Pos (20UL)                   /*!< MCUN1GPIO116 (Bit 20)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO116_Msk (0x100000UL)             /*!< MCUN1GPIO116 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO115_Pos (19UL)                   /*!< MCUN1GPIO115 (Bit 19)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO115_Msk (0x80000UL)              /*!< MCUN1GPIO115 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO114_Pos (18UL)                   /*!< MCUN1GPIO114 (Bit 18)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO114_Msk (0x40000UL)              /*!< MCUN1GPIO114 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO113_Pos (17UL)                   /*!< MCUN1GPIO113 (Bit 17)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO113_Msk (0x20000UL)              /*!< MCUN1GPIO113 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO112_Pos (16UL)                   /*!< MCUN1GPIO112 (Bit 16)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO112_Msk (0x10000UL)              /*!< MCUN1GPIO112 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO111_Pos (15UL)                   /*!< MCUN1GPIO111 (Bit 15)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO111_Msk (0x8000UL)               /*!< MCUN1GPIO111 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO110_Pos (14UL)                   /*!< MCUN1GPIO110 (Bit 14)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO110_Msk (0x4000UL)               /*!< MCUN1GPIO110 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO109_Pos (13UL)                   /*!< MCUN1GPIO109 (Bit 13)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO109_Msk (0x2000UL)               /*!< MCUN1GPIO109 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO108_Pos (12UL)                   /*!< MCUN1GPIO108 (Bit 12)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO108_Msk (0x1000UL)               /*!< MCUN1GPIO108 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO107_Pos (11UL)                   /*!< MCUN1GPIO107 (Bit 11)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO107_Msk (0x800UL)                /*!< MCUN1GPIO107 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO106_Pos (10UL)                   /*!< MCUN1GPIO106 (Bit 10)                                 */
#define GPIO_MCUN1INT3SET_MCUN1GPIO106_Msk (0x400UL)                /*!< MCUN1GPIO106 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO105_Pos (9UL)                    /*!< MCUN1GPIO105 (Bit 9)                                  */
#define GPIO_MCUN1INT3SET_MCUN1GPIO105_Msk (0x200UL)                /*!< MCUN1GPIO105 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO104_Pos (8UL)                    /*!< MCUN1GPIO104 (Bit 8)                                  */
#define GPIO_MCUN1INT3SET_MCUN1GPIO104_Msk (0x100UL)                /*!< MCUN1GPIO104 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO103_Pos (7UL)                    /*!< MCUN1GPIO103 (Bit 7)                                  */
#define GPIO_MCUN1INT3SET_MCUN1GPIO103_Msk (0x80UL)                 /*!< MCUN1GPIO103 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO102_Pos (6UL)                    /*!< MCUN1GPIO102 (Bit 6)                                  */
#define GPIO_MCUN1INT3SET_MCUN1GPIO102_Msk (0x40UL)                 /*!< MCUN1GPIO102 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO101_Pos (5UL)                    /*!< MCUN1GPIO101 (Bit 5)                                  */
#define GPIO_MCUN1INT3SET_MCUN1GPIO101_Msk (0x20UL)                 /*!< MCUN1GPIO101 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO100_Pos (4UL)                    /*!< MCUN1GPIO100 (Bit 4)                                  */
#define GPIO_MCUN1INT3SET_MCUN1GPIO100_Msk (0x10UL)                 /*!< MCUN1GPIO100 (Bitfield-Mask: 0x01)                    */
#define GPIO_MCUN1INT3SET_MCUN1GPIO99_Pos (3UL)                     /*!< MCUN1GPIO99 (Bit 3)                                   */
#define GPIO_MCUN1INT3SET_MCUN1GPIO99_Msk (0x8UL)                   /*!< MCUN1GPIO99 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT3SET_MCUN1GPIO98_Pos (2UL)                     /*!< MCUN1GPIO98 (Bit 2)                                   */
#define GPIO_MCUN1INT3SET_MCUN1GPIO98_Msk (0x4UL)                   /*!< MCUN1GPIO98 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT3SET_MCUN1GPIO97_Pos (1UL)                     /*!< MCUN1GPIO97 (Bit 1)                                   */
#define GPIO_MCUN1INT3SET_MCUN1GPIO97_Msk (0x2UL)                   /*!< MCUN1GPIO97 (Bitfield-Mask: 0x01)                     */
#define GPIO_MCUN1INT3SET_MCUN1GPIO96_Pos (0UL)                     /*!< MCUN1GPIO96 (Bit 0)                                   */
#define GPIO_MCUN1INT3SET_MCUN1GPIO96_Msk (0x1UL)                   /*!< MCUN1GPIO96 (Bitfield-Mask: 0x01)                     */
/* =====================================================  DSP0N0INT0EN  ====================================================== */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO31_Pos (31UL)                   /*!< DSP0N0GPIO31 (Bit 31)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO31_Msk (0x80000000UL)           /*!< DSP0N0GPIO31 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO30_Pos (30UL)                   /*!< DSP0N0GPIO30 (Bit 30)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO30_Msk (0x40000000UL)           /*!< DSP0N0GPIO30 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO29_Pos (29UL)                   /*!< DSP0N0GPIO29 (Bit 29)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO29_Msk (0x20000000UL)           /*!< DSP0N0GPIO29 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO28_Pos (28UL)                   /*!< DSP0N0GPIO28 (Bit 28)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO28_Msk (0x10000000UL)           /*!< DSP0N0GPIO28 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO27_Pos (27UL)                   /*!< DSP0N0GPIO27 (Bit 27)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO27_Msk (0x8000000UL)            /*!< DSP0N0GPIO27 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO26_Pos (26UL)                   /*!< DSP0N0GPIO26 (Bit 26)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO26_Msk (0x4000000UL)            /*!< DSP0N0GPIO26 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO25_Pos (25UL)                   /*!< DSP0N0GPIO25 (Bit 25)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO25_Msk (0x2000000UL)            /*!< DSP0N0GPIO25 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO24_Pos (24UL)                   /*!< DSP0N0GPIO24 (Bit 24)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO24_Msk (0x1000000UL)            /*!< DSP0N0GPIO24 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO23_Pos (23UL)                   /*!< DSP0N0GPIO23 (Bit 23)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO23_Msk (0x800000UL)             /*!< DSP0N0GPIO23 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO22_Pos (22UL)                   /*!< DSP0N0GPIO22 (Bit 22)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO22_Msk (0x400000UL)             /*!< DSP0N0GPIO22 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO21_Pos (21UL)                   /*!< DSP0N0GPIO21 (Bit 21)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO21_Msk (0x200000UL)             /*!< DSP0N0GPIO21 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO20_Pos (20UL)                   /*!< DSP0N0GPIO20 (Bit 20)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO20_Msk (0x100000UL)             /*!< DSP0N0GPIO20 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO19_Pos (19UL)                   /*!< DSP0N0GPIO19 (Bit 19)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO19_Msk (0x80000UL)              /*!< DSP0N0GPIO19 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO18_Pos (18UL)                   /*!< DSP0N0GPIO18 (Bit 18)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO18_Msk (0x40000UL)              /*!< DSP0N0GPIO18 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO17_Pos (17UL)                   /*!< DSP0N0GPIO17 (Bit 17)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO17_Msk (0x20000UL)              /*!< DSP0N0GPIO17 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO16_Pos (16UL)                   /*!< DSP0N0GPIO16 (Bit 16)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO16_Msk (0x10000UL)              /*!< DSP0N0GPIO16 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO15_Pos (15UL)                   /*!< DSP0N0GPIO15 (Bit 15)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO15_Msk (0x8000UL)               /*!< DSP0N0GPIO15 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO14_Pos (14UL)                   /*!< DSP0N0GPIO14 (Bit 14)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO14_Msk (0x4000UL)               /*!< DSP0N0GPIO14 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO13_Pos (13UL)                   /*!< DSP0N0GPIO13 (Bit 13)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO13_Msk (0x2000UL)               /*!< DSP0N0GPIO13 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO12_Pos (12UL)                   /*!< DSP0N0GPIO12 (Bit 12)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO12_Msk (0x1000UL)               /*!< DSP0N0GPIO12 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO11_Pos (11UL)                   /*!< DSP0N0GPIO11 (Bit 11)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO11_Msk (0x800UL)                /*!< DSP0N0GPIO11 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO10_Pos (10UL)                   /*!< DSP0N0GPIO10 (Bit 10)                                 */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO10_Msk (0x400UL)                /*!< DSP0N0GPIO10 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO9_Pos (9UL)                     /*!< DSP0N0GPIO9 (Bit 9)                                   */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO9_Msk (0x200UL)                 /*!< DSP0N0GPIO9 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO8_Pos (8UL)                     /*!< DSP0N0GPIO8 (Bit 8)                                   */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO8_Msk (0x100UL)                 /*!< DSP0N0GPIO8 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO7_Pos (7UL)                     /*!< DSP0N0GPIO7 (Bit 7)                                   */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO7_Msk (0x80UL)                  /*!< DSP0N0GPIO7 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO6_Pos (6UL)                     /*!< DSP0N0GPIO6 (Bit 6)                                   */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO6_Msk (0x40UL)                  /*!< DSP0N0GPIO6 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO5_Pos (5UL)                     /*!< DSP0N0GPIO5 (Bit 5)                                   */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO5_Msk (0x20UL)                  /*!< DSP0N0GPIO5 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO4_Pos (4UL)                     /*!< DSP0N0GPIO4 (Bit 4)                                   */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO4_Msk (0x10UL)                  /*!< DSP0N0GPIO4 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO3_Pos (3UL)                     /*!< DSP0N0GPIO3 (Bit 3)                                   */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO3_Msk (0x8UL)                   /*!< DSP0N0GPIO3 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO2_Pos (2UL)                     /*!< DSP0N0GPIO2 (Bit 2)                                   */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO2_Msk (0x4UL)                   /*!< DSP0N0GPIO2 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO1_Pos (1UL)                     /*!< DSP0N0GPIO1 (Bit 1)                                   */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO1_Msk (0x2UL)                   /*!< DSP0N0GPIO1 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO0_Pos (0UL)                     /*!< DSP0N0GPIO0 (Bit 0)                                   */
#define GPIO_DSP0N0INT0EN_DSP0N0GPIO0_Msk (0x1UL)                   /*!< DSP0N0GPIO0 (Bitfield-Mask: 0x01)                     */
/* ====================================================  DSP0N0INT0STAT  ===================================================== */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO31_Pos (31UL)                 /*!< DSP0N0GPIO31 (Bit 31)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO31_Msk (0x80000000UL)         /*!< DSP0N0GPIO31 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO30_Pos (30UL)                 /*!< DSP0N0GPIO30 (Bit 30)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO30_Msk (0x40000000UL)         /*!< DSP0N0GPIO30 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO29_Pos (29UL)                 /*!< DSP0N0GPIO29 (Bit 29)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO29_Msk (0x20000000UL)         /*!< DSP0N0GPIO29 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO28_Pos (28UL)                 /*!< DSP0N0GPIO28 (Bit 28)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO28_Msk (0x10000000UL)         /*!< DSP0N0GPIO28 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO27_Pos (27UL)                 /*!< DSP0N0GPIO27 (Bit 27)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO27_Msk (0x8000000UL)          /*!< DSP0N0GPIO27 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO26_Pos (26UL)                 /*!< DSP0N0GPIO26 (Bit 26)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO26_Msk (0x4000000UL)          /*!< DSP0N0GPIO26 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO25_Pos (25UL)                 /*!< DSP0N0GPIO25 (Bit 25)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO25_Msk (0x2000000UL)          /*!< DSP0N0GPIO25 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO24_Pos (24UL)                 /*!< DSP0N0GPIO24 (Bit 24)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO24_Msk (0x1000000UL)          /*!< DSP0N0GPIO24 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO23_Pos (23UL)                 /*!< DSP0N0GPIO23 (Bit 23)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO23_Msk (0x800000UL)           /*!< DSP0N0GPIO23 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO22_Pos (22UL)                 /*!< DSP0N0GPIO22 (Bit 22)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO22_Msk (0x400000UL)           /*!< DSP0N0GPIO22 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO21_Pos (21UL)                 /*!< DSP0N0GPIO21 (Bit 21)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO21_Msk (0x200000UL)           /*!< DSP0N0GPIO21 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO20_Pos (20UL)                 /*!< DSP0N0GPIO20 (Bit 20)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO20_Msk (0x100000UL)           /*!< DSP0N0GPIO20 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO19_Pos (19UL)                 /*!< DSP0N0GPIO19 (Bit 19)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO19_Msk (0x80000UL)            /*!< DSP0N0GPIO19 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO18_Pos (18UL)                 /*!< DSP0N0GPIO18 (Bit 18)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO18_Msk (0x40000UL)            /*!< DSP0N0GPIO18 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO17_Pos (17UL)                 /*!< DSP0N0GPIO17 (Bit 17)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO17_Msk (0x20000UL)            /*!< DSP0N0GPIO17 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO16_Pos (16UL)                 /*!< DSP0N0GPIO16 (Bit 16)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO16_Msk (0x10000UL)            /*!< DSP0N0GPIO16 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO15_Pos (15UL)                 /*!< DSP0N0GPIO15 (Bit 15)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO15_Msk (0x8000UL)             /*!< DSP0N0GPIO15 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO14_Pos (14UL)                 /*!< DSP0N0GPIO14 (Bit 14)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO14_Msk (0x4000UL)             /*!< DSP0N0GPIO14 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO13_Pos (13UL)                 /*!< DSP0N0GPIO13 (Bit 13)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO13_Msk (0x2000UL)             /*!< DSP0N0GPIO13 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO12_Pos (12UL)                 /*!< DSP0N0GPIO12 (Bit 12)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO12_Msk (0x1000UL)             /*!< DSP0N0GPIO12 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO11_Pos (11UL)                 /*!< DSP0N0GPIO11 (Bit 11)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO11_Msk (0x800UL)              /*!< DSP0N0GPIO11 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO10_Pos (10UL)                 /*!< DSP0N0GPIO10 (Bit 10)                                 */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO10_Msk (0x400UL)              /*!< DSP0N0GPIO10 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO9_Pos (9UL)                   /*!< DSP0N0GPIO9 (Bit 9)                                   */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO9_Msk (0x200UL)               /*!< DSP0N0GPIO9 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO8_Pos (8UL)                   /*!< DSP0N0GPIO8 (Bit 8)                                   */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO8_Msk (0x100UL)               /*!< DSP0N0GPIO8 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO7_Pos (7UL)                   /*!< DSP0N0GPIO7 (Bit 7)                                   */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO7_Msk (0x80UL)                /*!< DSP0N0GPIO7 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO6_Pos (6UL)                   /*!< DSP0N0GPIO6 (Bit 6)                                   */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO6_Msk (0x40UL)                /*!< DSP0N0GPIO6 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO5_Pos (5UL)                   /*!< DSP0N0GPIO5 (Bit 5)                                   */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO5_Msk (0x20UL)                /*!< DSP0N0GPIO5 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO4_Pos (4UL)                   /*!< DSP0N0GPIO4 (Bit 4)                                   */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO4_Msk (0x10UL)                /*!< DSP0N0GPIO4 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO3_Pos (3UL)                   /*!< DSP0N0GPIO3 (Bit 3)                                   */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO3_Msk (0x8UL)                 /*!< DSP0N0GPIO3 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO2_Pos (2UL)                   /*!< DSP0N0GPIO2 (Bit 2)                                   */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO2_Msk (0x4UL)                 /*!< DSP0N0GPIO2 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO1_Pos (1UL)                   /*!< DSP0N0GPIO1 (Bit 1)                                   */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO1_Msk (0x2UL)                 /*!< DSP0N0GPIO1 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO0_Pos (0UL)                   /*!< DSP0N0GPIO0 (Bit 0)                                   */
#define GPIO_DSP0N0INT0STAT_DSP0N0GPIO0_Msk (0x1UL)                 /*!< DSP0N0GPIO0 (Bitfield-Mask: 0x01)                     */
/* =====================================================  DSP0N0INT0CLR  ===================================================== */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO31_Pos (31UL)                  /*!< DSP0N0GPIO31 (Bit 31)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO31_Msk (0x80000000UL)          /*!< DSP0N0GPIO31 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO30_Pos (30UL)                  /*!< DSP0N0GPIO30 (Bit 30)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO30_Msk (0x40000000UL)          /*!< DSP0N0GPIO30 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO29_Pos (29UL)                  /*!< DSP0N0GPIO29 (Bit 29)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO29_Msk (0x20000000UL)          /*!< DSP0N0GPIO29 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO28_Pos (28UL)                  /*!< DSP0N0GPIO28 (Bit 28)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO28_Msk (0x10000000UL)          /*!< DSP0N0GPIO28 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO27_Pos (27UL)                  /*!< DSP0N0GPIO27 (Bit 27)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO27_Msk (0x8000000UL)           /*!< DSP0N0GPIO27 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO26_Pos (26UL)                  /*!< DSP0N0GPIO26 (Bit 26)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO26_Msk (0x4000000UL)           /*!< DSP0N0GPIO26 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO25_Pos (25UL)                  /*!< DSP0N0GPIO25 (Bit 25)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO25_Msk (0x2000000UL)           /*!< DSP0N0GPIO25 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO24_Pos (24UL)                  /*!< DSP0N0GPIO24 (Bit 24)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO24_Msk (0x1000000UL)           /*!< DSP0N0GPIO24 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO23_Pos (23UL)                  /*!< DSP0N0GPIO23 (Bit 23)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO23_Msk (0x800000UL)            /*!< DSP0N0GPIO23 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO22_Pos (22UL)                  /*!< DSP0N0GPIO22 (Bit 22)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO22_Msk (0x400000UL)            /*!< DSP0N0GPIO22 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO21_Pos (21UL)                  /*!< DSP0N0GPIO21 (Bit 21)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO21_Msk (0x200000UL)            /*!< DSP0N0GPIO21 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO20_Pos (20UL)                  /*!< DSP0N0GPIO20 (Bit 20)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO20_Msk (0x100000UL)            /*!< DSP0N0GPIO20 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO19_Pos (19UL)                  /*!< DSP0N0GPIO19 (Bit 19)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO19_Msk (0x80000UL)             /*!< DSP0N0GPIO19 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO18_Pos (18UL)                  /*!< DSP0N0GPIO18 (Bit 18)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO18_Msk (0x40000UL)             /*!< DSP0N0GPIO18 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO17_Pos (17UL)                  /*!< DSP0N0GPIO17 (Bit 17)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO17_Msk (0x20000UL)             /*!< DSP0N0GPIO17 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO16_Pos (16UL)                  /*!< DSP0N0GPIO16 (Bit 16)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO16_Msk (0x10000UL)             /*!< DSP0N0GPIO16 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO15_Pos (15UL)                  /*!< DSP0N0GPIO15 (Bit 15)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO15_Msk (0x8000UL)              /*!< DSP0N0GPIO15 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO14_Pos (14UL)                  /*!< DSP0N0GPIO14 (Bit 14)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO14_Msk (0x4000UL)              /*!< DSP0N0GPIO14 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO13_Pos (13UL)                  /*!< DSP0N0GPIO13 (Bit 13)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO13_Msk (0x2000UL)              /*!< DSP0N0GPIO13 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO12_Pos (12UL)                  /*!< DSP0N0GPIO12 (Bit 12)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO12_Msk (0x1000UL)              /*!< DSP0N0GPIO12 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO11_Pos (11UL)                  /*!< DSP0N0GPIO11 (Bit 11)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO11_Msk (0x800UL)               /*!< DSP0N0GPIO11 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO10_Pos (10UL)                  /*!< DSP0N0GPIO10 (Bit 10)                                 */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO10_Msk (0x400UL)               /*!< DSP0N0GPIO10 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO9_Pos (9UL)                    /*!< DSP0N0GPIO9 (Bit 9)                                   */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO9_Msk (0x200UL)                /*!< DSP0N0GPIO9 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO8_Pos (8UL)                    /*!< DSP0N0GPIO8 (Bit 8)                                   */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO8_Msk (0x100UL)                /*!< DSP0N0GPIO8 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO7_Pos (7UL)                    /*!< DSP0N0GPIO7 (Bit 7)                                   */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO7_Msk (0x80UL)                 /*!< DSP0N0GPIO7 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO6_Pos (6UL)                    /*!< DSP0N0GPIO6 (Bit 6)                                   */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO6_Msk (0x40UL)                 /*!< DSP0N0GPIO6 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO5_Pos (5UL)                    /*!< DSP0N0GPIO5 (Bit 5)                                   */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO5_Msk (0x20UL)                 /*!< DSP0N0GPIO5 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO4_Pos (4UL)                    /*!< DSP0N0GPIO4 (Bit 4)                                   */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO4_Msk (0x10UL)                 /*!< DSP0N0GPIO4 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO3_Pos (3UL)                    /*!< DSP0N0GPIO3 (Bit 3)                                   */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO3_Msk (0x8UL)                  /*!< DSP0N0GPIO3 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO2_Pos (2UL)                    /*!< DSP0N0GPIO2 (Bit 2)                                   */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO2_Msk (0x4UL)                  /*!< DSP0N0GPIO2 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO1_Pos (1UL)                    /*!< DSP0N0GPIO1 (Bit 1)                                   */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO1_Msk (0x2UL)                  /*!< DSP0N0GPIO1 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO0_Pos (0UL)                    /*!< DSP0N0GPIO0 (Bit 0)                                   */
#define GPIO_DSP0N0INT0CLR_DSP0N0GPIO0_Msk (0x1UL)                  /*!< DSP0N0GPIO0 (Bitfield-Mask: 0x01)                     */
/* =====================================================  DSP0N0INT0SET  ===================================================== */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO31_Pos (31UL)                  /*!< DSP0N0GPIO31 (Bit 31)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO31_Msk (0x80000000UL)          /*!< DSP0N0GPIO31 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO30_Pos (30UL)                  /*!< DSP0N0GPIO30 (Bit 30)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO30_Msk (0x40000000UL)          /*!< DSP0N0GPIO30 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO29_Pos (29UL)                  /*!< DSP0N0GPIO29 (Bit 29)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO29_Msk (0x20000000UL)          /*!< DSP0N0GPIO29 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO28_Pos (28UL)                  /*!< DSP0N0GPIO28 (Bit 28)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO28_Msk (0x10000000UL)          /*!< DSP0N0GPIO28 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO27_Pos (27UL)                  /*!< DSP0N0GPIO27 (Bit 27)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO27_Msk (0x8000000UL)           /*!< DSP0N0GPIO27 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO26_Pos (26UL)                  /*!< DSP0N0GPIO26 (Bit 26)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO26_Msk (0x4000000UL)           /*!< DSP0N0GPIO26 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO25_Pos (25UL)                  /*!< DSP0N0GPIO25 (Bit 25)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO25_Msk (0x2000000UL)           /*!< DSP0N0GPIO25 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO24_Pos (24UL)                  /*!< DSP0N0GPIO24 (Bit 24)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO24_Msk (0x1000000UL)           /*!< DSP0N0GPIO24 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO23_Pos (23UL)                  /*!< DSP0N0GPIO23 (Bit 23)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO23_Msk (0x800000UL)            /*!< DSP0N0GPIO23 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO22_Pos (22UL)                  /*!< DSP0N0GPIO22 (Bit 22)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO22_Msk (0x400000UL)            /*!< DSP0N0GPIO22 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO21_Pos (21UL)                  /*!< DSP0N0GPIO21 (Bit 21)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO21_Msk (0x200000UL)            /*!< DSP0N0GPIO21 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO20_Pos (20UL)                  /*!< DSP0N0GPIO20 (Bit 20)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO20_Msk (0x100000UL)            /*!< DSP0N0GPIO20 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO19_Pos (19UL)                  /*!< DSP0N0GPIO19 (Bit 19)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO19_Msk (0x80000UL)             /*!< DSP0N0GPIO19 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO18_Pos (18UL)                  /*!< DSP0N0GPIO18 (Bit 18)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO18_Msk (0x40000UL)             /*!< DSP0N0GPIO18 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO17_Pos (17UL)                  /*!< DSP0N0GPIO17 (Bit 17)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO17_Msk (0x20000UL)             /*!< DSP0N0GPIO17 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO16_Pos (16UL)                  /*!< DSP0N0GPIO16 (Bit 16)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO16_Msk (0x10000UL)             /*!< DSP0N0GPIO16 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO15_Pos (15UL)                  /*!< DSP0N0GPIO15 (Bit 15)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO15_Msk (0x8000UL)              /*!< DSP0N0GPIO15 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO14_Pos (14UL)                  /*!< DSP0N0GPIO14 (Bit 14)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO14_Msk (0x4000UL)              /*!< DSP0N0GPIO14 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO13_Pos (13UL)                  /*!< DSP0N0GPIO13 (Bit 13)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO13_Msk (0x2000UL)              /*!< DSP0N0GPIO13 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO12_Pos (12UL)                  /*!< DSP0N0GPIO12 (Bit 12)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO12_Msk (0x1000UL)              /*!< DSP0N0GPIO12 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO11_Pos (11UL)                  /*!< DSP0N0GPIO11 (Bit 11)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO11_Msk (0x800UL)               /*!< DSP0N0GPIO11 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO10_Pos (10UL)                  /*!< DSP0N0GPIO10 (Bit 10)                                 */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO10_Msk (0x400UL)               /*!< DSP0N0GPIO10 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO9_Pos (9UL)                    /*!< DSP0N0GPIO9 (Bit 9)                                   */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO9_Msk (0x200UL)                /*!< DSP0N0GPIO9 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO8_Pos (8UL)                    /*!< DSP0N0GPIO8 (Bit 8)                                   */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO8_Msk (0x100UL)                /*!< DSP0N0GPIO8 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO7_Pos (7UL)                    /*!< DSP0N0GPIO7 (Bit 7)                                   */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO7_Msk (0x80UL)                 /*!< DSP0N0GPIO7 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO6_Pos (6UL)                    /*!< DSP0N0GPIO6 (Bit 6)                                   */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO6_Msk (0x40UL)                 /*!< DSP0N0GPIO6 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO5_Pos (5UL)                    /*!< DSP0N0GPIO5 (Bit 5)                                   */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO5_Msk (0x20UL)                 /*!< DSP0N0GPIO5 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO4_Pos (4UL)                    /*!< DSP0N0GPIO4 (Bit 4)                                   */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO4_Msk (0x10UL)                 /*!< DSP0N0GPIO4 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO3_Pos (3UL)                    /*!< DSP0N0GPIO3 (Bit 3)                                   */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO3_Msk (0x8UL)                  /*!< DSP0N0GPIO3 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO2_Pos (2UL)                    /*!< DSP0N0GPIO2 (Bit 2)                                   */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO2_Msk (0x4UL)                  /*!< DSP0N0GPIO2 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO1_Pos (1UL)                    /*!< DSP0N0GPIO1 (Bit 1)                                   */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO1_Msk (0x2UL)                  /*!< DSP0N0GPIO1 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO0_Pos (0UL)                    /*!< DSP0N0GPIO0 (Bit 0)                                   */
#define GPIO_DSP0N0INT0SET_DSP0N0GPIO0_Msk (0x1UL)                  /*!< DSP0N0GPIO0 (Bitfield-Mask: 0x01)                     */
/* =====================================================  DSP0N0INT1EN  ====================================================== */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO63_Pos (31UL)                   /*!< DSP0N0GPIO63 (Bit 31)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO63_Msk (0x80000000UL)           /*!< DSP0N0GPIO63 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO62_Pos (30UL)                   /*!< DSP0N0GPIO62 (Bit 30)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO62_Msk (0x40000000UL)           /*!< DSP0N0GPIO62 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO61_Pos (29UL)                   /*!< DSP0N0GPIO61 (Bit 29)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO61_Msk (0x20000000UL)           /*!< DSP0N0GPIO61 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO60_Pos (28UL)                   /*!< DSP0N0GPIO60 (Bit 28)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO60_Msk (0x10000000UL)           /*!< DSP0N0GPIO60 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO59_Pos (27UL)                   /*!< DSP0N0GPIO59 (Bit 27)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO59_Msk (0x8000000UL)            /*!< DSP0N0GPIO59 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO58_Pos (26UL)                   /*!< DSP0N0GPIO58 (Bit 26)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO58_Msk (0x4000000UL)            /*!< DSP0N0GPIO58 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO57_Pos (25UL)                   /*!< DSP0N0GPIO57 (Bit 25)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO57_Msk (0x2000000UL)            /*!< DSP0N0GPIO57 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO56_Pos (24UL)                   /*!< DSP0N0GPIO56 (Bit 24)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO56_Msk (0x1000000UL)            /*!< DSP0N0GPIO56 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO55_Pos (23UL)                   /*!< DSP0N0GPIO55 (Bit 23)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO55_Msk (0x800000UL)             /*!< DSP0N0GPIO55 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO54_Pos (22UL)                   /*!< DSP0N0GPIO54 (Bit 22)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO54_Msk (0x400000UL)             /*!< DSP0N0GPIO54 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO53_Pos (21UL)                   /*!< DSP0N0GPIO53 (Bit 21)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO53_Msk (0x200000UL)             /*!< DSP0N0GPIO53 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO52_Pos (20UL)                   /*!< DSP0N0GPIO52 (Bit 20)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO52_Msk (0x100000UL)             /*!< DSP0N0GPIO52 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO51_Pos (19UL)                   /*!< DSP0N0GPIO51 (Bit 19)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO51_Msk (0x80000UL)              /*!< DSP0N0GPIO51 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO50_Pos (18UL)                   /*!< DSP0N0GPIO50 (Bit 18)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO50_Msk (0x40000UL)              /*!< DSP0N0GPIO50 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO49_Pos (17UL)                   /*!< DSP0N0GPIO49 (Bit 17)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO49_Msk (0x20000UL)              /*!< DSP0N0GPIO49 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO48_Pos (16UL)                   /*!< DSP0N0GPIO48 (Bit 16)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO48_Msk (0x10000UL)              /*!< DSP0N0GPIO48 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO47_Pos (15UL)                   /*!< DSP0N0GPIO47 (Bit 15)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO47_Msk (0x8000UL)               /*!< DSP0N0GPIO47 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO46_Pos (14UL)                   /*!< DSP0N0GPIO46 (Bit 14)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO46_Msk (0x4000UL)               /*!< DSP0N0GPIO46 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO45_Pos (13UL)                   /*!< DSP0N0GPIO45 (Bit 13)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO45_Msk (0x2000UL)               /*!< DSP0N0GPIO45 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO44_Pos (12UL)                   /*!< DSP0N0GPIO44 (Bit 12)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO44_Msk (0x1000UL)               /*!< DSP0N0GPIO44 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO43_Pos (11UL)                   /*!< DSP0N0GPIO43 (Bit 11)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO43_Msk (0x800UL)                /*!< DSP0N0GPIO43 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO42_Pos (10UL)                   /*!< DSP0N0GPIO42 (Bit 10)                                 */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO42_Msk (0x400UL)                /*!< DSP0N0GPIO42 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO41_Pos (9UL)                    /*!< DSP0N0GPIO41 (Bit 9)                                  */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO41_Msk (0x200UL)                /*!< DSP0N0GPIO41 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO40_Pos (8UL)                    /*!< DSP0N0GPIO40 (Bit 8)                                  */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO40_Msk (0x100UL)                /*!< DSP0N0GPIO40 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO39_Pos (7UL)                    /*!< DSP0N0GPIO39 (Bit 7)                                  */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO39_Msk (0x80UL)                 /*!< DSP0N0GPIO39 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO38_Pos (6UL)                    /*!< DSP0N0GPIO38 (Bit 6)                                  */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO38_Msk (0x40UL)                 /*!< DSP0N0GPIO38 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO37_Pos (5UL)                    /*!< DSP0N0GPIO37 (Bit 5)                                  */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO37_Msk (0x20UL)                 /*!< DSP0N0GPIO37 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO36_Pos (4UL)                    /*!< DSP0N0GPIO36 (Bit 4)                                  */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO36_Msk (0x10UL)                 /*!< DSP0N0GPIO36 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO35_Pos (3UL)                    /*!< DSP0N0GPIO35 (Bit 3)                                  */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO35_Msk (0x8UL)                  /*!< DSP0N0GPIO35 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO34_Pos (2UL)                    /*!< DSP0N0GPIO34 (Bit 2)                                  */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO34_Msk (0x4UL)                  /*!< DSP0N0GPIO34 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO33_Pos (1UL)                    /*!< DSP0N0GPIO33 (Bit 1)                                  */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO33_Msk (0x2UL)                  /*!< DSP0N0GPIO33 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO32_Pos (0UL)                    /*!< DSP0N0GPIO32 (Bit 0)                                  */
#define GPIO_DSP0N0INT1EN_DSP0N0GPIO32_Msk (0x1UL)                  /*!< DSP0N0GPIO32 (Bitfield-Mask: 0x01)                    */
/* ====================================================  DSP0N0INT1STAT  ===================================================== */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO63_Pos (31UL)                 /*!< DSP0N0GPIO63 (Bit 31)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO63_Msk (0x80000000UL)         /*!< DSP0N0GPIO63 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO62_Pos (30UL)                 /*!< DSP0N0GPIO62 (Bit 30)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO62_Msk (0x40000000UL)         /*!< DSP0N0GPIO62 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO61_Pos (29UL)                 /*!< DSP0N0GPIO61 (Bit 29)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO61_Msk (0x20000000UL)         /*!< DSP0N0GPIO61 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO60_Pos (28UL)                 /*!< DSP0N0GPIO60 (Bit 28)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO60_Msk (0x10000000UL)         /*!< DSP0N0GPIO60 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO59_Pos (27UL)                 /*!< DSP0N0GPIO59 (Bit 27)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO59_Msk (0x8000000UL)          /*!< DSP0N0GPIO59 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO58_Pos (26UL)                 /*!< DSP0N0GPIO58 (Bit 26)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO58_Msk (0x4000000UL)          /*!< DSP0N0GPIO58 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO57_Pos (25UL)                 /*!< DSP0N0GPIO57 (Bit 25)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO57_Msk (0x2000000UL)          /*!< DSP0N0GPIO57 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO56_Pos (24UL)                 /*!< DSP0N0GPIO56 (Bit 24)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO56_Msk (0x1000000UL)          /*!< DSP0N0GPIO56 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO55_Pos (23UL)                 /*!< DSP0N0GPIO55 (Bit 23)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO55_Msk (0x800000UL)           /*!< DSP0N0GPIO55 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO54_Pos (22UL)                 /*!< DSP0N0GPIO54 (Bit 22)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO54_Msk (0x400000UL)           /*!< DSP0N0GPIO54 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO53_Pos (21UL)                 /*!< DSP0N0GPIO53 (Bit 21)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO53_Msk (0x200000UL)           /*!< DSP0N0GPIO53 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO52_Pos (20UL)                 /*!< DSP0N0GPIO52 (Bit 20)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO52_Msk (0x100000UL)           /*!< DSP0N0GPIO52 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO51_Pos (19UL)                 /*!< DSP0N0GPIO51 (Bit 19)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO51_Msk (0x80000UL)            /*!< DSP0N0GPIO51 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO50_Pos (18UL)                 /*!< DSP0N0GPIO50 (Bit 18)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO50_Msk (0x40000UL)            /*!< DSP0N0GPIO50 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO49_Pos (17UL)                 /*!< DSP0N0GPIO49 (Bit 17)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO49_Msk (0x20000UL)            /*!< DSP0N0GPIO49 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO48_Pos (16UL)                 /*!< DSP0N0GPIO48 (Bit 16)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO48_Msk (0x10000UL)            /*!< DSP0N0GPIO48 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO47_Pos (15UL)                 /*!< DSP0N0GPIO47 (Bit 15)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO47_Msk (0x8000UL)             /*!< DSP0N0GPIO47 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO46_Pos (14UL)                 /*!< DSP0N0GPIO46 (Bit 14)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO46_Msk (0x4000UL)             /*!< DSP0N0GPIO46 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO45_Pos (13UL)                 /*!< DSP0N0GPIO45 (Bit 13)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO45_Msk (0x2000UL)             /*!< DSP0N0GPIO45 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO44_Pos (12UL)                 /*!< DSP0N0GPIO44 (Bit 12)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO44_Msk (0x1000UL)             /*!< DSP0N0GPIO44 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO43_Pos (11UL)                 /*!< DSP0N0GPIO43 (Bit 11)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO43_Msk (0x800UL)              /*!< DSP0N0GPIO43 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO42_Pos (10UL)                 /*!< DSP0N0GPIO42 (Bit 10)                                 */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO42_Msk (0x400UL)              /*!< DSP0N0GPIO42 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO41_Pos (9UL)                  /*!< DSP0N0GPIO41 (Bit 9)                                  */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO41_Msk (0x200UL)              /*!< DSP0N0GPIO41 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO40_Pos (8UL)                  /*!< DSP0N0GPIO40 (Bit 8)                                  */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO40_Msk (0x100UL)              /*!< DSP0N0GPIO40 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO39_Pos (7UL)                  /*!< DSP0N0GPIO39 (Bit 7)                                  */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO39_Msk (0x80UL)               /*!< DSP0N0GPIO39 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO38_Pos (6UL)                  /*!< DSP0N0GPIO38 (Bit 6)                                  */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO38_Msk (0x40UL)               /*!< DSP0N0GPIO38 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO37_Pos (5UL)                  /*!< DSP0N0GPIO37 (Bit 5)                                  */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO37_Msk (0x20UL)               /*!< DSP0N0GPIO37 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO36_Pos (4UL)                  /*!< DSP0N0GPIO36 (Bit 4)                                  */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO36_Msk (0x10UL)               /*!< DSP0N0GPIO36 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO35_Pos (3UL)                  /*!< DSP0N0GPIO35 (Bit 3)                                  */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO35_Msk (0x8UL)                /*!< DSP0N0GPIO35 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO34_Pos (2UL)                  /*!< DSP0N0GPIO34 (Bit 2)                                  */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO34_Msk (0x4UL)                /*!< DSP0N0GPIO34 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO33_Pos (1UL)                  /*!< DSP0N0GPIO33 (Bit 1)                                  */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO33_Msk (0x2UL)                /*!< DSP0N0GPIO33 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO32_Pos (0UL)                  /*!< DSP0N0GPIO32 (Bit 0)                                  */
#define GPIO_DSP0N0INT1STAT_DSP0N0GPIO32_Msk (0x1UL)                /*!< DSP0N0GPIO32 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0N0INT1CLR  ===================================================== */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO63_Pos (31UL)                  /*!< DSP0N0GPIO63 (Bit 31)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO63_Msk (0x80000000UL)          /*!< DSP0N0GPIO63 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO62_Pos (30UL)                  /*!< DSP0N0GPIO62 (Bit 30)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO62_Msk (0x40000000UL)          /*!< DSP0N0GPIO62 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO61_Pos (29UL)                  /*!< DSP0N0GPIO61 (Bit 29)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO61_Msk (0x20000000UL)          /*!< DSP0N0GPIO61 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO60_Pos (28UL)                  /*!< DSP0N0GPIO60 (Bit 28)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO60_Msk (0x10000000UL)          /*!< DSP0N0GPIO60 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO59_Pos (27UL)                  /*!< DSP0N0GPIO59 (Bit 27)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO59_Msk (0x8000000UL)           /*!< DSP0N0GPIO59 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO58_Pos (26UL)                  /*!< DSP0N0GPIO58 (Bit 26)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO58_Msk (0x4000000UL)           /*!< DSP0N0GPIO58 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO57_Pos (25UL)                  /*!< DSP0N0GPIO57 (Bit 25)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO57_Msk (0x2000000UL)           /*!< DSP0N0GPIO57 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO56_Pos (24UL)                  /*!< DSP0N0GPIO56 (Bit 24)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO56_Msk (0x1000000UL)           /*!< DSP0N0GPIO56 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO55_Pos (23UL)                  /*!< DSP0N0GPIO55 (Bit 23)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO55_Msk (0x800000UL)            /*!< DSP0N0GPIO55 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO54_Pos (22UL)                  /*!< DSP0N0GPIO54 (Bit 22)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO54_Msk (0x400000UL)            /*!< DSP0N0GPIO54 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO53_Pos (21UL)                  /*!< DSP0N0GPIO53 (Bit 21)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO53_Msk (0x200000UL)            /*!< DSP0N0GPIO53 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO52_Pos (20UL)                  /*!< DSP0N0GPIO52 (Bit 20)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO52_Msk (0x100000UL)            /*!< DSP0N0GPIO52 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO51_Pos (19UL)                  /*!< DSP0N0GPIO51 (Bit 19)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO51_Msk (0x80000UL)             /*!< DSP0N0GPIO51 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO50_Pos (18UL)                  /*!< DSP0N0GPIO50 (Bit 18)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO50_Msk (0x40000UL)             /*!< DSP0N0GPIO50 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO49_Pos (17UL)                  /*!< DSP0N0GPIO49 (Bit 17)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO49_Msk (0x20000UL)             /*!< DSP0N0GPIO49 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO48_Pos (16UL)                  /*!< DSP0N0GPIO48 (Bit 16)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO48_Msk (0x10000UL)             /*!< DSP0N0GPIO48 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO47_Pos (15UL)                  /*!< DSP0N0GPIO47 (Bit 15)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO47_Msk (0x8000UL)              /*!< DSP0N0GPIO47 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO46_Pos (14UL)                  /*!< DSP0N0GPIO46 (Bit 14)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO46_Msk (0x4000UL)              /*!< DSP0N0GPIO46 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO45_Pos (13UL)                  /*!< DSP0N0GPIO45 (Bit 13)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO45_Msk (0x2000UL)              /*!< DSP0N0GPIO45 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO44_Pos (12UL)                  /*!< DSP0N0GPIO44 (Bit 12)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO44_Msk (0x1000UL)              /*!< DSP0N0GPIO44 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO43_Pos (11UL)                  /*!< DSP0N0GPIO43 (Bit 11)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO43_Msk (0x800UL)               /*!< DSP0N0GPIO43 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO42_Pos (10UL)                  /*!< DSP0N0GPIO42 (Bit 10)                                 */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO42_Msk (0x400UL)               /*!< DSP0N0GPIO42 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO41_Pos (9UL)                   /*!< DSP0N0GPIO41 (Bit 9)                                  */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO41_Msk (0x200UL)               /*!< DSP0N0GPIO41 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO40_Pos (8UL)                   /*!< DSP0N0GPIO40 (Bit 8)                                  */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO40_Msk (0x100UL)               /*!< DSP0N0GPIO40 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO39_Pos (7UL)                   /*!< DSP0N0GPIO39 (Bit 7)                                  */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO39_Msk (0x80UL)                /*!< DSP0N0GPIO39 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO38_Pos (6UL)                   /*!< DSP0N0GPIO38 (Bit 6)                                  */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO38_Msk (0x40UL)                /*!< DSP0N0GPIO38 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO37_Pos (5UL)                   /*!< DSP0N0GPIO37 (Bit 5)                                  */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO37_Msk (0x20UL)                /*!< DSP0N0GPIO37 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO36_Pos (4UL)                   /*!< DSP0N0GPIO36 (Bit 4)                                  */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO36_Msk (0x10UL)                /*!< DSP0N0GPIO36 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO35_Pos (3UL)                   /*!< DSP0N0GPIO35 (Bit 3)                                  */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO35_Msk (0x8UL)                 /*!< DSP0N0GPIO35 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO34_Pos (2UL)                   /*!< DSP0N0GPIO34 (Bit 2)                                  */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO34_Msk (0x4UL)                 /*!< DSP0N0GPIO34 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO33_Pos (1UL)                   /*!< DSP0N0GPIO33 (Bit 1)                                  */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO33_Msk (0x2UL)                 /*!< DSP0N0GPIO33 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO32_Pos (0UL)                   /*!< DSP0N0GPIO32 (Bit 0)                                  */
#define GPIO_DSP0N0INT1CLR_DSP0N0GPIO32_Msk (0x1UL)                 /*!< DSP0N0GPIO32 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0N0INT1SET  ===================================================== */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO63_Pos (31UL)                  /*!< DSP0N0GPIO63 (Bit 31)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO63_Msk (0x80000000UL)          /*!< DSP0N0GPIO63 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO62_Pos (30UL)                  /*!< DSP0N0GPIO62 (Bit 30)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO62_Msk (0x40000000UL)          /*!< DSP0N0GPIO62 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO61_Pos (29UL)                  /*!< DSP0N0GPIO61 (Bit 29)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO61_Msk (0x20000000UL)          /*!< DSP0N0GPIO61 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO60_Pos (28UL)                  /*!< DSP0N0GPIO60 (Bit 28)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO60_Msk (0x10000000UL)          /*!< DSP0N0GPIO60 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO59_Pos (27UL)                  /*!< DSP0N0GPIO59 (Bit 27)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO59_Msk (0x8000000UL)           /*!< DSP0N0GPIO59 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO58_Pos (26UL)                  /*!< DSP0N0GPIO58 (Bit 26)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO58_Msk (0x4000000UL)           /*!< DSP0N0GPIO58 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO57_Pos (25UL)                  /*!< DSP0N0GPIO57 (Bit 25)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO57_Msk (0x2000000UL)           /*!< DSP0N0GPIO57 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO56_Pos (24UL)                  /*!< DSP0N0GPIO56 (Bit 24)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO56_Msk (0x1000000UL)           /*!< DSP0N0GPIO56 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO55_Pos (23UL)                  /*!< DSP0N0GPIO55 (Bit 23)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO55_Msk (0x800000UL)            /*!< DSP0N0GPIO55 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO54_Pos (22UL)                  /*!< DSP0N0GPIO54 (Bit 22)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO54_Msk (0x400000UL)            /*!< DSP0N0GPIO54 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO53_Pos (21UL)                  /*!< DSP0N0GPIO53 (Bit 21)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO53_Msk (0x200000UL)            /*!< DSP0N0GPIO53 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO52_Pos (20UL)                  /*!< DSP0N0GPIO52 (Bit 20)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO52_Msk (0x100000UL)            /*!< DSP0N0GPIO52 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO51_Pos (19UL)                  /*!< DSP0N0GPIO51 (Bit 19)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO51_Msk (0x80000UL)             /*!< DSP0N0GPIO51 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO50_Pos (18UL)                  /*!< DSP0N0GPIO50 (Bit 18)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO50_Msk (0x40000UL)             /*!< DSP0N0GPIO50 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO49_Pos (17UL)                  /*!< DSP0N0GPIO49 (Bit 17)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO49_Msk (0x20000UL)             /*!< DSP0N0GPIO49 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO48_Pos (16UL)                  /*!< DSP0N0GPIO48 (Bit 16)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO48_Msk (0x10000UL)             /*!< DSP0N0GPIO48 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO47_Pos (15UL)                  /*!< DSP0N0GPIO47 (Bit 15)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO47_Msk (0x8000UL)              /*!< DSP0N0GPIO47 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO46_Pos (14UL)                  /*!< DSP0N0GPIO46 (Bit 14)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO46_Msk (0x4000UL)              /*!< DSP0N0GPIO46 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO45_Pos (13UL)                  /*!< DSP0N0GPIO45 (Bit 13)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO45_Msk (0x2000UL)              /*!< DSP0N0GPIO45 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO44_Pos (12UL)                  /*!< DSP0N0GPIO44 (Bit 12)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO44_Msk (0x1000UL)              /*!< DSP0N0GPIO44 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO43_Pos (11UL)                  /*!< DSP0N0GPIO43 (Bit 11)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO43_Msk (0x800UL)               /*!< DSP0N0GPIO43 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO42_Pos (10UL)                  /*!< DSP0N0GPIO42 (Bit 10)                                 */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO42_Msk (0x400UL)               /*!< DSP0N0GPIO42 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO41_Pos (9UL)                   /*!< DSP0N0GPIO41 (Bit 9)                                  */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO41_Msk (0x200UL)               /*!< DSP0N0GPIO41 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO40_Pos (8UL)                   /*!< DSP0N0GPIO40 (Bit 8)                                  */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO40_Msk (0x100UL)               /*!< DSP0N0GPIO40 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO39_Pos (7UL)                   /*!< DSP0N0GPIO39 (Bit 7)                                  */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO39_Msk (0x80UL)                /*!< DSP0N0GPIO39 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO38_Pos (6UL)                   /*!< DSP0N0GPIO38 (Bit 6)                                  */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO38_Msk (0x40UL)                /*!< DSP0N0GPIO38 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO37_Pos (5UL)                   /*!< DSP0N0GPIO37 (Bit 5)                                  */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO37_Msk (0x20UL)                /*!< DSP0N0GPIO37 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO36_Pos (4UL)                   /*!< DSP0N0GPIO36 (Bit 4)                                  */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO36_Msk (0x10UL)                /*!< DSP0N0GPIO36 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO35_Pos (3UL)                   /*!< DSP0N0GPIO35 (Bit 3)                                  */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO35_Msk (0x8UL)                 /*!< DSP0N0GPIO35 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO34_Pos (2UL)                   /*!< DSP0N0GPIO34 (Bit 2)                                  */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO34_Msk (0x4UL)                 /*!< DSP0N0GPIO34 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO33_Pos (1UL)                   /*!< DSP0N0GPIO33 (Bit 1)                                  */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO33_Msk (0x2UL)                 /*!< DSP0N0GPIO33 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO32_Pos (0UL)                   /*!< DSP0N0GPIO32 (Bit 0)                                  */
#define GPIO_DSP0N0INT1SET_DSP0N0GPIO32_Msk (0x1UL)                 /*!< DSP0N0GPIO32 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0N0INT2EN  ====================================================== */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO95_Pos (31UL)                   /*!< DSP0N0GPIO95 (Bit 31)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO95_Msk (0x80000000UL)           /*!< DSP0N0GPIO95 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO94_Pos (30UL)                   /*!< DSP0N0GPIO94 (Bit 30)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO94_Msk (0x40000000UL)           /*!< DSP0N0GPIO94 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO93_Pos (29UL)                   /*!< DSP0N0GPIO93 (Bit 29)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO93_Msk (0x20000000UL)           /*!< DSP0N0GPIO93 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO92_Pos (28UL)                   /*!< DSP0N0GPIO92 (Bit 28)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO92_Msk (0x10000000UL)           /*!< DSP0N0GPIO92 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO91_Pos (27UL)                   /*!< DSP0N0GPIO91 (Bit 27)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO91_Msk (0x8000000UL)            /*!< DSP0N0GPIO91 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO90_Pos (26UL)                   /*!< DSP0N0GPIO90 (Bit 26)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO90_Msk (0x4000000UL)            /*!< DSP0N0GPIO90 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO89_Pos (25UL)                   /*!< DSP0N0GPIO89 (Bit 25)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO89_Msk (0x2000000UL)            /*!< DSP0N0GPIO89 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO88_Pos (24UL)                   /*!< DSP0N0GPIO88 (Bit 24)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO88_Msk (0x1000000UL)            /*!< DSP0N0GPIO88 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO87_Pos (23UL)                   /*!< DSP0N0GPIO87 (Bit 23)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO87_Msk (0x800000UL)             /*!< DSP0N0GPIO87 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO86_Pos (22UL)                   /*!< DSP0N0GPIO86 (Bit 22)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO86_Msk (0x400000UL)             /*!< DSP0N0GPIO86 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO85_Pos (21UL)                   /*!< DSP0N0GPIO85 (Bit 21)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO85_Msk (0x200000UL)             /*!< DSP0N0GPIO85 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO84_Pos (20UL)                   /*!< DSP0N0GPIO84 (Bit 20)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO84_Msk (0x100000UL)             /*!< DSP0N0GPIO84 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO83_Pos (19UL)                   /*!< DSP0N0GPIO83 (Bit 19)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO83_Msk (0x80000UL)              /*!< DSP0N0GPIO83 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO82_Pos (18UL)                   /*!< DSP0N0GPIO82 (Bit 18)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO82_Msk (0x40000UL)              /*!< DSP0N0GPIO82 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO81_Pos (17UL)                   /*!< DSP0N0GPIO81 (Bit 17)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO81_Msk (0x20000UL)              /*!< DSP0N0GPIO81 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO80_Pos (16UL)                   /*!< DSP0N0GPIO80 (Bit 16)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO80_Msk (0x10000UL)              /*!< DSP0N0GPIO80 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO79_Pos (15UL)                   /*!< DSP0N0GPIO79 (Bit 15)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO79_Msk (0x8000UL)               /*!< DSP0N0GPIO79 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO78_Pos (14UL)                   /*!< DSP0N0GPIO78 (Bit 14)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO78_Msk (0x4000UL)               /*!< DSP0N0GPIO78 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO77_Pos (13UL)                   /*!< DSP0N0GPIO77 (Bit 13)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO77_Msk (0x2000UL)               /*!< DSP0N0GPIO77 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO76_Pos (12UL)                   /*!< DSP0N0GPIO76 (Bit 12)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO76_Msk (0x1000UL)               /*!< DSP0N0GPIO76 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO75_Pos (11UL)                   /*!< DSP0N0GPIO75 (Bit 11)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO75_Msk (0x800UL)                /*!< DSP0N0GPIO75 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO74_Pos (10UL)                   /*!< DSP0N0GPIO74 (Bit 10)                                 */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO74_Msk (0x400UL)                /*!< DSP0N0GPIO74 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO73_Pos (9UL)                    /*!< DSP0N0GPIO73 (Bit 9)                                  */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO73_Msk (0x200UL)                /*!< DSP0N0GPIO73 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO72_Pos (8UL)                    /*!< DSP0N0GPIO72 (Bit 8)                                  */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO72_Msk (0x100UL)                /*!< DSP0N0GPIO72 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO71_Pos (7UL)                    /*!< DSP0N0GPIO71 (Bit 7)                                  */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO71_Msk (0x80UL)                 /*!< DSP0N0GPIO71 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO70_Pos (6UL)                    /*!< DSP0N0GPIO70 (Bit 6)                                  */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO70_Msk (0x40UL)                 /*!< DSP0N0GPIO70 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO69_Pos (5UL)                    /*!< DSP0N0GPIO69 (Bit 5)                                  */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO69_Msk (0x20UL)                 /*!< DSP0N0GPIO69 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO68_Pos (4UL)                    /*!< DSP0N0GPIO68 (Bit 4)                                  */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO68_Msk (0x10UL)                 /*!< DSP0N0GPIO68 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO67_Pos (3UL)                    /*!< DSP0N0GPIO67 (Bit 3)                                  */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO67_Msk (0x8UL)                  /*!< DSP0N0GPIO67 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO66_Pos (2UL)                    /*!< DSP0N0GPIO66 (Bit 2)                                  */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO66_Msk (0x4UL)                  /*!< DSP0N0GPIO66 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO65_Pos (1UL)                    /*!< DSP0N0GPIO65 (Bit 1)                                  */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO65_Msk (0x2UL)                  /*!< DSP0N0GPIO65 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO64_Pos (0UL)                    /*!< DSP0N0GPIO64 (Bit 0)                                  */
#define GPIO_DSP0N0INT2EN_DSP0N0GPIO64_Msk (0x1UL)                  /*!< DSP0N0GPIO64 (Bitfield-Mask: 0x01)                    */
/* ====================================================  DSP0N0INT2STAT  ===================================================== */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO95_Pos (31UL)                 /*!< DSP0N0GPIO95 (Bit 31)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO95_Msk (0x80000000UL)         /*!< DSP0N0GPIO95 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO94_Pos (30UL)                 /*!< DSP0N0GPIO94 (Bit 30)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO94_Msk (0x40000000UL)         /*!< DSP0N0GPIO94 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO93_Pos (29UL)                 /*!< DSP0N0GPIO93 (Bit 29)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO93_Msk (0x20000000UL)         /*!< DSP0N0GPIO93 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO92_Pos (28UL)                 /*!< DSP0N0GPIO92 (Bit 28)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO92_Msk (0x10000000UL)         /*!< DSP0N0GPIO92 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO91_Pos (27UL)                 /*!< DSP0N0GPIO91 (Bit 27)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO91_Msk (0x8000000UL)          /*!< DSP0N0GPIO91 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO90_Pos (26UL)                 /*!< DSP0N0GPIO90 (Bit 26)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO90_Msk (0x4000000UL)          /*!< DSP0N0GPIO90 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO89_Pos (25UL)                 /*!< DSP0N0GPIO89 (Bit 25)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO89_Msk (0x2000000UL)          /*!< DSP0N0GPIO89 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO88_Pos (24UL)                 /*!< DSP0N0GPIO88 (Bit 24)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO88_Msk (0x1000000UL)          /*!< DSP0N0GPIO88 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO87_Pos (23UL)                 /*!< DSP0N0GPIO87 (Bit 23)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO87_Msk (0x800000UL)           /*!< DSP0N0GPIO87 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO86_Pos (22UL)                 /*!< DSP0N0GPIO86 (Bit 22)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO86_Msk (0x400000UL)           /*!< DSP0N0GPIO86 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO85_Pos (21UL)                 /*!< DSP0N0GPIO85 (Bit 21)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO85_Msk (0x200000UL)           /*!< DSP0N0GPIO85 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO84_Pos (20UL)                 /*!< DSP0N0GPIO84 (Bit 20)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO84_Msk (0x100000UL)           /*!< DSP0N0GPIO84 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO83_Pos (19UL)                 /*!< DSP0N0GPIO83 (Bit 19)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO83_Msk (0x80000UL)            /*!< DSP0N0GPIO83 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO82_Pos (18UL)                 /*!< DSP0N0GPIO82 (Bit 18)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO82_Msk (0x40000UL)            /*!< DSP0N0GPIO82 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO81_Pos (17UL)                 /*!< DSP0N0GPIO81 (Bit 17)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO81_Msk (0x20000UL)            /*!< DSP0N0GPIO81 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO80_Pos (16UL)                 /*!< DSP0N0GPIO80 (Bit 16)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO80_Msk (0x10000UL)            /*!< DSP0N0GPIO80 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO79_Pos (15UL)                 /*!< DSP0N0GPIO79 (Bit 15)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO79_Msk (0x8000UL)             /*!< DSP0N0GPIO79 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO78_Pos (14UL)                 /*!< DSP0N0GPIO78 (Bit 14)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO78_Msk (0x4000UL)             /*!< DSP0N0GPIO78 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO77_Pos (13UL)                 /*!< DSP0N0GPIO77 (Bit 13)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO77_Msk (0x2000UL)             /*!< DSP0N0GPIO77 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO76_Pos (12UL)                 /*!< DSP0N0GPIO76 (Bit 12)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO76_Msk (0x1000UL)             /*!< DSP0N0GPIO76 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO75_Pos (11UL)                 /*!< DSP0N0GPIO75 (Bit 11)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO75_Msk (0x800UL)              /*!< DSP0N0GPIO75 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO74_Pos (10UL)                 /*!< DSP0N0GPIO74 (Bit 10)                                 */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO74_Msk (0x400UL)              /*!< DSP0N0GPIO74 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO73_Pos (9UL)                  /*!< DSP0N0GPIO73 (Bit 9)                                  */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO73_Msk (0x200UL)              /*!< DSP0N0GPIO73 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO72_Pos (8UL)                  /*!< DSP0N0GPIO72 (Bit 8)                                  */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO72_Msk (0x100UL)              /*!< DSP0N0GPIO72 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO71_Pos (7UL)                  /*!< DSP0N0GPIO71 (Bit 7)                                  */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO71_Msk (0x80UL)               /*!< DSP0N0GPIO71 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO70_Pos (6UL)                  /*!< DSP0N0GPIO70 (Bit 6)                                  */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO70_Msk (0x40UL)               /*!< DSP0N0GPIO70 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO69_Pos (5UL)                  /*!< DSP0N0GPIO69 (Bit 5)                                  */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO69_Msk (0x20UL)               /*!< DSP0N0GPIO69 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO68_Pos (4UL)                  /*!< DSP0N0GPIO68 (Bit 4)                                  */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO68_Msk (0x10UL)               /*!< DSP0N0GPIO68 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO67_Pos (3UL)                  /*!< DSP0N0GPIO67 (Bit 3)                                  */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO67_Msk (0x8UL)                /*!< DSP0N0GPIO67 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO66_Pos (2UL)                  /*!< DSP0N0GPIO66 (Bit 2)                                  */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO66_Msk (0x4UL)                /*!< DSP0N0GPIO66 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO65_Pos (1UL)                  /*!< DSP0N0GPIO65 (Bit 1)                                  */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO65_Msk (0x2UL)                /*!< DSP0N0GPIO65 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO64_Pos (0UL)                  /*!< DSP0N0GPIO64 (Bit 0)                                  */
#define GPIO_DSP0N0INT2STAT_DSP0N0GPIO64_Msk (0x1UL)                /*!< DSP0N0GPIO64 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0N0INT2CLR  ===================================================== */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO95_Pos (31UL)                  /*!< DSP0N0GPIO95 (Bit 31)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO95_Msk (0x80000000UL)          /*!< DSP0N0GPIO95 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO94_Pos (30UL)                  /*!< DSP0N0GPIO94 (Bit 30)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO94_Msk (0x40000000UL)          /*!< DSP0N0GPIO94 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO93_Pos (29UL)                  /*!< DSP0N0GPIO93 (Bit 29)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO93_Msk (0x20000000UL)          /*!< DSP0N0GPIO93 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO92_Pos (28UL)                  /*!< DSP0N0GPIO92 (Bit 28)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO92_Msk (0x10000000UL)          /*!< DSP0N0GPIO92 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO91_Pos (27UL)                  /*!< DSP0N0GPIO91 (Bit 27)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO91_Msk (0x8000000UL)           /*!< DSP0N0GPIO91 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO90_Pos (26UL)                  /*!< DSP0N0GPIO90 (Bit 26)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO90_Msk (0x4000000UL)           /*!< DSP0N0GPIO90 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO89_Pos (25UL)                  /*!< DSP0N0GPIO89 (Bit 25)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO89_Msk (0x2000000UL)           /*!< DSP0N0GPIO89 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO88_Pos (24UL)                  /*!< DSP0N0GPIO88 (Bit 24)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO88_Msk (0x1000000UL)           /*!< DSP0N0GPIO88 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO87_Pos (23UL)                  /*!< DSP0N0GPIO87 (Bit 23)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO87_Msk (0x800000UL)            /*!< DSP0N0GPIO87 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO86_Pos (22UL)                  /*!< DSP0N0GPIO86 (Bit 22)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO86_Msk (0x400000UL)            /*!< DSP0N0GPIO86 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO85_Pos (21UL)                  /*!< DSP0N0GPIO85 (Bit 21)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO85_Msk (0x200000UL)            /*!< DSP0N0GPIO85 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO84_Pos (20UL)                  /*!< DSP0N0GPIO84 (Bit 20)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO84_Msk (0x100000UL)            /*!< DSP0N0GPIO84 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO83_Pos (19UL)                  /*!< DSP0N0GPIO83 (Bit 19)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO83_Msk (0x80000UL)             /*!< DSP0N0GPIO83 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO82_Pos (18UL)                  /*!< DSP0N0GPIO82 (Bit 18)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO82_Msk (0x40000UL)             /*!< DSP0N0GPIO82 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO81_Pos (17UL)                  /*!< DSP0N0GPIO81 (Bit 17)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO81_Msk (0x20000UL)             /*!< DSP0N0GPIO81 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO80_Pos (16UL)                  /*!< DSP0N0GPIO80 (Bit 16)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO80_Msk (0x10000UL)             /*!< DSP0N0GPIO80 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO79_Pos (15UL)                  /*!< DSP0N0GPIO79 (Bit 15)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO79_Msk (0x8000UL)              /*!< DSP0N0GPIO79 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO78_Pos (14UL)                  /*!< DSP0N0GPIO78 (Bit 14)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO78_Msk (0x4000UL)              /*!< DSP0N0GPIO78 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO77_Pos (13UL)                  /*!< DSP0N0GPIO77 (Bit 13)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO77_Msk (0x2000UL)              /*!< DSP0N0GPIO77 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO76_Pos (12UL)                  /*!< DSP0N0GPIO76 (Bit 12)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO76_Msk (0x1000UL)              /*!< DSP0N0GPIO76 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO75_Pos (11UL)                  /*!< DSP0N0GPIO75 (Bit 11)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO75_Msk (0x800UL)               /*!< DSP0N0GPIO75 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO74_Pos (10UL)                  /*!< DSP0N0GPIO74 (Bit 10)                                 */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO74_Msk (0x400UL)               /*!< DSP0N0GPIO74 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO73_Pos (9UL)                   /*!< DSP0N0GPIO73 (Bit 9)                                  */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO73_Msk (0x200UL)               /*!< DSP0N0GPIO73 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO72_Pos (8UL)                   /*!< DSP0N0GPIO72 (Bit 8)                                  */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO72_Msk (0x100UL)               /*!< DSP0N0GPIO72 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO71_Pos (7UL)                   /*!< DSP0N0GPIO71 (Bit 7)                                  */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO71_Msk (0x80UL)                /*!< DSP0N0GPIO71 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO70_Pos (6UL)                   /*!< DSP0N0GPIO70 (Bit 6)                                  */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO70_Msk (0x40UL)                /*!< DSP0N0GPIO70 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO69_Pos (5UL)                   /*!< DSP0N0GPIO69 (Bit 5)                                  */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO69_Msk (0x20UL)                /*!< DSP0N0GPIO69 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO68_Pos (4UL)                   /*!< DSP0N0GPIO68 (Bit 4)                                  */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO68_Msk (0x10UL)                /*!< DSP0N0GPIO68 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO67_Pos (3UL)                   /*!< DSP0N0GPIO67 (Bit 3)                                  */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO67_Msk (0x8UL)                 /*!< DSP0N0GPIO67 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO66_Pos (2UL)                   /*!< DSP0N0GPIO66 (Bit 2)                                  */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO66_Msk (0x4UL)                 /*!< DSP0N0GPIO66 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO65_Pos (1UL)                   /*!< DSP0N0GPIO65 (Bit 1)                                  */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO65_Msk (0x2UL)                 /*!< DSP0N0GPIO65 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO64_Pos (0UL)                   /*!< DSP0N0GPIO64 (Bit 0)                                  */
#define GPIO_DSP0N0INT2CLR_DSP0N0GPIO64_Msk (0x1UL)                 /*!< DSP0N0GPIO64 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0N0INT2SET  ===================================================== */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO95_Pos (31UL)                  /*!< DSP0N0GPIO95 (Bit 31)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO95_Msk (0x80000000UL)          /*!< DSP0N0GPIO95 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO94_Pos (30UL)                  /*!< DSP0N0GPIO94 (Bit 30)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO94_Msk (0x40000000UL)          /*!< DSP0N0GPIO94 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO93_Pos (29UL)                  /*!< DSP0N0GPIO93 (Bit 29)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO93_Msk (0x20000000UL)          /*!< DSP0N0GPIO93 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO92_Pos (28UL)                  /*!< DSP0N0GPIO92 (Bit 28)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO92_Msk (0x10000000UL)          /*!< DSP0N0GPIO92 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO91_Pos (27UL)                  /*!< DSP0N0GPIO91 (Bit 27)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO91_Msk (0x8000000UL)           /*!< DSP0N0GPIO91 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO90_Pos (26UL)                  /*!< DSP0N0GPIO90 (Bit 26)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO90_Msk (0x4000000UL)           /*!< DSP0N0GPIO90 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO89_Pos (25UL)                  /*!< DSP0N0GPIO89 (Bit 25)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO89_Msk (0x2000000UL)           /*!< DSP0N0GPIO89 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO88_Pos (24UL)                  /*!< DSP0N0GPIO88 (Bit 24)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO88_Msk (0x1000000UL)           /*!< DSP0N0GPIO88 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO87_Pos (23UL)                  /*!< DSP0N0GPIO87 (Bit 23)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO87_Msk (0x800000UL)            /*!< DSP0N0GPIO87 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO86_Pos (22UL)                  /*!< DSP0N0GPIO86 (Bit 22)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO86_Msk (0x400000UL)            /*!< DSP0N0GPIO86 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO85_Pos (21UL)                  /*!< DSP0N0GPIO85 (Bit 21)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO85_Msk (0x200000UL)            /*!< DSP0N0GPIO85 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO84_Pos (20UL)                  /*!< DSP0N0GPIO84 (Bit 20)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO84_Msk (0x100000UL)            /*!< DSP0N0GPIO84 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO83_Pos (19UL)                  /*!< DSP0N0GPIO83 (Bit 19)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO83_Msk (0x80000UL)             /*!< DSP0N0GPIO83 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO82_Pos (18UL)                  /*!< DSP0N0GPIO82 (Bit 18)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO82_Msk (0x40000UL)             /*!< DSP0N0GPIO82 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO81_Pos (17UL)                  /*!< DSP0N0GPIO81 (Bit 17)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO81_Msk (0x20000UL)             /*!< DSP0N0GPIO81 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO80_Pos (16UL)                  /*!< DSP0N0GPIO80 (Bit 16)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO80_Msk (0x10000UL)             /*!< DSP0N0GPIO80 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO79_Pos (15UL)                  /*!< DSP0N0GPIO79 (Bit 15)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO79_Msk (0x8000UL)              /*!< DSP0N0GPIO79 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO78_Pos (14UL)                  /*!< DSP0N0GPIO78 (Bit 14)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO78_Msk (0x4000UL)              /*!< DSP0N0GPIO78 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO77_Pos (13UL)                  /*!< DSP0N0GPIO77 (Bit 13)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO77_Msk (0x2000UL)              /*!< DSP0N0GPIO77 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO76_Pos (12UL)                  /*!< DSP0N0GPIO76 (Bit 12)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO76_Msk (0x1000UL)              /*!< DSP0N0GPIO76 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO75_Pos (11UL)                  /*!< DSP0N0GPIO75 (Bit 11)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO75_Msk (0x800UL)               /*!< DSP0N0GPIO75 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO74_Pos (10UL)                  /*!< DSP0N0GPIO74 (Bit 10)                                 */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO74_Msk (0x400UL)               /*!< DSP0N0GPIO74 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO73_Pos (9UL)                   /*!< DSP0N0GPIO73 (Bit 9)                                  */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO73_Msk (0x200UL)               /*!< DSP0N0GPIO73 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO72_Pos (8UL)                   /*!< DSP0N0GPIO72 (Bit 8)                                  */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO72_Msk (0x100UL)               /*!< DSP0N0GPIO72 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO71_Pos (7UL)                   /*!< DSP0N0GPIO71 (Bit 7)                                  */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO71_Msk (0x80UL)                /*!< DSP0N0GPIO71 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO70_Pos (6UL)                   /*!< DSP0N0GPIO70 (Bit 6)                                  */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO70_Msk (0x40UL)                /*!< DSP0N0GPIO70 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO69_Pos (5UL)                   /*!< DSP0N0GPIO69 (Bit 5)                                  */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO69_Msk (0x20UL)                /*!< DSP0N0GPIO69 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO68_Pos (4UL)                   /*!< DSP0N0GPIO68 (Bit 4)                                  */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO68_Msk (0x10UL)                /*!< DSP0N0GPIO68 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO67_Pos (3UL)                   /*!< DSP0N0GPIO67 (Bit 3)                                  */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO67_Msk (0x8UL)                 /*!< DSP0N0GPIO67 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO66_Pos (2UL)                   /*!< DSP0N0GPIO66 (Bit 2)                                  */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO66_Msk (0x4UL)                 /*!< DSP0N0GPIO66 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO65_Pos (1UL)                   /*!< DSP0N0GPIO65 (Bit 1)                                  */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO65_Msk (0x2UL)                 /*!< DSP0N0GPIO65 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO64_Pos (0UL)                   /*!< DSP0N0GPIO64 (Bit 0)                                  */
#define GPIO_DSP0N0INT2SET_DSP0N0GPIO64_Msk (0x1UL)                 /*!< DSP0N0GPIO64 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0N0INT3EN  ====================================================== */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO127_Pos (31UL)                  /*!< DSP0N0GPIO127 (Bit 31)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO127_Msk (0x80000000UL)          /*!< DSP0N0GPIO127 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO126_Pos (30UL)                  /*!< DSP0N0GPIO126 (Bit 30)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO126_Msk (0x40000000UL)          /*!< DSP0N0GPIO126 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO125_Pos (29UL)                  /*!< DSP0N0GPIO125 (Bit 29)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO125_Msk (0x20000000UL)          /*!< DSP0N0GPIO125 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO124_Pos (28UL)                  /*!< DSP0N0GPIO124 (Bit 28)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO124_Msk (0x10000000UL)          /*!< DSP0N0GPIO124 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO123_Pos (27UL)                  /*!< DSP0N0GPIO123 (Bit 27)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO123_Msk (0x8000000UL)           /*!< DSP0N0GPIO123 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO122_Pos (26UL)                  /*!< DSP0N0GPIO122 (Bit 26)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO122_Msk (0x4000000UL)           /*!< DSP0N0GPIO122 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO121_Pos (25UL)                  /*!< DSP0N0GPIO121 (Bit 25)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO121_Msk (0x2000000UL)           /*!< DSP0N0GPIO121 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO120_Pos (24UL)                  /*!< DSP0N0GPIO120 (Bit 24)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO120_Msk (0x1000000UL)           /*!< DSP0N0GPIO120 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO119_Pos (23UL)                  /*!< DSP0N0GPIO119 (Bit 23)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO119_Msk (0x800000UL)            /*!< DSP0N0GPIO119 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO118_Pos (22UL)                  /*!< DSP0N0GPIO118 (Bit 22)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO118_Msk (0x400000UL)            /*!< DSP0N0GPIO118 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO117_Pos (21UL)                  /*!< DSP0N0GPIO117 (Bit 21)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO117_Msk (0x200000UL)            /*!< DSP0N0GPIO117 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO116_Pos (20UL)                  /*!< DSP0N0GPIO116 (Bit 20)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO116_Msk (0x100000UL)            /*!< DSP0N0GPIO116 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO115_Pos (19UL)                  /*!< DSP0N0GPIO115 (Bit 19)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO115_Msk (0x80000UL)             /*!< DSP0N0GPIO115 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO114_Pos (18UL)                  /*!< DSP0N0GPIO114 (Bit 18)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO114_Msk (0x40000UL)             /*!< DSP0N0GPIO114 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO113_Pos (17UL)                  /*!< DSP0N0GPIO113 (Bit 17)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO113_Msk (0x20000UL)             /*!< DSP0N0GPIO113 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO112_Pos (16UL)                  /*!< DSP0N0GPIO112 (Bit 16)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO112_Msk (0x10000UL)             /*!< DSP0N0GPIO112 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO111_Pos (15UL)                  /*!< DSP0N0GPIO111 (Bit 15)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO111_Msk (0x8000UL)              /*!< DSP0N0GPIO111 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO110_Pos (14UL)                  /*!< DSP0N0GPIO110 (Bit 14)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO110_Msk (0x4000UL)              /*!< DSP0N0GPIO110 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO109_Pos (13UL)                  /*!< DSP0N0GPIO109 (Bit 13)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO109_Msk (0x2000UL)              /*!< DSP0N0GPIO109 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO108_Pos (12UL)                  /*!< DSP0N0GPIO108 (Bit 12)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO108_Msk (0x1000UL)              /*!< DSP0N0GPIO108 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO107_Pos (11UL)                  /*!< DSP0N0GPIO107 (Bit 11)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO107_Msk (0x800UL)               /*!< DSP0N0GPIO107 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO106_Pos (10UL)                  /*!< DSP0N0GPIO106 (Bit 10)                                */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO106_Msk (0x400UL)               /*!< DSP0N0GPIO106 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO105_Pos (9UL)                   /*!< DSP0N0GPIO105 (Bit 9)                                 */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO105_Msk (0x200UL)               /*!< DSP0N0GPIO105 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO104_Pos (8UL)                   /*!< DSP0N0GPIO104 (Bit 8)                                 */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO104_Msk (0x100UL)               /*!< DSP0N0GPIO104 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO103_Pos (7UL)                   /*!< DSP0N0GPIO103 (Bit 7)                                 */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO103_Msk (0x80UL)                /*!< DSP0N0GPIO103 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO102_Pos (6UL)                   /*!< DSP0N0GPIO102 (Bit 6)                                 */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO102_Msk (0x40UL)                /*!< DSP0N0GPIO102 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO101_Pos (5UL)                   /*!< DSP0N0GPIO101 (Bit 5)                                 */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO101_Msk (0x20UL)                /*!< DSP0N0GPIO101 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO100_Pos (4UL)                   /*!< DSP0N0GPIO100 (Bit 4)                                 */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO100_Msk (0x10UL)                /*!< DSP0N0GPIO100 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO99_Pos (3UL)                    /*!< DSP0N0GPIO99 (Bit 3)                                  */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO99_Msk (0x8UL)                  /*!< DSP0N0GPIO99 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO98_Pos (2UL)                    /*!< DSP0N0GPIO98 (Bit 2)                                  */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO98_Msk (0x4UL)                  /*!< DSP0N0GPIO98 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO97_Pos (1UL)                    /*!< DSP0N0GPIO97 (Bit 1)                                  */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO97_Msk (0x2UL)                  /*!< DSP0N0GPIO97 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO96_Pos (0UL)                    /*!< DSP0N0GPIO96 (Bit 0)                                  */
#define GPIO_DSP0N0INT3EN_DSP0N0GPIO96_Msk (0x1UL)                  /*!< DSP0N0GPIO96 (Bitfield-Mask: 0x01)                    */
/* ====================================================  DSP0N0INT3STAT  ===================================================== */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO127_Pos (31UL)                /*!< DSP0N0GPIO127 (Bit 31)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO127_Msk (0x80000000UL)        /*!< DSP0N0GPIO127 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO126_Pos (30UL)                /*!< DSP0N0GPIO126 (Bit 30)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO126_Msk (0x40000000UL)        /*!< DSP0N0GPIO126 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO125_Pos (29UL)                /*!< DSP0N0GPIO125 (Bit 29)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO125_Msk (0x20000000UL)        /*!< DSP0N0GPIO125 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO124_Pos (28UL)                /*!< DSP0N0GPIO124 (Bit 28)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO124_Msk (0x10000000UL)        /*!< DSP0N0GPIO124 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO123_Pos (27UL)                /*!< DSP0N0GPIO123 (Bit 27)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO123_Msk (0x8000000UL)         /*!< DSP0N0GPIO123 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO122_Pos (26UL)                /*!< DSP0N0GPIO122 (Bit 26)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO122_Msk (0x4000000UL)         /*!< DSP0N0GPIO122 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO121_Pos (25UL)                /*!< DSP0N0GPIO121 (Bit 25)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO121_Msk (0x2000000UL)         /*!< DSP0N0GPIO121 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO120_Pos (24UL)                /*!< DSP0N0GPIO120 (Bit 24)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO120_Msk (0x1000000UL)         /*!< DSP0N0GPIO120 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO119_Pos (23UL)                /*!< DSP0N0GPIO119 (Bit 23)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO119_Msk (0x800000UL)          /*!< DSP0N0GPIO119 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO118_Pos (22UL)                /*!< DSP0N0GPIO118 (Bit 22)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO118_Msk (0x400000UL)          /*!< DSP0N0GPIO118 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO117_Pos (21UL)                /*!< DSP0N0GPIO117 (Bit 21)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO117_Msk (0x200000UL)          /*!< DSP0N0GPIO117 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO116_Pos (20UL)                /*!< DSP0N0GPIO116 (Bit 20)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO116_Msk (0x100000UL)          /*!< DSP0N0GPIO116 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO115_Pos (19UL)                /*!< DSP0N0GPIO115 (Bit 19)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO115_Msk (0x80000UL)           /*!< DSP0N0GPIO115 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO114_Pos (18UL)                /*!< DSP0N0GPIO114 (Bit 18)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO114_Msk (0x40000UL)           /*!< DSP0N0GPIO114 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO113_Pos (17UL)                /*!< DSP0N0GPIO113 (Bit 17)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO113_Msk (0x20000UL)           /*!< DSP0N0GPIO113 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO112_Pos (16UL)                /*!< DSP0N0GPIO112 (Bit 16)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO112_Msk (0x10000UL)           /*!< DSP0N0GPIO112 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO111_Pos (15UL)                /*!< DSP0N0GPIO111 (Bit 15)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO111_Msk (0x8000UL)            /*!< DSP0N0GPIO111 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO110_Pos (14UL)                /*!< DSP0N0GPIO110 (Bit 14)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO110_Msk (0x4000UL)            /*!< DSP0N0GPIO110 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO109_Pos (13UL)                /*!< DSP0N0GPIO109 (Bit 13)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO109_Msk (0x2000UL)            /*!< DSP0N0GPIO109 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO108_Pos (12UL)                /*!< DSP0N0GPIO108 (Bit 12)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO108_Msk (0x1000UL)            /*!< DSP0N0GPIO108 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO107_Pos (11UL)                /*!< DSP0N0GPIO107 (Bit 11)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO107_Msk (0x800UL)             /*!< DSP0N0GPIO107 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO106_Pos (10UL)                /*!< DSP0N0GPIO106 (Bit 10)                                */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO106_Msk (0x400UL)             /*!< DSP0N0GPIO106 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO105_Pos (9UL)                 /*!< DSP0N0GPIO105 (Bit 9)                                 */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO105_Msk (0x200UL)             /*!< DSP0N0GPIO105 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO104_Pos (8UL)                 /*!< DSP0N0GPIO104 (Bit 8)                                 */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO104_Msk (0x100UL)             /*!< DSP0N0GPIO104 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO103_Pos (7UL)                 /*!< DSP0N0GPIO103 (Bit 7)                                 */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO103_Msk (0x80UL)              /*!< DSP0N0GPIO103 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO102_Pos (6UL)                 /*!< DSP0N0GPIO102 (Bit 6)                                 */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO102_Msk (0x40UL)              /*!< DSP0N0GPIO102 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO101_Pos (5UL)                 /*!< DSP0N0GPIO101 (Bit 5)                                 */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO101_Msk (0x20UL)              /*!< DSP0N0GPIO101 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO100_Pos (4UL)                 /*!< DSP0N0GPIO100 (Bit 4)                                 */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO100_Msk (0x10UL)              /*!< DSP0N0GPIO100 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO99_Pos (3UL)                  /*!< DSP0N0GPIO99 (Bit 3)                                  */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO99_Msk (0x8UL)                /*!< DSP0N0GPIO99 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO98_Pos (2UL)                  /*!< DSP0N0GPIO98 (Bit 2)                                  */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO98_Msk (0x4UL)                /*!< DSP0N0GPIO98 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO97_Pos (1UL)                  /*!< DSP0N0GPIO97 (Bit 1)                                  */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO97_Msk (0x2UL)                /*!< DSP0N0GPIO97 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO96_Pos (0UL)                  /*!< DSP0N0GPIO96 (Bit 0)                                  */
#define GPIO_DSP0N0INT3STAT_DSP0N0GPIO96_Msk (0x1UL)                /*!< DSP0N0GPIO96 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0N0INT3CLR  ===================================================== */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO127_Pos (31UL)                 /*!< DSP0N0GPIO127 (Bit 31)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO127_Msk (0x80000000UL)         /*!< DSP0N0GPIO127 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO126_Pos (30UL)                 /*!< DSP0N0GPIO126 (Bit 30)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO126_Msk (0x40000000UL)         /*!< DSP0N0GPIO126 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO125_Pos (29UL)                 /*!< DSP0N0GPIO125 (Bit 29)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO125_Msk (0x20000000UL)         /*!< DSP0N0GPIO125 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO124_Pos (28UL)                 /*!< DSP0N0GPIO124 (Bit 28)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO124_Msk (0x10000000UL)         /*!< DSP0N0GPIO124 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO123_Pos (27UL)                 /*!< DSP0N0GPIO123 (Bit 27)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO123_Msk (0x8000000UL)          /*!< DSP0N0GPIO123 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO122_Pos (26UL)                 /*!< DSP0N0GPIO122 (Bit 26)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO122_Msk (0x4000000UL)          /*!< DSP0N0GPIO122 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO121_Pos (25UL)                 /*!< DSP0N0GPIO121 (Bit 25)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO121_Msk (0x2000000UL)          /*!< DSP0N0GPIO121 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO120_Pos (24UL)                 /*!< DSP0N0GPIO120 (Bit 24)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO120_Msk (0x1000000UL)          /*!< DSP0N0GPIO120 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO119_Pos (23UL)                 /*!< DSP0N0GPIO119 (Bit 23)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO119_Msk (0x800000UL)           /*!< DSP0N0GPIO119 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO118_Pos (22UL)                 /*!< DSP0N0GPIO118 (Bit 22)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO118_Msk (0x400000UL)           /*!< DSP0N0GPIO118 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO117_Pos (21UL)                 /*!< DSP0N0GPIO117 (Bit 21)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO117_Msk (0x200000UL)           /*!< DSP0N0GPIO117 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO116_Pos (20UL)                 /*!< DSP0N0GPIO116 (Bit 20)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO116_Msk (0x100000UL)           /*!< DSP0N0GPIO116 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO115_Pos (19UL)                 /*!< DSP0N0GPIO115 (Bit 19)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO115_Msk (0x80000UL)            /*!< DSP0N0GPIO115 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO114_Pos (18UL)                 /*!< DSP0N0GPIO114 (Bit 18)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO114_Msk (0x40000UL)            /*!< DSP0N0GPIO114 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO113_Pos (17UL)                 /*!< DSP0N0GPIO113 (Bit 17)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO113_Msk (0x20000UL)            /*!< DSP0N0GPIO113 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO112_Pos (16UL)                 /*!< DSP0N0GPIO112 (Bit 16)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO112_Msk (0x10000UL)            /*!< DSP0N0GPIO112 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO111_Pos (15UL)                 /*!< DSP0N0GPIO111 (Bit 15)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO111_Msk (0x8000UL)             /*!< DSP0N0GPIO111 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO110_Pos (14UL)                 /*!< DSP0N0GPIO110 (Bit 14)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO110_Msk (0x4000UL)             /*!< DSP0N0GPIO110 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO109_Pos (13UL)                 /*!< DSP0N0GPIO109 (Bit 13)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO109_Msk (0x2000UL)             /*!< DSP0N0GPIO109 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO108_Pos (12UL)                 /*!< DSP0N0GPIO108 (Bit 12)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO108_Msk (0x1000UL)             /*!< DSP0N0GPIO108 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO107_Pos (11UL)                 /*!< DSP0N0GPIO107 (Bit 11)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO107_Msk (0x800UL)              /*!< DSP0N0GPIO107 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO106_Pos (10UL)                 /*!< DSP0N0GPIO106 (Bit 10)                                */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO106_Msk (0x400UL)              /*!< DSP0N0GPIO106 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO105_Pos (9UL)                  /*!< DSP0N0GPIO105 (Bit 9)                                 */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO105_Msk (0x200UL)              /*!< DSP0N0GPIO105 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO104_Pos (8UL)                  /*!< DSP0N0GPIO104 (Bit 8)                                 */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO104_Msk (0x100UL)              /*!< DSP0N0GPIO104 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO103_Pos (7UL)                  /*!< DSP0N0GPIO103 (Bit 7)                                 */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO103_Msk (0x80UL)               /*!< DSP0N0GPIO103 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO102_Pos (6UL)                  /*!< DSP0N0GPIO102 (Bit 6)                                 */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO102_Msk (0x40UL)               /*!< DSP0N0GPIO102 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO101_Pos (5UL)                  /*!< DSP0N0GPIO101 (Bit 5)                                 */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO101_Msk (0x20UL)               /*!< DSP0N0GPIO101 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO100_Pos (4UL)                  /*!< DSP0N0GPIO100 (Bit 4)                                 */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO100_Msk (0x10UL)               /*!< DSP0N0GPIO100 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO99_Pos (3UL)                   /*!< DSP0N0GPIO99 (Bit 3)                                  */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO99_Msk (0x8UL)                 /*!< DSP0N0GPIO99 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO98_Pos (2UL)                   /*!< DSP0N0GPIO98 (Bit 2)                                  */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO98_Msk (0x4UL)                 /*!< DSP0N0GPIO98 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO97_Pos (1UL)                   /*!< DSP0N0GPIO97 (Bit 1)                                  */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO97_Msk (0x2UL)                 /*!< DSP0N0GPIO97 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO96_Pos (0UL)                   /*!< DSP0N0GPIO96 (Bit 0)                                  */
#define GPIO_DSP0N0INT3CLR_DSP0N0GPIO96_Msk (0x1UL)                 /*!< DSP0N0GPIO96 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0N0INT3SET  ===================================================== */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO127_Pos (31UL)                 /*!< DSP0N0GPIO127 (Bit 31)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO127_Msk (0x80000000UL)         /*!< DSP0N0GPIO127 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO126_Pos (30UL)                 /*!< DSP0N0GPIO126 (Bit 30)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO126_Msk (0x40000000UL)         /*!< DSP0N0GPIO126 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO125_Pos (29UL)                 /*!< DSP0N0GPIO125 (Bit 29)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO125_Msk (0x20000000UL)         /*!< DSP0N0GPIO125 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO124_Pos (28UL)                 /*!< DSP0N0GPIO124 (Bit 28)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO124_Msk (0x10000000UL)         /*!< DSP0N0GPIO124 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO123_Pos (27UL)                 /*!< DSP0N0GPIO123 (Bit 27)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO123_Msk (0x8000000UL)          /*!< DSP0N0GPIO123 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO122_Pos (26UL)                 /*!< DSP0N0GPIO122 (Bit 26)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO122_Msk (0x4000000UL)          /*!< DSP0N0GPIO122 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO121_Pos (25UL)                 /*!< DSP0N0GPIO121 (Bit 25)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO121_Msk (0x2000000UL)          /*!< DSP0N0GPIO121 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO120_Pos (24UL)                 /*!< DSP0N0GPIO120 (Bit 24)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO120_Msk (0x1000000UL)          /*!< DSP0N0GPIO120 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO119_Pos (23UL)                 /*!< DSP0N0GPIO119 (Bit 23)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO119_Msk (0x800000UL)           /*!< DSP0N0GPIO119 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO118_Pos (22UL)                 /*!< DSP0N0GPIO118 (Bit 22)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO118_Msk (0x400000UL)           /*!< DSP0N0GPIO118 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO117_Pos (21UL)                 /*!< DSP0N0GPIO117 (Bit 21)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO117_Msk (0x200000UL)           /*!< DSP0N0GPIO117 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO116_Pos (20UL)                 /*!< DSP0N0GPIO116 (Bit 20)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO116_Msk (0x100000UL)           /*!< DSP0N0GPIO116 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO115_Pos (19UL)                 /*!< DSP0N0GPIO115 (Bit 19)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO115_Msk (0x80000UL)            /*!< DSP0N0GPIO115 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO114_Pos (18UL)                 /*!< DSP0N0GPIO114 (Bit 18)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO114_Msk (0x40000UL)            /*!< DSP0N0GPIO114 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO113_Pos (17UL)                 /*!< DSP0N0GPIO113 (Bit 17)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO113_Msk (0x20000UL)            /*!< DSP0N0GPIO113 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO112_Pos (16UL)                 /*!< DSP0N0GPIO112 (Bit 16)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO112_Msk (0x10000UL)            /*!< DSP0N0GPIO112 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO111_Pos (15UL)                 /*!< DSP0N0GPIO111 (Bit 15)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO111_Msk (0x8000UL)             /*!< DSP0N0GPIO111 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO110_Pos (14UL)                 /*!< DSP0N0GPIO110 (Bit 14)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO110_Msk (0x4000UL)             /*!< DSP0N0GPIO110 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO109_Pos (13UL)                 /*!< DSP0N0GPIO109 (Bit 13)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO109_Msk (0x2000UL)             /*!< DSP0N0GPIO109 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO108_Pos (12UL)                 /*!< DSP0N0GPIO108 (Bit 12)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO108_Msk (0x1000UL)             /*!< DSP0N0GPIO108 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO107_Pos (11UL)                 /*!< DSP0N0GPIO107 (Bit 11)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO107_Msk (0x800UL)              /*!< DSP0N0GPIO107 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO106_Pos (10UL)                 /*!< DSP0N0GPIO106 (Bit 10)                                */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO106_Msk (0x400UL)              /*!< DSP0N0GPIO106 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO105_Pos (9UL)                  /*!< DSP0N0GPIO105 (Bit 9)                                 */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO105_Msk (0x200UL)              /*!< DSP0N0GPIO105 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO104_Pos (8UL)                  /*!< DSP0N0GPIO104 (Bit 8)                                 */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO104_Msk (0x100UL)              /*!< DSP0N0GPIO104 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO103_Pos (7UL)                  /*!< DSP0N0GPIO103 (Bit 7)                                 */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO103_Msk (0x80UL)               /*!< DSP0N0GPIO103 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO102_Pos (6UL)                  /*!< DSP0N0GPIO102 (Bit 6)                                 */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO102_Msk (0x40UL)               /*!< DSP0N0GPIO102 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO101_Pos (5UL)                  /*!< DSP0N0GPIO101 (Bit 5)                                 */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO101_Msk (0x20UL)               /*!< DSP0N0GPIO101 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO100_Pos (4UL)                  /*!< DSP0N0GPIO100 (Bit 4)                                 */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO100_Msk (0x10UL)               /*!< DSP0N0GPIO100 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO99_Pos (3UL)                   /*!< DSP0N0GPIO99 (Bit 3)                                  */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO99_Msk (0x8UL)                 /*!< DSP0N0GPIO99 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO98_Pos (2UL)                   /*!< DSP0N0GPIO98 (Bit 2)                                  */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO98_Msk (0x4UL)                 /*!< DSP0N0GPIO98 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO97_Pos (1UL)                   /*!< DSP0N0GPIO97 (Bit 1)                                  */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO97_Msk (0x2UL)                 /*!< DSP0N0GPIO97 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO96_Pos (0UL)                   /*!< DSP0N0GPIO96 (Bit 0)                                  */
#define GPIO_DSP0N0INT3SET_DSP0N0GPIO96_Msk (0x1UL)                 /*!< DSP0N0GPIO96 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0N1INT0EN  ====================================================== */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO31_Pos (31UL)                   /*!< DSP0N1GPIO31 (Bit 31)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO31_Msk (0x80000000UL)           /*!< DSP0N1GPIO31 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO30_Pos (30UL)                   /*!< DSP0N1GPIO30 (Bit 30)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO30_Msk (0x40000000UL)           /*!< DSP0N1GPIO30 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO29_Pos (29UL)                   /*!< DSP0N1GPIO29 (Bit 29)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO29_Msk (0x20000000UL)           /*!< DSP0N1GPIO29 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO28_Pos (28UL)                   /*!< DSP0N1GPIO28 (Bit 28)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO28_Msk (0x10000000UL)           /*!< DSP0N1GPIO28 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO27_Pos (27UL)                   /*!< DSP0N1GPIO27 (Bit 27)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO27_Msk (0x8000000UL)            /*!< DSP0N1GPIO27 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO26_Pos (26UL)                   /*!< DSP0N1GPIO26 (Bit 26)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO26_Msk (0x4000000UL)            /*!< DSP0N1GPIO26 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO25_Pos (25UL)                   /*!< DSP0N1GPIO25 (Bit 25)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO25_Msk (0x2000000UL)            /*!< DSP0N1GPIO25 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO24_Pos (24UL)                   /*!< DSP0N1GPIO24 (Bit 24)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO24_Msk (0x1000000UL)            /*!< DSP0N1GPIO24 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO23_Pos (23UL)                   /*!< DSP0N1GPIO23 (Bit 23)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO23_Msk (0x800000UL)             /*!< DSP0N1GPIO23 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO22_Pos (22UL)                   /*!< DSP0N1GPIO22 (Bit 22)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO22_Msk (0x400000UL)             /*!< DSP0N1GPIO22 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO21_Pos (21UL)                   /*!< DSP0N1GPIO21 (Bit 21)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO21_Msk (0x200000UL)             /*!< DSP0N1GPIO21 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO20_Pos (20UL)                   /*!< DSP0N1GPIO20 (Bit 20)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO20_Msk (0x100000UL)             /*!< DSP0N1GPIO20 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO19_Pos (19UL)                   /*!< DSP0N1GPIO19 (Bit 19)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO19_Msk (0x80000UL)              /*!< DSP0N1GPIO19 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO18_Pos (18UL)                   /*!< DSP0N1GPIO18 (Bit 18)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO18_Msk (0x40000UL)              /*!< DSP0N1GPIO18 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO17_Pos (17UL)                   /*!< DSP0N1GPIO17 (Bit 17)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO17_Msk (0x20000UL)              /*!< DSP0N1GPIO17 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO16_Pos (16UL)                   /*!< DSP0N1GPIO16 (Bit 16)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO16_Msk (0x10000UL)              /*!< DSP0N1GPIO16 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO15_Pos (15UL)                   /*!< DSP0N1GPIO15 (Bit 15)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO15_Msk (0x8000UL)               /*!< DSP0N1GPIO15 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO14_Pos (14UL)                   /*!< DSP0N1GPIO14 (Bit 14)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO14_Msk (0x4000UL)               /*!< DSP0N1GPIO14 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO13_Pos (13UL)                   /*!< DSP0N1GPIO13 (Bit 13)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO13_Msk (0x2000UL)               /*!< DSP0N1GPIO13 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO12_Pos (12UL)                   /*!< DSP0N1GPIO12 (Bit 12)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO12_Msk (0x1000UL)               /*!< DSP0N1GPIO12 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO11_Pos (11UL)                   /*!< DSP0N1GPIO11 (Bit 11)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO11_Msk (0x800UL)                /*!< DSP0N1GPIO11 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO10_Pos (10UL)                   /*!< DSP0N1GPIO10 (Bit 10)                                 */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO10_Msk (0x400UL)                /*!< DSP0N1GPIO10 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO9_Pos (9UL)                     /*!< DSP0N1GPIO9 (Bit 9)                                   */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO9_Msk (0x200UL)                 /*!< DSP0N1GPIO9 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO8_Pos (8UL)                     /*!< DSP0N1GPIO8 (Bit 8)                                   */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO8_Msk (0x100UL)                 /*!< DSP0N1GPIO8 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO7_Pos (7UL)                     /*!< DSP0N1GPIO7 (Bit 7)                                   */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO7_Msk (0x80UL)                  /*!< DSP0N1GPIO7 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO6_Pos (6UL)                     /*!< DSP0N1GPIO6 (Bit 6)                                   */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO6_Msk (0x40UL)                  /*!< DSP0N1GPIO6 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO5_Pos (5UL)                     /*!< DSP0N1GPIO5 (Bit 5)                                   */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO5_Msk (0x20UL)                  /*!< DSP0N1GPIO5 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO4_Pos (4UL)                     /*!< DSP0N1GPIO4 (Bit 4)                                   */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO4_Msk (0x10UL)                  /*!< DSP0N1GPIO4 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO3_Pos (3UL)                     /*!< DSP0N1GPIO3 (Bit 3)                                   */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO3_Msk (0x8UL)                   /*!< DSP0N1GPIO3 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO2_Pos (2UL)                     /*!< DSP0N1GPIO2 (Bit 2)                                   */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO2_Msk (0x4UL)                   /*!< DSP0N1GPIO2 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO1_Pos (1UL)                     /*!< DSP0N1GPIO1 (Bit 1)                                   */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO1_Msk (0x2UL)                   /*!< DSP0N1GPIO1 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO0_Pos (0UL)                     /*!< DSP0N1GPIO0 (Bit 0)                                   */
#define GPIO_DSP0N1INT0EN_DSP0N1GPIO0_Msk (0x1UL)                   /*!< DSP0N1GPIO0 (Bitfield-Mask: 0x01)                     */
/* ====================================================  DSP0N1INT0STAT  ===================================================== */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO31_Pos (31UL)                 /*!< DSP0N1GPIO31 (Bit 31)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO31_Msk (0x80000000UL)         /*!< DSP0N1GPIO31 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO30_Pos (30UL)                 /*!< DSP0N1GPIO30 (Bit 30)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO30_Msk (0x40000000UL)         /*!< DSP0N1GPIO30 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO29_Pos (29UL)                 /*!< DSP0N1GPIO29 (Bit 29)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO29_Msk (0x20000000UL)         /*!< DSP0N1GPIO29 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO28_Pos (28UL)                 /*!< DSP0N1GPIO28 (Bit 28)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO28_Msk (0x10000000UL)         /*!< DSP0N1GPIO28 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO27_Pos (27UL)                 /*!< DSP0N1GPIO27 (Bit 27)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO27_Msk (0x8000000UL)          /*!< DSP0N1GPIO27 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO26_Pos (26UL)                 /*!< DSP0N1GPIO26 (Bit 26)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO26_Msk (0x4000000UL)          /*!< DSP0N1GPIO26 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO25_Pos (25UL)                 /*!< DSP0N1GPIO25 (Bit 25)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO25_Msk (0x2000000UL)          /*!< DSP0N1GPIO25 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO24_Pos (24UL)                 /*!< DSP0N1GPIO24 (Bit 24)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO24_Msk (0x1000000UL)          /*!< DSP0N1GPIO24 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO23_Pos (23UL)                 /*!< DSP0N1GPIO23 (Bit 23)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO23_Msk (0x800000UL)           /*!< DSP0N1GPIO23 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO22_Pos (22UL)                 /*!< DSP0N1GPIO22 (Bit 22)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO22_Msk (0x400000UL)           /*!< DSP0N1GPIO22 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO21_Pos (21UL)                 /*!< DSP0N1GPIO21 (Bit 21)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO21_Msk (0x200000UL)           /*!< DSP0N1GPIO21 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO20_Pos (20UL)                 /*!< DSP0N1GPIO20 (Bit 20)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO20_Msk (0x100000UL)           /*!< DSP0N1GPIO20 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO19_Pos (19UL)                 /*!< DSP0N1GPIO19 (Bit 19)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO19_Msk (0x80000UL)            /*!< DSP0N1GPIO19 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO18_Pos (18UL)                 /*!< DSP0N1GPIO18 (Bit 18)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO18_Msk (0x40000UL)            /*!< DSP0N1GPIO18 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO17_Pos (17UL)                 /*!< DSP0N1GPIO17 (Bit 17)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO17_Msk (0x20000UL)            /*!< DSP0N1GPIO17 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO16_Pos (16UL)                 /*!< DSP0N1GPIO16 (Bit 16)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO16_Msk (0x10000UL)            /*!< DSP0N1GPIO16 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO15_Pos (15UL)                 /*!< DSP0N1GPIO15 (Bit 15)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO15_Msk (0x8000UL)             /*!< DSP0N1GPIO15 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO14_Pos (14UL)                 /*!< DSP0N1GPIO14 (Bit 14)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO14_Msk (0x4000UL)             /*!< DSP0N1GPIO14 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO13_Pos (13UL)                 /*!< DSP0N1GPIO13 (Bit 13)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO13_Msk (0x2000UL)             /*!< DSP0N1GPIO13 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO12_Pos (12UL)                 /*!< DSP0N1GPIO12 (Bit 12)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO12_Msk (0x1000UL)             /*!< DSP0N1GPIO12 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO11_Pos (11UL)                 /*!< DSP0N1GPIO11 (Bit 11)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO11_Msk (0x800UL)              /*!< DSP0N1GPIO11 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO10_Pos (10UL)                 /*!< DSP0N1GPIO10 (Bit 10)                                 */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO10_Msk (0x400UL)              /*!< DSP0N1GPIO10 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO9_Pos (9UL)                   /*!< DSP0N1GPIO9 (Bit 9)                                   */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO9_Msk (0x200UL)               /*!< DSP0N1GPIO9 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO8_Pos (8UL)                   /*!< DSP0N1GPIO8 (Bit 8)                                   */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO8_Msk (0x100UL)               /*!< DSP0N1GPIO8 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO7_Pos (7UL)                   /*!< DSP0N1GPIO7 (Bit 7)                                   */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO7_Msk (0x80UL)                /*!< DSP0N1GPIO7 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO6_Pos (6UL)                   /*!< DSP0N1GPIO6 (Bit 6)                                   */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO6_Msk (0x40UL)                /*!< DSP0N1GPIO6 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO5_Pos (5UL)                   /*!< DSP0N1GPIO5 (Bit 5)                                   */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO5_Msk (0x20UL)                /*!< DSP0N1GPIO5 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO4_Pos (4UL)                   /*!< DSP0N1GPIO4 (Bit 4)                                   */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO4_Msk (0x10UL)                /*!< DSP0N1GPIO4 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO3_Pos (3UL)                   /*!< DSP0N1GPIO3 (Bit 3)                                   */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO3_Msk (0x8UL)                 /*!< DSP0N1GPIO3 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO2_Pos (2UL)                   /*!< DSP0N1GPIO2 (Bit 2)                                   */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO2_Msk (0x4UL)                 /*!< DSP0N1GPIO2 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO1_Pos (1UL)                   /*!< DSP0N1GPIO1 (Bit 1)                                   */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO1_Msk (0x2UL)                 /*!< DSP0N1GPIO1 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO0_Pos (0UL)                   /*!< DSP0N1GPIO0 (Bit 0)                                   */
#define GPIO_DSP0N1INT0STAT_DSP0N1GPIO0_Msk (0x1UL)                 /*!< DSP0N1GPIO0 (Bitfield-Mask: 0x01)                     */
/* =====================================================  DSP0N1INT0CLR  ===================================================== */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO31_Pos (31UL)                  /*!< DSP0N1GPIO31 (Bit 31)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO31_Msk (0x80000000UL)          /*!< DSP0N1GPIO31 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO30_Pos (30UL)                  /*!< DSP0N1GPIO30 (Bit 30)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO30_Msk (0x40000000UL)          /*!< DSP0N1GPIO30 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO29_Pos (29UL)                  /*!< DSP0N1GPIO29 (Bit 29)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO29_Msk (0x20000000UL)          /*!< DSP0N1GPIO29 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO28_Pos (28UL)                  /*!< DSP0N1GPIO28 (Bit 28)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO28_Msk (0x10000000UL)          /*!< DSP0N1GPIO28 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO27_Pos (27UL)                  /*!< DSP0N1GPIO27 (Bit 27)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO27_Msk (0x8000000UL)           /*!< DSP0N1GPIO27 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO26_Pos (26UL)                  /*!< DSP0N1GPIO26 (Bit 26)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO26_Msk (0x4000000UL)           /*!< DSP0N1GPIO26 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO25_Pos (25UL)                  /*!< DSP0N1GPIO25 (Bit 25)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO25_Msk (0x2000000UL)           /*!< DSP0N1GPIO25 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO24_Pos (24UL)                  /*!< DSP0N1GPIO24 (Bit 24)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO24_Msk (0x1000000UL)           /*!< DSP0N1GPIO24 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO23_Pos (23UL)                  /*!< DSP0N1GPIO23 (Bit 23)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO23_Msk (0x800000UL)            /*!< DSP0N1GPIO23 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO22_Pos (22UL)                  /*!< DSP0N1GPIO22 (Bit 22)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO22_Msk (0x400000UL)            /*!< DSP0N1GPIO22 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO21_Pos (21UL)                  /*!< DSP0N1GPIO21 (Bit 21)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO21_Msk (0x200000UL)            /*!< DSP0N1GPIO21 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO20_Pos (20UL)                  /*!< DSP0N1GPIO20 (Bit 20)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO20_Msk (0x100000UL)            /*!< DSP0N1GPIO20 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO19_Pos (19UL)                  /*!< DSP0N1GPIO19 (Bit 19)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO19_Msk (0x80000UL)             /*!< DSP0N1GPIO19 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO18_Pos (18UL)                  /*!< DSP0N1GPIO18 (Bit 18)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO18_Msk (0x40000UL)             /*!< DSP0N1GPIO18 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO17_Pos (17UL)                  /*!< DSP0N1GPIO17 (Bit 17)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO17_Msk (0x20000UL)             /*!< DSP0N1GPIO17 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO16_Pos (16UL)                  /*!< DSP0N1GPIO16 (Bit 16)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO16_Msk (0x10000UL)             /*!< DSP0N1GPIO16 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO15_Pos (15UL)                  /*!< DSP0N1GPIO15 (Bit 15)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO15_Msk (0x8000UL)              /*!< DSP0N1GPIO15 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO14_Pos (14UL)                  /*!< DSP0N1GPIO14 (Bit 14)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO14_Msk (0x4000UL)              /*!< DSP0N1GPIO14 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO13_Pos (13UL)                  /*!< DSP0N1GPIO13 (Bit 13)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO13_Msk (0x2000UL)              /*!< DSP0N1GPIO13 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO12_Pos (12UL)                  /*!< DSP0N1GPIO12 (Bit 12)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO12_Msk (0x1000UL)              /*!< DSP0N1GPIO12 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO11_Pos (11UL)                  /*!< DSP0N1GPIO11 (Bit 11)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO11_Msk (0x800UL)               /*!< DSP0N1GPIO11 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO10_Pos (10UL)                  /*!< DSP0N1GPIO10 (Bit 10)                                 */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO10_Msk (0x400UL)               /*!< DSP0N1GPIO10 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO9_Pos (9UL)                    /*!< DSP0N1GPIO9 (Bit 9)                                   */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO9_Msk (0x200UL)                /*!< DSP0N1GPIO9 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO8_Pos (8UL)                    /*!< DSP0N1GPIO8 (Bit 8)                                   */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO8_Msk (0x100UL)                /*!< DSP0N1GPIO8 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO7_Pos (7UL)                    /*!< DSP0N1GPIO7 (Bit 7)                                   */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO7_Msk (0x80UL)                 /*!< DSP0N1GPIO7 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO6_Pos (6UL)                    /*!< DSP0N1GPIO6 (Bit 6)                                   */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO6_Msk (0x40UL)                 /*!< DSP0N1GPIO6 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO5_Pos (5UL)                    /*!< DSP0N1GPIO5 (Bit 5)                                   */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO5_Msk (0x20UL)                 /*!< DSP0N1GPIO5 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO4_Pos (4UL)                    /*!< DSP0N1GPIO4 (Bit 4)                                   */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO4_Msk (0x10UL)                 /*!< DSP0N1GPIO4 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO3_Pos (3UL)                    /*!< DSP0N1GPIO3 (Bit 3)                                   */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO3_Msk (0x8UL)                  /*!< DSP0N1GPIO3 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO2_Pos (2UL)                    /*!< DSP0N1GPIO2 (Bit 2)                                   */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO2_Msk (0x4UL)                  /*!< DSP0N1GPIO2 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO1_Pos (1UL)                    /*!< DSP0N1GPIO1 (Bit 1)                                   */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO1_Msk (0x2UL)                  /*!< DSP0N1GPIO1 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO0_Pos (0UL)                    /*!< DSP0N1GPIO0 (Bit 0)                                   */
#define GPIO_DSP0N1INT0CLR_DSP0N1GPIO0_Msk (0x1UL)                  /*!< DSP0N1GPIO0 (Bitfield-Mask: 0x01)                     */
/* =====================================================  DSP0N1INT0SET  ===================================================== */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO31_Pos (31UL)                  /*!< DSP0N1GPIO31 (Bit 31)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO31_Msk (0x80000000UL)          /*!< DSP0N1GPIO31 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO30_Pos (30UL)                  /*!< DSP0N1GPIO30 (Bit 30)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO30_Msk (0x40000000UL)          /*!< DSP0N1GPIO30 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO29_Pos (29UL)                  /*!< DSP0N1GPIO29 (Bit 29)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO29_Msk (0x20000000UL)          /*!< DSP0N1GPIO29 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO28_Pos (28UL)                  /*!< DSP0N1GPIO28 (Bit 28)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO28_Msk (0x10000000UL)          /*!< DSP0N1GPIO28 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO27_Pos (27UL)                  /*!< DSP0N1GPIO27 (Bit 27)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO27_Msk (0x8000000UL)           /*!< DSP0N1GPIO27 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO26_Pos (26UL)                  /*!< DSP0N1GPIO26 (Bit 26)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO26_Msk (0x4000000UL)           /*!< DSP0N1GPIO26 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO25_Pos (25UL)                  /*!< DSP0N1GPIO25 (Bit 25)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO25_Msk (0x2000000UL)           /*!< DSP0N1GPIO25 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO24_Pos (24UL)                  /*!< DSP0N1GPIO24 (Bit 24)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO24_Msk (0x1000000UL)           /*!< DSP0N1GPIO24 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO23_Pos (23UL)                  /*!< DSP0N1GPIO23 (Bit 23)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO23_Msk (0x800000UL)            /*!< DSP0N1GPIO23 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO22_Pos (22UL)                  /*!< DSP0N1GPIO22 (Bit 22)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO22_Msk (0x400000UL)            /*!< DSP0N1GPIO22 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO21_Pos (21UL)                  /*!< DSP0N1GPIO21 (Bit 21)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO21_Msk (0x200000UL)            /*!< DSP0N1GPIO21 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO20_Pos (20UL)                  /*!< DSP0N1GPIO20 (Bit 20)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO20_Msk (0x100000UL)            /*!< DSP0N1GPIO20 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO19_Pos (19UL)                  /*!< DSP0N1GPIO19 (Bit 19)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO19_Msk (0x80000UL)             /*!< DSP0N1GPIO19 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO18_Pos (18UL)                  /*!< DSP0N1GPIO18 (Bit 18)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO18_Msk (0x40000UL)             /*!< DSP0N1GPIO18 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO17_Pos (17UL)                  /*!< DSP0N1GPIO17 (Bit 17)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO17_Msk (0x20000UL)             /*!< DSP0N1GPIO17 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO16_Pos (16UL)                  /*!< DSP0N1GPIO16 (Bit 16)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO16_Msk (0x10000UL)             /*!< DSP0N1GPIO16 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO15_Pos (15UL)                  /*!< DSP0N1GPIO15 (Bit 15)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO15_Msk (0x8000UL)              /*!< DSP0N1GPIO15 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO14_Pos (14UL)                  /*!< DSP0N1GPIO14 (Bit 14)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO14_Msk (0x4000UL)              /*!< DSP0N1GPIO14 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO13_Pos (13UL)                  /*!< DSP0N1GPIO13 (Bit 13)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO13_Msk (0x2000UL)              /*!< DSP0N1GPIO13 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO12_Pos (12UL)                  /*!< DSP0N1GPIO12 (Bit 12)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO12_Msk (0x1000UL)              /*!< DSP0N1GPIO12 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO11_Pos (11UL)                  /*!< DSP0N1GPIO11 (Bit 11)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO11_Msk (0x800UL)               /*!< DSP0N1GPIO11 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO10_Pos (10UL)                  /*!< DSP0N1GPIO10 (Bit 10)                                 */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO10_Msk (0x400UL)               /*!< DSP0N1GPIO10 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO9_Pos (9UL)                    /*!< DSP0N1GPIO9 (Bit 9)                                   */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO9_Msk (0x200UL)                /*!< DSP0N1GPIO9 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO8_Pos (8UL)                    /*!< DSP0N1GPIO8 (Bit 8)                                   */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO8_Msk (0x100UL)                /*!< DSP0N1GPIO8 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO7_Pos (7UL)                    /*!< DSP0N1GPIO7 (Bit 7)                                   */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO7_Msk (0x80UL)                 /*!< DSP0N1GPIO7 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO6_Pos (6UL)                    /*!< DSP0N1GPIO6 (Bit 6)                                   */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO6_Msk (0x40UL)                 /*!< DSP0N1GPIO6 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO5_Pos (5UL)                    /*!< DSP0N1GPIO5 (Bit 5)                                   */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO5_Msk (0x20UL)                 /*!< DSP0N1GPIO5 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO4_Pos (4UL)                    /*!< DSP0N1GPIO4 (Bit 4)                                   */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO4_Msk (0x10UL)                 /*!< DSP0N1GPIO4 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO3_Pos (3UL)                    /*!< DSP0N1GPIO3 (Bit 3)                                   */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO3_Msk (0x8UL)                  /*!< DSP0N1GPIO3 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO2_Pos (2UL)                    /*!< DSP0N1GPIO2 (Bit 2)                                   */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO2_Msk (0x4UL)                  /*!< DSP0N1GPIO2 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO1_Pos (1UL)                    /*!< DSP0N1GPIO1 (Bit 1)                                   */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO1_Msk (0x2UL)                  /*!< DSP0N1GPIO1 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO0_Pos (0UL)                    /*!< DSP0N1GPIO0 (Bit 0)                                   */
#define GPIO_DSP0N1INT0SET_DSP0N1GPIO0_Msk (0x1UL)                  /*!< DSP0N1GPIO0 (Bitfield-Mask: 0x01)                     */
/* =====================================================  DSP0N1INT1EN  ====================================================== */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO63_Pos (31UL)                   /*!< DSP0N1GPIO63 (Bit 31)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO63_Msk (0x80000000UL)           /*!< DSP0N1GPIO63 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO62_Pos (30UL)                   /*!< DSP0N1GPIO62 (Bit 30)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO62_Msk (0x40000000UL)           /*!< DSP0N1GPIO62 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO61_Pos (29UL)                   /*!< DSP0N1GPIO61 (Bit 29)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO61_Msk (0x20000000UL)           /*!< DSP0N1GPIO61 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO60_Pos (28UL)                   /*!< DSP0N1GPIO60 (Bit 28)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO60_Msk (0x10000000UL)           /*!< DSP0N1GPIO60 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO59_Pos (27UL)                   /*!< DSP0N1GPIO59 (Bit 27)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO59_Msk (0x8000000UL)            /*!< DSP0N1GPIO59 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO58_Pos (26UL)                   /*!< DSP0N1GPIO58 (Bit 26)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO58_Msk (0x4000000UL)            /*!< DSP0N1GPIO58 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO57_Pos (25UL)                   /*!< DSP0N1GPIO57 (Bit 25)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO57_Msk (0x2000000UL)            /*!< DSP0N1GPIO57 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO56_Pos (24UL)                   /*!< DSP0N1GPIO56 (Bit 24)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO56_Msk (0x1000000UL)            /*!< DSP0N1GPIO56 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO55_Pos (23UL)                   /*!< DSP0N1GPIO55 (Bit 23)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO55_Msk (0x800000UL)             /*!< DSP0N1GPIO55 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO54_Pos (22UL)                   /*!< DSP0N1GPIO54 (Bit 22)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO54_Msk (0x400000UL)             /*!< DSP0N1GPIO54 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO53_Pos (21UL)                   /*!< DSP0N1GPIO53 (Bit 21)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO53_Msk (0x200000UL)             /*!< DSP0N1GPIO53 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO52_Pos (20UL)                   /*!< DSP0N1GPIO52 (Bit 20)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO52_Msk (0x100000UL)             /*!< DSP0N1GPIO52 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO51_Pos (19UL)                   /*!< DSP0N1GPIO51 (Bit 19)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO51_Msk (0x80000UL)              /*!< DSP0N1GPIO51 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO50_Pos (18UL)                   /*!< DSP0N1GPIO50 (Bit 18)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO50_Msk (0x40000UL)              /*!< DSP0N1GPIO50 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO49_Pos (17UL)                   /*!< DSP0N1GPIO49 (Bit 17)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO49_Msk (0x20000UL)              /*!< DSP0N1GPIO49 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO48_Pos (16UL)                   /*!< DSP0N1GPIO48 (Bit 16)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO48_Msk (0x10000UL)              /*!< DSP0N1GPIO48 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO47_Pos (15UL)                   /*!< DSP0N1GPIO47 (Bit 15)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO47_Msk (0x8000UL)               /*!< DSP0N1GPIO47 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO46_Pos (14UL)                   /*!< DSP0N1GPIO46 (Bit 14)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO46_Msk (0x4000UL)               /*!< DSP0N1GPIO46 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO45_Pos (13UL)                   /*!< DSP0N1GPIO45 (Bit 13)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO45_Msk (0x2000UL)               /*!< DSP0N1GPIO45 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO44_Pos (12UL)                   /*!< DSP0N1GPIO44 (Bit 12)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO44_Msk (0x1000UL)               /*!< DSP0N1GPIO44 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO43_Pos (11UL)                   /*!< DSP0N1GPIO43 (Bit 11)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO43_Msk (0x800UL)                /*!< DSP0N1GPIO43 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO42_Pos (10UL)                   /*!< DSP0N1GPIO42 (Bit 10)                                 */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO42_Msk (0x400UL)                /*!< DSP0N1GPIO42 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO41_Pos (9UL)                    /*!< DSP0N1GPIO41 (Bit 9)                                  */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO41_Msk (0x200UL)                /*!< DSP0N1GPIO41 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO40_Pos (8UL)                    /*!< DSP0N1GPIO40 (Bit 8)                                  */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO40_Msk (0x100UL)                /*!< DSP0N1GPIO40 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO39_Pos (7UL)                    /*!< DSP0N1GPIO39 (Bit 7)                                  */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO39_Msk (0x80UL)                 /*!< DSP0N1GPIO39 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO38_Pos (6UL)                    /*!< DSP0N1GPIO38 (Bit 6)                                  */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO38_Msk (0x40UL)                 /*!< DSP0N1GPIO38 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO37_Pos (5UL)                    /*!< DSP0N1GPIO37 (Bit 5)                                  */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO37_Msk (0x20UL)                 /*!< DSP0N1GPIO37 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO36_Pos (4UL)                    /*!< DSP0N1GPIO36 (Bit 4)                                  */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO36_Msk (0x10UL)                 /*!< DSP0N1GPIO36 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO35_Pos (3UL)                    /*!< DSP0N1GPIO35 (Bit 3)                                  */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO35_Msk (0x8UL)                  /*!< DSP0N1GPIO35 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO34_Pos (2UL)                    /*!< DSP0N1GPIO34 (Bit 2)                                  */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO34_Msk (0x4UL)                  /*!< DSP0N1GPIO34 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO33_Pos (1UL)                    /*!< DSP0N1GPIO33 (Bit 1)                                  */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO33_Msk (0x2UL)                  /*!< DSP0N1GPIO33 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO32_Pos (0UL)                    /*!< DSP0N1GPIO32 (Bit 0)                                  */
#define GPIO_DSP0N1INT1EN_DSP0N1GPIO32_Msk (0x1UL)                  /*!< DSP0N1GPIO32 (Bitfield-Mask: 0x01)                    */
/* ====================================================  DSP0N1INT1STAT  ===================================================== */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO63_Pos (31UL)                 /*!< DSP0N1GPIO63 (Bit 31)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO63_Msk (0x80000000UL)         /*!< DSP0N1GPIO63 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO62_Pos (30UL)                 /*!< DSP0N1GPIO62 (Bit 30)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO62_Msk (0x40000000UL)         /*!< DSP0N1GPIO62 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO61_Pos (29UL)                 /*!< DSP0N1GPIO61 (Bit 29)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO61_Msk (0x20000000UL)         /*!< DSP0N1GPIO61 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO60_Pos (28UL)                 /*!< DSP0N1GPIO60 (Bit 28)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO60_Msk (0x10000000UL)         /*!< DSP0N1GPIO60 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO59_Pos (27UL)                 /*!< DSP0N1GPIO59 (Bit 27)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO59_Msk (0x8000000UL)          /*!< DSP0N1GPIO59 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO58_Pos (26UL)                 /*!< DSP0N1GPIO58 (Bit 26)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO58_Msk (0x4000000UL)          /*!< DSP0N1GPIO58 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO57_Pos (25UL)                 /*!< DSP0N1GPIO57 (Bit 25)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO57_Msk (0x2000000UL)          /*!< DSP0N1GPIO57 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO56_Pos (24UL)                 /*!< DSP0N1GPIO56 (Bit 24)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO56_Msk (0x1000000UL)          /*!< DSP0N1GPIO56 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO55_Pos (23UL)                 /*!< DSP0N1GPIO55 (Bit 23)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO55_Msk (0x800000UL)           /*!< DSP0N1GPIO55 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO54_Pos (22UL)                 /*!< DSP0N1GPIO54 (Bit 22)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO54_Msk (0x400000UL)           /*!< DSP0N1GPIO54 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO53_Pos (21UL)                 /*!< DSP0N1GPIO53 (Bit 21)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO53_Msk (0x200000UL)           /*!< DSP0N1GPIO53 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO52_Pos (20UL)                 /*!< DSP0N1GPIO52 (Bit 20)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO52_Msk (0x100000UL)           /*!< DSP0N1GPIO52 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO51_Pos (19UL)                 /*!< DSP0N1GPIO51 (Bit 19)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO51_Msk (0x80000UL)            /*!< DSP0N1GPIO51 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO50_Pos (18UL)                 /*!< DSP0N1GPIO50 (Bit 18)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO50_Msk (0x40000UL)            /*!< DSP0N1GPIO50 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO49_Pos (17UL)                 /*!< DSP0N1GPIO49 (Bit 17)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO49_Msk (0x20000UL)            /*!< DSP0N1GPIO49 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO48_Pos (16UL)                 /*!< DSP0N1GPIO48 (Bit 16)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO48_Msk (0x10000UL)            /*!< DSP0N1GPIO48 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO47_Pos (15UL)                 /*!< DSP0N1GPIO47 (Bit 15)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO47_Msk (0x8000UL)             /*!< DSP0N1GPIO47 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO46_Pos (14UL)                 /*!< DSP0N1GPIO46 (Bit 14)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO46_Msk (0x4000UL)             /*!< DSP0N1GPIO46 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO45_Pos (13UL)                 /*!< DSP0N1GPIO45 (Bit 13)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO45_Msk (0x2000UL)             /*!< DSP0N1GPIO45 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO44_Pos (12UL)                 /*!< DSP0N1GPIO44 (Bit 12)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO44_Msk (0x1000UL)             /*!< DSP0N1GPIO44 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO43_Pos (11UL)                 /*!< DSP0N1GPIO43 (Bit 11)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO43_Msk (0x800UL)              /*!< DSP0N1GPIO43 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO42_Pos (10UL)                 /*!< DSP0N1GPIO42 (Bit 10)                                 */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO42_Msk (0x400UL)              /*!< DSP0N1GPIO42 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO41_Pos (9UL)                  /*!< DSP0N1GPIO41 (Bit 9)                                  */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO41_Msk (0x200UL)              /*!< DSP0N1GPIO41 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO40_Pos (8UL)                  /*!< DSP0N1GPIO40 (Bit 8)                                  */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO40_Msk (0x100UL)              /*!< DSP0N1GPIO40 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO39_Pos (7UL)                  /*!< DSP0N1GPIO39 (Bit 7)                                  */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO39_Msk (0x80UL)               /*!< DSP0N1GPIO39 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO38_Pos (6UL)                  /*!< DSP0N1GPIO38 (Bit 6)                                  */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO38_Msk (0x40UL)               /*!< DSP0N1GPIO38 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO37_Pos (5UL)                  /*!< DSP0N1GPIO37 (Bit 5)                                  */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO37_Msk (0x20UL)               /*!< DSP0N1GPIO37 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO36_Pos (4UL)                  /*!< DSP0N1GPIO36 (Bit 4)                                  */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO36_Msk (0x10UL)               /*!< DSP0N1GPIO36 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO35_Pos (3UL)                  /*!< DSP0N1GPIO35 (Bit 3)                                  */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO35_Msk (0x8UL)                /*!< DSP0N1GPIO35 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO34_Pos (2UL)                  /*!< DSP0N1GPIO34 (Bit 2)                                  */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO34_Msk (0x4UL)                /*!< DSP0N1GPIO34 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO33_Pos (1UL)                  /*!< DSP0N1GPIO33 (Bit 1)                                  */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO33_Msk (0x2UL)                /*!< DSP0N1GPIO33 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO32_Pos (0UL)                  /*!< DSP0N1GPIO32 (Bit 0)                                  */
#define GPIO_DSP0N1INT1STAT_DSP0N1GPIO32_Msk (0x1UL)                /*!< DSP0N1GPIO32 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0N1INT1CLR  ===================================================== */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO63_Pos (31UL)                  /*!< DSP0N1GPIO63 (Bit 31)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO63_Msk (0x80000000UL)          /*!< DSP0N1GPIO63 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO62_Pos (30UL)                  /*!< DSP0N1GPIO62 (Bit 30)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO62_Msk (0x40000000UL)          /*!< DSP0N1GPIO62 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO61_Pos (29UL)                  /*!< DSP0N1GPIO61 (Bit 29)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO61_Msk (0x20000000UL)          /*!< DSP0N1GPIO61 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO60_Pos (28UL)                  /*!< DSP0N1GPIO60 (Bit 28)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO60_Msk (0x10000000UL)          /*!< DSP0N1GPIO60 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO59_Pos (27UL)                  /*!< DSP0N1GPIO59 (Bit 27)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO59_Msk (0x8000000UL)           /*!< DSP0N1GPIO59 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO58_Pos (26UL)                  /*!< DSP0N1GPIO58 (Bit 26)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO58_Msk (0x4000000UL)           /*!< DSP0N1GPIO58 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO57_Pos (25UL)                  /*!< DSP0N1GPIO57 (Bit 25)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO57_Msk (0x2000000UL)           /*!< DSP0N1GPIO57 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO56_Pos (24UL)                  /*!< DSP0N1GPIO56 (Bit 24)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO56_Msk (0x1000000UL)           /*!< DSP0N1GPIO56 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO55_Pos (23UL)                  /*!< DSP0N1GPIO55 (Bit 23)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO55_Msk (0x800000UL)            /*!< DSP0N1GPIO55 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO54_Pos (22UL)                  /*!< DSP0N1GPIO54 (Bit 22)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO54_Msk (0x400000UL)            /*!< DSP0N1GPIO54 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO53_Pos (21UL)                  /*!< DSP0N1GPIO53 (Bit 21)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO53_Msk (0x200000UL)            /*!< DSP0N1GPIO53 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO52_Pos (20UL)                  /*!< DSP0N1GPIO52 (Bit 20)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO52_Msk (0x100000UL)            /*!< DSP0N1GPIO52 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO51_Pos (19UL)                  /*!< DSP0N1GPIO51 (Bit 19)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO51_Msk (0x80000UL)             /*!< DSP0N1GPIO51 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO50_Pos (18UL)                  /*!< DSP0N1GPIO50 (Bit 18)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO50_Msk (0x40000UL)             /*!< DSP0N1GPIO50 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO49_Pos (17UL)                  /*!< DSP0N1GPIO49 (Bit 17)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO49_Msk (0x20000UL)             /*!< DSP0N1GPIO49 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO48_Pos (16UL)                  /*!< DSP0N1GPIO48 (Bit 16)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO48_Msk (0x10000UL)             /*!< DSP0N1GPIO48 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO47_Pos (15UL)                  /*!< DSP0N1GPIO47 (Bit 15)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO47_Msk (0x8000UL)              /*!< DSP0N1GPIO47 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO46_Pos (14UL)                  /*!< DSP0N1GPIO46 (Bit 14)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO46_Msk (0x4000UL)              /*!< DSP0N1GPIO46 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO45_Pos (13UL)                  /*!< DSP0N1GPIO45 (Bit 13)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO45_Msk (0x2000UL)              /*!< DSP0N1GPIO45 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO44_Pos (12UL)                  /*!< DSP0N1GPIO44 (Bit 12)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO44_Msk (0x1000UL)              /*!< DSP0N1GPIO44 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO43_Pos (11UL)                  /*!< DSP0N1GPIO43 (Bit 11)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO43_Msk (0x800UL)               /*!< DSP0N1GPIO43 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO42_Pos (10UL)                  /*!< DSP0N1GPIO42 (Bit 10)                                 */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO42_Msk (0x400UL)               /*!< DSP0N1GPIO42 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO41_Pos (9UL)                   /*!< DSP0N1GPIO41 (Bit 9)                                  */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO41_Msk (0x200UL)               /*!< DSP0N1GPIO41 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO40_Pos (8UL)                   /*!< DSP0N1GPIO40 (Bit 8)                                  */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO40_Msk (0x100UL)               /*!< DSP0N1GPIO40 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO39_Pos (7UL)                   /*!< DSP0N1GPIO39 (Bit 7)                                  */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO39_Msk (0x80UL)                /*!< DSP0N1GPIO39 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO38_Pos (6UL)                   /*!< DSP0N1GPIO38 (Bit 6)                                  */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO38_Msk (0x40UL)                /*!< DSP0N1GPIO38 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO37_Pos (5UL)                   /*!< DSP0N1GPIO37 (Bit 5)                                  */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO37_Msk (0x20UL)                /*!< DSP0N1GPIO37 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO36_Pos (4UL)                   /*!< DSP0N1GPIO36 (Bit 4)                                  */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO36_Msk (0x10UL)                /*!< DSP0N1GPIO36 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO35_Pos (3UL)                   /*!< DSP0N1GPIO35 (Bit 3)                                  */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO35_Msk (0x8UL)                 /*!< DSP0N1GPIO35 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO34_Pos (2UL)                   /*!< DSP0N1GPIO34 (Bit 2)                                  */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO34_Msk (0x4UL)                 /*!< DSP0N1GPIO34 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO33_Pos (1UL)                   /*!< DSP0N1GPIO33 (Bit 1)                                  */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO33_Msk (0x2UL)                 /*!< DSP0N1GPIO33 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO32_Pos (0UL)                   /*!< DSP0N1GPIO32 (Bit 0)                                  */
#define GPIO_DSP0N1INT1CLR_DSP0N1GPIO32_Msk (0x1UL)                 /*!< DSP0N1GPIO32 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0N1INT1SET  ===================================================== */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO63_Pos (31UL)                  /*!< DSP0N1GPIO63 (Bit 31)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO63_Msk (0x80000000UL)          /*!< DSP0N1GPIO63 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO62_Pos (30UL)                  /*!< DSP0N1GPIO62 (Bit 30)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO62_Msk (0x40000000UL)          /*!< DSP0N1GPIO62 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO61_Pos (29UL)                  /*!< DSP0N1GPIO61 (Bit 29)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO61_Msk (0x20000000UL)          /*!< DSP0N1GPIO61 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO60_Pos (28UL)                  /*!< DSP0N1GPIO60 (Bit 28)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO60_Msk (0x10000000UL)          /*!< DSP0N1GPIO60 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO59_Pos (27UL)                  /*!< DSP0N1GPIO59 (Bit 27)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO59_Msk (0x8000000UL)           /*!< DSP0N1GPIO59 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO58_Pos (26UL)                  /*!< DSP0N1GPIO58 (Bit 26)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO58_Msk (0x4000000UL)           /*!< DSP0N1GPIO58 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO57_Pos (25UL)                  /*!< DSP0N1GPIO57 (Bit 25)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO57_Msk (0x2000000UL)           /*!< DSP0N1GPIO57 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO56_Pos (24UL)                  /*!< DSP0N1GPIO56 (Bit 24)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO56_Msk (0x1000000UL)           /*!< DSP0N1GPIO56 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO55_Pos (23UL)                  /*!< DSP0N1GPIO55 (Bit 23)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO55_Msk (0x800000UL)            /*!< DSP0N1GPIO55 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO54_Pos (22UL)                  /*!< DSP0N1GPIO54 (Bit 22)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO54_Msk (0x400000UL)            /*!< DSP0N1GPIO54 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO53_Pos (21UL)                  /*!< DSP0N1GPIO53 (Bit 21)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO53_Msk (0x200000UL)            /*!< DSP0N1GPIO53 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO52_Pos (20UL)                  /*!< DSP0N1GPIO52 (Bit 20)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO52_Msk (0x100000UL)            /*!< DSP0N1GPIO52 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO51_Pos (19UL)                  /*!< DSP0N1GPIO51 (Bit 19)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO51_Msk (0x80000UL)             /*!< DSP0N1GPIO51 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO50_Pos (18UL)                  /*!< DSP0N1GPIO50 (Bit 18)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO50_Msk (0x40000UL)             /*!< DSP0N1GPIO50 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO49_Pos (17UL)                  /*!< DSP0N1GPIO49 (Bit 17)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO49_Msk (0x20000UL)             /*!< DSP0N1GPIO49 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO48_Pos (16UL)                  /*!< DSP0N1GPIO48 (Bit 16)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO48_Msk (0x10000UL)             /*!< DSP0N1GPIO48 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO47_Pos (15UL)                  /*!< DSP0N1GPIO47 (Bit 15)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO47_Msk (0x8000UL)              /*!< DSP0N1GPIO47 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO46_Pos (14UL)                  /*!< DSP0N1GPIO46 (Bit 14)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO46_Msk (0x4000UL)              /*!< DSP0N1GPIO46 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO45_Pos (13UL)                  /*!< DSP0N1GPIO45 (Bit 13)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO45_Msk (0x2000UL)              /*!< DSP0N1GPIO45 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO44_Pos (12UL)                  /*!< DSP0N1GPIO44 (Bit 12)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO44_Msk (0x1000UL)              /*!< DSP0N1GPIO44 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO43_Pos (11UL)                  /*!< DSP0N1GPIO43 (Bit 11)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO43_Msk (0x800UL)               /*!< DSP0N1GPIO43 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO42_Pos (10UL)                  /*!< DSP0N1GPIO42 (Bit 10)                                 */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO42_Msk (0x400UL)               /*!< DSP0N1GPIO42 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO41_Pos (9UL)                   /*!< DSP0N1GPIO41 (Bit 9)                                  */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO41_Msk (0x200UL)               /*!< DSP0N1GPIO41 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO40_Pos (8UL)                   /*!< DSP0N1GPIO40 (Bit 8)                                  */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO40_Msk (0x100UL)               /*!< DSP0N1GPIO40 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO39_Pos (7UL)                   /*!< DSP0N1GPIO39 (Bit 7)                                  */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO39_Msk (0x80UL)                /*!< DSP0N1GPIO39 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO38_Pos (6UL)                   /*!< DSP0N1GPIO38 (Bit 6)                                  */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO38_Msk (0x40UL)                /*!< DSP0N1GPIO38 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO37_Pos (5UL)                   /*!< DSP0N1GPIO37 (Bit 5)                                  */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO37_Msk (0x20UL)                /*!< DSP0N1GPIO37 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO36_Pos (4UL)                   /*!< DSP0N1GPIO36 (Bit 4)                                  */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO36_Msk (0x10UL)                /*!< DSP0N1GPIO36 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO35_Pos (3UL)                   /*!< DSP0N1GPIO35 (Bit 3)                                  */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO35_Msk (0x8UL)                 /*!< DSP0N1GPIO35 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO34_Pos (2UL)                   /*!< DSP0N1GPIO34 (Bit 2)                                  */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO34_Msk (0x4UL)                 /*!< DSP0N1GPIO34 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO33_Pos (1UL)                   /*!< DSP0N1GPIO33 (Bit 1)                                  */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO33_Msk (0x2UL)                 /*!< DSP0N1GPIO33 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO32_Pos (0UL)                   /*!< DSP0N1GPIO32 (Bit 0)                                  */
#define GPIO_DSP0N1INT1SET_DSP0N1GPIO32_Msk (0x1UL)                 /*!< DSP0N1GPIO32 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0N1INT2EN  ====================================================== */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO95_Pos (31UL)                   /*!< DSP0N1GPIO95 (Bit 31)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO95_Msk (0x80000000UL)           /*!< DSP0N1GPIO95 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO94_Pos (30UL)                   /*!< DSP0N1GPIO94 (Bit 30)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO94_Msk (0x40000000UL)           /*!< DSP0N1GPIO94 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO93_Pos (29UL)                   /*!< DSP0N1GPIO93 (Bit 29)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO93_Msk (0x20000000UL)           /*!< DSP0N1GPIO93 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO92_Pos (28UL)                   /*!< DSP0N1GPIO92 (Bit 28)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO92_Msk (0x10000000UL)           /*!< DSP0N1GPIO92 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO91_Pos (27UL)                   /*!< DSP0N1GPIO91 (Bit 27)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO91_Msk (0x8000000UL)            /*!< DSP0N1GPIO91 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO90_Pos (26UL)                   /*!< DSP0N1GPIO90 (Bit 26)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO90_Msk (0x4000000UL)            /*!< DSP0N1GPIO90 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO89_Pos (25UL)                   /*!< DSP0N1GPIO89 (Bit 25)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO89_Msk (0x2000000UL)            /*!< DSP0N1GPIO89 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO88_Pos (24UL)                   /*!< DSP0N1GPIO88 (Bit 24)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO88_Msk (0x1000000UL)            /*!< DSP0N1GPIO88 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO87_Pos (23UL)                   /*!< DSP0N1GPIO87 (Bit 23)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO87_Msk (0x800000UL)             /*!< DSP0N1GPIO87 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO86_Pos (22UL)                   /*!< DSP0N1GPIO86 (Bit 22)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO86_Msk (0x400000UL)             /*!< DSP0N1GPIO86 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO85_Pos (21UL)                   /*!< DSP0N1GPIO85 (Bit 21)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO85_Msk (0x200000UL)             /*!< DSP0N1GPIO85 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO84_Pos (20UL)                   /*!< DSP0N1GPIO84 (Bit 20)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO84_Msk (0x100000UL)             /*!< DSP0N1GPIO84 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO83_Pos (19UL)                   /*!< DSP0N1GPIO83 (Bit 19)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO83_Msk (0x80000UL)              /*!< DSP0N1GPIO83 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO82_Pos (18UL)                   /*!< DSP0N1GPIO82 (Bit 18)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO82_Msk (0x40000UL)              /*!< DSP0N1GPIO82 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO81_Pos (17UL)                   /*!< DSP0N1GPIO81 (Bit 17)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO81_Msk (0x20000UL)              /*!< DSP0N1GPIO81 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO80_Pos (16UL)                   /*!< DSP0N1GPIO80 (Bit 16)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO80_Msk (0x10000UL)              /*!< DSP0N1GPIO80 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO79_Pos (15UL)                   /*!< DSP0N1GPIO79 (Bit 15)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO79_Msk (0x8000UL)               /*!< DSP0N1GPIO79 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO78_Pos (14UL)                   /*!< DSP0N1GPIO78 (Bit 14)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO78_Msk (0x4000UL)               /*!< DSP0N1GPIO78 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO77_Pos (13UL)                   /*!< DSP0N1GPIO77 (Bit 13)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO77_Msk (0x2000UL)               /*!< DSP0N1GPIO77 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO76_Pos (12UL)                   /*!< DSP0N1GPIO76 (Bit 12)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO76_Msk (0x1000UL)               /*!< DSP0N1GPIO76 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO75_Pos (11UL)                   /*!< DSP0N1GPIO75 (Bit 11)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO75_Msk (0x800UL)                /*!< DSP0N1GPIO75 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO74_Pos (10UL)                   /*!< DSP0N1GPIO74 (Bit 10)                                 */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO74_Msk (0x400UL)                /*!< DSP0N1GPIO74 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO73_Pos (9UL)                    /*!< DSP0N1GPIO73 (Bit 9)                                  */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO73_Msk (0x200UL)                /*!< DSP0N1GPIO73 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO72_Pos (8UL)                    /*!< DSP0N1GPIO72 (Bit 8)                                  */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO72_Msk (0x100UL)                /*!< DSP0N1GPIO72 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO71_Pos (7UL)                    /*!< DSP0N1GPIO71 (Bit 7)                                  */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO71_Msk (0x80UL)                 /*!< DSP0N1GPIO71 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO70_Pos (6UL)                    /*!< DSP0N1GPIO70 (Bit 6)                                  */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO70_Msk (0x40UL)                 /*!< DSP0N1GPIO70 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO69_Pos (5UL)                    /*!< DSP0N1GPIO69 (Bit 5)                                  */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO69_Msk (0x20UL)                 /*!< DSP0N1GPIO69 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO68_Pos (4UL)                    /*!< DSP0N1GPIO68 (Bit 4)                                  */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO68_Msk (0x10UL)                 /*!< DSP0N1GPIO68 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO67_Pos (3UL)                    /*!< DSP0N1GPIO67 (Bit 3)                                  */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO67_Msk (0x8UL)                  /*!< DSP0N1GPIO67 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO66_Pos (2UL)                    /*!< DSP0N1GPIO66 (Bit 2)                                  */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO66_Msk (0x4UL)                  /*!< DSP0N1GPIO66 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO65_Pos (1UL)                    /*!< DSP0N1GPIO65 (Bit 1)                                  */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO65_Msk (0x2UL)                  /*!< DSP0N1GPIO65 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO64_Pos (0UL)                    /*!< DSP0N1GPIO64 (Bit 0)                                  */
#define GPIO_DSP0N1INT2EN_DSP0N1GPIO64_Msk (0x1UL)                  /*!< DSP0N1GPIO64 (Bitfield-Mask: 0x01)                    */
/* ====================================================  DSP0N1INT2STAT  ===================================================== */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO95_Pos (31UL)                 /*!< DSP0N1GPIO95 (Bit 31)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO95_Msk (0x80000000UL)         /*!< DSP0N1GPIO95 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO94_Pos (30UL)                 /*!< DSP0N1GPIO94 (Bit 30)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO94_Msk (0x40000000UL)         /*!< DSP0N1GPIO94 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO93_Pos (29UL)                 /*!< DSP0N1GPIO93 (Bit 29)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO93_Msk (0x20000000UL)         /*!< DSP0N1GPIO93 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO92_Pos (28UL)                 /*!< DSP0N1GPIO92 (Bit 28)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO92_Msk (0x10000000UL)         /*!< DSP0N1GPIO92 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO91_Pos (27UL)                 /*!< DSP0N1GPIO91 (Bit 27)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO91_Msk (0x8000000UL)          /*!< DSP0N1GPIO91 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO90_Pos (26UL)                 /*!< DSP0N1GPIO90 (Bit 26)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO90_Msk (0x4000000UL)          /*!< DSP0N1GPIO90 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO89_Pos (25UL)                 /*!< DSP0N1GPIO89 (Bit 25)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO89_Msk (0x2000000UL)          /*!< DSP0N1GPIO89 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO88_Pos (24UL)                 /*!< DSP0N1GPIO88 (Bit 24)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO88_Msk (0x1000000UL)          /*!< DSP0N1GPIO88 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO87_Pos (23UL)                 /*!< DSP0N1GPIO87 (Bit 23)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO87_Msk (0x800000UL)           /*!< DSP0N1GPIO87 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO86_Pos (22UL)                 /*!< DSP0N1GPIO86 (Bit 22)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO86_Msk (0x400000UL)           /*!< DSP0N1GPIO86 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO85_Pos (21UL)                 /*!< DSP0N1GPIO85 (Bit 21)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO85_Msk (0x200000UL)           /*!< DSP0N1GPIO85 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO84_Pos (20UL)                 /*!< DSP0N1GPIO84 (Bit 20)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO84_Msk (0x100000UL)           /*!< DSP0N1GPIO84 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO83_Pos (19UL)                 /*!< DSP0N1GPIO83 (Bit 19)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO83_Msk (0x80000UL)            /*!< DSP0N1GPIO83 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO82_Pos (18UL)                 /*!< DSP0N1GPIO82 (Bit 18)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO82_Msk (0x40000UL)            /*!< DSP0N1GPIO82 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO81_Pos (17UL)                 /*!< DSP0N1GPIO81 (Bit 17)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO81_Msk (0x20000UL)            /*!< DSP0N1GPIO81 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO80_Pos (16UL)                 /*!< DSP0N1GPIO80 (Bit 16)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO80_Msk (0x10000UL)            /*!< DSP0N1GPIO80 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO79_Pos (15UL)                 /*!< DSP0N1GPIO79 (Bit 15)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO79_Msk (0x8000UL)             /*!< DSP0N1GPIO79 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO78_Pos (14UL)                 /*!< DSP0N1GPIO78 (Bit 14)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO78_Msk (0x4000UL)             /*!< DSP0N1GPIO78 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO77_Pos (13UL)                 /*!< DSP0N1GPIO77 (Bit 13)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO77_Msk (0x2000UL)             /*!< DSP0N1GPIO77 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO76_Pos (12UL)                 /*!< DSP0N1GPIO76 (Bit 12)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO76_Msk (0x1000UL)             /*!< DSP0N1GPIO76 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO75_Pos (11UL)                 /*!< DSP0N1GPIO75 (Bit 11)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO75_Msk (0x800UL)              /*!< DSP0N1GPIO75 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO74_Pos (10UL)                 /*!< DSP0N1GPIO74 (Bit 10)                                 */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO74_Msk (0x400UL)              /*!< DSP0N1GPIO74 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO73_Pos (9UL)                  /*!< DSP0N1GPIO73 (Bit 9)                                  */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO73_Msk (0x200UL)              /*!< DSP0N1GPIO73 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO72_Pos (8UL)                  /*!< DSP0N1GPIO72 (Bit 8)                                  */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO72_Msk (0x100UL)              /*!< DSP0N1GPIO72 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO71_Pos (7UL)                  /*!< DSP0N1GPIO71 (Bit 7)                                  */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO71_Msk (0x80UL)               /*!< DSP0N1GPIO71 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO70_Pos (6UL)                  /*!< DSP0N1GPIO70 (Bit 6)                                  */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO70_Msk (0x40UL)               /*!< DSP0N1GPIO70 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO69_Pos (5UL)                  /*!< DSP0N1GPIO69 (Bit 5)                                  */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO69_Msk (0x20UL)               /*!< DSP0N1GPIO69 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO68_Pos (4UL)                  /*!< DSP0N1GPIO68 (Bit 4)                                  */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO68_Msk (0x10UL)               /*!< DSP0N1GPIO68 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO67_Pos (3UL)                  /*!< DSP0N1GPIO67 (Bit 3)                                  */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO67_Msk (0x8UL)                /*!< DSP0N1GPIO67 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO66_Pos (2UL)                  /*!< DSP0N1GPIO66 (Bit 2)                                  */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO66_Msk (0x4UL)                /*!< DSP0N1GPIO66 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO65_Pos (1UL)                  /*!< DSP0N1GPIO65 (Bit 1)                                  */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO65_Msk (0x2UL)                /*!< DSP0N1GPIO65 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO64_Pos (0UL)                  /*!< DSP0N1GPIO64 (Bit 0)                                  */
#define GPIO_DSP0N1INT2STAT_DSP0N1GPIO64_Msk (0x1UL)                /*!< DSP0N1GPIO64 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0N1INT2CLR  ===================================================== */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO95_Pos (31UL)                  /*!< DSP0N1GPIO95 (Bit 31)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO95_Msk (0x80000000UL)          /*!< DSP0N1GPIO95 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO94_Pos (30UL)                  /*!< DSP0N1GPIO94 (Bit 30)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO94_Msk (0x40000000UL)          /*!< DSP0N1GPIO94 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO93_Pos (29UL)                  /*!< DSP0N1GPIO93 (Bit 29)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO93_Msk (0x20000000UL)          /*!< DSP0N1GPIO93 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO92_Pos (28UL)                  /*!< DSP0N1GPIO92 (Bit 28)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO92_Msk (0x10000000UL)          /*!< DSP0N1GPIO92 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO91_Pos (27UL)                  /*!< DSP0N1GPIO91 (Bit 27)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO91_Msk (0x8000000UL)           /*!< DSP0N1GPIO91 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO90_Pos (26UL)                  /*!< DSP0N1GPIO90 (Bit 26)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO90_Msk (0x4000000UL)           /*!< DSP0N1GPIO90 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO89_Pos (25UL)                  /*!< DSP0N1GPIO89 (Bit 25)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO89_Msk (0x2000000UL)           /*!< DSP0N1GPIO89 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO88_Pos (24UL)                  /*!< DSP0N1GPIO88 (Bit 24)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO88_Msk (0x1000000UL)           /*!< DSP0N1GPIO88 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO87_Pos (23UL)                  /*!< DSP0N1GPIO87 (Bit 23)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO87_Msk (0x800000UL)            /*!< DSP0N1GPIO87 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO86_Pos (22UL)                  /*!< DSP0N1GPIO86 (Bit 22)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO86_Msk (0x400000UL)            /*!< DSP0N1GPIO86 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO85_Pos (21UL)                  /*!< DSP0N1GPIO85 (Bit 21)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO85_Msk (0x200000UL)            /*!< DSP0N1GPIO85 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO84_Pos (20UL)                  /*!< DSP0N1GPIO84 (Bit 20)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO84_Msk (0x100000UL)            /*!< DSP0N1GPIO84 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO83_Pos (19UL)                  /*!< DSP0N1GPIO83 (Bit 19)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO83_Msk (0x80000UL)             /*!< DSP0N1GPIO83 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO82_Pos (18UL)                  /*!< DSP0N1GPIO82 (Bit 18)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO82_Msk (0x40000UL)             /*!< DSP0N1GPIO82 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO81_Pos (17UL)                  /*!< DSP0N1GPIO81 (Bit 17)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO81_Msk (0x20000UL)             /*!< DSP0N1GPIO81 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO80_Pos (16UL)                  /*!< DSP0N1GPIO80 (Bit 16)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO80_Msk (0x10000UL)             /*!< DSP0N1GPIO80 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO79_Pos (15UL)                  /*!< DSP0N1GPIO79 (Bit 15)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO79_Msk (0x8000UL)              /*!< DSP0N1GPIO79 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO78_Pos (14UL)                  /*!< DSP0N1GPIO78 (Bit 14)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO78_Msk (0x4000UL)              /*!< DSP0N1GPIO78 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO77_Pos (13UL)                  /*!< DSP0N1GPIO77 (Bit 13)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO77_Msk (0x2000UL)              /*!< DSP0N1GPIO77 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO76_Pos (12UL)                  /*!< DSP0N1GPIO76 (Bit 12)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO76_Msk (0x1000UL)              /*!< DSP0N1GPIO76 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO75_Pos (11UL)                  /*!< DSP0N1GPIO75 (Bit 11)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO75_Msk (0x800UL)               /*!< DSP0N1GPIO75 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO74_Pos (10UL)                  /*!< DSP0N1GPIO74 (Bit 10)                                 */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO74_Msk (0x400UL)               /*!< DSP0N1GPIO74 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO73_Pos (9UL)                   /*!< DSP0N1GPIO73 (Bit 9)                                  */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO73_Msk (0x200UL)               /*!< DSP0N1GPIO73 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO72_Pos (8UL)                   /*!< DSP0N1GPIO72 (Bit 8)                                  */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO72_Msk (0x100UL)               /*!< DSP0N1GPIO72 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO71_Pos (7UL)                   /*!< DSP0N1GPIO71 (Bit 7)                                  */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO71_Msk (0x80UL)                /*!< DSP0N1GPIO71 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO70_Pos (6UL)                   /*!< DSP0N1GPIO70 (Bit 6)                                  */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO70_Msk (0x40UL)                /*!< DSP0N1GPIO70 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO69_Pos (5UL)                   /*!< DSP0N1GPIO69 (Bit 5)                                  */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO69_Msk (0x20UL)                /*!< DSP0N1GPIO69 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO68_Pos (4UL)                   /*!< DSP0N1GPIO68 (Bit 4)                                  */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO68_Msk (0x10UL)                /*!< DSP0N1GPIO68 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO67_Pos (3UL)                   /*!< DSP0N1GPIO67 (Bit 3)                                  */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO67_Msk (0x8UL)                 /*!< DSP0N1GPIO67 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO66_Pos (2UL)                   /*!< DSP0N1GPIO66 (Bit 2)                                  */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO66_Msk (0x4UL)                 /*!< DSP0N1GPIO66 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO65_Pos (1UL)                   /*!< DSP0N1GPIO65 (Bit 1)                                  */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO65_Msk (0x2UL)                 /*!< DSP0N1GPIO65 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO64_Pos (0UL)                   /*!< DSP0N1GPIO64 (Bit 0)                                  */
#define GPIO_DSP0N1INT2CLR_DSP0N1GPIO64_Msk (0x1UL)                 /*!< DSP0N1GPIO64 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0N1INT2SET  ===================================================== */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO95_Pos (31UL)                  /*!< DSP0N1GPIO95 (Bit 31)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO95_Msk (0x80000000UL)          /*!< DSP0N1GPIO95 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO94_Pos (30UL)                  /*!< DSP0N1GPIO94 (Bit 30)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO94_Msk (0x40000000UL)          /*!< DSP0N1GPIO94 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO93_Pos (29UL)                  /*!< DSP0N1GPIO93 (Bit 29)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO93_Msk (0x20000000UL)          /*!< DSP0N1GPIO93 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO92_Pos (28UL)                  /*!< DSP0N1GPIO92 (Bit 28)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO92_Msk (0x10000000UL)          /*!< DSP0N1GPIO92 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO91_Pos (27UL)                  /*!< DSP0N1GPIO91 (Bit 27)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO91_Msk (0x8000000UL)           /*!< DSP0N1GPIO91 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO90_Pos (26UL)                  /*!< DSP0N1GPIO90 (Bit 26)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO90_Msk (0x4000000UL)           /*!< DSP0N1GPIO90 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO89_Pos (25UL)                  /*!< DSP0N1GPIO89 (Bit 25)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO89_Msk (0x2000000UL)           /*!< DSP0N1GPIO89 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO88_Pos (24UL)                  /*!< DSP0N1GPIO88 (Bit 24)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO88_Msk (0x1000000UL)           /*!< DSP0N1GPIO88 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO87_Pos (23UL)                  /*!< DSP0N1GPIO87 (Bit 23)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO87_Msk (0x800000UL)            /*!< DSP0N1GPIO87 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO86_Pos (22UL)                  /*!< DSP0N1GPIO86 (Bit 22)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO86_Msk (0x400000UL)            /*!< DSP0N1GPIO86 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO85_Pos (21UL)                  /*!< DSP0N1GPIO85 (Bit 21)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO85_Msk (0x200000UL)            /*!< DSP0N1GPIO85 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO84_Pos (20UL)                  /*!< DSP0N1GPIO84 (Bit 20)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO84_Msk (0x100000UL)            /*!< DSP0N1GPIO84 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO83_Pos (19UL)                  /*!< DSP0N1GPIO83 (Bit 19)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO83_Msk (0x80000UL)             /*!< DSP0N1GPIO83 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO82_Pos (18UL)                  /*!< DSP0N1GPIO82 (Bit 18)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO82_Msk (0x40000UL)             /*!< DSP0N1GPIO82 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO81_Pos (17UL)                  /*!< DSP0N1GPIO81 (Bit 17)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO81_Msk (0x20000UL)             /*!< DSP0N1GPIO81 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO80_Pos (16UL)                  /*!< DSP0N1GPIO80 (Bit 16)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO80_Msk (0x10000UL)             /*!< DSP0N1GPIO80 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO79_Pos (15UL)                  /*!< DSP0N1GPIO79 (Bit 15)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO79_Msk (0x8000UL)              /*!< DSP0N1GPIO79 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO78_Pos (14UL)                  /*!< DSP0N1GPIO78 (Bit 14)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO78_Msk (0x4000UL)              /*!< DSP0N1GPIO78 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO77_Pos (13UL)                  /*!< DSP0N1GPIO77 (Bit 13)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO77_Msk (0x2000UL)              /*!< DSP0N1GPIO77 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO76_Pos (12UL)                  /*!< DSP0N1GPIO76 (Bit 12)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO76_Msk (0x1000UL)              /*!< DSP0N1GPIO76 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO75_Pos (11UL)                  /*!< DSP0N1GPIO75 (Bit 11)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO75_Msk (0x800UL)               /*!< DSP0N1GPIO75 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO74_Pos (10UL)                  /*!< DSP0N1GPIO74 (Bit 10)                                 */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO74_Msk (0x400UL)               /*!< DSP0N1GPIO74 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO73_Pos (9UL)                   /*!< DSP0N1GPIO73 (Bit 9)                                  */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO73_Msk (0x200UL)               /*!< DSP0N1GPIO73 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO72_Pos (8UL)                   /*!< DSP0N1GPIO72 (Bit 8)                                  */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO72_Msk (0x100UL)               /*!< DSP0N1GPIO72 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO71_Pos (7UL)                   /*!< DSP0N1GPIO71 (Bit 7)                                  */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO71_Msk (0x80UL)                /*!< DSP0N1GPIO71 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO70_Pos (6UL)                   /*!< DSP0N1GPIO70 (Bit 6)                                  */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO70_Msk (0x40UL)                /*!< DSP0N1GPIO70 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO69_Pos (5UL)                   /*!< DSP0N1GPIO69 (Bit 5)                                  */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO69_Msk (0x20UL)                /*!< DSP0N1GPIO69 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO68_Pos (4UL)                   /*!< DSP0N1GPIO68 (Bit 4)                                  */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO68_Msk (0x10UL)                /*!< DSP0N1GPIO68 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO67_Pos (3UL)                   /*!< DSP0N1GPIO67 (Bit 3)                                  */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO67_Msk (0x8UL)                 /*!< DSP0N1GPIO67 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO66_Pos (2UL)                   /*!< DSP0N1GPIO66 (Bit 2)                                  */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO66_Msk (0x4UL)                 /*!< DSP0N1GPIO66 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO65_Pos (1UL)                   /*!< DSP0N1GPIO65 (Bit 1)                                  */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO65_Msk (0x2UL)                 /*!< DSP0N1GPIO65 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO64_Pos (0UL)                   /*!< DSP0N1GPIO64 (Bit 0)                                  */
#define GPIO_DSP0N1INT2SET_DSP0N1GPIO64_Msk (0x1UL)                 /*!< DSP0N1GPIO64 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0N1INT3EN  ====================================================== */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO127_Pos (31UL)                  /*!< DSP0N1GPIO127 (Bit 31)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO127_Msk (0x80000000UL)          /*!< DSP0N1GPIO127 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO126_Pos (30UL)                  /*!< DSP0N1GPIO126 (Bit 30)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO126_Msk (0x40000000UL)          /*!< DSP0N1GPIO126 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO125_Pos (29UL)                  /*!< DSP0N1GPIO125 (Bit 29)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO125_Msk (0x20000000UL)          /*!< DSP0N1GPIO125 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO124_Pos (28UL)                  /*!< DSP0N1GPIO124 (Bit 28)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO124_Msk (0x10000000UL)          /*!< DSP0N1GPIO124 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO123_Pos (27UL)                  /*!< DSP0N1GPIO123 (Bit 27)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO123_Msk (0x8000000UL)           /*!< DSP0N1GPIO123 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO122_Pos (26UL)                  /*!< DSP0N1GPIO122 (Bit 26)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO122_Msk (0x4000000UL)           /*!< DSP0N1GPIO122 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO121_Pos (25UL)                  /*!< DSP0N1GPIO121 (Bit 25)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO121_Msk (0x2000000UL)           /*!< DSP0N1GPIO121 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO120_Pos (24UL)                  /*!< DSP0N1GPIO120 (Bit 24)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO120_Msk (0x1000000UL)           /*!< DSP0N1GPIO120 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO119_Pos (23UL)                  /*!< DSP0N1GPIO119 (Bit 23)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO119_Msk (0x800000UL)            /*!< DSP0N1GPIO119 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO118_Pos (22UL)                  /*!< DSP0N1GPIO118 (Bit 22)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO118_Msk (0x400000UL)            /*!< DSP0N1GPIO118 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO117_Pos (21UL)                  /*!< DSP0N1GPIO117 (Bit 21)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO117_Msk (0x200000UL)            /*!< DSP0N1GPIO117 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO116_Pos (20UL)                  /*!< DSP0N1GPIO116 (Bit 20)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO116_Msk (0x100000UL)            /*!< DSP0N1GPIO116 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO115_Pos (19UL)                  /*!< DSP0N1GPIO115 (Bit 19)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO115_Msk (0x80000UL)             /*!< DSP0N1GPIO115 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO114_Pos (18UL)                  /*!< DSP0N1GPIO114 (Bit 18)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO114_Msk (0x40000UL)             /*!< DSP0N1GPIO114 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO113_Pos (17UL)                  /*!< DSP0N1GPIO113 (Bit 17)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO113_Msk (0x20000UL)             /*!< DSP0N1GPIO113 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO112_Pos (16UL)                  /*!< DSP0N1GPIO112 (Bit 16)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO112_Msk (0x10000UL)             /*!< DSP0N1GPIO112 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO111_Pos (15UL)                  /*!< DSP0N1GPIO111 (Bit 15)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO111_Msk (0x8000UL)              /*!< DSP0N1GPIO111 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO110_Pos (14UL)                  /*!< DSP0N1GPIO110 (Bit 14)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO110_Msk (0x4000UL)              /*!< DSP0N1GPIO110 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO109_Pos (13UL)                  /*!< DSP0N1GPIO109 (Bit 13)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO109_Msk (0x2000UL)              /*!< DSP0N1GPIO109 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO108_Pos (12UL)                  /*!< DSP0N1GPIO108 (Bit 12)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO108_Msk (0x1000UL)              /*!< DSP0N1GPIO108 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO107_Pos (11UL)                  /*!< DSP0N1GPIO107 (Bit 11)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO107_Msk (0x800UL)               /*!< DSP0N1GPIO107 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO106_Pos (10UL)                  /*!< DSP0N1GPIO106 (Bit 10)                                */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO106_Msk (0x400UL)               /*!< DSP0N1GPIO106 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO105_Pos (9UL)                   /*!< DSP0N1GPIO105 (Bit 9)                                 */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO105_Msk (0x200UL)               /*!< DSP0N1GPIO105 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO104_Pos (8UL)                   /*!< DSP0N1GPIO104 (Bit 8)                                 */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO104_Msk (0x100UL)               /*!< DSP0N1GPIO104 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO103_Pos (7UL)                   /*!< DSP0N1GPIO103 (Bit 7)                                 */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO103_Msk (0x80UL)                /*!< DSP0N1GPIO103 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO102_Pos (6UL)                   /*!< DSP0N1GPIO102 (Bit 6)                                 */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO102_Msk (0x40UL)                /*!< DSP0N1GPIO102 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO101_Pos (5UL)                   /*!< DSP0N1GPIO101 (Bit 5)                                 */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO101_Msk (0x20UL)                /*!< DSP0N1GPIO101 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO100_Pos (4UL)                   /*!< DSP0N1GPIO100 (Bit 4)                                 */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO100_Msk (0x10UL)                /*!< DSP0N1GPIO100 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO99_Pos (3UL)                    /*!< DSP0N1GPIO99 (Bit 3)                                  */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO99_Msk (0x8UL)                  /*!< DSP0N1GPIO99 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO98_Pos (2UL)                    /*!< DSP0N1GPIO98 (Bit 2)                                  */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO98_Msk (0x4UL)                  /*!< DSP0N1GPIO98 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO97_Pos (1UL)                    /*!< DSP0N1GPIO97 (Bit 1)                                  */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO97_Msk (0x2UL)                  /*!< DSP0N1GPIO97 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO96_Pos (0UL)                    /*!< DSP0N1GPIO96 (Bit 0)                                  */
#define GPIO_DSP0N1INT3EN_DSP0N1GPIO96_Msk (0x1UL)                  /*!< DSP0N1GPIO96 (Bitfield-Mask: 0x01)                    */
/* ====================================================  DSP0N1INT3STAT  ===================================================== */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO127_Pos (31UL)                /*!< DSP0N1GPIO127 (Bit 31)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO127_Msk (0x80000000UL)        /*!< DSP0N1GPIO127 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO126_Pos (30UL)                /*!< DSP0N1GPIO126 (Bit 30)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO126_Msk (0x40000000UL)        /*!< DSP0N1GPIO126 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO125_Pos (29UL)                /*!< DSP0N1GPIO125 (Bit 29)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO125_Msk (0x20000000UL)        /*!< DSP0N1GPIO125 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO124_Pos (28UL)                /*!< DSP0N1GPIO124 (Bit 28)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO124_Msk (0x10000000UL)        /*!< DSP0N1GPIO124 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO123_Pos (27UL)                /*!< DSP0N1GPIO123 (Bit 27)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO123_Msk (0x8000000UL)         /*!< DSP0N1GPIO123 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO122_Pos (26UL)                /*!< DSP0N1GPIO122 (Bit 26)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO122_Msk (0x4000000UL)         /*!< DSP0N1GPIO122 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO121_Pos (25UL)                /*!< DSP0N1GPIO121 (Bit 25)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO121_Msk (0x2000000UL)         /*!< DSP0N1GPIO121 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO120_Pos (24UL)                /*!< DSP0N1GPIO120 (Bit 24)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO120_Msk (0x1000000UL)         /*!< DSP0N1GPIO120 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO119_Pos (23UL)                /*!< DSP0N1GPIO119 (Bit 23)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO119_Msk (0x800000UL)          /*!< DSP0N1GPIO119 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO118_Pos (22UL)                /*!< DSP0N1GPIO118 (Bit 22)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO118_Msk (0x400000UL)          /*!< DSP0N1GPIO118 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO117_Pos (21UL)                /*!< DSP0N1GPIO117 (Bit 21)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO117_Msk (0x200000UL)          /*!< DSP0N1GPIO117 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO116_Pos (20UL)                /*!< DSP0N1GPIO116 (Bit 20)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO116_Msk (0x100000UL)          /*!< DSP0N1GPIO116 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO115_Pos (19UL)                /*!< DSP0N1GPIO115 (Bit 19)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO115_Msk (0x80000UL)           /*!< DSP0N1GPIO115 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO114_Pos (18UL)                /*!< DSP0N1GPIO114 (Bit 18)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO114_Msk (0x40000UL)           /*!< DSP0N1GPIO114 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO113_Pos (17UL)                /*!< DSP0N1GPIO113 (Bit 17)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO113_Msk (0x20000UL)           /*!< DSP0N1GPIO113 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO112_Pos (16UL)                /*!< DSP0N1GPIO112 (Bit 16)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO112_Msk (0x10000UL)           /*!< DSP0N1GPIO112 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO111_Pos (15UL)                /*!< DSP0N1GPIO111 (Bit 15)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO111_Msk (0x8000UL)            /*!< DSP0N1GPIO111 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO110_Pos (14UL)                /*!< DSP0N1GPIO110 (Bit 14)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO110_Msk (0x4000UL)            /*!< DSP0N1GPIO110 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO109_Pos (13UL)                /*!< DSP0N1GPIO109 (Bit 13)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO109_Msk (0x2000UL)            /*!< DSP0N1GPIO109 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO108_Pos (12UL)                /*!< DSP0N1GPIO108 (Bit 12)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO108_Msk (0x1000UL)            /*!< DSP0N1GPIO108 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO107_Pos (11UL)                /*!< DSP0N1GPIO107 (Bit 11)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO107_Msk (0x800UL)             /*!< DSP0N1GPIO107 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO106_Pos (10UL)                /*!< DSP0N1GPIO106 (Bit 10)                                */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO106_Msk (0x400UL)             /*!< DSP0N1GPIO106 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO105_Pos (9UL)                 /*!< DSP0N1GPIO105 (Bit 9)                                 */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO105_Msk (0x200UL)             /*!< DSP0N1GPIO105 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO104_Pos (8UL)                 /*!< DSP0N1GPIO104 (Bit 8)                                 */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO104_Msk (0x100UL)             /*!< DSP0N1GPIO104 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO103_Pos (7UL)                 /*!< DSP0N1GPIO103 (Bit 7)                                 */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO103_Msk (0x80UL)              /*!< DSP0N1GPIO103 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO102_Pos (6UL)                 /*!< DSP0N1GPIO102 (Bit 6)                                 */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO102_Msk (0x40UL)              /*!< DSP0N1GPIO102 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO101_Pos (5UL)                 /*!< DSP0N1GPIO101 (Bit 5)                                 */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO101_Msk (0x20UL)              /*!< DSP0N1GPIO101 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO100_Pos (4UL)                 /*!< DSP0N1GPIO100 (Bit 4)                                 */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO100_Msk (0x10UL)              /*!< DSP0N1GPIO100 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO99_Pos (3UL)                  /*!< DSP0N1GPIO99 (Bit 3)                                  */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO99_Msk (0x8UL)                /*!< DSP0N1GPIO99 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO98_Pos (2UL)                  /*!< DSP0N1GPIO98 (Bit 2)                                  */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO98_Msk (0x4UL)                /*!< DSP0N1GPIO98 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO97_Pos (1UL)                  /*!< DSP0N1GPIO97 (Bit 1)                                  */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO97_Msk (0x2UL)                /*!< DSP0N1GPIO97 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO96_Pos (0UL)                  /*!< DSP0N1GPIO96 (Bit 0)                                  */
#define GPIO_DSP0N1INT3STAT_DSP0N1GPIO96_Msk (0x1UL)                /*!< DSP0N1GPIO96 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0N1INT3CLR  ===================================================== */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO127_Pos (31UL)                 /*!< DSP0N1GPIO127 (Bit 31)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO127_Msk (0x80000000UL)         /*!< DSP0N1GPIO127 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO126_Pos (30UL)                 /*!< DSP0N1GPIO126 (Bit 30)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO126_Msk (0x40000000UL)         /*!< DSP0N1GPIO126 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO125_Pos (29UL)                 /*!< DSP0N1GPIO125 (Bit 29)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO125_Msk (0x20000000UL)         /*!< DSP0N1GPIO125 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO124_Pos (28UL)                 /*!< DSP0N1GPIO124 (Bit 28)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO124_Msk (0x10000000UL)         /*!< DSP0N1GPIO124 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO123_Pos (27UL)                 /*!< DSP0N1GPIO123 (Bit 27)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO123_Msk (0x8000000UL)          /*!< DSP0N1GPIO123 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO122_Pos (26UL)                 /*!< DSP0N1GPIO122 (Bit 26)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO122_Msk (0x4000000UL)          /*!< DSP0N1GPIO122 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO121_Pos (25UL)                 /*!< DSP0N1GPIO121 (Bit 25)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO121_Msk (0x2000000UL)          /*!< DSP0N1GPIO121 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO120_Pos (24UL)                 /*!< DSP0N1GPIO120 (Bit 24)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO120_Msk (0x1000000UL)          /*!< DSP0N1GPIO120 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO119_Pos (23UL)                 /*!< DSP0N1GPIO119 (Bit 23)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO119_Msk (0x800000UL)           /*!< DSP0N1GPIO119 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO118_Pos (22UL)                 /*!< DSP0N1GPIO118 (Bit 22)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO118_Msk (0x400000UL)           /*!< DSP0N1GPIO118 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO117_Pos (21UL)                 /*!< DSP0N1GPIO117 (Bit 21)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO117_Msk (0x200000UL)           /*!< DSP0N1GPIO117 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO116_Pos (20UL)                 /*!< DSP0N1GPIO116 (Bit 20)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO116_Msk (0x100000UL)           /*!< DSP0N1GPIO116 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO115_Pos (19UL)                 /*!< DSP0N1GPIO115 (Bit 19)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO115_Msk (0x80000UL)            /*!< DSP0N1GPIO115 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO114_Pos (18UL)                 /*!< DSP0N1GPIO114 (Bit 18)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO114_Msk (0x40000UL)            /*!< DSP0N1GPIO114 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO113_Pos (17UL)                 /*!< DSP0N1GPIO113 (Bit 17)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO113_Msk (0x20000UL)            /*!< DSP0N1GPIO113 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO112_Pos (16UL)                 /*!< DSP0N1GPIO112 (Bit 16)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO112_Msk (0x10000UL)            /*!< DSP0N1GPIO112 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO111_Pos (15UL)                 /*!< DSP0N1GPIO111 (Bit 15)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO111_Msk (0x8000UL)             /*!< DSP0N1GPIO111 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO110_Pos (14UL)                 /*!< DSP0N1GPIO110 (Bit 14)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO110_Msk (0x4000UL)             /*!< DSP0N1GPIO110 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO109_Pos (13UL)                 /*!< DSP0N1GPIO109 (Bit 13)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO109_Msk (0x2000UL)             /*!< DSP0N1GPIO109 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO108_Pos (12UL)                 /*!< DSP0N1GPIO108 (Bit 12)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO108_Msk (0x1000UL)             /*!< DSP0N1GPIO108 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO107_Pos (11UL)                 /*!< DSP0N1GPIO107 (Bit 11)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO107_Msk (0x800UL)              /*!< DSP0N1GPIO107 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO106_Pos (10UL)                 /*!< DSP0N1GPIO106 (Bit 10)                                */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO106_Msk (0x400UL)              /*!< DSP0N1GPIO106 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO105_Pos (9UL)                  /*!< DSP0N1GPIO105 (Bit 9)                                 */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO105_Msk (0x200UL)              /*!< DSP0N1GPIO105 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO104_Pos (8UL)                  /*!< DSP0N1GPIO104 (Bit 8)                                 */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO104_Msk (0x100UL)              /*!< DSP0N1GPIO104 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO103_Pos (7UL)                  /*!< DSP0N1GPIO103 (Bit 7)                                 */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO103_Msk (0x80UL)               /*!< DSP0N1GPIO103 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO102_Pos (6UL)                  /*!< DSP0N1GPIO102 (Bit 6)                                 */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO102_Msk (0x40UL)               /*!< DSP0N1GPIO102 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO101_Pos (5UL)                  /*!< DSP0N1GPIO101 (Bit 5)                                 */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO101_Msk (0x20UL)               /*!< DSP0N1GPIO101 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO100_Pos (4UL)                  /*!< DSP0N1GPIO100 (Bit 4)                                 */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO100_Msk (0x10UL)               /*!< DSP0N1GPIO100 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO99_Pos (3UL)                   /*!< DSP0N1GPIO99 (Bit 3)                                  */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO99_Msk (0x8UL)                 /*!< DSP0N1GPIO99 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO98_Pos (2UL)                   /*!< DSP0N1GPIO98 (Bit 2)                                  */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO98_Msk (0x4UL)                 /*!< DSP0N1GPIO98 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO97_Pos (1UL)                   /*!< DSP0N1GPIO97 (Bit 1)                                  */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO97_Msk (0x2UL)                 /*!< DSP0N1GPIO97 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO96_Pos (0UL)                   /*!< DSP0N1GPIO96 (Bit 0)                                  */
#define GPIO_DSP0N1INT3CLR_DSP0N1GPIO96_Msk (0x1UL)                 /*!< DSP0N1GPIO96 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0N1INT3SET  ===================================================== */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO127_Pos (31UL)                 /*!< DSP0N1GPIO127 (Bit 31)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO127_Msk (0x80000000UL)         /*!< DSP0N1GPIO127 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO126_Pos (30UL)                 /*!< DSP0N1GPIO126 (Bit 30)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO126_Msk (0x40000000UL)         /*!< DSP0N1GPIO126 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO125_Pos (29UL)                 /*!< DSP0N1GPIO125 (Bit 29)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO125_Msk (0x20000000UL)         /*!< DSP0N1GPIO125 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO124_Pos (28UL)                 /*!< DSP0N1GPIO124 (Bit 28)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO124_Msk (0x10000000UL)         /*!< DSP0N1GPIO124 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO123_Pos (27UL)                 /*!< DSP0N1GPIO123 (Bit 27)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO123_Msk (0x8000000UL)          /*!< DSP0N1GPIO123 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO122_Pos (26UL)                 /*!< DSP0N1GPIO122 (Bit 26)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO122_Msk (0x4000000UL)          /*!< DSP0N1GPIO122 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO121_Pos (25UL)                 /*!< DSP0N1GPIO121 (Bit 25)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO121_Msk (0x2000000UL)          /*!< DSP0N1GPIO121 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO120_Pos (24UL)                 /*!< DSP0N1GPIO120 (Bit 24)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO120_Msk (0x1000000UL)          /*!< DSP0N1GPIO120 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO119_Pos (23UL)                 /*!< DSP0N1GPIO119 (Bit 23)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO119_Msk (0x800000UL)           /*!< DSP0N1GPIO119 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO118_Pos (22UL)                 /*!< DSP0N1GPIO118 (Bit 22)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO118_Msk (0x400000UL)           /*!< DSP0N1GPIO118 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO117_Pos (21UL)                 /*!< DSP0N1GPIO117 (Bit 21)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO117_Msk (0x200000UL)           /*!< DSP0N1GPIO117 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO116_Pos (20UL)                 /*!< DSP0N1GPIO116 (Bit 20)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO116_Msk (0x100000UL)           /*!< DSP0N1GPIO116 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO115_Pos (19UL)                 /*!< DSP0N1GPIO115 (Bit 19)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO115_Msk (0x80000UL)            /*!< DSP0N1GPIO115 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO114_Pos (18UL)                 /*!< DSP0N1GPIO114 (Bit 18)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO114_Msk (0x40000UL)            /*!< DSP0N1GPIO114 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO113_Pos (17UL)                 /*!< DSP0N1GPIO113 (Bit 17)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO113_Msk (0x20000UL)            /*!< DSP0N1GPIO113 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO112_Pos (16UL)                 /*!< DSP0N1GPIO112 (Bit 16)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO112_Msk (0x10000UL)            /*!< DSP0N1GPIO112 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO111_Pos (15UL)                 /*!< DSP0N1GPIO111 (Bit 15)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO111_Msk (0x8000UL)             /*!< DSP0N1GPIO111 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO110_Pos (14UL)                 /*!< DSP0N1GPIO110 (Bit 14)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO110_Msk (0x4000UL)             /*!< DSP0N1GPIO110 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO109_Pos (13UL)                 /*!< DSP0N1GPIO109 (Bit 13)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO109_Msk (0x2000UL)             /*!< DSP0N1GPIO109 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO108_Pos (12UL)                 /*!< DSP0N1GPIO108 (Bit 12)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO108_Msk (0x1000UL)             /*!< DSP0N1GPIO108 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO107_Pos (11UL)                 /*!< DSP0N1GPIO107 (Bit 11)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO107_Msk (0x800UL)              /*!< DSP0N1GPIO107 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO106_Pos (10UL)                 /*!< DSP0N1GPIO106 (Bit 10)                                */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO106_Msk (0x400UL)              /*!< DSP0N1GPIO106 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO105_Pos (9UL)                  /*!< DSP0N1GPIO105 (Bit 9)                                 */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO105_Msk (0x200UL)              /*!< DSP0N1GPIO105 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO104_Pos (8UL)                  /*!< DSP0N1GPIO104 (Bit 8)                                 */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO104_Msk (0x100UL)              /*!< DSP0N1GPIO104 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO103_Pos (7UL)                  /*!< DSP0N1GPIO103 (Bit 7)                                 */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO103_Msk (0x80UL)               /*!< DSP0N1GPIO103 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO102_Pos (6UL)                  /*!< DSP0N1GPIO102 (Bit 6)                                 */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO102_Msk (0x40UL)               /*!< DSP0N1GPIO102 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO101_Pos (5UL)                  /*!< DSP0N1GPIO101 (Bit 5)                                 */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO101_Msk (0x20UL)               /*!< DSP0N1GPIO101 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO100_Pos (4UL)                  /*!< DSP0N1GPIO100 (Bit 4)                                 */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO100_Msk (0x10UL)               /*!< DSP0N1GPIO100 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO99_Pos (3UL)                   /*!< DSP0N1GPIO99 (Bit 3)                                  */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO99_Msk (0x8UL)                 /*!< DSP0N1GPIO99 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO98_Pos (2UL)                   /*!< DSP0N1GPIO98 (Bit 2)                                  */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO98_Msk (0x4UL)                 /*!< DSP0N1GPIO98 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO97_Pos (1UL)                   /*!< DSP0N1GPIO97 (Bit 1)                                  */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO97_Msk (0x2UL)                 /*!< DSP0N1GPIO97 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO96_Pos (0UL)                   /*!< DSP0N1GPIO96 (Bit 0)                                  */
#define GPIO_DSP0N1INT3SET_DSP0N1GPIO96_Msk (0x1UL)                 /*!< DSP0N1GPIO96 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1N0INT0EN  ====================================================== */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO31_Pos (31UL)                   /*!< DSP1N0GPIO31 (Bit 31)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO31_Msk (0x80000000UL)           /*!< DSP1N0GPIO31 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO30_Pos (30UL)                   /*!< DSP1N0GPIO30 (Bit 30)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO30_Msk (0x40000000UL)           /*!< DSP1N0GPIO30 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO29_Pos (29UL)                   /*!< DSP1N0GPIO29 (Bit 29)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO29_Msk (0x20000000UL)           /*!< DSP1N0GPIO29 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO28_Pos (28UL)                   /*!< DSP1N0GPIO28 (Bit 28)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO28_Msk (0x10000000UL)           /*!< DSP1N0GPIO28 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO27_Pos (27UL)                   /*!< DSP1N0GPIO27 (Bit 27)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO27_Msk (0x8000000UL)            /*!< DSP1N0GPIO27 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO26_Pos (26UL)                   /*!< DSP1N0GPIO26 (Bit 26)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO26_Msk (0x4000000UL)            /*!< DSP1N0GPIO26 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO25_Pos (25UL)                   /*!< DSP1N0GPIO25 (Bit 25)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO25_Msk (0x2000000UL)            /*!< DSP1N0GPIO25 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO24_Pos (24UL)                   /*!< DSP1N0GPIO24 (Bit 24)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO24_Msk (0x1000000UL)            /*!< DSP1N0GPIO24 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO23_Pos (23UL)                   /*!< DSP1N0GPIO23 (Bit 23)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO23_Msk (0x800000UL)             /*!< DSP1N0GPIO23 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO22_Pos (22UL)                   /*!< DSP1N0GPIO22 (Bit 22)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO22_Msk (0x400000UL)             /*!< DSP1N0GPIO22 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO21_Pos (21UL)                   /*!< DSP1N0GPIO21 (Bit 21)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO21_Msk (0x200000UL)             /*!< DSP1N0GPIO21 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO20_Pos (20UL)                   /*!< DSP1N0GPIO20 (Bit 20)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO20_Msk (0x100000UL)             /*!< DSP1N0GPIO20 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO19_Pos (19UL)                   /*!< DSP1N0GPIO19 (Bit 19)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO19_Msk (0x80000UL)              /*!< DSP1N0GPIO19 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO18_Pos (18UL)                   /*!< DSP1N0GPIO18 (Bit 18)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO18_Msk (0x40000UL)              /*!< DSP1N0GPIO18 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO17_Pos (17UL)                   /*!< DSP1N0GPIO17 (Bit 17)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO17_Msk (0x20000UL)              /*!< DSP1N0GPIO17 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO16_Pos (16UL)                   /*!< DSP1N0GPIO16 (Bit 16)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO16_Msk (0x10000UL)              /*!< DSP1N0GPIO16 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO15_Pos (15UL)                   /*!< DSP1N0GPIO15 (Bit 15)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO15_Msk (0x8000UL)               /*!< DSP1N0GPIO15 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO14_Pos (14UL)                   /*!< DSP1N0GPIO14 (Bit 14)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO14_Msk (0x4000UL)               /*!< DSP1N0GPIO14 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO13_Pos (13UL)                   /*!< DSP1N0GPIO13 (Bit 13)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO13_Msk (0x2000UL)               /*!< DSP1N0GPIO13 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO12_Pos (12UL)                   /*!< DSP1N0GPIO12 (Bit 12)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO12_Msk (0x1000UL)               /*!< DSP1N0GPIO12 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO11_Pos (11UL)                   /*!< DSP1N0GPIO11 (Bit 11)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO11_Msk (0x800UL)                /*!< DSP1N0GPIO11 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO10_Pos (10UL)                   /*!< DSP1N0GPIO10 (Bit 10)                                 */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO10_Msk (0x400UL)                /*!< DSP1N0GPIO10 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO9_Pos (9UL)                     /*!< DSP1N0GPIO9 (Bit 9)                                   */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO9_Msk (0x200UL)                 /*!< DSP1N0GPIO9 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO8_Pos (8UL)                     /*!< DSP1N0GPIO8 (Bit 8)                                   */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO8_Msk (0x100UL)                 /*!< DSP1N0GPIO8 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO7_Pos (7UL)                     /*!< DSP1N0GPIO7 (Bit 7)                                   */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO7_Msk (0x80UL)                  /*!< DSP1N0GPIO7 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO6_Pos (6UL)                     /*!< DSP1N0GPIO6 (Bit 6)                                   */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO6_Msk (0x40UL)                  /*!< DSP1N0GPIO6 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO5_Pos (5UL)                     /*!< DSP1N0GPIO5 (Bit 5)                                   */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO5_Msk (0x20UL)                  /*!< DSP1N0GPIO5 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO4_Pos (4UL)                     /*!< DSP1N0GPIO4 (Bit 4)                                   */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO4_Msk (0x10UL)                  /*!< DSP1N0GPIO4 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO3_Pos (3UL)                     /*!< DSP1N0GPIO3 (Bit 3)                                   */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO3_Msk (0x8UL)                   /*!< DSP1N0GPIO3 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO2_Pos (2UL)                     /*!< DSP1N0GPIO2 (Bit 2)                                   */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO2_Msk (0x4UL)                   /*!< DSP1N0GPIO2 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO1_Pos (1UL)                     /*!< DSP1N0GPIO1 (Bit 1)                                   */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO1_Msk (0x2UL)                   /*!< DSP1N0GPIO1 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO0_Pos (0UL)                     /*!< DSP1N0GPIO0 (Bit 0)                                   */
#define GPIO_DSP1N0INT0EN_DSP1N0GPIO0_Msk (0x1UL)                   /*!< DSP1N0GPIO0 (Bitfield-Mask: 0x01)                     */
/* ====================================================  DSP1N0INT0STAT  ===================================================== */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO31_Pos (31UL)                 /*!< DSP1N0GPIO31 (Bit 31)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO31_Msk (0x80000000UL)         /*!< DSP1N0GPIO31 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO30_Pos (30UL)                 /*!< DSP1N0GPIO30 (Bit 30)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO30_Msk (0x40000000UL)         /*!< DSP1N0GPIO30 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO29_Pos (29UL)                 /*!< DSP1N0GPIO29 (Bit 29)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO29_Msk (0x20000000UL)         /*!< DSP1N0GPIO29 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO28_Pos (28UL)                 /*!< DSP1N0GPIO28 (Bit 28)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO28_Msk (0x10000000UL)         /*!< DSP1N0GPIO28 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO27_Pos (27UL)                 /*!< DSP1N0GPIO27 (Bit 27)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO27_Msk (0x8000000UL)          /*!< DSP1N0GPIO27 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO26_Pos (26UL)                 /*!< DSP1N0GPIO26 (Bit 26)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO26_Msk (0x4000000UL)          /*!< DSP1N0GPIO26 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO25_Pos (25UL)                 /*!< DSP1N0GPIO25 (Bit 25)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO25_Msk (0x2000000UL)          /*!< DSP1N0GPIO25 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO24_Pos (24UL)                 /*!< DSP1N0GPIO24 (Bit 24)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO24_Msk (0x1000000UL)          /*!< DSP1N0GPIO24 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO23_Pos (23UL)                 /*!< DSP1N0GPIO23 (Bit 23)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO23_Msk (0x800000UL)           /*!< DSP1N0GPIO23 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO22_Pos (22UL)                 /*!< DSP1N0GPIO22 (Bit 22)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO22_Msk (0x400000UL)           /*!< DSP1N0GPIO22 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO21_Pos (21UL)                 /*!< DSP1N0GPIO21 (Bit 21)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO21_Msk (0x200000UL)           /*!< DSP1N0GPIO21 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO20_Pos (20UL)                 /*!< DSP1N0GPIO20 (Bit 20)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO20_Msk (0x100000UL)           /*!< DSP1N0GPIO20 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO19_Pos (19UL)                 /*!< DSP1N0GPIO19 (Bit 19)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO19_Msk (0x80000UL)            /*!< DSP1N0GPIO19 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO18_Pos (18UL)                 /*!< DSP1N0GPIO18 (Bit 18)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO18_Msk (0x40000UL)            /*!< DSP1N0GPIO18 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO17_Pos (17UL)                 /*!< DSP1N0GPIO17 (Bit 17)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO17_Msk (0x20000UL)            /*!< DSP1N0GPIO17 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO16_Pos (16UL)                 /*!< DSP1N0GPIO16 (Bit 16)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO16_Msk (0x10000UL)            /*!< DSP1N0GPIO16 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO15_Pos (15UL)                 /*!< DSP1N0GPIO15 (Bit 15)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO15_Msk (0x8000UL)             /*!< DSP1N0GPIO15 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO14_Pos (14UL)                 /*!< DSP1N0GPIO14 (Bit 14)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO14_Msk (0x4000UL)             /*!< DSP1N0GPIO14 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO13_Pos (13UL)                 /*!< DSP1N0GPIO13 (Bit 13)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO13_Msk (0x2000UL)             /*!< DSP1N0GPIO13 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO12_Pos (12UL)                 /*!< DSP1N0GPIO12 (Bit 12)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO12_Msk (0x1000UL)             /*!< DSP1N0GPIO12 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO11_Pos (11UL)                 /*!< DSP1N0GPIO11 (Bit 11)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO11_Msk (0x800UL)              /*!< DSP1N0GPIO11 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO10_Pos (10UL)                 /*!< DSP1N0GPIO10 (Bit 10)                                 */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO10_Msk (0x400UL)              /*!< DSP1N0GPIO10 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO9_Pos (9UL)                   /*!< DSP1N0GPIO9 (Bit 9)                                   */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO9_Msk (0x200UL)               /*!< DSP1N0GPIO9 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO8_Pos (8UL)                   /*!< DSP1N0GPIO8 (Bit 8)                                   */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO8_Msk (0x100UL)               /*!< DSP1N0GPIO8 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO7_Pos (7UL)                   /*!< DSP1N0GPIO7 (Bit 7)                                   */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO7_Msk (0x80UL)                /*!< DSP1N0GPIO7 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO6_Pos (6UL)                   /*!< DSP1N0GPIO6 (Bit 6)                                   */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO6_Msk (0x40UL)                /*!< DSP1N0GPIO6 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO5_Pos (5UL)                   /*!< DSP1N0GPIO5 (Bit 5)                                   */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO5_Msk (0x20UL)                /*!< DSP1N0GPIO5 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO4_Pos (4UL)                   /*!< DSP1N0GPIO4 (Bit 4)                                   */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO4_Msk (0x10UL)                /*!< DSP1N0GPIO4 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO3_Pos (3UL)                   /*!< DSP1N0GPIO3 (Bit 3)                                   */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO3_Msk (0x8UL)                 /*!< DSP1N0GPIO3 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO2_Pos (2UL)                   /*!< DSP1N0GPIO2 (Bit 2)                                   */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO2_Msk (0x4UL)                 /*!< DSP1N0GPIO2 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO1_Pos (1UL)                   /*!< DSP1N0GPIO1 (Bit 1)                                   */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO1_Msk (0x2UL)                 /*!< DSP1N0GPIO1 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO0_Pos (0UL)                   /*!< DSP1N0GPIO0 (Bit 0)                                   */
#define GPIO_DSP1N0INT0STAT_DSP1N0GPIO0_Msk (0x1UL)                 /*!< DSP1N0GPIO0 (Bitfield-Mask: 0x01)                     */
/* =====================================================  DSP1N0INT0CLR  ===================================================== */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO31_Pos (31UL)                  /*!< DSP1N0GPIO31 (Bit 31)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO31_Msk (0x80000000UL)          /*!< DSP1N0GPIO31 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO30_Pos (30UL)                  /*!< DSP1N0GPIO30 (Bit 30)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO30_Msk (0x40000000UL)          /*!< DSP1N0GPIO30 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO29_Pos (29UL)                  /*!< DSP1N0GPIO29 (Bit 29)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO29_Msk (0x20000000UL)          /*!< DSP1N0GPIO29 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO28_Pos (28UL)                  /*!< DSP1N0GPIO28 (Bit 28)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO28_Msk (0x10000000UL)          /*!< DSP1N0GPIO28 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO27_Pos (27UL)                  /*!< DSP1N0GPIO27 (Bit 27)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO27_Msk (0x8000000UL)           /*!< DSP1N0GPIO27 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO26_Pos (26UL)                  /*!< DSP1N0GPIO26 (Bit 26)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO26_Msk (0x4000000UL)           /*!< DSP1N0GPIO26 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO25_Pos (25UL)                  /*!< DSP1N0GPIO25 (Bit 25)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO25_Msk (0x2000000UL)           /*!< DSP1N0GPIO25 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO24_Pos (24UL)                  /*!< DSP1N0GPIO24 (Bit 24)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO24_Msk (0x1000000UL)           /*!< DSP1N0GPIO24 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO23_Pos (23UL)                  /*!< DSP1N0GPIO23 (Bit 23)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO23_Msk (0x800000UL)            /*!< DSP1N0GPIO23 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO22_Pos (22UL)                  /*!< DSP1N0GPIO22 (Bit 22)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO22_Msk (0x400000UL)            /*!< DSP1N0GPIO22 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO21_Pos (21UL)                  /*!< DSP1N0GPIO21 (Bit 21)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO21_Msk (0x200000UL)            /*!< DSP1N0GPIO21 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO20_Pos (20UL)                  /*!< DSP1N0GPIO20 (Bit 20)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO20_Msk (0x100000UL)            /*!< DSP1N0GPIO20 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO19_Pos (19UL)                  /*!< DSP1N0GPIO19 (Bit 19)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO19_Msk (0x80000UL)             /*!< DSP1N0GPIO19 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO18_Pos (18UL)                  /*!< DSP1N0GPIO18 (Bit 18)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO18_Msk (0x40000UL)             /*!< DSP1N0GPIO18 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO17_Pos (17UL)                  /*!< DSP1N0GPIO17 (Bit 17)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO17_Msk (0x20000UL)             /*!< DSP1N0GPIO17 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO16_Pos (16UL)                  /*!< DSP1N0GPIO16 (Bit 16)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO16_Msk (0x10000UL)             /*!< DSP1N0GPIO16 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO15_Pos (15UL)                  /*!< DSP1N0GPIO15 (Bit 15)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO15_Msk (0x8000UL)              /*!< DSP1N0GPIO15 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO14_Pos (14UL)                  /*!< DSP1N0GPIO14 (Bit 14)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO14_Msk (0x4000UL)              /*!< DSP1N0GPIO14 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO13_Pos (13UL)                  /*!< DSP1N0GPIO13 (Bit 13)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO13_Msk (0x2000UL)              /*!< DSP1N0GPIO13 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO12_Pos (12UL)                  /*!< DSP1N0GPIO12 (Bit 12)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO12_Msk (0x1000UL)              /*!< DSP1N0GPIO12 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO11_Pos (11UL)                  /*!< DSP1N0GPIO11 (Bit 11)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO11_Msk (0x800UL)               /*!< DSP1N0GPIO11 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO10_Pos (10UL)                  /*!< DSP1N0GPIO10 (Bit 10)                                 */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO10_Msk (0x400UL)               /*!< DSP1N0GPIO10 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO9_Pos (9UL)                    /*!< DSP1N0GPIO9 (Bit 9)                                   */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO9_Msk (0x200UL)                /*!< DSP1N0GPIO9 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO8_Pos (8UL)                    /*!< DSP1N0GPIO8 (Bit 8)                                   */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO8_Msk (0x100UL)                /*!< DSP1N0GPIO8 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO7_Pos (7UL)                    /*!< DSP1N0GPIO7 (Bit 7)                                   */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO7_Msk (0x80UL)                 /*!< DSP1N0GPIO7 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO6_Pos (6UL)                    /*!< DSP1N0GPIO6 (Bit 6)                                   */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO6_Msk (0x40UL)                 /*!< DSP1N0GPIO6 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO5_Pos (5UL)                    /*!< DSP1N0GPIO5 (Bit 5)                                   */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO5_Msk (0x20UL)                 /*!< DSP1N0GPIO5 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO4_Pos (4UL)                    /*!< DSP1N0GPIO4 (Bit 4)                                   */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO4_Msk (0x10UL)                 /*!< DSP1N0GPIO4 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO3_Pos (3UL)                    /*!< DSP1N0GPIO3 (Bit 3)                                   */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO3_Msk (0x8UL)                  /*!< DSP1N0GPIO3 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO2_Pos (2UL)                    /*!< DSP1N0GPIO2 (Bit 2)                                   */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO2_Msk (0x4UL)                  /*!< DSP1N0GPIO2 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO1_Pos (1UL)                    /*!< DSP1N0GPIO1 (Bit 1)                                   */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO1_Msk (0x2UL)                  /*!< DSP1N0GPIO1 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO0_Pos (0UL)                    /*!< DSP1N0GPIO0 (Bit 0)                                   */
#define GPIO_DSP1N0INT0CLR_DSP1N0GPIO0_Msk (0x1UL)                  /*!< DSP1N0GPIO0 (Bitfield-Mask: 0x01)                     */
/* =====================================================  DSP1N0INT0SET  ===================================================== */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO31_Pos (31UL)                  /*!< DSP1N0GPIO31 (Bit 31)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO31_Msk (0x80000000UL)          /*!< DSP1N0GPIO31 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO30_Pos (30UL)                  /*!< DSP1N0GPIO30 (Bit 30)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO30_Msk (0x40000000UL)          /*!< DSP1N0GPIO30 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO29_Pos (29UL)                  /*!< DSP1N0GPIO29 (Bit 29)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO29_Msk (0x20000000UL)          /*!< DSP1N0GPIO29 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO28_Pos (28UL)                  /*!< DSP1N0GPIO28 (Bit 28)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO28_Msk (0x10000000UL)          /*!< DSP1N0GPIO28 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO27_Pos (27UL)                  /*!< DSP1N0GPIO27 (Bit 27)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO27_Msk (0x8000000UL)           /*!< DSP1N0GPIO27 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO26_Pos (26UL)                  /*!< DSP1N0GPIO26 (Bit 26)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO26_Msk (0x4000000UL)           /*!< DSP1N0GPIO26 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO25_Pos (25UL)                  /*!< DSP1N0GPIO25 (Bit 25)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO25_Msk (0x2000000UL)           /*!< DSP1N0GPIO25 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO24_Pos (24UL)                  /*!< DSP1N0GPIO24 (Bit 24)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO24_Msk (0x1000000UL)           /*!< DSP1N0GPIO24 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO23_Pos (23UL)                  /*!< DSP1N0GPIO23 (Bit 23)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO23_Msk (0x800000UL)            /*!< DSP1N0GPIO23 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO22_Pos (22UL)                  /*!< DSP1N0GPIO22 (Bit 22)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO22_Msk (0x400000UL)            /*!< DSP1N0GPIO22 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO21_Pos (21UL)                  /*!< DSP1N0GPIO21 (Bit 21)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO21_Msk (0x200000UL)            /*!< DSP1N0GPIO21 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO20_Pos (20UL)                  /*!< DSP1N0GPIO20 (Bit 20)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO20_Msk (0x100000UL)            /*!< DSP1N0GPIO20 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO19_Pos (19UL)                  /*!< DSP1N0GPIO19 (Bit 19)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO19_Msk (0x80000UL)             /*!< DSP1N0GPIO19 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO18_Pos (18UL)                  /*!< DSP1N0GPIO18 (Bit 18)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO18_Msk (0x40000UL)             /*!< DSP1N0GPIO18 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO17_Pos (17UL)                  /*!< DSP1N0GPIO17 (Bit 17)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO17_Msk (0x20000UL)             /*!< DSP1N0GPIO17 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO16_Pos (16UL)                  /*!< DSP1N0GPIO16 (Bit 16)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO16_Msk (0x10000UL)             /*!< DSP1N0GPIO16 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO15_Pos (15UL)                  /*!< DSP1N0GPIO15 (Bit 15)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO15_Msk (0x8000UL)              /*!< DSP1N0GPIO15 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO14_Pos (14UL)                  /*!< DSP1N0GPIO14 (Bit 14)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO14_Msk (0x4000UL)              /*!< DSP1N0GPIO14 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO13_Pos (13UL)                  /*!< DSP1N0GPIO13 (Bit 13)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO13_Msk (0x2000UL)              /*!< DSP1N0GPIO13 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO12_Pos (12UL)                  /*!< DSP1N0GPIO12 (Bit 12)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO12_Msk (0x1000UL)              /*!< DSP1N0GPIO12 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO11_Pos (11UL)                  /*!< DSP1N0GPIO11 (Bit 11)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO11_Msk (0x800UL)               /*!< DSP1N0GPIO11 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO10_Pos (10UL)                  /*!< DSP1N0GPIO10 (Bit 10)                                 */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO10_Msk (0x400UL)               /*!< DSP1N0GPIO10 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO9_Pos (9UL)                    /*!< DSP1N0GPIO9 (Bit 9)                                   */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO9_Msk (0x200UL)                /*!< DSP1N0GPIO9 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO8_Pos (8UL)                    /*!< DSP1N0GPIO8 (Bit 8)                                   */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO8_Msk (0x100UL)                /*!< DSP1N0GPIO8 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO7_Pos (7UL)                    /*!< DSP1N0GPIO7 (Bit 7)                                   */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO7_Msk (0x80UL)                 /*!< DSP1N0GPIO7 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO6_Pos (6UL)                    /*!< DSP1N0GPIO6 (Bit 6)                                   */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO6_Msk (0x40UL)                 /*!< DSP1N0GPIO6 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO5_Pos (5UL)                    /*!< DSP1N0GPIO5 (Bit 5)                                   */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO5_Msk (0x20UL)                 /*!< DSP1N0GPIO5 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO4_Pos (4UL)                    /*!< DSP1N0GPIO4 (Bit 4)                                   */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO4_Msk (0x10UL)                 /*!< DSP1N0GPIO4 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO3_Pos (3UL)                    /*!< DSP1N0GPIO3 (Bit 3)                                   */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO3_Msk (0x8UL)                  /*!< DSP1N0GPIO3 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO2_Pos (2UL)                    /*!< DSP1N0GPIO2 (Bit 2)                                   */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO2_Msk (0x4UL)                  /*!< DSP1N0GPIO2 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO1_Pos (1UL)                    /*!< DSP1N0GPIO1 (Bit 1)                                   */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO1_Msk (0x2UL)                  /*!< DSP1N0GPIO1 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO0_Pos (0UL)                    /*!< DSP1N0GPIO0 (Bit 0)                                   */
#define GPIO_DSP1N0INT0SET_DSP1N0GPIO0_Msk (0x1UL)                  /*!< DSP1N0GPIO0 (Bitfield-Mask: 0x01)                     */
/* =====================================================  DSP1N0INT1EN  ====================================================== */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO63_Pos (31UL)                   /*!< DSP1N0GPIO63 (Bit 31)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO63_Msk (0x80000000UL)           /*!< DSP1N0GPIO63 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO62_Pos (30UL)                   /*!< DSP1N0GPIO62 (Bit 30)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO62_Msk (0x40000000UL)           /*!< DSP1N0GPIO62 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO61_Pos (29UL)                   /*!< DSP1N0GPIO61 (Bit 29)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO61_Msk (0x20000000UL)           /*!< DSP1N0GPIO61 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO60_Pos (28UL)                   /*!< DSP1N0GPIO60 (Bit 28)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO60_Msk (0x10000000UL)           /*!< DSP1N0GPIO60 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO59_Pos (27UL)                   /*!< DSP1N0GPIO59 (Bit 27)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO59_Msk (0x8000000UL)            /*!< DSP1N0GPIO59 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO58_Pos (26UL)                   /*!< DSP1N0GPIO58 (Bit 26)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO58_Msk (0x4000000UL)            /*!< DSP1N0GPIO58 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO57_Pos (25UL)                   /*!< DSP1N0GPIO57 (Bit 25)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO57_Msk (0x2000000UL)            /*!< DSP1N0GPIO57 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO56_Pos (24UL)                   /*!< DSP1N0GPIO56 (Bit 24)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO56_Msk (0x1000000UL)            /*!< DSP1N0GPIO56 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO55_Pos (23UL)                   /*!< DSP1N0GPIO55 (Bit 23)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO55_Msk (0x800000UL)             /*!< DSP1N0GPIO55 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO54_Pos (22UL)                   /*!< DSP1N0GPIO54 (Bit 22)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO54_Msk (0x400000UL)             /*!< DSP1N0GPIO54 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO53_Pos (21UL)                   /*!< DSP1N0GPIO53 (Bit 21)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO53_Msk (0x200000UL)             /*!< DSP1N0GPIO53 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO52_Pos (20UL)                   /*!< DSP1N0GPIO52 (Bit 20)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO52_Msk (0x100000UL)             /*!< DSP1N0GPIO52 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO51_Pos (19UL)                   /*!< DSP1N0GPIO51 (Bit 19)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO51_Msk (0x80000UL)              /*!< DSP1N0GPIO51 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO50_Pos (18UL)                   /*!< DSP1N0GPIO50 (Bit 18)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO50_Msk (0x40000UL)              /*!< DSP1N0GPIO50 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO49_Pos (17UL)                   /*!< DSP1N0GPIO49 (Bit 17)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO49_Msk (0x20000UL)              /*!< DSP1N0GPIO49 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO48_Pos (16UL)                   /*!< DSP1N0GPIO48 (Bit 16)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO48_Msk (0x10000UL)              /*!< DSP1N0GPIO48 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO47_Pos (15UL)                   /*!< DSP1N0GPIO47 (Bit 15)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO47_Msk (0x8000UL)               /*!< DSP1N0GPIO47 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO46_Pos (14UL)                   /*!< DSP1N0GPIO46 (Bit 14)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO46_Msk (0x4000UL)               /*!< DSP1N0GPIO46 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO45_Pos (13UL)                   /*!< DSP1N0GPIO45 (Bit 13)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO45_Msk (0x2000UL)               /*!< DSP1N0GPIO45 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO44_Pos (12UL)                   /*!< DSP1N0GPIO44 (Bit 12)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO44_Msk (0x1000UL)               /*!< DSP1N0GPIO44 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO43_Pos (11UL)                   /*!< DSP1N0GPIO43 (Bit 11)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO43_Msk (0x800UL)                /*!< DSP1N0GPIO43 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO42_Pos (10UL)                   /*!< DSP1N0GPIO42 (Bit 10)                                 */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO42_Msk (0x400UL)                /*!< DSP1N0GPIO42 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO41_Pos (9UL)                    /*!< DSP1N0GPIO41 (Bit 9)                                  */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO41_Msk (0x200UL)                /*!< DSP1N0GPIO41 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO40_Pos (8UL)                    /*!< DSP1N0GPIO40 (Bit 8)                                  */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO40_Msk (0x100UL)                /*!< DSP1N0GPIO40 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO39_Pos (7UL)                    /*!< DSP1N0GPIO39 (Bit 7)                                  */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO39_Msk (0x80UL)                 /*!< DSP1N0GPIO39 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO38_Pos (6UL)                    /*!< DSP1N0GPIO38 (Bit 6)                                  */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO38_Msk (0x40UL)                 /*!< DSP1N0GPIO38 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO37_Pos (5UL)                    /*!< DSP1N0GPIO37 (Bit 5)                                  */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO37_Msk (0x20UL)                 /*!< DSP1N0GPIO37 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO36_Pos (4UL)                    /*!< DSP1N0GPIO36 (Bit 4)                                  */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO36_Msk (0x10UL)                 /*!< DSP1N0GPIO36 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO35_Pos (3UL)                    /*!< DSP1N0GPIO35 (Bit 3)                                  */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO35_Msk (0x8UL)                  /*!< DSP1N0GPIO35 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO34_Pos (2UL)                    /*!< DSP1N0GPIO34 (Bit 2)                                  */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO34_Msk (0x4UL)                  /*!< DSP1N0GPIO34 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO33_Pos (1UL)                    /*!< DSP1N0GPIO33 (Bit 1)                                  */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO33_Msk (0x2UL)                  /*!< DSP1N0GPIO33 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO32_Pos (0UL)                    /*!< DSP1N0GPIO32 (Bit 0)                                  */
#define GPIO_DSP1N0INT1EN_DSP1N0GPIO32_Msk (0x1UL)                  /*!< DSP1N0GPIO32 (Bitfield-Mask: 0x01)                    */
/* ====================================================  DSP1N0INT1STAT  ===================================================== */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO63_Pos (31UL)                 /*!< DSP1N0GPIO63 (Bit 31)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO63_Msk (0x80000000UL)         /*!< DSP1N0GPIO63 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO62_Pos (30UL)                 /*!< DSP1N0GPIO62 (Bit 30)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO62_Msk (0x40000000UL)         /*!< DSP1N0GPIO62 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO61_Pos (29UL)                 /*!< DSP1N0GPIO61 (Bit 29)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO61_Msk (0x20000000UL)         /*!< DSP1N0GPIO61 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO60_Pos (28UL)                 /*!< DSP1N0GPIO60 (Bit 28)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO60_Msk (0x10000000UL)         /*!< DSP1N0GPIO60 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO59_Pos (27UL)                 /*!< DSP1N0GPIO59 (Bit 27)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO59_Msk (0x8000000UL)          /*!< DSP1N0GPIO59 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO58_Pos (26UL)                 /*!< DSP1N0GPIO58 (Bit 26)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO58_Msk (0x4000000UL)          /*!< DSP1N0GPIO58 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO57_Pos (25UL)                 /*!< DSP1N0GPIO57 (Bit 25)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO57_Msk (0x2000000UL)          /*!< DSP1N0GPIO57 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO56_Pos (24UL)                 /*!< DSP1N0GPIO56 (Bit 24)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO56_Msk (0x1000000UL)          /*!< DSP1N0GPIO56 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO55_Pos (23UL)                 /*!< DSP1N0GPIO55 (Bit 23)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO55_Msk (0x800000UL)           /*!< DSP1N0GPIO55 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO54_Pos (22UL)                 /*!< DSP1N0GPIO54 (Bit 22)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO54_Msk (0x400000UL)           /*!< DSP1N0GPIO54 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO53_Pos (21UL)                 /*!< DSP1N0GPIO53 (Bit 21)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO53_Msk (0x200000UL)           /*!< DSP1N0GPIO53 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO52_Pos (20UL)                 /*!< DSP1N0GPIO52 (Bit 20)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO52_Msk (0x100000UL)           /*!< DSP1N0GPIO52 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO51_Pos (19UL)                 /*!< DSP1N0GPIO51 (Bit 19)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO51_Msk (0x80000UL)            /*!< DSP1N0GPIO51 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO50_Pos (18UL)                 /*!< DSP1N0GPIO50 (Bit 18)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO50_Msk (0x40000UL)            /*!< DSP1N0GPIO50 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO49_Pos (17UL)                 /*!< DSP1N0GPIO49 (Bit 17)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO49_Msk (0x20000UL)            /*!< DSP1N0GPIO49 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO48_Pos (16UL)                 /*!< DSP1N0GPIO48 (Bit 16)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO48_Msk (0x10000UL)            /*!< DSP1N0GPIO48 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO47_Pos (15UL)                 /*!< DSP1N0GPIO47 (Bit 15)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO47_Msk (0x8000UL)             /*!< DSP1N0GPIO47 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO46_Pos (14UL)                 /*!< DSP1N0GPIO46 (Bit 14)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO46_Msk (0x4000UL)             /*!< DSP1N0GPIO46 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO45_Pos (13UL)                 /*!< DSP1N0GPIO45 (Bit 13)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO45_Msk (0x2000UL)             /*!< DSP1N0GPIO45 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO44_Pos (12UL)                 /*!< DSP1N0GPIO44 (Bit 12)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO44_Msk (0x1000UL)             /*!< DSP1N0GPIO44 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO43_Pos (11UL)                 /*!< DSP1N0GPIO43 (Bit 11)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO43_Msk (0x800UL)              /*!< DSP1N0GPIO43 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO42_Pos (10UL)                 /*!< DSP1N0GPIO42 (Bit 10)                                 */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO42_Msk (0x400UL)              /*!< DSP1N0GPIO42 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO41_Pos (9UL)                  /*!< DSP1N0GPIO41 (Bit 9)                                  */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO41_Msk (0x200UL)              /*!< DSP1N0GPIO41 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO40_Pos (8UL)                  /*!< DSP1N0GPIO40 (Bit 8)                                  */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO40_Msk (0x100UL)              /*!< DSP1N0GPIO40 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO39_Pos (7UL)                  /*!< DSP1N0GPIO39 (Bit 7)                                  */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO39_Msk (0x80UL)               /*!< DSP1N0GPIO39 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO38_Pos (6UL)                  /*!< DSP1N0GPIO38 (Bit 6)                                  */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO38_Msk (0x40UL)               /*!< DSP1N0GPIO38 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO37_Pos (5UL)                  /*!< DSP1N0GPIO37 (Bit 5)                                  */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO37_Msk (0x20UL)               /*!< DSP1N0GPIO37 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO36_Pos (4UL)                  /*!< DSP1N0GPIO36 (Bit 4)                                  */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO36_Msk (0x10UL)               /*!< DSP1N0GPIO36 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO35_Pos (3UL)                  /*!< DSP1N0GPIO35 (Bit 3)                                  */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO35_Msk (0x8UL)                /*!< DSP1N0GPIO35 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO34_Pos (2UL)                  /*!< DSP1N0GPIO34 (Bit 2)                                  */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO34_Msk (0x4UL)                /*!< DSP1N0GPIO34 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO33_Pos (1UL)                  /*!< DSP1N0GPIO33 (Bit 1)                                  */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO33_Msk (0x2UL)                /*!< DSP1N0GPIO33 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO32_Pos (0UL)                  /*!< DSP1N0GPIO32 (Bit 0)                                  */
#define GPIO_DSP1N0INT1STAT_DSP1N0GPIO32_Msk (0x1UL)                /*!< DSP1N0GPIO32 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1N0INT1CLR  ===================================================== */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO63_Pos (31UL)                  /*!< DSP1N0GPIO63 (Bit 31)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO63_Msk (0x80000000UL)          /*!< DSP1N0GPIO63 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO62_Pos (30UL)                  /*!< DSP1N0GPIO62 (Bit 30)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO62_Msk (0x40000000UL)          /*!< DSP1N0GPIO62 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO61_Pos (29UL)                  /*!< DSP1N0GPIO61 (Bit 29)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO61_Msk (0x20000000UL)          /*!< DSP1N0GPIO61 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO60_Pos (28UL)                  /*!< DSP1N0GPIO60 (Bit 28)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO60_Msk (0x10000000UL)          /*!< DSP1N0GPIO60 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO59_Pos (27UL)                  /*!< DSP1N0GPIO59 (Bit 27)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO59_Msk (0x8000000UL)           /*!< DSP1N0GPIO59 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO58_Pos (26UL)                  /*!< DSP1N0GPIO58 (Bit 26)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO58_Msk (0x4000000UL)           /*!< DSP1N0GPIO58 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO57_Pos (25UL)                  /*!< DSP1N0GPIO57 (Bit 25)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO57_Msk (0x2000000UL)           /*!< DSP1N0GPIO57 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO56_Pos (24UL)                  /*!< DSP1N0GPIO56 (Bit 24)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO56_Msk (0x1000000UL)           /*!< DSP1N0GPIO56 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO55_Pos (23UL)                  /*!< DSP1N0GPIO55 (Bit 23)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO55_Msk (0x800000UL)            /*!< DSP1N0GPIO55 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO54_Pos (22UL)                  /*!< DSP1N0GPIO54 (Bit 22)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO54_Msk (0x400000UL)            /*!< DSP1N0GPIO54 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO53_Pos (21UL)                  /*!< DSP1N0GPIO53 (Bit 21)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO53_Msk (0x200000UL)            /*!< DSP1N0GPIO53 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO52_Pos (20UL)                  /*!< DSP1N0GPIO52 (Bit 20)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO52_Msk (0x100000UL)            /*!< DSP1N0GPIO52 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO51_Pos (19UL)                  /*!< DSP1N0GPIO51 (Bit 19)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO51_Msk (0x80000UL)             /*!< DSP1N0GPIO51 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO50_Pos (18UL)                  /*!< DSP1N0GPIO50 (Bit 18)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO50_Msk (0x40000UL)             /*!< DSP1N0GPIO50 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO49_Pos (17UL)                  /*!< DSP1N0GPIO49 (Bit 17)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO49_Msk (0x20000UL)             /*!< DSP1N0GPIO49 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO48_Pos (16UL)                  /*!< DSP1N0GPIO48 (Bit 16)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO48_Msk (0x10000UL)             /*!< DSP1N0GPIO48 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO47_Pos (15UL)                  /*!< DSP1N0GPIO47 (Bit 15)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO47_Msk (0x8000UL)              /*!< DSP1N0GPIO47 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO46_Pos (14UL)                  /*!< DSP1N0GPIO46 (Bit 14)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO46_Msk (0x4000UL)              /*!< DSP1N0GPIO46 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO45_Pos (13UL)                  /*!< DSP1N0GPIO45 (Bit 13)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO45_Msk (0x2000UL)              /*!< DSP1N0GPIO45 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO44_Pos (12UL)                  /*!< DSP1N0GPIO44 (Bit 12)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO44_Msk (0x1000UL)              /*!< DSP1N0GPIO44 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO43_Pos (11UL)                  /*!< DSP1N0GPIO43 (Bit 11)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO43_Msk (0x800UL)               /*!< DSP1N0GPIO43 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO42_Pos (10UL)                  /*!< DSP1N0GPIO42 (Bit 10)                                 */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO42_Msk (0x400UL)               /*!< DSP1N0GPIO42 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO41_Pos (9UL)                   /*!< DSP1N0GPIO41 (Bit 9)                                  */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO41_Msk (0x200UL)               /*!< DSP1N0GPIO41 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO40_Pos (8UL)                   /*!< DSP1N0GPIO40 (Bit 8)                                  */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO40_Msk (0x100UL)               /*!< DSP1N0GPIO40 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO39_Pos (7UL)                   /*!< DSP1N0GPIO39 (Bit 7)                                  */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO39_Msk (0x80UL)                /*!< DSP1N0GPIO39 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO38_Pos (6UL)                   /*!< DSP1N0GPIO38 (Bit 6)                                  */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO38_Msk (0x40UL)                /*!< DSP1N0GPIO38 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO37_Pos (5UL)                   /*!< DSP1N0GPIO37 (Bit 5)                                  */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO37_Msk (0x20UL)                /*!< DSP1N0GPIO37 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO36_Pos (4UL)                   /*!< DSP1N0GPIO36 (Bit 4)                                  */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO36_Msk (0x10UL)                /*!< DSP1N0GPIO36 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO35_Pos (3UL)                   /*!< DSP1N0GPIO35 (Bit 3)                                  */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO35_Msk (0x8UL)                 /*!< DSP1N0GPIO35 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO34_Pos (2UL)                   /*!< DSP1N0GPIO34 (Bit 2)                                  */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO34_Msk (0x4UL)                 /*!< DSP1N0GPIO34 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO33_Pos (1UL)                   /*!< DSP1N0GPIO33 (Bit 1)                                  */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO33_Msk (0x2UL)                 /*!< DSP1N0GPIO33 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO32_Pos (0UL)                   /*!< DSP1N0GPIO32 (Bit 0)                                  */
#define GPIO_DSP1N0INT1CLR_DSP1N0GPIO32_Msk (0x1UL)                 /*!< DSP1N0GPIO32 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1N0INT1SET  ===================================================== */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO63_Pos (31UL)                  /*!< DSP1N0GPIO63 (Bit 31)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO63_Msk (0x80000000UL)          /*!< DSP1N0GPIO63 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO62_Pos (30UL)                  /*!< DSP1N0GPIO62 (Bit 30)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO62_Msk (0x40000000UL)          /*!< DSP1N0GPIO62 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO61_Pos (29UL)                  /*!< DSP1N0GPIO61 (Bit 29)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO61_Msk (0x20000000UL)          /*!< DSP1N0GPIO61 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO60_Pos (28UL)                  /*!< DSP1N0GPIO60 (Bit 28)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO60_Msk (0x10000000UL)          /*!< DSP1N0GPIO60 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO59_Pos (27UL)                  /*!< DSP1N0GPIO59 (Bit 27)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO59_Msk (0x8000000UL)           /*!< DSP1N0GPIO59 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO58_Pos (26UL)                  /*!< DSP1N0GPIO58 (Bit 26)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO58_Msk (0x4000000UL)           /*!< DSP1N0GPIO58 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO57_Pos (25UL)                  /*!< DSP1N0GPIO57 (Bit 25)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO57_Msk (0x2000000UL)           /*!< DSP1N0GPIO57 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO56_Pos (24UL)                  /*!< DSP1N0GPIO56 (Bit 24)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO56_Msk (0x1000000UL)           /*!< DSP1N0GPIO56 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO55_Pos (23UL)                  /*!< DSP1N0GPIO55 (Bit 23)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO55_Msk (0x800000UL)            /*!< DSP1N0GPIO55 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO54_Pos (22UL)                  /*!< DSP1N0GPIO54 (Bit 22)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO54_Msk (0x400000UL)            /*!< DSP1N0GPIO54 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO53_Pos (21UL)                  /*!< DSP1N0GPIO53 (Bit 21)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO53_Msk (0x200000UL)            /*!< DSP1N0GPIO53 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO52_Pos (20UL)                  /*!< DSP1N0GPIO52 (Bit 20)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO52_Msk (0x100000UL)            /*!< DSP1N0GPIO52 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO51_Pos (19UL)                  /*!< DSP1N0GPIO51 (Bit 19)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO51_Msk (0x80000UL)             /*!< DSP1N0GPIO51 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO50_Pos (18UL)                  /*!< DSP1N0GPIO50 (Bit 18)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO50_Msk (0x40000UL)             /*!< DSP1N0GPIO50 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO49_Pos (17UL)                  /*!< DSP1N0GPIO49 (Bit 17)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO49_Msk (0x20000UL)             /*!< DSP1N0GPIO49 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO48_Pos (16UL)                  /*!< DSP1N0GPIO48 (Bit 16)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO48_Msk (0x10000UL)             /*!< DSP1N0GPIO48 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO47_Pos (15UL)                  /*!< DSP1N0GPIO47 (Bit 15)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO47_Msk (0x8000UL)              /*!< DSP1N0GPIO47 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO46_Pos (14UL)                  /*!< DSP1N0GPIO46 (Bit 14)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO46_Msk (0x4000UL)              /*!< DSP1N0GPIO46 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO45_Pos (13UL)                  /*!< DSP1N0GPIO45 (Bit 13)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO45_Msk (0x2000UL)              /*!< DSP1N0GPIO45 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO44_Pos (12UL)                  /*!< DSP1N0GPIO44 (Bit 12)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO44_Msk (0x1000UL)              /*!< DSP1N0GPIO44 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO43_Pos (11UL)                  /*!< DSP1N0GPIO43 (Bit 11)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO43_Msk (0x800UL)               /*!< DSP1N0GPIO43 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO42_Pos (10UL)                  /*!< DSP1N0GPIO42 (Bit 10)                                 */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO42_Msk (0x400UL)               /*!< DSP1N0GPIO42 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO41_Pos (9UL)                   /*!< DSP1N0GPIO41 (Bit 9)                                  */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO41_Msk (0x200UL)               /*!< DSP1N0GPIO41 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO40_Pos (8UL)                   /*!< DSP1N0GPIO40 (Bit 8)                                  */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO40_Msk (0x100UL)               /*!< DSP1N0GPIO40 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO39_Pos (7UL)                   /*!< DSP1N0GPIO39 (Bit 7)                                  */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO39_Msk (0x80UL)                /*!< DSP1N0GPIO39 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO38_Pos (6UL)                   /*!< DSP1N0GPIO38 (Bit 6)                                  */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO38_Msk (0x40UL)                /*!< DSP1N0GPIO38 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO37_Pos (5UL)                   /*!< DSP1N0GPIO37 (Bit 5)                                  */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO37_Msk (0x20UL)                /*!< DSP1N0GPIO37 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO36_Pos (4UL)                   /*!< DSP1N0GPIO36 (Bit 4)                                  */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO36_Msk (0x10UL)                /*!< DSP1N0GPIO36 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO35_Pos (3UL)                   /*!< DSP1N0GPIO35 (Bit 3)                                  */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO35_Msk (0x8UL)                 /*!< DSP1N0GPIO35 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO34_Pos (2UL)                   /*!< DSP1N0GPIO34 (Bit 2)                                  */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO34_Msk (0x4UL)                 /*!< DSP1N0GPIO34 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO33_Pos (1UL)                   /*!< DSP1N0GPIO33 (Bit 1)                                  */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO33_Msk (0x2UL)                 /*!< DSP1N0GPIO33 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO32_Pos (0UL)                   /*!< DSP1N0GPIO32 (Bit 0)                                  */
#define GPIO_DSP1N0INT1SET_DSP1N0GPIO32_Msk (0x1UL)                 /*!< DSP1N0GPIO32 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1N0INT2EN  ====================================================== */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO95_Pos (31UL)                   /*!< DSP1N0GPIO95 (Bit 31)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO95_Msk (0x80000000UL)           /*!< DSP1N0GPIO95 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO94_Pos (30UL)                   /*!< DSP1N0GPIO94 (Bit 30)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO94_Msk (0x40000000UL)           /*!< DSP1N0GPIO94 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO93_Pos (29UL)                   /*!< DSP1N0GPIO93 (Bit 29)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO93_Msk (0x20000000UL)           /*!< DSP1N0GPIO93 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO92_Pos (28UL)                   /*!< DSP1N0GPIO92 (Bit 28)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO92_Msk (0x10000000UL)           /*!< DSP1N0GPIO92 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO91_Pos (27UL)                   /*!< DSP1N0GPIO91 (Bit 27)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO91_Msk (0x8000000UL)            /*!< DSP1N0GPIO91 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO90_Pos (26UL)                   /*!< DSP1N0GPIO90 (Bit 26)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO90_Msk (0x4000000UL)            /*!< DSP1N0GPIO90 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO89_Pos (25UL)                   /*!< DSP1N0GPIO89 (Bit 25)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO89_Msk (0x2000000UL)            /*!< DSP1N0GPIO89 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO88_Pos (24UL)                   /*!< DSP1N0GPIO88 (Bit 24)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO88_Msk (0x1000000UL)            /*!< DSP1N0GPIO88 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO87_Pos (23UL)                   /*!< DSP1N0GPIO87 (Bit 23)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO87_Msk (0x800000UL)             /*!< DSP1N0GPIO87 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO86_Pos (22UL)                   /*!< DSP1N0GPIO86 (Bit 22)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO86_Msk (0x400000UL)             /*!< DSP1N0GPIO86 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO85_Pos (21UL)                   /*!< DSP1N0GPIO85 (Bit 21)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO85_Msk (0x200000UL)             /*!< DSP1N0GPIO85 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO84_Pos (20UL)                   /*!< DSP1N0GPIO84 (Bit 20)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO84_Msk (0x100000UL)             /*!< DSP1N0GPIO84 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO83_Pos (19UL)                   /*!< DSP1N0GPIO83 (Bit 19)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO83_Msk (0x80000UL)              /*!< DSP1N0GPIO83 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO82_Pos (18UL)                   /*!< DSP1N0GPIO82 (Bit 18)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO82_Msk (0x40000UL)              /*!< DSP1N0GPIO82 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO81_Pos (17UL)                   /*!< DSP1N0GPIO81 (Bit 17)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO81_Msk (0x20000UL)              /*!< DSP1N0GPIO81 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO80_Pos (16UL)                   /*!< DSP1N0GPIO80 (Bit 16)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO80_Msk (0x10000UL)              /*!< DSP1N0GPIO80 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO79_Pos (15UL)                   /*!< DSP1N0GPIO79 (Bit 15)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO79_Msk (0x8000UL)               /*!< DSP1N0GPIO79 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO78_Pos (14UL)                   /*!< DSP1N0GPIO78 (Bit 14)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO78_Msk (0x4000UL)               /*!< DSP1N0GPIO78 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO77_Pos (13UL)                   /*!< DSP1N0GPIO77 (Bit 13)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO77_Msk (0x2000UL)               /*!< DSP1N0GPIO77 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO76_Pos (12UL)                   /*!< DSP1N0GPIO76 (Bit 12)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO76_Msk (0x1000UL)               /*!< DSP1N0GPIO76 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO75_Pos (11UL)                   /*!< DSP1N0GPIO75 (Bit 11)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO75_Msk (0x800UL)                /*!< DSP1N0GPIO75 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO74_Pos (10UL)                   /*!< DSP1N0GPIO74 (Bit 10)                                 */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO74_Msk (0x400UL)                /*!< DSP1N0GPIO74 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO73_Pos (9UL)                    /*!< DSP1N0GPIO73 (Bit 9)                                  */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO73_Msk (0x200UL)                /*!< DSP1N0GPIO73 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO72_Pos (8UL)                    /*!< DSP1N0GPIO72 (Bit 8)                                  */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO72_Msk (0x100UL)                /*!< DSP1N0GPIO72 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO71_Pos (7UL)                    /*!< DSP1N0GPIO71 (Bit 7)                                  */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO71_Msk (0x80UL)                 /*!< DSP1N0GPIO71 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO70_Pos (6UL)                    /*!< DSP1N0GPIO70 (Bit 6)                                  */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO70_Msk (0x40UL)                 /*!< DSP1N0GPIO70 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO69_Pos (5UL)                    /*!< DSP1N0GPIO69 (Bit 5)                                  */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO69_Msk (0x20UL)                 /*!< DSP1N0GPIO69 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO68_Pos (4UL)                    /*!< DSP1N0GPIO68 (Bit 4)                                  */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO68_Msk (0x10UL)                 /*!< DSP1N0GPIO68 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO67_Pos (3UL)                    /*!< DSP1N0GPIO67 (Bit 3)                                  */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO67_Msk (0x8UL)                  /*!< DSP1N0GPIO67 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO66_Pos (2UL)                    /*!< DSP1N0GPIO66 (Bit 2)                                  */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO66_Msk (0x4UL)                  /*!< DSP1N0GPIO66 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO65_Pos (1UL)                    /*!< DSP1N0GPIO65 (Bit 1)                                  */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO65_Msk (0x2UL)                  /*!< DSP1N0GPIO65 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO64_Pos (0UL)                    /*!< DSP1N0GPIO64 (Bit 0)                                  */
#define GPIO_DSP1N0INT2EN_DSP1N0GPIO64_Msk (0x1UL)                  /*!< DSP1N0GPIO64 (Bitfield-Mask: 0x01)                    */
/* ====================================================  DSP1N0INT2STAT  ===================================================== */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO95_Pos (31UL)                 /*!< DSP1N0GPIO95 (Bit 31)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO95_Msk (0x80000000UL)         /*!< DSP1N0GPIO95 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO94_Pos (30UL)                 /*!< DSP1N0GPIO94 (Bit 30)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO94_Msk (0x40000000UL)         /*!< DSP1N0GPIO94 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO93_Pos (29UL)                 /*!< DSP1N0GPIO93 (Bit 29)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO93_Msk (0x20000000UL)         /*!< DSP1N0GPIO93 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO92_Pos (28UL)                 /*!< DSP1N0GPIO92 (Bit 28)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO92_Msk (0x10000000UL)         /*!< DSP1N0GPIO92 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO91_Pos (27UL)                 /*!< DSP1N0GPIO91 (Bit 27)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO91_Msk (0x8000000UL)          /*!< DSP1N0GPIO91 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO90_Pos (26UL)                 /*!< DSP1N0GPIO90 (Bit 26)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO90_Msk (0x4000000UL)          /*!< DSP1N0GPIO90 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO89_Pos (25UL)                 /*!< DSP1N0GPIO89 (Bit 25)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO89_Msk (0x2000000UL)          /*!< DSP1N0GPIO89 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO88_Pos (24UL)                 /*!< DSP1N0GPIO88 (Bit 24)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO88_Msk (0x1000000UL)          /*!< DSP1N0GPIO88 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO87_Pos (23UL)                 /*!< DSP1N0GPIO87 (Bit 23)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO87_Msk (0x800000UL)           /*!< DSP1N0GPIO87 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO86_Pos (22UL)                 /*!< DSP1N0GPIO86 (Bit 22)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO86_Msk (0x400000UL)           /*!< DSP1N0GPIO86 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO85_Pos (21UL)                 /*!< DSP1N0GPIO85 (Bit 21)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO85_Msk (0x200000UL)           /*!< DSP1N0GPIO85 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO84_Pos (20UL)                 /*!< DSP1N0GPIO84 (Bit 20)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO84_Msk (0x100000UL)           /*!< DSP1N0GPIO84 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO83_Pos (19UL)                 /*!< DSP1N0GPIO83 (Bit 19)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO83_Msk (0x80000UL)            /*!< DSP1N0GPIO83 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO82_Pos (18UL)                 /*!< DSP1N0GPIO82 (Bit 18)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO82_Msk (0x40000UL)            /*!< DSP1N0GPIO82 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO81_Pos (17UL)                 /*!< DSP1N0GPIO81 (Bit 17)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO81_Msk (0x20000UL)            /*!< DSP1N0GPIO81 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO80_Pos (16UL)                 /*!< DSP1N0GPIO80 (Bit 16)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO80_Msk (0x10000UL)            /*!< DSP1N0GPIO80 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO79_Pos (15UL)                 /*!< DSP1N0GPIO79 (Bit 15)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO79_Msk (0x8000UL)             /*!< DSP1N0GPIO79 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO78_Pos (14UL)                 /*!< DSP1N0GPIO78 (Bit 14)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO78_Msk (0x4000UL)             /*!< DSP1N0GPIO78 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO77_Pos (13UL)                 /*!< DSP1N0GPIO77 (Bit 13)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO77_Msk (0x2000UL)             /*!< DSP1N0GPIO77 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO76_Pos (12UL)                 /*!< DSP1N0GPIO76 (Bit 12)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO76_Msk (0x1000UL)             /*!< DSP1N0GPIO76 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO75_Pos (11UL)                 /*!< DSP1N0GPIO75 (Bit 11)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO75_Msk (0x800UL)              /*!< DSP1N0GPIO75 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO74_Pos (10UL)                 /*!< DSP1N0GPIO74 (Bit 10)                                 */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO74_Msk (0x400UL)              /*!< DSP1N0GPIO74 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO73_Pos (9UL)                  /*!< DSP1N0GPIO73 (Bit 9)                                  */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO73_Msk (0x200UL)              /*!< DSP1N0GPIO73 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO72_Pos (8UL)                  /*!< DSP1N0GPIO72 (Bit 8)                                  */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO72_Msk (0x100UL)              /*!< DSP1N0GPIO72 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO71_Pos (7UL)                  /*!< DSP1N0GPIO71 (Bit 7)                                  */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO71_Msk (0x80UL)               /*!< DSP1N0GPIO71 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO70_Pos (6UL)                  /*!< DSP1N0GPIO70 (Bit 6)                                  */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO70_Msk (0x40UL)               /*!< DSP1N0GPIO70 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO69_Pos (5UL)                  /*!< DSP1N0GPIO69 (Bit 5)                                  */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO69_Msk (0x20UL)               /*!< DSP1N0GPIO69 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO68_Pos (4UL)                  /*!< DSP1N0GPIO68 (Bit 4)                                  */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO68_Msk (0x10UL)               /*!< DSP1N0GPIO68 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO67_Pos (3UL)                  /*!< DSP1N0GPIO67 (Bit 3)                                  */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO67_Msk (0x8UL)                /*!< DSP1N0GPIO67 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO66_Pos (2UL)                  /*!< DSP1N0GPIO66 (Bit 2)                                  */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO66_Msk (0x4UL)                /*!< DSP1N0GPIO66 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO65_Pos (1UL)                  /*!< DSP1N0GPIO65 (Bit 1)                                  */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO65_Msk (0x2UL)                /*!< DSP1N0GPIO65 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO64_Pos (0UL)                  /*!< DSP1N0GPIO64 (Bit 0)                                  */
#define GPIO_DSP1N0INT2STAT_DSP1N0GPIO64_Msk (0x1UL)                /*!< DSP1N0GPIO64 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1N0INT2CLR  ===================================================== */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO95_Pos (31UL)                  /*!< DSP1N0GPIO95 (Bit 31)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO95_Msk (0x80000000UL)          /*!< DSP1N0GPIO95 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO94_Pos (30UL)                  /*!< DSP1N0GPIO94 (Bit 30)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO94_Msk (0x40000000UL)          /*!< DSP1N0GPIO94 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO93_Pos (29UL)                  /*!< DSP1N0GPIO93 (Bit 29)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO93_Msk (0x20000000UL)          /*!< DSP1N0GPIO93 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO92_Pos (28UL)                  /*!< DSP1N0GPIO92 (Bit 28)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO92_Msk (0x10000000UL)          /*!< DSP1N0GPIO92 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO91_Pos (27UL)                  /*!< DSP1N0GPIO91 (Bit 27)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO91_Msk (0x8000000UL)           /*!< DSP1N0GPIO91 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO90_Pos (26UL)                  /*!< DSP1N0GPIO90 (Bit 26)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO90_Msk (0x4000000UL)           /*!< DSP1N0GPIO90 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO89_Pos (25UL)                  /*!< DSP1N0GPIO89 (Bit 25)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO89_Msk (0x2000000UL)           /*!< DSP1N0GPIO89 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO88_Pos (24UL)                  /*!< DSP1N0GPIO88 (Bit 24)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO88_Msk (0x1000000UL)           /*!< DSP1N0GPIO88 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO87_Pos (23UL)                  /*!< DSP1N0GPIO87 (Bit 23)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO87_Msk (0x800000UL)            /*!< DSP1N0GPIO87 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO86_Pos (22UL)                  /*!< DSP1N0GPIO86 (Bit 22)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO86_Msk (0x400000UL)            /*!< DSP1N0GPIO86 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO85_Pos (21UL)                  /*!< DSP1N0GPIO85 (Bit 21)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO85_Msk (0x200000UL)            /*!< DSP1N0GPIO85 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO84_Pos (20UL)                  /*!< DSP1N0GPIO84 (Bit 20)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO84_Msk (0x100000UL)            /*!< DSP1N0GPIO84 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO83_Pos (19UL)                  /*!< DSP1N0GPIO83 (Bit 19)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO83_Msk (0x80000UL)             /*!< DSP1N0GPIO83 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO82_Pos (18UL)                  /*!< DSP1N0GPIO82 (Bit 18)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO82_Msk (0x40000UL)             /*!< DSP1N0GPIO82 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO81_Pos (17UL)                  /*!< DSP1N0GPIO81 (Bit 17)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO81_Msk (0x20000UL)             /*!< DSP1N0GPIO81 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO80_Pos (16UL)                  /*!< DSP1N0GPIO80 (Bit 16)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO80_Msk (0x10000UL)             /*!< DSP1N0GPIO80 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO79_Pos (15UL)                  /*!< DSP1N0GPIO79 (Bit 15)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO79_Msk (0x8000UL)              /*!< DSP1N0GPIO79 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO78_Pos (14UL)                  /*!< DSP1N0GPIO78 (Bit 14)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO78_Msk (0x4000UL)              /*!< DSP1N0GPIO78 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO77_Pos (13UL)                  /*!< DSP1N0GPIO77 (Bit 13)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO77_Msk (0x2000UL)              /*!< DSP1N0GPIO77 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO76_Pos (12UL)                  /*!< DSP1N0GPIO76 (Bit 12)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO76_Msk (0x1000UL)              /*!< DSP1N0GPIO76 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO75_Pos (11UL)                  /*!< DSP1N0GPIO75 (Bit 11)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO75_Msk (0x800UL)               /*!< DSP1N0GPIO75 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO74_Pos (10UL)                  /*!< DSP1N0GPIO74 (Bit 10)                                 */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO74_Msk (0x400UL)               /*!< DSP1N0GPIO74 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO73_Pos (9UL)                   /*!< DSP1N0GPIO73 (Bit 9)                                  */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO73_Msk (0x200UL)               /*!< DSP1N0GPIO73 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO72_Pos (8UL)                   /*!< DSP1N0GPIO72 (Bit 8)                                  */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO72_Msk (0x100UL)               /*!< DSP1N0GPIO72 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO71_Pos (7UL)                   /*!< DSP1N0GPIO71 (Bit 7)                                  */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO71_Msk (0x80UL)                /*!< DSP1N0GPIO71 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO70_Pos (6UL)                   /*!< DSP1N0GPIO70 (Bit 6)                                  */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO70_Msk (0x40UL)                /*!< DSP1N0GPIO70 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO69_Pos (5UL)                   /*!< DSP1N0GPIO69 (Bit 5)                                  */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO69_Msk (0x20UL)                /*!< DSP1N0GPIO69 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO68_Pos (4UL)                   /*!< DSP1N0GPIO68 (Bit 4)                                  */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO68_Msk (0x10UL)                /*!< DSP1N0GPIO68 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO67_Pos (3UL)                   /*!< DSP1N0GPIO67 (Bit 3)                                  */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO67_Msk (0x8UL)                 /*!< DSP1N0GPIO67 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO66_Pos (2UL)                   /*!< DSP1N0GPIO66 (Bit 2)                                  */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO66_Msk (0x4UL)                 /*!< DSP1N0GPIO66 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO65_Pos (1UL)                   /*!< DSP1N0GPIO65 (Bit 1)                                  */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO65_Msk (0x2UL)                 /*!< DSP1N0GPIO65 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO64_Pos (0UL)                   /*!< DSP1N0GPIO64 (Bit 0)                                  */
#define GPIO_DSP1N0INT2CLR_DSP1N0GPIO64_Msk (0x1UL)                 /*!< DSP1N0GPIO64 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1N0INT2SET  ===================================================== */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO95_Pos (31UL)                  /*!< DSP1N0GPIO95 (Bit 31)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO95_Msk (0x80000000UL)          /*!< DSP1N0GPIO95 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO94_Pos (30UL)                  /*!< DSP1N0GPIO94 (Bit 30)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO94_Msk (0x40000000UL)          /*!< DSP1N0GPIO94 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO93_Pos (29UL)                  /*!< DSP1N0GPIO93 (Bit 29)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO93_Msk (0x20000000UL)          /*!< DSP1N0GPIO93 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO92_Pos (28UL)                  /*!< DSP1N0GPIO92 (Bit 28)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO92_Msk (0x10000000UL)          /*!< DSP1N0GPIO92 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO91_Pos (27UL)                  /*!< DSP1N0GPIO91 (Bit 27)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO91_Msk (0x8000000UL)           /*!< DSP1N0GPIO91 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO90_Pos (26UL)                  /*!< DSP1N0GPIO90 (Bit 26)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO90_Msk (0x4000000UL)           /*!< DSP1N0GPIO90 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO89_Pos (25UL)                  /*!< DSP1N0GPIO89 (Bit 25)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO89_Msk (0x2000000UL)           /*!< DSP1N0GPIO89 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO88_Pos (24UL)                  /*!< DSP1N0GPIO88 (Bit 24)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO88_Msk (0x1000000UL)           /*!< DSP1N0GPIO88 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO87_Pos (23UL)                  /*!< DSP1N0GPIO87 (Bit 23)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO87_Msk (0x800000UL)            /*!< DSP1N0GPIO87 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO86_Pos (22UL)                  /*!< DSP1N0GPIO86 (Bit 22)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO86_Msk (0x400000UL)            /*!< DSP1N0GPIO86 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO85_Pos (21UL)                  /*!< DSP1N0GPIO85 (Bit 21)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO85_Msk (0x200000UL)            /*!< DSP1N0GPIO85 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO84_Pos (20UL)                  /*!< DSP1N0GPIO84 (Bit 20)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO84_Msk (0x100000UL)            /*!< DSP1N0GPIO84 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO83_Pos (19UL)                  /*!< DSP1N0GPIO83 (Bit 19)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO83_Msk (0x80000UL)             /*!< DSP1N0GPIO83 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO82_Pos (18UL)                  /*!< DSP1N0GPIO82 (Bit 18)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO82_Msk (0x40000UL)             /*!< DSP1N0GPIO82 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO81_Pos (17UL)                  /*!< DSP1N0GPIO81 (Bit 17)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO81_Msk (0x20000UL)             /*!< DSP1N0GPIO81 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO80_Pos (16UL)                  /*!< DSP1N0GPIO80 (Bit 16)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO80_Msk (0x10000UL)             /*!< DSP1N0GPIO80 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO79_Pos (15UL)                  /*!< DSP1N0GPIO79 (Bit 15)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO79_Msk (0x8000UL)              /*!< DSP1N0GPIO79 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO78_Pos (14UL)                  /*!< DSP1N0GPIO78 (Bit 14)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO78_Msk (0x4000UL)              /*!< DSP1N0GPIO78 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO77_Pos (13UL)                  /*!< DSP1N0GPIO77 (Bit 13)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO77_Msk (0x2000UL)              /*!< DSP1N0GPIO77 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO76_Pos (12UL)                  /*!< DSP1N0GPIO76 (Bit 12)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO76_Msk (0x1000UL)              /*!< DSP1N0GPIO76 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO75_Pos (11UL)                  /*!< DSP1N0GPIO75 (Bit 11)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO75_Msk (0x800UL)               /*!< DSP1N0GPIO75 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO74_Pos (10UL)                  /*!< DSP1N0GPIO74 (Bit 10)                                 */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO74_Msk (0x400UL)               /*!< DSP1N0GPIO74 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO73_Pos (9UL)                   /*!< DSP1N0GPIO73 (Bit 9)                                  */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO73_Msk (0x200UL)               /*!< DSP1N0GPIO73 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO72_Pos (8UL)                   /*!< DSP1N0GPIO72 (Bit 8)                                  */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO72_Msk (0x100UL)               /*!< DSP1N0GPIO72 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO71_Pos (7UL)                   /*!< DSP1N0GPIO71 (Bit 7)                                  */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO71_Msk (0x80UL)                /*!< DSP1N0GPIO71 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO70_Pos (6UL)                   /*!< DSP1N0GPIO70 (Bit 6)                                  */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO70_Msk (0x40UL)                /*!< DSP1N0GPIO70 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO69_Pos (5UL)                   /*!< DSP1N0GPIO69 (Bit 5)                                  */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO69_Msk (0x20UL)                /*!< DSP1N0GPIO69 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO68_Pos (4UL)                   /*!< DSP1N0GPIO68 (Bit 4)                                  */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO68_Msk (0x10UL)                /*!< DSP1N0GPIO68 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO67_Pos (3UL)                   /*!< DSP1N0GPIO67 (Bit 3)                                  */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO67_Msk (0x8UL)                 /*!< DSP1N0GPIO67 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO66_Pos (2UL)                   /*!< DSP1N0GPIO66 (Bit 2)                                  */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO66_Msk (0x4UL)                 /*!< DSP1N0GPIO66 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO65_Pos (1UL)                   /*!< DSP1N0GPIO65 (Bit 1)                                  */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO65_Msk (0x2UL)                 /*!< DSP1N0GPIO65 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO64_Pos (0UL)                   /*!< DSP1N0GPIO64 (Bit 0)                                  */
#define GPIO_DSP1N0INT2SET_DSP1N0GPIO64_Msk (0x1UL)                 /*!< DSP1N0GPIO64 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1N0INT3EN  ====================================================== */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO127_Pos (31UL)                  /*!< DSP1N0GPIO127 (Bit 31)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO127_Msk (0x80000000UL)          /*!< DSP1N0GPIO127 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO126_Pos (30UL)                  /*!< DSP1N0GPIO126 (Bit 30)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO126_Msk (0x40000000UL)          /*!< DSP1N0GPIO126 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO125_Pos (29UL)                  /*!< DSP1N0GPIO125 (Bit 29)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO125_Msk (0x20000000UL)          /*!< DSP1N0GPIO125 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO124_Pos (28UL)                  /*!< DSP1N0GPIO124 (Bit 28)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO124_Msk (0x10000000UL)          /*!< DSP1N0GPIO124 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO123_Pos (27UL)                  /*!< DSP1N0GPIO123 (Bit 27)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO123_Msk (0x8000000UL)           /*!< DSP1N0GPIO123 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO122_Pos (26UL)                  /*!< DSP1N0GPIO122 (Bit 26)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO122_Msk (0x4000000UL)           /*!< DSP1N0GPIO122 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO121_Pos (25UL)                  /*!< DSP1N0GPIO121 (Bit 25)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO121_Msk (0x2000000UL)           /*!< DSP1N0GPIO121 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO120_Pos (24UL)                  /*!< DSP1N0GPIO120 (Bit 24)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO120_Msk (0x1000000UL)           /*!< DSP1N0GPIO120 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO119_Pos (23UL)                  /*!< DSP1N0GPIO119 (Bit 23)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO119_Msk (0x800000UL)            /*!< DSP1N0GPIO119 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO118_Pos (22UL)                  /*!< DSP1N0GPIO118 (Bit 22)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO118_Msk (0x400000UL)            /*!< DSP1N0GPIO118 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO117_Pos (21UL)                  /*!< DSP1N0GPIO117 (Bit 21)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO117_Msk (0x200000UL)            /*!< DSP1N0GPIO117 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO116_Pos (20UL)                  /*!< DSP1N0GPIO116 (Bit 20)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO116_Msk (0x100000UL)            /*!< DSP1N0GPIO116 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO115_Pos (19UL)                  /*!< DSP1N0GPIO115 (Bit 19)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO115_Msk (0x80000UL)             /*!< DSP1N0GPIO115 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO114_Pos (18UL)                  /*!< DSP1N0GPIO114 (Bit 18)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO114_Msk (0x40000UL)             /*!< DSP1N0GPIO114 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO113_Pos (17UL)                  /*!< DSP1N0GPIO113 (Bit 17)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO113_Msk (0x20000UL)             /*!< DSP1N0GPIO113 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO112_Pos (16UL)                  /*!< DSP1N0GPIO112 (Bit 16)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO112_Msk (0x10000UL)             /*!< DSP1N0GPIO112 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO111_Pos (15UL)                  /*!< DSP1N0GPIO111 (Bit 15)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO111_Msk (0x8000UL)              /*!< DSP1N0GPIO111 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO110_Pos (14UL)                  /*!< DSP1N0GPIO110 (Bit 14)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO110_Msk (0x4000UL)              /*!< DSP1N0GPIO110 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO109_Pos (13UL)                  /*!< DSP1N0GPIO109 (Bit 13)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO109_Msk (0x2000UL)              /*!< DSP1N0GPIO109 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO108_Pos (12UL)                  /*!< DSP1N0GPIO108 (Bit 12)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO108_Msk (0x1000UL)              /*!< DSP1N0GPIO108 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO107_Pos (11UL)                  /*!< DSP1N0GPIO107 (Bit 11)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO107_Msk (0x800UL)               /*!< DSP1N0GPIO107 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO106_Pos (10UL)                  /*!< DSP1N0GPIO106 (Bit 10)                                */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO106_Msk (0x400UL)               /*!< DSP1N0GPIO106 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO105_Pos (9UL)                   /*!< DSP1N0GPIO105 (Bit 9)                                 */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO105_Msk (0x200UL)               /*!< DSP1N0GPIO105 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO104_Pos (8UL)                   /*!< DSP1N0GPIO104 (Bit 8)                                 */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO104_Msk (0x100UL)               /*!< DSP1N0GPIO104 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO103_Pos (7UL)                   /*!< DSP1N0GPIO103 (Bit 7)                                 */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO103_Msk (0x80UL)                /*!< DSP1N0GPIO103 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO102_Pos (6UL)                   /*!< DSP1N0GPIO102 (Bit 6)                                 */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO102_Msk (0x40UL)                /*!< DSP1N0GPIO102 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO101_Pos (5UL)                   /*!< DSP1N0GPIO101 (Bit 5)                                 */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO101_Msk (0x20UL)                /*!< DSP1N0GPIO101 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO100_Pos (4UL)                   /*!< DSP1N0GPIO100 (Bit 4)                                 */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO100_Msk (0x10UL)                /*!< DSP1N0GPIO100 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO99_Pos (3UL)                    /*!< DSP1N0GPIO99 (Bit 3)                                  */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO99_Msk (0x8UL)                  /*!< DSP1N0GPIO99 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO98_Pos (2UL)                    /*!< DSP1N0GPIO98 (Bit 2)                                  */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO98_Msk (0x4UL)                  /*!< DSP1N0GPIO98 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO97_Pos (1UL)                    /*!< DSP1N0GPIO97 (Bit 1)                                  */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO97_Msk (0x2UL)                  /*!< DSP1N0GPIO97 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO96_Pos (0UL)                    /*!< DSP1N0GPIO96 (Bit 0)                                  */
#define GPIO_DSP1N0INT3EN_DSP1N0GPIO96_Msk (0x1UL)                  /*!< DSP1N0GPIO96 (Bitfield-Mask: 0x01)                    */
/* ====================================================  DSP1N0INT3STAT  ===================================================== */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO127_Pos (31UL)                /*!< DSP1N0GPIO127 (Bit 31)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO127_Msk (0x80000000UL)        /*!< DSP1N0GPIO127 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO126_Pos (30UL)                /*!< DSP1N0GPIO126 (Bit 30)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO126_Msk (0x40000000UL)        /*!< DSP1N0GPIO126 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO125_Pos (29UL)                /*!< DSP1N0GPIO125 (Bit 29)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO125_Msk (0x20000000UL)        /*!< DSP1N0GPIO125 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO124_Pos (28UL)                /*!< DSP1N0GPIO124 (Bit 28)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO124_Msk (0x10000000UL)        /*!< DSP1N0GPIO124 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO123_Pos (27UL)                /*!< DSP1N0GPIO123 (Bit 27)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO123_Msk (0x8000000UL)         /*!< DSP1N0GPIO123 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO122_Pos (26UL)                /*!< DSP1N0GPIO122 (Bit 26)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO122_Msk (0x4000000UL)         /*!< DSP1N0GPIO122 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO121_Pos (25UL)                /*!< DSP1N0GPIO121 (Bit 25)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO121_Msk (0x2000000UL)         /*!< DSP1N0GPIO121 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO120_Pos (24UL)                /*!< DSP1N0GPIO120 (Bit 24)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO120_Msk (0x1000000UL)         /*!< DSP1N0GPIO120 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO119_Pos (23UL)                /*!< DSP1N0GPIO119 (Bit 23)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO119_Msk (0x800000UL)          /*!< DSP1N0GPIO119 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO118_Pos (22UL)                /*!< DSP1N0GPIO118 (Bit 22)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO118_Msk (0x400000UL)          /*!< DSP1N0GPIO118 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO117_Pos (21UL)                /*!< DSP1N0GPIO117 (Bit 21)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO117_Msk (0x200000UL)          /*!< DSP1N0GPIO117 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO116_Pos (20UL)                /*!< DSP1N0GPIO116 (Bit 20)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO116_Msk (0x100000UL)          /*!< DSP1N0GPIO116 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO115_Pos (19UL)                /*!< DSP1N0GPIO115 (Bit 19)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO115_Msk (0x80000UL)           /*!< DSP1N0GPIO115 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO114_Pos (18UL)                /*!< DSP1N0GPIO114 (Bit 18)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO114_Msk (0x40000UL)           /*!< DSP1N0GPIO114 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO113_Pos (17UL)                /*!< DSP1N0GPIO113 (Bit 17)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO113_Msk (0x20000UL)           /*!< DSP1N0GPIO113 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO112_Pos (16UL)                /*!< DSP1N0GPIO112 (Bit 16)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO112_Msk (0x10000UL)           /*!< DSP1N0GPIO112 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO111_Pos (15UL)                /*!< DSP1N0GPIO111 (Bit 15)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO111_Msk (0x8000UL)            /*!< DSP1N0GPIO111 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO110_Pos (14UL)                /*!< DSP1N0GPIO110 (Bit 14)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO110_Msk (0x4000UL)            /*!< DSP1N0GPIO110 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO109_Pos (13UL)                /*!< DSP1N0GPIO109 (Bit 13)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO109_Msk (0x2000UL)            /*!< DSP1N0GPIO109 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO108_Pos (12UL)                /*!< DSP1N0GPIO108 (Bit 12)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO108_Msk (0x1000UL)            /*!< DSP1N0GPIO108 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO107_Pos (11UL)                /*!< DSP1N0GPIO107 (Bit 11)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO107_Msk (0x800UL)             /*!< DSP1N0GPIO107 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO106_Pos (10UL)                /*!< DSP1N0GPIO106 (Bit 10)                                */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO106_Msk (0x400UL)             /*!< DSP1N0GPIO106 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO105_Pos (9UL)                 /*!< DSP1N0GPIO105 (Bit 9)                                 */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO105_Msk (0x200UL)             /*!< DSP1N0GPIO105 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO104_Pos (8UL)                 /*!< DSP1N0GPIO104 (Bit 8)                                 */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO104_Msk (0x100UL)             /*!< DSP1N0GPIO104 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO103_Pos (7UL)                 /*!< DSP1N0GPIO103 (Bit 7)                                 */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO103_Msk (0x80UL)              /*!< DSP1N0GPIO103 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO102_Pos (6UL)                 /*!< DSP1N0GPIO102 (Bit 6)                                 */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO102_Msk (0x40UL)              /*!< DSP1N0GPIO102 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO101_Pos (5UL)                 /*!< DSP1N0GPIO101 (Bit 5)                                 */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO101_Msk (0x20UL)              /*!< DSP1N0GPIO101 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO100_Pos (4UL)                 /*!< DSP1N0GPIO100 (Bit 4)                                 */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO100_Msk (0x10UL)              /*!< DSP1N0GPIO100 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO99_Pos (3UL)                  /*!< DSP1N0GPIO99 (Bit 3)                                  */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO99_Msk (0x8UL)                /*!< DSP1N0GPIO99 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO98_Pos (2UL)                  /*!< DSP1N0GPIO98 (Bit 2)                                  */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO98_Msk (0x4UL)                /*!< DSP1N0GPIO98 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO97_Pos (1UL)                  /*!< DSP1N0GPIO97 (Bit 1)                                  */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO97_Msk (0x2UL)                /*!< DSP1N0GPIO97 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO96_Pos (0UL)                  /*!< DSP1N0GPIO96 (Bit 0)                                  */
#define GPIO_DSP1N0INT3STAT_DSP1N0GPIO96_Msk (0x1UL)                /*!< DSP1N0GPIO96 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1N0INT3CLR  ===================================================== */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO127_Pos (31UL)                 /*!< DSP1N0GPIO127 (Bit 31)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO127_Msk (0x80000000UL)         /*!< DSP1N0GPIO127 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO126_Pos (30UL)                 /*!< DSP1N0GPIO126 (Bit 30)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO126_Msk (0x40000000UL)         /*!< DSP1N0GPIO126 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO125_Pos (29UL)                 /*!< DSP1N0GPIO125 (Bit 29)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO125_Msk (0x20000000UL)         /*!< DSP1N0GPIO125 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO124_Pos (28UL)                 /*!< DSP1N0GPIO124 (Bit 28)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO124_Msk (0x10000000UL)         /*!< DSP1N0GPIO124 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO123_Pos (27UL)                 /*!< DSP1N0GPIO123 (Bit 27)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO123_Msk (0x8000000UL)          /*!< DSP1N0GPIO123 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO122_Pos (26UL)                 /*!< DSP1N0GPIO122 (Bit 26)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO122_Msk (0x4000000UL)          /*!< DSP1N0GPIO122 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO121_Pos (25UL)                 /*!< DSP1N0GPIO121 (Bit 25)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO121_Msk (0x2000000UL)          /*!< DSP1N0GPIO121 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO120_Pos (24UL)                 /*!< DSP1N0GPIO120 (Bit 24)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO120_Msk (0x1000000UL)          /*!< DSP1N0GPIO120 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO119_Pos (23UL)                 /*!< DSP1N0GPIO119 (Bit 23)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO119_Msk (0x800000UL)           /*!< DSP1N0GPIO119 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO118_Pos (22UL)                 /*!< DSP1N0GPIO118 (Bit 22)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO118_Msk (0x400000UL)           /*!< DSP1N0GPIO118 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO117_Pos (21UL)                 /*!< DSP1N0GPIO117 (Bit 21)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO117_Msk (0x200000UL)           /*!< DSP1N0GPIO117 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO116_Pos (20UL)                 /*!< DSP1N0GPIO116 (Bit 20)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO116_Msk (0x100000UL)           /*!< DSP1N0GPIO116 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO115_Pos (19UL)                 /*!< DSP1N0GPIO115 (Bit 19)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO115_Msk (0x80000UL)            /*!< DSP1N0GPIO115 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO114_Pos (18UL)                 /*!< DSP1N0GPIO114 (Bit 18)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO114_Msk (0x40000UL)            /*!< DSP1N0GPIO114 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO113_Pos (17UL)                 /*!< DSP1N0GPIO113 (Bit 17)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO113_Msk (0x20000UL)            /*!< DSP1N0GPIO113 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO112_Pos (16UL)                 /*!< DSP1N0GPIO112 (Bit 16)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO112_Msk (0x10000UL)            /*!< DSP1N0GPIO112 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO111_Pos (15UL)                 /*!< DSP1N0GPIO111 (Bit 15)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO111_Msk (0x8000UL)             /*!< DSP1N0GPIO111 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO110_Pos (14UL)                 /*!< DSP1N0GPIO110 (Bit 14)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO110_Msk (0x4000UL)             /*!< DSP1N0GPIO110 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO109_Pos (13UL)                 /*!< DSP1N0GPIO109 (Bit 13)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO109_Msk (0x2000UL)             /*!< DSP1N0GPIO109 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO108_Pos (12UL)                 /*!< DSP1N0GPIO108 (Bit 12)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO108_Msk (0x1000UL)             /*!< DSP1N0GPIO108 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO107_Pos (11UL)                 /*!< DSP1N0GPIO107 (Bit 11)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO107_Msk (0x800UL)              /*!< DSP1N0GPIO107 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO106_Pos (10UL)                 /*!< DSP1N0GPIO106 (Bit 10)                                */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO106_Msk (0x400UL)              /*!< DSP1N0GPIO106 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO105_Pos (9UL)                  /*!< DSP1N0GPIO105 (Bit 9)                                 */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO105_Msk (0x200UL)              /*!< DSP1N0GPIO105 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO104_Pos (8UL)                  /*!< DSP1N0GPIO104 (Bit 8)                                 */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO104_Msk (0x100UL)              /*!< DSP1N0GPIO104 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO103_Pos (7UL)                  /*!< DSP1N0GPIO103 (Bit 7)                                 */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO103_Msk (0x80UL)               /*!< DSP1N0GPIO103 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO102_Pos (6UL)                  /*!< DSP1N0GPIO102 (Bit 6)                                 */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO102_Msk (0x40UL)               /*!< DSP1N0GPIO102 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO101_Pos (5UL)                  /*!< DSP1N0GPIO101 (Bit 5)                                 */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO101_Msk (0x20UL)               /*!< DSP1N0GPIO101 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO100_Pos (4UL)                  /*!< DSP1N0GPIO100 (Bit 4)                                 */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO100_Msk (0x10UL)               /*!< DSP1N0GPIO100 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO99_Pos (3UL)                   /*!< DSP1N0GPIO99 (Bit 3)                                  */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO99_Msk (0x8UL)                 /*!< DSP1N0GPIO99 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO98_Pos (2UL)                   /*!< DSP1N0GPIO98 (Bit 2)                                  */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO98_Msk (0x4UL)                 /*!< DSP1N0GPIO98 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO97_Pos (1UL)                   /*!< DSP1N0GPIO97 (Bit 1)                                  */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO97_Msk (0x2UL)                 /*!< DSP1N0GPIO97 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO96_Pos (0UL)                   /*!< DSP1N0GPIO96 (Bit 0)                                  */
#define GPIO_DSP1N0INT3CLR_DSP1N0GPIO96_Msk (0x1UL)                 /*!< DSP1N0GPIO96 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1N0INT3SET  ===================================================== */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO127_Pos (31UL)                 /*!< DSP1N0GPIO127 (Bit 31)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO127_Msk (0x80000000UL)         /*!< DSP1N0GPIO127 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO126_Pos (30UL)                 /*!< DSP1N0GPIO126 (Bit 30)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO126_Msk (0x40000000UL)         /*!< DSP1N0GPIO126 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO125_Pos (29UL)                 /*!< DSP1N0GPIO125 (Bit 29)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO125_Msk (0x20000000UL)         /*!< DSP1N0GPIO125 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO124_Pos (28UL)                 /*!< DSP1N0GPIO124 (Bit 28)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO124_Msk (0x10000000UL)         /*!< DSP1N0GPIO124 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO123_Pos (27UL)                 /*!< DSP1N0GPIO123 (Bit 27)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO123_Msk (0x8000000UL)          /*!< DSP1N0GPIO123 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO122_Pos (26UL)                 /*!< DSP1N0GPIO122 (Bit 26)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO122_Msk (0x4000000UL)          /*!< DSP1N0GPIO122 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO121_Pos (25UL)                 /*!< DSP1N0GPIO121 (Bit 25)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO121_Msk (0x2000000UL)          /*!< DSP1N0GPIO121 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO120_Pos (24UL)                 /*!< DSP1N0GPIO120 (Bit 24)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO120_Msk (0x1000000UL)          /*!< DSP1N0GPIO120 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO119_Pos (23UL)                 /*!< DSP1N0GPIO119 (Bit 23)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO119_Msk (0x800000UL)           /*!< DSP1N0GPIO119 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO118_Pos (22UL)                 /*!< DSP1N0GPIO118 (Bit 22)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO118_Msk (0x400000UL)           /*!< DSP1N0GPIO118 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO117_Pos (21UL)                 /*!< DSP1N0GPIO117 (Bit 21)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO117_Msk (0x200000UL)           /*!< DSP1N0GPIO117 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO116_Pos (20UL)                 /*!< DSP1N0GPIO116 (Bit 20)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO116_Msk (0x100000UL)           /*!< DSP1N0GPIO116 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO115_Pos (19UL)                 /*!< DSP1N0GPIO115 (Bit 19)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO115_Msk (0x80000UL)            /*!< DSP1N0GPIO115 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO114_Pos (18UL)                 /*!< DSP1N0GPIO114 (Bit 18)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO114_Msk (0x40000UL)            /*!< DSP1N0GPIO114 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO113_Pos (17UL)                 /*!< DSP1N0GPIO113 (Bit 17)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO113_Msk (0x20000UL)            /*!< DSP1N0GPIO113 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO112_Pos (16UL)                 /*!< DSP1N0GPIO112 (Bit 16)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO112_Msk (0x10000UL)            /*!< DSP1N0GPIO112 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO111_Pos (15UL)                 /*!< DSP1N0GPIO111 (Bit 15)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO111_Msk (0x8000UL)             /*!< DSP1N0GPIO111 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO110_Pos (14UL)                 /*!< DSP1N0GPIO110 (Bit 14)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO110_Msk (0x4000UL)             /*!< DSP1N0GPIO110 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO109_Pos (13UL)                 /*!< DSP1N0GPIO109 (Bit 13)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO109_Msk (0x2000UL)             /*!< DSP1N0GPIO109 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO108_Pos (12UL)                 /*!< DSP1N0GPIO108 (Bit 12)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO108_Msk (0x1000UL)             /*!< DSP1N0GPIO108 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO107_Pos (11UL)                 /*!< DSP1N0GPIO107 (Bit 11)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO107_Msk (0x800UL)              /*!< DSP1N0GPIO107 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO106_Pos (10UL)                 /*!< DSP1N0GPIO106 (Bit 10)                                */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO106_Msk (0x400UL)              /*!< DSP1N0GPIO106 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO105_Pos (9UL)                  /*!< DSP1N0GPIO105 (Bit 9)                                 */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO105_Msk (0x200UL)              /*!< DSP1N0GPIO105 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO104_Pos (8UL)                  /*!< DSP1N0GPIO104 (Bit 8)                                 */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO104_Msk (0x100UL)              /*!< DSP1N0GPIO104 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO103_Pos (7UL)                  /*!< DSP1N0GPIO103 (Bit 7)                                 */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO103_Msk (0x80UL)               /*!< DSP1N0GPIO103 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO102_Pos (6UL)                  /*!< DSP1N0GPIO102 (Bit 6)                                 */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO102_Msk (0x40UL)               /*!< DSP1N0GPIO102 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO101_Pos (5UL)                  /*!< DSP1N0GPIO101 (Bit 5)                                 */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO101_Msk (0x20UL)               /*!< DSP1N0GPIO101 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO100_Pos (4UL)                  /*!< DSP1N0GPIO100 (Bit 4)                                 */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO100_Msk (0x10UL)               /*!< DSP1N0GPIO100 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO99_Pos (3UL)                   /*!< DSP1N0GPIO99 (Bit 3)                                  */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO99_Msk (0x8UL)                 /*!< DSP1N0GPIO99 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO98_Pos (2UL)                   /*!< DSP1N0GPIO98 (Bit 2)                                  */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO98_Msk (0x4UL)                 /*!< DSP1N0GPIO98 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO97_Pos (1UL)                   /*!< DSP1N0GPIO97 (Bit 1)                                  */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO97_Msk (0x2UL)                 /*!< DSP1N0GPIO97 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO96_Pos (0UL)                   /*!< DSP1N0GPIO96 (Bit 0)                                  */
#define GPIO_DSP1N0INT3SET_DSP1N0GPIO96_Msk (0x1UL)                 /*!< DSP1N0GPIO96 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1N1INT0EN  ====================================================== */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO31_Pos (31UL)                   /*!< DSP1N1GPIO31 (Bit 31)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO31_Msk (0x80000000UL)           /*!< DSP1N1GPIO31 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO30_Pos (30UL)                   /*!< DSP1N1GPIO30 (Bit 30)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO30_Msk (0x40000000UL)           /*!< DSP1N1GPIO30 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO29_Pos (29UL)                   /*!< DSP1N1GPIO29 (Bit 29)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO29_Msk (0x20000000UL)           /*!< DSP1N1GPIO29 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO28_Pos (28UL)                   /*!< DSP1N1GPIO28 (Bit 28)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO28_Msk (0x10000000UL)           /*!< DSP1N1GPIO28 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO27_Pos (27UL)                   /*!< DSP1N1GPIO27 (Bit 27)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO27_Msk (0x8000000UL)            /*!< DSP1N1GPIO27 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO26_Pos (26UL)                   /*!< DSP1N1GPIO26 (Bit 26)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO26_Msk (0x4000000UL)            /*!< DSP1N1GPIO26 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO25_Pos (25UL)                   /*!< DSP1N1GPIO25 (Bit 25)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO25_Msk (0x2000000UL)            /*!< DSP1N1GPIO25 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO24_Pos (24UL)                   /*!< DSP1N1GPIO24 (Bit 24)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO24_Msk (0x1000000UL)            /*!< DSP1N1GPIO24 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO23_Pos (23UL)                   /*!< DSP1N1GPIO23 (Bit 23)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO23_Msk (0x800000UL)             /*!< DSP1N1GPIO23 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO22_Pos (22UL)                   /*!< DSP1N1GPIO22 (Bit 22)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO22_Msk (0x400000UL)             /*!< DSP1N1GPIO22 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO21_Pos (21UL)                   /*!< DSP1N1GPIO21 (Bit 21)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO21_Msk (0x200000UL)             /*!< DSP1N1GPIO21 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO20_Pos (20UL)                   /*!< DSP1N1GPIO20 (Bit 20)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO20_Msk (0x100000UL)             /*!< DSP1N1GPIO20 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO19_Pos (19UL)                   /*!< DSP1N1GPIO19 (Bit 19)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO19_Msk (0x80000UL)              /*!< DSP1N1GPIO19 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO18_Pos (18UL)                   /*!< DSP1N1GPIO18 (Bit 18)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO18_Msk (0x40000UL)              /*!< DSP1N1GPIO18 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO17_Pos (17UL)                   /*!< DSP1N1GPIO17 (Bit 17)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO17_Msk (0x20000UL)              /*!< DSP1N1GPIO17 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO16_Pos (16UL)                   /*!< DSP1N1GPIO16 (Bit 16)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO16_Msk (0x10000UL)              /*!< DSP1N1GPIO16 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO15_Pos (15UL)                   /*!< DSP1N1GPIO15 (Bit 15)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO15_Msk (0x8000UL)               /*!< DSP1N1GPIO15 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO14_Pos (14UL)                   /*!< DSP1N1GPIO14 (Bit 14)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO14_Msk (0x4000UL)               /*!< DSP1N1GPIO14 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO13_Pos (13UL)                   /*!< DSP1N1GPIO13 (Bit 13)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO13_Msk (0x2000UL)               /*!< DSP1N1GPIO13 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO12_Pos (12UL)                   /*!< DSP1N1GPIO12 (Bit 12)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO12_Msk (0x1000UL)               /*!< DSP1N1GPIO12 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO11_Pos (11UL)                   /*!< DSP1N1GPIO11 (Bit 11)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO11_Msk (0x800UL)                /*!< DSP1N1GPIO11 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO10_Pos (10UL)                   /*!< DSP1N1GPIO10 (Bit 10)                                 */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO10_Msk (0x400UL)                /*!< DSP1N1GPIO10 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO9_Pos (9UL)                     /*!< DSP1N1GPIO9 (Bit 9)                                   */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO9_Msk (0x200UL)                 /*!< DSP1N1GPIO9 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO8_Pos (8UL)                     /*!< DSP1N1GPIO8 (Bit 8)                                   */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO8_Msk (0x100UL)                 /*!< DSP1N1GPIO8 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO7_Pos (7UL)                     /*!< DSP1N1GPIO7 (Bit 7)                                   */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO7_Msk (0x80UL)                  /*!< DSP1N1GPIO7 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO6_Pos (6UL)                     /*!< DSP1N1GPIO6 (Bit 6)                                   */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO6_Msk (0x40UL)                  /*!< DSP1N1GPIO6 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO5_Pos (5UL)                     /*!< DSP1N1GPIO5 (Bit 5)                                   */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO5_Msk (0x20UL)                  /*!< DSP1N1GPIO5 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO4_Pos (4UL)                     /*!< DSP1N1GPIO4 (Bit 4)                                   */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO4_Msk (0x10UL)                  /*!< DSP1N1GPIO4 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO3_Pos (3UL)                     /*!< DSP1N1GPIO3 (Bit 3)                                   */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO3_Msk (0x8UL)                   /*!< DSP1N1GPIO3 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO2_Pos (2UL)                     /*!< DSP1N1GPIO2 (Bit 2)                                   */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO2_Msk (0x4UL)                   /*!< DSP1N1GPIO2 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO1_Pos (1UL)                     /*!< DSP1N1GPIO1 (Bit 1)                                   */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO1_Msk (0x2UL)                   /*!< DSP1N1GPIO1 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO0_Pos (0UL)                     /*!< DSP1N1GPIO0 (Bit 0)                                   */
#define GPIO_DSP1N1INT0EN_DSP1N1GPIO0_Msk (0x1UL)                   /*!< DSP1N1GPIO0 (Bitfield-Mask: 0x01)                     */
/* ====================================================  DSP1N1INT0STAT  ===================================================== */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO31_Pos (31UL)                 /*!< DSP1N1GPIO31 (Bit 31)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO31_Msk (0x80000000UL)         /*!< DSP1N1GPIO31 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO30_Pos (30UL)                 /*!< DSP1N1GPIO30 (Bit 30)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO30_Msk (0x40000000UL)         /*!< DSP1N1GPIO30 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO29_Pos (29UL)                 /*!< DSP1N1GPIO29 (Bit 29)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO29_Msk (0x20000000UL)         /*!< DSP1N1GPIO29 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO28_Pos (28UL)                 /*!< DSP1N1GPIO28 (Bit 28)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO28_Msk (0x10000000UL)         /*!< DSP1N1GPIO28 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO27_Pos (27UL)                 /*!< DSP1N1GPIO27 (Bit 27)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO27_Msk (0x8000000UL)          /*!< DSP1N1GPIO27 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO26_Pos (26UL)                 /*!< DSP1N1GPIO26 (Bit 26)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO26_Msk (0x4000000UL)          /*!< DSP1N1GPIO26 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO25_Pos (25UL)                 /*!< DSP1N1GPIO25 (Bit 25)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO25_Msk (0x2000000UL)          /*!< DSP1N1GPIO25 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO24_Pos (24UL)                 /*!< DSP1N1GPIO24 (Bit 24)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO24_Msk (0x1000000UL)          /*!< DSP1N1GPIO24 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO23_Pos (23UL)                 /*!< DSP1N1GPIO23 (Bit 23)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO23_Msk (0x800000UL)           /*!< DSP1N1GPIO23 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO22_Pos (22UL)                 /*!< DSP1N1GPIO22 (Bit 22)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO22_Msk (0x400000UL)           /*!< DSP1N1GPIO22 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO21_Pos (21UL)                 /*!< DSP1N1GPIO21 (Bit 21)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO21_Msk (0x200000UL)           /*!< DSP1N1GPIO21 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO20_Pos (20UL)                 /*!< DSP1N1GPIO20 (Bit 20)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO20_Msk (0x100000UL)           /*!< DSP1N1GPIO20 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO19_Pos (19UL)                 /*!< DSP1N1GPIO19 (Bit 19)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO19_Msk (0x80000UL)            /*!< DSP1N1GPIO19 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO18_Pos (18UL)                 /*!< DSP1N1GPIO18 (Bit 18)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO18_Msk (0x40000UL)            /*!< DSP1N1GPIO18 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO17_Pos (17UL)                 /*!< DSP1N1GPIO17 (Bit 17)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO17_Msk (0x20000UL)            /*!< DSP1N1GPIO17 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO16_Pos (16UL)                 /*!< DSP1N1GPIO16 (Bit 16)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO16_Msk (0x10000UL)            /*!< DSP1N1GPIO16 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO15_Pos (15UL)                 /*!< DSP1N1GPIO15 (Bit 15)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO15_Msk (0x8000UL)             /*!< DSP1N1GPIO15 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO14_Pos (14UL)                 /*!< DSP1N1GPIO14 (Bit 14)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO14_Msk (0x4000UL)             /*!< DSP1N1GPIO14 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO13_Pos (13UL)                 /*!< DSP1N1GPIO13 (Bit 13)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO13_Msk (0x2000UL)             /*!< DSP1N1GPIO13 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO12_Pos (12UL)                 /*!< DSP1N1GPIO12 (Bit 12)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO12_Msk (0x1000UL)             /*!< DSP1N1GPIO12 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO11_Pos (11UL)                 /*!< DSP1N1GPIO11 (Bit 11)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO11_Msk (0x800UL)              /*!< DSP1N1GPIO11 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO10_Pos (10UL)                 /*!< DSP1N1GPIO10 (Bit 10)                                 */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO10_Msk (0x400UL)              /*!< DSP1N1GPIO10 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO9_Pos (9UL)                   /*!< DSP1N1GPIO9 (Bit 9)                                   */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO9_Msk (0x200UL)               /*!< DSP1N1GPIO9 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO8_Pos (8UL)                   /*!< DSP1N1GPIO8 (Bit 8)                                   */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO8_Msk (0x100UL)               /*!< DSP1N1GPIO8 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO7_Pos (7UL)                   /*!< DSP1N1GPIO7 (Bit 7)                                   */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO7_Msk (0x80UL)                /*!< DSP1N1GPIO7 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO6_Pos (6UL)                   /*!< DSP1N1GPIO6 (Bit 6)                                   */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO6_Msk (0x40UL)                /*!< DSP1N1GPIO6 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO5_Pos (5UL)                   /*!< DSP1N1GPIO5 (Bit 5)                                   */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO5_Msk (0x20UL)                /*!< DSP1N1GPIO5 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO4_Pos (4UL)                   /*!< DSP1N1GPIO4 (Bit 4)                                   */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO4_Msk (0x10UL)                /*!< DSP1N1GPIO4 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO3_Pos (3UL)                   /*!< DSP1N1GPIO3 (Bit 3)                                   */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO3_Msk (0x8UL)                 /*!< DSP1N1GPIO3 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO2_Pos (2UL)                   /*!< DSP1N1GPIO2 (Bit 2)                                   */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO2_Msk (0x4UL)                 /*!< DSP1N1GPIO2 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO1_Pos (1UL)                   /*!< DSP1N1GPIO1 (Bit 1)                                   */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO1_Msk (0x2UL)                 /*!< DSP1N1GPIO1 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO0_Pos (0UL)                   /*!< DSP1N1GPIO0 (Bit 0)                                   */
#define GPIO_DSP1N1INT0STAT_DSP1N1GPIO0_Msk (0x1UL)                 /*!< DSP1N1GPIO0 (Bitfield-Mask: 0x01)                     */
/* =====================================================  DSP1N1INT0CLR  ===================================================== */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO31_Pos (31UL)                  /*!< DSP1N1GPIO31 (Bit 31)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO31_Msk (0x80000000UL)          /*!< DSP1N1GPIO31 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO30_Pos (30UL)                  /*!< DSP1N1GPIO30 (Bit 30)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO30_Msk (0x40000000UL)          /*!< DSP1N1GPIO30 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO29_Pos (29UL)                  /*!< DSP1N1GPIO29 (Bit 29)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO29_Msk (0x20000000UL)          /*!< DSP1N1GPIO29 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO28_Pos (28UL)                  /*!< DSP1N1GPIO28 (Bit 28)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO28_Msk (0x10000000UL)          /*!< DSP1N1GPIO28 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO27_Pos (27UL)                  /*!< DSP1N1GPIO27 (Bit 27)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO27_Msk (0x8000000UL)           /*!< DSP1N1GPIO27 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO26_Pos (26UL)                  /*!< DSP1N1GPIO26 (Bit 26)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO26_Msk (0x4000000UL)           /*!< DSP1N1GPIO26 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO25_Pos (25UL)                  /*!< DSP1N1GPIO25 (Bit 25)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO25_Msk (0x2000000UL)           /*!< DSP1N1GPIO25 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO24_Pos (24UL)                  /*!< DSP1N1GPIO24 (Bit 24)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO24_Msk (0x1000000UL)           /*!< DSP1N1GPIO24 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO23_Pos (23UL)                  /*!< DSP1N1GPIO23 (Bit 23)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO23_Msk (0x800000UL)            /*!< DSP1N1GPIO23 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO22_Pos (22UL)                  /*!< DSP1N1GPIO22 (Bit 22)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO22_Msk (0x400000UL)            /*!< DSP1N1GPIO22 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO21_Pos (21UL)                  /*!< DSP1N1GPIO21 (Bit 21)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO21_Msk (0x200000UL)            /*!< DSP1N1GPIO21 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO20_Pos (20UL)                  /*!< DSP1N1GPIO20 (Bit 20)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO20_Msk (0x100000UL)            /*!< DSP1N1GPIO20 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO19_Pos (19UL)                  /*!< DSP1N1GPIO19 (Bit 19)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO19_Msk (0x80000UL)             /*!< DSP1N1GPIO19 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO18_Pos (18UL)                  /*!< DSP1N1GPIO18 (Bit 18)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO18_Msk (0x40000UL)             /*!< DSP1N1GPIO18 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO17_Pos (17UL)                  /*!< DSP1N1GPIO17 (Bit 17)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO17_Msk (0x20000UL)             /*!< DSP1N1GPIO17 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO16_Pos (16UL)                  /*!< DSP1N1GPIO16 (Bit 16)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO16_Msk (0x10000UL)             /*!< DSP1N1GPIO16 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO15_Pos (15UL)                  /*!< DSP1N1GPIO15 (Bit 15)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO15_Msk (0x8000UL)              /*!< DSP1N1GPIO15 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO14_Pos (14UL)                  /*!< DSP1N1GPIO14 (Bit 14)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO14_Msk (0x4000UL)              /*!< DSP1N1GPIO14 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO13_Pos (13UL)                  /*!< DSP1N1GPIO13 (Bit 13)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO13_Msk (0x2000UL)              /*!< DSP1N1GPIO13 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO12_Pos (12UL)                  /*!< DSP1N1GPIO12 (Bit 12)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO12_Msk (0x1000UL)              /*!< DSP1N1GPIO12 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO11_Pos (11UL)                  /*!< DSP1N1GPIO11 (Bit 11)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO11_Msk (0x800UL)               /*!< DSP1N1GPIO11 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO10_Pos (10UL)                  /*!< DSP1N1GPIO10 (Bit 10)                                 */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO10_Msk (0x400UL)               /*!< DSP1N1GPIO10 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO9_Pos (9UL)                    /*!< DSP1N1GPIO9 (Bit 9)                                   */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO9_Msk (0x200UL)                /*!< DSP1N1GPIO9 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO8_Pos (8UL)                    /*!< DSP1N1GPIO8 (Bit 8)                                   */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO8_Msk (0x100UL)                /*!< DSP1N1GPIO8 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO7_Pos (7UL)                    /*!< DSP1N1GPIO7 (Bit 7)                                   */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO7_Msk (0x80UL)                 /*!< DSP1N1GPIO7 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO6_Pos (6UL)                    /*!< DSP1N1GPIO6 (Bit 6)                                   */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO6_Msk (0x40UL)                 /*!< DSP1N1GPIO6 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO5_Pos (5UL)                    /*!< DSP1N1GPIO5 (Bit 5)                                   */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO5_Msk (0x20UL)                 /*!< DSP1N1GPIO5 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO4_Pos (4UL)                    /*!< DSP1N1GPIO4 (Bit 4)                                   */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO4_Msk (0x10UL)                 /*!< DSP1N1GPIO4 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO3_Pos (3UL)                    /*!< DSP1N1GPIO3 (Bit 3)                                   */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO3_Msk (0x8UL)                  /*!< DSP1N1GPIO3 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO2_Pos (2UL)                    /*!< DSP1N1GPIO2 (Bit 2)                                   */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO2_Msk (0x4UL)                  /*!< DSP1N1GPIO2 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO1_Pos (1UL)                    /*!< DSP1N1GPIO1 (Bit 1)                                   */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO1_Msk (0x2UL)                  /*!< DSP1N1GPIO1 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO0_Pos (0UL)                    /*!< DSP1N1GPIO0 (Bit 0)                                   */
#define GPIO_DSP1N1INT0CLR_DSP1N1GPIO0_Msk (0x1UL)                  /*!< DSP1N1GPIO0 (Bitfield-Mask: 0x01)                     */
/* =====================================================  DSP1N1INT0SET  ===================================================== */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO31_Pos (31UL)                  /*!< DSP1N1GPIO31 (Bit 31)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO31_Msk (0x80000000UL)          /*!< DSP1N1GPIO31 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO30_Pos (30UL)                  /*!< DSP1N1GPIO30 (Bit 30)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO30_Msk (0x40000000UL)          /*!< DSP1N1GPIO30 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO29_Pos (29UL)                  /*!< DSP1N1GPIO29 (Bit 29)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO29_Msk (0x20000000UL)          /*!< DSP1N1GPIO29 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO28_Pos (28UL)                  /*!< DSP1N1GPIO28 (Bit 28)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO28_Msk (0x10000000UL)          /*!< DSP1N1GPIO28 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO27_Pos (27UL)                  /*!< DSP1N1GPIO27 (Bit 27)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO27_Msk (0x8000000UL)           /*!< DSP1N1GPIO27 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO26_Pos (26UL)                  /*!< DSP1N1GPIO26 (Bit 26)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO26_Msk (0x4000000UL)           /*!< DSP1N1GPIO26 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO25_Pos (25UL)                  /*!< DSP1N1GPIO25 (Bit 25)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO25_Msk (0x2000000UL)           /*!< DSP1N1GPIO25 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO24_Pos (24UL)                  /*!< DSP1N1GPIO24 (Bit 24)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO24_Msk (0x1000000UL)           /*!< DSP1N1GPIO24 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO23_Pos (23UL)                  /*!< DSP1N1GPIO23 (Bit 23)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO23_Msk (0x800000UL)            /*!< DSP1N1GPIO23 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO22_Pos (22UL)                  /*!< DSP1N1GPIO22 (Bit 22)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO22_Msk (0x400000UL)            /*!< DSP1N1GPIO22 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO21_Pos (21UL)                  /*!< DSP1N1GPIO21 (Bit 21)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO21_Msk (0x200000UL)            /*!< DSP1N1GPIO21 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO20_Pos (20UL)                  /*!< DSP1N1GPIO20 (Bit 20)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO20_Msk (0x100000UL)            /*!< DSP1N1GPIO20 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO19_Pos (19UL)                  /*!< DSP1N1GPIO19 (Bit 19)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO19_Msk (0x80000UL)             /*!< DSP1N1GPIO19 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO18_Pos (18UL)                  /*!< DSP1N1GPIO18 (Bit 18)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO18_Msk (0x40000UL)             /*!< DSP1N1GPIO18 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO17_Pos (17UL)                  /*!< DSP1N1GPIO17 (Bit 17)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO17_Msk (0x20000UL)             /*!< DSP1N1GPIO17 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO16_Pos (16UL)                  /*!< DSP1N1GPIO16 (Bit 16)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO16_Msk (0x10000UL)             /*!< DSP1N1GPIO16 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO15_Pos (15UL)                  /*!< DSP1N1GPIO15 (Bit 15)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO15_Msk (0x8000UL)              /*!< DSP1N1GPIO15 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO14_Pos (14UL)                  /*!< DSP1N1GPIO14 (Bit 14)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO14_Msk (0x4000UL)              /*!< DSP1N1GPIO14 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO13_Pos (13UL)                  /*!< DSP1N1GPIO13 (Bit 13)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO13_Msk (0x2000UL)              /*!< DSP1N1GPIO13 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO12_Pos (12UL)                  /*!< DSP1N1GPIO12 (Bit 12)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO12_Msk (0x1000UL)              /*!< DSP1N1GPIO12 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO11_Pos (11UL)                  /*!< DSP1N1GPIO11 (Bit 11)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO11_Msk (0x800UL)               /*!< DSP1N1GPIO11 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO10_Pos (10UL)                  /*!< DSP1N1GPIO10 (Bit 10)                                 */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO10_Msk (0x400UL)               /*!< DSP1N1GPIO10 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO9_Pos (9UL)                    /*!< DSP1N1GPIO9 (Bit 9)                                   */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO9_Msk (0x200UL)                /*!< DSP1N1GPIO9 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO8_Pos (8UL)                    /*!< DSP1N1GPIO8 (Bit 8)                                   */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO8_Msk (0x100UL)                /*!< DSP1N1GPIO8 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO7_Pos (7UL)                    /*!< DSP1N1GPIO7 (Bit 7)                                   */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO7_Msk (0x80UL)                 /*!< DSP1N1GPIO7 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO6_Pos (6UL)                    /*!< DSP1N1GPIO6 (Bit 6)                                   */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO6_Msk (0x40UL)                 /*!< DSP1N1GPIO6 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO5_Pos (5UL)                    /*!< DSP1N1GPIO5 (Bit 5)                                   */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO5_Msk (0x20UL)                 /*!< DSP1N1GPIO5 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO4_Pos (4UL)                    /*!< DSP1N1GPIO4 (Bit 4)                                   */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO4_Msk (0x10UL)                 /*!< DSP1N1GPIO4 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO3_Pos (3UL)                    /*!< DSP1N1GPIO3 (Bit 3)                                   */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO3_Msk (0x8UL)                  /*!< DSP1N1GPIO3 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO2_Pos (2UL)                    /*!< DSP1N1GPIO2 (Bit 2)                                   */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO2_Msk (0x4UL)                  /*!< DSP1N1GPIO2 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO1_Pos (1UL)                    /*!< DSP1N1GPIO1 (Bit 1)                                   */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO1_Msk (0x2UL)                  /*!< DSP1N1GPIO1 (Bitfield-Mask: 0x01)                     */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO0_Pos (0UL)                    /*!< DSP1N1GPIO0 (Bit 0)                                   */
#define GPIO_DSP1N1INT0SET_DSP1N1GPIO0_Msk (0x1UL)                  /*!< DSP1N1GPIO0 (Bitfield-Mask: 0x01)                     */
/* =====================================================  DSP1N1INT1EN  ====================================================== */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO63_Pos (31UL)                   /*!< DSP1N1GPIO63 (Bit 31)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO63_Msk (0x80000000UL)           /*!< DSP1N1GPIO63 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO62_Pos (30UL)                   /*!< DSP1N1GPIO62 (Bit 30)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO62_Msk (0x40000000UL)           /*!< DSP1N1GPIO62 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO61_Pos (29UL)                   /*!< DSP1N1GPIO61 (Bit 29)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO61_Msk (0x20000000UL)           /*!< DSP1N1GPIO61 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO60_Pos (28UL)                   /*!< DSP1N1GPIO60 (Bit 28)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO60_Msk (0x10000000UL)           /*!< DSP1N1GPIO60 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO59_Pos (27UL)                   /*!< DSP1N1GPIO59 (Bit 27)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO59_Msk (0x8000000UL)            /*!< DSP1N1GPIO59 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO58_Pos (26UL)                   /*!< DSP1N1GPIO58 (Bit 26)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO58_Msk (0x4000000UL)            /*!< DSP1N1GPIO58 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO57_Pos (25UL)                   /*!< DSP1N1GPIO57 (Bit 25)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO57_Msk (0x2000000UL)            /*!< DSP1N1GPIO57 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO56_Pos (24UL)                   /*!< DSP1N1GPIO56 (Bit 24)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO56_Msk (0x1000000UL)            /*!< DSP1N1GPIO56 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO55_Pos (23UL)                   /*!< DSP1N1GPIO55 (Bit 23)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO55_Msk (0x800000UL)             /*!< DSP1N1GPIO55 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO54_Pos (22UL)                   /*!< DSP1N1GPIO54 (Bit 22)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO54_Msk (0x400000UL)             /*!< DSP1N1GPIO54 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO53_Pos (21UL)                   /*!< DSP1N1GPIO53 (Bit 21)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO53_Msk (0x200000UL)             /*!< DSP1N1GPIO53 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO52_Pos (20UL)                   /*!< DSP1N1GPIO52 (Bit 20)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO52_Msk (0x100000UL)             /*!< DSP1N1GPIO52 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO51_Pos (19UL)                   /*!< DSP1N1GPIO51 (Bit 19)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO51_Msk (0x80000UL)              /*!< DSP1N1GPIO51 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO50_Pos (18UL)                   /*!< DSP1N1GPIO50 (Bit 18)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO50_Msk (0x40000UL)              /*!< DSP1N1GPIO50 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO49_Pos (17UL)                   /*!< DSP1N1GPIO49 (Bit 17)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO49_Msk (0x20000UL)              /*!< DSP1N1GPIO49 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO48_Pos (16UL)                   /*!< DSP1N1GPIO48 (Bit 16)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO48_Msk (0x10000UL)              /*!< DSP1N1GPIO48 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO47_Pos (15UL)                   /*!< DSP1N1GPIO47 (Bit 15)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO47_Msk (0x8000UL)               /*!< DSP1N1GPIO47 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO46_Pos (14UL)                   /*!< DSP1N1GPIO46 (Bit 14)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO46_Msk (0x4000UL)               /*!< DSP1N1GPIO46 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO45_Pos (13UL)                   /*!< DSP1N1GPIO45 (Bit 13)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO45_Msk (0x2000UL)               /*!< DSP1N1GPIO45 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO44_Pos (12UL)                   /*!< DSP1N1GPIO44 (Bit 12)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO44_Msk (0x1000UL)               /*!< DSP1N1GPIO44 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO43_Pos (11UL)                   /*!< DSP1N1GPIO43 (Bit 11)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO43_Msk (0x800UL)                /*!< DSP1N1GPIO43 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO42_Pos (10UL)                   /*!< DSP1N1GPIO42 (Bit 10)                                 */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO42_Msk (0x400UL)                /*!< DSP1N1GPIO42 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO41_Pos (9UL)                    /*!< DSP1N1GPIO41 (Bit 9)                                  */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO41_Msk (0x200UL)                /*!< DSP1N1GPIO41 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO40_Pos (8UL)                    /*!< DSP1N1GPIO40 (Bit 8)                                  */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO40_Msk (0x100UL)                /*!< DSP1N1GPIO40 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO39_Pos (7UL)                    /*!< DSP1N1GPIO39 (Bit 7)                                  */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO39_Msk (0x80UL)                 /*!< DSP1N1GPIO39 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO38_Pos (6UL)                    /*!< DSP1N1GPIO38 (Bit 6)                                  */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO38_Msk (0x40UL)                 /*!< DSP1N1GPIO38 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO37_Pos (5UL)                    /*!< DSP1N1GPIO37 (Bit 5)                                  */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO37_Msk (0x20UL)                 /*!< DSP1N1GPIO37 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO36_Pos (4UL)                    /*!< DSP1N1GPIO36 (Bit 4)                                  */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO36_Msk (0x10UL)                 /*!< DSP1N1GPIO36 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO35_Pos (3UL)                    /*!< DSP1N1GPIO35 (Bit 3)                                  */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO35_Msk (0x8UL)                  /*!< DSP1N1GPIO35 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO34_Pos (2UL)                    /*!< DSP1N1GPIO34 (Bit 2)                                  */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO34_Msk (0x4UL)                  /*!< DSP1N1GPIO34 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO33_Pos (1UL)                    /*!< DSP1N1GPIO33 (Bit 1)                                  */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO33_Msk (0x2UL)                  /*!< DSP1N1GPIO33 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO32_Pos (0UL)                    /*!< DSP1N1GPIO32 (Bit 0)                                  */
#define GPIO_DSP1N1INT1EN_DSP1N1GPIO32_Msk (0x1UL)                  /*!< DSP1N1GPIO32 (Bitfield-Mask: 0x01)                    */
/* ====================================================  DSP1N1INT1STAT  ===================================================== */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO63_Pos (31UL)                 /*!< DSP1N1GPIO63 (Bit 31)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO63_Msk (0x80000000UL)         /*!< DSP1N1GPIO63 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO62_Pos (30UL)                 /*!< DSP1N1GPIO62 (Bit 30)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO62_Msk (0x40000000UL)         /*!< DSP1N1GPIO62 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO61_Pos (29UL)                 /*!< DSP1N1GPIO61 (Bit 29)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO61_Msk (0x20000000UL)         /*!< DSP1N1GPIO61 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO60_Pos (28UL)                 /*!< DSP1N1GPIO60 (Bit 28)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO60_Msk (0x10000000UL)         /*!< DSP1N1GPIO60 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO59_Pos (27UL)                 /*!< DSP1N1GPIO59 (Bit 27)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO59_Msk (0x8000000UL)          /*!< DSP1N1GPIO59 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO58_Pos (26UL)                 /*!< DSP1N1GPIO58 (Bit 26)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO58_Msk (0x4000000UL)          /*!< DSP1N1GPIO58 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO57_Pos (25UL)                 /*!< DSP1N1GPIO57 (Bit 25)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO57_Msk (0x2000000UL)          /*!< DSP1N1GPIO57 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO56_Pos (24UL)                 /*!< DSP1N1GPIO56 (Bit 24)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO56_Msk (0x1000000UL)          /*!< DSP1N1GPIO56 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO55_Pos (23UL)                 /*!< DSP1N1GPIO55 (Bit 23)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO55_Msk (0x800000UL)           /*!< DSP1N1GPIO55 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO54_Pos (22UL)                 /*!< DSP1N1GPIO54 (Bit 22)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO54_Msk (0x400000UL)           /*!< DSP1N1GPIO54 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO53_Pos (21UL)                 /*!< DSP1N1GPIO53 (Bit 21)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO53_Msk (0x200000UL)           /*!< DSP1N1GPIO53 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO52_Pos (20UL)                 /*!< DSP1N1GPIO52 (Bit 20)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO52_Msk (0x100000UL)           /*!< DSP1N1GPIO52 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO51_Pos (19UL)                 /*!< DSP1N1GPIO51 (Bit 19)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO51_Msk (0x80000UL)            /*!< DSP1N1GPIO51 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO50_Pos (18UL)                 /*!< DSP1N1GPIO50 (Bit 18)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO50_Msk (0x40000UL)            /*!< DSP1N1GPIO50 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO49_Pos (17UL)                 /*!< DSP1N1GPIO49 (Bit 17)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO49_Msk (0x20000UL)            /*!< DSP1N1GPIO49 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO48_Pos (16UL)                 /*!< DSP1N1GPIO48 (Bit 16)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO48_Msk (0x10000UL)            /*!< DSP1N1GPIO48 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO47_Pos (15UL)                 /*!< DSP1N1GPIO47 (Bit 15)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO47_Msk (0x8000UL)             /*!< DSP1N1GPIO47 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO46_Pos (14UL)                 /*!< DSP1N1GPIO46 (Bit 14)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO46_Msk (0x4000UL)             /*!< DSP1N1GPIO46 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO45_Pos (13UL)                 /*!< DSP1N1GPIO45 (Bit 13)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO45_Msk (0x2000UL)             /*!< DSP1N1GPIO45 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO44_Pos (12UL)                 /*!< DSP1N1GPIO44 (Bit 12)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO44_Msk (0x1000UL)             /*!< DSP1N1GPIO44 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO43_Pos (11UL)                 /*!< DSP1N1GPIO43 (Bit 11)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO43_Msk (0x800UL)              /*!< DSP1N1GPIO43 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO42_Pos (10UL)                 /*!< DSP1N1GPIO42 (Bit 10)                                 */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO42_Msk (0x400UL)              /*!< DSP1N1GPIO42 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO41_Pos (9UL)                  /*!< DSP1N1GPIO41 (Bit 9)                                  */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO41_Msk (0x200UL)              /*!< DSP1N1GPIO41 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO40_Pos (8UL)                  /*!< DSP1N1GPIO40 (Bit 8)                                  */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO40_Msk (0x100UL)              /*!< DSP1N1GPIO40 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO39_Pos (7UL)                  /*!< DSP1N1GPIO39 (Bit 7)                                  */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO39_Msk (0x80UL)               /*!< DSP1N1GPIO39 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO38_Pos (6UL)                  /*!< DSP1N1GPIO38 (Bit 6)                                  */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO38_Msk (0x40UL)               /*!< DSP1N1GPIO38 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO37_Pos (5UL)                  /*!< DSP1N1GPIO37 (Bit 5)                                  */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO37_Msk (0x20UL)               /*!< DSP1N1GPIO37 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO36_Pos (4UL)                  /*!< DSP1N1GPIO36 (Bit 4)                                  */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO36_Msk (0x10UL)               /*!< DSP1N1GPIO36 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO35_Pos (3UL)                  /*!< DSP1N1GPIO35 (Bit 3)                                  */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO35_Msk (0x8UL)                /*!< DSP1N1GPIO35 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO34_Pos (2UL)                  /*!< DSP1N1GPIO34 (Bit 2)                                  */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO34_Msk (0x4UL)                /*!< DSP1N1GPIO34 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO33_Pos (1UL)                  /*!< DSP1N1GPIO33 (Bit 1)                                  */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO33_Msk (0x2UL)                /*!< DSP1N1GPIO33 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO32_Pos (0UL)                  /*!< DSP1N1GPIO32 (Bit 0)                                  */
#define GPIO_DSP1N1INT1STAT_DSP1N1GPIO32_Msk (0x1UL)                /*!< DSP1N1GPIO32 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1N1INT1CLR  ===================================================== */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO63_Pos (31UL)                  /*!< DSP1N1GPIO63 (Bit 31)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO63_Msk (0x80000000UL)          /*!< DSP1N1GPIO63 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO62_Pos (30UL)                  /*!< DSP1N1GPIO62 (Bit 30)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO62_Msk (0x40000000UL)          /*!< DSP1N1GPIO62 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO61_Pos (29UL)                  /*!< DSP1N1GPIO61 (Bit 29)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO61_Msk (0x20000000UL)          /*!< DSP1N1GPIO61 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO60_Pos (28UL)                  /*!< DSP1N1GPIO60 (Bit 28)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO60_Msk (0x10000000UL)          /*!< DSP1N1GPIO60 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO59_Pos (27UL)                  /*!< DSP1N1GPIO59 (Bit 27)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO59_Msk (0x8000000UL)           /*!< DSP1N1GPIO59 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO58_Pos (26UL)                  /*!< DSP1N1GPIO58 (Bit 26)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO58_Msk (0x4000000UL)           /*!< DSP1N1GPIO58 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO57_Pos (25UL)                  /*!< DSP1N1GPIO57 (Bit 25)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO57_Msk (0x2000000UL)           /*!< DSP1N1GPIO57 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO56_Pos (24UL)                  /*!< DSP1N1GPIO56 (Bit 24)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO56_Msk (0x1000000UL)           /*!< DSP1N1GPIO56 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO55_Pos (23UL)                  /*!< DSP1N1GPIO55 (Bit 23)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO55_Msk (0x800000UL)            /*!< DSP1N1GPIO55 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO54_Pos (22UL)                  /*!< DSP1N1GPIO54 (Bit 22)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO54_Msk (0x400000UL)            /*!< DSP1N1GPIO54 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO53_Pos (21UL)                  /*!< DSP1N1GPIO53 (Bit 21)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO53_Msk (0x200000UL)            /*!< DSP1N1GPIO53 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO52_Pos (20UL)                  /*!< DSP1N1GPIO52 (Bit 20)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO52_Msk (0x100000UL)            /*!< DSP1N1GPIO52 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO51_Pos (19UL)                  /*!< DSP1N1GPIO51 (Bit 19)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO51_Msk (0x80000UL)             /*!< DSP1N1GPIO51 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO50_Pos (18UL)                  /*!< DSP1N1GPIO50 (Bit 18)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO50_Msk (0x40000UL)             /*!< DSP1N1GPIO50 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO49_Pos (17UL)                  /*!< DSP1N1GPIO49 (Bit 17)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO49_Msk (0x20000UL)             /*!< DSP1N1GPIO49 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO48_Pos (16UL)                  /*!< DSP1N1GPIO48 (Bit 16)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO48_Msk (0x10000UL)             /*!< DSP1N1GPIO48 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO47_Pos (15UL)                  /*!< DSP1N1GPIO47 (Bit 15)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO47_Msk (0x8000UL)              /*!< DSP1N1GPIO47 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO46_Pos (14UL)                  /*!< DSP1N1GPIO46 (Bit 14)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO46_Msk (0x4000UL)              /*!< DSP1N1GPIO46 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO45_Pos (13UL)                  /*!< DSP1N1GPIO45 (Bit 13)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO45_Msk (0x2000UL)              /*!< DSP1N1GPIO45 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO44_Pos (12UL)                  /*!< DSP1N1GPIO44 (Bit 12)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO44_Msk (0x1000UL)              /*!< DSP1N1GPIO44 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO43_Pos (11UL)                  /*!< DSP1N1GPIO43 (Bit 11)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO43_Msk (0x800UL)               /*!< DSP1N1GPIO43 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO42_Pos (10UL)                  /*!< DSP1N1GPIO42 (Bit 10)                                 */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO42_Msk (0x400UL)               /*!< DSP1N1GPIO42 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO41_Pos (9UL)                   /*!< DSP1N1GPIO41 (Bit 9)                                  */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO41_Msk (0x200UL)               /*!< DSP1N1GPIO41 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO40_Pos (8UL)                   /*!< DSP1N1GPIO40 (Bit 8)                                  */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO40_Msk (0x100UL)               /*!< DSP1N1GPIO40 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO39_Pos (7UL)                   /*!< DSP1N1GPIO39 (Bit 7)                                  */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO39_Msk (0x80UL)                /*!< DSP1N1GPIO39 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO38_Pos (6UL)                   /*!< DSP1N1GPIO38 (Bit 6)                                  */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO38_Msk (0x40UL)                /*!< DSP1N1GPIO38 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO37_Pos (5UL)                   /*!< DSP1N1GPIO37 (Bit 5)                                  */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO37_Msk (0x20UL)                /*!< DSP1N1GPIO37 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO36_Pos (4UL)                   /*!< DSP1N1GPIO36 (Bit 4)                                  */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO36_Msk (0x10UL)                /*!< DSP1N1GPIO36 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO35_Pos (3UL)                   /*!< DSP1N1GPIO35 (Bit 3)                                  */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO35_Msk (0x8UL)                 /*!< DSP1N1GPIO35 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO34_Pos (2UL)                   /*!< DSP1N1GPIO34 (Bit 2)                                  */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO34_Msk (0x4UL)                 /*!< DSP1N1GPIO34 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO33_Pos (1UL)                   /*!< DSP1N1GPIO33 (Bit 1)                                  */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO33_Msk (0x2UL)                 /*!< DSP1N1GPIO33 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO32_Pos (0UL)                   /*!< DSP1N1GPIO32 (Bit 0)                                  */
#define GPIO_DSP1N1INT1CLR_DSP1N1GPIO32_Msk (0x1UL)                 /*!< DSP1N1GPIO32 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1N1INT1SET  ===================================================== */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO63_Pos (31UL)                  /*!< DSP1N1GPIO63 (Bit 31)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO63_Msk (0x80000000UL)          /*!< DSP1N1GPIO63 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO62_Pos (30UL)                  /*!< DSP1N1GPIO62 (Bit 30)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO62_Msk (0x40000000UL)          /*!< DSP1N1GPIO62 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO61_Pos (29UL)                  /*!< DSP1N1GPIO61 (Bit 29)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO61_Msk (0x20000000UL)          /*!< DSP1N1GPIO61 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO60_Pos (28UL)                  /*!< DSP1N1GPIO60 (Bit 28)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO60_Msk (0x10000000UL)          /*!< DSP1N1GPIO60 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO59_Pos (27UL)                  /*!< DSP1N1GPIO59 (Bit 27)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO59_Msk (0x8000000UL)           /*!< DSP1N1GPIO59 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO58_Pos (26UL)                  /*!< DSP1N1GPIO58 (Bit 26)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO58_Msk (0x4000000UL)           /*!< DSP1N1GPIO58 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO57_Pos (25UL)                  /*!< DSP1N1GPIO57 (Bit 25)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO57_Msk (0x2000000UL)           /*!< DSP1N1GPIO57 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO56_Pos (24UL)                  /*!< DSP1N1GPIO56 (Bit 24)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO56_Msk (0x1000000UL)           /*!< DSP1N1GPIO56 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO55_Pos (23UL)                  /*!< DSP1N1GPIO55 (Bit 23)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO55_Msk (0x800000UL)            /*!< DSP1N1GPIO55 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO54_Pos (22UL)                  /*!< DSP1N1GPIO54 (Bit 22)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO54_Msk (0x400000UL)            /*!< DSP1N1GPIO54 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO53_Pos (21UL)                  /*!< DSP1N1GPIO53 (Bit 21)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO53_Msk (0x200000UL)            /*!< DSP1N1GPIO53 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO52_Pos (20UL)                  /*!< DSP1N1GPIO52 (Bit 20)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO52_Msk (0x100000UL)            /*!< DSP1N1GPIO52 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO51_Pos (19UL)                  /*!< DSP1N1GPIO51 (Bit 19)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO51_Msk (0x80000UL)             /*!< DSP1N1GPIO51 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO50_Pos (18UL)                  /*!< DSP1N1GPIO50 (Bit 18)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO50_Msk (0x40000UL)             /*!< DSP1N1GPIO50 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO49_Pos (17UL)                  /*!< DSP1N1GPIO49 (Bit 17)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO49_Msk (0x20000UL)             /*!< DSP1N1GPIO49 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO48_Pos (16UL)                  /*!< DSP1N1GPIO48 (Bit 16)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO48_Msk (0x10000UL)             /*!< DSP1N1GPIO48 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO47_Pos (15UL)                  /*!< DSP1N1GPIO47 (Bit 15)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO47_Msk (0x8000UL)              /*!< DSP1N1GPIO47 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO46_Pos (14UL)                  /*!< DSP1N1GPIO46 (Bit 14)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO46_Msk (0x4000UL)              /*!< DSP1N1GPIO46 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO45_Pos (13UL)                  /*!< DSP1N1GPIO45 (Bit 13)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO45_Msk (0x2000UL)              /*!< DSP1N1GPIO45 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO44_Pos (12UL)                  /*!< DSP1N1GPIO44 (Bit 12)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO44_Msk (0x1000UL)              /*!< DSP1N1GPIO44 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO43_Pos (11UL)                  /*!< DSP1N1GPIO43 (Bit 11)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO43_Msk (0x800UL)               /*!< DSP1N1GPIO43 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO42_Pos (10UL)                  /*!< DSP1N1GPIO42 (Bit 10)                                 */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO42_Msk (0x400UL)               /*!< DSP1N1GPIO42 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO41_Pos (9UL)                   /*!< DSP1N1GPIO41 (Bit 9)                                  */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO41_Msk (0x200UL)               /*!< DSP1N1GPIO41 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO40_Pos (8UL)                   /*!< DSP1N1GPIO40 (Bit 8)                                  */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO40_Msk (0x100UL)               /*!< DSP1N1GPIO40 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO39_Pos (7UL)                   /*!< DSP1N1GPIO39 (Bit 7)                                  */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO39_Msk (0x80UL)                /*!< DSP1N1GPIO39 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO38_Pos (6UL)                   /*!< DSP1N1GPIO38 (Bit 6)                                  */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO38_Msk (0x40UL)                /*!< DSP1N1GPIO38 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO37_Pos (5UL)                   /*!< DSP1N1GPIO37 (Bit 5)                                  */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO37_Msk (0x20UL)                /*!< DSP1N1GPIO37 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO36_Pos (4UL)                   /*!< DSP1N1GPIO36 (Bit 4)                                  */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO36_Msk (0x10UL)                /*!< DSP1N1GPIO36 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO35_Pos (3UL)                   /*!< DSP1N1GPIO35 (Bit 3)                                  */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO35_Msk (0x8UL)                 /*!< DSP1N1GPIO35 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO34_Pos (2UL)                   /*!< DSP1N1GPIO34 (Bit 2)                                  */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO34_Msk (0x4UL)                 /*!< DSP1N1GPIO34 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO33_Pos (1UL)                   /*!< DSP1N1GPIO33 (Bit 1)                                  */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO33_Msk (0x2UL)                 /*!< DSP1N1GPIO33 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO32_Pos (0UL)                   /*!< DSP1N1GPIO32 (Bit 0)                                  */
#define GPIO_DSP1N1INT1SET_DSP1N1GPIO32_Msk (0x1UL)                 /*!< DSP1N1GPIO32 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1N1INT2EN  ====================================================== */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO95_Pos (31UL)                   /*!< DSP1N1GPIO95 (Bit 31)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO95_Msk (0x80000000UL)           /*!< DSP1N1GPIO95 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO94_Pos (30UL)                   /*!< DSP1N1GPIO94 (Bit 30)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO94_Msk (0x40000000UL)           /*!< DSP1N1GPIO94 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO93_Pos (29UL)                   /*!< DSP1N1GPIO93 (Bit 29)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO93_Msk (0x20000000UL)           /*!< DSP1N1GPIO93 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO92_Pos (28UL)                   /*!< DSP1N1GPIO92 (Bit 28)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO92_Msk (0x10000000UL)           /*!< DSP1N1GPIO92 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO91_Pos (27UL)                   /*!< DSP1N1GPIO91 (Bit 27)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO91_Msk (0x8000000UL)            /*!< DSP1N1GPIO91 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO90_Pos (26UL)                   /*!< DSP1N1GPIO90 (Bit 26)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO90_Msk (0x4000000UL)            /*!< DSP1N1GPIO90 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO89_Pos (25UL)                   /*!< DSP1N1GPIO89 (Bit 25)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO89_Msk (0x2000000UL)            /*!< DSP1N1GPIO89 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO88_Pos (24UL)                   /*!< DSP1N1GPIO88 (Bit 24)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO88_Msk (0x1000000UL)            /*!< DSP1N1GPIO88 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO87_Pos (23UL)                   /*!< DSP1N1GPIO87 (Bit 23)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO87_Msk (0x800000UL)             /*!< DSP1N1GPIO87 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO86_Pos (22UL)                   /*!< DSP1N1GPIO86 (Bit 22)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO86_Msk (0x400000UL)             /*!< DSP1N1GPIO86 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO85_Pos (21UL)                   /*!< DSP1N1GPIO85 (Bit 21)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO85_Msk (0x200000UL)             /*!< DSP1N1GPIO85 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO84_Pos (20UL)                   /*!< DSP1N1GPIO84 (Bit 20)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO84_Msk (0x100000UL)             /*!< DSP1N1GPIO84 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO83_Pos (19UL)                   /*!< DSP1N1GPIO83 (Bit 19)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO83_Msk (0x80000UL)              /*!< DSP1N1GPIO83 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO82_Pos (18UL)                   /*!< DSP1N1GPIO82 (Bit 18)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO82_Msk (0x40000UL)              /*!< DSP1N1GPIO82 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO81_Pos (17UL)                   /*!< DSP1N1GPIO81 (Bit 17)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO81_Msk (0x20000UL)              /*!< DSP1N1GPIO81 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO80_Pos (16UL)                   /*!< DSP1N1GPIO80 (Bit 16)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO80_Msk (0x10000UL)              /*!< DSP1N1GPIO80 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO79_Pos (15UL)                   /*!< DSP1N1GPIO79 (Bit 15)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO79_Msk (0x8000UL)               /*!< DSP1N1GPIO79 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO78_Pos (14UL)                   /*!< DSP1N1GPIO78 (Bit 14)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO78_Msk (0x4000UL)               /*!< DSP1N1GPIO78 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO77_Pos (13UL)                   /*!< DSP1N1GPIO77 (Bit 13)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO77_Msk (0x2000UL)               /*!< DSP1N1GPIO77 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO76_Pos (12UL)                   /*!< DSP1N1GPIO76 (Bit 12)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO76_Msk (0x1000UL)               /*!< DSP1N1GPIO76 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO75_Pos (11UL)                   /*!< DSP1N1GPIO75 (Bit 11)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO75_Msk (0x800UL)                /*!< DSP1N1GPIO75 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO74_Pos (10UL)                   /*!< DSP1N1GPIO74 (Bit 10)                                 */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO74_Msk (0x400UL)                /*!< DSP1N1GPIO74 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO73_Pos (9UL)                    /*!< DSP1N1GPIO73 (Bit 9)                                  */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO73_Msk (0x200UL)                /*!< DSP1N1GPIO73 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO72_Pos (8UL)                    /*!< DSP1N1GPIO72 (Bit 8)                                  */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO72_Msk (0x100UL)                /*!< DSP1N1GPIO72 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO71_Pos (7UL)                    /*!< DSP1N1GPIO71 (Bit 7)                                  */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO71_Msk (0x80UL)                 /*!< DSP1N1GPIO71 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO70_Pos (6UL)                    /*!< DSP1N1GPIO70 (Bit 6)                                  */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO70_Msk (0x40UL)                 /*!< DSP1N1GPIO70 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO69_Pos (5UL)                    /*!< DSP1N1GPIO69 (Bit 5)                                  */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO69_Msk (0x20UL)                 /*!< DSP1N1GPIO69 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO68_Pos (4UL)                    /*!< DSP1N1GPIO68 (Bit 4)                                  */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO68_Msk (0x10UL)                 /*!< DSP1N1GPIO68 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO67_Pos (3UL)                    /*!< DSP1N1GPIO67 (Bit 3)                                  */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO67_Msk (0x8UL)                  /*!< DSP1N1GPIO67 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO66_Pos (2UL)                    /*!< DSP1N1GPIO66 (Bit 2)                                  */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO66_Msk (0x4UL)                  /*!< DSP1N1GPIO66 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO65_Pos (1UL)                    /*!< DSP1N1GPIO65 (Bit 1)                                  */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO65_Msk (0x2UL)                  /*!< DSP1N1GPIO65 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO64_Pos (0UL)                    /*!< DSP1N1GPIO64 (Bit 0)                                  */
#define GPIO_DSP1N1INT2EN_DSP1N1GPIO64_Msk (0x1UL)                  /*!< DSP1N1GPIO64 (Bitfield-Mask: 0x01)                    */
/* ====================================================  DSP1N1INT2STAT  ===================================================== */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO95_Pos (31UL)                 /*!< DSP1N1GPIO95 (Bit 31)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO95_Msk (0x80000000UL)         /*!< DSP1N1GPIO95 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO94_Pos (30UL)                 /*!< DSP1N1GPIO94 (Bit 30)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO94_Msk (0x40000000UL)         /*!< DSP1N1GPIO94 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO93_Pos (29UL)                 /*!< DSP1N1GPIO93 (Bit 29)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO93_Msk (0x20000000UL)         /*!< DSP1N1GPIO93 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO92_Pos (28UL)                 /*!< DSP1N1GPIO92 (Bit 28)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO92_Msk (0x10000000UL)         /*!< DSP1N1GPIO92 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO91_Pos (27UL)                 /*!< DSP1N1GPIO91 (Bit 27)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO91_Msk (0x8000000UL)          /*!< DSP1N1GPIO91 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO90_Pos (26UL)                 /*!< DSP1N1GPIO90 (Bit 26)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO90_Msk (0x4000000UL)          /*!< DSP1N1GPIO90 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO89_Pos (25UL)                 /*!< DSP1N1GPIO89 (Bit 25)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO89_Msk (0x2000000UL)          /*!< DSP1N1GPIO89 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO88_Pos (24UL)                 /*!< DSP1N1GPIO88 (Bit 24)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO88_Msk (0x1000000UL)          /*!< DSP1N1GPIO88 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO87_Pos (23UL)                 /*!< DSP1N1GPIO87 (Bit 23)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO87_Msk (0x800000UL)           /*!< DSP1N1GPIO87 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO86_Pos (22UL)                 /*!< DSP1N1GPIO86 (Bit 22)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO86_Msk (0x400000UL)           /*!< DSP1N1GPIO86 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO85_Pos (21UL)                 /*!< DSP1N1GPIO85 (Bit 21)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO85_Msk (0x200000UL)           /*!< DSP1N1GPIO85 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO84_Pos (20UL)                 /*!< DSP1N1GPIO84 (Bit 20)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO84_Msk (0x100000UL)           /*!< DSP1N1GPIO84 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO83_Pos (19UL)                 /*!< DSP1N1GPIO83 (Bit 19)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO83_Msk (0x80000UL)            /*!< DSP1N1GPIO83 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO82_Pos (18UL)                 /*!< DSP1N1GPIO82 (Bit 18)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO82_Msk (0x40000UL)            /*!< DSP1N1GPIO82 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO81_Pos (17UL)                 /*!< DSP1N1GPIO81 (Bit 17)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO81_Msk (0x20000UL)            /*!< DSP1N1GPIO81 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO80_Pos (16UL)                 /*!< DSP1N1GPIO80 (Bit 16)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO80_Msk (0x10000UL)            /*!< DSP1N1GPIO80 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO79_Pos (15UL)                 /*!< DSP1N1GPIO79 (Bit 15)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO79_Msk (0x8000UL)             /*!< DSP1N1GPIO79 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO78_Pos (14UL)                 /*!< DSP1N1GPIO78 (Bit 14)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO78_Msk (0x4000UL)             /*!< DSP1N1GPIO78 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO77_Pos (13UL)                 /*!< DSP1N1GPIO77 (Bit 13)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO77_Msk (0x2000UL)             /*!< DSP1N1GPIO77 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO76_Pos (12UL)                 /*!< DSP1N1GPIO76 (Bit 12)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO76_Msk (0x1000UL)             /*!< DSP1N1GPIO76 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO75_Pos (11UL)                 /*!< DSP1N1GPIO75 (Bit 11)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO75_Msk (0x800UL)              /*!< DSP1N1GPIO75 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO74_Pos (10UL)                 /*!< DSP1N1GPIO74 (Bit 10)                                 */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO74_Msk (0x400UL)              /*!< DSP1N1GPIO74 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO73_Pos (9UL)                  /*!< DSP1N1GPIO73 (Bit 9)                                  */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO73_Msk (0x200UL)              /*!< DSP1N1GPIO73 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO72_Pos (8UL)                  /*!< DSP1N1GPIO72 (Bit 8)                                  */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO72_Msk (0x100UL)              /*!< DSP1N1GPIO72 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO71_Pos (7UL)                  /*!< DSP1N1GPIO71 (Bit 7)                                  */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO71_Msk (0x80UL)               /*!< DSP1N1GPIO71 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO70_Pos (6UL)                  /*!< DSP1N1GPIO70 (Bit 6)                                  */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO70_Msk (0x40UL)               /*!< DSP1N1GPIO70 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO69_Pos (5UL)                  /*!< DSP1N1GPIO69 (Bit 5)                                  */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO69_Msk (0x20UL)               /*!< DSP1N1GPIO69 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO68_Pos (4UL)                  /*!< DSP1N1GPIO68 (Bit 4)                                  */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO68_Msk (0x10UL)               /*!< DSP1N1GPIO68 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO67_Pos (3UL)                  /*!< DSP1N1GPIO67 (Bit 3)                                  */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO67_Msk (0x8UL)                /*!< DSP1N1GPIO67 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO66_Pos (2UL)                  /*!< DSP1N1GPIO66 (Bit 2)                                  */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO66_Msk (0x4UL)                /*!< DSP1N1GPIO66 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO65_Pos (1UL)                  /*!< DSP1N1GPIO65 (Bit 1)                                  */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO65_Msk (0x2UL)                /*!< DSP1N1GPIO65 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO64_Pos (0UL)                  /*!< DSP1N1GPIO64 (Bit 0)                                  */
#define GPIO_DSP1N1INT2STAT_DSP1N1GPIO64_Msk (0x1UL)                /*!< DSP1N1GPIO64 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1N1INT2CLR  ===================================================== */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO95_Pos (31UL)                  /*!< DSP1N1GPIO95 (Bit 31)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO95_Msk (0x80000000UL)          /*!< DSP1N1GPIO95 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO94_Pos (30UL)                  /*!< DSP1N1GPIO94 (Bit 30)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO94_Msk (0x40000000UL)          /*!< DSP1N1GPIO94 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO93_Pos (29UL)                  /*!< DSP1N1GPIO93 (Bit 29)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO93_Msk (0x20000000UL)          /*!< DSP1N1GPIO93 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO92_Pos (28UL)                  /*!< DSP1N1GPIO92 (Bit 28)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO92_Msk (0x10000000UL)          /*!< DSP1N1GPIO92 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO91_Pos (27UL)                  /*!< DSP1N1GPIO91 (Bit 27)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO91_Msk (0x8000000UL)           /*!< DSP1N1GPIO91 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO90_Pos (26UL)                  /*!< DSP1N1GPIO90 (Bit 26)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO90_Msk (0x4000000UL)           /*!< DSP1N1GPIO90 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO89_Pos (25UL)                  /*!< DSP1N1GPIO89 (Bit 25)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO89_Msk (0x2000000UL)           /*!< DSP1N1GPIO89 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO88_Pos (24UL)                  /*!< DSP1N1GPIO88 (Bit 24)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO88_Msk (0x1000000UL)           /*!< DSP1N1GPIO88 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO87_Pos (23UL)                  /*!< DSP1N1GPIO87 (Bit 23)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO87_Msk (0x800000UL)            /*!< DSP1N1GPIO87 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO86_Pos (22UL)                  /*!< DSP1N1GPIO86 (Bit 22)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO86_Msk (0x400000UL)            /*!< DSP1N1GPIO86 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO85_Pos (21UL)                  /*!< DSP1N1GPIO85 (Bit 21)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO85_Msk (0x200000UL)            /*!< DSP1N1GPIO85 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO84_Pos (20UL)                  /*!< DSP1N1GPIO84 (Bit 20)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO84_Msk (0x100000UL)            /*!< DSP1N1GPIO84 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO83_Pos (19UL)                  /*!< DSP1N1GPIO83 (Bit 19)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO83_Msk (0x80000UL)             /*!< DSP1N1GPIO83 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO82_Pos (18UL)                  /*!< DSP1N1GPIO82 (Bit 18)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO82_Msk (0x40000UL)             /*!< DSP1N1GPIO82 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO81_Pos (17UL)                  /*!< DSP1N1GPIO81 (Bit 17)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO81_Msk (0x20000UL)             /*!< DSP1N1GPIO81 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO80_Pos (16UL)                  /*!< DSP1N1GPIO80 (Bit 16)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO80_Msk (0x10000UL)             /*!< DSP1N1GPIO80 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO79_Pos (15UL)                  /*!< DSP1N1GPIO79 (Bit 15)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO79_Msk (0x8000UL)              /*!< DSP1N1GPIO79 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO78_Pos (14UL)                  /*!< DSP1N1GPIO78 (Bit 14)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO78_Msk (0x4000UL)              /*!< DSP1N1GPIO78 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO77_Pos (13UL)                  /*!< DSP1N1GPIO77 (Bit 13)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO77_Msk (0x2000UL)              /*!< DSP1N1GPIO77 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO76_Pos (12UL)                  /*!< DSP1N1GPIO76 (Bit 12)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO76_Msk (0x1000UL)              /*!< DSP1N1GPIO76 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO75_Pos (11UL)                  /*!< DSP1N1GPIO75 (Bit 11)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO75_Msk (0x800UL)               /*!< DSP1N1GPIO75 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO74_Pos (10UL)                  /*!< DSP1N1GPIO74 (Bit 10)                                 */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO74_Msk (0x400UL)               /*!< DSP1N1GPIO74 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO73_Pos (9UL)                   /*!< DSP1N1GPIO73 (Bit 9)                                  */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO73_Msk (0x200UL)               /*!< DSP1N1GPIO73 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO72_Pos (8UL)                   /*!< DSP1N1GPIO72 (Bit 8)                                  */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO72_Msk (0x100UL)               /*!< DSP1N1GPIO72 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO71_Pos (7UL)                   /*!< DSP1N1GPIO71 (Bit 7)                                  */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO71_Msk (0x80UL)                /*!< DSP1N1GPIO71 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO70_Pos (6UL)                   /*!< DSP1N1GPIO70 (Bit 6)                                  */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO70_Msk (0x40UL)                /*!< DSP1N1GPIO70 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO69_Pos (5UL)                   /*!< DSP1N1GPIO69 (Bit 5)                                  */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO69_Msk (0x20UL)                /*!< DSP1N1GPIO69 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO68_Pos (4UL)                   /*!< DSP1N1GPIO68 (Bit 4)                                  */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO68_Msk (0x10UL)                /*!< DSP1N1GPIO68 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO67_Pos (3UL)                   /*!< DSP1N1GPIO67 (Bit 3)                                  */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO67_Msk (0x8UL)                 /*!< DSP1N1GPIO67 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO66_Pos (2UL)                   /*!< DSP1N1GPIO66 (Bit 2)                                  */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO66_Msk (0x4UL)                 /*!< DSP1N1GPIO66 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO65_Pos (1UL)                   /*!< DSP1N1GPIO65 (Bit 1)                                  */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO65_Msk (0x2UL)                 /*!< DSP1N1GPIO65 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO64_Pos (0UL)                   /*!< DSP1N1GPIO64 (Bit 0)                                  */
#define GPIO_DSP1N1INT2CLR_DSP1N1GPIO64_Msk (0x1UL)                 /*!< DSP1N1GPIO64 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1N1INT2SET  ===================================================== */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO95_Pos (31UL)                  /*!< DSP1N1GPIO95 (Bit 31)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO95_Msk (0x80000000UL)          /*!< DSP1N1GPIO95 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO94_Pos (30UL)                  /*!< DSP1N1GPIO94 (Bit 30)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO94_Msk (0x40000000UL)          /*!< DSP1N1GPIO94 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO93_Pos (29UL)                  /*!< DSP1N1GPIO93 (Bit 29)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO93_Msk (0x20000000UL)          /*!< DSP1N1GPIO93 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO92_Pos (28UL)                  /*!< DSP1N1GPIO92 (Bit 28)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO92_Msk (0x10000000UL)          /*!< DSP1N1GPIO92 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO91_Pos (27UL)                  /*!< DSP1N1GPIO91 (Bit 27)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO91_Msk (0x8000000UL)           /*!< DSP1N1GPIO91 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO90_Pos (26UL)                  /*!< DSP1N1GPIO90 (Bit 26)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO90_Msk (0x4000000UL)           /*!< DSP1N1GPIO90 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO89_Pos (25UL)                  /*!< DSP1N1GPIO89 (Bit 25)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO89_Msk (0x2000000UL)           /*!< DSP1N1GPIO89 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO88_Pos (24UL)                  /*!< DSP1N1GPIO88 (Bit 24)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO88_Msk (0x1000000UL)           /*!< DSP1N1GPIO88 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO87_Pos (23UL)                  /*!< DSP1N1GPIO87 (Bit 23)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO87_Msk (0x800000UL)            /*!< DSP1N1GPIO87 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO86_Pos (22UL)                  /*!< DSP1N1GPIO86 (Bit 22)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO86_Msk (0x400000UL)            /*!< DSP1N1GPIO86 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO85_Pos (21UL)                  /*!< DSP1N1GPIO85 (Bit 21)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO85_Msk (0x200000UL)            /*!< DSP1N1GPIO85 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO84_Pos (20UL)                  /*!< DSP1N1GPIO84 (Bit 20)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO84_Msk (0x100000UL)            /*!< DSP1N1GPIO84 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO83_Pos (19UL)                  /*!< DSP1N1GPIO83 (Bit 19)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO83_Msk (0x80000UL)             /*!< DSP1N1GPIO83 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO82_Pos (18UL)                  /*!< DSP1N1GPIO82 (Bit 18)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO82_Msk (0x40000UL)             /*!< DSP1N1GPIO82 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO81_Pos (17UL)                  /*!< DSP1N1GPIO81 (Bit 17)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO81_Msk (0x20000UL)             /*!< DSP1N1GPIO81 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO80_Pos (16UL)                  /*!< DSP1N1GPIO80 (Bit 16)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO80_Msk (0x10000UL)             /*!< DSP1N1GPIO80 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO79_Pos (15UL)                  /*!< DSP1N1GPIO79 (Bit 15)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO79_Msk (0x8000UL)              /*!< DSP1N1GPIO79 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO78_Pos (14UL)                  /*!< DSP1N1GPIO78 (Bit 14)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO78_Msk (0x4000UL)              /*!< DSP1N1GPIO78 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO77_Pos (13UL)                  /*!< DSP1N1GPIO77 (Bit 13)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO77_Msk (0x2000UL)              /*!< DSP1N1GPIO77 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO76_Pos (12UL)                  /*!< DSP1N1GPIO76 (Bit 12)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO76_Msk (0x1000UL)              /*!< DSP1N1GPIO76 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO75_Pos (11UL)                  /*!< DSP1N1GPIO75 (Bit 11)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO75_Msk (0x800UL)               /*!< DSP1N1GPIO75 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO74_Pos (10UL)                  /*!< DSP1N1GPIO74 (Bit 10)                                 */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO74_Msk (0x400UL)               /*!< DSP1N1GPIO74 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO73_Pos (9UL)                   /*!< DSP1N1GPIO73 (Bit 9)                                  */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO73_Msk (0x200UL)               /*!< DSP1N1GPIO73 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO72_Pos (8UL)                   /*!< DSP1N1GPIO72 (Bit 8)                                  */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO72_Msk (0x100UL)               /*!< DSP1N1GPIO72 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO71_Pos (7UL)                   /*!< DSP1N1GPIO71 (Bit 7)                                  */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO71_Msk (0x80UL)                /*!< DSP1N1GPIO71 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO70_Pos (6UL)                   /*!< DSP1N1GPIO70 (Bit 6)                                  */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO70_Msk (0x40UL)                /*!< DSP1N1GPIO70 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO69_Pos (5UL)                   /*!< DSP1N1GPIO69 (Bit 5)                                  */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO69_Msk (0x20UL)                /*!< DSP1N1GPIO69 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO68_Pos (4UL)                   /*!< DSP1N1GPIO68 (Bit 4)                                  */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO68_Msk (0x10UL)                /*!< DSP1N1GPIO68 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO67_Pos (3UL)                   /*!< DSP1N1GPIO67 (Bit 3)                                  */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO67_Msk (0x8UL)                 /*!< DSP1N1GPIO67 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO66_Pos (2UL)                   /*!< DSP1N1GPIO66 (Bit 2)                                  */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO66_Msk (0x4UL)                 /*!< DSP1N1GPIO66 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO65_Pos (1UL)                   /*!< DSP1N1GPIO65 (Bit 1)                                  */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO65_Msk (0x2UL)                 /*!< DSP1N1GPIO65 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO64_Pos (0UL)                   /*!< DSP1N1GPIO64 (Bit 0)                                  */
#define GPIO_DSP1N1INT2SET_DSP1N1GPIO64_Msk (0x1UL)                 /*!< DSP1N1GPIO64 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1N1INT3EN  ====================================================== */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO127_Pos (31UL)                  /*!< DSP1N1GPIO127 (Bit 31)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO127_Msk (0x80000000UL)          /*!< DSP1N1GPIO127 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO126_Pos (30UL)                  /*!< DSP1N1GPIO126 (Bit 30)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO126_Msk (0x40000000UL)          /*!< DSP1N1GPIO126 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO125_Pos (29UL)                  /*!< DSP1N1GPIO125 (Bit 29)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO125_Msk (0x20000000UL)          /*!< DSP1N1GPIO125 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO124_Pos (28UL)                  /*!< DSP1N1GPIO124 (Bit 28)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO124_Msk (0x10000000UL)          /*!< DSP1N1GPIO124 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO123_Pos (27UL)                  /*!< DSP1N1GPIO123 (Bit 27)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO123_Msk (0x8000000UL)           /*!< DSP1N1GPIO123 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO122_Pos (26UL)                  /*!< DSP1N1GPIO122 (Bit 26)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO122_Msk (0x4000000UL)           /*!< DSP1N1GPIO122 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO121_Pos (25UL)                  /*!< DSP1N1GPIO121 (Bit 25)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO121_Msk (0x2000000UL)           /*!< DSP1N1GPIO121 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO120_Pos (24UL)                  /*!< DSP1N1GPIO120 (Bit 24)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO120_Msk (0x1000000UL)           /*!< DSP1N1GPIO120 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO119_Pos (23UL)                  /*!< DSP1N1GPIO119 (Bit 23)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO119_Msk (0x800000UL)            /*!< DSP1N1GPIO119 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO118_Pos (22UL)                  /*!< DSP1N1GPIO118 (Bit 22)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO118_Msk (0x400000UL)            /*!< DSP1N1GPIO118 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO117_Pos (21UL)                  /*!< DSP1N1GPIO117 (Bit 21)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO117_Msk (0x200000UL)            /*!< DSP1N1GPIO117 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO116_Pos (20UL)                  /*!< DSP1N1GPIO116 (Bit 20)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO116_Msk (0x100000UL)            /*!< DSP1N1GPIO116 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO115_Pos (19UL)                  /*!< DSP1N1GPIO115 (Bit 19)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO115_Msk (0x80000UL)             /*!< DSP1N1GPIO115 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO114_Pos (18UL)                  /*!< DSP1N1GPIO114 (Bit 18)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO114_Msk (0x40000UL)             /*!< DSP1N1GPIO114 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO113_Pos (17UL)                  /*!< DSP1N1GPIO113 (Bit 17)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO113_Msk (0x20000UL)             /*!< DSP1N1GPIO113 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO112_Pos (16UL)                  /*!< DSP1N1GPIO112 (Bit 16)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO112_Msk (0x10000UL)             /*!< DSP1N1GPIO112 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO111_Pos (15UL)                  /*!< DSP1N1GPIO111 (Bit 15)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO111_Msk (0x8000UL)              /*!< DSP1N1GPIO111 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO110_Pos (14UL)                  /*!< DSP1N1GPIO110 (Bit 14)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO110_Msk (0x4000UL)              /*!< DSP1N1GPIO110 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO109_Pos (13UL)                  /*!< DSP1N1GPIO109 (Bit 13)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO109_Msk (0x2000UL)              /*!< DSP1N1GPIO109 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO108_Pos (12UL)                  /*!< DSP1N1GPIO108 (Bit 12)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO108_Msk (0x1000UL)              /*!< DSP1N1GPIO108 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO107_Pos (11UL)                  /*!< DSP1N1GPIO107 (Bit 11)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO107_Msk (0x800UL)               /*!< DSP1N1GPIO107 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO106_Pos (10UL)                  /*!< DSP1N1GPIO106 (Bit 10)                                */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO106_Msk (0x400UL)               /*!< DSP1N1GPIO106 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO105_Pos (9UL)                   /*!< DSP1N1GPIO105 (Bit 9)                                 */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO105_Msk (0x200UL)               /*!< DSP1N1GPIO105 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO104_Pos (8UL)                   /*!< DSP1N1GPIO104 (Bit 8)                                 */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO104_Msk (0x100UL)               /*!< DSP1N1GPIO104 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO103_Pos (7UL)                   /*!< DSP1N1GPIO103 (Bit 7)                                 */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO103_Msk (0x80UL)                /*!< DSP1N1GPIO103 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO102_Pos (6UL)                   /*!< DSP1N1GPIO102 (Bit 6)                                 */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO102_Msk (0x40UL)                /*!< DSP1N1GPIO102 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO101_Pos (5UL)                   /*!< DSP1N1GPIO101 (Bit 5)                                 */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO101_Msk (0x20UL)                /*!< DSP1N1GPIO101 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO100_Pos (4UL)                   /*!< DSP1N1GPIO100 (Bit 4)                                 */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO100_Msk (0x10UL)                /*!< DSP1N1GPIO100 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO99_Pos (3UL)                    /*!< DSP1N1GPIO99 (Bit 3)                                  */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO99_Msk (0x8UL)                  /*!< DSP1N1GPIO99 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO98_Pos (2UL)                    /*!< DSP1N1GPIO98 (Bit 2)                                  */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO98_Msk (0x4UL)                  /*!< DSP1N1GPIO98 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO97_Pos (1UL)                    /*!< DSP1N1GPIO97 (Bit 1)                                  */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO97_Msk (0x2UL)                  /*!< DSP1N1GPIO97 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO96_Pos (0UL)                    /*!< DSP1N1GPIO96 (Bit 0)                                  */
#define GPIO_DSP1N1INT3EN_DSP1N1GPIO96_Msk (0x1UL)                  /*!< DSP1N1GPIO96 (Bitfield-Mask: 0x01)                    */
/* ====================================================  DSP1N1INT3STAT  ===================================================== */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO127_Pos (31UL)                /*!< DSP1N1GPIO127 (Bit 31)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO127_Msk (0x80000000UL)        /*!< DSP1N1GPIO127 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO126_Pos (30UL)                /*!< DSP1N1GPIO126 (Bit 30)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO126_Msk (0x40000000UL)        /*!< DSP1N1GPIO126 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO125_Pos (29UL)                /*!< DSP1N1GPIO125 (Bit 29)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO125_Msk (0x20000000UL)        /*!< DSP1N1GPIO125 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO124_Pos (28UL)                /*!< DSP1N1GPIO124 (Bit 28)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO124_Msk (0x10000000UL)        /*!< DSP1N1GPIO124 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO123_Pos (27UL)                /*!< DSP1N1GPIO123 (Bit 27)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO123_Msk (0x8000000UL)         /*!< DSP1N1GPIO123 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO122_Pos (26UL)                /*!< DSP1N1GPIO122 (Bit 26)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO122_Msk (0x4000000UL)         /*!< DSP1N1GPIO122 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO121_Pos (25UL)                /*!< DSP1N1GPIO121 (Bit 25)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO121_Msk (0x2000000UL)         /*!< DSP1N1GPIO121 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO120_Pos (24UL)                /*!< DSP1N1GPIO120 (Bit 24)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO120_Msk (0x1000000UL)         /*!< DSP1N1GPIO120 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO119_Pos (23UL)                /*!< DSP1N1GPIO119 (Bit 23)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO119_Msk (0x800000UL)          /*!< DSP1N1GPIO119 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO118_Pos (22UL)                /*!< DSP1N1GPIO118 (Bit 22)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO118_Msk (0x400000UL)          /*!< DSP1N1GPIO118 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO117_Pos (21UL)                /*!< DSP1N1GPIO117 (Bit 21)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO117_Msk (0x200000UL)          /*!< DSP1N1GPIO117 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO116_Pos (20UL)                /*!< DSP1N1GPIO116 (Bit 20)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO116_Msk (0x100000UL)          /*!< DSP1N1GPIO116 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO115_Pos (19UL)                /*!< DSP1N1GPIO115 (Bit 19)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO115_Msk (0x80000UL)           /*!< DSP1N1GPIO115 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO114_Pos (18UL)                /*!< DSP1N1GPIO114 (Bit 18)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO114_Msk (0x40000UL)           /*!< DSP1N1GPIO114 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO113_Pos (17UL)                /*!< DSP1N1GPIO113 (Bit 17)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO113_Msk (0x20000UL)           /*!< DSP1N1GPIO113 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO112_Pos (16UL)                /*!< DSP1N1GPIO112 (Bit 16)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO112_Msk (0x10000UL)           /*!< DSP1N1GPIO112 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO111_Pos (15UL)                /*!< DSP1N1GPIO111 (Bit 15)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO111_Msk (0x8000UL)            /*!< DSP1N1GPIO111 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO110_Pos (14UL)                /*!< DSP1N1GPIO110 (Bit 14)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO110_Msk (0x4000UL)            /*!< DSP1N1GPIO110 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO109_Pos (13UL)                /*!< DSP1N1GPIO109 (Bit 13)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO109_Msk (0x2000UL)            /*!< DSP1N1GPIO109 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO108_Pos (12UL)                /*!< DSP1N1GPIO108 (Bit 12)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO108_Msk (0x1000UL)            /*!< DSP1N1GPIO108 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO107_Pos (11UL)                /*!< DSP1N1GPIO107 (Bit 11)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO107_Msk (0x800UL)             /*!< DSP1N1GPIO107 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO106_Pos (10UL)                /*!< DSP1N1GPIO106 (Bit 10)                                */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO106_Msk (0x400UL)             /*!< DSP1N1GPIO106 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO105_Pos (9UL)                 /*!< DSP1N1GPIO105 (Bit 9)                                 */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO105_Msk (0x200UL)             /*!< DSP1N1GPIO105 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO104_Pos (8UL)                 /*!< DSP1N1GPIO104 (Bit 8)                                 */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO104_Msk (0x100UL)             /*!< DSP1N1GPIO104 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO103_Pos (7UL)                 /*!< DSP1N1GPIO103 (Bit 7)                                 */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO103_Msk (0x80UL)              /*!< DSP1N1GPIO103 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO102_Pos (6UL)                 /*!< DSP1N1GPIO102 (Bit 6)                                 */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO102_Msk (0x40UL)              /*!< DSP1N1GPIO102 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO101_Pos (5UL)                 /*!< DSP1N1GPIO101 (Bit 5)                                 */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO101_Msk (0x20UL)              /*!< DSP1N1GPIO101 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO100_Pos (4UL)                 /*!< DSP1N1GPIO100 (Bit 4)                                 */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO100_Msk (0x10UL)              /*!< DSP1N1GPIO100 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO99_Pos (3UL)                  /*!< DSP1N1GPIO99 (Bit 3)                                  */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO99_Msk (0x8UL)                /*!< DSP1N1GPIO99 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO98_Pos (2UL)                  /*!< DSP1N1GPIO98 (Bit 2)                                  */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO98_Msk (0x4UL)                /*!< DSP1N1GPIO98 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO97_Pos (1UL)                  /*!< DSP1N1GPIO97 (Bit 1)                                  */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO97_Msk (0x2UL)                /*!< DSP1N1GPIO97 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO96_Pos (0UL)                  /*!< DSP1N1GPIO96 (Bit 0)                                  */
#define GPIO_DSP1N1INT3STAT_DSP1N1GPIO96_Msk (0x1UL)                /*!< DSP1N1GPIO96 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1N1INT3CLR  ===================================================== */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO127_Pos (31UL)                 /*!< DSP1N1GPIO127 (Bit 31)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO127_Msk (0x80000000UL)         /*!< DSP1N1GPIO127 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO126_Pos (30UL)                 /*!< DSP1N1GPIO126 (Bit 30)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO126_Msk (0x40000000UL)         /*!< DSP1N1GPIO126 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO125_Pos (29UL)                 /*!< DSP1N1GPIO125 (Bit 29)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO125_Msk (0x20000000UL)         /*!< DSP1N1GPIO125 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO124_Pos (28UL)                 /*!< DSP1N1GPIO124 (Bit 28)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO124_Msk (0x10000000UL)         /*!< DSP1N1GPIO124 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO123_Pos (27UL)                 /*!< DSP1N1GPIO123 (Bit 27)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO123_Msk (0x8000000UL)          /*!< DSP1N1GPIO123 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO122_Pos (26UL)                 /*!< DSP1N1GPIO122 (Bit 26)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO122_Msk (0x4000000UL)          /*!< DSP1N1GPIO122 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO121_Pos (25UL)                 /*!< DSP1N1GPIO121 (Bit 25)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO121_Msk (0x2000000UL)          /*!< DSP1N1GPIO121 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO120_Pos (24UL)                 /*!< DSP1N1GPIO120 (Bit 24)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO120_Msk (0x1000000UL)          /*!< DSP1N1GPIO120 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO119_Pos (23UL)                 /*!< DSP1N1GPIO119 (Bit 23)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO119_Msk (0x800000UL)           /*!< DSP1N1GPIO119 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO118_Pos (22UL)                 /*!< DSP1N1GPIO118 (Bit 22)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO118_Msk (0x400000UL)           /*!< DSP1N1GPIO118 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO117_Pos (21UL)                 /*!< DSP1N1GPIO117 (Bit 21)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO117_Msk (0x200000UL)           /*!< DSP1N1GPIO117 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO116_Pos (20UL)                 /*!< DSP1N1GPIO116 (Bit 20)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO116_Msk (0x100000UL)           /*!< DSP1N1GPIO116 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO115_Pos (19UL)                 /*!< DSP1N1GPIO115 (Bit 19)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO115_Msk (0x80000UL)            /*!< DSP1N1GPIO115 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO114_Pos (18UL)                 /*!< DSP1N1GPIO114 (Bit 18)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO114_Msk (0x40000UL)            /*!< DSP1N1GPIO114 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO113_Pos (17UL)                 /*!< DSP1N1GPIO113 (Bit 17)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO113_Msk (0x20000UL)            /*!< DSP1N1GPIO113 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO112_Pos (16UL)                 /*!< DSP1N1GPIO112 (Bit 16)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO112_Msk (0x10000UL)            /*!< DSP1N1GPIO112 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO111_Pos (15UL)                 /*!< DSP1N1GPIO111 (Bit 15)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO111_Msk (0x8000UL)             /*!< DSP1N1GPIO111 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO110_Pos (14UL)                 /*!< DSP1N1GPIO110 (Bit 14)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO110_Msk (0x4000UL)             /*!< DSP1N1GPIO110 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO109_Pos (13UL)                 /*!< DSP1N1GPIO109 (Bit 13)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO109_Msk (0x2000UL)             /*!< DSP1N1GPIO109 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO108_Pos (12UL)                 /*!< DSP1N1GPIO108 (Bit 12)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO108_Msk (0x1000UL)             /*!< DSP1N1GPIO108 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO107_Pos (11UL)                 /*!< DSP1N1GPIO107 (Bit 11)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO107_Msk (0x800UL)              /*!< DSP1N1GPIO107 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO106_Pos (10UL)                 /*!< DSP1N1GPIO106 (Bit 10)                                */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO106_Msk (0x400UL)              /*!< DSP1N1GPIO106 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO105_Pos (9UL)                  /*!< DSP1N1GPIO105 (Bit 9)                                 */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO105_Msk (0x200UL)              /*!< DSP1N1GPIO105 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO104_Pos (8UL)                  /*!< DSP1N1GPIO104 (Bit 8)                                 */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO104_Msk (0x100UL)              /*!< DSP1N1GPIO104 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO103_Pos (7UL)                  /*!< DSP1N1GPIO103 (Bit 7)                                 */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO103_Msk (0x80UL)               /*!< DSP1N1GPIO103 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO102_Pos (6UL)                  /*!< DSP1N1GPIO102 (Bit 6)                                 */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO102_Msk (0x40UL)               /*!< DSP1N1GPIO102 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO101_Pos (5UL)                  /*!< DSP1N1GPIO101 (Bit 5)                                 */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO101_Msk (0x20UL)               /*!< DSP1N1GPIO101 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO100_Pos (4UL)                  /*!< DSP1N1GPIO100 (Bit 4)                                 */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO100_Msk (0x10UL)               /*!< DSP1N1GPIO100 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO99_Pos (3UL)                   /*!< DSP1N1GPIO99 (Bit 3)                                  */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO99_Msk (0x8UL)                 /*!< DSP1N1GPIO99 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO98_Pos (2UL)                   /*!< DSP1N1GPIO98 (Bit 2)                                  */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO98_Msk (0x4UL)                 /*!< DSP1N1GPIO98 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO97_Pos (1UL)                   /*!< DSP1N1GPIO97 (Bit 1)                                  */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO97_Msk (0x2UL)                 /*!< DSP1N1GPIO97 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO96_Pos (0UL)                   /*!< DSP1N1GPIO96 (Bit 0)                                  */
#define GPIO_DSP1N1INT3CLR_DSP1N1GPIO96_Msk (0x1UL)                 /*!< DSP1N1GPIO96 (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1N1INT3SET  ===================================================== */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO127_Pos (31UL)                 /*!< DSP1N1GPIO127 (Bit 31)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO127_Msk (0x80000000UL)         /*!< DSP1N1GPIO127 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO126_Pos (30UL)                 /*!< DSP1N1GPIO126 (Bit 30)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO126_Msk (0x40000000UL)         /*!< DSP1N1GPIO126 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO125_Pos (29UL)                 /*!< DSP1N1GPIO125 (Bit 29)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO125_Msk (0x20000000UL)         /*!< DSP1N1GPIO125 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO124_Pos (28UL)                 /*!< DSP1N1GPIO124 (Bit 28)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO124_Msk (0x10000000UL)         /*!< DSP1N1GPIO124 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO123_Pos (27UL)                 /*!< DSP1N1GPIO123 (Bit 27)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO123_Msk (0x8000000UL)          /*!< DSP1N1GPIO123 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO122_Pos (26UL)                 /*!< DSP1N1GPIO122 (Bit 26)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO122_Msk (0x4000000UL)          /*!< DSP1N1GPIO122 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO121_Pos (25UL)                 /*!< DSP1N1GPIO121 (Bit 25)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO121_Msk (0x2000000UL)          /*!< DSP1N1GPIO121 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO120_Pos (24UL)                 /*!< DSP1N1GPIO120 (Bit 24)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO120_Msk (0x1000000UL)          /*!< DSP1N1GPIO120 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO119_Pos (23UL)                 /*!< DSP1N1GPIO119 (Bit 23)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO119_Msk (0x800000UL)           /*!< DSP1N1GPIO119 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO118_Pos (22UL)                 /*!< DSP1N1GPIO118 (Bit 22)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO118_Msk (0x400000UL)           /*!< DSP1N1GPIO118 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO117_Pos (21UL)                 /*!< DSP1N1GPIO117 (Bit 21)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO117_Msk (0x200000UL)           /*!< DSP1N1GPIO117 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO116_Pos (20UL)                 /*!< DSP1N1GPIO116 (Bit 20)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO116_Msk (0x100000UL)           /*!< DSP1N1GPIO116 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO115_Pos (19UL)                 /*!< DSP1N1GPIO115 (Bit 19)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO115_Msk (0x80000UL)            /*!< DSP1N1GPIO115 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO114_Pos (18UL)                 /*!< DSP1N1GPIO114 (Bit 18)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO114_Msk (0x40000UL)            /*!< DSP1N1GPIO114 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO113_Pos (17UL)                 /*!< DSP1N1GPIO113 (Bit 17)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO113_Msk (0x20000UL)            /*!< DSP1N1GPIO113 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO112_Pos (16UL)                 /*!< DSP1N1GPIO112 (Bit 16)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO112_Msk (0x10000UL)            /*!< DSP1N1GPIO112 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO111_Pos (15UL)                 /*!< DSP1N1GPIO111 (Bit 15)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO111_Msk (0x8000UL)             /*!< DSP1N1GPIO111 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO110_Pos (14UL)                 /*!< DSP1N1GPIO110 (Bit 14)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO110_Msk (0x4000UL)             /*!< DSP1N1GPIO110 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO109_Pos (13UL)                 /*!< DSP1N1GPIO109 (Bit 13)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO109_Msk (0x2000UL)             /*!< DSP1N1GPIO109 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO108_Pos (12UL)                 /*!< DSP1N1GPIO108 (Bit 12)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO108_Msk (0x1000UL)             /*!< DSP1N1GPIO108 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO107_Pos (11UL)                 /*!< DSP1N1GPIO107 (Bit 11)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO107_Msk (0x800UL)              /*!< DSP1N1GPIO107 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO106_Pos (10UL)                 /*!< DSP1N1GPIO106 (Bit 10)                                */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO106_Msk (0x400UL)              /*!< DSP1N1GPIO106 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO105_Pos (9UL)                  /*!< DSP1N1GPIO105 (Bit 9)                                 */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO105_Msk (0x200UL)              /*!< DSP1N1GPIO105 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO104_Pos (8UL)                  /*!< DSP1N1GPIO104 (Bit 8)                                 */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO104_Msk (0x100UL)              /*!< DSP1N1GPIO104 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO103_Pos (7UL)                  /*!< DSP1N1GPIO103 (Bit 7)                                 */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO103_Msk (0x80UL)               /*!< DSP1N1GPIO103 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO102_Pos (6UL)                  /*!< DSP1N1GPIO102 (Bit 6)                                 */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO102_Msk (0x40UL)               /*!< DSP1N1GPIO102 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO101_Pos (5UL)                  /*!< DSP1N1GPIO101 (Bit 5)                                 */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO101_Msk (0x20UL)               /*!< DSP1N1GPIO101 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO100_Pos (4UL)                  /*!< DSP1N1GPIO100 (Bit 4)                                 */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO100_Msk (0x10UL)               /*!< DSP1N1GPIO100 (Bitfield-Mask: 0x01)                   */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO99_Pos (3UL)                   /*!< DSP1N1GPIO99 (Bit 3)                                  */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO99_Msk (0x8UL)                 /*!< DSP1N1GPIO99 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO98_Pos (2UL)                   /*!< DSP1N1GPIO98 (Bit 2)                                  */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO98_Msk (0x4UL)                 /*!< DSP1N1GPIO98 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO97_Pos (1UL)                   /*!< DSP1N1GPIO97 (Bit 1)                                  */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO97_Msk (0x2UL)                 /*!< DSP1N1GPIO97 (Bitfield-Mask: 0x01)                    */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO96_Pos (0UL)                   /*!< DSP1N1GPIO96 (Bit 0)                                  */
#define GPIO_DSP1N1INT3SET_DSP1N1GPIO96_Msk (0x1UL)                 /*!< DSP1N1GPIO96 (Bitfield-Mask: 0x01)                    */


/* =========================================================================================================================== */
/* ================                                            GPU                                            ================ */
/* =========================================================================================================================== */

/* =======================================================  TEX0BASE  ======================================================== */
#define GPU_TEX0BASE_Base_Pos             (0UL)                     /*!< Base (Bit 0)                                          */
#define GPU_TEX0BASE_Base_Msk             (0xffffffffUL)            /*!< Base (Bitfield-Mask: 0xffffffff)                      */
/* ======================================================  TEX0STRIDE  ======================================================= */
#define GPU_TEX0STRIDE_IMGFMT_Pos         (24UL)                    /*!< IMGFMT (Bit 24)                                       */
#define GPU_TEX0STRIDE_IMGFMT_Msk         (0xff000000UL)            /*!< IMGFMT (Bitfield-Mask: 0xff)                          */
#define GPU_TEX0STRIDE_IMGMODE_Pos        (16UL)                    /*!< IMGMODE (Bit 16)                                      */
#define GPU_TEX0STRIDE_IMGMODE_Msk        (0xff0000UL)              /*!< IMGMODE (Bitfield-Mask: 0xff)                         */
#define GPU_TEX0STRIDE_IMGSTRD_Pos        (0UL)                     /*!< IMGSTRD (Bit 0)                                       */
#define GPU_TEX0STRIDE_IMGSTRD_Msk        (0xffffUL)                /*!< IMGSTRD (Bitfield-Mask: 0xffff)                       */
/* ========================================================  TEX0RES  ======================================================== */
#define GPU_TEX0RES_RESY_Pos              (16UL)                    /*!< RESY (Bit 16)                                         */
#define GPU_TEX0RES_RESY_Msk              (0xffff0000UL)            /*!< RESY (Bitfield-Mask: 0xffff)                          */
#define GPU_TEX0RES_RESX_Pos              (0UL)                     /*!< RESX (Bit 0)                                          */
#define GPU_TEX0RES_RESX_Msk              (0xffffUL)                /*!< RESX (Bitfield-Mask: 0xffff)                          */
/* =======================================================  TEX1BASE  ======================================================== */
#define GPU_TEX1BASE_Base_Pos             (0UL)                     /*!< Base (Bit 0)                                          */
#define GPU_TEX1BASE_Base_Msk             (0xffffffffUL)            /*!< Base (Bitfield-Mask: 0xffffffff)                      */
/* ======================================================  TEX1STRIDE  ======================================================= */
#define GPU_TEX1STRIDE_IMGFMT_Pos         (24UL)                    /*!< IMGFMT (Bit 24)                                       */
#define GPU_TEX1STRIDE_IMGFMT_Msk         (0xff000000UL)            /*!< IMGFMT (Bitfield-Mask: 0xff)                          */
#define GPU_TEX1STRIDE_IMGMODE_Pos        (16UL)                    /*!< IMGMODE (Bit 16)                                      */
#define GPU_TEX1STRIDE_IMGMODE_Msk        (0xff0000UL)              /*!< IMGMODE (Bitfield-Mask: 0xff)                         */
#define GPU_TEX1STRIDE_IMGSTRD_Pos        (0UL)                     /*!< IMGSTRD (Bit 0)                                       */
#define GPU_TEX1STRIDE_IMGSTRD_Msk        (0xffffUL)                /*!< IMGSTRD (Bitfield-Mask: 0xffff)                       */
/* ========================================================  TEX1RES  ======================================================== */
#define GPU_TEX1RES_RESY_Pos              (16UL)                    /*!< RESY (Bit 16)                                         */
#define GPU_TEX1RES_RESY_Msk              (0xffff0000UL)            /*!< RESY (Bitfield-Mask: 0xffff)                          */
#define GPU_TEX1RES_RESX_Pos              (0UL)                     /*!< RESX (Bit 0)                                          */
#define GPU_TEX1RES_RESX_Msk              (0xffffUL)                /*!< RESX (Bitfield-Mask: 0xffff)                          */
/* =======================================================  TEX1COLOR  ======================================================= */
#define GPU_TEX1COLOR_ALPHA_Pos           (24UL)                    /*!< ALPHA (Bit 24)                                        */
#define GPU_TEX1COLOR_ALPHA_Msk           (0xff000000UL)            /*!< ALPHA (Bitfield-Mask: 0xff)                           */
#define GPU_TEX1COLOR_BLUE_Pos            (16UL)                    /*!< BLUE (Bit 16)                                         */
#define GPU_TEX1COLOR_BLUE_Msk            (0xff0000UL)              /*!< BLUE (Bitfield-Mask: 0xff)                            */
#define GPU_TEX1COLOR_GREEN_Pos           (8UL)                     /*!< GREEN (Bit 8)                                         */
#define GPU_TEX1COLOR_GREEN_Msk           (0xff00UL)                /*!< GREEN (Bitfield-Mask: 0xff)                           */
#define GPU_TEX1COLOR_RED_Pos             (0UL)                     /*!< RED (Bit 0)                                           */
#define GPU_TEX1COLOR_RED_Msk             (0xffUL)                  /*!< RED (Bitfield-Mask: 0xff)                             */
/* =======================================================  TEX2BASE  ======================================================== */
#define GPU_TEX2BASE_Drawing_Pos          (0UL)                     /*!< Drawing (Bit 0)                                       */
#define GPU_TEX2BASE_Drawing_Msk          (0xffffffffUL)            /*!< Drawing (Bitfield-Mask: 0xffffffff)                   */
/* ======================================================  TEX2STRIDE  ======================================================= */
#define GPU_TEX2STRIDE_IMGFMT_Pos         (24UL)                    /*!< IMGFMT (Bit 24)                                       */
#define GPU_TEX2STRIDE_IMGFMT_Msk         (0xff000000UL)            /*!< IMGFMT (Bitfield-Mask: 0xff)                          */
#define GPU_TEX2STRIDE_IMGMODE_Pos        (16UL)                    /*!< IMGMODE (Bit 16)                                      */
#define GPU_TEX2STRIDE_IMGMODE_Msk        (0xff0000UL)              /*!< IMGMODE (Bitfield-Mask: 0xff)                         */
#define GPU_TEX2STRIDE_IMGSTRD_Pos        (0UL)                     /*!< IMGSTRD (Bit 0)                                       */
#define GPU_TEX2STRIDE_IMGSTRD_Msk        (0xffffUL)                /*!< IMGSTRD (Bitfield-Mask: 0xffff)                       */
/* ========================================================  TEX2RES  ======================================================== */
#define GPU_TEX2RES_RESY_Pos              (16UL)                    /*!< RESY (Bit 16)                                         */
#define GPU_TEX2RES_RESY_Msk              (0xffff0000UL)            /*!< RESY (Bitfield-Mask: 0xffff)                          */
#define GPU_TEX2RES_RESX_Pos              (0UL)                     /*!< RESX (Bit 0)                                          */
#define GPU_TEX2RES_RESX_Msk              (0xffffUL)                /*!< RESX (Bitfield-Mask: 0xffff)                          */
/* =======================================================  TEX3BASE  ======================================================== */
#define GPU_TEX3BASE_Image_Pos            (0UL)                     /*!< Image (Bit 0)                                         */
#define GPU_TEX3BASE_Image_Msk            (0xffffffffUL)            /*!< Image (Bitfield-Mask: 0xffffffff)                     */
/* ======================================================  TEX3STRIDE  ======================================================= */
#define GPU_TEX3STRIDE_IMGFMT_Pos         (24UL)                    /*!< IMGFMT (Bit 24)                                       */
#define GPU_TEX3STRIDE_IMGFMT_Msk         (0xff000000UL)            /*!< IMGFMT (Bitfield-Mask: 0xff)                          */
#define GPU_TEX3STRIDE_IMGMODE_Pos        (16UL)                    /*!< IMGMODE (Bit 16)                                      */
#define GPU_TEX3STRIDE_IMGMODE_Msk        (0xff0000UL)              /*!< IMGMODE (Bitfield-Mask: 0xff)                         */
#define GPU_TEX3STRIDE_IMGSTRD_Pos        (0UL)                     /*!< IMGSTRD (Bit 0)                                       */
#define GPU_TEX3STRIDE_IMGSTRD_Msk        (0xffffUL)                /*!< IMGSTRD (Bitfield-Mask: 0xffff)                       */
/* ========================================================  TEX3RES  ======================================================== */
#define GPU_TEX3RES_RESY_Pos              (16UL)                    /*!< RESY (Bit 16)                                         */
#define GPU_TEX3RES_RESY_Msk              (0xffff0000UL)            /*!< RESY (Bitfield-Mask: 0xffff)                          */
#define GPU_TEX3RES_RESX_Pos              (0UL)                     /*!< RESX (Bit 0)                                          */
#define GPU_TEX3RES_RESX_Msk              (0xffffUL)                /*!< RESX (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CGCMD  ========================================================= */
#define GPU_CGCMD_START_Pos               (1UL)                     /*!< START (Bit 1)                                         */
#define GPU_CGCMD_START_Msk               (0x2UL)                   /*!< START (Bitfield-Mask: 0x01)                           */
#define GPU_CGCMD_STOP_Pos                (0UL)                     /*!< STOP (Bit 0)                                          */
#define GPU_CGCMD_STOP_Msk                (0x1UL)                   /*!< STOP (Bitfield-Mask: 0x01)                            */
/* ========================================================  CGCTRL  ========================================================= */
#define GPU_CGCTRL_DISCLKMOD_Pos          (30UL)                    /*!< DISCLKMOD (Bit 30)                                    */
#define GPU_CGCTRL_DISCLKMOD_Msk          (0xc0000000UL)            /*!< DISCLKMOD (Bitfield-Mask: 0x03)                       */
#define GPU_CGCTRL_RSVD1_Pos              (24UL)                    /*!< RSVD1 (Bit 24)                                        */
#define GPU_CGCTRL_RSVD1_Msk              (0x3f000000UL)            /*!< RSVD1 (Bitfield-Mask: 0x3f)                           */
#define GPU_CGCTRL_DISCLKCORE_Pos         (23UL)                    /*!< DISCLKCORE (Bit 23)                                   */
#define GPU_CGCTRL_DISCLKCORE_Msk         (0x800000UL)              /*!< DISCLKCORE (Bitfield-Mask: 0x01)                      */
#define GPU_CGCTRL_RSVD0_Pos              (4UL)                     /*!< RSVD0 (Bit 4)                                         */
#define GPU_CGCTRL_RSVD0_Msk              (0x7ffff0UL)              /*!< RSVD0 (Bitfield-Mask: 0x7ffff)                        */
#define GPU_CGCTRL_DISCLKFRAME_Pos        (2UL)                     /*!< DISCLKFRAME (Bit 2)                                   */
#define GPU_CGCTRL_DISCLKFRAME_Msk        (0xcUL)                   /*!< DISCLKFRAME (Bitfield-Mask: 0x03)                     */
#define GPU_CGCTRL_DISCLKCFG_Pos          (1UL)                     /*!< DISCLKCFG (Bit 1)                                     */
#define GPU_CGCTRL_DISCLKCFG_Msk          (0x2UL)                   /*!< DISCLKCFG (Bitfield-Mask: 0x01)                       */
#define GPU_CGCTRL_DISCLKPROC_Pos         (0UL)                     /*!< DISCLKPROC (Bit 0)                                    */
#define GPU_CGCTRL_DISCLKPROC_Msk         (0x1UL)                   /*!< DISCLKPROC (Bitfield-Mask: 0x01)                      */
/* =====================================================  DIRTYTRIGMIN  ====================================================== */
#define GPU_DIRTYTRIGMIN_DRTYREG_Pos      (0UL)                     /*!< DRTYREG (Bit 0)                                       */
#define GPU_DIRTYTRIGMIN_DRTYREG_Msk      (0xffffffffUL)            /*!< DRTYREG (Bitfield-Mask: 0xffffffff)                   */
/* =====================================================  DIRTYTRIGMAX  ====================================================== */
#define GPU_DIRTYTRIGMAX_DRTYREG_Pos      (0UL)                     /*!< DRTYREG (Bit 0)                                       */
#define GPU_DIRTYTRIGMAX_DRTYREG_Msk      (0xffffffffUL)            /*!< DRTYREG (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  STATUS  ========================================================= */
#define GPU_STATUS_SYSBSY_Pos             (31UL)                    /*!< SYSBSY (Bit 31)                                       */
#define GPU_STATUS_SYSBSY_Msk             (0x80000000UL)            /*!< SYSBSY (Bitfield-Mask: 0x01)                          */
#define GPU_STATUS_MEMBSY_Pos             (30UL)                    /*!< MEMBSY (Bit 30)                                       */
#define GPU_STATUS_MEMBSY_Msk             (0x40000000UL)            /*!< MEMBSY (Bitfield-Mask: 0x01)                          */
#define GPU_STATUS_CLBSY_Pos              (29UL)                    /*!< CLBSY (Bit 29)                                        */
#define GPU_STATUS_CLBSY_Msk              (0x20000000UL)            /*!< CLBSY (Bitfield-Mask: 0x01)                           */
#define GPU_STATUS_CLPBSY_Pos             (28UL)                    /*!< CLPBSY (Bit 28)                                       */
#define GPU_STATUS_CLPBSY_Msk             (0x10000000UL)            /*!< CLPBSY (Bitfield-Mask: 0x01)                          */
#define GPU_STATUS_RASTBSY_Pos            (24UL)                    /*!< RASTBSY (Bit 24)                                      */
#define GPU_STATUS_RASTBSY_Msk            (0xf000000UL)             /*!< RASTBSY (Bitfield-Mask: 0x0f)                         */
#define GPU_STATUS_DEPTHFIFOBSY_Pos       (16UL)                    /*!< DEPTHFIFOBSY (Bit 16)                                 */
#define GPU_STATUS_DEPTHFIFOBSY_Msk       (0xf0000UL)               /*!< DEPTHFIFOBSY (Bitfield-Mask: 0x0f)                    */
#define GPU_STATUS_RENDERBSY_Pos          (12UL)                    /*!< RENDERBSY (Bit 12)                                    */
#define GPU_STATUS_RENDERBSY_Msk          (0xf000UL)                /*!< RENDERBSY (Bitfield-Mask: 0x0f)                       */
#define GPU_STATUS_TEXTMAPBSY_Pos         (8UL)                     /*!< TEXTMAPBSY (Bit 8)                                    */
#define GPU_STATUS_TEXTMAPBSY_Msk         (0xf00UL)                 /*!< TEXTMAPBSY (Bitfield-Mask: 0x0f)                      */
#define GPU_STATUS_PIPEBSY_Pos            (4UL)                     /*!< PIPEBSY (Bit 4)                                       */
#define GPU_STATUS_PIPEBSY_Msk            (0xf0UL)                  /*!< PIPEBSY (Bitfield-Mask: 0x0f)                         */
#define GPU_STATUS_COREBSY_Pos            (0UL)                     /*!< COREBSY (Bit 0)                                       */
#define GPU_STATUS_COREBSY_Msk            (0xfUL)                   /*!< COREBSY (Bitfield-Mask: 0x0f)                         */
/* ========================================================  BUSCTRL  ======================================================== */
#define GPU_BUSCTRL_BUSCTRL_Pos           (0UL)                     /*!< BUSCTRL (Bit 0)                                       */
#define GPU_BUSCTRL_BUSCTRL_Msk           (0xffffffffUL)            /*!< BUSCTRL (Bitfield-Mask: 0xffffffff)                   */
/* ======================================================  IMEMLDIADDR  ====================================================== */
#define GPU_IMEMLDIADDR_IMEM_Pos          (0UL)                     /*!< IMEM (Bit 0)                                          */
#define GPU_IMEMLDIADDR_IMEM_Msk          (0xffffffffUL)            /*!< IMEM (Bitfield-Mask: 0xffffffff)                      */
/* =====================================================  IMEMLDIDATAHL  ===================================================== */
#define GPU_IMEMLDIDATAHL_IMEM_Pos        (0UL)                     /*!< IMEM (Bit 0)                                          */
#define GPU_IMEMLDIDATAHL_IMEM_Msk        (0xffffffffUL)            /*!< IMEM (Bitfield-Mask: 0xffffffff)                      */
/* =====================================================  IMEMLDIDATAHH  ===================================================== */
#define GPU_IMEMLDIDATAHH_IMEM_Pos        (0UL)                     /*!< IMEM (Bit 0)                                          */
#define GPU_IMEMLDIDATAHH_IMEM_Msk        (0xffffffffUL)            /*!< IMEM (Bitfield-Mask: 0xffffffff)                      */
/* =====================================================  CMDLISTSTATUS  ===================================================== */
#define GPU_CMDLISTSTATUS_LIST_Pos        (0UL)                     /*!< LIST (Bit 0)                                          */
#define GPU_CMDLISTSTATUS_LIST_Msk        (0x1UL)                   /*!< LIST (Bitfield-Mask: 0x01)                            */
/* ====================================================  CMDLISTRINGSTOP  ==================================================== */
#define GPU_CMDLISTRINGSTOP_UPDATEPRT_Pos (0UL)                     /*!< UPDATEPRT (Bit 0)                                     */
#define GPU_CMDLISTRINGSTOP_UPDATEPRT_Msk (0xffffffffUL)            /*!< UPDATEPRT (Bitfield-Mask: 0xffffffff)                 */
/* ======================================================  CMDLISTADDR  ====================================================== */
#define GPU_CMDLISTADDR_BASEPTR_Pos       (0UL)                     /*!< BASEPTR (Bit 0)                                       */
#define GPU_CMDLISTADDR_BASEPTR_Msk       (0xffffffffUL)            /*!< BASEPTR (Bitfield-Mask: 0xffffffff)                   */
/* ======================================================  CMDLISTSIZE  ====================================================== */
#define GPU_CMDLISTSIZE_LISTWORDS_Pos     (0UL)                     /*!< LISTWORDS (Bit 0)                                     */
#define GPU_CMDLISTSIZE_LISTWORDS_Msk     (0xffffffffUL)            /*!< LISTWORDS (Bitfield-Mask: 0xffffffff)                 */
/* =====================================================  INTERRUPTCTRL  ===================================================== */
#define GPU_INTERRUPTCTRL_CHANGEFREQ_Pos  (30UL)                    /*!< CHANGEFREQ (Bit 30)                                   */
#define GPU_INTERRUPTCTRL_CHANGEFREQ_Msk  (0xc0000000UL)            /*!< CHANGEFREQ (Bitfield-Mask: 0x03)                      */
#define GPU_INTERRUPTCTRL_RSVD_Pos        (4UL)                     /*!< RSVD (Bit 4)                                          */
#define GPU_INTERRUPTCTRL_RSVD_Msk        (0x3ffffff0UL)            /*!< RSVD (Bitfield-Mask: 0x3ffffff)                       */
#define GPU_INTERRUPTCTRL_AUTOCLR_Pos     (3UL)                     /*!< AUTOCLR (Bit 3)                                       */
#define GPU_INTERRUPTCTRL_AUTOCLR_Msk     (0x8UL)                   /*!< AUTOCLR (Bitfield-Mask: 0x01)                         */
#define GPU_INTERRUPTCTRL_INTDRAWEND_Pos  (2UL)                     /*!< INTDRAWEND (Bit 2)                                    */
#define GPU_INTERRUPTCTRL_INTDRAWEND_Msk  (0x4UL)                   /*!< INTDRAWEND (Bitfield-Mask: 0x01)                      */
#define GPU_INTERRUPTCTRL_INTCMDEND_Pos   (1UL)                     /*!< INTCMDEND (Bit 1)                                     */
#define GPU_INTERRUPTCTRL_INTCMDEND_Msk   (0x2UL)                   /*!< INTCMDEND (Bitfield-Mask: 0x01)                       */
#define GPU_INTERRUPTCTRL_IRQACTIVE_Pos   (0UL)                     /*!< IRQACTIVE (Bit 0)                                     */
#define GPU_INTERRUPTCTRL_IRQACTIVE_Msk   (0x1UL)                   /*!< IRQACTIVE (Bitfield-Mask: 0x01)                       */
/* =======================================================  SYSCLEAR  ======================================================== */
#define GPU_SYSCLEAR_RESETGPU_Pos         (0UL)                     /*!< RESETGPU (Bit 0)                                      */
#define GPU_SYSCLEAR_RESETGPU_Msk         (0xffffffffUL)            /*!< RESETGPU (Bitfield-Mask: 0xffffffff)                  */
/* ========================================================  DRAWCMD  ======================================================== */
#define GPU_DRAWCMD_RSVD_Pos              (3UL)                     /*!< RSVD (Bit 3)                                          */
#define GPU_DRAWCMD_RSVD_Msk              (0xfffffff8UL)            /*!< RSVD (Bitfield-Mask: 0x1fffffff)                      */
#define GPU_DRAWCMD_START_Pos             (0UL)                     /*!< START (Bit 0)                                         */
#define GPU_DRAWCMD_START_Msk             (0x7UL)                   /*!< START (Bitfield-Mask: 0x07)                           */
/* ========================================================  DRAWPT0  ======================================================== */
#define GPU_DRAWPT0_COORDY_Pos            (16UL)                    /*!< COORDY (Bit 16)                                       */
#define GPU_DRAWPT0_COORDY_Msk            (0xffff0000UL)            /*!< COORDY (Bitfield-Mask: 0xffff)                        */
#define GPU_DRAWPT0_COORDX_Pos            (0UL)                     /*!< COORDX (Bit 0)                                        */
#define GPU_DRAWPT0_COORDX_Msk            (0xffffUL)                /*!< COORDX (Bitfield-Mask: 0xffff)                        */
/* ========================================================  DRAWPT1  ======================================================== */
#define GPU_DRAWPT1_COORDY_Pos            (16UL)                    /*!< COORDY (Bit 16)                                       */
#define GPU_DRAWPT1_COORDY_Msk            (0xffff0000UL)            /*!< COORDY (Bitfield-Mask: 0xffff)                        */
#define GPU_DRAWPT1_COORDX_Pos            (0UL)                     /*!< COORDX (Bit 0)                                        */
#define GPU_DRAWPT1_COORDX_Msk            (0xffffUL)                /*!< COORDX (Bitfield-Mask: 0xffff)                        */
/* ========================================================  CLIPMIN  ======================================================== */
#define GPU_CLIPMIN_COORDY_Pos            (16UL)                    /*!< COORDY (Bit 16)                                       */
#define GPU_CLIPMIN_COORDY_Msk            (0xffff0000UL)            /*!< COORDY (Bitfield-Mask: 0xffff)                        */
#define GPU_CLIPMIN_COORDX_Pos            (0UL)                     /*!< COORDX (Bit 0)                                        */
#define GPU_CLIPMIN_COORDX_Msk            (0xffffUL)                /*!< COORDX (Bitfield-Mask: 0xffff)                        */
/* ========================================================  CLIPMAX  ======================================================== */
#define GPU_CLIPMAX_COORDY_Pos            (16UL)                    /*!< COORDY (Bit 16)                                       */
#define GPU_CLIPMAX_COORDY_Msk            (0xffff0000UL)            /*!< COORDY (Bitfield-Mask: 0xffff)                        */
#define GPU_CLIPMAX_COORDX_Pos            (0UL)                     /*!< COORDX (Bit 0)                                        */
#define GPU_CLIPMAX_COORDX_Msk            (0xffffUL)                /*!< COORDX (Bitfield-Mask: 0xffff)                        */
/* =======================================================  RASTCTRL  ======================================================== */
#define GPU_RASTCTRL_PERSP_Pos            (30UL)                    /*!< PERSP (Bit 30)                                        */
#define GPU_RASTCTRL_PERSP_Msk            (0xc0000000UL)            /*!< PERSP (Bitfield-Mask: 0x03)                           */
#define GPU_RASTCTRL_ADD_Pos              (29UL)                    /*!< ADD (Bit 29)                                          */
#define GPU_RASTCTRL_ADD_Msk              (0x20000000UL)            /*!< ADD (Bitfield-Mask: 0x01)                             */
#define GPU_RASTCTRL_BYPASS_Pos           (28UL)                    /*!< BYPASS (Bit 28)                                       */
#define GPU_RASTCTRL_BYPASS_Msk           (0x10000000UL)            /*!< BYPASS (Bitfield-Mask: 0x01)                          */
#define GPU_RASTCTRL_RSVD_Pos             (0UL)                     /*!< RSVD (Bit 0)                                          */
#define GPU_RASTCTRL_RSVD_Msk             (0xfffffffUL)             /*!< RSVD (Bitfield-Mask: 0xfffffff)                       */
/* ======================================================  DRAWCODEPTR  ====================================================== */
#define GPU_DRAWCODEPTR_BKGND_Pos         (16UL)                    /*!< BKGND (Bit 16)                                        */
#define GPU_DRAWCODEPTR_BKGND_Msk         (0xffff0000UL)            /*!< BKGND (Bitfield-Mask: 0xffff)                         */
#define GPU_DRAWCODEPTR_FRGND_Pos         (0UL)                     /*!< FRGND (Bit 0)                                         */
#define GPU_DRAWCODEPTR_FRGND_Msk         (0xffffUL)                /*!< FRGND (Bitfield-Mask: 0xffff)                         */
/* =======================================================  DRAWPT0X  ======================================================== */
#define GPU_DRAWPT0X_DRAW0X_Pos           (0UL)                     /*!< DRAW0X (Bit 0)                                        */
#define GPU_DRAWPT0X_DRAW0X_Msk           (0xffffffffUL)            /*!< DRAW0X (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  DRAWPT0Y  ======================================================== */
#define GPU_DRAWPT0Y_DRAW0Y_Pos           (0UL)                     /*!< DRAW0Y (Bit 0)                                        */
#define GPU_DRAWPT0Y_DRAW0Y_Msk           (0xffffffffUL)            /*!< DRAW0Y (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  DRAWPT0Z  ======================================================== */
#define GPU_DRAWPT0Z_DRAW0Z_Pos           (0UL)                     /*!< DRAW0Z (Bit 0)                                        */
#define GPU_DRAWPT0Z_DRAW0Z_Msk           (0xffffffffUL)            /*!< DRAW0Z (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  DRAWCOLOR  ======================================================= */
#define GPU_DRAWCOLOR_RASTPRIM_Pos        (0UL)                     /*!< RASTPRIM (Bit 0)                                      */
#define GPU_DRAWCOLOR_RASTPRIM_Msk        (0xffffffffUL)            /*!< RASTPRIM (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  DRAWPT1X  ======================================================== */
#define GPU_DRAWPT1X_DRAW1X_Pos           (0UL)                     /*!< DRAW1X (Bit 0)                                        */
#define GPU_DRAWPT1X_DRAW1X_Msk           (0xffffffffUL)            /*!< DRAW1X (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  DRAWPT1Y  ======================================================== */
#define GPU_DRAWPT1Y_DRAW1Y_Pos           (0UL)                     /*!< DRAW1Y (Bit 0)                                        */
#define GPU_DRAWPT1Y_DRAW1Y_Msk           (0xffffffffUL)            /*!< DRAW1Y (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  DRAWPT1Z  ======================================================== */
#define GPU_DRAWPT1Z_DRAW1Z_Pos           (0UL)                     /*!< DRAW1Z (Bit 0)                                        */
#define GPU_DRAWPT1Z_DRAW1Z_Msk           (0xffffffffUL)            /*!< DRAW1Z (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  DRAWPT2X  ======================================================== */
#define GPU_DRAWPT2X_DRAW2X_Pos           (0UL)                     /*!< DRAW2X (Bit 0)                                        */
#define GPU_DRAWPT2X_DRAW2X_Msk           (0xffffffffUL)            /*!< DRAW2X (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  DRAWPT2Y  ======================================================== */
#define GPU_DRAWPT2Y_DRAW2Y_Pos           (0UL)                     /*!< DRAW2Y (Bit 0)                                        */
#define GPU_DRAWPT2Y_DRAW2Y_Msk           (0xffffffffUL)            /*!< DRAW2Y (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  DRAWPT2Z  ======================================================== */
#define GPU_DRAWPT2Z_RSVD_Pos             (0UL)                     /*!< RSVD (Bit 0)                                          */
#define GPU_DRAWPT2Z_RSVD_Msk             (0xffffffffUL)            /*!< RSVD (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  DRAWPT3X  ======================================================== */
#define GPU_DRAWPT3X_DRAW3X_Pos           (0UL)                     /*!< DRAW3X (Bit 0)                                        */
#define GPU_DRAWPT3X_DRAW3X_Msk           (0xffffffffUL)            /*!< DRAW3X (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  DRAWPT3Y  ======================================================== */
#define GPU_DRAWPT3Y_DRAW3Y_Pos           (0UL)                     /*!< DRAW3Y (Bit 0)                                        */
#define GPU_DRAWPT3Y_DRAW3Y_Msk           (0xffffffffUL)            /*!< DRAW3Y (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  DRAWPT3Z  ======================================================== */
#define GPU_DRAWPT3Z_DRAW3Z_Pos           (0UL)                     /*!< DRAW3Z (Bit 0)                                        */
#define GPU_DRAWPT3Z_DRAW3Z_Msk           (0xffffffffUL)            /*!< DRAW3Z (Bitfield-Mask: 0xffffffff)                    */
/* =========================================================  MM00  ========================================================== */
#define GPU_MM00_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
#define GPU_MM00_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  MM01  ========================================================== */
#define GPU_MM01_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
#define GPU_MM01_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  MM02  ========================================================== */
#define GPU_MM02_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
#define GPU_MM02_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  MM10  ========================================================== */
#define GPU_MM10_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
#define GPU_MM10_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  MM11  ========================================================== */
#define GPU_MM11_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
#define GPU_MM11_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  MM12  ========================================================== */
#define GPU_MM12_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
#define GPU_MM12_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  MM20  ========================================================== */
#define GPU_MM20_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
#define GPU_MM20_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  MM21  ========================================================== */
#define GPU_MM21_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
#define GPU_MM21_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  MM22  ========================================================== */
#define GPU_MM22_MTX_Pos                  (0UL)                     /*!< MTX (Bit 0)                                           */
#define GPU_MM22_MTX_Msk                  (0xffffffffUL)            /*!< MTX (Bitfield-Mask: 0xffffffff)                       */
/* ======================================================  DEPTHSTARTL  ====================================================== */
#define GPU_DEPTHSTARTL_DEPTH32LO_Pos     (0UL)                     /*!< DEPTH32LO (Bit 0)                                     */
#define GPU_DEPTHSTARTL_DEPTH32LO_Msk     (0xffffffffUL)            /*!< DEPTH32LO (Bitfield-Mask: 0xffffffff)                 */
/* ======================================================  DEPTHSTARTH  ====================================================== */
#define GPU_DEPTHSTARTH_DEPTH32HI_Pos     (0UL)                     /*!< DEPTH32HI (Bit 0)                                     */
#define GPU_DEPTHSTARTH_DEPTH32HI_Msk     (0xffffffffUL)            /*!< DEPTH32HI (Bitfield-Mask: 0xffffffff)                 */
/* =======================================================  DEPTHDXL  ======================================================== */
#define GPU_DEPTHDXL_XAXISLO_Pos          (0UL)                     /*!< XAXISLO (Bit 0)                                       */
#define GPU_DEPTHDXL_XAXISLO_Msk          (0xffffffffUL)            /*!< XAXISLO (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  DEPTHDXH  ======================================================== */
#define GPU_DEPTHDXH_XAXISHI_Pos          (0UL)                     /*!< XAXISHI (Bit 0)                                       */
#define GPU_DEPTHDXH_XAXISHI_Msk          (0xffffffffUL)            /*!< XAXISHI (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  DEPTHDYL  ======================================================== */
#define GPU_DEPTHDYL_YAXISLO_Pos          (0UL)                     /*!< YAXISLO (Bit 0)                                       */
#define GPU_DEPTHDYL_YAXISLO_Msk          (0xffffffffUL)            /*!< YAXISLO (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  DEPTHDYH  ======================================================== */
#define GPU_DEPTHDYH_YAXISHI_Pos          (0UL)                     /*!< YAXISHI (Bit 0)                                       */
#define GPU_DEPTHDYH_YAXISHI_Msk          (0xffffffffUL)            /*!< YAXISHI (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  REDX  ========================================================== */
#define GPU_REDX_REDX_Pos                 (0UL)                     /*!< REDX (Bit 0)                                          */
#define GPU_REDX_REDX_Msk                 (0xffffffffUL)            /*!< REDX (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  REDY  ========================================================== */
#define GPU_REDY_REDY_Pos                 (0UL)                     /*!< REDY (Bit 0)                                          */
#define GPU_REDY_REDY_Msk                 (0xffffffffUL)            /*!< REDY (Bitfield-Mask: 0xffffffff)                      */
/* ========================================================  GREENX  ========================================================= */
#define GPU_GREENX_GREENX_Pos             (0UL)                     /*!< GREENX (Bit 0)                                        */
#define GPU_GREENX_GREENX_Msk             (0xffffffffUL)            /*!< GREENX (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  GREENY  ========================================================= */
#define GPU_GREENY_GREENY_Pos             (0UL)                     /*!< GREENY (Bit 0)                                        */
#define GPU_GREENY_GREENY_Msk             (0xffffffffUL)            /*!< GREENY (Bitfield-Mask: 0xffffffff)                    */
/* =========================================================  BLUEX  ========================================================= */
#define GPU_BLUEX_BLUEX_Pos               (0UL)                     /*!< BLUEX (Bit 0)                                         */
#define GPU_BLUEX_BLUEX_Msk               (0xffffffffUL)            /*!< BLUEX (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  BLUEY  ========================================================= */
#define GPU_BLUEY_BLUEY_Pos               (0UL)                     /*!< BLUEY (Bit 0)                                         */
#define GPU_BLUEY_BLUEY_Msk               (0xffffffffUL)            /*!< BLUEY (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  ALFX  ========================================================== */
#define GPU_ALFX_ALFX_Pos                 (0UL)                     /*!< ALFX (Bit 0)                                          */
#define GPU_ALFX_ALFX_Msk                 (0xffffffffUL)            /*!< ALFX (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  ALFY  ========================================================== */
#define GPU_ALFY_ALFY_Pos                 (0UL)                     /*!< ALFY (Bit 0)                                          */
#define GPU_ALFY_ALFY_Msk                 (0xffffffffUL)            /*!< ALFY (Bitfield-Mask: 0xffffffff)                      */
/* ========================================================  REDINIT  ======================================================== */
#define GPU_REDINIT_REDXY_Pos             (0UL)                     /*!< REDXY (Bit 0)                                         */
#define GPU_REDINIT_REDXY_Msk             (0xffffffffUL)            /*!< REDXY (Bitfield-Mask: 0xffffffff)                     */
/* ========================================================  GREINIT  ======================================================== */
#define GPU_GREINIT_GREENXY_Pos           (0UL)                     /*!< GREENXY (Bit 0)                                       */
#define GPU_GREINIT_GREENXY_Msk           (0xffffffffUL)            /*!< GREENXY (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  BLUINIT  ======================================================== */
#define GPU_BLUINIT_BLUEXY_Pos            (0UL)                     /*!< BLUEXY (Bit 0)                                        */
#define GPU_BLUINIT_BLUEXY_Msk            (0xffffffffUL)            /*!< BLUEXY (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  ALFINIT  ======================================================== */
#define GPU_ALFINIT_ALFXY_Pos             (0UL)                     /*!< ALFXY (Bit 0)                                         */
#define GPU_ALFINIT_ALFXY_Msk             (0xffffffffUL)            /*!< ALFXY (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  IDREG  ========================================================= */
#define GPU_IDREG_GPUID_Pos               (0UL)                     /*!< GPUID (Bit 0)                                         */
#define GPU_IDREG_GPUID_Msk               (0xffffffffUL)            /*!< GPUID (Bitfield-Mask: 0xffffffff)                     */
/* =======================================================  LOADCTRL  ======================================================== */
#define GPU_LOADCTRL_LOADCTRL_Pos         (0UL)                     /*!< LOADCTRL (Bit 0)                                      */
#define GPU_LOADCTRL_LOADCTRL_Msk         (0xffffffffUL)            /*!< LOADCTRL (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  C0REG  ========================================================= */
#define GPU_C0REG_C0SHADER_Pos            (0UL)                     /*!< C0SHADER (Bit 0)                                      */
#define GPU_C0REG_C0SHADER_Msk            (0xffffffffUL)            /*!< C0SHADER (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  C1REG  ========================================================= */
#define GPU_C1REG_C1SHADER_Pos            (0UL)                     /*!< C1SHADER (Bit 0)                                      */
#define GPU_C1REG_C1SHADER_Msk            (0xffffffffUL)            /*!< C1SHADER (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  C2REG  ========================================================= */
#define GPU_C2REG_C2SHADER_Pos            (0UL)                     /*!< C2SHADER (Bit 0)                                      */
#define GPU_C2REG_C2SHADER_Msk            (0xffffffffUL)            /*!< C2SHADER (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  C3REG  ========================================================= */
#define GPU_C3REG_C3SHADER_Pos            (0UL)                     /*!< C3SHADER (Bit 0)                                      */
#define GPU_C3REG_C3SHADER_Msk            (0xffffffffUL)            /*!< C3SHADER (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  IRQID  ========================================================= */
#define GPU_IRQID_IRQID_Pos               (0UL)                     /*!< IRQID (Bit 0)                                         */
#define GPU_IRQID_IRQID_Msk               (0xffffffffUL)            /*!< IRQID (Bitfield-Mask: 0xffffffff)                     */


/* =========================================================================================================================== */
/* ================                                           I2S0                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  RXDATA  ========================================================= */
#define I2S0_RXDATA_RXSAMPLE_Pos          (0UL)                     /*!< RXSAMPLE (Bit 0)                                      */
#define I2S0_RXDATA_RXSAMPLE_Msk          (0xffffffffUL)            /*!< RXSAMPLE (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  RXCHANID  ======================================================== */
#define I2S0_RXCHANID_RXCHANID_Pos        (0UL)                     /*!< RXCHANID (Bit 0)                                      */
#define I2S0_RXCHANID_RXCHANID_Msk        (0xffUL)                  /*!< RXCHANID (Bitfield-Mask: 0xff)                        */
/* =====================================================  RXFIFOSTATUS  ====================================================== */
#define I2S0_RXFIFOSTATUS_RXEMPTY_Pos     (28UL)                    /*!< RXEMPTY (Bit 28)                                      */
#define I2S0_RXFIFOSTATUS_RXEMPTY_Msk     (0x10000000UL)            /*!< RXEMPTY (Bitfield-Mask: 0x01)                         */
#define I2S0_RXFIFOSTATUS_RXSAMPLECNT_Pos (0UL)                     /*!< RXSAMPLECNT (Bit 0)                                   */
#define I2S0_RXFIFOSTATUS_RXSAMPLECNT_Msk (0xfffffffUL)             /*!< RXSAMPLECNT (Bitfield-Mask: 0xfffffff)                */
/* ======================================================  RXFIFOSIZE  ======================================================= */
#define I2S0_RXFIFOSIZE_SIZE_Pos          (0UL)                     /*!< SIZE (Bit 0)                                          */
#define I2S0_RXFIFOSIZE_SIZE_Msk          (0xffffffffUL)            /*!< SIZE (Bitfield-Mask: 0xffffffff)                      */
/* =====================================================  RXUPPERLIMIT  ====================================================== */
#define I2S0_RXUPPERLIMIT_SIZE_Pos        (0UL)                     /*!< SIZE (Bit 0)                                          */
#define I2S0_RXUPPERLIMIT_SIZE_Msk        (0xffffffffUL)            /*!< SIZE (Bitfield-Mask: 0xffffffff)                      */
/* ========================================================  TXDATA  ========================================================= */
#define I2S0_TXDATA_TXSAMPLE_Pos          (0UL)                     /*!< TXSAMPLE (Bit 0)                                      */
#define I2S0_TXDATA_TXSAMPLE_Msk          (0xffffffffUL)            /*!< TXSAMPLE (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  TXCHANID  ======================================================== */
#define I2S0_TXCHANID_TXCHANID_Pos        (0UL)                     /*!< TXCHANID (Bit 0)                                      */
#define I2S0_TXCHANID_TXCHANID_Msk        (0xffUL)                  /*!< TXCHANID (Bitfield-Mask: 0xff)                        */
/* =====================================================  TXFIFOSTATUS  ====================================================== */
#define I2S0_TXFIFOSTATUS_TXFIFOFULL_Pos  (29UL)                    /*!< TXFIFOFULL (Bit 29)                                   */
#define I2S0_TXFIFOSTATUS_TXFIFOFULL_Msk  (0x20000000UL)            /*!< TXFIFOFULL (Bitfield-Mask: 0x01)                      */
#define I2S0_TXFIFOSTATUS_TXFIFOCNT_Pos   (0UL)                     /*!< TXFIFOCNT (Bit 0)                                     */
#define I2S0_TXFIFOSTATUS_TXFIFOCNT_Msk   (0xfffffffUL)             /*!< TXFIFOCNT (Bitfield-Mask: 0xfffffff)                  */
/* ======================================================  TXFIFOSIZE  ======================================================= */
#define I2S0_TXFIFOSIZE_SIZE_Pos          (0UL)                     /*!< SIZE (Bit 0)                                          */
#define I2S0_TXFIFOSIZE_SIZE_Msk          (0xffffffffUL)            /*!< SIZE (Bitfield-Mask: 0xffffffff)                      */
/* =====================================================  TXLOWERLIMIT  ====================================================== */
#define I2S0_TXLOWERLIMIT_SIZE_Pos        (0UL)                     /*!< SIZE (Bit 0)                                          */
#define I2S0_TXLOWERLIMIT_SIZE_Msk        (0xffffffffUL)            /*!< SIZE (Bitfield-Mask: 0xffffffff)                      */
/* ======================================================  I2SDATACFG  ======================================================= */
#define I2S0_I2SDATACFG_PH_Pos            (31UL)                    /*!< PH (Bit 31)                                           */
#define I2S0_I2SDATACFG_PH_Msk            (0x80000000UL)            /*!< PH (Bitfield-Mask: 0x01)                              */
#define I2S0_I2SDATACFG_FRLEN2_Pos        (24UL)                    /*!< FRLEN2 (Bit 24)                                       */
#define I2S0_I2SDATACFG_FRLEN2_Msk        (0x7f000000UL)            /*!< FRLEN2 (Bitfield-Mask: 0x7f)                          */
#define I2S0_I2SDATACFG_WDLEN2_Pos        (21UL)                    /*!< WDLEN2 (Bit 21)                                       */
#define I2S0_I2SDATACFG_WDLEN2_Msk        (0xe00000UL)              /*!< WDLEN2 (Bitfield-Mask: 0x07)                          */
#define I2S0_I2SDATACFG_DATADLY_Pos       (19UL)                    /*!< DATADLY (Bit 19)                                      */
#define I2S0_I2SDATACFG_DATADLY_Msk       (0x180000UL)              /*!< DATADLY (Bitfield-Mask: 0x03)                         */
#define I2S0_I2SDATACFG_SSZ2_Pos          (16UL)                    /*!< SSZ2 (Bit 16)                                         */
#define I2S0_I2SDATACFG_SSZ2_Msk          (0x70000UL)               /*!< SSZ2 (Bitfield-Mask: 0x07)                            */
#define I2S0_I2SDATACFG_FRLEN1_Pos        (8UL)                     /*!< FRLEN1 (Bit 8)                                        */
#define I2S0_I2SDATACFG_FRLEN1_Msk        (0x7f00UL)                /*!< FRLEN1 (Bitfield-Mask: 0x7f)                          */
#define I2S0_I2SDATACFG_WDLEN1_Pos        (5UL)                     /*!< WDLEN1 (Bit 5)                                        */
#define I2S0_I2SDATACFG_WDLEN1_Msk        (0xe0UL)                  /*!< WDLEN1 (Bitfield-Mask: 0x07)                          */
#define I2S0_I2SDATACFG_JUST_Pos          (3UL)                     /*!< JUST (Bit 3)                                          */
#define I2S0_I2SDATACFG_JUST_Msk          (0x8UL)                   /*!< JUST (Bitfield-Mask: 0x01)                            */
#define I2S0_I2SDATACFG_SSZ1_Pos          (0UL)                     /*!< SSZ1 (Bit 0)                                          */
#define I2S0_I2SDATACFG_SSZ1_Msk          (0x7UL)                   /*!< SSZ1 (Bitfield-Mask: 0x07)                            */
/* =======================================================  I2SIOCFG  ======================================================== */
#define I2S0_I2SIOCFG_FWID_Pos            (20UL)                    /*!< FWID (Bit 20)                                         */
#define I2S0_I2SIOCFG_FWID_Msk            (0xff00000UL)             /*!< FWID (Bitfield-Mask: 0xff)                            */
#define I2S0_I2SIOCFG_PRx_Pos             (19UL)                    /*!< PRx (Bit 19)                                          */
#define I2S0_I2SIOCFG_PRx_Msk             (0x80000UL)               /*!< PRx (Bitfield-Mask: 0x01)                             */
#define I2S0_I2SIOCFG_MSL_Pos             (18UL)                    /*!< MSL (Bit 18)                                          */
#define I2S0_I2SIOCFG_MSL_Msk             (0x40000UL)               /*!< MSL (Bitfield-Mask: 0x01)                             */
#define I2S0_I2SIOCFG_PRTX_Pos            (17UL)                    /*!< PRTX (Bit 17)                                         */
#define I2S0_I2SIOCFG_PRTX_Msk            (0x20000UL)               /*!< PRTX (Bitfield-Mask: 0x01)                            */
#define I2S0_I2SIOCFG_FSP_Pos             (16UL)                    /*!< FSP (Bit 16)                                          */
#define I2S0_I2SIOCFG_FSP_Msk             (0x10000UL)               /*!< FSP (Bitfield-Mask: 0x01)                             */
#define I2S0_I2SIOCFG_FPER_Pos            (4UL)                     /*!< FPER (Bit 4)                                          */
#define I2S0_I2SIOCFG_FPER_Msk            (0xfff0UL)                /*!< FPER (Bitfield-Mask: 0xfff)                           */
#define I2S0_I2SIOCFG_OEN_Pos             (0UL)                     /*!< OEN (Bit 0)                                           */
#define I2S0_I2SIOCFG_OEN_Msk             (0x1UL)                   /*!< OEN (Bitfield-Mask: 0x01)                             */
/* ========================================================  I2SCTL  ========================================================= */
#define I2S0_I2SCTL_I2SVAL_Pos            (31UL)                    /*!< I2SVAL (Bit 31)                                       */
#define I2S0_I2SCTL_I2SVAL_Msk            (0x80000000UL)            /*!< I2SVAL (Bitfield-Mask: 0x01)                          */
#define I2S0_I2SCTL_RXRST_Pos             (5UL)                     /*!< RXRST (Bit 5)                                         */
#define I2S0_I2SCTL_RXRST_Msk             (0x20UL)                  /*!< RXRST (Bitfield-Mask: 0x01)                           */
#define I2S0_I2SCTL_RXEN_Pos              (4UL)                     /*!< RXEN (Bit 4)                                          */
#define I2S0_I2SCTL_RXEN_Msk              (0x10UL)                  /*!< RXEN (Bitfield-Mask: 0x01)                            */
#define I2S0_I2SCTL_TXRST_Pos             (1UL)                     /*!< TXRST (Bit 1)                                         */
#define I2S0_I2SCTL_TXRST_Msk             (0x2UL)                   /*!< TXRST (Bitfield-Mask: 0x01)                           */
#define I2S0_I2SCTL_TXEN_Pos              (0UL)                     /*!< TXEN (Bit 0)                                          */
#define I2S0_I2SCTL_TXEN_Msk              (0x1UL)                   /*!< TXEN (Bitfield-Mask: 0x01)                            */
/* ========================================================  IPBIRPT  ======================================================== */
#define I2S0_IPBIRPT_TXDMAI_Pos           (21UL)                    /*!< TXDMAI (Bit 21)                                       */
#define I2S0_IPBIRPT_TXDMAI_Msk           (0x200000UL)              /*!< TXDMAI (Bitfield-Mask: 0x01)                          */
#define I2S0_IPBIRPT_RXDMAI_Pos           (20UL)                    /*!< RXDMAI (Bit 20)                                       */
#define I2S0_IPBIRPT_RXDMAI_Msk           (0x100000UL)              /*!< RXDMAI (Bitfield-Mask: 0x01)                          */
#define I2S0_IPBIRPT_TXEI_Pos             (19UL)                    /*!< TXEI (Bit 19)                                         */
#define I2S0_IPBIRPT_TXEI_Msk             (0x80000UL)               /*!< TXEI (Bitfield-Mask: 0x01)                            */
#define I2S0_IPBIRPT_RXFI_Pos             (18UL)                    /*!< RXFI (Bit 18)                                         */
#define I2S0_IPBIRPT_RXFI_Msk             (0x40000UL)               /*!< RXFI (Bitfield-Mask: 0x01)                            */
#define I2S0_IPBIRPT_TXFFI_Pos            (17UL)                    /*!< TXFFI (Bit 17)                                        */
#define I2S0_IPBIRPT_TXFFI_Msk            (0x20000UL)               /*!< TXFFI (Bitfield-Mask: 0x01)                           */
#define I2S0_IPBIRPT_RXFFI_Pos            (16UL)                    /*!< RXFFI (Bit 16)                                        */
#define I2S0_IPBIRPT_RXFFI_Msk            (0x10000UL)               /*!< RXFFI (Bitfield-Mask: 0x01)                           */
#define I2S0_IPBIRPT_TXDMAM_Pos           (5UL)                     /*!< TXDMAM (Bit 5)                                        */
#define I2S0_IPBIRPT_TXDMAM_Msk           (0x20UL)                  /*!< TXDMAM (Bitfield-Mask: 0x01)                          */
#define I2S0_IPBIRPT_RXDMAM_Pos           (4UL)                     /*!< RXDMAM (Bit 4)                                        */
#define I2S0_IPBIRPT_RXDMAM_Msk           (0x10UL)                  /*!< RXDMAM (Bitfield-Mask: 0x01)                          */
#define I2S0_IPBIRPT_TXEM_Pos             (3UL)                     /*!< TXEM (Bit 3)                                          */
#define I2S0_IPBIRPT_TXEM_Msk             (0x8UL)                   /*!< TXEM (Bitfield-Mask: 0x01)                            */
#define I2S0_IPBIRPT_RXFM_Pos             (2UL)                     /*!< RXFM (Bit 2)                                          */
#define I2S0_IPBIRPT_RXFM_Msk             (0x4UL)                   /*!< RXFM (Bitfield-Mask: 0x01)                            */
#define I2S0_IPBIRPT_TXFFM_Pos            (1UL)                     /*!< TXFFM (Bit 1)                                         */
#define I2S0_IPBIRPT_TXFFM_Msk            (0x2UL)                   /*!< TXFFM (Bitfield-Mask: 0x01)                           */
#define I2S0_IPBIRPT_RXFFM_Pos            (0UL)                     /*!< RXFFM (Bit 0)                                         */
#define I2S0_IPBIRPT_RXFFM_Msk            (0x1UL)                   /*!< RXFFM (Bitfield-Mask: 0x01)                           */
/* =======================================================  IPCOREID  ======================================================== */
#define I2S0_IPCOREID_COREFAM_Pos         (24UL)                    /*!< COREFAM (Bit 24)                                      */
#define I2S0_IPCOREID_COREFAM_Msk         (0xff000000UL)            /*!< COREFAM (Bitfield-Mask: 0xff)                         */
#define I2S0_IPCOREID_COREID_Pos          (16UL)                    /*!< COREID (Bit 16)                                       */
#define I2S0_IPCOREID_COREID_Msk          (0xff0000UL)              /*!< COREID (Bitfield-Mask: 0xff)                          */
/* ========================================================  AMQCFG  ========================================================= */
#define I2S0_AMQCFG_MCLKSRC_Pos           (0UL)                     /*!< MCLKSRC (Bit 0)                                       */
#define I2S0_AMQCFG_MCLKSRC_Msk           (0x1UL)                   /*!< MCLKSRC (Bitfield-Mask: 0x01)                         */
/* ========================================================  CLKCFG  ========================================================= */
#define I2S0_CLKCFG_DIV3_Pos              (20UL)                    /*!< DIV3 (Bit 20)                                         */
#define I2S0_CLKCFG_DIV3_Msk              (0x100000UL)              /*!< DIV3 (Bitfield-Mask: 0x01)                            */
#define I2S0_CLKCFG_REFFSEL_Pos           (16UL)                    /*!< REFFSEL (Bit 16)                                      */
#define I2S0_CLKCFG_REFFSEL_Msk           (0x30000UL)               /*!< REFFSEL (Bitfield-Mask: 0x03)                         */
#define I2S0_CLKCFG_REFCLKEN_Pos          (12UL)                    /*!< REFCLKEN (Bit 12)                                     */
#define I2S0_CLKCFG_REFCLKEN_Msk          (0x1000UL)                /*!< REFCLKEN (Bitfield-Mask: 0x01)                        */
#define I2S0_CLKCFG_FSEL_Pos              (4UL)                     /*!< FSEL (Bit 4)                                          */
#define I2S0_CLKCFG_FSEL_Msk              (0x1f0UL)                 /*!< FSEL (Bitfield-Mask: 0x1f)                            */
#define I2S0_CLKCFG_MCLKEN_Pos            (0UL)                     /*!< MCLKEN (Bit 0)                                        */
#define I2S0_CLKCFG_MCLKEN_Msk            (0x1UL)                   /*!< MCLKEN (Bitfield-Mask: 0x01)                          */
/* ========================================================  DMACFG  ========================================================= */
#define I2S0_DMACFG_RXREQCNT_Pos          (16UL)                    /*!< RXREQCNT (Bit 16)                                     */
#define I2S0_DMACFG_RXREQCNT_Msk          (0xff0000UL)              /*!< RXREQCNT (Bitfield-Mask: 0xff)                        */
#define I2S0_DMACFG_TXREQCNT_Pos          (8UL)                     /*!< TXREQCNT (Bit 8)                                      */
#define I2S0_DMACFG_TXREQCNT_Msk          (0xff00UL)                /*!< TXREQCNT (Bitfield-Mask: 0xff)                        */
#define I2S0_DMACFG_TXDMAPRI_Pos          (5UL)                     /*!< TXDMAPRI (Bit 5)                                      */
#define I2S0_DMACFG_TXDMAPRI_Msk          (0x20UL)                  /*!< TXDMAPRI (Bitfield-Mask: 0x01)                        */
#define I2S0_DMACFG_TXDMAEN_Pos           (4UL)                     /*!< TXDMAEN (Bit 4)                                       */
#define I2S0_DMACFG_TXDMAEN_Msk           (0x10UL)                  /*!< TXDMAEN (Bitfield-Mask: 0x01)                         */
#define I2S0_DMACFG_RXDMAPRI_Pos          (1UL)                     /*!< RXDMAPRI (Bit 1)                                      */
#define I2S0_DMACFG_RXDMAPRI_Msk          (0x2UL)                   /*!< RXDMAPRI (Bitfield-Mask: 0x01)                        */
#define I2S0_DMACFG_RXDMAEN_Pos           (0UL)                     /*!< RXDMAEN (Bit 0)                                       */
#define I2S0_DMACFG_RXDMAEN_Msk           (0x1UL)                   /*!< RXDMAEN (Bitfield-Mask: 0x01)                         */
/* ======================================================  RXDMATOTCNT  ====================================================== */
#define I2S0_RXDMATOTCNT_RXTOTCNT_Pos     (0UL)                     /*!< RXTOTCNT (Bit 0)                                      */
#define I2S0_RXDMATOTCNT_RXTOTCNT_Msk     (0xfffUL)                 /*!< RXTOTCNT (Bitfield-Mask: 0xfff)                       */
/* =======================================================  RXDMAADDR  ======================================================= */
#define I2S0_RXDMAADDR_RXTARGADDR_Pos     (0UL)                     /*!< RXTARGADDR (Bit 0)                                    */
#define I2S0_RXDMAADDR_RXTARGADDR_Msk     (0xffffffffUL)            /*!< RXTARGADDR (Bitfield-Mask: 0xffffffff)                */
/* =======================================================  RXDMASTAT  ======================================================= */
#define I2S0_RXDMASTAT_RXDMAERR_Pos       (2UL)                     /*!< RXDMAERR (Bit 2)                                      */
#define I2S0_RXDMASTAT_RXDMAERR_Msk       (0x4UL)                   /*!< RXDMAERR (Bitfield-Mask: 0x01)                        */
#define I2S0_RXDMASTAT_RXDMACPL_Pos       (1UL)                     /*!< RXDMACPL (Bit 1)                                      */
#define I2S0_RXDMASTAT_RXDMACPL_Msk       (0x2UL)                   /*!< RXDMACPL (Bitfield-Mask: 0x01)                        */
#define I2S0_RXDMASTAT_RXDMATIP_Pos       (0UL)                     /*!< RXDMATIP (Bit 0)                                      */
#define I2S0_RXDMASTAT_RXDMATIP_Msk       (0x1UL)                   /*!< RXDMATIP (Bitfield-Mask: 0x01)                        */
/* ======================================================  TXDMATOTCNT  ====================================================== */
#define I2S0_TXDMATOTCNT_TXTOTCNT_Pos     (0UL)                     /*!< TXTOTCNT (Bit 0)                                      */
#define I2S0_TXDMATOTCNT_TXTOTCNT_Msk     (0xfffUL)                 /*!< TXTOTCNT (Bitfield-Mask: 0xfff)                       */
/* =======================================================  TXDMAADDR  ======================================================= */
#define I2S0_TXDMAADDR_TXTARGADDR_Pos     (0UL)                     /*!< TXTARGADDR (Bit 0)                                    */
#define I2S0_TXDMAADDR_TXTARGADDR_Msk     (0xffffffffUL)            /*!< TXTARGADDR (Bitfield-Mask: 0xffffffff)                */
/* =======================================================  TXDMASTAT  ======================================================= */
#define I2S0_TXDMASTAT_TXDMAERR_Pos       (2UL)                     /*!< TXDMAERR (Bit 2)                                      */
#define I2S0_TXDMASTAT_TXDMAERR_Msk       (0x4UL)                   /*!< TXDMAERR (Bitfield-Mask: 0x01)                        */
#define I2S0_TXDMASTAT_TXDMACPL_Pos       (1UL)                     /*!< TXDMACPL (Bit 1)                                      */
#define I2S0_TXDMASTAT_TXDMACPL_Msk       (0x2UL)                   /*!< TXDMACPL (Bitfield-Mask: 0x01)                        */
#define I2S0_TXDMASTAT_TXDMATIP_Pos       (0UL)                     /*!< TXDMATIP (Bit 0)                                      */
#define I2S0_TXDMASTAT_TXDMATIP_Msk       (0x1UL)                   /*!< TXDMATIP (Bitfield-Mask: 0x01)                        */
/* ========================================================  STATUS  ========================================================= */
#define I2S0_STATUS_TBD_Pos               (0UL)                     /*!< TBD (Bit 0)                                           */
#define I2S0_STATUS_TBD_Msk               (0x1UL)                   /*!< TBD (Bitfield-Mask: 0x01)                             */
/* =========================================================  INTEN  ========================================================= */
#define I2S0_INTEN_RXDMACPL_Pos           (4UL)                     /*!< RXDMACPL (Bit 4)                                      */
#define I2S0_INTEN_RXDMACPL_Msk           (0x10UL)                  /*!< RXDMACPL (Bitfield-Mask: 0x01)                        */
#define I2S0_INTEN_TXDMACPL_Pos           (3UL)                     /*!< TXDMACPL (Bit 3)                                      */
#define I2S0_INTEN_TXDMACPL_Msk           (0x8UL)                   /*!< TXDMACPL (Bitfield-Mask: 0x01)                        */
#define I2S0_INTEN_TXREQCNT_Pos           (2UL)                     /*!< TXREQCNT (Bit 2)                                      */
#define I2S0_INTEN_TXREQCNT_Msk           (0x4UL)                   /*!< TXREQCNT (Bitfield-Mask: 0x01)                        */
#define I2S0_INTEN_RXREQCNT_Pos           (1UL)                     /*!< RXREQCNT (Bit 1)                                      */
#define I2S0_INTEN_RXREQCNT_Msk           (0x2UL)                   /*!< RXREQCNT (Bitfield-Mask: 0x01)                        */
#define I2S0_INTEN_IPB_Pos                (0UL)                     /*!< IPB (Bit 0)                                           */
#define I2S0_INTEN_IPB_Msk                (0x1UL)                   /*!< IPB (Bitfield-Mask: 0x01)                             */
/* ========================================================  INTSTAT  ======================================================== */
#define I2S0_INTSTAT_RXDMACPL_Pos         (4UL)                     /*!< RXDMACPL (Bit 4)                                      */
#define I2S0_INTSTAT_RXDMACPL_Msk         (0x10UL)                  /*!< RXDMACPL (Bitfield-Mask: 0x01)                        */
#define I2S0_INTSTAT_TXDMACPL_Pos         (3UL)                     /*!< TXDMACPL (Bit 3)                                      */
#define I2S0_INTSTAT_TXDMACPL_Msk         (0x8UL)                   /*!< TXDMACPL (Bitfield-Mask: 0x01)                        */
#define I2S0_INTSTAT_TXREQCNT_Pos         (2UL)                     /*!< TXREQCNT (Bit 2)                                      */
#define I2S0_INTSTAT_TXREQCNT_Msk         (0x4UL)                   /*!< TXREQCNT (Bitfield-Mask: 0x01)                        */
#define I2S0_INTSTAT_RXREQCNT_Pos         (1UL)                     /*!< RXREQCNT (Bit 1)                                      */
#define I2S0_INTSTAT_RXREQCNT_Msk         (0x2UL)                   /*!< RXREQCNT (Bitfield-Mask: 0x01)                        */
#define I2S0_INTSTAT_IPB_Pos              (0UL)                     /*!< IPB (Bit 0)                                           */
#define I2S0_INTSTAT_IPB_Msk              (0x1UL)                   /*!< IPB (Bitfield-Mask: 0x01)                             */
/* ========================================================  INTCLR  ========================================================= */
#define I2S0_INTCLR_RXDMACPL_Pos          (4UL)                     /*!< RXDMACPL (Bit 4)                                      */
#define I2S0_INTCLR_RXDMACPL_Msk          (0x10UL)                  /*!< RXDMACPL (Bitfield-Mask: 0x01)                        */
#define I2S0_INTCLR_TXDMACPL_Pos          (3UL)                     /*!< TXDMACPL (Bit 3)                                      */
#define I2S0_INTCLR_TXDMACPL_Msk          (0x8UL)                   /*!< TXDMACPL (Bitfield-Mask: 0x01)                        */
#define I2S0_INTCLR_TXREQCNT_Pos          (2UL)                     /*!< TXREQCNT (Bit 2)                                      */
#define I2S0_INTCLR_TXREQCNT_Msk          (0x4UL)                   /*!< TXREQCNT (Bitfield-Mask: 0x01)                        */
#define I2S0_INTCLR_RXREQCNT_Pos          (1UL)                     /*!< RXREQCNT (Bit 1)                                      */
#define I2S0_INTCLR_RXREQCNT_Msk          (0x2UL)                   /*!< RXREQCNT (Bitfield-Mask: 0x01)                        */
#define I2S0_INTCLR_IPB_Pos               (0UL)                     /*!< IPB (Bit 0)                                           */
#define I2S0_INTCLR_IPB_Msk               (0x1UL)                   /*!< IPB (Bitfield-Mask: 0x01)                             */
/* ========================================================  INTSET  ========================================================= */
#define I2S0_INTSET_RXDMACPL_Pos          (4UL)                     /*!< RXDMACPL (Bit 4)                                      */
#define I2S0_INTSET_RXDMACPL_Msk          (0x10UL)                  /*!< RXDMACPL (Bitfield-Mask: 0x01)                        */
#define I2S0_INTSET_TXDMACPL_Pos          (3UL)                     /*!< TXDMACPL (Bit 3)                                      */
#define I2S0_INTSET_TXDMACPL_Msk          (0x8UL)                   /*!< TXDMACPL (Bitfield-Mask: 0x01)                        */
#define I2S0_INTSET_TXREQCNT_Pos          (2UL)                     /*!< TXREQCNT (Bit 2)                                      */
#define I2S0_INTSET_TXREQCNT_Msk          (0x4UL)                   /*!< TXREQCNT (Bitfield-Mask: 0x01)                        */
#define I2S0_INTSET_RXREQCNT_Pos          (1UL)                     /*!< RXREQCNT (Bit 1)                                      */
#define I2S0_INTSET_RXREQCNT_Msk          (0x2UL)                   /*!< RXREQCNT (Bitfield-Mask: 0x01)                        */
#define I2S0_INTSET_IPB_Pos               (0UL)                     /*!< IPB (Bit 0)                                           */
#define I2S0_INTSET_IPB_Msk               (0x1UL)                   /*!< IPB (Bitfield-Mask: 0x01)                             */
/* ========================================================  I2SDBG  ========================================================= */
#define I2S0_I2SDBG_DBGDATA_Pos           (3UL)                     /*!< DBGDATA (Bit 3)                                       */
#define I2S0_I2SDBG_DBGDATA_Msk           (0xfffffff8UL)            /*!< DBGDATA (Bitfield-Mask: 0x1fffffff)                   */
#define I2S0_I2SDBG_APBCLKON_Pos          (2UL)                     /*!< APBCLKON (Bit 2)                                      */
#define I2S0_I2SDBG_APBCLKON_Msk          (0x4UL)                   /*!< APBCLKON (Bitfield-Mask: 0x01)                        */
#define I2S0_I2SDBG_MCLKON_Pos            (1UL)                     /*!< MCLKON (Bit 1)                                        */
#define I2S0_I2SDBG_MCLKON_Msk            (0x2UL)                   /*!< MCLKON (Bitfield-Mask: 0x01)                          */
#define I2S0_I2SDBG_DBGEN_Pos             (0UL)                     /*!< DBGEN (Bit 0)                                         */
#define I2S0_I2SDBG_DBGEN_Msk             (0x1UL)                   /*!< DBGEN (Bitfield-Mask: 0x01)                           */


/* =========================================================================================================================== */
/* ================                                           IOM0                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  FIFO  ========================================================== */
#define IOM0_FIFO_FIFO_Pos                (0UL)                     /*!< FIFO (Bit 0)                                          */
#define IOM0_FIFO_FIFO_Msk                (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
/* ========================================================  FIFOPTR  ======================================================== */
#define IOM0_FIFOPTR_FIFO1REM_Pos         (24UL)                    /*!< FIFO1REM (Bit 24)                                     */
#define IOM0_FIFOPTR_FIFO1REM_Msk         (0xff000000UL)            /*!< FIFO1REM (Bitfield-Mask: 0xff)                        */
#define IOM0_FIFOPTR_FIFO1SIZ_Pos         (16UL)                    /*!< FIFO1SIZ (Bit 16)                                     */
#define IOM0_FIFOPTR_FIFO1SIZ_Msk         (0xff0000UL)              /*!< FIFO1SIZ (Bitfield-Mask: 0xff)                        */
#define IOM0_FIFOPTR_FIFO0REM_Pos         (8UL)                     /*!< FIFO0REM (Bit 8)                                      */
#define IOM0_FIFOPTR_FIFO0REM_Msk         (0xff00UL)                /*!< FIFO0REM (Bitfield-Mask: 0xff)                        */
#define IOM0_FIFOPTR_FIFO0SIZ_Pos         (0UL)                     /*!< FIFO0SIZ (Bit 0)                                      */
#define IOM0_FIFOPTR_FIFO0SIZ_Msk         (0xffUL)                  /*!< FIFO0SIZ (Bitfield-Mask: 0xff)                        */
/* ========================================================  FIFOTHR  ======================================================== */
#define IOM0_FIFOTHR_FIFOWTHR_Pos         (8UL)                     /*!< FIFOWTHR (Bit 8)                                      */
#define IOM0_FIFOTHR_FIFOWTHR_Msk         (0x3f00UL)                /*!< FIFOWTHR (Bitfield-Mask: 0x3f)                        */
#define IOM0_FIFOTHR_FIFORTHR_Pos         (0UL)                     /*!< FIFORTHR (Bit 0)                                      */
#define IOM0_FIFOTHR_FIFORTHR_Msk         (0x3fUL)                  /*!< FIFORTHR (Bitfield-Mask: 0x3f)                        */
/* ========================================================  FIFOPOP  ======================================================== */
#define IOM0_FIFOPOP_FIFODOUT_Pos         (0UL)                     /*!< FIFODOUT (Bit 0)                                      */
#define IOM0_FIFOPOP_FIFODOUT_Msk         (0xffffffffUL)            /*!< FIFODOUT (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  FIFOPUSH  ======================================================== */
#define IOM0_FIFOPUSH_FIFODIN_Pos         (0UL)                     /*!< FIFODIN (Bit 0)                                       */
#define IOM0_FIFOPUSH_FIFODIN_Msk         (0xffffffffUL)            /*!< FIFODIN (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  FIFOCTRL  ======================================================== */
#define IOM0_FIFOCTRL_FIFORSTN_Pos        (1UL)                     /*!< FIFORSTN (Bit 1)                                      */
#define IOM0_FIFOCTRL_FIFORSTN_Msk        (0x2UL)                   /*!< FIFORSTN (Bitfield-Mask: 0x01)                        */
#define IOM0_FIFOCTRL_POPWR_Pos           (0UL)                     /*!< POPWR (Bit 0)                                         */
#define IOM0_FIFOCTRL_POPWR_Msk           (0x1UL)                   /*!< POPWR (Bitfield-Mask: 0x01)                           */
/* ========================================================  FIFOLOC  ======================================================== */
#define IOM0_FIFOLOC_FIFORPTR_Pos         (8UL)                     /*!< FIFORPTR (Bit 8)                                      */
#define IOM0_FIFOLOC_FIFORPTR_Msk         (0xf00UL)                 /*!< FIFORPTR (Bitfield-Mask: 0x0f)                        */
#define IOM0_FIFOLOC_FIFOWPTR_Pos         (0UL)                     /*!< FIFOWPTR (Bit 0)                                      */
#define IOM0_FIFOLOC_FIFOWPTR_Msk         (0xfUL)                   /*!< FIFOWPTR (Bitfield-Mask: 0x0f)                        */
/* ========================================================  CLKCFG  ========================================================= */
#define IOM0_CLKCFG_TOTPER_Pos            (24UL)                    /*!< TOTPER (Bit 24)                                       */
#define IOM0_CLKCFG_TOTPER_Msk            (0xff000000UL)            /*!< TOTPER (Bitfield-Mask: 0xff)                          */
#define IOM0_CLKCFG_LOWPER_Pos            (16UL)                    /*!< LOWPER (Bit 16)                                       */
#define IOM0_CLKCFG_LOWPER_Msk            (0xff0000UL)              /*!< LOWPER (Bitfield-Mask: 0xff)                          */
#define IOM0_CLKCFG_DIVEN_Pos             (12UL)                    /*!< DIVEN (Bit 12)                                        */
#define IOM0_CLKCFG_DIVEN_Msk             (0x1000UL)                /*!< DIVEN (Bitfield-Mask: 0x01)                           */
#define IOM0_CLKCFG_DIV3_Pos              (11UL)                    /*!< DIV3 (Bit 11)                                         */
#define IOM0_CLKCFG_DIV3_Msk              (0x800UL)                 /*!< DIV3 (Bitfield-Mask: 0x01)                            */
#define IOM0_CLKCFG_FSEL_Pos              (8UL)                     /*!< FSEL (Bit 8)                                          */
#define IOM0_CLKCFG_FSEL_Msk              (0x700UL)                 /*!< FSEL (Bitfield-Mask: 0x07)                            */
#define IOM0_CLKCFG_IOCLKEN_Pos           (0UL)                     /*!< IOCLKEN (Bit 0)                                       */
#define IOM0_CLKCFG_IOCLKEN_Msk           (0x1UL)                   /*!< IOCLKEN (Bitfield-Mask: 0x01)                         */
/* ======================================================  SUBMODCTRL  ======================================================= */
#define IOM0_SUBMODCTRL_SMOD2TYPE_Pos     (9UL)                     /*!< SMOD2TYPE (Bit 9)                                     */
#define IOM0_SUBMODCTRL_SMOD2TYPE_Msk     (0xe00UL)                 /*!< SMOD2TYPE (Bitfield-Mask: 0x07)                       */
#define IOM0_SUBMODCTRL_SMOD2EN_Pos       (8UL)                     /*!< SMOD2EN (Bit 8)                                       */
#define IOM0_SUBMODCTRL_SMOD2EN_Msk       (0x100UL)                 /*!< SMOD2EN (Bitfield-Mask: 0x01)                         */
#define IOM0_SUBMODCTRL_SMOD1TYPE_Pos     (5UL)                     /*!< SMOD1TYPE (Bit 5)                                     */
#define IOM0_SUBMODCTRL_SMOD1TYPE_Msk     (0xe0UL)                  /*!< SMOD1TYPE (Bitfield-Mask: 0x07)                       */
#define IOM0_SUBMODCTRL_SMOD1EN_Pos       (4UL)                     /*!< SMOD1EN (Bit 4)                                       */
#define IOM0_SUBMODCTRL_SMOD1EN_Msk       (0x10UL)                  /*!< SMOD1EN (Bitfield-Mask: 0x01)                         */
#define IOM0_SUBMODCTRL_SMOD0TYPE_Pos     (1UL)                     /*!< SMOD0TYPE (Bit 1)                                     */
#define IOM0_SUBMODCTRL_SMOD0TYPE_Msk     (0xeUL)                   /*!< SMOD0TYPE (Bitfield-Mask: 0x07)                       */
#define IOM0_SUBMODCTRL_SMOD0EN_Pos       (0UL)                     /*!< SMOD0EN (Bit 0)                                       */
#define IOM0_SUBMODCTRL_SMOD0EN_Msk       (0x1UL)                   /*!< SMOD0EN (Bitfield-Mask: 0x01)                         */
/* ==========================================================  CMD  ========================================================== */
#define IOM0_CMD_OFFSETLO_Pos             (24UL)                    /*!< OFFSETLO (Bit 24)                                     */
#define IOM0_CMD_OFFSETLO_Msk             (0xff000000UL)            /*!< OFFSETLO (Bitfield-Mask: 0xff)                        */
#define IOM0_CMD_CMDSEL_Pos               (20UL)                    /*!< CMDSEL (Bit 20)                                       */
#define IOM0_CMD_CMDSEL_Msk               (0x300000UL)              /*!< CMDSEL (Bitfield-Mask: 0x03)                          */
#define IOM0_CMD_TSIZE_Pos                (8UL)                     /*!< TSIZE (Bit 8)                                         */
#define IOM0_CMD_TSIZE_Msk                (0xfff00UL)               /*!< TSIZE (Bitfield-Mask: 0xfff)                          */
#define IOM0_CMD_CONT_Pos                 (7UL)                     /*!< CONT (Bit 7)                                          */
#define IOM0_CMD_CONT_Msk                 (0x80UL)                  /*!< CONT (Bitfield-Mask: 0x01)                            */
#define IOM0_CMD_OFFSETCNT_Pos            (4UL)                     /*!< OFFSETCNT (Bit 4)                                     */
#define IOM0_CMD_OFFSETCNT_Msk            (0x70UL)                  /*!< OFFSETCNT (Bitfield-Mask: 0x07)                       */
#define IOM0_CMD_CMD_Pos                  (0UL)                     /*!< CMD (Bit 0)                                           */
#define IOM0_CMD_CMD_Msk                  (0xfUL)                   /*!< CMD (Bitfield-Mask: 0x0f)                             */
/* ========================================================  DCXCTRL  ======================================================== */
#define IOM0_DCXCTRL_DCXEN_Pos            (4UL)                     /*!< DCXEN (Bit 4)                                         */
#define IOM0_DCXCTRL_DCXEN_Msk            (0x10UL)                  /*!< DCXEN (Bitfield-Mask: 0x01)                           */
#define IOM0_DCXCTRL_DCXSEL_Pos           (0UL)                     /*!< DCXSEL (Bit 0)                                        */
#define IOM0_DCXCTRL_DCXSEL_Msk           (0xfUL)                   /*!< DCXSEL (Bitfield-Mask: 0x0f)                          */
/* =======================================================  OFFSETHI  ======================================================== */
#define IOM0_OFFSETHI_OFFSETHI_Pos        (0UL)                     /*!< OFFSETHI (Bit 0)                                      */
#define IOM0_OFFSETHI_OFFSETHI_Msk        (0xffffffffUL)            /*!< OFFSETHI (Bitfield-Mask: 0xffffffff)                  */
/* ========================================================  CMDSTAT  ======================================================== */
#define IOM0_CMDSTAT_CTSIZE_Pos           (8UL)                     /*!< CTSIZE (Bit 8)                                        */
#define IOM0_CMDSTAT_CTSIZE_Msk           (0xfff00UL)               /*!< CTSIZE (Bitfield-Mask: 0xfff)                         */
#define IOM0_CMDSTAT_CMDSTAT_Pos          (5UL)                     /*!< CMDSTAT (Bit 5)                                       */
#define IOM0_CMDSTAT_CMDSTAT_Msk          (0xe0UL)                  /*!< CMDSTAT (Bitfield-Mask: 0x07)                         */
#define IOM0_CMDSTAT_CCMD_Pos             (0UL)                     /*!< CCMD (Bit 0)                                          */
#define IOM0_CMDSTAT_CCMD_Msk             (0x1fUL)                  /*!< CCMD (Bitfield-Mask: 0x1f)                            */
/* =========================================================  INTEN  ========================================================= */
#define IOM0_INTEN_CQERR_Pos              (14UL)                    /*!< CQERR (Bit 14)                                        */
#define IOM0_INTEN_CQERR_Msk              (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
#define IOM0_INTEN_CQUPD_Pos              (13UL)                    /*!< CQUPD (Bit 13)                                        */
#define IOM0_INTEN_CQUPD_Msk              (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
#define IOM0_INTEN_CQPAUSED_Pos           (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
#define IOM0_INTEN_CQPAUSED_Msk           (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
#define IOM0_INTEN_DERR_Pos               (11UL)                    /*!< DERR (Bit 11)                                         */
#define IOM0_INTEN_DERR_Msk               (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
#define IOM0_INTEN_DCMP_Pos               (10UL)                    /*!< DCMP (Bit 10)                                         */
#define IOM0_INTEN_DCMP_Msk               (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
#define IOM0_INTEN_ARB_Pos                (9UL)                     /*!< ARB (Bit 9)                                           */
#define IOM0_INTEN_ARB_Msk                (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
#define IOM0_INTEN_STOP_Pos               (8UL)                     /*!< STOP (Bit 8)                                          */
#define IOM0_INTEN_STOP_Msk               (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
#define IOM0_INTEN_START_Pos              (7UL)                     /*!< START (Bit 7)                                         */
#define IOM0_INTEN_START_Msk              (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
#define IOM0_INTEN_ICMD_Pos               (6UL)                     /*!< ICMD (Bit 6)                                          */
#define IOM0_INTEN_ICMD_Msk               (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
#define IOM0_INTEN_IACC_Pos               (5UL)                     /*!< IACC (Bit 5)                                          */
#define IOM0_INTEN_IACC_Msk               (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
#define IOM0_INTEN_NAK_Pos                (4UL)                     /*!< NAK (Bit 4)                                           */
#define IOM0_INTEN_NAK_Msk                (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
#define IOM0_INTEN_FOVFL_Pos              (3UL)                     /*!< FOVFL (Bit 3)                                         */
#define IOM0_INTEN_FOVFL_Msk              (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
#define IOM0_INTEN_FUNDFL_Pos             (2UL)                     /*!< FUNDFL (Bit 2)                                        */
#define IOM0_INTEN_FUNDFL_Msk             (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
#define IOM0_INTEN_THR_Pos                (1UL)                     /*!< THR (Bit 1)                                           */
#define IOM0_INTEN_THR_Msk                (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
#define IOM0_INTEN_CMDCMP_Pos             (0UL)                     /*!< CMDCMP (Bit 0)                                        */
#define IOM0_INTEN_CMDCMP_Msk             (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
/* ========================================================  INTSTAT  ======================================================== */
#define IOM0_INTSTAT_CQERR_Pos            (14UL)                    /*!< CQERR (Bit 14)                                        */
#define IOM0_INTSTAT_CQERR_Msk            (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
#define IOM0_INTSTAT_CQUPD_Pos            (13UL)                    /*!< CQUPD (Bit 13)                                        */
#define IOM0_INTSTAT_CQUPD_Msk            (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
#define IOM0_INTSTAT_CQPAUSED_Pos         (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
#define IOM0_INTSTAT_CQPAUSED_Msk         (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
#define IOM0_INTSTAT_DERR_Pos             (11UL)                    /*!< DERR (Bit 11)                                         */
#define IOM0_INTSTAT_DERR_Msk             (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
#define IOM0_INTSTAT_DCMP_Pos             (10UL)                    /*!< DCMP (Bit 10)                                         */
#define IOM0_INTSTAT_DCMP_Msk             (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
#define IOM0_INTSTAT_ARB_Pos              (9UL)                     /*!< ARB (Bit 9)                                           */
#define IOM0_INTSTAT_ARB_Msk              (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
#define IOM0_INTSTAT_STOP_Pos             (8UL)                     /*!< STOP (Bit 8)                                          */
#define IOM0_INTSTAT_STOP_Msk             (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
#define IOM0_INTSTAT_START_Pos            (7UL)                     /*!< START (Bit 7)                                         */
#define IOM0_INTSTAT_START_Msk            (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
#define IOM0_INTSTAT_ICMD_Pos             (6UL)                     /*!< ICMD (Bit 6)                                          */
#define IOM0_INTSTAT_ICMD_Msk             (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
#define IOM0_INTSTAT_IACC_Pos             (5UL)                     /*!< IACC (Bit 5)                                          */
#define IOM0_INTSTAT_IACC_Msk             (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
#define IOM0_INTSTAT_NAK_Pos              (4UL)                     /*!< NAK (Bit 4)                                           */
#define IOM0_INTSTAT_NAK_Msk              (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
#define IOM0_INTSTAT_FOVFL_Pos            (3UL)                     /*!< FOVFL (Bit 3)                                         */
#define IOM0_INTSTAT_FOVFL_Msk            (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
#define IOM0_INTSTAT_FUNDFL_Pos           (2UL)                     /*!< FUNDFL (Bit 2)                                        */
#define IOM0_INTSTAT_FUNDFL_Msk           (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
#define IOM0_INTSTAT_THR_Pos              (1UL)                     /*!< THR (Bit 1)                                           */
#define IOM0_INTSTAT_THR_Msk              (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
#define IOM0_INTSTAT_CMDCMP_Pos           (0UL)                     /*!< CMDCMP (Bit 0)                                        */
#define IOM0_INTSTAT_CMDCMP_Msk           (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
/* ========================================================  INTCLR  ========================================================= */
#define IOM0_INTCLR_CQERR_Pos             (14UL)                    /*!< CQERR (Bit 14)                                        */
#define IOM0_INTCLR_CQERR_Msk             (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
#define IOM0_INTCLR_CQUPD_Pos             (13UL)                    /*!< CQUPD (Bit 13)                                        */
#define IOM0_INTCLR_CQUPD_Msk             (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
#define IOM0_INTCLR_CQPAUSED_Pos          (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
#define IOM0_INTCLR_CQPAUSED_Msk          (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
#define IOM0_INTCLR_DERR_Pos              (11UL)                    /*!< DERR (Bit 11)                                         */
#define IOM0_INTCLR_DERR_Msk              (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
#define IOM0_INTCLR_DCMP_Pos              (10UL)                    /*!< DCMP (Bit 10)                                         */
#define IOM0_INTCLR_DCMP_Msk              (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
#define IOM0_INTCLR_ARB_Pos               (9UL)                     /*!< ARB (Bit 9)                                           */
#define IOM0_INTCLR_ARB_Msk               (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
#define IOM0_INTCLR_STOP_Pos              (8UL)                     /*!< STOP (Bit 8)                                          */
#define IOM0_INTCLR_STOP_Msk              (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
#define IOM0_INTCLR_START_Pos             (7UL)                     /*!< START (Bit 7)                                         */
#define IOM0_INTCLR_START_Msk             (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
#define IOM0_INTCLR_ICMD_Pos              (6UL)                     /*!< ICMD (Bit 6)                                          */
#define IOM0_INTCLR_ICMD_Msk              (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
#define IOM0_INTCLR_IACC_Pos              (5UL)                     /*!< IACC (Bit 5)                                          */
#define IOM0_INTCLR_IACC_Msk              (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
#define IOM0_INTCLR_NAK_Pos               (4UL)                     /*!< NAK (Bit 4)                                           */
#define IOM0_INTCLR_NAK_Msk               (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
#define IOM0_INTCLR_FOVFL_Pos             (3UL)                     /*!< FOVFL (Bit 3)                                         */
#define IOM0_INTCLR_FOVFL_Msk             (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
#define IOM0_INTCLR_FUNDFL_Pos            (2UL)                     /*!< FUNDFL (Bit 2)                                        */
#define IOM0_INTCLR_FUNDFL_Msk            (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
#define IOM0_INTCLR_THR_Pos               (1UL)                     /*!< THR (Bit 1)                                           */
#define IOM0_INTCLR_THR_Msk               (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
#define IOM0_INTCLR_CMDCMP_Pos            (0UL)                     /*!< CMDCMP (Bit 0)                                        */
#define IOM0_INTCLR_CMDCMP_Msk            (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
/* ========================================================  INTSET  ========================================================= */
#define IOM0_INTSET_CQERR_Pos             (14UL)                    /*!< CQERR (Bit 14)                                        */
#define IOM0_INTSET_CQERR_Msk             (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
#define IOM0_INTSET_CQUPD_Pos             (13UL)                    /*!< CQUPD (Bit 13)                                        */
#define IOM0_INTSET_CQUPD_Msk             (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
#define IOM0_INTSET_CQPAUSED_Pos          (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
#define IOM0_INTSET_CQPAUSED_Msk          (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
#define IOM0_INTSET_DERR_Pos              (11UL)                    /*!< DERR (Bit 11)                                         */
#define IOM0_INTSET_DERR_Msk              (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
#define IOM0_INTSET_DCMP_Pos              (10UL)                    /*!< DCMP (Bit 10)                                         */
#define IOM0_INTSET_DCMP_Msk              (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
#define IOM0_INTSET_ARB_Pos               (9UL)                     /*!< ARB (Bit 9)                                           */
#define IOM0_INTSET_ARB_Msk               (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
#define IOM0_INTSET_STOP_Pos              (8UL)                     /*!< STOP (Bit 8)                                          */
#define IOM0_INTSET_STOP_Msk              (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
#define IOM0_INTSET_START_Pos             (7UL)                     /*!< START (Bit 7)                                         */
#define IOM0_INTSET_START_Msk             (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
#define IOM0_INTSET_ICMD_Pos              (6UL)                     /*!< ICMD (Bit 6)                                          */
#define IOM0_INTSET_ICMD_Msk              (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
#define IOM0_INTSET_IACC_Pos              (5UL)                     /*!< IACC (Bit 5)                                          */
#define IOM0_INTSET_IACC_Msk              (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
#define IOM0_INTSET_NAK_Pos               (4UL)                     /*!< NAK (Bit 4)                                           */
#define IOM0_INTSET_NAK_Msk               (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
#define IOM0_INTSET_FOVFL_Pos             (3UL)                     /*!< FOVFL (Bit 3)                                         */
#define IOM0_INTSET_FOVFL_Msk             (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
#define IOM0_INTSET_FUNDFL_Pos            (2UL)                     /*!< FUNDFL (Bit 2)                                        */
#define IOM0_INTSET_FUNDFL_Msk            (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
#define IOM0_INTSET_THR_Pos               (1UL)                     /*!< THR (Bit 1)                                           */
#define IOM0_INTSET_THR_Msk               (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
#define IOM0_INTSET_CMDCMP_Pos            (0UL)                     /*!< CMDCMP (Bit 0)                                        */
#define IOM0_INTSET_CMDCMP_Msk            (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
/* =======================================================  DMATRIGEN  ======================================================= */
#define IOM0_DMATRIGEN_DTHREN_Pos         (1UL)                     /*!< DTHREN (Bit 1)                                        */
#define IOM0_DMATRIGEN_DTHREN_Msk         (0x2UL)                   /*!< DTHREN (Bitfield-Mask: 0x01)                          */
#define IOM0_DMATRIGEN_DCMDCMPEN_Pos      (0UL)                     /*!< DCMDCMPEN (Bit 0)                                     */
#define IOM0_DMATRIGEN_DCMDCMPEN_Msk      (0x1UL)                   /*!< DCMDCMPEN (Bitfield-Mask: 0x01)                       */
/* ======================================================  DMATRIGSTAT  ====================================================== */
#define IOM0_DMATRIGSTAT_DTOTCMP_Pos      (2UL)                     /*!< DTOTCMP (Bit 2)                                       */
#define IOM0_DMATRIGSTAT_DTOTCMP_Msk      (0x4UL)                   /*!< DTOTCMP (Bitfield-Mask: 0x01)                         */
#define IOM0_DMATRIGSTAT_DTHR_Pos         (1UL)                     /*!< DTHR (Bit 1)                                          */
#define IOM0_DMATRIGSTAT_DTHR_Msk         (0x2UL)                   /*!< DTHR (Bitfield-Mask: 0x01)                            */
#define IOM0_DMATRIGSTAT_DCMDCMP_Pos      (0UL)                     /*!< DCMDCMP (Bit 0)                                       */
#define IOM0_DMATRIGSTAT_DCMDCMP_Msk      (0x1UL)                   /*!< DCMDCMP (Bitfield-Mask: 0x01)                         */
/* ========================================================  DMACFG  ========================================================= */
#define IOM0_DMACFG_DPWROFF_Pos           (9UL)                     /*!< DPWROFF (Bit 9)                                       */
#define IOM0_DMACFG_DPWROFF_Msk           (0x200UL)                 /*!< DPWROFF (Bitfield-Mask: 0x01)                         */
#define IOM0_DMACFG_DMAPRI_Pos            (8UL)                     /*!< DMAPRI (Bit 8)                                        */
#define IOM0_DMACFG_DMAPRI_Msk            (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
#define IOM0_DMACFG_DMADIR_Pos            (1UL)                     /*!< DMADIR (Bit 1)                                        */
#define IOM0_DMACFG_DMADIR_Msk            (0x2UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
#define IOM0_DMACFG_DMAEN_Pos             (0UL)                     /*!< DMAEN (Bit 0)                                         */
#define IOM0_DMACFG_DMAEN_Msk             (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
/* ======================================================  DMATOTCOUNT  ====================================================== */
#define IOM0_DMATOTCOUNT_TOTCOUNT_Pos     (0UL)                     /*!< TOTCOUNT (Bit 0)                                      */
#define IOM0_DMATOTCOUNT_TOTCOUNT_Msk     (0xfffUL)                 /*!< TOTCOUNT (Bitfield-Mask: 0xfff)                       */
/* ======================================================  DMATARGADDR  ====================================================== */
#define IOM0_DMATARGADDR_TARGADDR_Pos     (0UL)                     /*!< TARGADDR (Bit 0)                                      */
#define IOM0_DMATARGADDR_TARGADDR_Msk     (0x1fffffffUL)            /*!< TARGADDR (Bitfield-Mask: 0x1fffffff)                  */
/* ========================================================  DMASTAT  ======================================================== */
#define IOM0_DMASTAT_DMAERR_Pos           (2UL)                     /*!< DMAERR (Bit 2)                                        */
#define IOM0_DMASTAT_DMAERR_Msk           (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
#define IOM0_DMASTAT_DMACPL_Pos           (1UL)                     /*!< DMACPL (Bit 1)                                        */
#define IOM0_DMASTAT_DMACPL_Msk           (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
#define IOM0_DMASTAT_DMATIP_Pos           (0UL)                     /*!< DMATIP (Bit 0)                                        */
#define IOM0_DMASTAT_DMATIP_Msk           (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
/* =========================================================  CQCFG  ========================================================= */
#define IOM0_CQCFG_MSPIFLGSEL_Pos         (2UL)                     /*!< MSPIFLGSEL (Bit 2)                                    */
#define IOM0_CQCFG_MSPIFLGSEL_Msk         (0xcUL)                   /*!< MSPIFLGSEL (Bitfield-Mask: 0x03)                      */
#define IOM0_CQCFG_CQPRI_Pos              (1UL)                     /*!< CQPRI (Bit 1)                                         */
#define IOM0_CQCFG_CQPRI_Msk              (0x2UL)                   /*!< CQPRI (Bitfield-Mask: 0x01)                           */
#define IOM0_CQCFG_CQEN_Pos               (0UL)                     /*!< CQEN (Bit 0)                                          */
#define IOM0_CQCFG_CQEN_Msk               (0x1UL)                   /*!< CQEN (Bitfield-Mask: 0x01)                            */
/* ========================================================  CQADDR  ========================================================= */
#define IOM0_CQADDR_CQADDR_Pos            (2UL)                     /*!< CQADDR (Bit 2)                                        */
#define IOM0_CQADDR_CQADDR_Msk            (0x1ffffffcUL)            /*!< CQADDR (Bitfield-Mask: 0x7ffffff)                     */
/* ========================================================  CQSTAT  ========================================================= */
#define IOM0_CQSTAT_CQERR_Pos             (2UL)                     /*!< CQERR (Bit 2)                                         */
#define IOM0_CQSTAT_CQERR_Msk             (0x4UL)                   /*!< CQERR (Bitfield-Mask: 0x01)                           */
#define IOM0_CQSTAT_CQPAUSED_Pos          (1UL)                     /*!< CQPAUSED (Bit 1)                                      */
#define IOM0_CQSTAT_CQPAUSED_Msk          (0x2UL)                   /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
#define IOM0_CQSTAT_CQTIP_Pos             (0UL)                     /*!< CQTIP (Bit 0)                                         */
#define IOM0_CQSTAT_CQTIP_Msk             (0x1UL)                   /*!< CQTIP (Bitfield-Mask: 0x01)                           */
/* ========================================================  CQFLAGS  ======================================================== */
#define IOM0_CQFLAGS_CQIRQMASK_Pos        (16UL)                    /*!< CQIRQMASK (Bit 16)                                    */
#define IOM0_CQFLAGS_CQIRQMASK_Msk        (0xffff0000UL)            /*!< CQIRQMASK (Bitfield-Mask: 0xffff)                     */
#define IOM0_CQFLAGS_CQFLAGS_Pos          (0UL)                     /*!< CQFLAGS (Bit 0)                                       */
#define IOM0_CQFLAGS_CQFLAGS_Msk          (0xffffUL)                /*!< CQFLAGS (Bitfield-Mask: 0xffff)                       */
/* ======================================================  CQSETCLEAR  ======================================================= */
#define IOM0_CQSETCLEAR_CQFCLR_Pos        (16UL)                    /*!< CQFCLR (Bit 16)                                       */
#define IOM0_CQSETCLEAR_CQFCLR_Msk        (0xff0000UL)              /*!< CQFCLR (Bitfield-Mask: 0xff)                          */
#define IOM0_CQSETCLEAR_CQFTGL_Pos        (8UL)                     /*!< CQFTGL (Bit 8)                                        */
#define IOM0_CQSETCLEAR_CQFTGL_Msk        (0xff00UL)                /*!< CQFTGL (Bitfield-Mask: 0xff)                          */
#define IOM0_CQSETCLEAR_CQFSET_Pos        (0UL)                     /*!< CQFSET (Bit 0)                                        */
#define IOM0_CQSETCLEAR_CQFSET_Msk        (0xffUL)                  /*!< CQFSET (Bitfield-Mask: 0xff)                          */
/* =======================================================  CQPAUSEEN  ======================================================= */
#define IOM0_CQPAUSEEN_CQPEN_Pos          (0UL)                     /*!< CQPEN (Bit 0)                                         */
#define IOM0_CQPAUSEEN_CQPEN_Msk          (0xffffUL)                /*!< CQPEN (Bitfield-Mask: 0xffff)                         */
/* =======================================================  CQCURIDX  ======================================================== */
#define IOM0_CQCURIDX_CQCURIDX_Pos        (0UL)                     /*!< CQCURIDX (Bit 0)                                      */
#define IOM0_CQCURIDX_CQCURIDX_Msk        (0xffUL)                  /*!< CQCURIDX (Bitfield-Mask: 0xff)                        */
/* =======================================================  CQENDIDX  ======================================================== */
#define IOM0_CQENDIDX_CQENDIDX_Pos        (0UL)                     /*!< CQENDIDX (Bit 0)                                      */
#define IOM0_CQENDIDX_CQENDIDX_Msk        (0xffUL)                  /*!< CQENDIDX (Bitfield-Mask: 0xff)                        */
/* ========================================================  STATUS  ========================================================= */
#define IOM0_STATUS_IDLEST_Pos            (2UL)                     /*!< IDLEST (Bit 2)                                        */
#define IOM0_STATUS_IDLEST_Msk            (0x4UL)                   /*!< IDLEST (Bitfield-Mask: 0x01)                          */
#define IOM0_STATUS_CMDACT_Pos            (1UL)                     /*!< CMDACT (Bit 1)                                        */
#define IOM0_STATUS_CMDACT_Msk            (0x2UL)                   /*!< CMDACT (Bitfield-Mask: 0x01)                          */
#define IOM0_STATUS_ERR_Pos               (0UL)                     /*!< ERR (Bit 0)                                           */
#define IOM0_STATUS_ERR_Msk               (0x1UL)                   /*!< ERR (Bitfield-Mask: 0x01)                             */
/* ========================================================  MSPICFG  ======================================================== */
#define IOM0_MSPICFG_MSPIRST_Pos          (30UL)                    /*!< MSPIRST (Bit 30)                                      */
#define IOM0_MSPICFG_MSPIRST_Msk          (0x40000000UL)            /*!< MSPIRST (Bitfield-Mask: 0x01)                         */
#define IOM0_MSPICFG_DOUTDLY_Pos          (27UL)                    /*!< DOUTDLY (Bit 27)                                      */
#define IOM0_MSPICFG_DOUTDLY_Msk          (0x38000000UL)            /*!< DOUTDLY (Bitfield-Mask: 0x07)                         */
#define IOM0_MSPICFG_DINDLY_Pos           (24UL)                    /*!< DINDLY (Bit 24)                                       */
#define IOM0_MSPICFG_DINDLY_Msk           (0x7000000UL)             /*!< DINDLY (Bitfield-Mask: 0x07)                          */
#define IOM0_MSPICFG_SPILSB_Pos           (23UL)                    /*!< SPILSB (Bit 23)                                       */
#define IOM0_MSPICFG_SPILSB_Msk           (0x800000UL)              /*!< SPILSB (Bitfield-Mask: 0x01)                          */
#define IOM0_MSPICFG_RDFCPOL_Pos          (22UL)                    /*!< RDFCPOL (Bit 22)                                      */
#define IOM0_MSPICFG_RDFCPOL_Msk          (0x400000UL)              /*!< RDFCPOL (Bitfield-Mask: 0x01)                         */
#define IOM0_MSPICFG_WTFCPOL_Pos          (21UL)                    /*!< WTFCPOL (Bit 21)                                      */
#define IOM0_MSPICFG_WTFCPOL_Msk          (0x200000UL)              /*!< WTFCPOL (Bitfield-Mask: 0x01)                         */
#define IOM0_MSPICFG_WTFCIRQ_Pos          (20UL)                    /*!< WTFCIRQ (Bit 20)                                      */
#define IOM0_MSPICFG_WTFCIRQ_Msk          (0x100000UL)              /*!< WTFCIRQ (Bitfield-Mask: 0x01)                         */
#define IOM0_MSPICFG_MOSIINV_Pos          (18UL)                    /*!< MOSIINV (Bit 18)                                      */
#define IOM0_MSPICFG_MOSIINV_Msk          (0x40000UL)               /*!< MOSIINV (Bitfield-Mask: 0x01)                         */
#define IOM0_MSPICFG_RDFC_Pos             (17UL)                    /*!< RDFC (Bit 17)                                         */
#define IOM0_MSPICFG_RDFC_Msk             (0x20000UL)               /*!< RDFC (Bitfield-Mask: 0x01)                            */
#define IOM0_MSPICFG_WTFC_Pos             (16UL)                    /*!< WTFC (Bit 16)                                         */
#define IOM0_MSPICFG_WTFC_Msk             (0x10000UL)               /*!< WTFC (Bitfield-Mask: 0x01)                            */
#define IOM0_MSPICFG_FULLDUP_Pos          (2UL)                     /*!< FULLDUP (Bit 2)                                       */
#define IOM0_MSPICFG_FULLDUP_Msk          (0x4UL)                   /*!< FULLDUP (Bitfield-Mask: 0x01)                         */
#define IOM0_MSPICFG_SPHA_Pos             (1UL)                     /*!< SPHA (Bit 1)                                          */
#define IOM0_MSPICFG_SPHA_Msk             (0x2UL)                   /*!< SPHA (Bitfield-Mask: 0x01)                            */
#define IOM0_MSPICFG_SPOL_Pos             (0UL)                     /*!< SPOL (Bit 0)                                          */
#define IOM0_MSPICFG_SPOL_Msk             (0x1UL)                   /*!< SPOL (Bitfield-Mask: 0x01)                            */
/* ========================================================  MI2CCFG  ======================================================== */
#define IOM0_MI2CCFG_STRDIS_Pos           (24UL)                    /*!< STRDIS (Bit 24)                                       */
#define IOM0_MI2CCFG_STRDIS_Msk           (0x1000000UL)             /*!< STRDIS (Bitfield-Mask: 0x01)                          */
#define IOM0_MI2CCFG_SMPCNT_Pos           (16UL)                    /*!< SMPCNT (Bit 16)                                       */
#define IOM0_MI2CCFG_SMPCNT_Msk           (0xff0000UL)              /*!< SMPCNT (Bitfield-Mask: 0xff)                          */
#define IOM0_MI2CCFG_SDAENDLY_Pos         (12UL)                    /*!< SDAENDLY (Bit 12)                                     */
#define IOM0_MI2CCFG_SDAENDLY_Msk         (0xf000UL)                /*!< SDAENDLY (Bitfield-Mask: 0x0f)                        */
#define IOM0_MI2CCFG_SCLENDLY_Pos         (8UL)                     /*!< SCLENDLY (Bit 8)                                      */
#define IOM0_MI2CCFG_SCLENDLY_Msk         (0xf00UL)                 /*!< SCLENDLY (Bitfield-Mask: 0x0f)                        */
#define IOM0_MI2CCFG_MI2CRST_Pos          (6UL)                     /*!< MI2CRST (Bit 6)                                       */
#define IOM0_MI2CCFG_MI2CRST_Msk          (0x40UL)                  /*!< MI2CRST (Bitfield-Mask: 0x01)                         */
#define IOM0_MI2CCFG_SDADLY_Pos           (4UL)                     /*!< SDADLY (Bit 4)                                        */
#define IOM0_MI2CCFG_SDADLY_Msk           (0x30UL)                  /*!< SDADLY (Bitfield-Mask: 0x03)                          */
#define IOM0_MI2CCFG_ARBEN_Pos            (2UL)                     /*!< ARBEN (Bit 2)                                         */
#define IOM0_MI2CCFG_ARBEN_Msk            (0x4UL)                   /*!< ARBEN (Bitfield-Mask: 0x01)                           */
#define IOM0_MI2CCFG_I2CLSB_Pos           (1UL)                     /*!< I2CLSB (Bit 1)                                        */
#define IOM0_MI2CCFG_I2CLSB_Msk           (0x2UL)                   /*!< I2CLSB (Bitfield-Mask: 0x01)                          */
#define IOM0_MI2CCFG_ADDRSZ_Pos           (0UL)                     /*!< ADDRSZ (Bit 0)                                        */
#define IOM0_MI2CCFG_ADDRSZ_Msk           (0x1UL)                   /*!< ADDRSZ (Bitfield-Mask: 0x01)                          */
/* ========================================================  DEVCFG  ========================================================= */
#define IOM0_DEVCFG_DEVADDR_Pos           (0UL)                     /*!< DEVADDR (Bit 0)                                       */
#define IOM0_DEVCFG_DEVADDR_Msk           (0x3ffUL)                 /*!< DEVADDR (Bitfield-Mask: 0x3ff)                        */
/* ========================================================  IOMDBG  ========================================================= */
#define IOM0_IOMDBG_DBGDATA_Pos           (3UL)                     /*!< DBGDATA (Bit 3)                                       */
#define IOM0_IOMDBG_DBGDATA_Msk           (0xfffffff8UL)            /*!< DBGDATA (Bitfield-Mask: 0x1fffffff)                   */
#define IOM0_IOMDBG_APBCLKON_Pos          (2UL)                     /*!< APBCLKON (Bit 2)                                      */
#define IOM0_IOMDBG_APBCLKON_Msk          (0x4UL)                   /*!< APBCLKON (Bitfield-Mask: 0x01)                        */
#define IOM0_IOMDBG_IOCLKON_Pos           (1UL)                     /*!< IOCLKON (Bit 1)                                       */
#define IOM0_IOMDBG_IOCLKON_Msk           (0x2UL)                   /*!< IOCLKON (Bitfield-Mask: 0x01)                         */
#define IOM0_IOMDBG_DBGEN_Pos             (0UL)                     /*!< DBGEN (Bit 0)                                         */
#define IOM0_IOMDBG_DBGEN_Msk             (0x1UL)                   /*!< DBGEN (Bitfield-Mask: 0x01)                           */


/* =========================================================================================================================== */
/* ================                                          IOSLAVE                                          ================ */
/* =========================================================================================================================== */

/* ========================================================  FIFOPTR  ======================================================== */
#define IOSLAVE_FIFOPTR_FIFOSIZ_Pos       (8UL)                     /*!< FIFOSIZ (Bit 8)                                       */
#define IOSLAVE_FIFOPTR_FIFOSIZ_Msk       (0xff00UL)                /*!< FIFOSIZ (Bitfield-Mask: 0xff)                         */
#define IOSLAVE_FIFOPTR_FIFOPTR_Pos       (0UL)                     /*!< FIFOPTR (Bit 0)                                       */
#define IOSLAVE_FIFOPTR_FIFOPTR_Msk       (0xffUL)                  /*!< FIFOPTR (Bitfield-Mask: 0xff)                         */
/* ========================================================  FIFOCFG  ======================================================== */
#define IOSLAVE_FIFOCFG_ROBASE_Pos        (24UL)                    /*!< ROBASE (Bit 24)                                       */
#define IOSLAVE_FIFOCFG_ROBASE_Msk        (0x3f000000UL)            /*!< ROBASE (Bitfield-Mask: 0x3f)                          */
#define IOSLAVE_FIFOCFG_FIFOMAX_Pos       (8UL)                     /*!< FIFOMAX (Bit 8)                                       */
#define IOSLAVE_FIFOCFG_FIFOMAX_Msk       (0x3f00UL)                /*!< FIFOMAX (Bitfield-Mask: 0x3f)                         */
#define IOSLAVE_FIFOCFG_FIFOBASE_Pos      (0UL)                     /*!< FIFOBASE (Bit 0)                                      */
#define IOSLAVE_FIFOCFG_FIFOBASE_Msk      (0x1fUL)                  /*!< FIFOBASE (Bitfield-Mask: 0x1f)                        */
/* ========================================================  FIFOTHR  ======================================================== */
#define IOSLAVE_FIFOTHR_FIFOTHR_Pos       (0UL)                     /*!< FIFOTHR (Bit 0)                                       */
#define IOSLAVE_FIFOTHR_FIFOTHR_Msk       (0xffUL)                  /*!< FIFOTHR (Bitfield-Mask: 0xff)                         */
/* =========================================================  FUPD  ========================================================== */
#define IOSLAVE_FUPD_IOREAD_Pos           (1UL)                     /*!< IOREAD (Bit 1)                                        */
#define IOSLAVE_FUPD_IOREAD_Msk           (0x2UL)                   /*!< IOREAD (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_FUPD_FIFOUPD_Pos          (0UL)                     /*!< FIFOUPD (Bit 0)                                       */
#define IOSLAVE_FUPD_FIFOUPD_Msk          (0x1UL)                   /*!< FIFOUPD (Bitfield-Mask: 0x01)                         */
/* ========================================================  FIFOCTR  ======================================================== */
#define IOSLAVE_FIFOCTR_FIFOCTR_Pos       (0UL)                     /*!< FIFOCTR (Bit 0)                                       */
#define IOSLAVE_FIFOCTR_FIFOCTR_Msk       (0x3ffUL)                 /*!< FIFOCTR (Bitfield-Mask: 0x3ff)                        */
/* ========================================================  FIFOINC  ======================================================== */
#define IOSLAVE_FIFOINC_FIFOINC_Pos       (0UL)                     /*!< FIFOINC (Bit 0)                                       */
#define IOSLAVE_FIFOINC_FIFOINC_Msk       (0x3ffUL)                 /*!< FIFOINC (Bitfield-Mask: 0x3ff)                        */
/* ==========================================================  CFG  ========================================================== */
#define IOSLAVE_CFG_IFCEN_Pos             (31UL)                    /*!< IFCEN (Bit 31)                                        */
#define IOSLAVE_CFG_IFCEN_Msk             (0x80000000UL)            /*!< IFCEN (Bitfield-Mask: 0x01)                           */
#define IOSLAVE_CFG_WRAPPTR_Pos           (20UL)                    /*!< WRAPPTR (Bit 20)                                      */
#define IOSLAVE_CFG_WRAPPTR_Msk           (0x100000UL)              /*!< WRAPPTR (Bitfield-Mask: 0x01)                         */
#define IOSLAVE_CFG_I2CADDR_Pos           (8UL)                     /*!< I2CADDR (Bit 8)                                       */
#define IOSLAVE_CFG_I2CADDR_Msk           (0xfff00UL)               /*!< I2CADDR (Bitfield-Mask: 0xfff)                        */
#define IOSLAVE_CFG_STARTRD_Pos           (4UL)                     /*!< STARTRD (Bit 4)                                       */
#define IOSLAVE_CFG_STARTRD_Msk           (0x10UL)                  /*!< STARTRD (Bitfield-Mask: 0x01)                         */
#define IOSLAVE_CFG_LSB_Pos               (2UL)                     /*!< LSB (Bit 2)                                           */
#define IOSLAVE_CFG_LSB_Msk               (0x4UL)                   /*!< LSB (Bitfield-Mask: 0x01)                             */
#define IOSLAVE_CFG_SPOL_Pos              (1UL)                     /*!< SPOL (Bit 1)                                          */
#define IOSLAVE_CFG_SPOL_Msk              (0x2UL)                   /*!< SPOL (Bitfield-Mask: 0x01)                            */
#define IOSLAVE_CFG_IFCSEL_Pos            (0UL)                     /*!< IFCSEL (Bit 0)                                        */
#define IOSLAVE_CFG_IFCSEL_Msk            (0x1UL)                   /*!< IFCSEL (Bitfield-Mask: 0x01)                          */
/* =========================================================  PRENC  ========================================================= */
#define IOSLAVE_PRENC_PRENC_Pos           (0UL)                     /*!< PRENC (Bit 0)                                         */
#define IOSLAVE_PRENC_PRENC_Msk           (0x1fUL)                  /*!< PRENC (Bitfield-Mask: 0x1f)                           */
/* =======================================================  IOINTCTL  ======================================================== */
#define IOSLAVE_IOINTCTL_IOINTSET_Pos     (24UL)                    /*!< IOINTSET (Bit 24)                                     */
#define IOSLAVE_IOINTCTL_IOINTSET_Msk     (0xff000000UL)            /*!< IOINTSET (Bitfield-Mask: 0xff)                        */
#define IOSLAVE_IOINTCTL_IOINTCLR_Pos     (16UL)                    /*!< IOINTCLR (Bit 16)                                     */
#define IOSLAVE_IOINTCTL_IOINTCLR_Msk     (0x10000UL)               /*!< IOINTCLR (Bitfield-Mask: 0x01)                        */
#define IOSLAVE_IOINTCTL_IOINT_Pos        (8UL)                     /*!< IOINT (Bit 8)                                         */
#define IOSLAVE_IOINTCTL_IOINT_Msk        (0xff00UL)                /*!< IOINT (Bitfield-Mask: 0xff)                           */
#define IOSLAVE_IOINTCTL_IOINTEN_Pos      (0UL)                     /*!< IOINTEN (Bit 0)                                       */
#define IOSLAVE_IOINTCTL_IOINTEN_Msk      (0xffUL)                  /*!< IOINTEN (Bitfield-Mask: 0xff)                         */
/* ========================================================  GENADD  ========================================================= */
#define IOSLAVE_GENADD_GADATA_Pos         (0UL)                     /*!< GADATA (Bit 0)                                        */
#define IOSLAVE_GENADD_GADATA_Msk         (0xffUL)                  /*!< GADATA (Bitfield-Mask: 0xff)                          */
/* ========================================================  ADDPTR  ========================================================= */
#define IOSLAVE_ADDPTR_ADDPTR_Pos         (0UL)                     /*!< ADDPTR (Bit 0)                                        */
#define IOSLAVE_ADDPTR_ADDPTR_Msk         (0xffUL)                  /*!< ADDPTR (Bitfield-Mask: 0xff)                          */
/* =========================================================  INTEN  ========================================================= */
#define IOSLAVE_INTEN_XCMPWR_Pos          (9UL)                     /*!< XCMPWR (Bit 9)                                        */
#define IOSLAVE_INTEN_XCMPWR_Msk          (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTEN_XCMPWF_Pos          (8UL)                     /*!< XCMPWF (Bit 8)                                        */
#define IOSLAVE_INTEN_XCMPWF_Msk          (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTEN_XCMPRR_Pos          (7UL)                     /*!< XCMPRR (Bit 7)                                        */
#define IOSLAVE_INTEN_XCMPRR_Msk          (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTEN_XCMPRF_Pos          (6UL)                     /*!< XCMPRF (Bit 6)                                        */
#define IOSLAVE_INTEN_XCMPRF_Msk          (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTEN_IOINTW_Pos          (5UL)                     /*!< IOINTW (Bit 5)                                        */
#define IOSLAVE_INTEN_IOINTW_Msk          (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTEN_GENAD_Pos           (4UL)                     /*!< GENAD (Bit 4)                                         */
#define IOSLAVE_INTEN_GENAD_Msk           (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
#define IOSLAVE_INTEN_FRDERR_Pos          (3UL)                     /*!< FRDERR (Bit 3)                                        */
#define IOSLAVE_INTEN_FRDERR_Msk          (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTEN_FUNDFL_Pos          (2UL)                     /*!< FUNDFL (Bit 2)                                        */
#define IOSLAVE_INTEN_FUNDFL_Msk          (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTEN_FOVFL_Pos           (1UL)                     /*!< FOVFL (Bit 1)                                         */
#define IOSLAVE_INTEN_FOVFL_Msk           (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
#define IOSLAVE_INTEN_FSIZE_Pos           (0UL)                     /*!< FSIZE (Bit 0)                                         */
#define IOSLAVE_INTEN_FSIZE_Msk           (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
/* ========================================================  INTSTAT  ======================================================== */
#define IOSLAVE_INTSTAT_XCMPWR_Pos        (9UL)                     /*!< XCMPWR (Bit 9)                                        */
#define IOSLAVE_INTSTAT_XCMPWR_Msk        (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTSTAT_XCMPWF_Pos        (8UL)                     /*!< XCMPWF (Bit 8)                                        */
#define IOSLAVE_INTSTAT_XCMPWF_Msk        (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTSTAT_XCMPRR_Pos        (7UL)                     /*!< XCMPRR (Bit 7)                                        */
#define IOSLAVE_INTSTAT_XCMPRR_Msk        (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTSTAT_XCMPRF_Pos        (6UL)                     /*!< XCMPRF (Bit 6)                                        */
#define IOSLAVE_INTSTAT_XCMPRF_Msk        (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTSTAT_IOINTW_Pos        (5UL)                     /*!< IOINTW (Bit 5)                                        */
#define IOSLAVE_INTSTAT_IOINTW_Msk        (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTSTAT_GENAD_Pos         (4UL)                     /*!< GENAD (Bit 4)                                         */
#define IOSLAVE_INTSTAT_GENAD_Msk         (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
#define IOSLAVE_INTSTAT_FRDERR_Pos        (3UL)                     /*!< FRDERR (Bit 3)                                        */
#define IOSLAVE_INTSTAT_FRDERR_Msk        (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTSTAT_FUNDFL_Pos        (2UL)                     /*!< FUNDFL (Bit 2)                                        */
#define IOSLAVE_INTSTAT_FUNDFL_Msk        (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTSTAT_FOVFL_Pos         (1UL)                     /*!< FOVFL (Bit 1)                                         */
#define IOSLAVE_INTSTAT_FOVFL_Msk         (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
#define IOSLAVE_INTSTAT_FSIZE_Pos         (0UL)                     /*!< FSIZE (Bit 0)                                         */
#define IOSLAVE_INTSTAT_FSIZE_Msk         (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
/* ========================================================  INTCLR  ========================================================= */
#define IOSLAVE_INTCLR_XCMPWR_Pos         (9UL)                     /*!< XCMPWR (Bit 9)                                        */
#define IOSLAVE_INTCLR_XCMPWR_Msk         (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTCLR_XCMPWF_Pos         (8UL)                     /*!< XCMPWF (Bit 8)                                        */
#define IOSLAVE_INTCLR_XCMPWF_Msk         (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTCLR_XCMPRR_Pos         (7UL)                     /*!< XCMPRR (Bit 7)                                        */
#define IOSLAVE_INTCLR_XCMPRR_Msk         (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTCLR_XCMPRF_Pos         (6UL)                     /*!< XCMPRF (Bit 6)                                        */
#define IOSLAVE_INTCLR_XCMPRF_Msk         (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTCLR_IOINTW_Pos         (5UL)                     /*!< IOINTW (Bit 5)                                        */
#define IOSLAVE_INTCLR_IOINTW_Msk         (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTCLR_GENAD_Pos          (4UL)                     /*!< GENAD (Bit 4)                                         */
#define IOSLAVE_INTCLR_GENAD_Msk          (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
#define IOSLAVE_INTCLR_FRDERR_Pos         (3UL)                     /*!< FRDERR (Bit 3)                                        */
#define IOSLAVE_INTCLR_FRDERR_Msk         (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTCLR_FUNDFL_Pos         (2UL)                     /*!< FUNDFL (Bit 2)                                        */
#define IOSLAVE_INTCLR_FUNDFL_Msk         (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTCLR_FOVFL_Pos          (1UL)                     /*!< FOVFL (Bit 1)                                         */
#define IOSLAVE_INTCLR_FOVFL_Msk          (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
#define IOSLAVE_INTCLR_FSIZE_Pos          (0UL)                     /*!< FSIZE (Bit 0)                                         */
#define IOSLAVE_INTCLR_FSIZE_Msk          (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
/* ========================================================  INTSET  ========================================================= */
#define IOSLAVE_INTSET_XCMPWR_Pos         (9UL)                     /*!< XCMPWR (Bit 9)                                        */
#define IOSLAVE_INTSET_XCMPWR_Msk         (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTSET_XCMPWF_Pos         (8UL)                     /*!< XCMPWF (Bit 8)                                        */
#define IOSLAVE_INTSET_XCMPWF_Msk         (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTSET_XCMPRR_Pos         (7UL)                     /*!< XCMPRR (Bit 7)                                        */
#define IOSLAVE_INTSET_XCMPRR_Msk         (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTSET_XCMPRF_Pos         (6UL)                     /*!< XCMPRF (Bit 6)                                        */
#define IOSLAVE_INTSET_XCMPRF_Msk         (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTSET_IOINTW_Pos         (5UL)                     /*!< IOINTW (Bit 5)                                        */
#define IOSLAVE_INTSET_IOINTW_Msk         (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTSET_GENAD_Pos          (4UL)                     /*!< GENAD (Bit 4)                                         */
#define IOSLAVE_INTSET_GENAD_Msk          (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
#define IOSLAVE_INTSET_FRDERR_Pos         (3UL)                     /*!< FRDERR (Bit 3)                                        */
#define IOSLAVE_INTSET_FRDERR_Msk         (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTSET_FUNDFL_Pos         (2UL)                     /*!< FUNDFL (Bit 2)                                        */
#define IOSLAVE_INTSET_FUNDFL_Msk         (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
#define IOSLAVE_INTSET_FOVFL_Pos          (1UL)                     /*!< FOVFL (Bit 1)                                         */
#define IOSLAVE_INTSET_FOVFL_Msk          (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
#define IOSLAVE_INTSET_FSIZE_Pos          (0UL)                     /*!< FSIZE (Bit 0)                                         */
#define IOSLAVE_INTSET_FSIZE_Msk          (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
/* ======================================================  REGACCINTEN  ====================================================== */
#define IOSLAVE_REGACCINTEN_REGACC_Pos    (0UL)                     /*!< REGACC (Bit 0)                                        */
#define IOSLAVE_REGACCINTEN_REGACC_Msk    (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
/* =====================================================  REGACCINTSTAT  ===================================================== */
#define IOSLAVE_REGACCINTSTAT_REGACC_Pos  (0UL)                     /*!< REGACC (Bit 0)                                        */
#define IOSLAVE_REGACCINTSTAT_REGACC_Msk  (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
/* =====================================================  REGACCINTCLR  ====================================================== */
#define IOSLAVE_REGACCINTCLR_REGACC_Pos   (0UL)                     /*!< REGACC (Bit 0)                                        */
#define IOSLAVE_REGACCINTCLR_REGACC_Msk   (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
/* =====================================================  REGACCINTSET  ====================================================== */
#define IOSLAVE_REGACCINTSET_REGACC_Pos   (0UL)                     /*!< REGACC (Bit 0)                                        */
#define IOSLAVE_REGACCINTSET_REGACC_Msk   (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */


/* =========================================================================================================================== */
/* ================                                          MCUCTRL                                          ================ */
/* =========================================================================================================================== */

/* ========================================================  CHIPPN  ========================================================= */
#define MCUCTRL_CHIPPN_PN_Pos             (24UL)                    /*!< PN (Bit 24)                                           */
#define MCUCTRL_CHIPPN_PN_Msk             (0xff000000UL)            /*!< PN (Bitfield-Mask: 0xff)                              */
#define MCUCTRL_CHIPPN_MRAMSIZE_Pos       (20UL)                    /*!< MRAMSIZE (Bit 20)                                     */
#define MCUCTRL_CHIPPN_MRAMSIZE_Msk       (0xf00000UL)              /*!< MRAMSIZE (Bitfield-Mask: 0x0f)                        */
#define MCUCTRL_CHIPPN_SRAMSIZE_Pos       (16UL)                    /*!< SRAMSIZE (Bit 16)                                     */
#define MCUCTRL_CHIPPN_SRAMSIZE_Msk       (0xf0000UL)               /*!< SRAMSIZE (Bitfield-Mask: 0x0f)                        */
#define MCUCTRL_CHIPPN_REVMAJ_Pos         (12UL)                    /*!< REVMAJ (Bit 12)                                       */
#define MCUCTRL_CHIPPN_REVMAJ_Msk         (0xf000UL)                /*!< REVMAJ (Bitfield-Mask: 0x0f)                          */
#define MCUCTRL_CHIPPN_REVMIN_Pos         (8UL)                     /*!< REVMIN (Bit 8)                                        */
#define MCUCTRL_CHIPPN_REVMIN_Msk         (0xf00UL)                 /*!< REVMIN (Bitfield-Mask: 0x0f)                          */
#define MCUCTRL_CHIPPN_PKG_Pos            (6UL)                     /*!< PKG (Bit 6)                                           */
#define MCUCTRL_CHIPPN_PKG_Msk            (0xc0UL)                  /*!< PKG (Bitfield-Mask: 0x03)                             */
#define MCUCTRL_CHIPPN_PINS_Pos           (3UL)                     /*!< PINS (Bit 3)                                          */
#define MCUCTRL_CHIPPN_PINS_Msk           (0x38UL)                  /*!< PINS (Bitfield-Mask: 0x07)                            */
#define MCUCTRL_CHIPPN_TEMP_Pos           (1UL)                     /*!< TEMP (Bit 1)                                          */
#define MCUCTRL_CHIPPN_TEMP_Msk           (0x6UL)                   /*!< TEMP (Bitfield-Mask: 0x03)                            */
/* ========================================================  CHIPID0  ======================================================== */
#define MCUCTRL_CHIPID0_CHIPID0_Pos       (0UL)                     /*!< CHIPID0 (Bit 0)                                       */
#define MCUCTRL_CHIPID0_CHIPID0_Msk       (0xffffffffUL)            /*!< CHIPID0 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  CHIPID1  ======================================================== */
#define MCUCTRL_CHIPID1_CHIPID1_Pos       (0UL)                     /*!< CHIPID1 (Bit 0)                                       */
#define MCUCTRL_CHIPID1_CHIPID1_Msk       (0xffffffffUL)            /*!< CHIPID1 (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  CHIPREV  ======================================================== */
#define MCUCTRL_CHIPREV_SIPART_Pos        (8UL)                     /*!< SIPART (Bit 8)                                        */
#define MCUCTRL_CHIPREV_SIPART_Msk        (0xfff00UL)               /*!< SIPART (Bitfield-Mask: 0xfff)                         */
#define MCUCTRL_CHIPREV_REVMAJ_Pos        (4UL)                     /*!< REVMAJ (Bit 4)                                        */
#define MCUCTRL_CHIPREV_REVMAJ_Msk        (0xf0UL)                  /*!< REVMAJ (Bitfield-Mask: 0x0f)                          */
#define MCUCTRL_CHIPREV_REVMIN_Pos        (0UL)                     /*!< REVMIN (Bit 0)                                        */
#define MCUCTRL_CHIPREV_REVMIN_Msk        (0xfUL)                   /*!< REVMIN (Bitfield-Mask: 0x0f)                          */
/* =======================================================  VENDORID  ======================================================== */
#define MCUCTRL_VENDORID_VENDORID_Pos     (0UL)                     /*!< VENDORID (Bit 0)                                      */
#define MCUCTRL_VENDORID_VENDORID_Msk     (0xffffffffUL)            /*!< VENDORID (Bitfield-Mask: 0xffffffff)                  */
/* ==========================================================  SKU  ========================================================== */
#define MCUCTRL_SKU_SKUSECURESPOT_Pos     (10UL)                    /*!< SKUSECURESPOT (Bit 10)                                */
#define MCUCTRL_SKU_SKUSECURESPOT_Msk     (0x400UL)                 /*!< SKUSECURESPOT (Bitfield-Mask: 0x01)                   */
#define MCUCTRL_SKU_SKUUSB_Pos            (9UL)                     /*!< SKUUSB (Bit 9)                                        */
#define MCUCTRL_SKU_SKUUSB_Msk            (0x200UL)                 /*!< SKUUSB (Bitfield-Mask: 0x01)                          */
#define MCUCTRL_SKU_SKUGFX_Pos            (8UL)                     /*!< SKUGFX (Bit 8)                                        */
#define MCUCTRL_SKU_SKUGFX_Msk            (0x100UL)                 /*!< SKUGFX (Bitfield-Mask: 0x01)                          */
#define MCUCTRL_SKU_SKUMIPIDSI_Pos        (7UL)                     /*!< SKUMIPIDSI (Bit 7)                                    */
#define MCUCTRL_SKU_SKUMIPIDSI_Msk        (0x80UL)                  /*!< SKUMIPIDSI (Bitfield-Mask: 0x01)                      */
#define MCUCTRL_SKU_SKUTURBOSPOT_Pos      (6UL)                     /*!< SKUTURBOSPOT (Bit 6)                                  */
#define MCUCTRL_SKU_SKUTURBOSPOT_Msk      (0x40UL)                  /*!< SKUTURBOSPOT (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_SKU_SKUDSP_Pos            (4UL)                     /*!< SKUDSP (Bit 4)                                        */
#define MCUCTRL_SKU_SKUDSP_Msk            (0x30UL)                  /*!< SKUDSP (Bitfield-Mask: 0x03)                          */
#define MCUCTRL_SKU_SKUMRAMSIZE_Pos       (2UL)                     /*!< SKUMRAMSIZE (Bit 2)                                   */
#define MCUCTRL_SKU_SKUMRAMSIZE_Msk       (0xcUL)                   /*!< SKUMRAMSIZE (Bitfield-Mask: 0x03)                     */
#define MCUCTRL_SKU_SKUSRAMSIZE_Pos       (0UL)                     /*!< SKUSRAMSIZE (Bit 0)                                   */
#define MCUCTRL_SKU_SKUSRAMSIZE_Msk       (0x3UL)                   /*!< SKUSRAMSIZE (Bitfield-Mask: 0x03)                     */
/* =======================================================  DEBUGGER  ======================================================== */
#define MCUCTRL_DEBUGGER_LOCKOUT_Pos      (0UL)                     /*!< LOCKOUT (Bit 0)                                       */
#define MCUCTRL_DEBUGGER_LOCKOUT_Msk      (0xffffffffUL)            /*!< LOCKOUT (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  ACRG  ========================================================== */
#define MCUCTRL_ACRG_ACRGTRIM_Pos         (3UL)                     /*!< ACRGTRIM (Bit 3)                                      */
#define MCUCTRL_ACRG_ACRGTRIM_Msk         (0xf8UL)                  /*!< ACRGTRIM (Bitfield-Mask: 0x1f)                        */
#define MCUCTRL_ACRG_ACRGIBIASSEL_Pos     (2UL)                     /*!< ACRGIBIASSEL (Bit 2)                                  */
#define MCUCTRL_ACRG_ACRGIBIASSEL_Msk     (0x4UL)                   /*!< ACRGIBIASSEL (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_ACRG_ACRGPWD_Pos          (1UL)                     /*!< ACRGPWD (Bit 1)                                       */
#define MCUCTRL_ACRG_ACRGPWD_Msk          (0x2UL)                   /*!< ACRGPWD (Bitfield-Mask: 0x01)                         */
#define MCUCTRL_ACRG_ACRGSWE_Pos          (0UL)                     /*!< ACRGSWE (Bit 0)                                       */
#define MCUCTRL_ACRG_ACRGSWE_Msk          (0x1UL)                   /*!< ACRGSWE (Bitfield-Mask: 0x01)                         */
/* =======================================================  VREFGEN2  ======================================================== */
#define MCUCTRL_VREFGEN2_TVRG2SELVREF_Pos (29UL)                    /*!< TVRG2SELVREF (Bit 29)                                 */
#define MCUCTRL_VREFGEN2_TVRG2SELVREF_Msk (0x20000000UL)            /*!< TVRG2SELVREF (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_VREFGEN2_TVRGSELVREF_Pos  (28UL)                    /*!< TVRGSELVREF (Bit 28)                                  */
#define MCUCTRL_VREFGEN2_TVRGSELVREF_Msk  (0x10000000UL)            /*!< TVRGSELVREF (Bitfield-Mask: 0x01)                     */
#define MCUCTRL_VREFGEN2_TVRG2VREFTRIM_Pos (21UL)                   /*!< TVRG2VREFTRIM (Bit 21)                                */
#define MCUCTRL_VREFGEN2_TVRG2VREFTRIM_Msk (0xfe00000UL)            /*!< TVRG2VREFTRIM (Bitfield-Mask: 0x7f)                   */
#define MCUCTRL_VREFGEN2_TVRG2CURRENTTRIM_Pos (20UL)                /*!< TVRG2CURRENTTRIM (Bit 20)                             */
#define MCUCTRL_VREFGEN2_TVRG2CURRENTTRIM_Msk (0x100000UL)          /*!< TVRG2CURRENTTRIM (Bitfield-Mask: 0x01)                */
#define MCUCTRL_VREFGEN2_TVRG2PWD_Pos     (19UL)                    /*!< TVRG2PWD (Bit 19)                                     */
#define MCUCTRL_VREFGEN2_TVRG2PWD_Msk     (0x80000UL)               /*!< TVRG2PWD (Bitfield-Mask: 0x01)                        */
#define MCUCTRL_VREFGEN2_TVRG2TEMPCOTRIM_Pos (14UL)                 /*!< TVRG2TEMPCOTRIM (Bit 14)                              */
#define MCUCTRL_VREFGEN2_TVRG2TEMPCOTRIM_Msk (0x7c000UL)            /*!< TVRG2TEMPCOTRIM (Bitfield-Mask: 0x1f)                 */
#define MCUCTRL_VREFGEN2_TVRGVREFTRIM_Pos (7UL)                     /*!< TVRGVREFTRIM (Bit 7)                                  */
#define MCUCTRL_VREFGEN2_TVRGVREFTRIM_Msk (0x3f80UL)                /*!< TVRGVREFTRIM (Bitfield-Mask: 0x7f)                    */
#define MCUCTRL_VREFGEN2_TVRGCURRENTTRIM_Pos (6UL)                  /*!< TVRGCURRENTTRIM (Bit 6)                               */
#define MCUCTRL_VREFGEN2_TVRGCURRENTTRIM_Msk (0x40UL)               /*!< TVRGCURRENTTRIM (Bitfield-Mask: 0x01)                 */
#define MCUCTRL_VREFGEN2_TVRGPWD_Pos      (5UL)                     /*!< TVRGPWD (Bit 5)                                       */
#define MCUCTRL_VREFGEN2_TVRGPWD_Msk      (0x20UL)                  /*!< TVRGPWD (Bitfield-Mask: 0x01)                         */
#define MCUCTRL_VREFGEN2_TVRGTEMPCOTRIM_Pos (0UL)                   /*!< TVRGTEMPCOTRIM (Bit 0)                                */
#define MCUCTRL_VREFGEN2_TVRGTEMPCOTRIM_Msk (0x1fUL)                /*!< TVRGTEMPCOTRIM (Bitfield-Mask: 0x1f)                  */
/* ========================================================  VRCTRL  ========================================================= */
#define MCUCTRL_VRCTRL_SIMOBUCKACTIVE_Pos (19UL)                    /*!< SIMOBUCKACTIVE (Bit 19)                               */
#define MCUCTRL_VRCTRL_SIMOBUCKACTIVE_Msk (0x80000UL)               /*!< SIMOBUCKACTIVE (Bitfield-Mask: 0x01)                  */
#define MCUCTRL_VRCTRL_SIMOBUCKRSTB_Pos   (18UL)                    /*!< SIMOBUCKRSTB (Bit 18)                                 */
#define MCUCTRL_VRCTRL_SIMOBUCKRSTB_Msk   (0x40000UL)               /*!< SIMOBUCKRSTB (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_VRCTRL_SIMOBUCKPDNB_Pos   (17UL)                    /*!< SIMOBUCKPDNB (Bit 17)                                 */
#define MCUCTRL_VRCTRL_SIMOBUCKPDNB_Msk   (0x20000UL)               /*!< SIMOBUCKPDNB (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_VRCTRL_SIMOBUCKOVER_Pos   (16UL)                    /*!< SIMOBUCKOVER (Bit 16)                                 */
#define MCUCTRL_VRCTRL_SIMOBUCKOVER_Msk   (0x10000UL)               /*!< SIMOBUCKOVER (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_VRCTRL_ANALDOACTIVE_Pos   (15UL)                    /*!< ANALDOACTIVE (Bit 15)                                 */
#define MCUCTRL_VRCTRL_ANALDOACTIVE_Msk   (0x8000UL)                /*!< ANALDOACTIVE (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_VRCTRL_ANALDOPDNB_Pos     (14UL)                    /*!< ANALDOPDNB (Bit 14)                                   */
#define MCUCTRL_VRCTRL_ANALDOPDNB_Msk     (0x4000UL)                /*!< ANALDOPDNB (Bitfield-Mask: 0x01)                      */
#define MCUCTRL_VRCTRL_ANALDOOVER_Pos     (13UL)                    /*!< ANALDOOVER (Bit 13)                                   */
#define MCUCTRL_VRCTRL_ANALDOOVER_Msk     (0x2000UL)                /*!< ANALDOOVER (Bitfield-Mask: 0x01)                      */
#define MCUCTRL_VRCTRL_MEMLPLDOACTIVE_Pos (12UL)                    /*!< MEMLPLDOACTIVE (Bit 12)                               */
#define MCUCTRL_VRCTRL_MEMLPLDOACTIVE_Msk (0x1000UL)                /*!< MEMLPLDOACTIVE (Bitfield-Mask: 0x01)                  */
#define MCUCTRL_VRCTRL_MEMLPLDOPDNB_Pos   (11UL)                    /*!< MEMLPLDOPDNB (Bit 11)                                 */
#define MCUCTRL_VRCTRL_MEMLPLDOPDNB_Msk   (0x800UL)                 /*!< MEMLPLDOPDNB (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_VRCTRL_MEMLPLDOOVER_Pos   (10UL)                    /*!< MEMLPLDOOVER (Bit 10)                                 */
#define MCUCTRL_VRCTRL_MEMLPLDOOVER_Msk   (0x400UL)                 /*!< MEMLPLDOOVER (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_VRCTRL_MEMLDOCOLDSTARTEN_Pos (9UL)                  /*!< MEMLDOCOLDSTARTEN (Bit 9)                             */
#define MCUCTRL_VRCTRL_MEMLDOCOLDSTARTEN_Msk (0x200UL)              /*!< MEMLDOCOLDSTARTEN (Bitfield-Mask: 0x01)               */
#define MCUCTRL_VRCTRL_MEMLDOACTIVE_Pos   (8UL)                     /*!< MEMLDOACTIVE (Bit 8)                                  */
#define MCUCTRL_VRCTRL_MEMLDOACTIVE_Msk   (0x100UL)                 /*!< MEMLDOACTIVE (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_VRCTRL_MEMLDOACTIVEEARLY_Pos (7UL)                  /*!< MEMLDOACTIVEEARLY (Bit 7)                             */
#define MCUCTRL_VRCTRL_MEMLDOACTIVEEARLY_Msk (0x80UL)               /*!< MEMLDOACTIVEEARLY (Bitfield-Mask: 0x01)               */
#define MCUCTRL_VRCTRL_MEMLDOPDNB_Pos     (6UL)                     /*!< MEMLDOPDNB (Bit 6)                                    */
#define MCUCTRL_VRCTRL_MEMLDOPDNB_Msk     (0x40UL)                  /*!< MEMLDOPDNB (Bitfield-Mask: 0x01)                      */
#define MCUCTRL_VRCTRL_MEMLDOOVER_Pos     (5UL)                     /*!< MEMLDOOVER (Bit 5)                                    */
#define MCUCTRL_VRCTRL_MEMLDOOVER_Msk     (0x20UL)                  /*!< MEMLDOOVER (Bitfield-Mask: 0x01)                      */
#define MCUCTRL_VRCTRL_CORELDOCOLDSTARTEN_Pos (4UL)                 /*!< CORELDOCOLDSTARTEN (Bit 4)                            */
#define MCUCTRL_VRCTRL_CORELDOCOLDSTARTEN_Msk (0x10UL)              /*!< CORELDOCOLDSTARTEN (Bitfield-Mask: 0x01)              */
#define MCUCTRL_VRCTRL_CORELDOACTIVE_Pos  (3UL)                     /*!< CORELDOACTIVE (Bit 3)                                 */
#define MCUCTRL_VRCTRL_CORELDOACTIVE_Msk  (0x8UL)                   /*!< CORELDOACTIVE (Bitfield-Mask: 0x01)                   */
#define MCUCTRL_VRCTRL_CORELDOACTIVEEARLY_Pos (2UL)                 /*!< CORELDOACTIVEEARLY (Bit 2)                            */
#define MCUCTRL_VRCTRL_CORELDOACTIVEEARLY_Msk (0x4UL)               /*!< CORELDOACTIVEEARLY (Bitfield-Mask: 0x01)              */
#define MCUCTRL_VRCTRL_CORELDOPDNB_Pos    (1UL)                     /*!< CORELDOPDNB (Bit 1)                                   */
#define MCUCTRL_VRCTRL_CORELDOPDNB_Msk    (0x2UL)                   /*!< CORELDOPDNB (Bitfield-Mask: 0x01)                     */
#define MCUCTRL_VRCTRL_CORELDOOVER_Pos    (0UL)                     /*!< CORELDOOVER (Bit 0)                                   */
#define MCUCTRL_VRCTRL_CORELDOOVER_Msk    (0x1UL)                   /*!< CORELDOOVER (Bitfield-Mask: 0x01)                     */
/* ========================================================  LDOREG1  ======================================================== */
#define MCUCTRL_LDOREG1_CORELDOIBIASSEL_Pos (21UL)                  /*!< CORELDOIBIASSEL (Bit 21)                              */
#define MCUCTRL_LDOREG1_CORELDOIBIASSEL_Msk (0x200000UL)            /*!< CORELDOIBIASSEL (Bitfield-Mask: 0x01)                 */
#define MCUCTRL_LDOREG1_CORELDOIBIASTRIM_Pos (20UL)                 /*!< CORELDOIBIASTRIM (Bit 20)                             */
#define MCUCTRL_LDOREG1_CORELDOIBIASTRIM_Msk (0x100000UL)           /*!< CORELDOIBIASTRIM (Bitfield-Mask: 0x01)                */
#define MCUCTRL_LDOREG1_CORELDOLPTRIM_Pos (14UL)                    /*!< CORELDOLPTRIM (Bit 14)                                */
#define MCUCTRL_LDOREG1_CORELDOLPTRIM_Msk (0xfc000UL)               /*!< CORELDOLPTRIM (Bitfield-Mask: 0x3f)                   */
#define MCUCTRL_LDOREG1_CORELDOTEMPCOTRIM_Pos (10UL)                /*!< CORELDOTEMPCOTRIM (Bit 10)                            */
#define MCUCTRL_LDOREG1_CORELDOTEMPCOTRIM_Msk (0x3c00UL)            /*!< CORELDOTEMPCOTRIM (Bitfield-Mask: 0x0f)               */
#define MCUCTRL_LDOREG1_CORELDOACTIVETRIM_Pos (0UL)                 /*!< CORELDOACTIVETRIM (Bit 0)                             */
#define MCUCTRL_LDOREG1_CORELDOACTIVETRIM_Msk (0x3ffUL)             /*!< CORELDOACTIVETRIM (Bitfield-Mask: 0x3ff)              */
/* ========================================================  LDOREG2  ======================================================== */
#define MCUCTRL_LDOREG2_TRIMANALDO_Pos    (26UL)                    /*!< TRIMANALDO (Bit 26)                                   */
#define MCUCTRL_LDOREG2_TRIMANALDO_Msk    (0x3c000000UL)            /*!< TRIMANALDO (Bitfield-Mask: 0x0f)                      */
#define MCUCTRL_LDOREG2_MEMLDOIBIASSEL_Pos (25UL)                   /*!< MEMLDOIBIASSEL (Bit 25)                               */
#define MCUCTRL_LDOREG2_MEMLDOIBIASSEL_Msk (0x2000000UL)            /*!< MEMLDOIBIASSEL (Bitfield-Mask: 0x01)                  */
#define MCUCTRL_LDOREG2_MEMLPLDOIBIASTRIM_Pos (24UL)                /*!< MEMLPLDOIBIASTRIM (Bit 24)                            */
#define MCUCTRL_LDOREG2_MEMLPLDOIBIASTRIM_Msk (0x1000000UL)         /*!< MEMLPLDOIBIASTRIM (Bitfield-Mask: 0x01)               */
#define MCUCTRL_LDOREG2_MEMLPLDOTRIM_Pos  (18UL)                    /*!< MEMLPLDOTRIM (Bit 18)                                 */
#define MCUCTRL_LDOREG2_MEMLPLDOTRIM_Msk  (0xfc0000UL)              /*!< MEMLPLDOTRIM (Bitfield-Mask: 0x3f)                    */
#define MCUCTRL_LDOREG2_MEMLDOLPALTTRIM_Pos (12UL)                  /*!< MEMLDOLPALTTRIM (Bit 12)                              */
#define MCUCTRL_LDOREG2_MEMLDOLPALTTRIM_Msk (0x3f000UL)             /*!< MEMLDOLPALTTRIM (Bitfield-Mask: 0x3f)                 */
#define MCUCTRL_LDOREG2_MEMLDOLPTRIM_Pos  (6UL)                     /*!< MEMLDOLPTRIM (Bit 6)                                  */
#define MCUCTRL_LDOREG2_MEMLDOLPTRIM_Msk  (0xfc0UL)                 /*!< MEMLDOLPTRIM (Bitfield-Mask: 0x3f)                    */
#define MCUCTRL_LDOREG2_MEMLDOACTIVETRIM_Pos (0UL)                  /*!< MEMLDOACTIVETRIM (Bit 0)                              */
#define MCUCTRL_LDOREG2_MEMLDOACTIVETRIM_Msk (0x3fUL)               /*!< MEMLDOACTIVETRIM (Bitfield-Mask: 0x3f)                */
/* =========================================================  HFRC2  ========================================================= */
#define MCUCTRL_HFRC2_HF2TUNE_Pos         (11UL)                    /*!< HF2TUNE (Bit 11)                                      */
#define MCUCTRL_HFRC2_HF2TUNE_Msk         (0x3ff800UL)              /*!< HF2TUNE (Bitfield-Mask: 0x7ff)                        */
/* =========================================================  LFRC  ========================================================== */
#define MCUCTRL_LFRC_LFRCSIMOCLKDIV_Pos   (10UL)                    /*!< LFRCSIMOCLKDIV (Bit 10)                               */
#define MCUCTRL_LFRC_LFRCSIMOCLKDIV_Msk   (0x1c00UL)                /*!< LFRCSIMOCLKDIV (Bitfield-Mask: 0x07)                  */
#define MCUCTRL_LFRC_LFRCITAILTRIM_Pos    (8UL)                     /*!< LFRCITAILTRIM (Bit 8)                                 */
#define MCUCTRL_LFRC_LFRCITAILTRIM_Msk    (0x300UL)                 /*!< LFRCITAILTRIM (Bitfield-Mask: 0x03)                   */
#define MCUCTRL_LFRC_RESETLFRC_Pos        (7UL)                     /*!< RESETLFRC (Bit 7)                                     */
#define MCUCTRL_LFRC_RESETLFRC_Msk        (0x80UL)                  /*!< RESETLFRC (Bitfield-Mask: 0x01)                       */
#define MCUCTRL_LFRC_PWDLFRC_Pos          (6UL)                     /*!< PWDLFRC (Bit 6)                                       */
#define MCUCTRL_LFRC_PWDLFRC_Msk          (0x40UL)                  /*!< PWDLFRC (Bitfield-Mask: 0x01)                         */
#define MCUCTRL_LFRC_TRIMTUNELFRC_Pos     (1UL)                     /*!< TRIMTUNELFRC (Bit 1)                                  */
#define MCUCTRL_LFRC_TRIMTUNELFRC_Msk     (0x3eUL)                  /*!< TRIMTUNELFRC (Bitfield-Mask: 0x1f)                    */
#define MCUCTRL_LFRC_LFRCSWE_Pos          (0UL)                     /*!< LFRCSWE (Bit 0)                                       */
#define MCUCTRL_LFRC_LFRCSWE_Msk          (0x1UL)                   /*!< LFRCSWE (Bitfield-Mask: 0x01)                         */
/* ========================================================  BODCTRL  ======================================================== */
#define MCUCTRL_BODCTRL_BODHVREFSEL_Pos   (7UL)                     /*!< BODHVREFSEL (Bit 7)                                   */
#define MCUCTRL_BODCTRL_BODHVREFSEL_Msk   (0x80UL)                  /*!< BODHVREFSEL (Bitfield-Mask: 0x01)                     */
#define MCUCTRL_BODCTRL_BODLVREFSEL_Pos   (6UL)                     /*!< BODLVREFSEL (Bit 6)                                   */
#define MCUCTRL_BODCTRL_BODLVREFSEL_Msk   (0x40UL)                  /*!< BODLVREFSEL (Bitfield-Mask: 0x01)                     */
#define MCUCTRL_BODCTRL_BODCLVPWD_Pos     (5UL)                     /*!< BODCLVPWD (Bit 5)                                     */
#define MCUCTRL_BODCTRL_BODCLVPWD_Msk     (0x20UL)                  /*!< BODCLVPWD (Bitfield-Mask: 0x01)                       */
#define MCUCTRL_BODCTRL_BODSPWD_Pos       (4UL)                     /*!< BODSPWD (Bit 4)                                       */
#define MCUCTRL_BODCTRL_BODSPWD_Msk       (0x10UL)                  /*!< BODSPWD (Bitfield-Mask: 0x01)                         */
#define MCUCTRL_BODCTRL_BODFPWD_Pos       (3UL)                     /*!< BODFPWD (Bit 3)                                       */
#define MCUCTRL_BODCTRL_BODFPWD_Msk       (0x8UL)                   /*!< BODFPWD (Bitfield-Mask: 0x01)                         */
#define MCUCTRL_BODCTRL_BODCPWD_Pos       (2UL)                     /*!< BODCPWD (Bit 2)                                       */
#define MCUCTRL_BODCTRL_BODCPWD_Msk       (0x4UL)                   /*!< BODCPWD (Bitfield-Mask: 0x01)                         */
#define MCUCTRL_BODCTRL_BODHPWD_Pos       (1UL)                     /*!< BODHPWD (Bit 1)                                       */
#define MCUCTRL_BODCTRL_BODHPWD_Msk       (0x2UL)                   /*!< BODHPWD (Bitfield-Mask: 0x01)                         */
#define MCUCTRL_BODCTRL_BODLPWD_Pos       (0UL)                     /*!< BODLPWD (Bit 0)                                       */
#define MCUCTRL_BODCTRL_BODLPWD_Msk       (0x1UL)                   /*!< BODLPWD (Bitfield-Mask: 0x01)                         */
/* =======================================================  ADCPWRDLY  ======================================================= */
#define MCUCTRL_ADCPWRDLY_ADCPWR1_Pos     (8UL)                     /*!< ADCPWR1 (Bit 8)                                       */
#define MCUCTRL_ADCPWRDLY_ADCPWR1_Msk     (0xff00UL)                /*!< ADCPWR1 (Bitfield-Mask: 0xff)                         */
#define MCUCTRL_ADCPWRDLY_ADCPWR0_Pos     (0UL)                     /*!< ADCPWR0 (Bit 0)                                       */
#define MCUCTRL_ADCPWRDLY_ADCPWR0_Msk     (0xffUL)                  /*!< ADCPWR0 (Bitfield-Mask: 0xff)                         */
/* ======================================================  ADCPWRCTRL  ======================================================= */
#define MCUCTRL_ADCPWRCTRL_ADCKEEPOUTEN_Pos (16UL)                  /*!< ADCKEEPOUTEN (Bit 16)                                 */
#define MCUCTRL_ADCPWRCTRL_ADCKEEPOUTEN_Msk (0x10000UL)             /*!< ADCKEEPOUTEN (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_ADCPWRCTRL_ADCRFBUFSLWEN_Pos (15UL)                 /*!< ADCRFBUFSLWEN (Bit 15)                                */
#define MCUCTRL_ADCPWRCTRL_ADCRFBUFSLWEN_Msk (0x8000UL)             /*!< ADCRFBUFSLWEN (Bitfield-Mask: 0x01)                   */
#define MCUCTRL_ADCPWRCTRL_ADCINBUFEN_Pos (14UL)                    /*!< ADCINBUFEN (Bit 14)                                   */
#define MCUCTRL_ADCPWRCTRL_ADCINBUFEN_Msk (0x4000UL)                /*!< ADCINBUFEN (Bitfield-Mask: 0x01)                      */
#define MCUCTRL_ADCPWRCTRL_ADCINBUFSEL_Pos (12UL)                   /*!< ADCINBUFSEL (Bit 12)                                  */
#define MCUCTRL_ADCPWRCTRL_ADCINBUFSEL_Msk (0x3000UL)               /*!< ADCINBUFSEL (Bitfield-Mask: 0x03)                     */
#define MCUCTRL_ADCPWRCTRL_ADCVBATDIVEN_Pos (11UL)                  /*!< ADCVBATDIVEN (Bit 11)                                 */
#define MCUCTRL_ADCPWRCTRL_ADCVBATDIVEN_Msk (0x800UL)               /*!< ADCVBATDIVEN (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_ADCPWRCTRL_VDDADCRESETN_Pos (9UL)                   /*!< VDDADCRESETN (Bit 9)                                  */
#define MCUCTRL_ADCPWRCTRL_VDDADCRESETN_Msk (0x200UL)               /*!< VDDADCRESETN (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE_Pos (8UL)               /*!< VDDADCDIGISOLATE (Bit 8)                              */
#define MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE_Msk (0x100UL)           /*!< VDDADCDIGISOLATE (Bitfield-Mask: 0x01)                */
#define MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE_Pos (7UL)               /*!< VDDADCSARISOLATE (Bit 7)                              */
#define MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE_Msk (0x80UL)            /*!< VDDADCSARISOLATE (Bitfield-Mask: 0x01)                */
#define MCUCTRL_ADCPWRCTRL_REFKEEPPEN_Pos (6UL)                     /*!< REFKEEPPEN (Bit 6)                                    */
#define MCUCTRL_ADCPWRCTRL_REFKEEPPEN_Msk (0x40UL)                  /*!< REFKEEPPEN (Bitfield-Mask: 0x01)                      */
#define MCUCTRL_ADCPWRCTRL_REFBUFPEN_Pos  (5UL)                     /*!< REFBUFPEN (Bit 5)                                     */
#define MCUCTRL_ADCPWRCTRL_REFBUFPEN_Msk  (0x20UL)                  /*!< REFBUFPEN (Bitfield-Mask: 0x01)                       */
#define MCUCTRL_ADCPWRCTRL_BGTLPPEN_Pos   (4UL)                     /*!< BGTLPPEN (Bit 4)                                      */
#define MCUCTRL_ADCPWRCTRL_BGTLPPEN_Msk   (0x10UL)                  /*!< BGTLPPEN (Bitfield-Mask: 0x01)                        */
#define MCUCTRL_ADCPWRCTRL_BGTPEN_Pos     (3UL)                     /*!< BGTPEN (Bit 3)                                        */
#define MCUCTRL_ADCPWRCTRL_BGTPEN_Msk     (0x8UL)                   /*!< BGTPEN (Bitfield-Mask: 0x01)                          */
#define MCUCTRL_ADCPWRCTRL_ADCBPSEN_Pos   (2UL)                     /*!< ADCBPSEN (Bit 2)                                      */
#define MCUCTRL_ADCPWRCTRL_ADCBPSEN_Msk   (0x4UL)                   /*!< ADCBPSEN (Bitfield-Mask: 0x01)                        */
#define MCUCTRL_ADCPWRCTRL_ADCAPSEN_Pos   (1UL)                     /*!< ADCAPSEN (Bit 1)                                      */
#define MCUCTRL_ADCPWRCTRL_ADCAPSEN_Msk   (0x2UL)                   /*!< ADCAPSEN (Bitfield-Mask: 0x01)                        */
#define MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE_Pos (0UL)                  /*!< ADCPWRCTRLSWE (Bit 0)                                 */
#define MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE_Msk (0x1UL)                /*!< ADCPWRCTRLSWE (Bitfield-Mask: 0x01)                   */
/* ========================================================  ADCCAL  ========================================================= */
#define MCUCTRL_ADCCAL_ADCCALIBRATED_Pos  (1UL)                     /*!< ADCCALIBRATED (Bit 1)                                 */
#define MCUCTRL_ADCCAL_ADCCALIBRATED_Msk  (0x2UL)                   /*!< ADCCALIBRATED (Bitfield-Mask: 0x01)                   */
#define MCUCTRL_ADCCAL_CALONPWRUP_Pos     (0UL)                     /*!< CALONPWRUP (Bit 0)                                    */
#define MCUCTRL_ADCCAL_CALONPWRUP_Msk     (0x1UL)                   /*!< CALONPWRUP (Bitfield-Mask: 0x01)                      */
/* ======================================================  ADCBATTLOAD  ====================================================== */
#define MCUCTRL_ADCBATTLOAD_BATTLOAD_Pos  (0UL)                     /*!< BATTLOAD (Bit 0)                                      */
#define MCUCTRL_ADCBATTLOAD_BATTLOAD_Msk  (0x1UL)                   /*!< BATTLOAD (Bitfield-Mask: 0x01)                        */
/* =======================================================  XTALCTRL  ======================================================== */
#define MCUCTRL_XTALCTRL_XTALICOMPTRIM_Pos (7UL)                    /*!< XTALICOMPTRIM (Bit 7)                                 */
#define MCUCTRL_XTALCTRL_XTALICOMPTRIM_Msk (0x180UL)                /*!< XTALICOMPTRIM (Bitfield-Mask: 0x03)                   */
#define MCUCTRL_XTALCTRL_XTALIBUFTRIM_Pos (5UL)                     /*!< XTALIBUFTRIM (Bit 5)                                  */
#define MCUCTRL_XTALCTRL_XTALIBUFTRIM_Msk (0x60UL)                  /*!< XTALIBUFTRIM (Bitfield-Mask: 0x03)                    */
#define MCUCTRL_XTALCTRL_XTALCOMPPDNB_Pos (4UL)                     /*!< XTALCOMPPDNB (Bit 4)                                  */
#define MCUCTRL_XTALCTRL_XTALCOMPPDNB_Msk (0x10UL)                  /*!< XTALCOMPPDNB (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_XTALCTRL_XTALPDNB_Pos     (3UL)                     /*!< XTALPDNB (Bit 3)                                      */
#define MCUCTRL_XTALCTRL_XTALPDNB_Msk     (0x8UL)                   /*!< XTALPDNB (Bitfield-Mask: 0x01)                        */
#define MCUCTRL_XTALCTRL_XTALCOMPBYPASS_Pos (2UL)                   /*!< XTALCOMPBYPASS (Bit 2)                                */
#define MCUCTRL_XTALCTRL_XTALCOMPBYPASS_Msk (0x4UL)                 /*!< XTALCOMPBYPASS (Bitfield-Mask: 0x01)                  */
#define MCUCTRL_XTALCTRL_XTALCOREDISFB_Pos (1UL)                    /*!< XTALCOREDISFB (Bit 1)                                 */
#define MCUCTRL_XTALCTRL_XTALCOREDISFB_Msk (0x2UL)                  /*!< XTALCOREDISFB (Bitfield-Mask: 0x01)                   */
#define MCUCTRL_XTALCTRL_XTALSWE_Pos      (0UL)                     /*!< XTALSWE (Bit 0)                                       */
#define MCUCTRL_XTALCTRL_XTALSWE_Msk      (0x1UL)                   /*!< XTALSWE (Bitfield-Mask: 0x01)                         */
/* ======================================================  XTALGENCTRL  ====================================================== */
#define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Pos (8UL)                /*!< XTALKSBIASTRIM (Bit 8)                                */
#define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Msk (0x3f00UL)           /*!< XTALKSBIASTRIM (Bitfield-Mask: 0x3f)                  */
#define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Pos (2UL)                  /*!< XTALBIASTRIM (Bit 2)                                  */
#define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Msk (0xfcUL)               /*!< XTALBIASTRIM (Bitfield-Mask: 0x3f)                    */
#define MCUCTRL_XTALGENCTRL_ACWARMUP_Pos  (0UL)                     /*!< ACWARMUP (Bit 0)                                      */
#define MCUCTRL_XTALGENCTRL_ACWARMUP_Msk  (0x3UL)                   /*!< ACWARMUP (Bitfield-Mask: 0x03)                        */
/* ======================================================  XTALHSTRIMS  ====================================================== */
#define MCUCTRL_XTALHSTRIMS_XTALHSSPARE_Pos (29UL)                  /*!< XTALHSSPARE (Bit 29)                                  */
#define MCUCTRL_XTALHSTRIMS_XTALHSSPARE_Msk (0x20000000UL)          /*!< XTALHSSPARE (Bitfield-Mask: 0x01)                     */
#define MCUCTRL_XTALHSTRIMS_XTALHSRSTRIM_Pos (28UL)                 /*!< XTALHSRSTRIM (Bit 28)                                 */
#define MCUCTRL_XTALHSTRIMS_XTALHSRSTRIM_Msk (0x10000000UL)         /*!< XTALHSRSTRIM (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_XTALHSTRIMS_XTALHSIBIASTRIM_Pos (21UL)              /*!< XTALHSIBIASTRIM (Bit 21)                              */
#define MCUCTRL_XTALHSTRIMS_XTALHSIBIASTRIM_Msk (0xfe00000UL)       /*!< XTALHSIBIASTRIM (Bitfield-Mask: 0x7f)                 */
#define MCUCTRL_XTALHSTRIMS_XTALHSIBIASCOMPTRIM_Pos (17UL)          /*!< XTALHSIBIASCOMPTRIM (Bit 17)                          */
#define MCUCTRL_XTALHSTRIMS_XTALHSIBIASCOMPTRIM_Msk (0x1e0000UL)    /*!< XTALHSIBIASCOMPTRIM (Bitfield-Mask: 0x0f)             */
#define MCUCTRL_XTALHSTRIMS_XTALHSIBIASCOMP2TRIM_Pos (15UL)         /*!< XTALHSIBIASCOMP2TRIM (Bit 15)                         */
#define MCUCTRL_XTALHSTRIMS_XTALHSIBIASCOMP2TRIM_Msk (0x18000UL)    /*!< XTALHSIBIASCOMP2TRIM (Bitfield-Mask: 0x03)            */
#define MCUCTRL_XTALHSTRIMS_XTALHSDRIVERSTRENGTH_Pos (12UL)         /*!< XTALHSDRIVERSTRENGTH (Bit 12)                         */
#define MCUCTRL_XTALHSTRIMS_XTALHSDRIVERSTRENGTH_Msk (0x7000UL)     /*!< XTALHSDRIVERSTRENGTH (Bitfield-Mask: 0x07)            */
#define MCUCTRL_XTALHSTRIMS_XTALHSDRIVETRIM_Pos (10UL)              /*!< XTALHSDRIVETRIM (Bit 10)                              */
#define MCUCTRL_XTALHSTRIMS_XTALHSDRIVETRIM_Msk (0xc00UL)           /*!< XTALHSDRIVETRIM (Bitfield-Mask: 0x03)                 */
#define MCUCTRL_XTALHSTRIMS_XTALHSCAPTRIM_Pos (6UL)                 /*!< XTALHSCAPTRIM (Bit 6)                                 */
#define MCUCTRL_XTALHSTRIMS_XTALHSCAPTRIM_Msk (0x3c0UL)             /*!< XTALHSCAPTRIM (Bitfield-Mask: 0x0f)                   */
#define MCUCTRL_XTALHSTRIMS_XTALHSCAP2TRIM_Pos (0UL)                /*!< XTALHSCAP2TRIM (Bit 0)                                */
#define MCUCTRL_XTALHSTRIMS_XTALHSCAP2TRIM_Msk (0x3fUL)             /*!< XTALHSCAP2TRIM (Bitfield-Mask: 0x3f)                  */
/* ======================================================  XTALHSCTRL  ======================================================= */
#define MCUCTRL_XTALHSCTRL_XTALHSEXTERNALCLOCK_Pos (8UL)            /*!< XTALHSEXTERNALCLOCK (Bit 8)                           */
#define MCUCTRL_XTALHSCTRL_XTALHSEXTERNALCLOCK_Msk (0x100UL)        /*!< XTALHSEXTERNALCLOCK (Bitfield-Mask: 0x01)             */
#define MCUCTRL_XTALHSCTRL_XTALHSPADOUTEN_Pos (7UL)                 /*!< XTALHSPADOUTEN (Bit 7)                                */
#define MCUCTRL_XTALHSCTRL_XTALHSPADOUTEN_Msk (0x80UL)              /*!< XTALHSPADOUTEN (Bitfield-Mask: 0x01)                  */
#define MCUCTRL_XTALHSCTRL_XTALHSSELRCOM_Pos (6UL)                  /*!< XTALHSSELRCOM (Bit 6)                                 */
#define MCUCTRL_XTALHSCTRL_XTALHSSELRCOM_Msk (0x40UL)               /*!< XTALHSSELRCOM (Bitfield-Mask: 0x01)                   */
#define MCUCTRL_XTALHSCTRL_XTALHSPDNPNIMPROVE_Pos (5UL)             /*!< XTALHSPDNPNIMPROVE (Bit 5)                            */
#define MCUCTRL_XTALHSCTRL_XTALHSPDNPNIMPROVE_Msk (0x20UL)          /*!< XTALHSPDNPNIMPROVE (Bitfield-Mask: 0x01)              */
#define MCUCTRL_XTALHSCTRL_XTALHSINJECTIONENABLE_Pos (4UL)          /*!< XTALHSINJECTIONENABLE (Bit 4)                         */
#define MCUCTRL_XTALHSCTRL_XTALHSINJECTIONENABLE_Msk (0x10UL)       /*!< XTALHSINJECTIONENABLE (Bitfield-Mask: 0x01)           */
#define MCUCTRL_XTALHSCTRL_XTALHSIBSTENABLE_Pos (3UL)               /*!< XTALHSIBSTENABLE (Bit 3)                              */
#define MCUCTRL_XTALHSCTRL_XTALHSIBSTENABLE_Msk (0x8UL)             /*!< XTALHSIBSTENABLE (Bitfield-Mask: 0x01)                */
#define MCUCTRL_XTALHSCTRL_XTALHSCOMPSEL_Pos (2UL)                  /*!< XTALHSCOMPSEL (Bit 2)                                 */
#define MCUCTRL_XTALHSCTRL_XTALHSCOMPSEL_Msk (0x4UL)                /*!< XTALHSCOMPSEL (Bitfield-Mask: 0x01)                   */
#define MCUCTRL_XTALHSCTRL_XTALHSCOMPPDNB_Pos (1UL)                 /*!< XTALHSCOMPPDNB (Bit 1)                                */
#define MCUCTRL_XTALHSCTRL_XTALHSCOMPPDNB_Msk (0x2UL)               /*!< XTALHSCOMPPDNB (Bitfield-Mask: 0x01)                  */
#define MCUCTRL_XTALHSCTRL_XTALHSPDNB_Pos (0UL)                     /*!< XTALHSPDNB (Bit 0)                                    */
#define MCUCTRL_XTALHSCTRL_XTALHSPDNB_Msk (0x1UL)                   /*!< XTALHSPDNB (Bitfield-Mask: 0x01)                      */
/* ======================================================  MRAMPWRCTRL  ====================================================== */
#define MCUCTRL_MRAMPWRCTRL_MRAMPWRCTRL_Pos (2UL)                   /*!< MRAMPWRCTRL (Bit 2)                                   */
#define MCUCTRL_MRAMPWRCTRL_MRAMPWRCTRL_Msk (0x4UL)                 /*!< MRAMPWRCTRL (Bitfield-Mask: 0x01)                     */
#define MCUCTRL_MRAMPWRCTRL_MRAMSLPEN_Pos (1UL)                     /*!< MRAMSLPEN (Bit 1)                                     */
#define MCUCTRL_MRAMPWRCTRL_MRAMSLPEN_Msk (0x2UL)                   /*!< MRAMSLPEN (Bitfield-Mask: 0x01)                       */
#define MCUCTRL_MRAMPWRCTRL_MRAMLPREN_Pos (0UL)                     /*!< MRAMLPREN (Bit 0)                                     */
#define MCUCTRL_MRAMPWRCTRL_MRAMLPREN_Msk (0x1UL)                   /*!< MRAMLPREN (Bitfield-Mask: 0x01)                       */
/* =======================================================  BODISABLE  ======================================================= */
#define MCUCTRL_BODISABLE_BODCLVREN_Pos   (4UL)                     /*!< BODCLVREN (Bit 4)                                     */
#define MCUCTRL_BODISABLE_BODCLVREN_Msk   (0x10UL)                  /*!< BODCLVREN (Bitfield-Mask: 0x01)                       */
#define MCUCTRL_BODISABLE_BODSREN_Pos     (3UL)                     /*!< BODSREN (Bit 3)                                       */
#define MCUCTRL_BODISABLE_BODSREN_Msk     (0x8UL)                   /*!< BODSREN (Bitfield-Mask: 0x01)                         */
#define MCUCTRL_BODISABLE_BODFREN_Pos     (2UL)                     /*!< BODFREN (Bit 2)                                       */
#define MCUCTRL_BODISABLE_BODFREN_Msk     (0x4UL)                   /*!< BODFREN (Bitfield-Mask: 0x01)                         */
#define MCUCTRL_BODISABLE_BODCREN_Pos     (1UL)                     /*!< BODCREN (Bit 1)                                       */
#define MCUCTRL_BODISABLE_BODCREN_Msk     (0x2UL)                   /*!< BODCREN (Bitfield-Mask: 0x01)                         */
#define MCUCTRL_BODISABLE_BODLRDE_Pos     (0UL)                     /*!< BODLRDE (Bit 0)                                       */
#define MCUCTRL_BODISABLE_BODLRDE_Msk     (0x1UL)                   /*!< BODLRDE (Bitfield-Mask: 0x01)                         */
/* ======================================================  BOOTLOADER  ======================================================= */
#define MCUCTRL_BOOTLOADER_SECBOOTONRST_Pos (30UL)                  /*!< SECBOOTONRST (Bit 30)                                 */
#define MCUCTRL_BOOTLOADER_SECBOOTONRST_Msk (0xc0000000UL)          /*!< SECBOOTONRST (Bitfield-Mask: 0x03)                    */
#define MCUCTRL_BOOTLOADER_SECBOOT_Pos    (28UL)                    /*!< SECBOOT (Bit 28)                                      */
#define MCUCTRL_BOOTLOADER_SECBOOT_Msk    (0x30000000UL)            /*!< SECBOOT (Bitfield-Mask: 0x03)                         */
#define MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Pos (26UL)                /*!< SECBOOTFEATURE (Bit 26)                               */
#define MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Msk (0xc000000UL)         /*!< SECBOOTFEATURE (Bitfield-Mask: 0x03)                  */
#define MCUCTRL_BOOTLOADER_SBLLOCK_Pos    (3UL)                     /*!< SBLLOCK (Bit 3)                                       */
#define MCUCTRL_BOOTLOADER_SBLLOCK_Msk    (0x8UL)                   /*!< SBLLOCK (Bitfield-Mask: 0x01)                         */
#define MCUCTRL_BOOTLOADER_PROTLOCK_Pos   (2UL)                     /*!< PROTLOCK (Bit 2)                                      */
#define MCUCTRL_BOOTLOADER_PROTLOCK_Msk   (0x4UL)                   /*!< PROTLOCK (Bitfield-Mask: 0x01)                        */
#define MCUCTRL_BOOTLOADER_SBRLOCK_Pos    (1UL)                     /*!< SBRLOCK (Bit 1)                                       */
#define MCUCTRL_BOOTLOADER_SBRLOCK_Msk    (0x2UL)                   /*!< SBRLOCK (Bitfield-Mask: 0x01)                         */
#define MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Pos (0UL)                  /*!< BOOTLOADERLOW (Bit 0)                                 */
#define MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Msk (0x1UL)                /*!< BOOTLOADERLOW (Bitfield-Mask: 0x01)                   */
/* ======================================================  SHADOWVALID  ====================================================== */
#define MCUCTRL_SHADOWVALID_INFO0VALID_Pos (2UL)                    /*!< INFO0VALID (Bit 2)                                    */
#define MCUCTRL_SHADOWVALID_INFO0VALID_Msk (0x4UL)                  /*!< INFO0VALID (Bitfield-Mask: 0x01)                      */
#define MCUCTRL_SHADOWVALID_BLDSLEEP_Pos  (1UL)                     /*!< BLDSLEEP (Bit 1)                                      */
#define MCUCTRL_SHADOWVALID_BLDSLEEP_Msk  (0x2UL)                   /*!< BLDSLEEP (Bitfield-Mask: 0x01)                        */
#define MCUCTRL_SHADOWVALID_VALID_Pos     (0UL)                     /*!< VALID (Bit 0)                                         */
#define MCUCTRL_SHADOWVALID_VALID_Msk     (0x1UL)                   /*!< VALID (Bitfield-Mask: 0x01)                           */
/* =======================================================  SCRATCH0  ======================================================== */
#define MCUCTRL_SCRATCH0_SCRATCH0_Pos     (0UL)                     /*!< SCRATCH0 (Bit 0)                                      */
#define MCUCTRL_SCRATCH0_SCRATCH0_Msk     (0xffffffffUL)            /*!< SCRATCH0 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  SCRATCH1  ======================================================== */
#define MCUCTRL_SCRATCH1_SCRATCH1_Pos     (0UL)                     /*!< SCRATCH1 (Bit 0)                                      */
#define MCUCTRL_SCRATCH1_SCRATCH1_Msk     (0xffffffffUL)            /*!< SCRATCH1 (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  DBGR1  ========================================================= */
#define MCUCTRL_DBGR1_ONETO8_Pos          (0UL)                     /*!< ONETO8 (Bit 0)                                        */
#define MCUCTRL_DBGR1_ONETO8_Msk          (0xffffffffUL)            /*!< ONETO8 (Bitfield-Mask: 0xffffffff)                    */
/* =========================================================  DBGR2  ========================================================= */
#define MCUCTRL_DBGR2_COOLCODE_Pos        (0UL)                     /*!< COOLCODE (Bit 0)                                      */
#define MCUCTRL_DBGR2_COOLCODE_Msk        (0xffffffffUL)            /*!< COOLCODE (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  PMUENABLE  ======================================================= */
#define MCUCTRL_PMUENABLE_ENABLE_Pos      (0UL)                     /*!< ENABLE (Bit 0)                                        */
#define MCUCTRL_PMUENABLE_ENABLE_Msk      (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
/* ========================================================  DBGCTRL  ======================================================== */
#define MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST_Pos (17UL)              /*!< DBGDSP1OCDHALTONRST (Bit 17)                          */
#define MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST_Msk (0x20000UL)         /*!< DBGDSP1OCDHALTONRST (Bitfield-Mask: 0x01)             */
#define MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST_Pos (16UL)              /*!< DBGDSP0OCDHALTONRST (Bit 16)                          */
#define MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST_Msk (0x10000UL)         /*!< DBGDSP0OCDHALTONRST (Bitfield-Mask: 0x01)             */
#define MCUCTRL_DBGCTRL_DBGTSCLKSEL_Pos   (12UL)                    /*!< DBGTSCLKSEL (Bit 12)                                  */
#define MCUCTRL_DBGCTRL_DBGTSCLKSEL_Msk   (0x7000UL)                /*!< DBGTSCLKSEL (Bitfield-Mask: 0x07)                     */
#define MCUCTRL_DBGCTRL_DBGDSP1TRACEEN_Pos (11UL)                   /*!< DBGDSP1TRACEEN (Bit 11)                               */
#define MCUCTRL_DBGCTRL_DBGDSP1TRACEEN_Msk (0x800UL)                /*!< DBGDSP1TRACEEN (Bitfield-Mask: 0x01)                  */
#define MCUCTRL_DBGCTRL_DBGDSP0TRACEEN_Pos (10UL)                   /*!< DBGDSP0TRACEEN (Bit 10)                               */
#define MCUCTRL_DBGCTRL_DBGDSP0TRACEEN_Msk (0x400UL)                /*!< DBGDSP0TRACEEN (Bitfield-Mask: 0x01)                  */
#define MCUCTRL_DBGCTRL_DBGETMTRACEEN_Pos (9UL)                     /*!< DBGETMTRACEEN (Bit 9)                                 */
#define MCUCTRL_DBGCTRL_DBGETMTRACEEN_Msk (0x200UL)                 /*!< DBGETMTRACEEN (Bitfield-Mask: 0x01)                   */
#define MCUCTRL_DBGCTRL_DBGETBENABLE_Pos  (8UL)                     /*!< DBGETBENABLE (Bit 8)                                  */
#define MCUCTRL_DBGCTRL_DBGETBENABLE_Msk  (0x100UL)                 /*!< DBGETBENABLE (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_DBGCTRL_CM4CLKSEL_Pos     (1UL)                     /*!< CM4CLKSEL (Bit 1)                                     */
#define MCUCTRL_DBGCTRL_CM4CLKSEL_Msk     (0xeUL)                   /*!< CM4CLKSEL (Bitfield-Mask: 0x07)                       */
#define MCUCTRL_DBGCTRL_CM4TPIUENABLE_Pos (0UL)                     /*!< CM4TPIUENABLE (Bit 0)                                 */
#define MCUCTRL_DBGCTRL_CM4TPIUENABLE_Msk (0x1UL)                   /*!< CM4TPIUENABLE (Bitfield-Mask: 0x01)                   */
/* ======================================================  OTAPOINTER  ======================================================= */
#define MCUCTRL_OTAPOINTER_OTAPOINTER_Pos (2UL)                     /*!< OTAPOINTER (Bit 2)                                    */
#define MCUCTRL_OTAPOINTER_OTAPOINTER_Msk (0xfffffffcUL)            /*!< OTAPOINTER (Bitfield-Mask: 0x3fffffff)                */
#define MCUCTRL_OTAPOINTER_OTASBLUPDATE_Pos (1UL)                   /*!< OTASBLUPDATE (Bit 1)                                  */
#define MCUCTRL_OTAPOINTER_OTASBLUPDATE_Msk (0x2UL)                 /*!< OTASBLUPDATE (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_OTAPOINTER_OTAVALID_Pos   (0UL)                     /*!< OTAVALID (Bit 0)                                      */
#define MCUCTRL_OTAPOINTER_OTAVALID_Msk   (0x1UL)                   /*!< OTAVALID (Bitfield-Mask: 0x01)                        */
/* ======================================================  APBDMACTRL  ======================================================= */
#define MCUCTRL_APBDMACTRL_HYSTERESIS_Pos (8UL)                     /*!< HYSTERESIS (Bit 8)                                    */
#define MCUCTRL_APBDMACTRL_HYSTERESIS_Msk (0xff00UL)                /*!< HYSTERESIS (Bitfield-Mask: 0xff)                      */
#define MCUCTRL_APBDMACTRL_DECODEABORT_Pos (1UL)                    /*!< DECODEABORT (Bit 1)                                   */
#define MCUCTRL_APBDMACTRL_DECODEABORT_Msk (0x2UL)                  /*!< DECODEABORT (Bitfield-Mask: 0x01)                     */
#define MCUCTRL_APBDMACTRL_DMAENABLE_Pos  (0UL)                     /*!< DMAENABLE (Bit 0)                                     */
#define MCUCTRL_APBDMACTRL_DMAENABLE_Msk  (0x1UL)                   /*!< DMAENABLE (Bitfield-Mask: 0x01)                       */
/* ======================================================  KEXTCLKSEL  ======================================================= */
#define MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Pos (0UL)                     /*!< KEXTCLKSEL (Bit 0)                                    */
#define MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Msk (0xffffffffUL)            /*!< KEXTCLKSEL (Bitfield-Mask: 0xffffffff)                */
/* =======================================================  SIMOBUCK0  ======================================================= */
#define MCUCTRL_SIMOBUCK0_TONTOFFNODEGLITCH_Pos (4UL)               /*!< TONTOFFNODEGLITCH (Bit 4)                             */
#define MCUCTRL_SIMOBUCK0_TONTOFFNODEGLITCH_Msk (0x10UL)            /*!< TONTOFFNODEGLITCH (Bitfield-Mask: 0x01)               */
#define MCUCTRL_SIMOBUCK0_VDDCLVRXCOMPEN_Pos (3UL)                  /*!< VDDCLVRXCOMPEN (Bit 3)                                */
#define MCUCTRL_SIMOBUCK0_VDDCLVRXCOMPEN_Msk (0x8UL)                /*!< VDDCLVRXCOMPEN (Bitfield-Mask: 0x01)                  */
#define MCUCTRL_SIMOBUCK0_VDDSRXCOMPEN_Pos (2UL)                    /*!< VDDSRXCOMPEN (Bit 2)                                  */
#define MCUCTRL_SIMOBUCK0_VDDSRXCOMPEN_Msk (0x4UL)                  /*!< VDDSRXCOMPEN (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_SIMOBUCK0_VDDFRXCOMPEN_Pos (1UL)                    /*!< VDDFRXCOMPEN (Bit 1)                                  */
#define MCUCTRL_SIMOBUCK0_VDDFRXCOMPEN_Msk (0x2UL)                  /*!< VDDFRXCOMPEN (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_SIMOBUCK0_VDDCRXCOMPEN_Pos (0UL)                    /*!< VDDCRXCOMPEN (Bit 0)                                  */
#define MCUCTRL_SIMOBUCK0_VDDCRXCOMPEN_Msk (0x1UL)                  /*!< VDDCRXCOMPEN (Bitfield-Mask: 0x01)                    */
/* =======================================================  SIMOBUCK1  ======================================================= */
#define MCUCTRL_SIMOBUCK1_TONCLKTRIM_Pos  (22UL)                    /*!< TONCLKTRIM (Bit 22)                                   */
#define MCUCTRL_SIMOBUCK1_TONCLKTRIM_Msk  (0x3c00000UL)             /*!< TONCLKTRIM (Bitfield-Mask: 0x0f)                      */
#define MCUCTRL_SIMOBUCK1_RXCLKACTTRIM_Pos (6UL)                    /*!< RXCLKACTTRIM (Bit 6)                                  */
#define MCUCTRL_SIMOBUCK1_RXCLKACTTRIM_Msk (0x7c0UL)                /*!< RXCLKACTTRIM (Bitfield-Mask: 0x1f)                    */
/* =======================================================  SIMOBUCK2  ======================================================= */
#define MCUCTRL_SIMOBUCK2_VDDCACTLOWTONTRIM_Pos (24UL)              /*!< VDDCACTLOWTONTRIM (Bit 24)                            */
#define MCUCTRL_SIMOBUCK2_VDDCACTLOWTONTRIM_Msk (0x1f000000UL)      /*!< VDDCACTLOWTONTRIM (Bitfield-Mask: 0x1f)               */
#define MCUCTRL_SIMOBUCK2_VDDCACTHIGHTONTRIM_Pos (11UL)             /*!< VDDCACTHIGHTONTRIM (Bit 11)                           */
#define MCUCTRL_SIMOBUCK2_VDDCACTHIGHTONTRIM_Msk (0x7800UL)         /*!< VDDCACTHIGHTONTRIM (Bitfield-Mask: 0x0f)              */
/* =======================================================  SIMOBUCK3  ======================================================= */
#define MCUCTRL_SIMOBUCK3_VDDCLPLOWTONTRIM_Pos (26UL)               /*!< VDDCLPLOWTONTRIM (Bit 26)                             */
#define MCUCTRL_SIMOBUCK3_VDDCLPLOWTONTRIM_Msk (0x3c000000UL)       /*!< VDDCLPLOWTONTRIM (Bitfield-Mask: 0x0f)                */
#define MCUCTRL_SIMOBUCK3_VDDCLPHIGHTONTRIM_Pos (13UL)              /*!< VDDCLPHIGHTONTRIM (Bit 13)                            */
#define MCUCTRL_SIMOBUCK3_VDDCLPHIGHTONTRIM_Msk (0x1e000UL)         /*!< VDDCLPHIGHTONTRIM (Bitfield-Mask: 0x0f)               */
/* =======================================================  SIMOBUCK6  ======================================================= */
#define MCUCTRL_SIMOBUCK6_VDDFACTHIGHTONTRIM_Pos (17UL)             /*!< VDDFACTHIGHTONTRIM (Bit 17)                           */
#define MCUCTRL_SIMOBUCK6_VDDFACTHIGHTONTRIM_Msk (0x1e0000UL)       /*!< VDDFACTHIGHTONTRIM (Bitfield-Mask: 0x0f)              */
/* =======================================================  SIMOBUCK7  ======================================================= */
#define MCUCTRL_SIMOBUCK7_ZXCOMPZXTRIM_Pos (18UL)                   /*!< ZXCOMPZXTRIM (Bit 18)                                 */
#define MCUCTRL_SIMOBUCK7_ZXCOMPZXTRIM_Msk (0x7c0000UL)             /*!< ZXCOMPZXTRIM (Bitfield-Mask: 0x1f)                    */
#define MCUCTRL_SIMOBUCK7_VDDFACTLOWTONTRIM_Pos (8UL)               /*!< VDDFACTLOWTONTRIM (Bit 8)                             */
#define MCUCTRL_SIMOBUCK7_VDDFACTLOWTONTRIM_Msk (0x1f00UL)          /*!< VDDFACTLOWTONTRIM (Bitfield-Mask: 0x1f)               */
/* =======================================================  SIMOBUCK8  ======================================================= */
#define MCUCTRL_SIMOBUCK8_VDDFLPLOWTONTRIM_Pos (22UL)               /*!< VDDFLPLOWTONTRIM (Bit 22)                             */
#define MCUCTRL_SIMOBUCK8_VDDFLPLOWTONTRIM_Msk (0x3c00000UL)        /*!< VDDFLPLOWTONTRIM (Bitfield-Mask: 0x0f)                */
#define MCUCTRL_SIMOBUCK8_VDDFLPHIGHTONTRIM_Pos (9UL)               /*!< VDDFLPHIGHTONTRIM (Bit 9)                             */
#define MCUCTRL_SIMOBUCK8_VDDFLPHIGHTONTRIM_Msk (0x1e00UL)          /*!< VDDFLPHIGHTONTRIM (Bitfield-Mask: 0x0f)               */
/* =======================================================  SIMOBUCK9  ======================================================= */
#define MCUCTRL_SIMOBUCK9_VDDSACTLOWTONTRIM_Pos (22UL)              /*!< VDDSACTLOWTONTRIM (Bit 22)                            */
#define MCUCTRL_SIMOBUCK9_VDDSACTLOWTONTRIM_Msk (0x7c00000UL)       /*!< VDDSACTLOWTONTRIM (Bitfield-Mask: 0x1f)               */
#define MCUCTRL_SIMOBUCK9_VDDSACTHIGHTONTRIM_Pos (17UL)             /*!< VDDSACTHIGHTONTRIM (Bit 17)                           */
#define MCUCTRL_SIMOBUCK9_VDDSACTHIGHTONTRIM_Msk (0x1e0000UL)       /*!< VDDSACTHIGHTONTRIM (Bitfield-Mask: 0x0f)              */
/* ======================================================  SIMOBUCK12  ======================================================= */
#define MCUCTRL_SIMOBUCK12_LPTRIMVDDF_Pos (26UL)                    /*!< LPTRIMVDDF (Bit 26)                                   */
#define MCUCTRL_SIMOBUCK12_LPTRIMVDDF_Msk (0xfc000000UL)            /*!< LPTRIMVDDF (Bitfield-Mask: 0x3f)                      */
#define MCUCTRL_SIMOBUCK12_ACTTRIMVDDF_Pos (20UL)                   /*!< ACTTRIMVDDF (Bit 20)                                  */
#define MCUCTRL_SIMOBUCK12_ACTTRIMVDDF_Msk (0x3f00000UL)            /*!< ACTTRIMVDDF (Bitfield-Mask: 0x3f)                     */
/* ======================================================  SIMOBUCK13  ======================================================= */
#define MCUCTRL_SIMOBUCK13_LPTRIMVDDS_Pos (26UL)                    /*!< LPTRIMVDDS (Bit 26)                                   */
#define MCUCTRL_SIMOBUCK13_LPTRIMVDDS_Msk (0xfc000000UL)            /*!< LPTRIMVDDS (Bitfield-Mask: 0x3f)                      */
#define MCUCTRL_SIMOBUCK13_ACTTRIMVDDS_Pos (20UL)                   /*!< ACTTRIMVDDS (Bit 20)                                  */
#define MCUCTRL_SIMOBUCK13_ACTTRIMVDDS_Msk (0x3f00000UL)            /*!< ACTTRIMVDDS (Bitfield-Mask: 0x3f)                     */
/* ======================================================  SIMOBUCK15  ======================================================= */
#define MCUCTRL_SIMOBUCK15_TRIMLATCHOVER_Pos (31UL)                 /*!< TRIMLATCHOVER (Bit 31)                                */
#define MCUCTRL_SIMOBUCK15_TRIMLATCHOVER_Msk (0x80000000UL)         /*!< TRIMLATCHOVER (Bitfield-Mask: 0x01)                   */
#define MCUCTRL_SIMOBUCK15_ZXCOMPOFFSETTRIM_Pos (24UL)              /*!< ZXCOMPOFFSETTRIM (Bit 24)                             */
#define MCUCTRL_SIMOBUCK15_ZXCOMPOFFSETTRIM_Msk (0x1f000000UL)      /*!< ZXCOMPOFFSETTRIM (Bitfield-Mask: 0x1f)                */
/* ========================================================  PWRSW0  ========================================================= */
#define MCUCTRL_PWRSW0_PWRSWVDDRCPUOVERRIDE_Pos (31UL)              /*!< PWRSWVDDRCPUOVERRIDE (Bit 31)                         */
#define MCUCTRL_PWRSW0_PWRSWVDDRCPUOVERRIDE_Msk (0x80000000UL)      /*!< PWRSWVDDRCPUOVERRIDE (Bitfield-Mask: 0x01)            */
#define MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL_Pos (30UL)               /*!< PWRSWVDDRCPUSTATSEL (Bit 30)                          */
#define MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL_Msk (0x40000000UL)       /*!< PWRSWVDDRCPUSTATSEL (Bitfield-Mask: 0x01)             */
#define MCUCTRL_PWRSW0_PWRSWVDDRCPUPGN_Pos (29UL)                   /*!< PWRSWVDDRCPUPGN (Bit 29)                              */
#define MCUCTRL_PWRSW0_PWRSWVDDRCPUPGN_Msk (0x20000000UL)           /*!< PWRSWVDDRCPUPGN (Bitfield-Mask: 0x01)                 */
#define MCUCTRL_PWRSW0_PWRSWVDDRCPUDYNSEL_Pos (27UL)                /*!< PWRSWVDDRCPUDYNSEL (Bit 27)                           */
#define MCUCTRL_PWRSW0_PWRSWVDDRCPUDYNSEL_Msk (0x18000000UL)        /*!< PWRSWVDDRCPUDYNSEL (Bitfield-Mask: 0x03)              */
#define MCUCTRL_PWRSW0_PWRSWVDDMLOVERRIDE_Pos (26UL)                /*!< PWRSWVDDMLOVERRIDE (Bit 26)                           */
#define MCUCTRL_PWRSW0_PWRSWVDDMLOVERRIDE_Msk (0x4000000UL)         /*!< PWRSWVDDMLOVERRIDE (Bitfield-Mask: 0x01)              */
#define MCUCTRL_PWRSW0_PWRSWVDDMLSTATSEL_Pos (25UL)                 /*!< PWRSWVDDMLSTATSEL (Bit 25)                            */
#define MCUCTRL_PWRSW0_PWRSWVDDMLSTATSEL_Msk (0x2000000UL)          /*!< PWRSWVDDMLSTATSEL (Bitfield-Mask: 0x01)               */
#define MCUCTRL_PWRSW0_PWRSWVDDMLDYNSEL_Pos (24UL)                  /*!< PWRSWVDDMLDYNSEL (Bit 24)                             */
#define MCUCTRL_PWRSW0_PWRSWVDDMLDYNSEL_Msk (0x1000000UL)           /*!< PWRSWVDDMLDYNSEL (Bitfield-Mask: 0x01)                */
#define MCUCTRL_PWRSW0_PWRSWVDDMDSP1OVERRIDE_Pos (23UL)             /*!< PWRSWVDDMDSP1OVERRIDE (Bit 23)                        */
#define MCUCTRL_PWRSW0_PWRSWVDDMDSP1OVERRIDE_Msk (0x800000UL)       /*!< PWRSWVDDMDSP1OVERRIDE (Bitfield-Mask: 0x01)           */
#define MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL_Pos (22UL)              /*!< PWRSWVDDMDSP1STATSEL (Bit 22)                         */
#define MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL_Msk (0x400000UL)        /*!< PWRSWVDDMDSP1STATSEL (Bitfield-Mask: 0x01)            */
#define MCUCTRL_PWRSW0_PWRSWVDDMDSP1DYNSEL_Pos (21UL)               /*!< PWRSWVDDMDSP1DYNSEL (Bit 21)                          */
#define MCUCTRL_PWRSW0_PWRSWVDDMDSP1DYNSEL_Msk (0x200000UL)         /*!< PWRSWVDDMDSP1DYNSEL (Bitfield-Mask: 0x01)             */
#define MCUCTRL_PWRSW0_PWRSWVDDMDSP0OVERRIDE_Pos (20UL)             /*!< PWRSWVDDMDSP0OVERRIDE (Bit 20)                        */
#define MCUCTRL_PWRSW0_PWRSWVDDMDSP0OVERRIDE_Msk (0x100000UL)       /*!< PWRSWVDDMDSP0OVERRIDE (Bitfield-Mask: 0x01)           */
#define MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL_Pos (19UL)              /*!< PWRSWVDDMDSP0STATSEL (Bit 19)                         */
#define MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL_Msk (0x80000UL)         /*!< PWRSWVDDMDSP0STATSEL (Bitfield-Mask: 0x01)            */
#define MCUCTRL_PWRSW0_PWRSWVDDMDSP0DYNSEL_Pos (18UL)               /*!< PWRSWVDDMDSP0DYNSEL (Bit 18)                          */
#define MCUCTRL_PWRSW0_PWRSWVDDMDSP0DYNSEL_Msk (0x40000UL)          /*!< PWRSWVDDMDSP0DYNSEL (Bitfield-Mask: 0x01)             */
#define MCUCTRL_PWRSW0_PWRSWVDDMCPUOVERRIDE_Pos (17UL)              /*!< PWRSWVDDMCPUOVERRIDE (Bit 17)                         */
#define MCUCTRL_PWRSW0_PWRSWVDDMCPUOVERRIDE_Msk (0x20000UL)         /*!< PWRSWVDDMCPUOVERRIDE (Bitfield-Mask: 0x01)            */
#define MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL_Pos (16UL)               /*!< PWRSWVDDMCPUSTATSEL (Bit 16)                          */
#define MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL_Msk (0x10000UL)          /*!< PWRSWVDDMCPUSTATSEL (Bitfield-Mask: 0x01)             */
#define MCUCTRL_PWRSW0_PWRSWVDDMCPUDYNSEL_Pos (15UL)                /*!< PWRSWVDDMCPUDYNSEL (Bit 15)                           */
#define MCUCTRL_PWRSW0_PWRSWVDDMCPUDYNSEL_Msk (0x8000UL)            /*!< PWRSWVDDMCPUDYNSEL (Bitfield-Mask: 0x01)              */
#define MCUCTRL_PWRSW0_PWRSWVDDDSP1OVERRIDE_Pos (14UL)              /*!< PWRSWVDDDSP1OVERRIDE (Bit 14)                         */
#define MCUCTRL_PWRSW0_PWRSWVDDDSP1OVERRIDE_Msk (0x4000UL)          /*!< PWRSWVDDDSP1OVERRIDE (Bitfield-Mask: 0x01)            */
#define MCUCTRL_PWRSW0_PWRSWVDDDSP1PGN_Pos (13UL)                   /*!< PWRSWVDDDSP1PGN (Bit 13)                              */
#define MCUCTRL_PWRSW0_PWRSWVDDDSP1PGN_Msk (0x2000UL)               /*!< PWRSWVDDDSP1PGN (Bitfield-Mask: 0x01)                 */
#define MCUCTRL_PWRSW0_PWRSWVDDDSP1DYNSEL_Pos (11UL)                /*!< PWRSWVDDDSP1DYNSEL (Bit 11)                           */
#define MCUCTRL_PWRSW0_PWRSWVDDDSP1DYNSEL_Msk (0x1800UL)            /*!< PWRSWVDDDSP1DYNSEL (Bitfield-Mask: 0x03)              */
#define MCUCTRL_PWRSW0_PWRSWVDDDSP0OVERRIDE_Pos (10UL)              /*!< PWRSWVDDDSP0OVERRIDE (Bit 10)                         */
#define MCUCTRL_PWRSW0_PWRSWVDDDSP0OVERRIDE_Msk (0x400UL)           /*!< PWRSWVDDDSP0OVERRIDE (Bitfield-Mask: 0x01)            */
#define MCUCTRL_PWRSW0_PWRSWVDDDSP0PGN_Pos (9UL)                    /*!< PWRSWVDDDSP0PGN (Bit 9)                               */
#define MCUCTRL_PWRSW0_PWRSWVDDDSP0PGN_Msk (0x200UL)                /*!< PWRSWVDDDSP0PGN (Bitfield-Mask: 0x01)                 */
#define MCUCTRL_PWRSW0_PWRSWVDDDSP0DYNSEL_Pos (7UL)                 /*!< PWRSWVDDDSP0DYNSEL (Bit 7)                            */
#define MCUCTRL_PWRSW0_PWRSWVDDDSP0DYNSEL_Msk (0x180UL)             /*!< PWRSWVDDDSP0DYNSEL (Bitfield-Mask: 0x03)              */
#define MCUCTRL_PWRSW0_PWRSWVDDCAOROVERRIDE_Pos (6UL)               /*!< PWRSWVDDCAOROVERRIDE (Bit 6)                          */
#define MCUCTRL_PWRSW0_PWRSWVDDCAOROVERRIDE_Msk (0x40UL)            /*!< PWRSWVDDCAOROVERRIDE (Bitfield-Mask: 0x01)            */
#define MCUCTRL_PWRSW0_PWRSWVDDCAORDYNSEL_Pos (4UL)                 /*!< PWRSWVDDCAORDYNSEL (Bit 4)                            */
#define MCUCTRL_PWRSW0_PWRSWVDDCAORDYNSEL_Msk (0x30UL)              /*!< PWRSWVDDCAORDYNSEL (Bitfield-Mask: 0x03)              */
#define MCUCTRL_PWRSW0_PWRSWVDDCPUOVERRIDE_Pos (3UL)                /*!< PWRSWVDDCPUOVERRIDE (Bit 3)                           */
#define MCUCTRL_PWRSW0_PWRSWVDDCPUOVERRIDE_Msk (0x8UL)              /*!< PWRSWVDDCPUOVERRIDE (Bitfield-Mask: 0x01)             */
#define MCUCTRL_PWRSW0_PWRSWVDDCPUPGN_Pos (2UL)                     /*!< PWRSWVDDCPUPGN (Bit 2)                                */
#define MCUCTRL_PWRSW0_PWRSWVDDCPUPGN_Msk (0x4UL)                   /*!< PWRSWVDDCPUPGN (Bitfield-Mask: 0x01)                  */
#define MCUCTRL_PWRSW0_PWRSWVDDCPUDYNSEL_Pos (0UL)                  /*!< PWRSWVDDCPUDYNSEL (Bit 0)                             */
#define MCUCTRL_PWRSW0_PWRSWVDDCPUDYNSEL_Msk (0x3UL)                /*!< PWRSWVDDCPUDYNSEL (Bitfield-Mask: 0x03)               */
/* ========================================================  PWRSW1  ========================================================= */
#define MCUCTRL_PWRSW1_SHORTVDDFVDDSORVAL_Pos (31UL)                /*!< SHORTVDDFVDDSORVAL (Bit 31)                           */
#define MCUCTRL_PWRSW1_SHORTVDDFVDDSORVAL_Msk (0x80000000UL)        /*!< SHORTVDDFVDDSORVAL (Bitfield-Mask: 0x01)              */
#define MCUCTRL_PWRSW1_SHORTVDDFVDDSOREN_Pos (30UL)                 /*!< SHORTVDDFVDDSOREN (Bit 30)                            */
#define MCUCTRL_PWRSW1_SHORTVDDFVDDSOREN_Msk (0x40000000UL)         /*!< SHORTVDDFVDDSOREN (Bitfield-Mask: 0x01)               */
#define MCUCTRL_PWRSW1_SHORTVDDCVDDCLVORVAL_Pos (29UL)              /*!< SHORTVDDCVDDCLVORVAL (Bit 29)                         */
#define MCUCTRL_PWRSW1_SHORTVDDCVDDCLVORVAL_Msk (0x20000000UL)      /*!< SHORTVDDCVDDCLVORVAL (Bitfield-Mask: 0x01)            */
#define MCUCTRL_PWRSW1_SHORTVDDCVDDCLVOREN_Pos (28UL)               /*!< SHORTVDDCVDDCLVOREN (Bit 28)                          */
#define MCUCTRL_PWRSW1_SHORTVDDCVDDCLVOREN_Msk (0x10000000UL)       /*!< SHORTVDDCVDDCLVOREN (Bitfield-Mask: 0x01)             */
#define MCUCTRL_PWRSW1_FORCEVDDRMOFF_Pos  (27UL)                    /*!< FORCEVDDRMOFF (Bit 27)                                */
#define MCUCTRL_PWRSW1_FORCEVDDRMOFF_Msk  (0x8000000UL)             /*!< FORCEVDDRMOFF (Bitfield-Mask: 0x01)                   */
#define MCUCTRL_PWRSW1_FORCEVDDRMVDDS_Pos (26UL)                    /*!< FORCEVDDRMVDDS (Bit 26)                               */
#define MCUCTRL_PWRSW1_FORCEVDDRMVDDS_Msk (0x4000000UL)             /*!< FORCEVDDRMVDDS (Bitfield-Mask: 0x01)                  */
#define MCUCTRL_PWRSW1_USEVDDF4VDDRCPUINHP_Pos (25UL)               /*!< USEVDDF4VDDRCPUINHP (Bit 25)                          */
#define MCUCTRL_PWRSW1_USEVDDF4VDDRCPUINHP_Msk (0x2000000UL)        /*!< USEVDDF4VDDRCPUINHP (Bitfield-Mask: 0x01)             */
#define MCUCTRL_PWRSW1_DIGPWRSWOVRDRVSEL_Pos (23UL)                 /*!< DIGPWRSWOVRDRVSEL (Bit 23)                            */
#define MCUCTRL_PWRSW1_DIGPWRSWOVRDRVSEL_Msk (0x1800000UL)          /*!< DIGPWRSWOVRDRVSEL (Bitfield-Mask: 0x03)               */
#define MCUCTRL_PWRSW1_DIGPWRSWOVRDRVEN_Pos (22UL)                  /*!< DIGPWRSWOVRDRVEN (Bit 22)                             */
#define MCUCTRL_PWRSW1_DIGPWRSWOVRDRVEN_Msk (0x400000UL)            /*!< DIGPWRSWOVRDRVEN (Bitfield-Mask: 0x01)                */
#define MCUCTRL_PWRSW1_PWRSWOVRDRVEN_Pos  (21UL)                    /*!< PWRSWOVRDRVEN (Bit 21)                                */
#define MCUCTRL_PWRSW1_PWRSWOVRDRVEN_Msk  (0x200000UL)              /*!< PWRSWOVRDRVEN (Bitfield-Mask: 0x01)                   */
#define MCUCTRL_PWRSW1_PWRSWCOMPPDNB_Pos  (20UL)                    /*!< PWRSWCOMPPDNB (Bit 20)                                */
#define MCUCTRL_PWRSW1_PWRSWCOMPPDNB_Msk  (0x100000UL)              /*!< PWRSWCOMPPDNB (Bitfield-Mask: 0x01)                   */
#define MCUCTRL_PWRSW1_PWRSWVDDLOVERRIDE_Pos (19UL)                 /*!< PWRSWVDDLOVERRIDE (Bit 19)                            */
#define MCUCTRL_PWRSW1_PWRSWVDDLOVERRIDE_Msk (0x80000UL)            /*!< PWRSWVDDLOVERRIDE (Bitfield-Mask: 0x01)               */
#define MCUCTRL_PWRSW1_PWRSWVDDLPGN_Pos   (18UL)                    /*!< PWRSWVDDLPGN (Bit 18)                                 */
#define MCUCTRL_PWRSW1_PWRSWVDDLPGN_Msk   (0x40000UL)               /*!< PWRSWVDDLPGN (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_PWRSW1_PWRSWVDDRMOVERRIDE_Pos (17UL)                /*!< PWRSWVDDRMOVERRIDE (Bit 17)                           */
#define MCUCTRL_PWRSW1_PWRSWVDDRMOVERRIDE_Msk (0x20000UL)           /*!< PWRSWVDDRMOVERRIDE (Bitfield-Mask: 0x01)              */
#define MCUCTRL_PWRSW1_PWRSWVDDRMSTATSEL_Pos (16UL)                 /*!< PWRSWVDDRMSTATSEL (Bit 16)                            */
#define MCUCTRL_PWRSW1_PWRSWVDDRMSTATSEL_Msk (0x10000UL)            /*!< PWRSWVDDRMSTATSEL (Bitfield-Mask: 0x01)               */
#define MCUCTRL_PWRSW1_PWRSWVDDRMPGN_Pos  (15UL)                    /*!< PWRSWVDDRMPGN (Bit 15)                                */
#define MCUCTRL_PWRSW1_PWRSWVDDRMPGN_Msk  (0x8000UL)                /*!< PWRSWVDDRMPGN (Bitfield-Mask: 0x01)                   */
#define MCUCTRL_PWRSW1_PWRSWVDDRMDYNSEL_Pos (14UL)                  /*!< PWRSWVDDRMDYNSEL (Bit 14)                             */
#define MCUCTRL_PWRSW1_PWRSWVDDRMDYNSEL_Msk (0x4000UL)              /*!< PWRSWVDDRMDYNSEL (Bitfield-Mask: 0x01)                */
#define MCUCTRL_PWRSW1_PWRSWVDDRLOVERRIDE_Pos (13UL)                /*!< PWRSWVDDRLOVERRIDE (Bit 13)                           */
#define MCUCTRL_PWRSW1_PWRSWVDDRLOVERRIDE_Msk (0x2000UL)            /*!< PWRSWVDDRLOVERRIDE (Bitfield-Mask: 0x01)              */
#define MCUCTRL_PWRSW1_PWRSWVDDRLSTATSEL_Pos (12UL)                 /*!< PWRSWVDDRLSTATSEL (Bit 12)                            */
#define MCUCTRL_PWRSW1_PWRSWVDDRLSTATSEL_Msk (0x1000UL)             /*!< PWRSWVDDRLSTATSEL (Bitfield-Mask: 0x01)               */
#define MCUCTRL_PWRSW1_PWRSWVDDRLPGN_Pos  (11UL)                    /*!< PWRSWVDDRLPGN (Bit 11)                                */
#define MCUCTRL_PWRSW1_PWRSWVDDRLPGN_Msk  (0x800UL)                 /*!< PWRSWVDDRLPGN (Bitfield-Mask: 0x01)                   */
#define MCUCTRL_PWRSW1_PWRSWVDDRLDYNSEL_Pos (10UL)                  /*!< PWRSWVDDRLDYNSEL (Bit 10)                             */
#define MCUCTRL_PWRSW1_PWRSWVDDRLDYNSEL_Msk (0x400UL)               /*!< PWRSWVDDRLDYNSEL (Bitfield-Mask: 0x01)                */
#define MCUCTRL_PWRSW1_PWRSWVDDRDSP1OVERRIDE_Pos (9UL)              /*!< PWRSWVDDRDSP1OVERRIDE (Bit 9)                         */
#define MCUCTRL_PWRSW1_PWRSWVDDRDSP1OVERRIDE_Msk (0x200UL)          /*!< PWRSWVDDRDSP1OVERRIDE (Bitfield-Mask: 0x01)           */
#define MCUCTRL_PWRSW1_PWRSWVDDRDSP1STATSEL_Pos (8UL)               /*!< PWRSWVDDRDSP1STATSEL (Bit 8)                          */
#define MCUCTRL_PWRSW1_PWRSWVDDRDSP1STATSEL_Msk (0x100UL)           /*!< PWRSWVDDRDSP1STATSEL (Bitfield-Mask: 0x01)            */
#define MCUCTRL_PWRSW1_PWRSWVDDRDSP1PGN_Pos (7UL)                   /*!< PWRSWVDDRDSP1PGN (Bit 7)                              */
#define MCUCTRL_PWRSW1_PWRSWVDDRDSP1PGN_Msk (0x80UL)                /*!< PWRSWVDDRDSP1PGN (Bitfield-Mask: 0x01)                */
#define MCUCTRL_PWRSW1_PWRSWVDDRDSP1DYNSEL_Pos (5UL)                /*!< PWRSWVDDRDSP1DYNSEL (Bit 5)                           */
#define MCUCTRL_PWRSW1_PWRSWVDDRDSP1DYNSEL_Msk (0x60UL)             /*!< PWRSWVDDRDSP1DYNSEL (Bitfield-Mask: 0x03)             */
#define MCUCTRL_PWRSW1_PWRSWVDDRDSP0OVERRIDE_Pos (4UL)              /*!< PWRSWVDDRDSP0OVERRIDE (Bit 4)                         */
#define MCUCTRL_PWRSW1_PWRSWVDDRDSP0OVERRIDE_Msk (0x10UL)           /*!< PWRSWVDDRDSP0OVERRIDE (Bitfield-Mask: 0x01)           */
#define MCUCTRL_PWRSW1_PWRSWVDDRDSP0STATSEL_Pos (3UL)               /*!< PWRSWVDDRDSP0STATSEL (Bit 3)                          */
#define MCUCTRL_PWRSW1_PWRSWVDDRDSP0STATSEL_Msk (0x8UL)             /*!< PWRSWVDDRDSP0STATSEL (Bitfield-Mask: 0x01)            */
#define MCUCTRL_PWRSW1_PWRSWVDDRDSP0PGN_Pos (2UL)                   /*!< PWRSWVDDRDSP0PGN (Bit 2)                              */
#define MCUCTRL_PWRSW1_PWRSWVDDRDSP0PGN_Msk (0x4UL)                 /*!< PWRSWVDDRDSP0PGN (Bitfield-Mask: 0x01)                */
#define MCUCTRL_PWRSW1_PWRSWVDDRDSP0DYNSEL_Pos (0UL)                /*!< PWRSWVDDRDSP0DYNSEL (Bit 0)                           */
#define MCUCTRL_PWRSW1_PWRSWVDDRDSP0DYNSEL_Msk (0x3UL)              /*!< PWRSWVDDRDSP0DYNSEL (Bitfield-Mask: 0x03)             */
/* ======================================================  USBRSTCTRL  ======================================================= */
#define MCUCTRL_USBRSTCTRL_USBUTMIRSTRELEASE_Pos (2UL)              /*!< USBUTMIRSTRELEASE (Bit 2)                             */
#define MCUCTRL_USBRSTCTRL_USBUTMIRSTRELEASE_Msk (0x4UL)            /*!< USBUTMIRSTRELEASE (Bitfield-Mask: 0x01)               */
#define MCUCTRL_USBRSTCTRL_USBPORRSTRELEASE_Pos (1UL)               /*!< USBPORRSTRELEASE (Bit 1)                              */
#define MCUCTRL_USBRSTCTRL_USBPORRSTRELEASE_Msk (0x2UL)             /*!< USBPORRSTRELEASE (Bitfield-Mask: 0x01)                */
#define MCUCTRL_USBRSTCTRL_USBRSTENABLE_Pos (0UL)                   /*!< USBRSTENABLE (Bit 0)                                  */
#define MCUCTRL_USBRSTCTRL_USBRSTENABLE_Msk (0x1UL)                 /*!< USBRSTENABLE (Bitfield-Mask: 0x01)                    */
/* ======================================================  FLASHWPROT0  ====================================================== */
#define MCUCTRL_FLASHWPROT0_FW0BITS_Pos   (0UL)                     /*!< FW0BITS (Bit 0)                                       */
#define MCUCTRL_FLASHWPROT0_FW0BITS_Msk   (0xffffffffUL)            /*!< FW0BITS (Bitfield-Mask: 0xffffffff)                   */
/* ======================================================  FLASHWPROT1  ====================================================== */
#define MCUCTRL_FLASHWPROT1_FW1BITS_Pos   (0UL)                     /*!< FW1BITS (Bit 0)                                       */
#define MCUCTRL_FLASHWPROT1_FW1BITS_Msk   (0xffffffffUL)            /*!< FW1BITS (Bitfield-Mask: 0xffffffff)                   */
/* ======================================================  FLASHWPROT2  ====================================================== */
#define MCUCTRL_FLASHWPROT2_FW2BITS_Pos   (0UL)                     /*!< FW2BITS (Bit 0)                                       */
#define MCUCTRL_FLASHWPROT2_FW2BITS_Msk   (0xffffffffUL)            /*!< FW2BITS (Bitfield-Mask: 0xffffffff)                   */
/* ======================================================  FLASHWPROT3  ====================================================== */
#define MCUCTRL_FLASHWPROT3_FW3BITS_Pos   (0UL)                     /*!< FW3BITS (Bit 0)                                       */
#define MCUCTRL_FLASHWPROT3_FW3BITS_Msk   (0xffffffffUL)            /*!< FW3BITS (Bitfield-Mask: 0xffffffff)                   */
/* ======================================================  FLASHRPROT0  ====================================================== */
#define MCUCTRL_FLASHRPROT0_FR0BITS_Pos   (0UL)                     /*!< FR0BITS (Bit 0)                                       */
#define MCUCTRL_FLASHRPROT0_FR0BITS_Msk   (0xffffffffUL)            /*!< FR0BITS (Bitfield-Mask: 0xffffffff)                   */
/* ======================================================  FLASHRPROT1  ====================================================== */
#define MCUCTRL_FLASHRPROT1_FR1BITS_Pos   (0UL)                     /*!< FR1BITS (Bit 0)                                       */
#define MCUCTRL_FLASHRPROT1_FR1BITS_Msk   (0xffffffffUL)            /*!< FR1BITS (Bitfield-Mask: 0xffffffff)                   */
/* ======================================================  FLASHRPROT2  ====================================================== */
#define MCUCTRL_FLASHRPROT2_FR2BITS_Pos   (0UL)                     /*!< FR2BITS (Bit 0)                                       */
#define MCUCTRL_FLASHRPROT2_FR2BITS_Msk   (0xffffffffUL)            /*!< FR2BITS (Bitfield-Mask: 0xffffffff)                   */
/* ======================================================  FLASHRPROT3  ====================================================== */
#define MCUCTRL_FLASHRPROT3_FR3BITS_Pos   (0UL)                     /*!< FR3BITS (Bit 0)                                       */
#define MCUCTRL_FLASHRPROT3_FR3BITS_Msk   (0xffffffffUL)            /*!< FR3BITS (Bitfield-Mask: 0xffffffff)                   */
/* =====================================================  DMASRAMWPROT0  ===================================================== */
#define MCUCTRL_DMASRAMWPROT0_DMAWPROT0_Pos (0UL)                   /*!< DMAWPROT0 (Bit 0)                                     */
#define MCUCTRL_DMASRAMWPROT0_DMAWPROT0_Msk (0xffffffffUL)          /*!< DMAWPROT0 (Bitfield-Mask: 0xffffffff)                 */
/* =====================================================  DMASRAMWPROT1  ===================================================== */
#define MCUCTRL_DMASRAMWPROT1_DMAWPROT1_Pos (0UL)                   /*!< DMAWPROT1 (Bit 0)                                     */
#define MCUCTRL_DMASRAMWPROT1_DMAWPROT1_Msk (0xffffUL)              /*!< DMAWPROT1 (Bitfield-Mask: 0xffff)                     */
/* =====================================================  DMASRAMRPROT0  ===================================================== */
#define MCUCTRL_DMASRAMRPROT0_DMARPROT0_Pos (0UL)                   /*!< DMARPROT0 (Bit 0)                                     */
#define MCUCTRL_DMASRAMRPROT0_DMARPROT0_Msk (0xffffffffUL)          /*!< DMARPROT0 (Bitfield-Mask: 0xffffffff)                 */
/* =====================================================  DMASRAMRPROT1  ===================================================== */
#define MCUCTRL_DMASRAMRPROT1_DMARPROT1_Pos (0UL)                   /*!< DMARPROT1 (Bit 0)                                     */
#define MCUCTRL_DMASRAMRPROT1_DMARPROT1_Msk (0xffffUL)              /*!< DMARPROT1 (Bitfield-Mask: 0xffff)                     */
/* ======================================================  USBPHYRESET  ====================================================== */
#define MCUCTRL_USBPHYRESET_RESERVED18_Pos (31UL)                   /*!< RESERVED18 (Bit 31)                                   */
#define MCUCTRL_USBPHYRESET_RESERVED18_Msk (0x80000000UL)           /*!< RESERVED18 (Bitfield-Mask: 0x01)                      */
#define MCUCTRL_USBPHYRESET_RESERVED17_Pos (28UL)                   /*!< RESERVED17 (Bit 28)                                   */
#define MCUCTRL_USBPHYRESET_RESERVED17_Msk (0x70000000UL)           /*!< RESERVED17 (Bitfield-Mask: 0x07)                      */
#define MCUCTRL_USBPHYRESET_RESERVED16_Pos (27UL)                   /*!< RESERVED16 (Bit 27)                                   */
#define MCUCTRL_USBPHYRESET_RESERVED16_Msk (0x8000000UL)            /*!< RESERVED16 (Bitfield-Mask: 0x01)                      */
#define MCUCTRL_USBPHYRESET_RESERVED15_Pos (25UL)                   /*!< RESERVED15 (Bit 25)                                   */
#define MCUCTRL_USBPHYRESET_RESERVED15_Msk (0x6000000UL)            /*!< RESERVED15 (Bitfield-Mask: 0x03)                      */
#define MCUCTRL_USBPHYRESET_RESERVED14_Pos (24UL)                   /*!< RESERVED14 (Bit 24)                                   */
#define MCUCTRL_USBPHYRESET_RESERVED14_Msk (0x1000000UL)            /*!< RESERVED14 (Bitfield-Mask: 0x01)                      */
#define MCUCTRL_USBPHYRESET_RESERVED13_Pos (22UL)                   /*!< RESERVED13 (Bit 22)                                   */
#define MCUCTRL_USBPHYRESET_RESERVED13_Msk (0xc00000UL)             /*!< RESERVED13 (Bitfield-Mask: 0x03)                      */
#define MCUCTRL_USBPHYRESET_RESERVED12_Pos (21UL)                   /*!< RESERVED12 (Bit 21)                                   */
#define MCUCTRL_USBPHYRESET_RESERVED12_Msk (0x200000UL)             /*!< RESERVED12 (Bitfield-Mask: 0x01)                      */
#define MCUCTRL_USBPHYRESET_RESERVED11_Pos (18UL)                   /*!< RESERVED11 (Bit 18)                                   */
#define MCUCTRL_USBPHYRESET_RESERVED11_Msk (0x1c0000UL)             /*!< RESERVED11 (Bitfield-Mask: 0x07)                      */
#define MCUCTRL_USBPHYRESET_RESERVED10_Pos (17UL)                   /*!< RESERVED10 (Bit 17)                                   */
#define MCUCTRL_USBPHYRESET_RESERVED10_Msk (0x20000UL)              /*!< RESERVED10 (Bitfield-Mask: 0x01)                      */
#define MCUCTRL_USBPHYRESET_RESERVED09_Pos (16UL)                   /*!< RESERVED09 (Bit 16)                                   */
#define MCUCTRL_USBPHYRESET_RESERVED09_Msk (0x10000UL)              /*!< RESERVED09 (Bitfield-Mask: 0x01)                      */
#define MCUCTRL_USBPHYRESET_RESERVED07_Pos (12UL)                   /*!< RESERVED07 (Bit 12)                                   */
#define MCUCTRL_USBPHYRESET_RESERVED07_Msk (0x7000UL)               /*!< RESERVED07 (Bitfield-Mask: 0x07)                      */
#define MCUCTRL_USBPHYRESET_RESERVED06_Pos (11UL)                   /*!< RESERVED06 (Bit 11)                                   */
#define MCUCTRL_USBPHYRESET_RESERVED06_Msk (0x800UL)                /*!< RESERVED06 (Bitfield-Mask: 0x01)                      */
#define MCUCTRL_USBPHYRESET_RESERVED05_Pos (9UL)                    /*!< RESERVED05 (Bit 9)                                    */
#define MCUCTRL_USBPHYRESET_RESERVED05_Msk (0x600UL)                /*!< RESERVED05 (Bitfield-Mask: 0x03)                      */
#define MCUCTRL_USBPHYRESET_RESERVED04_Pos (8UL)                    /*!< RESERVED04 (Bit 8)                                    */
#define MCUCTRL_USBPHYRESET_RESERVED04_Msk (0x100UL)                /*!< RESERVED04 (Bitfield-Mask: 0x01)                      */
#define MCUCTRL_USBPHYRESET_RESERVED03_Pos (6UL)                    /*!< RESERVED03 (Bit 6)                                    */
#define MCUCTRL_USBPHYRESET_RESERVED03_Msk (0xc0UL)                 /*!< RESERVED03 (Bitfield-Mask: 0x03)                      */
#define MCUCTRL_USBPHYRESET_RESERVED02_Pos (5UL)                    /*!< RESERVED02 (Bit 5)                                    */
#define MCUCTRL_USBPHYRESET_RESERVED02_Msk (0x20UL)                 /*!< RESERVED02 (Bitfield-Mask: 0x01)                      */
#define MCUCTRL_USBPHYRESET_RESERVED01_Pos (2UL)                    /*!< RESERVED01 (Bit 2)                                    */
#define MCUCTRL_USBPHYRESET_RESERVED01_Msk (0x1cUL)                 /*!< RESERVED01 (Bitfield-Mask: 0x07)                      */
#define MCUCTRL_USBPHYRESET_USBPHYUTMIRSTDIS_Pos (1UL)              /*!< USBPHYUTMIRSTDIS (Bit 1)                              */
#define MCUCTRL_USBPHYRESET_USBPHYUTMIRSTDIS_Msk (0x2UL)            /*!< USBPHYUTMIRSTDIS (Bitfield-Mask: 0x01)                */
#define MCUCTRL_USBPHYRESET_USBPHYPORRSTDIS_Pos (0UL)               /*!< USBPHYPORRSTDIS (Bit 0)                               */
#define MCUCTRL_USBPHYRESET_USBPHYPORRSTDIS_Msk (0x1UL)             /*!< USBPHYPORRSTDIS (Bitfield-Mask: 0x01)                 */
/* =====================================================  AUDADCPWRCTRL  ===================================================== */
#define MCUCTRL_AUDADCPWRCTRL_AUDADCKEEPOUTEN_Pos (18UL)            /*!< AUDADCKEEPOUTEN (Bit 18)                              */
#define MCUCTRL_AUDADCPWRCTRL_AUDADCKEEPOUTEN_Msk (0x40000UL)       /*!< AUDADCKEEPOUTEN (Bitfield-Mask: 0x01)                 */
#define MCUCTRL_AUDADCPWRCTRL_AUDADCRFBUFSLWEN_Pos (17UL)           /*!< AUDADCRFBUFSLWEN (Bit 17)                             */
#define MCUCTRL_AUDADCPWRCTRL_AUDADCRFBUFSLWEN_Msk (0x20000UL)      /*!< AUDADCRFBUFSLWEN (Bitfield-Mask: 0x01)                */
#define MCUCTRL_AUDADCPWRCTRL_AUDADCINBUFEN_Pos (16UL)              /*!< AUDADCINBUFEN (Bit 16)                                */
#define MCUCTRL_AUDADCPWRCTRL_AUDADCINBUFEN_Msk (0x10000UL)         /*!< AUDADCINBUFEN (Bitfield-Mask: 0x01)                   */
#define MCUCTRL_AUDADCPWRCTRL_AUDADCINBUFSEL_Pos (14UL)             /*!< AUDADCINBUFSEL (Bit 14)                               */
#define MCUCTRL_AUDADCPWRCTRL_AUDADCINBUFSEL_Msk (0xc000UL)         /*!< AUDADCINBUFSEL (Bitfield-Mask: 0x03)                  */
#define MCUCTRL_AUDADCPWRCTRL_AUDADCVBATDIVEN_Pos (12UL)            /*!< AUDADCVBATDIVEN (Bit 12)                              */
#define MCUCTRL_AUDADCPWRCTRL_AUDADCVBATDIVEN_Msk (0x1000UL)        /*!< AUDADCVBATDIVEN (Bitfield-Mask: 0x01)                 */
#define MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN_Pos (10UL)            /*!< VDDAUDADCRESETN (Bit 10)                              */
#define MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN_Msk (0x400UL)         /*!< VDDAUDADCRESETN (Bitfield-Mask: 0x01)                 */
#define MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE_Pos (9UL)         /*!< VDDAUDADCDIGISOLATE (Bit 9)                           */
#define MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE_Msk (0x200UL)     /*!< VDDAUDADCDIGISOLATE (Bitfield-Mask: 0x01)             */
#define MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE_Pos (8UL)         /*!< VDDAUDADCSARISOLATE (Bit 8)                           */
#define MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE_Msk (0x100UL)     /*!< VDDAUDADCSARISOLATE (Bitfield-Mask: 0x01)             */
#define MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN_Pos (5UL)               /*!< AUDREFKEEPPEN (Bit 5)                                 */
#define MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN_Msk (0x20UL)            /*!< AUDREFKEEPPEN (Bitfield-Mask: 0x01)                   */
#define MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN_Pos (4UL)                /*!< AUDREFBUFPEN (Bit 4)                                  */
#define MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN_Msk (0x10UL)             /*!< AUDREFBUFPEN (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN_Pos (3UL)                   /*!< AUDBGTPEN (Bit 3)                                     */
#define MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN_Msk (0x8UL)                 /*!< AUDBGTPEN (Bitfield-Mask: 0x01)                       */
#define MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN_Pos (2UL)                 /*!< AUDADCBPSEN (Bit 2)                                   */
#define MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN_Msk (0x4UL)               /*!< AUDADCBPSEN (Bitfield-Mask: 0x01)                     */
#define MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN_Pos (1UL)                 /*!< AUDADCAPSEN (Bit 1)                                   */
#define MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN_Msk (0x2UL)               /*!< AUDADCAPSEN (Bitfield-Mask: 0x01)                     */
#define MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE_Pos (0UL)            /*!< AUDADCPWRCTRLSWE (Bit 0)                              */
#define MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE_Msk (0x1UL)          /*!< AUDADCPWRCTRLSWE (Bitfield-Mask: 0x01)                */
/* ========================================================  AUDIO1  ========================================================= */
#define MCUCTRL_AUDIO1_MICBIASPDNB_Pos    (12UL)                    /*!< MICBIASPDNB (Bit 12)                                  */
#define MCUCTRL_AUDIO1_MICBIASPDNB_Msk    (0x1000UL)                /*!< MICBIASPDNB (Bitfield-Mask: 0x01)                     */
#define MCUCTRL_AUDIO1_MICBIASVOLTAGETRIM_Pos (6UL)                 /*!< MICBIASVOLTAGETRIM (Bit 6)                            */
#define MCUCTRL_AUDIO1_MICBIASVOLTAGETRIM_Msk (0xfc0UL)             /*!< MICBIASVOLTAGETRIM (Bitfield-Mask: 0x3f)              */
/* =====================================================  PGAADCIFCTRL  ====================================================== */
#define MCUCTRL_PGAADCIFCTRL_PGAADCIFVCOMPSEL_Pos (13UL)            /*!< PGAADCIFVCOMPSEL (Bit 13)                             */
#define MCUCTRL_PGAADCIFCTRL_PGAADCIFVCOMPSEL_Msk (0x6000UL)        /*!< PGAADCIFVCOMPSEL (Bitfield-Mask: 0x03)                */
#define MCUCTRL_PGAADCIFCTRL_PGAADCIFVCOMPEN_Pos (12UL)             /*!< PGAADCIFVCOMPEN (Bit 12)                              */
#define MCUCTRL_PGAADCIFCTRL_PGAADCIFVCOMPEN_Msk (0x1000UL)         /*!< PGAADCIFVCOMPEN (Bitfield-Mask: 0x01)                 */
#define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHBPDNB_Pos (6UL)              /*!< PGAADCIFCHBPDNB (Bit 6)                               */
#define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHBPDNB_Msk (0xc0UL)           /*!< PGAADCIFCHBPDNB (Bitfield-Mask: 0x03)                 */
#define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHBACTIVE_Pos (4UL)            /*!< PGAADCIFCHBACTIVE (Bit 4)                             */
#define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHBACTIVE_Msk (0x30UL)         /*!< PGAADCIFCHBACTIVE (Bitfield-Mask: 0x03)               */
#define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHAPDNB_Pos (2UL)              /*!< PGAADCIFCHAPDNB (Bit 2)                               */
#define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHAPDNB_Msk (0xcUL)            /*!< PGAADCIFCHAPDNB (Bitfield-Mask: 0x03)                 */
#define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHAACTIVE_Pos (0UL)            /*!< PGAADCIFCHAACTIVE (Bit 0)                             */
#define MCUCTRL_PGAADCIFCTRL_PGAADCIFCHAACTIVE_Msk (0x3UL)          /*!< PGAADCIFCHAACTIVE (Bitfield-Mask: 0x03)               */
/* =======================================================  PGACTRL1  ======================================================== */
#define MCUCTRL_PGACTRL1_PGAGAINAOVRD_Pos (31UL)                    /*!< PGAGAINAOVRD (Bit 31)                                 */
#define MCUCTRL_PGACTRL1_PGAGAINAOVRD_Msk (0x80000000UL)            /*!< PGAGAINAOVRD (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_PGACTRL1_VCOMPSELPGA_Pos  (29UL)                    /*!< VCOMPSELPGA (Bit 29)                                  */
#define MCUCTRL_PGACTRL1_VCOMPSELPGA_Msk  (0x20000000UL)            /*!< VCOMPSELPGA (Bitfield-Mask: 0x01)                     */
#define MCUCTRL_PGACTRL1_PGAVREFGENQUICKSTARTEN_Pos (28UL)          /*!< PGAVREFGENQUICKSTARTEN (Bit 28)                       */
#define MCUCTRL_PGACTRL1_PGAVREFGENQUICKSTARTEN_Msk (0x10000000UL)  /*!< PGAVREFGENQUICKSTARTEN (Bitfield-Mask: 0x01)          */
#define MCUCTRL_PGACTRL1_PGAVREFGENPDNB_Pos (27UL)                  /*!< PGAVREFGENPDNB (Bit 27)                               */
#define MCUCTRL_PGACTRL1_PGAVREFGENPDNB_Msk (0x8000000UL)           /*!< PGAVREFGENPDNB (Bitfield-Mask: 0x01)                  */
#define MCUCTRL_PGACTRL1_PGAIREFGENPDNB_Pos (26UL)                  /*!< PGAIREFGENPDNB (Bit 26)                               */
#define MCUCTRL_PGACTRL1_PGAIREFGENPDNB_Msk (0x4000000UL)           /*!< PGAIREFGENPDNB (Bitfield-Mask: 0x01)                  */
#define MCUCTRL_PGACTRL1_PGACHAVCMGENQCHARGEEN_Pos (25UL)           /*!< PGACHAVCMGENQCHARGEEN (Bit 25)                        */
#define MCUCTRL_PGACTRL1_PGACHAVCMGENQCHARGEEN_Msk (0x2000000UL)    /*!< PGACHAVCMGENQCHARGEEN (Bitfield-Mask: 0x01)           */
#define MCUCTRL_PGACTRL1_PGACHAVCMGENPDNB_Pos (24UL)                /*!< PGACHAVCMGENPDNB (Bit 24)                             */
#define MCUCTRL_PGACTRL1_PGACHAVCMGENPDNB_Msk (0x1000000UL)         /*!< PGACHAVCMGENPDNB (Bitfield-Mask: 0x01)                */
#define MCUCTRL_PGACTRL1_PGACHAOPAMPOUTPDNB_Pos (22UL)              /*!< PGACHAOPAMPOUTPDNB (Bit 22)                           */
#define MCUCTRL_PGACTRL1_PGACHAOPAMPOUTPDNB_Msk (0xc00000UL)        /*!< PGACHAOPAMPOUTPDNB (Bitfield-Mask: 0x03)              */
#define MCUCTRL_PGACTRL1_PGACHAOPAMPINPDNB_Pos (20UL)               /*!< PGACHAOPAMPINPDNB (Bit 20)                            */
#define MCUCTRL_PGACTRL1_PGACHAOPAMPINPDNB_Msk (0x300000UL)         /*!< PGACHAOPAMPINPDNB (Bitfield-Mask: 0x03)               */
#define MCUCTRL_PGACTRL1_PGACHABYPASSEN_Pos (18UL)                  /*!< PGACHABYPASSEN (Bit 18)                               */
#define MCUCTRL_PGACTRL1_PGACHABYPASSEN_Msk (0xc0000UL)             /*!< PGACHABYPASSEN (Bitfield-Mask: 0x03)                  */
#define MCUCTRL_PGACTRL1_PGACHA1GAIN2SEL_Pos (13UL)                 /*!< PGACHA1GAIN2SEL (Bit 13)                              */
#define MCUCTRL_PGACTRL1_PGACHA1GAIN2SEL_Msk (0x3e000UL)            /*!< PGACHA1GAIN2SEL (Bitfield-Mask: 0x1f)                 */
#define MCUCTRL_PGACTRL1_PGACHA1GAIN2DIV2SEL_Pos (12UL)             /*!< PGACHA1GAIN2DIV2SEL (Bit 12)                          */
#define MCUCTRL_PGACTRL1_PGACHA1GAIN2DIV2SEL_Msk (0x1000UL)         /*!< PGACHA1GAIN2DIV2SEL (Bitfield-Mask: 0x01)             */
#define MCUCTRL_PGACTRL1_PGACHA1GAIN1SEL_Pos (9UL)                  /*!< PGACHA1GAIN1SEL (Bit 9)                               */
#define MCUCTRL_PGACTRL1_PGACHA1GAIN1SEL_Msk (0xe00UL)              /*!< PGACHA1GAIN1SEL (Bitfield-Mask: 0x07)                 */
#define MCUCTRL_PGACTRL1_PGACHA0GAIN2SEL_Pos (4UL)                  /*!< PGACHA0GAIN2SEL (Bit 4)                               */
#define MCUCTRL_PGACTRL1_PGACHA0GAIN2SEL_Msk (0x1f0UL)              /*!< PGACHA0GAIN2SEL (Bitfield-Mask: 0x1f)                 */
#define MCUCTRL_PGACTRL1_PGACHA0GAIN2DIV2SEL_Pos (3UL)              /*!< PGACHA0GAIN2DIV2SEL (Bit 3)                           */
#define MCUCTRL_PGACTRL1_PGACHA0GAIN2DIV2SEL_Msk (0x8UL)            /*!< PGACHA0GAIN2DIV2SEL (Bitfield-Mask: 0x01)             */
#define MCUCTRL_PGACTRL1_PGACHA0GAIN1SEL_Pos (0UL)                  /*!< PGACHA0GAIN1SEL (Bit 0)                               */
#define MCUCTRL_PGACTRL1_PGACHA0GAIN1SEL_Msk (0x7UL)                /*!< PGACHA0GAIN1SEL (Bitfield-Mask: 0x07)                 */
/* =======================================================  PGACTRL2  ======================================================== */
#define MCUCTRL_PGACTRL2_PGAGAINBOVRD_Pos (31UL)                    /*!< PGAGAINBOVRD (Bit 31)                                 */
#define MCUCTRL_PGACTRL2_PGAGAINBOVRD_Msk (0x80000000UL)            /*!< PGAGAINBOVRD (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_PGACTRL2_PGACHBVCMGENQCHARGEEN_Pos (25UL)           /*!< PGACHBVCMGENQCHARGEEN (Bit 25)                        */
#define MCUCTRL_PGACTRL2_PGACHBVCMGENQCHARGEEN_Msk (0x2000000UL)    /*!< PGACHBVCMGENQCHARGEEN (Bitfield-Mask: 0x01)           */
#define MCUCTRL_PGACTRL2_PGACHBVCMGENPDNB_Pos (24UL)                /*!< PGACHBVCMGENPDNB (Bit 24)                             */
#define MCUCTRL_PGACTRL2_PGACHBVCMGENPDNB_Msk (0x1000000UL)         /*!< PGACHBVCMGENPDNB (Bitfield-Mask: 0x01)                */
#define MCUCTRL_PGACTRL2_PGACHBOPAMPOUTPDNB_Pos (22UL)              /*!< PGACHBOPAMPOUTPDNB (Bit 22)                           */
#define MCUCTRL_PGACTRL2_PGACHBOPAMPOUTPDNB_Msk (0xc00000UL)        /*!< PGACHBOPAMPOUTPDNB (Bitfield-Mask: 0x03)              */
#define MCUCTRL_PGACTRL2_PGACHBOPAMPINPDNB_Pos (20UL)               /*!< PGACHBOPAMPINPDNB (Bit 20)                            */
#define MCUCTRL_PGACTRL2_PGACHBOPAMPINPDNB_Msk (0x300000UL)         /*!< PGACHBOPAMPINPDNB (Bitfield-Mask: 0x03)               */
#define MCUCTRL_PGACTRL2_PGACHBBYPASSEN_Pos (18UL)                  /*!< PGACHBBYPASSEN (Bit 18)                               */
#define MCUCTRL_PGACTRL2_PGACHBBYPASSEN_Msk (0xc0000UL)             /*!< PGACHBBYPASSEN (Bitfield-Mask: 0x03)                  */
#define MCUCTRL_PGACTRL2_PGACHB1GAIN2SEL_Pos (13UL)                 /*!< PGACHB1GAIN2SEL (Bit 13)                              */
#define MCUCTRL_PGACTRL2_PGACHB1GAIN2SEL_Msk (0x3e000UL)            /*!< PGACHB1GAIN2SEL (Bitfield-Mask: 0x1f)                 */
#define MCUCTRL_PGACTRL2_PGACHB1GAIN2DIV2SEL_Pos (12UL)             /*!< PGACHB1GAIN2DIV2SEL (Bit 12)                          */
#define MCUCTRL_PGACTRL2_PGACHB1GAIN2DIV2SEL_Msk (0x1000UL)         /*!< PGACHB1GAIN2DIV2SEL (Bitfield-Mask: 0x01)             */
#define MCUCTRL_PGACTRL2_PGACHB1GAIN1SEL_Pos (9UL)                  /*!< PGACHB1GAIN1SEL (Bit 9)                               */
#define MCUCTRL_PGACTRL2_PGACHB1GAIN1SEL_Msk (0xe00UL)              /*!< PGACHB1GAIN1SEL (Bitfield-Mask: 0x07)                 */
#define MCUCTRL_PGACTRL2_PGACHB0GAIN2SEL_Pos (4UL)                  /*!< PGACHB0GAIN2SEL (Bit 4)                               */
#define MCUCTRL_PGACTRL2_PGACHB0GAIN2SEL_Msk (0x1f0UL)              /*!< PGACHB0GAIN2SEL (Bitfield-Mask: 0x1f)                 */
#define MCUCTRL_PGACTRL2_PGACHB0GAIN2DIV2SEL_Pos (3UL)              /*!< PGACHB0GAIN2DIV2SEL (Bit 3)                           */
#define MCUCTRL_PGACTRL2_PGACHB0GAIN2DIV2SEL_Msk (0x8UL)            /*!< PGACHB0GAIN2DIV2SEL (Bitfield-Mask: 0x01)             */
#define MCUCTRL_PGACTRL2_PGACHB0GAIN1SEL_Pos (0UL)                  /*!< PGACHB0GAIN1SEL (Bit 0)                               */
#define MCUCTRL_PGACTRL2_PGACHB0GAIN1SEL_Msk (0x7UL)                /*!< PGACHB0GAIN1SEL (Bitfield-Mask: 0x07)                 */
/* =====================================================  AUDADCPWRDLY  ====================================================== */
#define MCUCTRL_AUDADCPWRDLY_AUDADCPWR1_Pos (8UL)                   /*!< AUDADCPWR1 (Bit 8)                                    */
#define MCUCTRL_AUDADCPWRDLY_AUDADCPWR1_Msk (0xff00UL)              /*!< AUDADCPWR1 (Bitfield-Mask: 0xff)                      */
#define MCUCTRL_AUDADCPWRDLY_AUDADCPWR0_Pos (0UL)                   /*!< AUDADCPWR0 (Bit 0)                                    */
#define MCUCTRL_AUDADCPWRDLY_AUDADCPWR0_Msk (0xffUL)                /*!< AUDADCPWR0 (Bitfield-Mask: 0xff)                      */
/* =======================================================  SDIOCTRL  ======================================================== */
#define MCUCTRL_SDIOCTRL_SDIODATOPENDRAINEN_Pos (18UL)              /*!< SDIODATOPENDRAINEN (Bit 18)                           */
#define MCUCTRL_SDIOCTRL_SDIODATOPENDRAINEN_Msk (0x40000UL)         /*!< SDIODATOPENDRAINEN (Bitfield-Mask: 0x01)              */
#define MCUCTRL_SDIOCTRL_SDIOCMDOPENDRAINEN_Pos (17UL)              /*!< SDIOCMDOPENDRAINEN (Bit 17)                           */
#define MCUCTRL_SDIOCTRL_SDIOCMDOPENDRAINEN_Msk (0x20000UL)         /*!< SDIOCMDOPENDRAINEN (Bitfield-Mask: 0x01)              */
#define MCUCTRL_SDIOCTRL_SDIOXINCLKSEL_Pos (15UL)                   /*!< SDIOXINCLKSEL (Bit 15)                                */
#define MCUCTRL_SDIOCTRL_SDIOXINCLKSEL_Msk (0x18000UL)              /*!< SDIOXINCLKSEL (Bitfield-Mask: 0x03)                   */
#define MCUCTRL_SDIOCTRL_SDIOASYNCWKUPENA_Pos (14UL)                /*!< SDIOASYNCWKUPENA (Bit 14)                             */
#define MCUCTRL_SDIOCTRL_SDIOASYNCWKUPENA_Msk (0x4000UL)            /*!< SDIOASYNCWKUPENA (Bitfield-Mask: 0x01)                */
#define MCUCTRL_SDIOCTRL_SDIOOTAPDLYSEL_Pos (10UL)                  /*!< SDIOOTAPDLYSEL (Bit 10)                               */
#define MCUCTRL_SDIOCTRL_SDIOOTAPDLYSEL_Msk (0x3c00UL)              /*!< SDIOOTAPDLYSEL (Bitfield-Mask: 0x0f)                  */
#define MCUCTRL_SDIOCTRL_SDIOOTAPDLYENA_Pos (9UL)                   /*!< SDIOOTAPDLYENA (Bit 9)                                */
#define MCUCTRL_SDIOCTRL_SDIOOTAPDLYENA_Msk (0x200UL)               /*!< SDIOOTAPDLYENA (Bitfield-Mask: 0x01)                  */
#define MCUCTRL_SDIOCTRL_SDIOITAPDLYSEL_Pos (4UL)                   /*!< SDIOITAPDLYSEL (Bit 4)                                */
#define MCUCTRL_SDIOCTRL_SDIOITAPDLYSEL_Msk (0x1f0UL)               /*!< SDIOITAPDLYSEL (Bitfield-Mask: 0x1f)                  */
#define MCUCTRL_SDIOCTRL_SDIOITAPDLYENA_Pos (3UL)                   /*!< SDIOITAPDLYENA (Bit 3)                                */
#define MCUCTRL_SDIOCTRL_SDIOITAPDLYENA_Msk (0x8UL)                 /*!< SDIOITAPDLYENA (Bitfield-Mask: 0x01)                  */
#define MCUCTRL_SDIOCTRL_SDIOITAPCHGWIN_Pos (2UL)                   /*!< SDIOITAPCHGWIN (Bit 2)                                */
#define MCUCTRL_SDIOCTRL_SDIOITAPCHGWIN_Msk (0x4UL)                 /*!< SDIOITAPCHGWIN (Bitfield-Mask: 0x01)                  */
#define MCUCTRL_SDIOCTRL_SDIOXINCLKEN_Pos (1UL)                     /*!< SDIOXINCLKEN (Bit 1)                                  */
#define MCUCTRL_SDIOCTRL_SDIOXINCLKEN_Msk (0x2UL)                   /*!< SDIOXINCLKEN (Bitfield-Mask: 0x01)                    */
#define MCUCTRL_SDIOCTRL_SDIOSYSCLKEN_Pos (0UL)                     /*!< SDIOSYSCLKEN (Bit 0)                                  */
#define MCUCTRL_SDIOCTRL_SDIOSYSCLKEN_Msk (0x1UL)                   /*!< SDIOSYSCLKEN (Bitfield-Mask: 0x01)                    */
/* ========================================================  PDMCTRL  ======================================================== */
#define MCUCTRL_PDMCTRL_PDMGLOBALEN_Pos   (0UL)                     /*!< PDMGLOBALEN (Bit 0)                                   */
#define MCUCTRL_PDMCTRL_PDMGLOBALEN_Msk   (0x1UL)                   /*!< PDMGLOBALEN (Bitfield-Mask: 0x01)                     */


/* =========================================================================================================================== */
/* ================                                           MSPI0                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
#define MSPI0_CTRL_XFERBYTES_Pos          (16UL)                    /*!< XFERBYTES (Bit 16)                                    */
#define MSPI0_CTRL_XFERBYTES_Msk          (0xffff0000UL)            /*!< XFERBYTES (Bitfield-Mask: 0xffff)                     */
#define MSPI0_CTRL_HALFWORDREVERSE_Pos    (13UL)                    /*!< HALFWORDREVERSE (Bit 13)                              */
#define MSPI0_CTRL_HALFWORDREVERSE_Msk    (0x2000UL)                /*!< HALFWORDREVERSE (Bitfield-Mask: 0x01)                 */
#define MSPI0_CTRL_ENWLAT_Pos             (12UL)                    /*!< ENWLAT (Bit 12)                                       */
#define MSPI0_CTRL_ENWLAT_Msk             (0x1000UL)                /*!< ENWLAT (Bitfield-Mask: 0x01)                          */
#define MSPI0_CTRL_ENDCX_Pos              (11UL)                    /*!< ENDCX (Bit 11)                                        */
#define MSPI0_CTRL_ENDCX_Msk              (0x800UL)                 /*!< ENDCX (Bitfield-Mask: 0x01)                           */
#define MSPI0_CTRL_ENTURN_Pos             (10UL)                    /*!< ENTURN (Bit 10)                                       */
#define MSPI0_CTRL_ENTURN_Msk             (0x400UL)                 /*!< ENTURN (Bitfield-Mask: 0x01)                          */
#define MSPI0_CTRL_PIOSCRAMBLE_Pos        (9UL)                     /*!< PIOSCRAMBLE (Bit 9)                                   */
#define MSPI0_CTRL_PIOSCRAMBLE_Msk        (0x200UL)                 /*!< PIOSCRAMBLE (Bitfield-Mask: 0x01)                     */
#define MSPI0_CTRL_BIGENDIAN_Pos          (8UL)                     /*!< BIGENDIAN (Bit 8)                                     */
#define MSPI0_CTRL_BIGENDIAN_Msk          (0x100UL)                 /*!< BIGENDIAN (Bitfield-Mask: 0x01)                       */
#define MSPI0_CTRL_TXRX_Pos               (7UL)                     /*!< TXRX (Bit 7)                                          */
#define MSPI0_CTRL_TXRX_Msk               (0x80UL)                  /*!< TXRX (Bitfield-Mask: 0x01)                            */
#define MSPI0_CTRL_SENDI_Pos              (6UL)                     /*!< SENDI (Bit 6)                                         */
#define MSPI0_CTRL_SENDI_Msk              (0x40UL)                  /*!< SENDI (Bitfield-Mask: 0x01)                           */
#define MSPI0_CTRL_SENDA_Pos              (5UL)                     /*!< SENDA (Bit 5)                                         */
#define MSPI0_CTRL_SENDA_Msk              (0x20UL)                  /*!< SENDA (Bitfield-Mask: 0x01)                           */
#define MSPI0_CTRL_PIODEV_Pos             (4UL)                     /*!< PIODEV (Bit 4)                                        */
#define MSPI0_CTRL_PIODEV_Msk             (0x10UL)                  /*!< PIODEV (Bitfield-Mask: 0x01)                          */
#define MSPI0_CTRL_BUSY_Pos               (2UL)                     /*!< BUSY (Bit 2)                                          */
#define MSPI0_CTRL_BUSY_Msk               (0x4UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
#define MSPI0_CTRL_STATUS_Pos             (1UL)                     /*!< STATUS (Bit 1)                                        */
#define MSPI0_CTRL_STATUS_Msk             (0x2UL)                   /*!< STATUS (Bitfield-Mask: 0x01)                          */
#define MSPI0_CTRL_START_Pos              (0UL)                     /*!< START (Bit 0)                                         */
#define MSPI0_CTRL_START_Msk              (0x1UL)                   /*!< START (Bitfield-Mask: 0x01)                           */
/* =========================================================  CTRL1  ========================================================= */
#define MSPI0_CTRL1_PIOMIXED_Pos          (0UL)                     /*!< PIOMIXED (Bit 0)                                      */
#define MSPI0_CTRL1_PIOMIXED_Msk          (0xfUL)                   /*!< PIOMIXED (Bitfield-Mask: 0x0f)                        */
/* =========================================================  ADDR  ========================================================== */
#define MSPI0_ADDR_ADDR_Pos               (0UL)                     /*!< ADDR (Bit 0)                                          */
#define MSPI0_ADDR_ADDR_Msk               (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  INSTR  ========================================================= */
#define MSPI0_INSTR_INSTR_Pos             (0UL)                     /*!< INSTR (Bit 0)                                         */
#define MSPI0_INSTR_INSTR_Msk             (0xffffUL)                /*!< INSTR (Bitfield-Mask: 0xffff)                         */
/* ========================================================  TXFIFO  ========================================================= */
#define MSPI0_TXFIFO_TXFIFO_Pos           (0UL)                     /*!< TXFIFO (Bit 0)                                        */
#define MSPI0_TXFIFO_TXFIFO_Msk           (0xffffffffUL)            /*!< TXFIFO (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  RXFIFO  ========================================================= */
#define MSPI0_RXFIFO_RXFIFO_Pos           (0UL)                     /*!< RXFIFO (Bit 0)                                        */
#define MSPI0_RXFIFO_RXFIFO_Msk           (0xffffffffUL)            /*!< RXFIFO (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  TXENTRIES  ======================================================= */
#define MSPI0_TXENTRIES_TXENTRIES_Pos     (0UL)                     /*!< TXENTRIES (Bit 0)                                     */
#define MSPI0_TXENTRIES_TXENTRIES_Msk     (0x3fUL)                  /*!< TXENTRIES (Bitfield-Mask: 0x3f)                       */
/* =======================================================  RXENTRIES  ======================================================= */
#define MSPI0_RXENTRIES_RXENTRIES_Pos     (0UL)                     /*!< RXENTRIES (Bit 0)                                     */
#define MSPI0_RXENTRIES_RXENTRIES_Msk     (0x3fUL)                  /*!< RXENTRIES (Bitfield-Mask: 0x3f)                       */
/* =======================================================  THRESHOLD  ======================================================= */
#define MSPI0_THRESHOLD_RXTHRESH_Pos      (8UL)                     /*!< RXTHRESH (Bit 8)                                      */
#define MSPI0_THRESHOLD_RXTHRESH_Msk      (0x3f00UL)                /*!< RXTHRESH (Bitfield-Mask: 0x3f)                        */
#define MSPI0_THRESHOLD_TXTHRESH_Pos      (0UL)                     /*!< TXTHRESH (Bit 0)                                      */
#define MSPI0_THRESHOLD_TXTHRESH_Msk      (0x3fUL)                  /*!< TXTHRESH (Bitfield-Mask: 0x3f)                        */
/* ========================================================  MSPICFG  ======================================================== */
#define MSPI0_MSPICFG_PRSTN_Pos           (31UL)                    /*!< PRSTN (Bit 31)                                        */
#define MSPI0_MSPICFG_PRSTN_Msk           (0x80000000UL)            /*!< PRSTN (Bitfield-Mask: 0x01)                           */
#define MSPI0_MSPICFG_IPRSTN_Pos          (30UL)                    /*!< IPRSTN (Bit 30)                                       */
#define MSPI0_MSPICFG_IPRSTN_Msk          (0x40000000UL)            /*!< IPRSTN (Bitfield-Mask: 0x01)                          */
#define MSPI0_MSPICFG_FIFORESET_Pos       (29UL)                    /*!< FIFORESET (Bit 29)                                    */
#define MSPI0_MSPICFG_FIFORESET_Msk       (0x20000000UL)            /*!< FIFORESET (Bitfield-Mask: 0x01)                       */
#define MSPI0_MSPICFG_IOMSEL_Pos          (4UL)                     /*!< IOMSEL (Bit 4)                                        */
#define MSPI0_MSPICFG_IOMSEL_Msk          (0xf0UL)                  /*!< IOMSEL (Bitfield-Mask: 0x0f)                          */
#define MSPI0_MSPICFG_APBCLK_Pos          (0UL)                     /*!< APBCLK (Bit 0)                                        */
#define MSPI0_MSPICFG_APBCLK_Msk          (0x1UL)                   /*!< APBCLK (Bitfield-Mask: 0x01)                          */
/* =======================================================  PADOUTEN  ======================================================== */
#define MSPI0_PADOUTEN_CLKOND4_Pos        (31UL)                    /*!< CLKOND4 (Bit 31)                                      */
#define MSPI0_PADOUTEN_CLKOND4_Msk        (0x80000000UL)            /*!< CLKOND4 (Bitfield-Mask: 0x01)                         */
#define MSPI0_PADOUTEN_PADSET1_Pos        (30UL)                    /*!< PADSET1 (Bit 30)                                      */
#define MSPI0_PADOUTEN_PADSET1_Msk        (0x40000000UL)            /*!< PADSET1 (Bitfield-Mask: 0x01)                         */
#define MSPI0_PADOUTEN_OUTEN_Pos          (0UL)                     /*!< OUTEN (Bit 0)                                         */
#define MSPI0_PADOUTEN_OUTEN_Msk          (0xfffffUL)               /*!< OUTEN (Bitfield-Mask: 0xfffff)                        */
/* =======================================================  PADOVEREN  ======================================================= */
#define MSPI0_PADOVEREN_OVERRIDEEN_Pos    (0UL)                     /*!< OVERRIDEEN (Bit 0)                                    */
#define MSPI0_PADOVEREN_OVERRIDEEN_Msk    (0xfffffUL)               /*!< OVERRIDEEN (Bitfield-Mask: 0xfffff)                   */
/* ========================================================  PADOVER  ======================================================== */
#define MSPI0_PADOVER_OVERRIDE_Pos        (0UL)                     /*!< OVERRIDE (Bit 0)                                      */
#define MSPI0_PADOVER_OVERRIDE_Msk        (0xfffffUL)               /*!< OVERRIDE (Bitfield-Mask: 0xfffff)                     */
/* ========================================================  DEV0AXI  ======================================================== */
#define MSPI0_DEV0AXI_BASE0_Pos           (16UL)                    /*!< BASE0 (Bit 16)                                        */
#define MSPI0_DEV0AXI_BASE0_Msk           (0x3ff0000UL)             /*!< BASE0 (Bitfield-Mask: 0x3ff)                          */
#define MSPI0_DEV0AXI_READONLY0_Pos       (4UL)                     /*!< READONLY0 (Bit 4)                                     */
#define MSPI0_DEV0AXI_READONLY0_Msk       (0x10UL)                  /*!< READONLY0 (Bitfield-Mask: 0x01)                       */
#define MSPI0_DEV0AXI_SIZE0_Pos           (0UL)                     /*!< SIZE0 (Bit 0)                                         */
#define MSPI0_DEV0AXI_SIZE0_Msk           (0xfUL)                   /*!< SIZE0 (Bitfield-Mask: 0x0f)                           */
/* ========================================================  DEV0CFG  ======================================================== */
#define MSPI0_DEV0CFG_WRITELATENCY0_Pos   (26UL)                    /*!< WRITELATENCY0 (Bit 26)                                */
#define MSPI0_DEV0CFG_WRITELATENCY0_Msk   (0xfc000000UL)            /*!< WRITELATENCY0 (Bitfield-Mask: 0x3f)                   */
#define MSPI0_DEV0CFG_SEPIO0_Pos          (25UL)                    /*!< SEPIO0 (Bit 25)                                       */
#define MSPI0_DEV0CFG_SEPIO0_Msk          (0x2000000UL)             /*!< SEPIO0 (Bitfield-Mask: 0x01)                          */
#define MSPI0_DEV0CFG_TXNEG0_Pos          (24UL)                    /*!< TXNEG0 (Bit 24)                                       */
#define MSPI0_DEV0CFG_TXNEG0_Msk          (0x1000000UL)             /*!< TXNEG0 (Bitfield-Mask: 0x01)                          */
#define MSPI0_DEV0CFG_RXNEG0_Pos          (23UL)                    /*!< RXNEG0 (Bit 23)                                       */
#define MSPI0_DEV0CFG_RXNEG0_Msk          (0x800000UL)              /*!< RXNEG0 (Bitfield-Mask: 0x01)                          */
#define MSPI0_DEV0CFG_RXCAP0_Pos          (22UL)                    /*!< RXCAP0 (Bit 22)                                       */
#define MSPI0_DEV0CFG_RXCAP0_Msk          (0x400000UL)              /*!< RXCAP0 (Bitfield-Mask: 0x01)                          */
#define MSPI0_DEV0CFG_CLKDIV0_Pos         (16UL)                    /*!< CLKDIV0 (Bit 16)                                      */
#define MSPI0_DEV0CFG_CLKDIV0_Msk         (0x3f0000UL)              /*!< CLKDIV0 (Bitfield-Mask: 0x3f)                         */
#define MSPI0_DEV0CFG_CPOL0_Pos           (15UL)                    /*!< CPOL0 (Bit 15)                                        */
#define MSPI0_DEV0CFG_CPOL0_Msk           (0x8000UL)                /*!< CPOL0 (Bitfield-Mask: 0x01)                           */
#define MSPI0_DEV0CFG_CPHA0_Pos           (14UL)                    /*!< CPHA0 (Bit 14)                                        */
#define MSPI0_DEV0CFG_CPHA0_Msk           (0x4000UL)                /*!< CPHA0 (Bitfield-Mask: 0x01)                           */
#define MSPI0_DEV0CFG_TURNAROUND0_Pos     (8UL)                     /*!< TURNAROUND0 (Bit 8)                                   */
#define MSPI0_DEV0CFG_TURNAROUND0_Msk     (0x3f00UL)                /*!< TURNAROUND0 (Bitfield-Mask: 0x3f)                     */
#define MSPI0_DEV0CFG_ISIZE0_Pos          (7UL)                     /*!< ISIZE0 (Bit 7)                                        */
#define MSPI0_DEV0CFG_ISIZE0_Msk          (0x80UL)                  /*!< ISIZE0 (Bitfield-Mask: 0x01)                          */
#define MSPI0_DEV0CFG_ASIZE0_Pos          (5UL)                     /*!< ASIZE0 (Bit 5)                                        */
#define MSPI0_DEV0CFG_ASIZE0_Msk          (0x60UL)                  /*!< ASIZE0 (Bitfield-Mask: 0x03)                          */
#define MSPI0_DEV0CFG_DEVCFG0_Pos         (0UL)                     /*!< DEVCFG0 (Bit 0)                                       */
#define MSPI0_DEV0CFG_DEVCFG0_Msk         (0x1fUL)                  /*!< DEVCFG0 (Bitfield-Mask: 0x1f)                         */
/* ========================================================  DEV0DDR  ======================================================== */
#define MSPI0_DEV0DDR_RXDQSDELAYHIEN0_Pos (31UL)                    /*!< RXDQSDELAYHIEN0 (Bit 31)                              */
#define MSPI0_DEV0DDR_RXDQSDELAYHIEN0_Msk (0x80000000UL)            /*!< RXDQSDELAYHIEN0 (Bitfield-Mask: 0x01)                 */
#define MSPI0_DEV0DDR_RXDQSDELAYNEGHI0_Pos (26UL)                   /*!< RXDQSDELAYNEGHI0 (Bit 26)                             */
#define MSPI0_DEV0DDR_RXDQSDELAYNEGHI0_Msk (0x7c000000UL)           /*!< RXDQSDELAYNEGHI0 (Bitfield-Mask: 0x1f)                */
#define MSPI0_DEV0DDR_RXDQSDELAYHI0_Pos   (21UL)                    /*!< RXDQSDELAYHI0 (Bit 21)                                */
#define MSPI0_DEV0DDR_RXDQSDELAYHI0_Msk   (0x3e00000UL)             /*!< RXDQSDELAYHI0 (Bitfield-Mask: 0x1f)                   */
#define MSPI0_DEV0DDR_RXDQSDELAYNEGEN0_Pos (20UL)                   /*!< RXDQSDELAYNEGEN0 (Bit 20)                             */
#define MSPI0_DEV0DDR_RXDQSDELAYNEGEN0_Msk (0x100000UL)             /*!< RXDQSDELAYNEGEN0 (Bitfield-Mask: 0x01)                */
#define MSPI0_DEV0DDR_RXDQSDELAYNEG0_Pos  (15UL)                    /*!< RXDQSDELAYNEG0 (Bit 15)                               */
#define MSPI0_DEV0DDR_RXDQSDELAYNEG0_Msk  (0xf8000UL)               /*!< RXDQSDELAYNEG0 (Bitfield-Mask: 0x1f)                  */
#define MSPI0_DEV0DDR_RXDQSDELAY0_Pos     (10UL)                    /*!< RXDQSDELAY0 (Bit 10)                                  */
#define MSPI0_DEV0DDR_RXDQSDELAY0_Msk     (0x7c00UL)                /*!< RXDQSDELAY0 (Bitfield-Mask: 0x1f)                     */
#define MSPI0_DEV0DDR_TXDQSDELAY0_Pos     (5UL)                     /*!< TXDQSDELAY0 (Bit 5)                                   */
#define MSPI0_DEV0DDR_TXDQSDELAY0_Msk     (0x3e0UL)                 /*!< TXDQSDELAY0 (Bitfield-Mask: 0x1f)                     */
#define MSPI0_DEV0DDR_ENABLEFINEDELAY0_Pos (4UL)                    /*!< ENABLEFINEDELAY0 (Bit 4)                              */
#define MSPI0_DEV0DDR_ENABLEFINEDELAY0_Msk (0x10UL)                 /*!< ENABLEFINEDELAY0 (Bitfield-Mask: 0x01)                */
#define MSPI0_DEV0DDR_DQSSYNCNEG0_Pos     (3UL)                     /*!< DQSSYNCNEG0 (Bit 3)                                   */
#define MSPI0_DEV0DDR_DQSSYNCNEG0_Msk     (0x8UL)                   /*!< DQSSYNCNEG0 (Bitfield-Mask: 0x01)                     */
#define MSPI0_DEV0DDR_ENABLEDQS0_Pos      (2UL)                     /*!< ENABLEDQS0 (Bit 2)                                    */
#define MSPI0_DEV0DDR_ENABLEDQS0_Msk      (0x4UL)                   /*!< ENABLEDQS0 (Bitfield-Mask: 0x01)                      */
#define MSPI0_DEV0DDR_QUADDDR0_Pos        (1UL)                     /*!< QUADDDR0 (Bit 1)                                      */
#define MSPI0_DEV0DDR_QUADDDR0_Msk        (0x2UL)                   /*!< QUADDDR0 (Bitfield-Mask: 0x01)                        */
#define MSPI0_DEV0DDR_EMULATEDDR0_Pos     (0UL)                     /*!< EMULATEDDR0 (Bit 0)                                   */
#define MSPI0_DEV0DDR_EMULATEDDR0_Msk     (0x1UL)                   /*!< EMULATEDDR0 (Bitfield-Mask: 0x01)                     */
/* =======================================================  DEV0CFG1  ======================================================== */
#define MSPI0_DEV0CFG1_DQSTURN0_Pos       (14UL)                    /*!< DQSTURN0 (Bit 14)                                     */
#define MSPI0_DEV0CFG1_DQSTURN0_Msk       (0x1c000UL)               /*!< DQSTURN0 (Bitfield-Mask: 0x07)                        */
#define MSPI0_DEV0CFG1_RXHI0_Pos          (13UL)                    /*!< RXHI0 (Bit 13)                                        */
#define MSPI0_DEV0CFG1_RXHI0_Msk          (0x2000UL)                /*!< RXHI0 (Bitfield-Mask: 0x01)                           */
#define MSPI0_DEV0CFG1_TAFOURTH0_Pos      (12UL)                    /*!< TAFOURTH0 (Bit 12)                                    */
#define MSPI0_DEV0CFG1_TAFOURTH0_Msk      (0x1000UL)                /*!< TAFOURTH0 (Bitfield-Mask: 0x01)                       */
#define MSPI0_DEV0CFG1_HYPERIO0_Pos       (11UL)                    /*!< HYPERIO0 (Bit 11)                                     */
#define MSPI0_DEV0CFG1_HYPERIO0_Msk       (0x800UL)                 /*!< HYPERIO0 (Bitfield-Mask: 0x01)                        */
#define MSPI0_DEV0CFG1_RXSMP0_Pos         (9UL)                     /*!< RXSMP0 (Bit 9)                                        */
#define MSPI0_DEV0CFG1_RXSMP0_Msk         (0x600UL)                 /*!< RXSMP0 (Bitfield-Mask: 0x03)                          */
#define MSPI0_DEV0CFG1_RBX0_Pos           (8UL)                     /*!< RBX0 (Bit 8)                                          */
#define MSPI0_DEV0CFG1_RBX0_Msk           (0x100UL)                 /*!< RBX0 (Bitfield-Mask: 0x01)                            */
#define MSPI0_DEV0CFG1_WBX0_Pos           (7UL)                     /*!< WBX0 (Bit 7)                                          */
#define MSPI0_DEV0CFG1_WBX0_Msk           (0x80UL)                  /*!< WBX0 (Bitfield-Mask: 0x01)                            */
#define MSPI0_DEV0CFG1_SCLKRXHALT0_Pos    (5UL)                     /*!< SCLKRXHALT0 (Bit 5)                                   */
#define MSPI0_DEV0CFG1_SCLKRXHALT0_Msk    (0x20UL)                  /*!< SCLKRXHALT0 (Bitfield-Mask: 0x01)                     */
#define MSPI0_DEV0CFG1_RXCAPEXT0_Pos      (4UL)                     /*!< RXCAPEXT0 (Bit 4)                                     */
#define MSPI0_DEV0CFG1_RXCAPEXT0_Msk      (0x10UL)                  /*!< RXCAPEXT0 (Bitfield-Mask: 0x01)                       */
#define MSPI0_DEV0CFG1_SFTURN0_Pos        (0UL)                     /*!< SFTURN0 (Bit 0)                                       */
#define MSPI0_DEV0CFG1_SFTURN0_Msk        (0xfUL)                   /*!< SFTURN0 (Bitfield-Mask: 0x0f)                         */
/* ========================================================  DEV0XIP  ======================================================== */
#define MSPI0_DEV0XIP_XIPHALFWORDREVERSE0_Pos (26UL)                /*!< XIPHALFWORDREVERSE0 (Bit 26)                          */
#define MSPI0_DEV0XIP_XIPHALFWORDREVERSE0_Msk (0x4000000UL)         /*!< XIPHALFWORDREVERSE0 (Bitfield-Mask: 0x01)             */
#define MSPI0_DEV0XIP_XIPWRITELATENCY0_Pos (20UL)                   /*!< XIPWRITELATENCY0 (Bit 20)                             */
#define MSPI0_DEV0XIP_XIPWRITELATENCY0_Msk (0x3f00000UL)            /*!< XIPWRITELATENCY0 (Bitfield-Mask: 0x3f)                */
#define MSPI0_DEV0XIP_XIPTURNAROUND0_Pos  (14UL)                    /*!< XIPTURNAROUND0 (Bit 14)                               */
#define MSPI0_DEV0XIP_XIPTURNAROUND0_Msk  (0xfc000UL)               /*!< XIPTURNAROUND0 (Bitfield-Mask: 0x3f)                  */
#define MSPI0_DEV0XIP_XIPENWLAT0_Pos      (13UL)                    /*!< XIPENWLAT0 (Bit 13)                                   */
#define MSPI0_DEV0XIP_XIPENWLAT0_Msk      (0x2000UL)                /*!< XIPENWLAT0 (Bitfield-Mask: 0x01)                      */
#define MSPI0_DEV0XIP_XIPENDCX0_Pos       (12UL)                    /*!< XIPENDCX0 (Bit 12)                                    */
#define MSPI0_DEV0XIP_XIPENDCX0_Msk       (0x1000UL)                /*!< XIPENDCX0 (Bitfield-Mask: 0x01)                       */
#define MSPI0_DEV0XIP_XIPMIXED0_Pos       (8UL)                     /*!< XIPMIXED0 (Bit 8)                                     */
#define MSPI0_DEV0XIP_XIPMIXED0_Msk       (0xf00UL)                 /*!< XIPMIXED0 (Bitfield-Mask: 0x0f)                       */
#define MSPI0_DEV0XIP_XIPSENDI0_Pos       (7UL)                     /*!< XIPSENDI0 (Bit 7)                                     */
#define MSPI0_DEV0XIP_XIPSENDI0_Msk       (0x80UL)                  /*!< XIPSENDI0 (Bitfield-Mask: 0x01)                       */
#define MSPI0_DEV0XIP_XIPSENDA0_Pos       (6UL)                     /*!< XIPSENDA0 (Bit 6)                                     */
#define MSPI0_DEV0XIP_XIPSENDA0_Msk       (0x40UL)                  /*!< XIPSENDA0 (Bitfield-Mask: 0x01)                       */
#define MSPI0_DEV0XIP_XIPENTURN0_Pos      (5UL)                     /*!< XIPENTURN0 (Bit 5)                                    */
#define MSPI0_DEV0XIP_XIPENTURN0_Msk      (0x20UL)                  /*!< XIPENTURN0 (Bitfield-Mask: 0x01)                      */
#define MSPI0_DEV0XIP_XIPBIGENDIAN0_Pos   (4UL)                     /*!< XIPBIGENDIAN0 (Bit 4)                                 */
#define MSPI0_DEV0XIP_XIPBIGENDIAN0_Msk   (0x10UL)                  /*!< XIPBIGENDIAN0 (Bitfield-Mask: 0x01)                   */
#define MSPI0_DEV0XIP_XIPACK0_Pos         (2UL)                     /*!< XIPACK0 (Bit 2)                                       */
#define MSPI0_DEV0XIP_XIPACK0_Msk         (0xcUL)                   /*!< XIPACK0 (Bitfield-Mask: 0x03)                         */
#define MSPI0_DEV0XIP_XIPEN0_Pos          (0UL)                     /*!< XIPEN0 (Bit 0)                                        */
#define MSPI0_DEV0XIP_XIPEN0_Msk          (0x1UL)                   /*!< XIPEN0 (Bitfield-Mask: 0x01)                          */
/* =======================================================  DEV0INSTR  ======================================================= */
#define MSPI0_DEV0INSTR_READINSTR0_Pos    (16UL)                    /*!< READINSTR0 (Bit 16)                                   */
#define MSPI0_DEV0INSTR_READINSTR0_Msk    (0xffff0000UL)            /*!< READINSTR0 (Bitfield-Mask: 0xffff)                    */
#define MSPI0_DEV0INSTR_WRITEINSTR0_Pos   (0UL)                     /*!< WRITEINSTR0 (Bit 0)                                   */
#define MSPI0_DEV0INSTR_WRITEINSTR0_Msk   (0xffffUL)                /*!< WRITEINSTR0 (Bitfield-Mask: 0xffff)                   */
/* =====================================================  DEV0BOUNDARY  ====================================================== */
#define MSPI0_DEV0BOUNDARY_DMABOUND0_Pos  (12UL)                    /*!< DMABOUND0 (Bit 12)                                    */
#define MSPI0_DEV0BOUNDARY_DMABOUND0_Msk  (0xf000UL)                /*!< DMABOUND0 (Bitfield-Mask: 0x0f)                       */
#define MSPI0_DEV0BOUNDARY_DMATIMELIMIT0_Pos (0UL)                  /*!< DMATIMELIMIT0 (Bit 0)                                 */
#define MSPI0_DEV0BOUNDARY_DMATIMELIMIT0_Msk (0xfffUL)              /*!< DMATIMELIMIT0 (Bitfield-Mask: 0xfff)                  */
/* ====================================================  DEV0SCRAMBLING  ===================================================== */
#define MSPI0_DEV0SCRAMBLING_SCRENABLE0_Pos (31UL)                  /*!< SCRENABLE0 (Bit 31)                                   */
#define MSPI0_DEV0SCRAMBLING_SCRENABLE0_Msk (0x80000000UL)          /*!< SCRENABLE0 (Bitfield-Mask: 0x01)                      */
#define MSPI0_DEV0SCRAMBLING_SCREND0_Pos  (16UL)                    /*!< SCREND0 (Bit 16)                                      */
#define MSPI0_DEV0SCRAMBLING_SCREND0_Msk  (0x3ff0000UL)             /*!< SCREND0 (Bitfield-Mask: 0x3ff)                        */
#define MSPI0_DEV0SCRAMBLING_SCRSTART0_Pos (0UL)                    /*!< SCRSTART0 (Bit 0)                                     */
#define MSPI0_DEV0SCRAMBLING_SCRSTART0_Msk (0x3ffUL)                /*!< SCRSTART0 (Bitfield-Mask: 0x3ff)                      */
/* ======================================================  DEV0XIPMISC  ====================================================== */
#define MSPI0_DEV0XIPMISC_APNDODD0_Pos    (21UL)                    /*!< APNDODD0 (Bit 21)                                     */
#define MSPI0_DEV0XIPMISC_APNDODD0_Msk    (0x200000UL)              /*!< APNDODD0 (Bitfield-Mask: 0x01)                        */
#define MSPI0_DEV0XIPMISC_XIPBOUNDARY0_Pos (15UL)                   /*!< XIPBOUNDARY0 (Bit 15)                                 */
#define MSPI0_DEV0XIPMISC_XIPBOUNDARY0_Msk (0x8000UL)               /*!< XIPBOUNDARY0 (Bitfield-Mask: 0x01)                    */
#define MSPI0_DEV0XIPMISC_BEON0_Pos       (14UL)                    /*!< BEON0 (Bit 14)                                        */
#define MSPI0_DEV0XIPMISC_BEON0_Msk       (0x4000UL)                /*!< BEON0 (Bitfield-Mask: 0x01)                           */
#define MSPI0_DEV0XIPMISC_BEPOL0_Pos      (13UL)                    /*!< BEPOL0 (Bit 13)                                       */
#define MSPI0_DEV0XIPMISC_BEPOL0_Msk      (0x2000UL)                /*!< BEPOL0 (Bitfield-Mask: 0x01)                          */
#define MSPI0_DEV0XIPMISC_XIPODD0_Pos     (12UL)                    /*!< XIPODD0 (Bit 12)                                      */
#define MSPI0_DEV0XIPMISC_XIPODD0_Msk     (0x1000UL)                /*!< XIPODD0 (Bitfield-Mask: 0x01)                         */
#define MSPI0_DEV0XIPMISC_CEBREAK0_Pos    (0UL)                     /*!< CEBREAK0 (Bit 0)                                      */
#define MSPI0_DEV0XIPMISC_CEBREAK0_Msk    (0xfffUL)                 /*!< CEBREAK0 (Bitfield-Mask: 0xfff)                       */
/* ========================================================  DMACFG  ========================================================= */
#define MSPI0_DMACFG_DMAPWROFF_Pos        (18UL)                    /*!< DMAPWROFF (Bit 18)                                    */
#define MSPI0_DMACFG_DMAPWROFF_Msk        (0x40000UL)               /*!< DMAPWROFF (Bitfield-Mask: 0x01)                       */
#define MSPI0_DMACFG_DMATXEMPT_Pos        (17UL)                    /*!< DMATXEMPT (Bit 17)                                    */
#define MSPI0_DMACFG_DMATXEMPT_Msk        (0x20000UL)               /*!< DMATXEMPT (Bitfield-Mask: 0x01)                       */
#define MSPI0_DMACFG_DMAPRI_Pos           (4UL)                     /*!< DMAPRI (Bit 4)                                        */
#define MSPI0_DMACFG_DMAPRI_Msk           (0x30UL)                  /*!< DMAPRI (Bitfield-Mask: 0x03)                          */
#define MSPI0_DMACFG_DMADEV_Pos           (3UL)                     /*!< DMADEV (Bit 3)                                        */
#define MSPI0_DMACFG_DMADEV_Msk           (0x8UL)                   /*!< DMADEV (Bitfield-Mask: 0x01)                          */
#define MSPI0_DMACFG_DMADIR_Pos           (2UL)                     /*!< DMADIR (Bit 2)                                        */
#define MSPI0_DMACFG_DMADIR_Msk           (0x4UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
#define MSPI0_DMACFG_DMAEN_Pos            (0UL)                     /*!< DMAEN (Bit 0)                                         */
#define MSPI0_DMACFG_DMAEN_Msk            (0x3UL)                   /*!< DMAEN (Bitfield-Mask: 0x03)                           */
/* ========================================================  DMASTAT  ======================================================== */
#define MSPI0_DMASTAT_SCRERR_Pos          (3UL)                     /*!< SCRERR (Bit 3)                                        */
#define MSPI0_DMASTAT_SCRERR_Msk          (0x8UL)                   /*!< SCRERR (Bitfield-Mask: 0x01)                          */
#define MSPI0_DMASTAT_DMAERR_Pos          (2UL)                     /*!< DMAERR (Bit 2)                                        */
#define MSPI0_DMASTAT_DMAERR_Msk          (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
#define MSPI0_DMASTAT_DMACPL_Pos          (1UL)                     /*!< DMACPL (Bit 1)                                        */
#define MSPI0_DMASTAT_DMACPL_Msk          (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
#define MSPI0_DMASTAT_DMATIP_Pos          (0UL)                     /*!< DMATIP (Bit 0)                                        */
#define MSPI0_DMASTAT_DMATIP_Msk          (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
/* ======================================================  DMATARGADDR  ====================================================== */
#define MSPI0_DMATARGADDR_TARGADDR_Pos    (0UL)                     /*!< TARGADDR (Bit 0)                                      */
#define MSPI0_DMATARGADDR_TARGADDR_Msk    (0xffffffffUL)            /*!< TARGADDR (Bitfield-Mask: 0xffffffff)                  */
/* ======================================================  DMADEVADDR  ======================================================= */
#define MSPI0_DMADEVADDR_DEVADDR_Pos      (0UL)                     /*!< DEVADDR (Bit 0)                                       */
#define MSPI0_DMADEVADDR_DEVADDR_Msk      (0xffffffffUL)            /*!< DEVADDR (Bitfield-Mask: 0xffffffff)                   */
/* ======================================================  DMATOTCOUNT  ====================================================== */
#define MSPI0_DMATOTCOUNT_TOTCOUNT_Pos    (0UL)                     /*!< TOTCOUNT (Bit 0)                                      */
#define MSPI0_DMATOTCOUNT_TOTCOUNT_Msk    (0xffffffUL)              /*!< TOTCOUNT (Bitfield-Mask: 0xffffff)                    */
/* =======================================================  DMABCOUNT  ======================================================= */
#define MSPI0_DMABCOUNT_BCOUNT_Pos        (0UL)                     /*!< BCOUNT (Bit 0)                                        */
#define MSPI0_DMABCOUNT_BCOUNT_Msk        (0xffUL)                  /*!< BCOUNT (Bitfield-Mask: 0xff)                          */
/* =======================================================  DMATHRESH  ======================================================= */
#define MSPI0_DMATHRESH_DMARXTHRESH_Pos   (8UL)                     /*!< DMARXTHRESH (Bit 8)                                   */
#define MSPI0_DMATHRESH_DMARXTHRESH_Msk   (0x1f00UL)                /*!< DMARXTHRESH (Bitfield-Mask: 0x1f)                     */
#define MSPI0_DMATHRESH_DMATXTHRESH_Pos   (0UL)                     /*!< DMATXTHRESH (Bit 0)                                   */
#define MSPI0_DMATHRESH_DMATXTHRESH_Msk   (0x1fUL)                  /*!< DMATXTHRESH (Bitfield-Mask: 0x1f)                     */
/* =========================================================  INTEN  ========================================================= */
#define MSPI0_INTEN_APBDMAERR_Pos         (13UL)                    /*!< APBDMAERR (Bit 13)                                    */
#define MSPI0_INTEN_APBDMAERR_Msk         (0x2000UL)                /*!< APBDMAERR (Bitfield-Mask: 0x01)                       */
#define MSPI0_INTEN_SCRERR_Pos            (12UL)                    /*!< SCRERR (Bit 12)                                       */
#define MSPI0_INTEN_SCRERR_Msk            (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
#define MSPI0_INTEN_CQERR_Pos             (11UL)                    /*!< CQERR (Bit 11)                                        */
#define MSPI0_INTEN_CQERR_Msk             (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
#define MSPI0_INTEN_CQPAUSED_Pos          (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
#define MSPI0_INTEN_CQPAUSED_Msk          (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
#define MSPI0_INTEN_CQUPD_Pos             (9UL)                     /*!< CQUPD (Bit 9)                                         */
#define MSPI0_INTEN_CQUPD_Msk             (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
#define MSPI0_INTEN_CQCMP_Pos             (8UL)                     /*!< CQCMP (Bit 8)                                         */
#define MSPI0_INTEN_CQCMP_Msk             (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
#define MSPI0_INTEN_DERR_Pos              (7UL)                     /*!< DERR (Bit 7)                                          */
#define MSPI0_INTEN_DERR_Msk              (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
#define MSPI0_INTEN_DCMP_Pos              (6UL)                     /*!< DCMP (Bit 6)                                          */
#define MSPI0_INTEN_DCMP_Msk              (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
#define MSPI0_INTEN_RXF_Pos               (5UL)                     /*!< RXF (Bit 5)                                           */
#define MSPI0_INTEN_RXF_Msk               (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTEN_RXO_Pos               (4UL)                     /*!< RXO (Bit 4)                                           */
#define MSPI0_INTEN_RXO_Msk               (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTEN_RXU_Pos               (3UL)                     /*!< RXU (Bit 3)                                           */
#define MSPI0_INTEN_RXU_Msk               (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTEN_TXO_Pos               (2UL)                     /*!< TXO (Bit 2)                                           */
#define MSPI0_INTEN_TXO_Msk               (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTEN_TXE_Pos               (1UL)                     /*!< TXE (Bit 1)                                           */
#define MSPI0_INTEN_TXE_Msk               (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTEN_CMDCMP_Pos            (0UL)                     /*!< CMDCMP (Bit 0)                                        */
#define MSPI0_INTEN_CMDCMP_Msk            (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
/* ========================================================  INTSTAT  ======================================================== */
#define MSPI0_INTSTAT_APBDMAERR_Pos       (13UL)                    /*!< APBDMAERR (Bit 13)                                    */
#define MSPI0_INTSTAT_APBDMAERR_Msk       (0x2000UL)                /*!< APBDMAERR (Bitfield-Mask: 0x01)                       */
#define MSPI0_INTSTAT_SCRERR_Pos          (12UL)                    /*!< SCRERR (Bit 12)                                       */
#define MSPI0_INTSTAT_SCRERR_Msk          (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
#define MSPI0_INTSTAT_CQERR_Pos           (11UL)                    /*!< CQERR (Bit 11)                                        */
#define MSPI0_INTSTAT_CQERR_Msk           (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
#define MSPI0_INTSTAT_CQPAUSED_Pos        (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
#define MSPI0_INTSTAT_CQPAUSED_Msk        (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
#define MSPI0_INTSTAT_CQUPD_Pos           (9UL)                     /*!< CQUPD (Bit 9)                                         */
#define MSPI0_INTSTAT_CQUPD_Msk           (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
#define MSPI0_INTSTAT_CQCMP_Pos           (8UL)                     /*!< CQCMP (Bit 8)                                         */
#define MSPI0_INTSTAT_CQCMP_Msk           (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
#define MSPI0_INTSTAT_DERR_Pos            (7UL)                     /*!< DERR (Bit 7)                                          */
#define MSPI0_INTSTAT_DERR_Msk            (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
#define MSPI0_INTSTAT_DCMP_Pos            (6UL)                     /*!< DCMP (Bit 6)                                          */
#define MSPI0_INTSTAT_DCMP_Msk            (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
#define MSPI0_INTSTAT_RXF_Pos             (5UL)                     /*!< RXF (Bit 5)                                           */
#define MSPI0_INTSTAT_RXF_Msk             (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTSTAT_RXO_Pos             (4UL)                     /*!< RXO (Bit 4)                                           */
#define MSPI0_INTSTAT_RXO_Msk             (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTSTAT_RXU_Pos             (3UL)                     /*!< RXU (Bit 3)                                           */
#define MSPI0_INTSTAT_RXU_Msk             (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTSTAT_TXO_Pos             (2UL)                     /*!< TXO (Bit 2)                                           */
#define MSPI0_INTSTAT_TXO_Msk             (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTSTAT_TXE_Pos             (1UL)                     /*!< TXE (Bit 1)                                           */
#define MSPI0_INTSTAT_TXE_Msk             (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTSTAT_CMDCMP_Pos          (0UL)                     /*!< CMDCMP (Bit 0)                                        */
#define MSPI0_INTSTAT_CMDCMP_Msk          (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
/* ========================================================  INTCLR  ========================================================= */
#define MSPI0_INTCLR_APBDMAERR_Pos        (13UL)                    /*!< APBDMAERR (Bit 13)                                    */
#define MSPI0_INTCLR_APBDMAERR_Msk        (0x2000UL)                /*!< APBDMAERR (Bitfield-Mask: 0x01)                       */
#define MSPI0_INTCLR_SCRERR_Pos           (12UL)                    /*!< SCRERR (Bit 12)                                       */
#define MSPI0_INTCLR_SCRERR_Msk           (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
#define MSPI0_INTCLR_CQERR_Pos            (11UL)                    /*!< CQERR (Bit 11)                                        */
#define MSPI0_INTCLR_CQERR_Msk            (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
#define MSPI0_INTCLR_CQPAUSED_Pos         (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
#define MSPI0_INTCLR_CQPAUSED_Msk         (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
#define MSPI0_INTCLR_CQUPD_Pos            (9UL)                     /*!< CQUPD (Bit 9)                                         */
#define MSPI0_INTCLR_CQUPD_Msk            (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
#define MSPI0_INTCLR_CQCMP_Pos            (8UL)                     /*!< CQCMP (Bit 8)                                         */
#define MSPI0_INTCLR_CQCMP_Msk            (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
#define MSPI0_INTCLR_DERR_Pos             (7UL)                     /*!< DERR (Bit 7)                                          */
#define MSPI0_INTCLR_DERR_Msk             (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
#define MSPI0_INTCLR_DCMP_Pos             (6UL)                     /*!< DCMP (Bit 6)                                          */
#define MSPI0_INTCLR_DCMP_Msk             (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
#define MSPI0_INTCLR_RXF_Pos              (5UL)                     /*!< RXF (Bit 5)                                           */
#define MSPI0_INTCLR_RXF_Msk              (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTCLR_RXO_Pos              (4UL)                     /*!< RXO (Bit 4)                                           */
#define MSPI0_INTCLR_RXO_Msk              (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTCLR_RXU_Pos              (3UL)                     /*!< RXU (Bit 3)                                           */
#define MSPI0_INTCLR_RXU_Msk              (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTCLR_TXO_Pos              (2UL)                     /*!< TXO (Bit 2)                                           */
#define MSPI0_INTCLR_TXO_Msk              (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTCLR_TXE_Pos              (1UL)                     /*!< TXE (Bit 1)                                           */
#define MSPI0_INTCLR_TXE_Msk              (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTCLR_CMDCMP_Pos           (0UL)                     /*!< CMDCMP (Bit 0)                                        */
#define MSPI0_INTCLR_CMDCMP_Msk           (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
/* ========================================================  INTSET  ========================================================= */
#define MSPI0_INTSET_APBDMAERR_Pos        (13UL)                    /*!< APBDMAERR (Bit 13)                                    */
#define MSPI0_INTSET_APBDMAERR_Msk        (0x2000UL)                /*!< APBDMAERR (Bitfield-Mask: 0x01)                       */
#define MSPI0_INTSET_SCRERR_Pos           (12UL)                    /*!< SCRERR (Bit 12)                                       */
#define MSPI0_INTSET_SCRERR_Msk           (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
#define MSPI0_INTSET_CQERR_Pos            (11UL)                    /*!< CQERR (Bit 11)                                        */
#define MSPI0_INTSET_CQERR_Msk            (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
#define MSPI0_INTSET_CQPAUSED_Pos         (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
#define MSPI0_INTSET_CQPAUSED_Msk         (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
#define MSPI0_INTSET_CQUPD_Pos            (9UL)                     /*!< CQUPD (Bit 9)                                         */
#define MSPI0_INTSET_CQUPD_Msk            (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
#define MSPI0_INTSET_CQCMP_Pos            (8UL)                     /*!< CQCMP (Bit 8)                                         */
#define MSPI0_INTSET_CQCMP_Msk            (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
#define MSPI0_INTSET_DERR_Pos             (7UL)                     /*!< DERR (Bit 7)                                          */
#define MSPI0_INTSET_DERR_Msk             (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
#define MSPI0_INTSET_DCMP_Pos             (6UL)                     /*!< DCMP (Bit 6)                                          */
#define MSPI0_INTSET_DCMP_Msk             (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
#define MSPI0_INTSET_RXF_Pos              (5UL)                     /*!< RXF (Bit 5)                                           */
#define MSPI0_INTSET_RXF_Msk              (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTSET_RXO_Pos              (4UL)                     /*!< RXO (Bit 4)                                           */
#define MSPI0_INTSET_RXO_Msk              (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTSET_RXU_Pos              (3UL)                     /*!< RXU (Bit 3)                                           */
#define MSPI0_INTSET_RXU_Msk              (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTSET_TXO_Pos              (2UL)                     /*!< TXO (Bit 2)                                           */
#define MSPI0_INTSET_TXO_Msk              (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTSET_TXE_Pos              (1UL)                     /*!< TXE (Bit 1)                                           */
#define MSPI0_INTSET_TXE_Msk              (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
#define MSPI0_INTSET_CMDCMP_Pos           (0UL)                     /*!< CMDCMP (Bit 0)                                        */
#define MSPI0_INTSET_CMDCMP_Msk           (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
/* =========================================================  CQCFG  ========================================================= */
#define MSPI0_CQCFG_CQPAUSEOP_Pos         (4UL)                     /*!< CQPAUSEOP (Bit 4)                                     */
#define MSPI0_CQCFG_CQPAUSEOP_Msk         (0x10UL)                  /*!< CQPAUSEOP (Bitfield-Mask: 0x01)                       */
#define MSPI0_CQCFG_CQAUTOCLEARMASK_Pos   (3UL)                     /*!< CQAUTOCLEARMASK (Bit 3)                               */
#define MSPI0_CQCFG_CQAUTOCLEARMASK_Msk   (0x8UL)                   /*!< CQAUTOCLEARMASK (Bitfield-Mask: 0x01)                 */
#define MSPI0_CQCFG_CQPWROFF_Pos          (2UL)                     /*!< CQPWROFF (Bit 2)                                      */
#define MSPI0_CQCFG_CQPWROFF_Msk          (0x4UL)                   /*!< CQPWROFF (Bitfield-Mask: 0x01)                        */
#define MSPI0_CQCFG_CQPRI_Pos             (1UL)                     /*!< CQPRI (Bit 1)                                         */
#define MSPI0_CQCFG_CQPRI_Msk             (0x2UL)                   /*!< CQPRI (Bitfield-Mask: 0x01)                           */
#define MSPI0_CQCFG_CQEN_Pos              (0UL)                     /*!< CQEN (Bit 0)                                          */
#define MSPI0_CQCFG_CQEN_Msk              (0x1UL)                   /*!< CQEN (Bitfield-Mask: 0x01)                            */
/* ========================================================  CQADDR  ========================================================= */
#define MSPI0_CQADDR_CQADDR_Pos           (0UL)                     /*!< CQADDR (Bit 0)                                        */
#define MSPI0_CQADDR_CQADDR_Msk           (0x1fffffffUL)            /*!< CQADDR (Bitfield-Mask: 0x1fffffff)                    */
/* ========================================================  CQSTAT  ========================================================= */
#define MSPI0_CQSTAT_CQPAUSED_Pos         (3UL)                     /*!< CQPAUSED (Bit 3)                                      */
#define MSPI0_CQSTAT_CQPAUSED_Msk         (0x8UL)                   /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
#define MSPI0_CQSTAT_CQERR_Pos            (2UL)                     /*!< CQERR (Bit 2)                                         */
#define MSPI0_CQSTAT_CQERR_Msk            (0x4UL)                   /*!< CQERR (Bitfield-Mask: 0x01)                           */
#define MSPI0_CQSTAT_CQCPL_Pos            (1UL)                     /*!< CQCPL (Bit 1)                                         */
#define MSPI0_CQSTAT_CQCPL_Msk            (0x2UL)                   /*!< CQCPL (Bitfield-Mask: 0x01)                           */
#define MSPI0_CQSTAT_CQTIP_Pos            (0UL)                     /*!< CQTIP (Bit 0)                                         */
#define MSPI0_CQSTAT_CQTIP_Msk            (0x1UL)                   /*!< CQTIP (Bitfield-Mask: 0x01)                           */
/* ========================================================  CQFLAGS  ======================================================== */
#define MSPI0_CQFLAGS_CQFLAGS_Pos         (0UL)                     /*!< CQFLAGS (Bit 0)                                       */
#define MSPI0_CQFLAGS_CQFLAGS_Msk         (0xffffUL)                /*!< CQFLAGS (Bitfield-Mask: 0xffff)                       */
/* ======================================================  CQSETCLEAR  ======================================================= */
#define MSPI0_CQSETCLEAR_CQFCLR_Pos       (16UL)                    /*!< CQFCLR (Bit 16)                                       */
#define MSPI0_CQSETCLEAR_CQFCLR_Msk       (0xff0000UL)              /*!< CQFCLR (Bitfield-Mask: 0xff)                          */
#define MSPI0_CQSETCLEAR_CQFTOGGLE_Pos    (8UL)                     /*!< CQFTOGGLE (Bit 8)                                     */
#define MSPI0_CQSETCLEAR_CQFTOGGLE_Msk    (0xff00UL)                /*!< CQFTOGGLE (Bitfield-Mask: 0xff)                       */
#define MSPI0_CQSETCLEAR_CQFSET_Pos       (0UL)                     /*!< CQFSET (Bit 0)                                        */
#define MSPI0_CQSETCLEAR_CQFSET_Msk       (0xffUL)                  /*!< CQFSET (Bitfield-Mask: 0xff)                          */
/* ========================================================  CQPAUSE  ======================================================== */
#define MSPI0_CQPAUSE_CQMASK_Pos          (0UL)                     /*!< CQMASK (Bit 0)                                        */
#define MSPI0_CQPAUSE_CQMASK_Msk          (0xffffUL)                /*!< CQMASK (Bitfield-Mask: 0xffff)                        */
/* =======================================================  CQCURIDX  ======================================================== */
#define MSPI0_CQCURIDX_CQCURIDX_Pos       (0UL)                     /*!< CQCURIDX (Bit 0)                                      */
#define MSPI0_CQCURIDX_CQCURIDX_Msk       (0xffUL)                  /*!< CQCURIDX (Bitfield-Mask: 0xff)                        */
/* =======================================================  CQENDIDX  ======================================================== */
#define MSPI0_CQENDIDX_CQENDIDX_Pos       (0UL)                     /*!< CQENDIDX (Bit 0)                                      */
#define MSPI0_CQENDIDX_CQENDIDX_Msk       (0xffUL)                  /*!< CQENDIDX (Bitfield-Mask: 0xff)                        */
/* ======================================================  STATXIPDMA  ======================================================= */
#define MSPI0_STATXIPDMA_FLD32_Pos        (0UL)                     /*!< FLD32 (Bit 0)                                         */
#define MSPI0_STATXIPDMA_FLD32_Msk        (0xffffffffUL)            /*!< FLD32 (Bitfield-Mask: 0xffffffff)                     */


/* =========================================================================================================================== */
/* ================                                           PDM0                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
#define PDM0_CTRL_EN_Pos                  (6UL)                     /*!< EN (Bit 6)                                            */
#define PDM0_CTRL_EN_Msk                  (0x40UL)                  /*!< EN (Bitfield-Mask: 0x01)                              */
#define PDM0_CTRL_PCMPACK_Pos             (5UL)                     /*!< PCMPACK (Bit 5)                                       */
#define PDM0_CTRL_PCMPACK_Msk             (0x20UL)                  /*!< PCMPACK (Bitfield-Mask: 0x01)                         */
#define PDM0_CTRL_RSTB_Pos                (4UL)                     /*!< RSTB (Bit 4)                                          */
#define PDM0_CTRL_RSTB_Msk                (0x10UL)                  /*!< RSTB (Bitfield-Mask: 0x01)                            */
#define PDM0_CTRL_CLKSEL_Pos              (1UL)                     /*!< CLKSEL (Bit 1)                                        */
#define PDM0_CTRL_CLKSEL_Msk              (0x6UL)                   /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
#define PDM0_CTRL_CLKEN_Pos               (0UL)                     /*!< CLKEN (Bit 0)                                         */
#define PDM0_CTRL_CLKEN_Msk               (0x1UL)                   /*!< CLKEN (Bitfield-Mask: 0x01)                           */
/* =======================================================  CORECFG0  ======================================================== */
#define PDM0_CORECFG0_PGAR_Pos            (26UL)                    /*!< PGAR (Bit 26)                                         */
#define PDM0_CORECFG0_PGAR_Msk            (0x7c000000UL)            /*!< PGAR (Bitfield-Mask: 0x1f)                            */
#define PDM0_CORECFG0_PGAL_Pos            (21UL)                    /*!< PGAL (Bit 21)                                         */
#define PDM0_CORECFG0_PGAL_Msk            (0x3e00000UL)             /*!< PGAL (Bitfield-Mask: 0x1f)                            */
#define PDM0_CORECFG0_SINCRATE_Pos        (14UL)                    /*!< SINCRATE (Bit 14)                                     */
#define PDM0_CORECFG0_SINCRATE_Msk        (0x1fc000UL)              /*!< SINCRATE (Bitfield-Mask: 0x7f)                        */
#define PDM0_CORECFG0_MCLKDIV_Pos         (10UL)                    /*!< MCLKDIV (Bit 10)                                      */
#define PDM0_CORECFG0_MCLKDIV_Msk         (0x3c00UL)                /*!< MCLKDIV (Bitfield-Mask: 0x0f)                         */
#define PDM0_CORECFG0_ADCHPD_Pos          (9UL)                     /*!< ADCHPD (Bit 9)                                        */
#define PDM0_CORECFG0_ADCHPD_Msk          (0x200UL)                 /*!< ADCHPD (Bitfield-Mask: 0x01)                          */
#define PDM0_CORECFG0_HPGAIN_Pos          (5UL)                     /*!< HPGAIN (Bit 5)                                        */
#define PDM0_CORECFG0_HPGAIN_Msk          (0x1e0UL)                 /*!< HPGAIN (Bitfield-Mask: 0x0f)                          */
#define PDM0_CORECFG0_SCYCLES_Pos         (2UL)                     /*!< SCYCLES (Bit 2)                                       */
#define PDM0_CORECFG0_SCYCLES_Msk         (0x1cUL)                  /*!< SCYCLES (Bitfield-Mask: 0x07)                         */
#define PDM0_CORECFG0_SOFTMUTE_Pos        (1UL)                     /*!< SOFTMUTE (Bit 1)                                      */
#define PDM0_CORECFG0_SOFTMUTE_Msk        (0x2UL)                   /*!< SOFTMUTE (Bitfield-Mask: 0x01)                        */
#define PDM0_CORECFG0_LRSWAP_Pos          (0UL)                     /*!< LRSWAP (Bit 0)                                        */
#define PDM0_CORECFG0_LRSWAP_Msk          (0x1UL)                   /*!< LRSWAP (Bitfield-Mask: 0x01)                          */
/* =======================================================  CORECFG1  ======================================================== */
#define PDM0_CORECFG1_SELSTEP_Pos         (7UL)                     /*!< SELSTEP (Bit 7)                                       */
#define PDM0_CORECFG1_SELSTEP_Msk         (0x80UL)                  /*!< SELSTEP (Bitfield-Mask: 0x01)                         */
#define PDM0_CORECFG1_CKODLY_Pos          (4UL)                     /*!< CKODLY (Bit 4)                                        */
#define PDM0_CORECFG1_CKODLY_Msk          (0x70UL)                  /*!< CKODLY (Bitfield-Mask: 0x07)                          */
#define PDM0_CORECFG1_DIVMCLKQ_Pos        (2UL)                     /*!< DIVMCLKQ (Bit 2)                                      */
#define PDM0_CORECFG1_DIVMCLKQ_Msk        (0xcUL)                   /*!< DIVMCLKQ (Bitfield-Mask: 0x03)                        */
#define PDM0_CORECFG1_PCMCHSET_Pos        (0UL)                     /*!< PCMCHSET (Bit 0)                                      */
#define PDM0_CORECFG1_PCMCHSET_Msk        (0x3UL)                   /*!< PCMCHSET (Bitfield-Mask: 0x03)                        */
/* =======================================================  CORECTRL  ======================================================== */
#define PDM0_CORECTRL_CORECTRL_Pos        (0UL)                     /*!< CORECTRL (Bit 0)                                      */
#define PDM0_CORECTRL_CORECTRL_Msk        (0xffffffffUL)            /*!< CORECTRL (Bitfield-Mask: 0xffffffff)                  */
/* ========================================================  FIFOCNT  ======================================================== */
#define PDM0_FIFOCNT_FIFOCNT_Pos          (0UL)                     /*!< FIFOCNT (Bit 0)                                       */
#define PDM0_FIFOCNT_FIFOCNT_Msk          (0x3fUL)                  /*!< FIFOCNT (Bitfield-Mask: 0x3f)                         */
/* =======================================================  FIFOREAD  ======================================================== */
#define PDM0_FIFOREAD_FIFOREAD_Pos        (0UL)                     /*!< FIFOREAD (Bit 0)                                      */
#define PDM0_FIFOREAD_FIFOREAD_Msk        (0xffffffffUL)            /*!< FIFOREAD (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  FIFOFLUSH  ======================================================= */
#define PDM0_FIFOFLUSH_FIFOFLUSH_Pos      (0UL)                     /*!< FIFOFLUSH (Bit 0)                                     */
#define PDM0_FIFOFLUSH_FIFOFLUSH_Msk      (0x1UL)                   /*!< FIFOFLUSH (Bitfield-Mask: 0x01)                       */
/* ========================================================  FIFOTHR  ======================================================== */
#define PDM0_FIFOTHR_FIFOTHR_Pos          (0UL)                     /*!< FIFOTHR (Bit 0)                                       */
#define PDM0_FIFOTHR_FIFOTHR_Msk          (0x1fUL)                  /*!< FIFOTHR (Bitfield-Mask: 0x1f)                         */
/* =========================================================  INTEN  ========================================================= */
#define PDM0_INTEN_DERR_Pos               (4UL)                     /*!< DERR (Bit 4)                                          */
#define PDM0_INTEN_DERR_Msk               (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
#define PDM0_INTEN_DCMP_Pos               (3UL)                     /*!< DCMP (Bit 3)                                          */
#define PDM0_INTEN_DCMP_Msk               (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
#define PDM0_INTEN_UNDFL_Pos              (2UL)                     /*!< UNDFL (Bit 2)                                         */
#define PDM0_INTEN_UNDFL_Msk              (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
#define PDM0_INTEN_OVF_Pos                (1UL)                     /*!< OVF (Bit 1)                                           */
#define PDM0_INTEN_OVF_Msk                (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
#define PDM0_INTEN_THR_Pos                (0UL)                     /*!< THR (Bit 0)                                           */
#define PDM0_INTEN_THR_Msk                (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
/* ========================================================  INTSTAT  ======================================================== */
#define PDM0_INTSTAT_DERR_Pos             (4UL)                     /*!< DERR (Bit 4)                                          */
#define PDM0_INTSTAT_DERR_Msk             (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
#define PDM0_INTSTAT_DCMP_Pos             (3UL)                     /*!< DCMP (Bit 3)                                          */
#define PDM0_INTSTAT_DCMP_Msk             (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
#define PDM0_INTSTAT_UNDFL_Pos            (2UL)                     /*!< UNDFL (Bit 2)                                         */
#define PDM0_INTSTAT_UNDFL_Msk            (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
#define PDM0_INTSTAT_OVF_Pos              (1UL)                     /*!< OVF (Bit 1)                                           */
#define PDM0_INTSTAT_OVF_Msk              (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
#define PDM0_INTSTAT_THR_Pos              (0UL)                     /*!< THR (Bit 0)                                           */
#define PDM0_INTSTAT_THR_Msk              (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
/* ========================================================  INTCLR  ========================================================= */
#define PDM0_INTCLR_DERR_Pos              (4UL)                     /*!< DERR (Bit 4)                                          */
#define PDM0_INTCLR_DERR_Msk              (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
#define PDM0_INTCLR_DCMP_Pos              (3UL)                     /*!< DCMP (Bit 3)                                          */
#define PDM0_INTCLR_DCMP_Msk              (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
#define PDM0_INTCLR_UNDFL_Pos             (2UL)                     /*!< UNDFL (Bit 2)                                         */
#define PDM0_INTCLR_UNDFL_Msk             (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
#define PDM0_INTCLR_OVF_Pos               (1UL)                     /*!< OVF (Bit 1)                                           */
#define PDM0_INTCLR_OVF_Msk               (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
#define PDM0_INTCLR_THR_Pos               (0UL)                     /*!< THR (Bit 0)                                           */
#define PDM0_INTCLR_THR_Msk               (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
/* ========================================================  INTSET  ========================================================= */
#define PDM0_INTSET_DERR_Pos              (4UL)                     /*!< DERR (Bit 4)                                          */
#define PDM0_INTSET_DERR_Msk              (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
#define PDM0_INTSET_DCMP_Pos              (3UL)                     /*!< DCMP (Bit 3)                                          */
#define PDM0_INTSET_DCMP_Msk              (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
#define PDM0_INTSET_UNDFL_Pos             (2UL)                     /*!< UNDFL (Bit 2)                                         */
#define PDM0_INTSET_UNDFL_Msk             (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
#define PDM0_INTSET_OVF_Pos               (1UL)                     /*!< OVF (Bit 1)                                           */
#define PDM0_INTSET_OVF_Msk               (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
#define PDM0_INTSET_THR_Pos               (0UL)                     /*!< THR (Bit 0)                                           */
#define PDM0_INTSET_THR_Msk               (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
/* =======================================================  DMATRIGEN  ======================================================= */
#define PDM0_DMATRIGEN_DTHR90_Pos         (1UL)                     /*!< DTHR90 (Bit 1)                                        */
#define PDM0_DMATRIGEN_DTHR90_Msk         (0x2UL)                   /*!< DTHR90 (Bitfield-Mask: 0x01)                          */
#define PDM0_DMATRIGEN_DTHR_Pos           (0UL)                     /*!< DTHR (Bit 0)                                          */
#define PDM0_DMATRIGEN_DTHR_Msk           (0x1UL)                   /*!< DTHR (Bitfield-Mask: 0x01)                            */
/* ======================================================  DMATRIGSTAT  ====================================================== */
#define PDM0_DMATRIGSTAT_DTHR90STAT_Pos   (1UL)                     /*!< DTHR90STAT (Bit 1)                                    */
#define PDM0_DMATRIGSTAT_DTHR90STAT_Msk   (0x2UL)                   /*!< DTHR90STAT (Bitfield-Mask: 0x01)                      */
#define PDM0_DMATRIGSTAT_DTHRSTAT_Pos     (0UL)                     /*!< DTHRSTAT (Bit 0)                                      */
#define PDM0_DMATRIGSTAT_DTHRSTAT_Msk     (0x1UL)                   /*!< DTHRSTAT (Bitfield-Mask: 0x01)                        */
/* ========================================================  DMACFG  ========================================================= */
#define PDM0_DMACFG_DPWROFF_Pos           (10UL)                    /*!< DPWROFF (Bit 10)                                      */
#define PDM0_DMACFG_DPWROFF_Msk           (0x400UL)                 /*!< DPWROFF (Bitfield-Mask: 0x01)                         */
#define PDM0_DMACFG_DAUTOHIP_Pos          (9UL)                     /*!< DAUTOHIP (Bit 9)                                      */
#define PDM0_DMACFG_DAUTOHIP_Msk          (0x200UL)                 /*!< DAUTOHIP (Bitfield-Mask: 0x01)                        */
#define PDM0_DMACFG_DMAPRI_Pos            (8UL)                     /*!< DMAPRI (Bit 8)                                        */
#define PDM0_DMACFG_DMAPRI_Msk            (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
#define PDM0_DMACFG_DMADIR_Pos            (2UL)                     /*!< DMADIR (Bit 2)                                        */
#define PDM0_DMACFG_DMADIR_Msk            (0x4UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
#define PDM0_DMACFG_DMAEN_Pos             (0UL)                     /*!< DMAEN (Bit 0)                                         */
#define PDM0_DMACFG_DMAEN_Msk             (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
/* ======================================================  DMATARGADDR  ====================================================== */
#define PDM0_DMATARGADDR_UTARGADDR_Pos    (28UL)                    /*!< UTARGADDR (Bit 28)                                    */
#define PDM0_DMATARGADDR_UTARGADDR_Msk    (0xf0000000UL)            /*!< UTARGADDR (Bitfield-Mask: 0x0f)                       */
#define PDM0_DMATARGADDR_LTARGADDR_Pos    (0UL)                     /*!< LTARGADDR (Bit 0)                                     */
#define PDM0_DMATARGADDR_LTARGADDR_Msk    (0xfffffffUL)             /*!< LTARGADDR (Bitfield-Mask: 0xfffffff)                  */
/* ========================================================  DMASTAT  ======================================================== */
#define PDM0_DMASTAT_DMAERR_Pos           (2UL)                     /*!< DMAERR (Bit 2)                                        */
#define PDM0_DMASTAT_DMAERR_Msk           (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
#define PDM0_DMASTAT_DMACPL_Pos           (1UL)                     /*!< DMACPL (Bit 1)                                        */
#define PDM0_DMASTAT_DMACPL_Msk           (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
#define PDM0_DMASTAT_DMATIP_Pos           (0UL)                     /*!< DMATIP (Bit 0)                                        */
#define PDM0_DMASTAT_DMATIP_Msk           (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
/* ======================================================  DMATOTCOUNT  ====================================================== */
#define PDM0_DMATOTCOUNT_TOTCOUNT_Pos     (0UL)                     /*!< TOTCOUNT (Bit 0)                                      */
#define PDM0_DMATOTCOUNT_TOTCOUNT_Msk     (0xfffffUL)               /*!< TOTCOUNT (Bitfield-Mask: 0xfffff)                     */


/* =========================================================================================================================== */
/* ================                                          PWRCTRL                                          ================ */
/* =========================================================================================================================== */

/* ======================================================  MCUPERFREQ  ======================================================= */
#define PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_Pos (3UL)                  /*!< MCUPERFSTATUS (Bit 3)                                 */
#define PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_Msk (0x18UL)               /*!< MCUPERFSTATUS (Bitfield-Mask: 0x03)                   */
#define PWRCTRL_MCUPERFREQ_MCUPERFACK_Pos (2UL)                     /*!< MCUPERFACK (Bit 2)                                    */
#define PWRCTRL_MCUPERFREQ_MCUPERFACK_Msk (0x4UL)                   /*!< MCUPERFACK (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_MCUPERFREQ_MCUPERFREQ_Pos (0UL)                     /*!< MCUPERFREQ (Bit 0)                                    */
#define PWRCTRL_MCUPERFREQ_MCUPERFREQ_Msk (0x3UL)                   /*!< MCUPERFREQ (Bitfield-Mask: 0x03)                      */
/* =======================================================  DEVPWREN  ======================================================== */
#define PWRCTRL_DEVPWREN_PWRENDBG_Pos     (24UL)                    /*!< PWRENDBG (Bit 24)                                     */
#define PWRCTRL_DEVPWREN_PWRENDBG_Msk     (0x1000000UL)             /*!< PWRENDBG (Bitfield-Mask: 0x01)                        */
#define PWRCTRL_DEVPWREN_PWRENSDIO_Pos    (21UL)                    /*!< PWRENSDIO (Bit 21)                                    */
#define PWRCTRL_DEVPWREN_PWRENSDIO_Msk    (0x200000UL)              /*!< PWRENSDIO (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_DEVPWREN_PWRENCRYPTO_Pos  (20UL)                    /*!< PWRENCRYPTO (Bit 20)                                  */
#define PWRCTRL_DEVPWREN_PWRENCRYPTO_Msk  (0x100000UL)              /*!< PWRENCRYPTO (Bitfield-Mask: 0x01)                     */
#define PWRCTRL_DEVPWREN_PWRENGFX_Pos     (17UL)                    /*!< PWRENGFX (Bit 17)                                     */
#define PWRCTRL_DEVPWREN_PWRENGFX_Msk     (0x20000UL)               /*!< PWRENGFX (Bitfield-Mask: 0x01)                        */
#define PWRCTRL_DEVPWREN_PWRENMSPI2_Pos   (16UL)                    /*!< PWRENMSPI2 (Bit 16)                                   */
#define PWRCTRL_DEVPWREN_PWRENMSPI2_Msk   (0x10000UL)               /*!< PWRENMSPI2 (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_DEVPWREN_PWRENMSPI1_Pos   (15UL)                    /*!< PWRENMSPI1 (Bit 15)                                   */
#define PWRCTRL_DEVPWREN_PWRENMSPI1_Msk   (0x8000UL)                /*!< PWRENMSPI1 (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_DEVPWREN_PWRENMSPI0_Pos   (14UL)                    /*!< PWRENMSPI0 (Bit 14)                                   */
#define PWRCTRL_DEVPWREN_PWRENMSPI0_Msk   (0x4000UL)                /*!< PWRENMSPI0 (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_DEVPWREN_PWRENADC_Pos     (13UL)                    /*!< PWRENADC (Bit 13)                                     */
#define PWRCTRL_DEVPWREN_PWRENADC_Msk     (0x2000UL)                /*!< PWRENADC (Bitfield-Mask: 0x01)                        */
#define PWRCTRL_DEVPWREN_PWRENUART3_Pos   (12UL)                    /*!< PWRENUART3 (Bit 12)                                   */
#define PWRCTRL_DEVPWREN_PWRENUART3_Msk   (0x1000UL)                /*!< PWRENUART3 (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_DEVPWREN_PWRENUART2_Pos   (11UL)                    /*!< PWRENUART2 (Bit 11)                                   */
#define PWRCTRL_DEVPWREN_PWRENUART2_Msk   (0x800UL)                 /*!< PWRENUART2 (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_DEVPWREN_PWRENUART1_Pos   (10UL)                    /*!< PWRENUART1 (Bit 10)                                   */
#define PWRCTRL_DEVPWREN_PWRENUART1_Msk   (0x400UL)                 /*!< PWRENUART1 (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_DEVPWREN_PWRENUART0_Pos   (9UL)                     /*!< PWRENUART0 (Bit 9)                                    */
#define PWRCTRL_DEVPWREN_PWRENUART0_Msk   (0x200UL)                 /*!< PWRENUART0 (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_DEVPWREN_PWRENIOM7_Pos    (8UL)                     /*!< PWRENIOM7 (Bit 8)                                     */
#define PWRCTRL_DEVPWREN_PWRENIOM7_Msk    (0x100UL)                 /*!< PWRENIOM7 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_DEVPWREN_PWRENIOM6_Pos    (7UL)                     /*!< PWRENIOM6 (Bit 7)                                     */
#define PWRCTRL_DEVPWREN_PWRENIOM6_Msk    (0x80UL)                  /*!< PWRENIOM6 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_DEVPWREN_PWRENIOM5_Pos    (6UL)                     /*!< PWRENIOM5 (Bit 6)                                     */
#define PWRCTRL_DEVPWREN_PWRENIOM5_Msk    (0x40UL)                  /*!< PWRENIOM5 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_DEVPWREN_PWRENIOM4_Pos    (5UL)                     /*!< PWRENIOM4 (Bit 5)                                     */
#define PWRCTRL_DEVPWREN_PWRENIOM4_Msk    (0x20UL)                  /*!< PWRENIOM4 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_DEVPWREN_PWRENIOM3_Pos    (4UL)                     /*!< PWRENIOM3 (Bit 4)                                     */
#define PWRCTRL_DEVPWREN_PWRENIOM3_Msk    (0x10UL)                  /*!< PWRENIOM3 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_DEVPWREN_PWRENIOM2_Pos    (3UL)                     /*!< PWRENIOM2 (Bit 3)                                     */
#define PWRCTRL_DEVPWREN_PWRENIOM2_Msk    (0x8UL)                   /*!< PWRENIOM2 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_DEVPWREN_PWRENIOM1_Pos    (2UL)                     /*!< PWRENIOM1 (Bit 2)                                     */
#define PWRCTRL_DEVPWREN_PWRENIOM1_Msk    (0x4UL)                   /*!< PWRENIOM1 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_DEVPWREN_PWRENIOM0_Pos    (1UL)                     /*!< PWRENIOM0 (Bit 1)                                     */
#define PWRCTRL_DEVPWREN_PWRENIOM0_Msk    (0x2UL)                   /*!< PWRENIOM0 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_DEVPWREN_PWRENIOS_Pos     (0UL)                     /*!< PWRENIOS (Bit 0)                                      */
#define PWRCTRL_DEVPWREN_PWRENIOS_Msk     (0x1UL)                   /*!< PWRENIOS (Bitfield-Mask: 0x01)                        */
/* =====================================================  DEVPWRSTATUS  ====================================================== */
#define PWRCTRL_DEVPWRSTATUS_PWRSTDBG_Pos (24UL)                    /*!< PWRSTDBG (Bit 24)                                     */
#define PWRCTRL_DEVPWRSTATUS_PWRSTDBG_Msk (0x1000000UL)             /*!< PWRSTDBG (Bitfield-Mask: 0x01)                        */
#define PWRCTRL_DEVPWRSTATUS_PWRSTSDIO_Pos (21UL)                   /*!< PWRSTSDIO (Bit 21)                                    */
#define PWRCTRL_DEVPWRSTATUS_PWRSTSDIO_Msk (0x200000UL)             /*!< PWRSTSDIO (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO_Pos (20UL)                 /*!< PWRSTCRYPTO (Bit 20)                                  */
#define PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO_Msk (0x100000UL)           /*!< PWRSTCRYPTO (Bitfield-Mask: 0x01)                     */
#define PWRCTRL_DEVPWRSTATUS_PWRSTGFX_Pos (17UL)                    /*!< PWRSTGFX (Bit 17)                                     */
#define PWRCTRL_DEVPWRSTATUS_PWRSTGFX_Msk (0x20000UL)               /*!< PWRSTGFX (Bitfield-Mask: 0x01)                        */
#define PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2_Pos (16UL)                  /*!< PWRSTMSPI2 (Bit 16)                                   */
#define PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2_Msk (0x10000UL)             /*!< PWRSTMSPI2 (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1_Pos (15UL)                  /*!< PWRSTMSPI1 (Bit 15)                                   */
#define PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1_Msk (0x8000UL)              /*!< PWRSTMSPI1 (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0_Pos (14UL)                  /*!< PWRSTMSPI0 (Bit 14)                                   */
#define PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0_Msk (0x4000UL)              /*!< PWRSTMSPI0 (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_DEVPWRSTATUS_PWRSTADC_Pos (13UL)                    /*!< PWRSTADC (Bit 13)                                     */
#define PWRCTRL_DEVPWRSTATUS_PWRSTADC_Msk (0x2000UL)                /*!< PWRSTADC (Bitfield-Mask: 0x01)                        */
#define PWRCTRL_DEVPWRSTATUS_PWRSTUART3_Pos (12UL)                  /*!< PWRSTUART3 (Bit 12)                                   */
#define PWRCTRL_DEVPWRSTATUS_PWRSTUART3_Msk (0x1000UL)              /*!< PWRSTUART3 (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_DEVPWRSTATUS_PWRSTUART2_Pos (11UL)                  /*!< PWRSTUART2 (Bit 11)                                   */
#define PWRCTRL_DEVPWRSTATUS_PWRSTUART2_Msk (0x800UL)               /*!< PWRSTUART2 (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_DEVPWRSTATUS_PWRSTUART1_Pos (10UL)                  /*!< PWRSTUART1 (Bit 10)                                   */
#define PWRCTRL_DEVPWRSTATUS_PWRSTUART1_Msk (0x400UL)               /*!< PWRSTUART1 (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_DEVPWRSTATUS_PWRSTUART0_Pos (9UL)                   /*!< PWRSTUART0 (Bit 9)                                    */
#define PWRCTRL_DEVPWRSTATUS_PWRSTUART0_Msk (0x200UL)               /*!< PWRSTUART0 (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_DEVPWRSTATUS_PWRSTIOM7_Pos (8UL)                    /*!< PWRSTIOM7 (Bit 8)                                     */
#define PWRCTRL_DEVPWRSTATUS_PWRSTIOM7_Msk (0x100UL)                /*!< PWRSTIOM7 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_DEVPWRSTATUS_PWRSTIOM6_Pos (7UL)                    /*!< PWRSTIOM6 (Bit 7)                                     */
#define PWRCTRL_DEVPWRSTATUS_PWRSTIOM6_Msk (0x80UL)                 /*!< PWRSTIOM6 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_DEVPWRSTATUS_PWRSTIOM5_Pos (6UL)                    /*!< PWRSTIOM5 (Bit 6)                                     */
#define PWRCTRL_DEVPWRSTATUS_PWRSTIOM5_Msk (0x40UL)                 /*!< PWRSTIOM5 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_DEVPWRSTATUS_PWRSTIOM4_Pos (5UL)                    /*!< PWRSTIOM4 (Bit 5)                                     */
#define PWRCTRL_DEVPWRSTATUS_PWRSTIOM4_Msk (0x20UL)                 /*!< PWRSTIOM4 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_DEVPWRSTATUS_PWRSTIOM3_Pos (4UL)                    /*!< PWRSTIOM3 (Bit 4)                                     */
#define PWRCTRL_DEVPWRSTATUS_PWRSTIOM3_Msk (0x10UL)                 /*!< PWRSTIOM3 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_DEVPWRSTATUS_PWRSTIOM2_Pos (3UL)                    /*!< PWRSTIOM2 (Bit 3)                                     */
#define PWRCTRL_DEVPWRSTATUS_PWRSTIOM2_Msk (0x8UL)                  /*!< PWRSTIOM2 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_DEVPWRSTATUS_PWRSTIOM1_Pos (2UL)                    /*!< PWRSTIOM1 (Bit 2)                                     */
#define PWRCTRL_DEVPWRSTATUS_PWRSTIOM1_Msk (0x4UL)                  /*!< PWRSTIOM1 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_DEVPWRSTATUS_PWRSTIOM0_Pos (1UL)                    /*!< PWRSTIOM0 (Bit 1)                                     */
#define PWRCTRL_DEVPWRSTATUS_PWRSTIOM0_Msk (0x2UL)                  /*!< PWRSTIOM0 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_DEVPWRSTATUS_PWRSTIOS_Pos (0UL)                     /*!< PWRSTIOS (Bit 0)                                      */
#define PWRCTRL_DEVPWRSTATUS_PWRSTIOS_Msk (0x1UL)                   /*!< PWRSTIOS (Bitfield-Mask: 0x01)                        */
/* ======================================================  AUDSSPWREN  ======================================================= */
#define PWRCTRL_AUDSSPWREN_PWRENI2S1_Pos  (7UL)                     /*!< PWRENI2S1 (Bit 7)                                     */
#define PWRCTRL_AUDSSPWREN_PWRENI2S1_Msk  (0x80UL)                  /*!< PWRENI2S1 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_AUDSSPWREN_PWRENI2S0_Pos  (6UL)                     /*!< PWRENI2S0 (Bit 6)                                     */
#define PWRCTRL_AUDSSPWREN_PWRENI2S0_Msk  (0x40UL)                  /*!< PWRENI2S0 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_AUDSSPWREN_PWRENPDM0_Pos  (2UL)                     /*!< PWRENPDM0 (Bit 2)                                     */
#define PWRCTRL_AUDSSPWREN_PWRENPDM0_Msk  (0x4UL)                   /*!< PWRENPDM0 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_AUDSSPWREN_PWRENAUDPB_Pos (1UL)                     /*!< PWRENAUDPB (Bit 1)                                    */
#define PWRCTRL_AUDSSPWREN_PWRENAUDPB_Msk (0x2UL)                   /*!< PWRENAUDPB (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_AUDSSPWREN_PWRENAUDREC_Pos (0UL)                    /*!< PWRENAUDREC (Bit 0)                                   */
#define PWRCTRL_AUDSSPWREN_PWRENAUDREC_Msk (0x1UL)                  /*!< PWRENAUDREC (Bitfield-Mask: 0x01)                     */
/* ====================================================  AUDSSPWRSTATUS  ===================================================== */
#define PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1_Pos (7UL)                  /*!< PWRSTI2S1 (Bit 7)                                     */
#define PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1_Msk (0x80UL)               /*!< PWRSTI2S1 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0_Pos (6UL)                  /*!< PWRSTI2S0 (Bit 6)                                     */
#define PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0_Msk (0x40UL)               /*!< PWRSTI2S0 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0_Pos (2UL)                  /*!< PWRSTPDM0 (Bit 2)                                     */
#define PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0_Msk (0x4UL)                /*!< PWRSTPDM0 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB_Pos (1UL)                 /*!< PWRSTAUDPB (Bit 1)                                    */
#define PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB_Msk (0x2UL)               /*!< PWRSTAUDPB (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC_Pos (0UL)                /*!< PWRSTAUDREC (Bit 0)                                   */
#define PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC_Msk (0x1UL)              /*!< PWRSTAUDREC (Bitfield-Mask: 0x01)                     */
/* =======================================================  MEMPWREN  ======================================================== */
#define PWRCTRL_MEMPWREN_PWRENCACHEB2_Pos (5UL)                     /*!< PWRENCACHEB2 (Bit 5)                                  */
#define PWRCTRL_MEMPWREN_PWRENCACHEB2_Msk (0x20UL)                  /*!< PWRENCACHEB2 (Bitfield-Mask: 0x01)                    */
#define PWRCTRL_MEMPWREN_PWRENCACHEB0_Pos (4UL)                     /*!< PWRENCACHEB0 (Bit 4)                                  */
#define PWRCTRL_MEMPWREN_PWRENCACHEB0_Msk (0x10UL)                  /*!< PWRENCACHEB0 (Bitfield-Mask: 0x01)                    */
#define PWRCTRL_MEMPWREN_PWRENNVM0_Pos    (3UL)                     /*!< PWRENNVM0 (Bit 3)                                     */
#define PWRCTRL_MEMPWREN_PWRENNVM0_Msk    (0x8UL)                   /*!< PWRENNVM0 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_MEMPWREN_PWRENDTCM_Pos    (0UL)                     /*!< PWRENDTCM (Bit 0)                                     */
#define PWRCTRL_MEMPWREN_PWRENDTCM_Msk    (0x7UL)                   /*!< PWRENDTCM (Bitfield-Mask: 0x07)                       */
/* =====================================================  MEMPWRSTATUS  ====================================================== */
#define PWRCTRL_MEMPWRSTATUS_PWRSTCACHEB2_Pos (5UL)                 /*!< PWRSTCACHEB2 (Bit 5)                                  */
#define PWRCTRL_MEMPWRSTATUS_PWRSTCACHEB2_Msk (0x20UL)              /*!< PWRSTCACHEB2 (Bitfield-Mask: 0x01)                    */
#define PWRCTRL_MEMPWRSTATUS_PWRSTCACHEB0_Pos (4UL)                 /*!< PWRSTCACHEB0 (Bit 4)                                  */
#define PWRCTRL_MEMPWRSTATUS_PWRSTCACHEB0_Msk (0x10UL)              /*!< PWRSTCACHEB0 (Bitfield-Mask: 0x01)                    */
#define PWRCTRL_MEMPWRSTATUS_PWRSTNVM0_Pos (3UL)                    /*!< PWRSTNVM0 (Bit 3)                                     */
#define PWRCTRL_MEMPWRSTATUS_PWRSTNVM0_Msk (0x8UL)                  /*!< PWRSTNVM0 (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_Pos (0UL)                    /*!< PWRSTDTCM (Bit 0)                                     */
#define PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_Msk (0x7UL)                  /*!< PWRSTDTCM (Bitfield-Mask: 0x07)                       */
/* =======================================================  MEMRETCFG  ======================================================= */
#define PWRCTRL_MEMRETCFG_CACHEPWDSLP_Pos (4UL)                     /*!< CACHEPWDSLP (Bit 4)                                   */
#define PWRCTRL_MEMRETCFG_CACHEPWDSLP_Msk (0x10UL)                  /*!< CACHEPWDSLP (Bitfield-Mask: 0x01)                     */
#define PWRCTRL_MEMRETCFG_NVM0PWDSLP_Pos  (3UL)                     /*!< NVM0PWDSLP (Bit 3)                                    */
#define PWRCTRL_MEMRETCFG_NVM0PWDSLP_Msk  (0x8UL)                   /*!< NVM0PWDSLP (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_MEMRETCFG_DTCMPWDSLP_Pos  (0UL)                     /*!< DTCMPWDSLP (Bit 0)                                    */
#define PWRCTRL_MEMRETCFG_DTCMPWDSLP_Msk  (0x7UL)                   /*!< DTCMPWDSLP (Bitfield-Mask: 0x07)                      */
/* =====================================================  SYSPWRSTATUS  ====================================================== */
#define PWRCTRL_SYSPWRSTATUS_SYSDEEPSLEEP_Pos (31UL)                /*!< SYSDEEPSLEEP (Bit 31)                                 */
#define PWRCTRL_SYSPWRSTATUS_SYSDEEPSLEEP_Msk (0x80000000UL)        /*!< SYSDEEPSLEEP (Bitfield-Mask: 0x01)                    */
#define PWRCTRL_SYSPWRSTATUS_COREDEEPSLEEP_Pos (30UL)               /*!< COREDEEPSLEEP (Bit 30)                                */
#define PWRCTRL_SYSPWRSTATUS_COREDEEPSLEEP_Msk (0x40000000UL)       /*!< COREDEEPSLEEP (Bitfield-Mask: 0x01)                   */
#define PWRCTRL_SYSPWRSTATUS_CORESLEEP_Pos (29UL)                   /*!< CORESLEEP (Bit 29)                                    */
#define PWRCTRL_SYSPWRSTATUS_CORESLEEP_Msk (0x20000000UL)           /*!< CORESLEEP (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_SYSPWRSTATUS_PWRSTDSP1H_Pos (3UL)                   /*!< PWRSTDSP1H (Bit 3)                                    */
#define PWRCTRL_SYSPWRSTATUS_PWRSTDSP1H_Msk (0x8UL)                 /*!< PWRSTDSP1H (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_SYSPWRSTATUS_PWRSTDSP0H_Pos (2UL)                   /*!< PWRSTDSP0H (Bit 2)                                    */
#define PWRCTRL_SYSPWRSTATUS_PWRSTDSP0H_Msk (0x4UL)                 /*!< PWRSTDSP0H (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_SYSPWRSTATUS_PWRSTMCUH_Pos (1UL)                    /*!< PWRSTMCUH (Bit 1)                                     */
#define PWRCTRL_SYSPWRSTATUS_PWRSTMCUH_Msk (0x2UL)                  /*!< PWRSTMCUH (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_SYSPWRSTATUS_PWRSTMCUL_Pos (0UL)                    /*!< PWRSTMCUL (Bit 0)                                     */
#define PWRCTRL_SYSPWRSTATUS_PWRSTMCUL_Msk (0x1UL)                  /*!< PWRSTMCUL (Bitfield-Mask: 0x01)                       */
/* ======================================================  SSRAMPWREN  ======================================================= */
#define PWRCTRL_SSRAMPWREN_PWRENSSRAM_Pos (0UL)                     /*!< PWRENSSRAM (Bit 0)                                    */
#define PWRCTRL_SSRAMPWREN_PWRENSSRAM_Msk (0x3UL)                   /*!< PWRENSSRAM (Bitfield-Mask: 0x03)                      */
/* ======================================================  SSRAMPWRST  ======================================================= */
#define PWRCTRL_SSRAMPWRST_SSRAMPWRST_Pos (0UL)                     /*!< SSRAMPWRST (Bit 0)                                    */
#define PWRCTRL_SSRAMPWRST_SSRAMPWRST_Msk (0x3UL)                   /*!< SSRAMPWRST (Bitfield-Mask: 0x03)                      */
/* ======================================================  SSRAMRETCFG  ====================================================== */
#define PWRCTRL_SSRAMRETCFG_SSRAMACTDISP_Pos (8UL)                  /*!< SSRAMACTDISP (Bit 8)                                  */
#define PWRCTRL_SSRAMRETCFG_SSRAMACTDISP_Msk (0x300UL)              /*!< SSRAMACTDISP (Bitfield-Mask: 0x03)                    */
#define PWRCTRL_SSRAMRETCFG_SSRAMACTGFX_Pos (6UL)                   /*!< SSRAMACTGFX (Bit 6)                                   */
#define PWRCTRL_SSRAMRETCFG_SSRAMACTGFX_Msk (0xc0UL)                /*!< SSRAMACTGFX (Bitfield-Mask: 0x03)                     */
#define PWRCTRL_SSRAMRETCFG_SSRAMACTDSP_Pos (4UL)                   /*!< SSRAMACTDSP (Bit 4)                                   */
#define PWRCTRL_SSRAMRETCFG_SSRAMACTDSP_Msk (0x30UL)                /*!< SSRAMACTDSP (Bitfield-Mask: 0x03)                     */
#define PWRCTRL_SSRAMRETCFG_SSRAMACTMCU_Pos (2UL)                   /*!< SSRAMACTMCU (Bit 2)                                   */
#define PWRCTRL_SSRAMRETCFG_SSRAMACTMCU_Msk (0xcUL)                 /*!< SSRAMACTMCU (Bitfield-Mask: 0x03)                     */
#define PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_Pos (0UL)                   /*!< SSRAMPWDSLP (Bit 0)                                   */
#define PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_Msk (0x3UL)                 /*!< SSRAMPWDSLP (Bitfield-Mask: 0x03)                     */
/* =====================================================  DEVPWREVENTEN  ===================================================== */
#define PWRCTRL_DEVPWREVENTEN_AUDEVEN_Pos (7UL)                     /*!< AUDEVEN (Bit 7)                                       */
#define PWRCTRL_DEVPWREVENTEN_AUDEVEN_Msk (0x80UL)                  /*!< AUDEVEN (Bitfield-Mask: 0x01)                         */
#define PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Pos (6UL)                    /*!< MSPIEVEN (Bit 6)                                      */
#define PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Msk (0x40UL)                 /*!< MSPIEVEN (Bitfield-Mask: 0x01)                        */
#define PWRCTRL_DEVPWREVENTEN_ADCEVEN_Pos (5UL)                     /*!< ADCEVEN (Bit 5)                                       */
#define PWRCTRL_DEVPWREVENTEN_ADCEVEN_Msk (0x20UL)                  /*!< ADCEVEN (Bitfield-Mask: 0x01)                         */
#define PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Pos (4UL)                    /*!< HCPCEVEN (Bit 4)                                      */
#define PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Msk (0x10UL)                 /*!< HCPCEVEN (Bitfield-Mask: 0x01)                        */
#define PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Pos (3UL)                    /*!< HCPBEVEN (Bit 3)                                      */
#define PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Msk (0x8UL)                  /*!< HCPBEVEN (Bitfield-Mask: 0x01)                        */
#define PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Pos (2UL)                    /*!< HCPAEVEN (Bit 2)                                      */
#define PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Msk (0x4UL)                  /*!< HCPAEVEN (Bitfield-Mask: 0x01)                        */
#define PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Pos (1UL)                    /*!< MCUHEVEN (Bit 1)                                      */
#define PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Msk (0x2UL)                  /*!< MCUHEVEN (Bitfield-Mask: 0x01)                        */
#define PWRCTRL_DEVPWREVENTEN_MCULEVEN_Pos (0UL)                    /*!< MCULEVEN (Bit 0)                                      */
#define PWRCTRL_DEVPWREVENTEN_MCULEVEN_Msk (0x1UL)                  /*!< MCULEVEN (Bitfield-Mask: 0x01)                        */
/* =====================================================  MEMPWREVENTEN  ===================================================== */
#define PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Pos (5UL)                   /*!< CACHEB2EN (Bit 5)                                     */
#define PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Msk (0x20UL)                /*!< CACHEB2EN (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Pos (4UL)                   /*!< CACHEB0EN (Bit 4)                                     */
#define PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Msk (0x10UL)                /*!< CACHEB0EN (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_MEMPWREVENTEN_NVM0EN_Pos  (3UL)                     /*!< NVM0EN (Bit 3)                                        */
#define PWRCTRL_MEMPWREVENTEN_NVM0EN_Msk  (0x8UL)                   /*!< NVM0EN (Bitfield-Mask: 0x01)                          */
#define PWRCTRL_MEMPWREVENTEN_DTCMEN_Pos  (0UL)                     /*!< DTCMEN (Bit 0)                                        */
#define PWRCTRL_MEMPWREVENTEN_DTCMEN_Msk  (0x7UL)                   /*!< DTCMEN (Bitfield-Mask: 0x07)                          */
/* ======================================================  MMSOVERRIDE  ====================================================== */
#define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX_Pos (10UL)            /*!< MMSOVRSSRAMRETGFX (Bit 10)                            */
#define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX_Msk (0xc00UL)         /*!< MMSOVRSSRAMRETGFX (Bitfield-Mask: 0x03)               */
#define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP_Pos (8UL)            /*!< MMSOVRSSRAMRETDISP (Bit 8)                            */
#define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP_Msk (0x300UL)        /*!< MMSOVRSSRAMRETDISP (Bitfield-Mask: 0x03)              */
#define PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX_Pos (6UL)            /*!< MMSOVRDSPRAMRETGFX (Bit 6)                            */
#define PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX_Msk (0xc0UL)         /*!< MMSOVRDSPRAMRETGFX (Bitfield-Mask: 0x03)              */
#define PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP_Pos (4UL)           /*!< MMSOVRDSPRAMRETDISP (Bit 4)                           */
#define PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP_Msk (0x30UL)        /*!< MMSOVRDSPRAMRETDISP (Bitfield-Mask: 0x03)             */
#define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX_Pos (3UL)                /*!< MMSOVRSSRAMGFX (Bit 3)                                */
#define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX_Msk (0x8UL)              /*!< MMSOVRSSRAMGFX (Bitfield-Mask: 0x01)                  */
#define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP_Pos (2UL)               /*!< MMSOVRSSRAMDISP (Bit 2)                               */
#define PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP_Msk (0x4UL)             /*!< MMSOVRSSRAMDISP (Bitfield-Mask: 0x01)                 */
#define PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX_Pos (1UL)                 /*!< MMSOVRMCULGFX (Bit 1)                                 */
#define PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX_Msk (0x2UL)               /*!< MMSOVRMCULGFX (Bitfield-Mask: 0x01)                   */
#define PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP_Pos (0UL)                /*!< MMSOVRMCULDISP (Bit 0)                                */
#define PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP_Msk (0x1UL)              /*!< MMSOVRMCULDISP (Bitfield-Mask: 0x01)                  */
/* ======================================================  DSP0PWRCTRL  ====================================================== */
#define PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR_Pos (4UL)                  /*!< DSP0PCMRSTOR (Bit 4)                                  */
#define PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR_Msk (0x10UL)               /*!< DSP0PCMRSTOR (Bitfield-Mask: 0x01)                    */
#define PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTDLY_Pos (0UL)                 /*!< DSP0PCMRSTDLY (Bit 0)                                 */
#define PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTDLY_Msk (0xfUL)               /*!< DSP0PCMRSTDLY (Bitfield-Mask: 0x0f)                   */
/* ======================================================  DSP0PERFREQ  ====================================================== */
#define PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_Pos (3UL)                /*!< DSP0PERFSTATUS (Bit 3)                                */
#define PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_Msk (0x18UL)             /*!< DSP0PERFSTATUS (Bitfield-Mask: 0x03)                  */
#define PWRCTRL_DSP0PERFREQ_DSP0PERFACK_Pos (2UL)                   /*!< DSP0PERFACK (Bit 2)                                   */
#define PWRCTRL_DSP0PERFREQ_DSP0PERFACK_Msk (0x4UL)                 /*!< DSP0PERFACK (Bitfield-Mask: 0x01)                     */
#define PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_Pos (0UL)                   /*!< DSP0PERFREQ (Bit 0)                                   */
#define PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_Msk (0x3UL)                 /*!< DSP0PERFREQ (Bitfield-Mask: 0x03)                     */
/* =====================================================  DSP0MEMPWREN  ====================================================== */
#define PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE_Pos (1UL)              /*!< PWRENDSP0ICACHE (Bit 1)                               */
#define PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE_Msk (0x2UL)            /*!< PWRENDSP0ICACHE (Bitfield-Mask: 0x01)                 */
#define PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM_Pos (0UL)                 /*!< PWRENDSP0RAM (Bit 0)                                  */
#define PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM_Msk (0x1UL)               /*!< PWRENDSP0RAM (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0MEMPWRST  ====================================================== */
#define PWRCTRL_DSP0MEMPWRST_PWRSTDSP0ICACHE_Pos (1UL)              /*!< PWRSTDSP0ICACHE (Bit 1)                               */
#define PWRCTRL_DSP0MEMPWRST_PWRSTDSP0ICACHE_Msk (0x2UL)            /*!< PWRSTDSP0ICACHE (Bitfield-Mask: 0x01)                 */
#define PWRCTRL_DSP0MEMPWRST_PWRSTDSP0RAM_Pos (0UL)                 /*!< PWRSTDSP0RAM (Bit 0)                                  */
#define PWRCTRL_DSP0MEMPWRST_PWRSTDSP0RAM_Msk (0x1UL)               /*!< PWRSTDSP0RAM (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP0MEMRETCFG  ===================================================== */
#define PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX_Pos (4UL)               /*!< DSP0RAMACTGFX (Bit 4)                                 */
#define PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX_Msk (0x10UL)            /*!< DSP0RAMACTGFX (Bitfield-Mask: 0x01)                   */
#define PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP_Pos (3UL)              /*!< DSP0RAMACTDISP (Bit 3)                                */
#define PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP_Msk (0x8UL)            /*!< DSP0RAMACTDISP (Bitfield-Mask: 0x01)                  */
#define PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF_Pos (2UL)            /*!< ICACHEPWDDSP0OFF (Bit 2)                              */
#define PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF_Msk (0x4UL)          /*!< ICACHEPWDDSP0OFF (Bitfield-Mask: 0x01)                */
#define PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU_Pos (1UL)               /*!< DSP0RAMACTMCU (Bit 1)                                 */
#define PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU_Msk (0x2UL)             /*!< DSP0RAMACTMCU (Bitfield-Mask: 0x01)                   */
#define PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF_Pos (0UL)               /*!< RAMPWDDSP0OFF (Bit 0)                                 */
#define PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF_Msk (0x1UL)             /*!< RAMPWDDSP0OFF (Bitfield-Mask: 0x01)                   */
/* ======================================================  DSP1PWRCTRL  ====================================================== */
#define PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR_Pos (4UL)                  /*!< DSP1PCMRSTOR (Bit 4)                                  */
#define PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR_Msk (0x10UL)               /*!< DSP1PCMRSTOR (Bitfield-Mask: 0x01)                    */
#define PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTDLY_Pos (0UL)                 /*!< DSP1PCMRSTDLY (Bit 0)                                 */
#define PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTDLY_Msk (0xfUL)               /*!< DSP1PCMRSTDLY (Bitfield-Mask: 0x0f)                   */
/* ======================================================  DSP1PERFREQ  ====================================================== */
#define PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_Pos (3UL)                /*!< DSP1PERFSTATUS (Bit 3)                                */
#define PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_Msk (0x18UL)             /*!< DSP1PERFSTATUS (Bitfield-Mask: 0x03)                  */
#define PWRCTRL_DSP1PERFREQ_DSP1PERFACK_Pos (2UL)                   /*!< DSP1PERFACK (Bit 2)                                   */
#define PWRCTRL_DSP1PERFREQ_DSP1PERFACK_Msk (0x4UL)                 /*!< DSP1PERFACK (Bitfield-Mask: 0x01)                     */
#define PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_Pos (0UL)                   /*!< DSP1PERFREQ (Bit 0)                                   */
#define PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_Msk (0x3UL)                 /*!< DSP1PERFREQ (Bitfield-Mask: 0x03)                     */
/* =====================================================  DSP1MEMPWREN  ====================================================== */
#define PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE_Pos (1UL)              /*!< PWRENDSP1ICACHE (Bit 1)                               */
#define PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE_Msk (0x2UL)            /*!< PWRENDSP1ICACHE (Bitfield-Mask: 0x01)                 */
#define PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM_Pos (0UL)                 /*!< PWRENDSP1RAM (Bit 0)                                  */
#define PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM_Msk (0x1UL)               /*!< PWRENDSP1RAM (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1MEMPWRST  ====================================================== */
#define PWRCTRL_DSP1MEMPWRST_PWRSTDSP1ICACHE_Pos (1UL)              /*!< PWRSTDSP1ICACHE (Bit 1)                               */
#define PWRCTRL_DSP1MEMPWRST_PWRSTDSP1ICACHE_Msk (0x2UL)            /*!< PWRSTDSP1ICACHE (Bitfield-Mask: 0x01)                 */
#define PWRCTRL_DSP1MEMPWRST_PWRSTDSP1RAM_Pos (0UL)                 /*!< PWRSTDSP1RAM (Bit 0)                                  */
#define PWRCTRL_DSP1MEMPWRST_PWRSTDSP1RAM_Msk (0x1UL)               /*!< PWRSTDSP1RAM (Bitfield-Mask: 0x01)                    */
/* =====================================================  DSP1MEMRETCFG  ===================================================== */
#define PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX_Pos (4UL)               /*!< DSP1RAMACTGFX (Bit 4)                                 */
#define PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX_Msk (0x10UL)            /*!< DSP1RAMACTGFX (Bitfield-Mask: 0x01)                   */
#define PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP_Pos (3UL)              /*!< DSP1RAMACTDISP (Bit 3)                                */
#define PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP_Msk (0x8UL)            /*!< DSP1RAMACTDISP (Bitfield-Mask: 0x01)                  */
#define PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF_Pos (2UL)            /*!< ICACHEPWDDSP1OFF (Bit 2)                              */
#define PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF_Msk (0x4UL)          /*!< ICACHEPWDDSP1OFF (Bitfield-Mask: 0x01)                */
#define PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU_Pos (1UL)               /*!< DSP1RAMACTMCU (Bit 1)                                 */
#define PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU_Msk (0x2UL)             /*!< DSP1RAMACTMCU (Bitfield-Mask: 0x01)                   */
#define PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF_Pos (0UL)               /*!< RAMPWDDSP1OFF (Bit 0)                                 */
#define PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF_Msk (0x1UL)             /*!< RAMPWDDSP1OFF (Bitfield-Mask: 0x01)                   */
/* =======================================================  PWRACKOVR  ======================================================= */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDSPA_Pos (17UL)             /*!< PWRACKOVERRIDEDSPA (Bit 17)                           */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDSPA_Msk (0x20000UL)        /*!< PWRACKOVERRIDEDSPA (Bitfield-Mask: 0x01)              */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSBPHY_Pos (16UL)           /*!< PWRACKOVERRIDEUSBPHY (Bit 16)                         */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSBPHY_Msk (0x10000UL)      /*!< PWRACKOVERRIDEUSBPHY (Bitfield-Mask: 0x01)            */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSB_Pos (15UL)              /*!< PWRACKOVERRIDEUSB (Bit 15)                            */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSB_Msk (0x8000UL)          /*!< PWRACKOVERRIDEUSB (Bitfield-Mask: 0x01)               */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDESDIO_Pos (14UL)             /*!< PWRACKOVERRIDESDIO (Bit 14)                           */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDESDIO_Msk (0x4000UL)         /*!< PWRACKOVERRIDESDIO (Bitfield-Mask: 0x01)              */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMSPI_Pos (13UL)             /*!< PWRACKOVERRIDEMSPI (Bit 13)                           */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMSPI_Msk (0x2000UL)         /*!< PWRACKOVERRIDEMSPI (Bitfield-Mask: 0x01)              */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMCUL_Pos (12UL)             /*!< PWRACKOVERRIDEMCUL (Bit 12)                           */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMCUL_Msk (0x1000UL)         /*!< PWRACKOVERRIDEMCUL (Bitfield-Mask: 0x01)              */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEIOS_Pos (11UL)              /*!< PWRACKOVERRIDEIOS (Bit 11)                            */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEIOS_Msk (0x800UL)           /*!< PWRACKOVERRIDEIOS (Bitfield-Mask: 0x01)               */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPC_Pos (10UL)             /*!< PWRACKOVERRIDEHCPC (Bit 10)                           */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPC_Msk (0x400UL)          /*!< PWRACKOVERRIDEHCPC (Bitfield-Mask: 0x01)              */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPB_Pos (9UL)              /*!< PWRACKOVERRIDEHCPB (Bit 9)                            */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPB_Msk (0x200UL)          /*!< PWRACKOVERRIDEHCPB (Bitfield-Mask: 0x01)              */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPA_Pos (8UL)              /*!< PWRACKOVERRIDEHCPA (Bit 8)                            */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPA_Msk (0x100UL)          /*!< PWRACKOVERRIDEHCPA (Bitfield-Mask: 0x01)              */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEGFX_Pos (7UL)               /*!< PWRACKOVERRIDEGFX (Bit 7)                             */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEGFX_Msk (0x80UL)            /*!< PWRACKOVERRIDEGFX (Bitfield-Mask: 0x01)               */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISPPHY_Pos (6UL)           /*!< PWRACKOVERRIDEDISPPHY (Bit 6)                         */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISPPHY_Msk (0x40UL)        /*!< PWRACKOVERRIDEDISPPHY (Bitfield-Mask: 0x01)           */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISP_Pos (5UL)              /*!< PWRACKOVERRIDEDISP (Bit 5)                            */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISP_Msk (0x20UL)           /*!< PWRACKOVERRIDEDISP (Bitfield-Mask: 0x01)              */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDBG_Pos (4UL)               /*!< PWRACKOVERRIDEDBG (Bit 4)                             */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDBG_Msk (0x10UL)            /*!< PWRACKOVERRIDEDBG (Bitfield-Mask: 0x01)               */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDECRYPTO_Pos (3UL)            /*!< PWRACKOVERRIDECRYPTO (Bit 3)                          */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDECRYPTO_Msk (0x8UL)          /*!< PWRACKOVERRIDECRYPTO (Bitfield-Mask: 0x01)            */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUDADC_Pos (2UL)            /*!< PWRACKOVERRIDEAUDADC (Bit 2)                          */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUDADC_Msk (0x4UL)          /*!< PWRACKOVERRIDEAUDADC (Bitfield-Mask: 0x01)            */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUD_Pos (1UL)               /*!< PWRACKOVERRIDEAUD (Bit 1)                             */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUD_Msk (0x2UL)             /*!< PWRACKOVERRIDEAUD (Bitfield-Mask: 0x01)               */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEADC_Pos (0UL)               /*!< PWRACKOVERRIDEADC (Bit 0)                             */
#define PWRCTRL_PWRACKOVR_PWRACKOVERRIDEADC_Msk (0x1UL)             /*!< PWRACKOVERRIDEADC (Bitfield-Mask: 0x01)               */
/* =====================================================  PWRCNTDEFVAL  ====================================================== */
#define PWRCTRL_PWRCNTDEFVAL_PWRACKWAITDELSIMOSTMC_Pos (6UL)        /*!< PWRACKWAITDELSIMOSTMC (Bit 6)                         */
#define PWRCTRL_PWRCNTDEFVAL_PWRACKWAITDELSIMOSTMC_Msk (0xffc0UL)   /*!< PWRACKWAITDELSIMOSTMC (Bitfield-Mask: 0x3ff)          */
#define PWRCTRL_PWRCNTDEFVAL_PWRDEFVALDEVSTMC_Pos (0UL)             /*!< PWRDEFVALDEVSTMC (Bit 0)                              */
#define PWRCTRL_PWRCNTDEFVAL_PWRDEFVALDEVSTMC_Msk (0x3fUL)          /*!< PWRDEFVALDEVSTMC (Bitfield-Mask: 0x3f)                */
/* ========================================================  VRCTRL  ========================================================= */
#define PWRCTRL_VRCTRL_SIMOBUCKEN_Pos     (0UL)                     /*!< SIMOBUCKEN (Bit 0)                                    */
#define PWRCTRL_VRCTRL_SIMOBUCKEN_Msk     (0x1UL)                   /*!< SIMOBUCKEN (Bitfield-Mask: 0x01)                      */
/* =====================================================  LEGACYVRLPOVR  ===================================================== */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREDBG_Pos (18UL)                  /*!< IGNOREDBG (Bit 18)                                    */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREDBG_Msk (0x40000UL)             /*!< IGNOREDBG (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREAUD_Pos (14UL)                  /*!< IGNOREAUD (Bit 14)                                    */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREAUD_Msk (0x4000UL)              /*!< IGNOREAUD (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_LEGACYVRLPOVR_IGNORESDIO_Pos (11UL)                 /*!< IGNORESDIO (Bit 11)                                   */
#define PWRCTRL_LEGACYVRLPOVR_IGNORESDIO_Msk (0x800UL)              /*!< IGNORESDIO (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_LEGACYVRLPOVR_IGNORECRYPTO_Pos (10UL)               /*!< IGNORECRYPTO (Bit 10)                                 */
#define PWRCTRL_LEGACYVRLPOVR_IGNORECRYPTO_Msk (0x400UL)            /*!< IGNORECRYPTO (Bitfield-Mask: 0x01)                    */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREGFX_Pos (7UL)                   /*!< IGNOREGFX (Bit 7)                                     */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREGFX_Msk (0x80UL)                /*!< IGNOREGFX (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREMSPI_Pos (6UL)                  /*!< IGNOREMSPI (Bit 6)                                    */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREMSPI_Msk (0x40UL)               /*!< IGNOREMSPI (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPE_Pos (5UL)                  /*!< IGNOREHCPE (Bit 5)                                    */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPE_Msk (0x20UL)               /*!< IGNOREHCPE (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPD_Pos (4UL)                  /*!< IGNOREHCPD (Bit 4)                                    */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPD_Msk (0x10UL)               /*!< IGNOREHCPD (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPC_Pos (3UL)                  /*!< IGNOREHCPC (Bit 3)                                    */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPC_Msk (0x8UL)                /*!< IGNOREHCPC (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPB_Pos (2UL)                  /*!< IGNOREHCPB (Bit 2)                                    */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPB_Msk (0x4UL)                /*!< IGNOREHCPB (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPA_Pos (1UL)                  /*!< IGNOREHCPA (Bit 1)                                    */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREHCPA_Msk (0x2UL)                /*!< IGNOREHCPA (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREIOS_Pos (0UL)                   /*!< IGNOREIOS (Bit 0)                                     */
#define PWRCTRL_LEGACYVRLPOVR_IGNOREIOS_Msk (0x1UL)                 /*!< IGNOREIOS (Bitfield-Mask: 0x01)                       */
/* =======================================================  VRSTATUS  ======================================================== */
#define PWRCTRL_VRSTATUS_SIMOBUCKST_Pos   (4UL)                     /*!< SIMOBUCKST (Bit 4)                                    */
#define PWRCTRL_VRSTATUS_SIMOBUCKST_Msk   (0x30UL)                  /*!< SIMOBUCKST (Bitfield-Mask: 0x03)                      */
#define PWRCTRL_VRSTATUS_MEMLDOST_Pos     (2UL)                     /*!< MEMLDOST (Bit 2)                                      */
#define PWRCTRL_VRSTATUS_MEMLDOST_Msk     (0xcUL)                   /*!< MEMLDOST (Bitfield-Mask: 0x03)                        */
#define PWRCTRL_VRSTATUS_CORELDOST_Pos    (0UL)                     /*!< CORELDOST (Bit 0)                                     */
#define PWRCTRL_VRSTATUS_CORELDOST_Msk    (0x3UL)                   /*!< CORELDOST (Bitfield-Mask: 0x03)                       */
/* =======================================================  SRAMCTRL  ======================================================== */
#define PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Pos (8UL)                   /*!< SRAMLIGHTSLEEP (Bit 8)                                */
#define PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Msk (0xfff00UL)             /*!< SRAMLIGHTSLEEP (Bitfield-Mask: 0xfff)                 */
#define PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Pos (2UL)                /*!< SRAMMASTERCLKGATE (Bit 2)                             */
#define PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Msk (0x4UL)              /*!< SRAMMASTERCLKGATE (Bitfield-Mask: 0x01)               */
#define PWRCTRL_SRAMCTRL_SRAMCLKGATE_Pos  (1UL)                     /*!< SRAMCLKGATE (Bit 1)                                   */
#define PWRCTRL_SRAMCTRL_SRAMCLKGATE_Msk  (0x2UL)                   /*!< SRAMCLKGATE (Bitfield-Mask: 0x01)                     */
/* =======================================================  ADCSTATUS  ======================================================= */
#define PWRCTRL_ADCSTATUS_REFBUFPWD_Pos   (5UL)                     /*!< REFBUFPWD (Bit 5)                                     */
#define PWRCTRL_ADCSTATUS_REFBUFPWD_Msk   (0x20UL)                  /*!< REFBUFPWD (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_ADCSTATUS_REFKEEPPWD_Pos  (4UL)                     /*!< REFKEEPPWD (Bit 4)                                    */
#define PWRCTRL_ADCSTATUS_REFKEEPPWD_Msk  (0x10UL)                  /*!< REFKEEPPWD (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_ADCSTATUS_VBATPWD_Pos     (3UL)                     /*!< VBATPWD (Bit 3)                                       */
#define PWRCTRL_ADCSTATUS_VBATPWD_Msk     (0x8UL)                   /*!< VBATPWD (Bitfield-Mask: 0x01)                         */
#define PWRCTRL_ADCSTATUS_VPTATPWD_Pos    (2UL)                     /*!< VPTATPWD (Bit 2)                                      */
#define PWRCTRL_ADCSTATUS_VPTATPWD_Msk    (0x4UL)                   /*!< VPTATPWD (Bitfield-Mask: 0x01)                        */
#define PWRCTRL_ADCSTATUS_BGTPWD_Pos      (1UL)                     /*!< BGTPWD (Bit 1)                                        */
#define PWRCTRL_ADCSTATUS_BGTPWD_Msk      (0x2UL)                   /*!< BGTPWD (Bitfield-Mask: 0x01)                          */
#define PWRCTRL_ADCSTATUS_ADCPWD_Pos      (0UL)                     /*!< ADCPWD (Bit 0)                                        */
#define PWRCTRL_ADCSTATUS_ADCPWD_Msk      (0x1UL)                   /*!< ADCPWD (Bitfield-Mask: 0x01)                          */
/* =====================================================  AUDADCSTATUS  ====================================================== */
#define PWRCTRL_AUDADCSTATUS_AUDREFBUFPWD_Pos (5UL)                 /*!< AUDREFBUFPWD (Bit 5)                                  */
#define PWRCTRL_AUDADCSTATUS_AUDREFBUFPWD_Msk (0x20UL)              /*!< AUDREFBUFPWD (Bitfield-Mask: 0x01)                    */
#define PWRCTRL_AUDADCSTATUS_AUDREFKEEPPWD_Pos (4UL)                /*!< AUDREFKEEPPWD (Bit 4)                                 */
#define PWRCTRL_AUDADCSTATUS_AUDREFKEEPPWD_Msk (0x10UL)             /*!< AUDREFKEEPPWD (Bitfield-Mask: 0x01)                   */
#define PWRCTRL_AUDADCSTATUS_AUDVBATPWD_Pos (3UL)                   /*!< AUDVBATPWD (Bit 3)                                    */
#define PWRCTRL_AUDADCSTATUS_AUDVBATPWD_Msk (0x8UL)                 /*!< AUDVBATPWD (Bitfield-Mask: 0x01)                      */
#define PWRCTRL_AUDADCSTATUS_AUDVPTATPWD_Pos (2UL)                  /*!< AUDVPTATPWD (Bit 2)                                   */
#define PWRCTRL_AUDADCSTATUS_AUDVPTATPWD_Msk (0x4UL)                /*!< AUDVPTATPWD (Bitfield-Mask: 0x01)                     */
#define PWRCTRL_AUDADCSTATUS_AUDBGTPWD_Pos (1UL)                    /*!< AUDBGTPWD (Bit 1)                                     */
#define PWRCTRL_AUDADCSTATUS_AUDBGTPWD_Msk (0x2UL)                  /*!< AUDBGTPWD (Bitfield-Mask: 0x01)                       */
#define PWRCTRL_AUDADCSTATUS_AUDADCPWD_Pos (0UL)                    /*!< AUDADCPWD (Bit 0)                                     */
#define PWRCTRL_AUDADCSTATUS_AUDADCPWD_Msk (0x1UL)                  /*!< AUDADCPWD (Bitfield-Mask: 0x01)                       */
/* =======================================================  EMONCTRL  ======================================================== */
#define PWRCTRL_EMONCTRL_CLEAR_Pos        (8UL)                     /*!< CLEAR (Bit 8)                                         */
#define PWRCTRL_EMONCTRL_CLEAR_Msk        (0xff00UL)                /*!< CLEAR (Bitfield-Mask: 0xff)                           */
#define PWRCTRL_EMONCTRL_FREEZE_Pos       (0UL)                     /*!< FREEZE (Bit 0)                                        */
#define PWRCTRL_EMONCTRL_FREEZE_Msk       (0xffUL)                  /*!< FREEZE (Bitfield-Mask: 0xff)                          */
/* =======================================================  EMONCFG0  ======================================================== */
#define PWRCTRL_EMONCFG0_EMONSEL0_Pos     (0UL)                     /*!< EMONSEL0 (Bit 0)                                      */
#define PWRCTRL_EMONCFG0_EMONSEL0_Msk     (0xffUL)                  /*!< EMONSEL0 (Bitfield-Mask: 0xff)                        */
/* =======================================================  EMONCFG1  ======================================================== */
#define PWRCTRL_EMONCFG1_EMONSEL1_Pos     (0UL)                     /*!< EMONSEL1 (Bit 0)                                      */
#define PWRCTRL_EMONCFG1_EMONSEL1_Msk     (0xffUL)                  /*!< EMONSEL1 (Bitfield-Mask: 0xff)                        */
/* =======================================================  EMONCFG2  ======================================================== */
#define PWRCTRL_EMONCFG2_EMONSEL2_Pos     (0UL)                     /*!< EMONSEL2 (Bit 0)                                      */
#define PWRCTRL_EMONCFG2_EMONSEL2_Msk     (0xffUL)                  /*!< EMONSEL2 (Bitfield-Mask: 0xff)                        */
/* =======================================================  EMONCFG3  ======================================================== */
#define PWRCTRL_EMONCFG3_EMONSEL3_Pos     (0UL)                     /*!< EMONSEL3 (Bit 0)                                      */
#define PWRCTRL_EMONCFG3_EMONSEL3_Msk     (0xffUL)                  /*!< EMONSEL3 (Bitfield-Mask: 0xff)                        */
/* =======================================================  EMONCFG4  ======================================================== */
#define PWRCTRL_EMONCFG4_EMONSEL4_Pos     (0UL)                     /*!< EMONSEL4 (Bit 0)                                      */
#define PWRCTRL_EMONCFG4_EMONSEL4_Msk     (0xffUL)                  /*!< EMONSEL4 (Bitfield-Mask: 0xff)                        */
/* =======================================================  EMONCFG5  ======================================================== */
#define PWRCTRL_EMONCFG5_EMONSEL5_Pos     (0UL)                     /*!< EMONSEL5 (Bit 0)                                      */
#define PWRCTRL_EMONCFG5_EMONSEL5_Msk     (0xffUL)                  /*!< EMONSEL5 (Bitfield-Mask: 0xff)                        */
/* =======================================================  EMONCFG6  ======================================================== */
#define PWRCTRL_EMONCFG6_EMONSEL6_Pos     (0UL)                     /*!< EMONSEL6 (Bit 0)                                      */
#define PWRCTRL_EMONCFG6_EMONSEL6_Msk     (0xffUL)                  /*!< EMONSEL6 (Bitfield-Mask: 0xff)                        */
/* =======================================================  EMONCFG7  ======================================================== */
#define PWRCTRL_EMONCFG7_EMONSEL7_Pos     (0UL)                     /*!< EMONSEL7 (Bit 0)                                      */
#define PWRCTRL_EMONCFG7_EMONSEL7_Msk     (0xffUL)                  /*!< EMONSEL7 (Bitfield-Mask: 0xff)                        */
/* ======================================================  EMONCOUNT0  ======================================================= */
#define PWRCTRL_EMONCOUNT0_EMONCOUNT0_Pos (0UL)                     /*!< EMONCOUNT0 (Bit 0)                                    */
#define PWRCTRL_EMONCOUNT0_EMONCOUNT0_Msk (0xffffffffUL)            /*!< EMONCOUNT0 (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  EMONCOUNT1  ======================================================= */
#define PWRCTRL_EMONCOUNT1_EMONCOUNT1_Pos (0UL)                     /*!< EMONCOUNT1 (Bit 0)                                    */
#define PWRCTRL_EMONCOUNT1_EMONCOUNT1_Msk (0xffffffffUL)            /*!< EMONCOUNT1 (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  EMONCOUNT2  ======================================================= */
#define PWRCTRL_EMONCOUNT2_EMONCOUNT2_Pos (0UL)                     /*!< EMONCOUNT2 (Bit 0)                                    */
#define PWRCTRL_EMONCOUNT2_EMONCOUNT2_Msk (0xffffffffUL)            /*!< EMONCOUNT2 (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  EMONCOUNT3  ======================================================= */
#define PWRCTRL_EMONCOUNT3_EMONCOUNT3_Pos (0UL)                     /*!< EMONCOUNT3 (Bit 0)                                    */
#define PWRCTRL_EMONCOUNT3_EMONCOUNT3_Msk (0xffffffffUL)            /*!< EMONCOUNT3 (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  EMONCOUNT4  ======================================================= */
#define PWRCTRL_EMONCOUNT4_EMONCOUNT4_Pos (0UL)                     /*!< EMONCOUNT4 (Bit 0)                                    */
#define PWRCTRL_EMONCOUNT4_EMONCOUNT4_Msk (0xffffffffUL)            /*!< EMONCOUNT4 (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  EMONCOUNT5  ======================================================= */
#define PWRCTRL_EMONCOUNT5_EMONCOUNT5_Pos (0UL)                     /*!< EMONCOUNT5 (Bit 0)                                    */
#define PWRCTRL_EMONCOUNT5_EMONCOUNT5_Msk (0xffffffffUL)            /*!< EMONCOUNT5 (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  EMONCOUNT6  ======================================================= */
#define PWRCTRL_EMONCOUNT6_EMONCOUNT6_Pos (0UL)                     /*!< EMONCOUNT6 (Bit 0)                                    */
#define PWRCTRL_EMONCOUNT6_EMONCOUNT6_Msk (0xffffffffUL)            /*!< EMONCOUNT6 (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  EMONCOUNT7  ======================================================= */
#define PWRCTRL_EMONCOUNT7_EMONCOUNT7_Pos (0UL)                     /*!< EMONCOUNT7 (Bit 0)                                    */
#define PWRCTRL_EMONCOUNT7_EMONCOUNT7_Msk (0xffffffffUL)            /*!< EMONCOUNT7 (Bitfield-Mask: 0xffffffff)                */
/* ======================================================  EMONSTATUS  ======================================================= */
#define PWRCTRL_EMONSTATUS_EMONOVERFLOW7_Pos (7UL)                  /*!< EMONOVERFLOW7 (Bit 7)                                 */
#define PWRCTRL_EMONSTATUS_EMONOVERFLOW7_Msk (0x80UL)               /*!< EMONOVERFLOW7 (Bitfield-Mask: 0x01)                   */
#define PWRCTRL_EMONSTATUS_EMONOVERFLOW6_Pos (6UL)                  /*!< EMONOVERFLOW6 (Bit 6)                                 */
#define PWRCTRL_EMONSTATUS_EMONOVERFLOW6_Msk (0x40UL)               /*!< EMONOVERFLOW6 (Bitfield-Mask: 0x01)                   */
#define PWRCTRL_EMONSTATUS_EMONOVERFLOW5_Pos (5UL)                  /*!< EMONOVERFLOW5 (Bit 5)                                 */
#define PWRCTRL_EMONSTATUS_EMONOVERFLOW5_Msk (0x20UL)               /*!< EMONOVERFLOW5 (Bitfield-Mask: 0x01)                   */
#define PWRCTRL_EMONSTATUS_EMONOVERFLOW4_Pos (4UL)                  /*!< EMONOVERFLOW4 (Bit 4)                                 */
#define PWRCTRL_EMONSTATUS_EMONOVERFLOW4_Msk (0x10UL)               /*!< EMONOVERFLOW4 (Bitfield-Mask: 0x01)                   */
#define PWRCTRL_EMONSTATUS_EMONOVERFLOW3_Pos (3UL)                  /*!< EMONOVERFLOW3 (Bit 3)                                 */
#define PWRCTRL_EMONSTATUS_EMONOVERFLOW3_Msk (0x8UL)                /*!< EMONOVERFLOW3 (Bitfield-Mask: 0x01)                   */
#define PWRCTRL_EMONSTATUS_EMONOVERFLOW2_Pos (2UL)                  /*!< EMONOVERFLOW2 (Bit 2)                                 */
#define PWRCTRL_EMONSTATUS_EMONOVERFLOW2_Msk (0x4UL)                /*!< EMONOVERFLOW2 (Bitfield-Mask: 0x01)                   */
#define PWRCTRL_EMONSTATUS_EMONOVERFLOW1_Pos (1UL)                  /*!< EMONOVERFLOW1 (Bit 1)                                 */
#define PWRCTRL_EMONSTATUS_EMONOVERFLOW1_Msk (0x2UL)                /*!< EMONOVERFLOW1 (Bitfield-Mask: 0x01)                   */
#define PWRCTRL_EMONSTATUS_EMONOVERFLOW0_Pos (0UL)                  /*!< EMONOVERFLOW0 (Bit 0)                                 */
#define PWRCTRL_EMONSTATUS_EMONOVERFLOW0_Msk (0x1UL)                /*!< EMONOVERFLOW0 (Bitfield-Mask: 0x01)                   */


/* =========================================================================================================================== */
/* ================                                          RSTGEN                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  CFG  ========================================================== */
#define RSTGEN_CFG_WDREN_Pos              (1UL)                     /*!< WDREN (Bit 1)                                         */
#define RSTGEN_CFG_WDREN_Msk              (0x2UL)                   /*!< WDREN (Bitfield-Mask: 0x01)                           */
#define RSTGEN_CFG_BODHREN_Pos            (0UL)                     /*!< BODHREN (Bit 0)                                       */
#define RSTGEN_CFG_BODHREN_Msk            (0x1UL)                   /*!< BODHREN (Bitfield-Mask: 0x01)                         */
/* =========================================================  SWPOI  ========================================================= */
#define RSTGEN_SWPOI_SWPOIKEY_Pos         (0UL)                     /*!< SWPOIKEY (Bit 0)                                      */
#define RSTGEN_SWPOI_SWPOIKEY_Msk         (0xffUL)                  /*!< SWPOIKEY (Bitfield-Mask: 0xff)                        */
/* =========================================================  SWPOR  ========================================================= */
#define RSTGEN_SWPOR_SWPORKEY_Pos         (0UL)                     /*!< SWPORKEY (Bit 0)                                      */
#define RSTGEN_SWPOR_SWPORKEY_Msk         (0xffUL)                  /*!< SWPORKEY (Bitfield-Mask: 0xff)                        */
/* =======================================================  SIMOBODM  ======================================================== */
#define RSTGEN_SIMOBODM_DIGBOECLV_Pos     (3UL)                     /*!< DIGBOECLV (Bit 3)                                     */
#define RSTGEN_SIMOBODM_DIGBOECLV_Msk     (0x8UL)                   /*!< DIGBOECLV (Bitfield-Mask: 0x01)                       */
#define RSTGEN_SIMOBODM_DIGBOES_Pos       (2UL)                     /*!< DIGBOES (Bit 2)                                       */
#define RSTGEN_SIMOBODM_DIGBOES_Msk       (0x4UL)                   /*!< DIGBOES (Bitfield-Mask: 0x01)                         */
#define RSTGEN_SIMOBODM_DIGBOEF_Pos       (1UL)                     /*!< DIGBOEF (Bit 1)                                       */
#define RSTGEN_SIMOBODM_DIGBOEF_Msk       (0x2UL)                   /*!< DIGBOEF (Bitfield-Mask: 0x01)                         */
#define RSTGEN_SIMOBODM_DIGBOEC_Pos       (0UL)                     /*!< DIGBOEC (Bit 0)                                       */
#define RSTGEN_SIMOBODM_DIGBOEC_Msk       (0x1UL)                   /*!< DIGBOEC (Bitfield-Mask: 0x01)                         */
/* =========================================================  INTEN  ========================================================= */
#define RSTGEN_INTEN_BODDIGCLV_Pos        (4UL)                     /*!< BODDIGCLV (Bit 4)                                     */
#define RSTGEN_INTEN_BODDIGCLV_Msk        (0x10UL)                  /*!< BODDIGCLV (Bitfield-Mask: 0x01)                       */
#define RSTGEN_INTEN_BODDIGS_Pos          (3UL)                     /*!< BODDIGS (Bit 3)                                       */
#define RSTGEN_INTEN_BODDIGS_Msk          (0x8UL)                   /*!< BODDIGS (Bitfield-Mask: 0x01)                         */
#define RSTGEN_INTEN_BODDIGF_Pos          (2UL)                     /*!< BODDIGF (Bit 2)                                       */
#define RSTGEN_INTEN_BODDIGF_Msk          (0x4UL)                   /*!< BODDIGF (Bitfield-Mask: 0x01)                         */
#define RSTGEN_INTEN_BODDIGC_Pos          (1UL)                     /*!< BODDIGC (Bit 1)                                       */
#define RSTGEN_INTEN_BODDIGC_Msk          (0x2UL)                   /*!< BODDIGC (Bitfield-Mask: 0x01)                         */
#define RSTGEN_INTEN_BODH_Pos             (0UL)                     /*!< BODH (Bit 0)                                          */
#define RSTGEN_INTEN_BODH_Msk             (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
/* ========================================================  INTSTAT  ======================================================== */
#define RSTGEN_INTSTAT_BODDIGCLV_Pos      (4UL)                     /*!< BODDIGCLV (Bit 4)                                     */
#define RSTGEN_INTSTAT_BODDIGCLV_Msk      (0x10UL)                  /*!< BODDIGCLV (Bitfield-Mask: 0x01)                       */
#define RSTGEN_INTSTAT_BODDIGS_Pos        (3UL)                     /*!< BODDIGS (Bit 3)                                       */
#define RSTGEN_INTSTAT_BODDIGS_Msk        (0x8UL)                   /*!< BODDIGS (Bitfield-Mask: 0x01)                         */
#define RSTGEN_INTSTAT_BODDIGF_Pos        (2UL)                     /*!< BODDIGF (Bit 2)                                       */
#define RSTGEN_INTSTAT_BODDIGF_Msk        (0x4UL)                   /*!< BODDIGF (Bitfield-Mask: 0x01)                         */
#define RSTGEN_INTSTAT_BODDIGC_Pos        (1UL)                     /*!< BODDIGC (Bit 1)                                       */
#define RSTGEN_INTSTAT_BODDIGC_Msk        (0x2UL)                   /*!< BODDIGC (Bitfield-Mask: 0x01)                         */
#define RSTGEN_INTSTAT_BODH_Pos           (0UL)                     /*!< BODH (Bit 0)                                          */
#define RSTGEN_INTSTAT_BODH_Msk           (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
/* ========================================================  INTCLR  ========================================================= */
#define RSTGEN_INTCLR_BODDIGCLV_Pos       (4UL)                     /*!< BODDIGCLV (Bit 4)                                     */
#define RSTGEN_INTCLR_BODDIGCLV_Msk       (0x10UL)                  /*!< BODDIGCLV (Bitfield-Mask: 0x01)                       */
#define RSTGEN_INTCLR_BODDIGS_Pos         (3UL)                     /*!< BODDIGS (Bit 3)                                       */
#define RSTGEN_INTCLR_BODDIGS_Msk         (0x8UL)                   /*!< BODDIGS (Bitfield-Mask: 0x01)                         */
#define RSTGEN_INTCLR_BODDIGF_Pos         (2UL)                     /*!< BODDIGF (Bit 2)                                       */
#define RSTGEN_INTCLR_BODDIGF_Msk         (0x4UL)                   /*!< BODDIGF (Bitfield-Mask: 0x01)                         */
#define RSTGEN_INTCLR_BODDIGC_Pos         (1UL)                     /*!< BODDIGC (Bit 1)                                       */
#define RSTGEN_INTCLR_BODDIGC_Msk         (0x2UL)                   /*!< BODDIGC (Bitfield-Mask: 0x01)                         */
#define RSTGEN_INTCLR_BODH_Pos            (0UL)                     /*!< BODH (Bit 0)                                          */
#define RSTGEN_INTCLR_BODH_Msk            (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
/* ========================================================  INTSET  ========================================================= */
#define RSTGEN_INTSET_BODDIGCLV_Pos       (4UL)                     /*!< BODDIGCLV (Bit 4)                                     */
#define RSTGEN_INTSET_BODDIGCLV_Msk       (0x10UL)                  /*!< BODDIGCLV (Bitfield-Mask: 0x01)                       */
#define RSTGEN_INTSET_BODDIGS_Pos         (3UL)                     /*!< BODDIGS (Bit 3)                                       */
#define RSTGEN_INTSET_BODDIGS_Msk         (0x8UL)                   /*!< BODDIGS (Bitfield-Mask: 0x01)                         */
#define RSTGEN_INTSET_BODDIGF_Pos         (2UL)                     /*!< BODDIGF (Bit 2)                                       */
#define RSTGEN_INTSET_BODDIGF_Msk         (0x4UL)                   /*!< BODDIGF (Bitfield-Mask: 0x01)                         */
#define RSTGEN_INTSET_BODDIGC_Pos         (1UL)                     /*!< BODDIGC (Bit 1)                                       */
#define RSTGEN_INTSET_BODDIGC_Msk         (0x2UL)                   /*!< BODDIGC (Bitfield-Mask: 0x01)                         */
#define RSTGEN_INTSET_BODH_Pos            (0UL)                     /*!< BODH (Bit 0)                                          */
#define RSTGEN_INTSET_BODH_Msk            (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
/* =========================================================  STAT  ========================================================== */
#define RSTGEN_STAT_BOSSTAT_Pos           (10UL)                    /*!< BOSSTAT (Bit 10)                                      */
#define RSTGEN_STAT_BOSSTAT_Msk           (0x400UL)                 /*!< BOSSTAT (Bitfield-Mask: 0x01)                         */
#define RSTGEN_STAT_BOFSTAT_Pos           (9UL)                     /*!< BOFSTAT (Bit 9)                                       */
#define RSTGEN_STAT_BOFSTAT_Msk           (0x200UL)                 /*!< BOFSTAT (Bitfield-Mask: 0x01)                         */
#define RSTGEN_STAT_BOCSTAT_Pos           (8UL)                     /*!< BOCSTAT (Bit 8)                                       */
#define RSTGEN_STAT_BOCSTAT_Msk           (0x100UL)                 /*!< BOCSTAT (Bitfield-Mask: 0x01)                         */
#define RSTGEN_STAT_BOUSTAT_Pos           (7UL)                     /*!< BOUSTAT (Bit 7)                                       */
#define RSTGEN_STAT_BOUSTAT_Msk           (0x80UL)                  /*!< BOUSTAT (Bitfield-Mask: 0x01)                         */
#define RSTGEN_STAT_WDRSTAT_Pos           (6UL)                     /*!< WDRSTAT (Bit 6)                                       */
#define RSTGEN_STAT_WDRSTAT_Msk           (0x40UL)                  /*!< WDRSTAT (Bitfield-Mask: 0x01)                         */
#define RSTGEN_STAT_DBGRSTAT_Pos          (5UL)                     /*!< DBGRSTAT (Bit 5)                                      */
#define RSTGEN_STAT_DBGRSTAT_Msk          (0x20UL)                  /*!< DBGRSTAT (Bitfield-Mask: 0x01)                        */
#define RSTGEN_STAT_POIRSTAT_Pos          (4UL)                     /*!< POIRSTAT (Bit 4)                                      */
#define RSTGEN_STAT_POIRSTAT_Msk          (0x10UL)                  /*!< POIRSTAT (Bitfield-Mask: 0x01)                        */
#define RSTGEN_STAT_SWRSTAT_Pos           (3UL)                     /*!< SWRSTAT (Bit 3)                                       */
#define RSTGEN_STAT_SWRSTAT_Msk           (0x8UL)                   /*!< SWRSTAT (Bitfield-Mask: 0x01)                         */
#define RSTGEN_STAT_BORSTAT_Pos           (2UL)                     /*!< BORSTAT (Bit 2)                                       */
#define RSTGEN_STAT_BORSTAT_Msk           (0x4UL)                   /*!< BORSTAT (Bitfield-Mask: 0x01)                         */
#define RSTGEN_STAT_PORSTAT_Pos           (1UL)                     /*!< PORSTAT (Bit 1)                                       */
#define RSTGEN_STAT_PORSTAT_Msk           (0x2UL)                   /*!< PORSTAT (Bitfield-Mask: 0x01)                         */
#define RSTGEN_STAT_EXRSTAT_Pos           (0UL)                     /*!< EXRSTAT (Bit 0)                                       */
#define RSTGEN_STAT_EXRSTAT_Msk           (0x1UL)                   /*!< EXRSTAT (Bitfield-Mask: 0x01)                         */


/* =========================================================================================================================== */
/* ================                                            RTC                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  RTCCTL  ========================================================= */
#define RTC_RTCCTL_HR1224_Pos             (5UL)                     /*!< HR1224 (Bit 5)                                        */
#define RTC_RTCCTL_HR1224_Msk             (0x20UL)                  /*!< HR1224 (Bitfield-Mask: 0x01)                          */
#define RTC_RTCCTL_RSTOP_Pos              (4UL)                     /*!< RSTOP (Bit 4)                                         */
#define RTC_RTCCTL_RSTOP_Msk              (0x10UL)                  /*!< RSTOP (Bitfield-Mask: 0x01)                           */
#define RTC_RTCCTL_RPT_Pos                (1UL)                     /*!< RPT (Bit 1)                                           */
#define RTC_RTCCTL_RPT_Msk                (0xeUL)                   /*!< RPT (Bitfield-Mask: 0x07)                             */
#define RTC_RTCCTL_WRTC_Pos               (0UL)                     /*!< WRTC (Bit 0)                                          */
#define RTC_RTCCTL_WRTC_Msk               (0x1UL)                   /*!< WRTC (Bitfield-Mask: 0x01)                            */
/* ========================================================  RTCSTAT  ======================================================== */
#define RTC_RTCSTAT_WRITEBUSY_Pos         (0UL)                     /*!< WRITEBUSY (Bit 0)                                     */
#define RTC_RTCSTAT_WRITEBUSY_Msk         (0x1UL)                   /*!< WRITEBUSY (Bitfield-Mask: 0x01)                       */
/* ========================================================  CTRLOW  ========================================================= */
#define RTC_CTRLOW_CTRHR_Pos              (24UL)                    /*!< CTRHR (Bit 24)                                        */
#define RTC_CTRLOW_CTRHR_Msk              (0x3f000000UL)            /*!< CTRHR (Bitfield-Mask: 0x3f)                           */
#define RTC_CTRLOW_CTRMIN_Pos             (16UL)                    /*!< CTRMIN (Bit 16)                                       */
#define RTC_CTRLOW_CTRMIN_Msk             (0x7f0000UL)              /*!< CTRMIN (Bitfield-Mask: 0x7f)                          */
#define RTC_CTRLOW_CTRSEC_Pos             (8UL)                     /*!< CTRSEC (Bit 8)                                        */
#define RTC_CTRLOW_CTRSEC_Msk             (0x7f00UL)                /*!< CTRSEC (Bitfield-Mask: 0x7f)                          */
#define RTC_CTRLOW_CTR100_Pos             (0UL)                     /*!< CTR100 (Bit 0)                                        */
#define RTC_CTRLOW_CTR100_Msk             (0xffUL)                  /*!< CTR100 (Bitfield-Mask: 0xff)                          */
/* =========================================================  CTRUP  ========================================================= */
#define RTC_CTRUP_CTERR_Pos               (31UL)                    /*!< CTERR (Bit 31)                                        */
#define RTC_CTRUP_CTERR_Msk               (0x80000000UL)            /*!< CTERR (Bitfield-Mask: 0x01)                           */
#define RTC_CTRUP_CEB_Pos                 (29UL)                    /*!< CEB (Bit 29)                                          */
#define RTC_CTRUP_CEB_Msk                 (0x20000000UL)            /*!< CEB (Bitfield-Mask: 0x01)                             */
#define RTC_CTRUP_CB_Pos                  (28UL)                    /*!< CB (Bit 28)                                           */
#define RTC_CTRUP_CB_Msk                  (0x10000000UL)            /*!< CB (Bitfield-Mask: 0x01)                              */
#define RTC_CTRUP_CTRWKDY_Pos             (24UL)                    /*!< CTRWKDY (Bit 24)                                      */
#define RTC_CTRUP_CTRWKDY_Msk             (0x7000000UL)             /*!< CTRWKDY (Bitfield-Mask: 0x07)                         */
#define RTC_CTRUP_CTRYR_Pos               (16UL)                    /*!< CTRYR (Bit 16)                                        */
#define RTC_CTRUP_CTRYR_Msk               (0xff0000UL)              /*!< CTRYR (Bitfield-Mask: 0xff)                           */
#define RTC_CTRUP_CTRMO_Pos               (8UL)                     /*!< CTRMO (Bit 8)                                         */
#define RTC_CTRUP_CTRMO_Msk               (0x1f00UL)                /*!< CTRMO (Bitfield-Mask: 0x1f)                           */
#define RTC_CTRUP_CTRDATE_Pos             (0UL)                     /*!< CTRDATE (Bit 0)                                       */
#define RTC_CTRUP_CTRDATE_Msk             (0x3fUL)                  /*!< CTRDATE (Bitfield-Mask: 0x3f)                         */
/* ========================================================  ALMLOW  ========================================================= */
#define RTC_ALMLOW_ALMHR_Pos              (24UL)                    /*!< ALMHR (Bit 24)                                        */
#define RTC_ALMLOW_ALMHR_Msk              (0x3f000000UL)            /*!< ALMHR (Bitfield-Mask: 0x3f)                           */
#define RTC_ALMLOW_ALMMIN_Pos             (16UL)                    /*!< ALMMIN (Bit 16)                                       */
#define RTC_ALMLOW_ALMMIN_Msk             (0x7f0000UL)              /*!< ALMMIN (Bitfield-Mask: 0x7f)                          */
#define RTC_ALMLOW_ALMSEC_Pos             (8UL)                     /*!< ALMSEC (Bit 8)                                        */
#define RTC_ALMLOW_ALMSEC_Msk             (0x7f00UL)                /*!< ALMSEC (Bitfield-Mask: 0x7f)                          */
#define RTC_ALMLOW_ALM100_Pos             (0UL)                     /*!< ALM100 (Bit 0)                                        */
#define RTC_ALMLOW_ALM100_Msk             (0xffUL)                  /*!< ALM100 (Bitfield-Mask: 0xff)                          */
/* =========================================================  ALMUP  ========================================================= */
#define RTC_ALMUP_ALMWKDY_Pos             (16UL)                    /*!< ALMWKDY (Bit 16)                                      */
#define RTC_ALMUP_ALMWKDY_Msk             (0x70000UL)               /*!< ALMWKDY (Bitfield-Mask: 0x07)                         */
#define RTC_ALMUP_ALMMO_Pos               (8UL)                     /*!< ALMMO (Bit 8)                                         */
#define RTC_ALMUP_ALMMO_Msk               (0x1f00UL)                /*!< ALMMO (Bitfield-Mask: 0x1f)                           */
#define RTC_ALMUP_ALMDATE_Pos             (0UL)                     /*!< ALMDATE (Bit 0)                                       */
#define RTC_ALMUP_ALMDATE_Msk             (0x3fUL)                  /*!< ALMDATE (Bitfield-Mask: 0x3f)                         */
/* =========================================================  INTEN  ========================================================= */
#define RTC_INTEN_ALM_Pos                 (0UL)                     /*!< ALM (Bit 0)                                           */
#define RTC_INTEN_ALM_Msk                 (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
/* ========================================================  INTSTAT  ======================================================== */
#define RTC_INTSTAT_ALM_Pos               (0UL)                     /*!< ALM (Bit 0)                                           */
#define RTC_INTSTAT_ALM_Msk               (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
/* ========================================================  INTCLR  ========================================================= */
#define RTC_INTCLR_ALM_Pos                (0UL)                     /*!< ALM (Bit 0)                                           */
#define RTC_INTCLR_ALM_Msk                (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
/* ========================================================  INTSET  ========================================================= */
#define RTC_INTSET_ALM_Pos                (0UL)                     /*!< ALM (Bit 0)                                           */
#define RTC_INTSET_ALM_Msk                (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */


/* =========================================================================================================================== */
/* ================                                           SDIO                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  SDMA  ========================================================== */
#define SDIO_SDMA_SDMASYSTEMADDRESS_Pos   (0UL)                     /*!< SDMASYSTEMADDRESS (Bit 0)                             */
#define SDIO_SDMA_SDMASYSTEMADDRESS_Msk   (0xffffffffUL)            /*!< SDMASYSTEMADDRESS (Bitfield-Mask: 0xffffffff)         */
/* =========================================================  BLOCK  ========================================================= */
#define SDIO_BLOCK_BLKCNT_Pos             (16UL)                    /*!< BLKCNT (Bit 16)                                       */
#define SDIO_BLOCK_BLKCNT_Msk             (0xffff0000UL)            /*!< BLKCNT (Bitfield-Mask: 0xffff)                        */
#define SDIO_BLOCK_HOSTSDMABUFSZ_Pos      (12UL)                    /*!< HOSTSDMABUFSZ (Bit 12)                                */
#define SDIO_BLOCK_HOSTSDMABUFSZ_Msk      (0x7000UL)                /*!< HOSTSDMABUFSZ (Bitfield-Mask: 0x07)                   */
#define SDIO_BLOCK_TRANSFERBLOCKSIZE_Pos  (0UL)                     /*!< TRANSFERBLOCKSIZE (Bit 0)                             */
#define SDIO_BLOCK_TRANSFERBLOCKSIZE_Msk  (0xfffUL)                 /*!< TRANSFERBLOCKSIZE (Bitfield-Mask: 0xfff)              */
/* =======================================================  ARGUMENT1  ======================================================= */
#define SDIO_ARGUMENT1_CMDARG1_Pos        (0UL)                     /*!< CMDARG1 (Bit 0)                                       */
#define SDIO_ARGUMENT1_CMDARG1_Msk        (0xffffffffUL)            /*!< CMDARG1 (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  TRANSFER  ======================================================== */
#define SDIO_TRANSFER_CMDIDX_Pos          (24UL)                    /*!< CMDIDX (Bit 24)                                       */
#define SDIO_TRANSFER_CMDIDX_Msk          (0x3f000000UL)            /*!< CMDIDX (Bitfield-Mask: 0x3f)                          */
#define SDIO_TRANSFER_CMDTYPE_Pos         (22UL)                    /*!< CMDTYPE (Bit 22)                                      */
#define SDIO_TRANSFER_CMDTYPE_Msk         (0xc00000UL)              /*!< CMDTYPE (Bitfield-Mask: 0x03)                         */
#define SDIO_TRANSFER_DATAPRSNTSEL_Pos    (21UL)                    /*!< DATAPRSNTSEL (Bit 21)                                 */
#define SDIO_TRANSFER_DATAPRSNTSEL_Msk    (0x200000UL)              /*!< DATAPRSNTSEL (Bitfield-Mask: 0x01)                    */
#define SDIO_TRANSFER_CMDIDXCHKEN_Pos     (20UL)                    /*!< CMDIDXCHKEN (Bit 20)                                  */
#define SDIO_TRANSFER_CMDIDXCHKEN_Msk     (0x100000UL)              /*!< CMDIDXCHKEN (Bitfield-Mask: 0x01)                     */
#define SDIO_TRANSFER_CMDCRCCHKEN_Pos     (19UL)                    /*!< CMDCRCCHKEN (Bit 19)                                  */
#define SDIO_TRANSFER_CMDCRCCHKEN_Msk     (0x80000UL)               /*!< CMDCRCCHKEN (Bitfield-Mask: 0x01)                     */
#define SDIO_TRANSFER_RESPTYPESEL_Pos     (16UL)                    /*!< RESPTYPESEL (Bit 16)                                  */
#define SDIO_TRANSFER_RESPTYPESEL_Msk     (0x30000UL)               /*!< RESPTYPESEL (Bitfield-Mask: 0x03)                     */
#define SDIO_TRANSFER_BLKSEL_Pos          (5UL)                     /*!< BLKSEL (Bit 5)                                        */
#define SDIO_TRANSFER_BLKSEL_Msk          (0x20UL)                  /*!< BLKSEL (Bitfield-Mask: 0x01)                          */
#define SDIO_TRANSFER_DXFERDIRSEL_Pos     (4UL)                     /*!< DXFERDIRSEL (Bit 4)                                   */
#define SDIO_TRANSFER_DXFERDIRSEL_Msk     (0x10UL)                  /*!< DXFERDIRSEL (Bitfield-Mask: 0x01)                     */
#define SDIO_TRANSFER_ACMDEN_Pos          (2UL)                     /*!< ACMDEN (Bit 2)                                        */
#define SDIO_TRANSFER_ACMDEN_Msk          (0xcUL)                   /*!< ACMDEN (Bitfield-Mask: 0x03)                          */
#define SDIO_TRANSFER_BLKCNTEN_Pos        (1UL)                     /*!< BLKCNTEN (Bit 1)                                      */
#define SDIO_TRANSFER_BLKCNTEN_Msk        (0x2UL)                   /*!< BLKCNTEN (Bitfield-Mask: 0x01)                        */
#define SDIO_TRANSFER_DMAEN_Pos           (0UL)                     /*!< DMAEN (Bit 0)                                         */
#define SDIO_TRANSFER_DMAEN_Msk           (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
/* =======================================================  RESPONSE0  ======================================================= */
#define SDIO_RESPONSE0_CMDRESP0_Pos       (0UL)                     /*!< CMDRESP0 (Bit 0)                                      */
#define SDIO_RESPONSE0_CMDRESP0_Msk       (0xffffffffUL)            /*!< CMDRESP0 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  RESPONSE1  ======================================================= */
#define SDIO_RESPONSE1_CMDRESP1_Pos       (0UL)                     /*!< CMDRESP1 (Bit 0)                                      */
#define SDIO_RESPONSE1_CMDRESP1_Msk       (0xffffffffUL)            /*!< CMDRESP1 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  RESPONSE2  ======================================================= */
#define SDIO_RESPONSE2_CMDRESP2_Pos       (0UL)                     /*!< CMDRESP2 (Bit 0)                                      */
#define SDIO_RESPONSE2_CMDRESP2_Msk       (0xffffffffUL)            /*!< CMDRESP2 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  RESPONSE3  ======================================================= */
#define SDIO_RESPONSE3_CMDRESP3_Pos       (0UL)                     /*!< CMDRESP3 (Bit 0)                                      */
#define SDIO_RESPONSE3_CMDRESP3_Msk       (0xffffffffUL)            /*!< CMDRESP3 (Bitfield-Mask: 0xffffffff)                  */
/* ========================================================  BUFFER  ========================================================= */
#define SDIO_BUFFER_BUFFERDATA_Pos        (0UL)                     /*!< BUFFERDATA (Bit 0)                                    */
#define SDIO_BUFFER_BUFFERDATA_Msk        (0xffffffffUL)            /*!< BUFFERDATA (Bitfield-Mask: 0xffffffff)                */
/* ========================================================  PRESENT  ======================================================== */
#define SDIO_PRESENT_DAT74LINE_Pos        (25UL)                    /*!< DAT74LINE (Bit 25)                                    */
#define SDIO_PRESENT_DAT74LINE_Msk        (0x1e000000UL)            /*!< DAT74LINE (Bitfield-Mask: 0x0f)                       */
#define SDIO_PRESENT_CMDLINE_Pos          (24UL)                    /*!< CMDLINE (Bit 24)                                      */
#define SDIO_PRESENT_CMDLINE_Msk          (0x1000000UL)             /*!< CMDLINE (Bitfield-Mask: 0x01)                         */
#define SDIO_PRESENT_DAT30LINE_Pos        (20UL)                    /*!< DAT30LINE (Bit 20)                                    */
#define SDIO_PRESENT_DAT30LINE_Msk        (0xf00000UL)              /*!< DAT30LINE (Bitfield-Mask: 0x0f)                       */
#define SDIO_PRESENT_WRPROTSW_Pos         (19UL)                    /*!< WRPROTSW (Bit 19)                                     */
#define SDIO_PRESENT_WRPROTSW_Msk         (0x80000UL)               /*!< WRPROTSW (Bitfield-Mask: 0x01)                        */
#define SDIO_PRESENT_CARDDET_Pos          (18UL)                    /*!< CARDDET (Bit 18)                                      */
#define SDIO_PRESENT_CARDDET_Msk          (0x40000UL)               /*!< CARDDET (Bitfield-Mask: 0x01)                         */
#define SDIO_PRESENT_CARDSTABLE_Pos       (17UL)                    /*!< CARDSTABLE (Bit 17)                                   */
#define SDIO_PRESENT_CARDSTABLE_Msk       (0x20000UL)               /*!< CARDSTABLE (Bitfield-Mask: 0x01)                      */
#define SDIO_PRESENT_CARDINSERTED_Pos     (16UL)                    /*!< CARDINSERTED (Bit 16)                                 */
#define SDIO_PRESENT_CARDINSERTED_Msk     (0x10000UL)               /*!< CARDINSERTED (Bitfield-Mask: 0x01)                    */
#define SDIO_PRESENT_BUFRDEN_Pos          (11UL)                    /*!< BUFRDEN (Bit 11)                                      */
#define SDIO_PRESENT_BUFRDEN_Msk          (0x800UL)                 /*!< BUFRDEN (Bitfield-Mask: 0x01)                         */
#define SDIO_PRESENT_BUFWREN_Pos          (10UL)                    /*!< BUFWREN (Bit 10)                                      */
#define SDIO_PRESENT_BUFWREN_Msk          (0x400UL)                 /*!< BUFWREN (Bitfield-Mask: 0x01)                         */
#define SDIO_PRESENT_RDXFERACT_Pos        (9UL)                     /*!< RDXFERACT (Bit 9)                                     */
#define SDIO_PRESENT_RDXFERACT_Msk        (0x200UL)                 /*!< RDXFERACT (Bitfield-Mask: 0x01)                       */
#define SDIO_PRESENT_WRXFERACT_Pos        (8UL)                     /*!< WRXFERACT (Bit 8)                                     */
#define SDIO_PRESENT_WRXFERACT_Msk        (0x100UL)                 /*!< WRXFERACT (Bitfield-Mask: 0x01)                       */
#define SDIO_PRESENT_RETUNINGREQUEST_Pos  (3UL)                     /*!< RETUNINGREQUEST (Bit 3)                               */
#define SDIO_PRESENT_RETUNINGREQUEST_Msk  (0x8UL)                   /*!< RETUNINGREQUEST (Bitfield-Mask: 0x01)                 */
#define SDIO_PRESENT_DLINEACT_Pos         (2UL)                     /*!< DLINEACT (Bit 2)                                      */
#define SDIO_PRESENT_DLINEACT_Msk         (0x4UL)                   /*!< DLINEACT (Bitfield-Mask: 0x01)                        */
#define SDIO_PRESENT_CMDINHDAT_Pos        (1UL)                     /*!< CMDINHDAT (Bit 1)                                     */
#define SDIO_PRESENT_CMDINHDAT_Msk        (0x2UL)                   /*!< CMDINHDAT (Bitfield-Mask: 0x01)                       */
#define SDIO_PRESENT_CMDINHCMD_Pos        (0UL)                     /*!< CMDINHCMD (Bit 0)                                     */
#define SDIO_PRESENT_CMDINHCMD_Msk        (0x1UL)                   /*!< CMDINHCMD (Bitfield-Mask: 0x01)                       */
/* =======================================================  HOSTCTRL1  ======================================================= */
#define SDIO_HOSTCTRL1_WUENCARDREMOVL_Pos (26UL)                    /*!< WUENCARDREMOVL (Bit 26)                               */
#define SDIO_HOSTCTRL1_WUENCARDREMOVL_Msk (0x4000000UL)             /*!< WUENCARDREMOVL (Bitfield-Mask: 0x01)                  */
#define SDIO_HOSTCTRL1_WUENCARDINSERT_Pos (25UL)                    /*!< WUENCARDINSERT (Bit 25)                               */
#define SDIO_HOSTCTRL1_WUENCARDINSERT_Msk (0x2000000UL)             /*!< WUENCARDINSERT (Bitfield-Mask: 0x01)                  */
#define SDIO_HOSTCTRL1_WUENCARDINT_Pos    (24UL)                    /*!< WUENCARDINT (Bit 24)                                  */
#define SDIO_HOSTCTRL1_WUENCARDINT_Msk    (0x1000000UL)             /*!< WUENCARDINT (Bitfield-Mask: 0x01)                     */
#define SDIO_HOSTCTRL1_BOOTACKCHK_Pos     (23UL)                    /*!< BOOTACKCHK (Bit 23)                                   */
#define SDIO_HOSTCTRL1_BOOTACKCHK_Msk     (0x800000UL)              /*!< BOOTACKCHK (Bitfield-Mask: 0x01)                      */
#define SDIO_HOSTCTRL1_ALTBOOTEN_Pos      (22UL)                    /*!< ALTBOOTEN (Bit 22)                                    */
#define SDIO_HOSTCTRL1_ALTBOOTEN_Msk      (0x400000UL)              /*!< ALTBOOTEN (Bitfield-Mask: 0x01)                       */
#define SDIO_HOSTCTRL1_BOOTEN_Pos         (21UL)                    /*!< BOOTEN (Bit 21)                                       */
#define SDIO_HOSTCTRL1_BOOTEN_Msk         (0x200000UL)              /*!< BOOTEN (Bitfield-Mask: 0x01)                          */
#define SDIO_HOSTCTRL1_SPIMODE_Pos        (20UL)                    /*!< SPIMODE (Bit 20)                                      */
#define SDIO_HOSTCTRL1_SPIMODE_Msk        (0x100000UL)              /*!< SPIMODE (Bitfield-Mask: 0x01)                         */
#define SDIO_HOSTCTRL1_GAP_Pos            (19UL)                    /*!< GAP (Bit 19)                                          */
#define SDIO_HOSTCTRL1_GAP_Msk            (0x80000UL)               /*!< GAP (Bitfield-Mask: 0x01)                             */
#define SDIO_HOSTCTRL1_READWAITCTRL_Pos   (18UL)                    /*!< READWAITCTRL (Bit 18)                                 */
#define SDIO_HOSTCTRL1_READWAITCTRL_Msk   (0x40000UL)               /*!< READWAITCTRL (Bitfield-Mask: 0x01)                    */
#define SDIO_HOSTCTRL1_CONTREQ_Pos        (17UL)                    /*!< CONTREQ (Bit 17)                                      */
#define SDIO_HOSTCTRL1_CONTREQ_Msk        (0x20000UL)               /*!< CONTREQ (Bitfield-Mask: 0x01)                         */
#define SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST_Pos (16UL)             /*!< STOPATBLOCKGAPREQUEST (Bit 16)                        */
#define SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST_Msk (0x10000UL)        /*!< STOPATBLOCKGAPREQUEST (Bitfield-Mask: 0x01)           */
#define SDIO_HOSTCTRL1_HWRESET_Pos        (12UL)                    /*!< HWRESET (Bit 12)                                      */
#define SDIO_HOSTCTRL1_HWRESET_Msk        (0x1000UL)                /*!< HWRESET (Bitfield-Mask: 0x01)                         */
#define SDIO_HOSTCTRL1_VOLTSELECT_Pos     (9UL)                     /*!< VOLTSELECT (Bit 9)                                    */
#define SDIO_HOSTCTRL1_VOLTSELECT_Msk     (0xe00UL)                 /*!< VOLTSELECT (Bitfield-Mask: 0x07)                      */
#define SDIO_HOSTCTRL1_SDBUSPOWER_Pos     (8UL)                     /*!< SDBUSPOWER (Bit 8)                                    */
#define SDIO_HOSTCTRL1_SDBUSPOWER_Msk     (0x100UL)                 /*!< SDBUSPOWER (Bitfield-Mask: 0x01)                      */
#define SDIO_HOSTCTRL1_CARDSRC_Pos        (7UL)                     /*!< CARDSRC (Bit 7)                                       */
#define SDIO_HOSTCTRL1_CARDSRC_Msk        (0x80UL)                  /*!< CARDSRC (Bitfield-Mask: 0x01)                         */
#define SDIO_HOSTCTRL1_TESTLEVEL_Pos      (6UL)                     /*!< TESTLEVEL (Bit 6)                                     */
#define SDIO_HOSTCTRL1_TESTLEVEL_Msk      (0x40UL)                  /*!< TESTLEVEL (Bitfield-Mask: 0x01)                       */
#define SDIO_HOSTCTRL1_XFERWIDTH_Pos      (5UL)                     /*!< XFERWIDTH (Bit 5)                                     */
#define SDIO_HOSTCTRL1_XFERWIDTH_Msk      (0x20UL)                  /*!< XFERWIDTH (Bitfield-Mask: 0x01)                       */
#define SDIO_HOSTCTRL1_DMASELECT_Pos      (3UL)                     /*!< DMASELECT (Bit 3)                                     */
#define SDIO_HOSTCTRL1_DMASELECT_Msk      (0x18UL)                  /*!< DMASELECT (Bitfield-Mask: 0x03)                       */
#define SDIO_HOSTCTRL1_HISPEEDEN_Pos      (2UL)                     /*!< HISPEEDEN (Bit 2)                                     */
#define SDIO_HOSTCTRL1_HISPEEDEN_Msk      (0x4UL)                   /*!< HISPEEDEN (Bitfield-Mask: 0x01)                       */
#define SDIO_HOSTCTRL1_DATATRANSFERWIDTH_Pos (1UL)                  /*!< DATATRANSFERWIDTH (Bit 1)                             */
#define SDIO_HOSTCTRL1_DATATRANSFERWIDTH_Msk (0x2UL)                /*!< DATATRANSFERWIDTH (Bitfield-Mask: 0x01)               */
#define SDIO_HOSTCTRL1_LEDCONTROL_Pos     (0UL)                     /*!< LEDCONTROL (Bit 0)                                    */
#define SDIO_HOSTCTRL1_LEDCONTROL_Msk     (0x1UL)                   /*!< LEDCONTROL (Bitfield-Mask: 0x01)                      */
/* =======================================================  CLOCKCTRL  ======================================================= */
#define SDIO_CLOCKCTRL_SWRSTDAT_Pos       (26UL)                    /*!< SWRSTDAT (Bit 26)                                     */
#define SDIO_CLOCKCTRL_SWRSTDAT_Msk       (0x4000000UL)             /*!< SWRSTDAT (Bitfield-Mask: 0x01)                        */
#define SDIO_CLOCKCTRL_SWRSTCMD_Pos       (25UL)                    /*!< SWRSTCMD (Bit 25)                                     */
#define SDIO_CLOCKCTRL_SWRSTCMD_Msk       (0x2000000UL)             /*!< SWRSTCMD (Bitfield-Mask: 0x01)                        */
#define SDIO_CLOCKCTRL_SWRSTALL_Pos       (24UL)                    /*!< SWRSTALL (Bit 24)                                     */
#define SDIO_CLOCKCTRL_SWRSTALL_Msk       (0x1000000UL)             /*!< SWRSTALL (Bitfield-Mask: 0x01)                        */
#define SDIO_CLOCKCTRL_TIMEOUTCNT_Pos     (16UL)                    /*!< TIMEOUTCNT (Bit 16)                                   */
#define SDIO_CLOCKCTRL_TIMEOUTCNT_Msk     (0xf0000UL)               /*!< TIMEOUTCNT (Bitfield-Mask: 0x0f)                      */
#define SDIO_CLOCKCTRL_FREQSEL_Pos        (8UL)                     /*!< FREQSEL (Bit 8)                                       */
#define SDIO_CLOCKCTRL_FREQSEL_Msk        (0xff00UL)                /*!< FREQSEL (Bitfield-Mask: 0xff)                         */
#define SDIO_CLOCKCTRL_UPRCLKDIV_Pos      (6UL)                     /*!< UPRCLKDIV (Bit 6)                                     */
#define SDIO_CLOCKCTRL_UPRCLKDIV_Msk      (0xc0UL)                  /*!< UPRCLKDIV (Bitfield-Mask: 0x03)                       */
#define SDIO_CLOCKCTRL_CLKGENSEL_Pos      (5UL)                     /*!< CLKGENSEL (Bit 5)                                     */
#define SDIO_CLOCKCTRL_CLKGENSEL_Msk      (0x20UL)                  /*!< CLKGENSEL (Bitfield-Mask: 0x01)                       */
#define SDIO_CLOCKCTRL_SDCLKEN_Pos        (2UL)                     /*!< SDCLKEN (Bit 2)                                       */
#define SDIO_CLOCKCTRL_SDCLKEN_Msk        (0x4UL)                   /*!< SDCLKEN (Bitfield-Mask: 0x01)                         */
#define SDIO_CLOCKCTRL_CLKSTABLE_Pos      (1UL)                     /*!< CLKSTABLE (Bit 1)                                     */
#define SDIO_CLOCKCTRL_CLKSTABLE_Msk      (0x2UL)                   /*!< CLKSTABLE (Bitfield-Mask: 0x01)                       */
#define SDIO_CLOCKCTRL_CLKEN_Pos          (0UL)                     /*!< CLKEN (Bit 0)                                         */
#define SDIO_CLOCKCTRL_CLKEN_Msk          (0x1UL)                   /*!< CLKEN (Bitfield-Mask: 0x01)                           */
/* ========================================================  INTSTAT  ======================================================== */
#define SDIO_INTSTAT_VNDERRSTAT_Pos       (29UL)                    /*!< VNDERRSTAT (Bit 29)                                   */
#define SDIO_INTSTAT_VNDERRSTAT_Msk       (0xe0000000UL)            /*!< VNDERRSTAT (Bitfield-Mask: 0x07)                      */
#define SDIO_INTSTAT_TGTRESPERR_Pos       (28UL)                    /*!< TGTRESPERR (Bit 28)                                   */
#define SDIO_INTSTAT_TGTRESPERR_Msk       (0x10000000UL)            /*!< TGTRESPERR (Bitfield-Mask: 0x01)                      */
#define SDIO_INTSTAT_ADMAERROR_Pos        (25UL)                    /*!< ADMAERROR (Bit 25)                                    */
#define SDIO_INTSTAT_ADMAERROR_Msk        (0x2000000UL)             /*!< ADMAERROR (Bitfield-Mask: 0x01)                       */
#define SDIO_INTSTAT_AUTOCMDERROR_Pos     (24UL)                    /*!< AUTOCMDERROR (Bit 24)                                 */
#define SDIO_INTSTAT_AUTOCMDERROR_Msk     (0x1000000UL)             /*!< AUTOCMDERROR (Bitfield-Mask: 0x01)                    */
#define SDIO_INTSTAT_CURRENTLIMITERROR_Pos (23UL)                   /*!< CURRENTLIMITERROR (Bit 23)                            */
#define SDIO_INTSTAT_CURRENTLIMITERROR_Msk (0x800000UL)             /*!< CURRENTLIMITERROR (Bitfield-Mask: 0x01)               */
#define SDIO_INTSTAT_DATAENDBITERROR_Pos  (22UL)                    /*!< DATAENDBITERROR (Bit 22)                              */
#define SDIO_INTSTAT_DATAENDBITERROR_Msk  (0x400000UL)              /*!< DATAENDBITERROR (Bitfield-Mask: 0x01)                 */
#define SDIO_INTSTAT_DATACRCERROR_Pos     (21UL)                    /*!< DATACRCERROR (Bit 21)                                 */
#define SDIO_INTSTAT_DATACRCERROR_Msk     (0x200000UL)              /*!< DATACRCERROR (Bitfield-Mask: 0x01)                    */
#define SDIO_INTSTAT_DATATIMEOUTERROR_Pos (20UL)                    /*!< DATATIMEOUTERROR (Bit 20)                             */
#define SDIO_INTSTAT_DATATIMEOUTERROR_Msk (0x100000UL)              /*!< DATATIMEOUTERROR (Bitfield-Mask: 0x01)                */
#define SDIO_INTSTAT_COMMANDINDEXERROR_Pos (19UL)                   /*!< COMMANDINDEXERROR (Bit 19)                            */
#define SDIO_INTSTAT_COMMANDINDEXERROR_Msk (0x80000UL)              /*!< COMMANDINDEXERROR (Bitfield-Mask: 0x01)               */
#define SDIO_INTSTAT_COMMANDENDBITERROR_Pos (18UL)                  /*!< COMMANDENDBITERROR (Bit 18)                           */
#define SDIO_INTSTAT_COMMANDENDBITERROR_Msk (0x40000UL)             /*!< COMMANDENDBITERROR (Bitfield-Mask: 0x01)              */
#define SDIO_INTSTAT_COMMANDCRCERROR_Pos  (17UL)                    /*!< COMMANDCRCERROR (Bit 17)                              */
#define SDIO_INTSTAT_COMMANDCRCERROR_Msk  (0x20000UL)               /*!< COMMANDCRCERROR (Bitfield-Mask: 0x01)                 */
#define SDIO_INTSTAT_COMMANDTIMEOUTERROR_Pos (16UL)                 /*!< COMMANDTIMEOUTERROR (Bit 16)                          */
#define SDIO_INTSTAT_COMMANDTIMEOUTERROR_Msk (0x10000UL)            /*!< COMMANDTIMEOUTERROR (Bitfield-Mask: 0x01)             */
#define SDIO_INTSTAT_ERRORINTERRUPT_Pos   (15UL)                    /*!< ERRORINTERRUPT (Bit 15)                               */
#define SDIO_INTSTAT_ERRORINTERRUPT_Msk   (0x8000UL)                /*!< ERRORINTERRUPT (Bitfield-Mask: 0x01)                  */
#define SDIO_INTSTAT_BOOTTERMINATE_Pos    (14UL)                    /*!< BOOTTERMINATE (Bit 14)                                */
#define SDIO_INTSTAT_BOOTTERMINATE_Msk    (0x4000UL)                /*!< BOOTTERMINATE (Bitfield-Mask: 0x01)                   */
#define SDIO_INTSTAT_BOOTACKRCV_Pos       (13UL)                    /*!< BOOTACKRCV (Bit 13)                                   */
#define SDIO_INTSTAT_BOOTACKRCV_Msk       (0x2000UL)                /*!< BOOTACKRCV (Bitfield-Mask: 0x01)                      */
#define SDIO_INTSTAT_RETUNINGEVENT_Pos    (12UL)                    /*!< RETUNINGEVENT (Bit 12)                                */
#define SDIO_INTSTAT_RETUNINGEVENT_Msk    (0x1000UL)                /*!< RETUNINGEVENT (Bitfield-Mask: 0x01)                   */
#define SDIO_INTSTAT_INTC_Pos             (11UL)                    /*!< INTC (Bit 11)                                         */
#define SDIO_INTSTAT_INTC_Msk             (0x800UL)                 /*!< INTC (Bitfield-Mask: 0x01)                            */
#define SDIO_INTSTAT_INTB_Pos             (10UL)                    /*!< INTB (Bit 10)                                         */
#define SDIO_INTSTAT_INTB_Msk             (0x400UL)                 /*!< INTB (Bitfield-Mask: 0x01)                            */
#define SDIO_INTSTAT_INTA_Pos             (9UL)                     /*!< INTA (Bit 9)                                          */
#define SDIO_INTSTAT_INTA_Msk             (0x200UL)                 /*!< INTA (Bitfield-Mask: 0x01)                            */
#define SDIO_INTSTAT_CARDINTERRUPT_Pos    (8UL)                     /*!< CARDINTERRUPT (Bit 8)                                 */
#define SDIO_INTSTAT_CARDINTERRUPT_Msk    (0x100UL)                 /*!< CARDINTERRUPT (Bitfield-Mask: 0x01)                   */
#define SDIO_INTSTAT_CARDREMOVAL_Pos      (7UL)                     /*!< CARDREMOVAL (Bit 7)                                   */
#define SDIO_INTSTAT_CARDREMOVAL_Msk      (0x80UL)                  /*!< CARDREMOVAL (Bitfield-Mask: 0x01)                     */
#define SDIO_INTSTAT_CARDINSERTION_Pos    (6UL)                     /*!< CARDINSERTION (Bit 6)                                 */
#define SDIO_INTSTAT_CARDINSERTION_Msk    (0x40UL)                  /*!< CARDINSERTION (Bitfield-Mask: 0x01)                   */
#define SDIO_INTSTAT_BUFFERREADREADY_Pos  (5UL)                     /*!< BUFFERREADREADY (Bit 5)                               */
#define SDIO_INTSTAT_BUFFERREADREADY_Msk  (0x20UL)                  /*!< BUFFERREADREADY (Bitfield-Mask: 0x01)                 */
#define SDIO_INTSTAT_BUFFERWRITEREADY_Pos (4UL)                     /*!< BUFFERWRITEREADY (Bit 4)                              */
#define SDIO_INTSTAT_BUFFERWRITEREADY_Msk (0x10UL)                  /*!< BUFFERWRITEREADY (Bitfield-Mask: 0x01)                */
#define SDIO_INTSTAT_DMAINTERRUPT_Pos     (3UL)                     /*!< DMAINTERRUPT (Bit 3)                                  */
#define SDIO_INTSTAT_DMAINTERRUPT_Msk     (0x8UL)                   /*!< DMAINTERRUPT (Bitfield-Mask: 0x01)                    */
#define SDIO_INTSTAT_BLOCKGAPEVENT_Pos    (2UL)                     /*!< BLOCKGAPEVENT (Bit 2)                                 */
#define SDIO_INTSTAT_BLOCKGAPEVENT_Msk    (0x4UL)                   /*!< BLOCKGAPEVENT (Bitfield-Mask: 0x01)                   */
#define SDIO_INTSTAT_TRANSFERCOMPLETE_Pos (1UL)                     /*!< TRANSFERCOMPLETE (Bit 1)                              */
#define SDIO_INTSTAT_TRANSFERCOMPLETE_Msk (0x2UL)                   /*!< TRANSFERCOMPLETE (Bitfield-Mask: 0x01)                */
#define SDIO_INTSTAT_COMMANDCOMPLETE_Pos  (0UL)                     /*!< COMMANDCOMPLETE (Bit 0)                               */
#define SDIO_INTSTAT_COMMANDCOMPLETE_Msk  (0x1UL)                   /*!< COMMANDCOMPLETE (Bitfield-Mask: 0x01)                 */
/* =======================================================  INTENABLE  ======================================================= */
#define SDIO_INTENABLE_VENDORSPECIFICERRORSTATUSENABLE_Pos (29UL)   /*!< VENDORSPECIFICERRORSTATUSENABLE (Bit 29)              */
#define SDIO_INTENABLE_VENDORSPECIFICERRORSTATUSENABLE_Msk (0xe0000000UL) /*!< VENDORSPECIFICERRORSTATUSENABLE (Bitfield-Mask: 0x07) */
#define SDIO_INTENABLE_TGTRESPERRHOSTERRSTATEN_Pos (28UL)           /*!< TGTRESPERRHOSTERRSTATEN (Bit 28)                      */
#define SDIO_INTENABLE_TGTRESPERRHOSTERRSTATEN_Msk (0x10000000UL)   /*!< TGTRESPERRHOSTERRSTATEN (Bitfield-Mask: 0x01)         */
#define SDIO_INTENABLE_TUNINGERRORSTATUS_Pos (26UL)                 /*!< TUNINGERRORSTATUS (Bit 26)                            */
#define SDIO_INTENABLE_TUNINGERRORSTATUS_Msk (0x4000000UL)          /*!< TUNINGERRORSTATUS (Bitfield-Mask: 0x01)               */
#define SDIO_INTENABLE_ADMAERRORSTATUSENABLE_Pos (25UL)             /*!< ADMAERRORSTATUSENABLE (Bit 25)                        */
#define SDIO_INTENABLE_ADMAERRORSTATUSENABLE_Msk (0x2000000UL)      /*!< ADMAERRORSTATUSENABLE (Bitfield-Mask: 0x01)           */
#define SDIO_INTENABLE_AUTOCMD12ERRORSTATUSENABLE_Pos (24UL)        /*!< AUTOCMD12ERRORSTATUSENABLE (Bit 24)                   */
#define SDIO_INTENABLE_AUTOCMD12ERRORSTATUSENABLE_Msk (0x1000000UL) /*!< AUTOCMD12ERRORSTATUSENABLE (Bitfield-Mask: 0x01)      */
#define SDIO_INTENABLE_CURRENTLIMITERRORSTATUSENABLE_Pos (23UL)     /*!< CURRENTLIMITERRORSTATUSENABLE (Bit 23)                */
#define SDIO_INTENABLE_CURRENTLIMITERRORSTATUSENABLE_Msk (0x800000UL) /*!< CURRENTLIMITERRORSTATUSENABLE (Bitfield-Mask: 0x01) */
#define SDIO_INTENABLE_DATAENDBITERRORSTATUSENABLE_Pos (22UL)       /*!< DATAENDBITERRORSTATUSENABLE (Bit 22)                  */
#define SDIO_INTENABLE_DATAENDBITERRORSTATUSENABLE_Msk (0x400000UL) /*!< DATAENDBITERRORSTATUSENABLE (Bitfield-Mask: 0x01)     */
#define SDIO_INTENABLE_DATACRCERRORSTATUSENABLE_Pos (21UL)          /*!< DATACRCERRORSTATUSENABLE (Bit 21)                     */
#define SDIO_INTENABLE_DATACRCERRORSTATUSENABLE_Msk (0x200000UL)    /*!< DATACRCERRORSTATUSENABLE (Bitfield-Mask: 0x01)        */
#define SDIO_INTENABLE_DATATIMEOUTERRORSTATUSENABLE_Pos (20UL)      /*!< DATATIMEOUTERRORSTATUSENABLE (Bit 20)                 */
#define SDIO_INTENABLE_DATATIMEOUTERRORSTATUSENABLE_Msk (0x100000UL) /*!< DATATIMEOUTERRORSTATUSENABLE (Bitfield-Mask: 0x01)   */
#define SDIO_INTENABLE_COMMANDINDEXERRORSTATUSENABLE_Pos (19UL)     /*!< COMMANDINDEXERRORSTATUSENABLE (Bit 19)                */
#define SDIO_INTENABLE_COMMANDINDEXERRORSTATUSENABLE_Msk (0x80000UL) /*!< COMMANDINDEXERRORSTATUSENABLE (Bitfield-Mask: 0x01)  */
#define SDIO_INTENABLE_COMMANDENDBITERRORSTATUSENABLE_Pos (18UL)    /*!< COMMANDENDBITERRORSTATUSENABLE (Bit 18)               */
#define SDIO_INTENABLE_COMMANDENDBITERRORSTATUSENABLE_Msk (0x40000UL) /*!< COMMANDENDBITERRORSTATUSENABLE (Bitfield-Mask: 0x01) */
#define SDIO_INTENABLE_COMMANDCRCERRORSTATUSENABLE_Pos (17UL)       /*!< COMMANDCRCERRORSTATUSENABLE (Bit 17)                  */
#define SDIO_INTENABLE_COMMANDCRCERRORSTATUSENABLE_Msk (0x20000UL)  /*!< COMMANDCRCERRORSTATUSENABLE (Bitfield-Mask: 0x01)     */
#define SDIO_INTENABLE_COMMANDTIMEOUTERRORSTATUSENABLE_Pos (16UL)   /*!< COMMANDTIMEOUTERRORSTATUSENABLE (Bit 16)              */
#define SDIO_INTENABLE_COMMANDTIMEOUTERRORSTATUSENABLE_Msk (0x10000UL) /*!< COMMANDTIMEOUTERRORSTATUSENABLE (Bitfield-Mask: 0x01) */
#define SDIO_INTENABLE_FIXEDTO0_Pos       (15UL)                    /*!< FIXEDTO0 (Bit 15)                                     */
#define SDIO_INTENABLE_FIXEDTO0_Msk       (0x8000UL)                /*!< FIXEDTO0 (Bitfield-Mask: 0x01)                        */
#define SDIO_INTENABLE_BOOTTERMINATE_Pos  (14UL)                    /*!< BOOTTERMINATE (Bit 14)                                */
#define SDIO_INTENABLE_BOOTTERMINATE_Msk  (0x4000UL)                /*!< BOOTTERMINATE (Bitfield-Mask: 0x01)                   */
#define SDIO_INTENABLE_BOOTACKRCVENABLE_Pos (13UL)                  /*!< BOOTACKRCVENABLE (Bit 13)                             */
#define SDIO_INTENABLE_BOOTACKRCVENABLE_Msk (0x2000UL)              /*!< BOOTACKRCVENABLE (Bitfield-Mask: 0x01)                */
#define SDIO_INTENABLE_RETUNINGEVENTSTATUSENABLE_Pos (12UL)         /*!< RETUNINGEVENTSTATUSENABLE (Bit 12)                    */
#define SDIO_INTENABLE_RETUNINGEVENTSTATUSENABLE_Msk (0x1000UL)     /*!< RETUNINGEVENTSTATUSENABLE (Bitfield-Mask: 0x01)       */
#define SDIO_INTENABLE_INTCSTATUSENABLE_Pos (11UL)                  /*!< INTCSTATUSENABLE (Bit 11)                             */
#define SDIO_INTENABLE_INTCSTATUSENABLE_Msk (0x800UL)               /*!< INTCSTATUSENABLE (Bitfield-Mask: 0x01)                */
#define SDIO_INTENABLE_INTBSTATUSENABLE_Pos (10UL)                  /*!< INTBSTATUSENABLE (Bit 10)                             */
#define SDIO_INTENABLE_INTBSTATUSENABLE_Msk (0x400UL)               /*!< INTBSTATUSENABLE (Bitfield-Mask: 0x01)                */
#define SDIO_INTENABLE_INTASTATUSENABLE_Pos (9UL)                   /*!< INTASTATUSENABLE (Bit 9)                              */
#define SDIO_INTENABLE_INTASTATUSENABLE_Msk (0x200UL)               /*!< INTASTATUSENABLE (Bitfield-Mask: 0x01)                */
#define SDIO_INTENABLE_CARDINTERRUPTSTATUSENABLE_Pos (8UL)          /*!< CARDINTERRUPTSTATUSENABLE (Bit 8)                     */
#define SDIO_INTENABLE_CARDINTERRUPTSTATUSENABLE_Msk (0x100UL)      /*!< CARDINTERRUPTSTATUSENABLE (Bitfield-Mask: 0x01)       */
#define SDIO_INTENABLE_CARDREMOVALSTATUSENABLE_Pos (7UL)            /*!< CARDREMOVALSTATUSENABLE (Bit 7)                       */
#define SDIO_INTENABLE_CARDREMOVALSTATUSENABLE_Msk (0x80UL)         /*!< CARDREMOVALSTATUSENABLE (Bitfield-Mask: 0x01)         */
#define SDIO_INTENABLE_CARDINSERTIONSTATUSENABLE_Pos (6UL)          /*!< CARDINSERTIONSTATUSENABLE (Bit 6)                     */
#define SDIO_INTENABLE_CARDINSERTIONSTATUSENABLE_Msk (0x40UL)       /*!< CARDINSERTIONSTATUSENABLE (Bitfield-Mask: 0x01)       */
#define SDIO_INTENABLE_BUFFERREADREADYSTATUSENABLE_Pos (5UL)        /*!< BUFFERREADREADYSTATUSENABLE (Bit 5)                   */
#define SDIO_INTENABLE_BUFFERREADREADYSTATUSENABLE_Msk (0x20UL)     /*!< BUFFERREADREADYSTATUSENABLE (Bitfield-Mask: 0x01)     */
#define SDIO_INTENABLE_BUFFERWRITEREADYSTATUSENABLE_Pos (4UL)       /*!< BUFFERWRITEREADYSTATUSENABLE (Bit 4)                  */
#define SDIO_INTENABLE_BUFFERWRITEREADYSTATUSENABLE_Msk (0x10UL)    /*!< BUFFERWRITEREADYSTATUSENABLE (Bitfield-Mask: 0x01)    */
#define SDIO_INTENABLE_DMAINTERRUPTSTATUSENABLE_Pos (3UL)           /*!< DMAINTERRUPTSTATUSENABLE (Bit 3)                      */
#define SDIO_INTENABLE_DMAINTERRUPTSTATUSENABLE_Msk (0x8UL)         /*!< DMAINTERRUPTSTATUSENABLE (Bitfield-Mask: 0x01)        */
#define SDIO_INTENABLE_BLOCKGAPEVENTSTATUSENABLE_Pos (2UL)          /*!< BLOCKGAPEVENTSTATUSENABLE (Bit 2)                     */
#define SDIO_INTENABLE_BLOCKGAPEVENTSTATUSENABLE_Msk (0x4UL)        /*!< BLOCKGAPEVENTSTATUSENABLE (Bitfield-Mask: 0x01)       */
#define SDIO_INTENABLE_TRANSFERCOMPLETESTATUSENABLE_Pos (1UL)       /*!< TRANSFERCOMPLETESTATUSENABLE (Bit 1)                  */
#define SDIO_INTENABLE_TRANSFERCOMPLETESTATUSENABLE_Msk (0x2UL)     /*!< TRANSFERCOMPLETESTATUSENABLE (Bitfield-Mask: 0x01)    */
#define SDIO_INTENABLE_COMMANDCOMPLETESTATUSENABLE_Pos (0UL)        /*!< COMMANDCOMPLETESTATUSENABLE (Bit 0)                   */
#define SDIO_INTENABLE_COMMANDCOMPLETESTATUSENABLE_Msk (0x1UL)      /*!< COMMANDCOMPLETESTATUSENABLE (Bitfield-Mask: 0x01)     */
/* ========================================================  INTSIG  ========================================================= */
#define SDIO_INTSIG_VNDERREN_Pos          (29UL)                    /*!< VNDERREN (Bit 29)                                     */
#define SDIO_INTSIG_VNDERREN_Msk          (0xe0000000UL)            /*!< VNDERREN (Bitfield-Mask: 0x07)                        */
#define SDIO_INTSIG_TGTRESPEN_Pos         (28UL)                    /*!< TGTRESPEN (Bit 28)                                    */
#define SDIO_INTSIG_TGTRESPEN_Msk         (0x10000000UL)            /*!< TGTRESPEN (Bitfield-Mask: 0x01)                       */
#define SDIO_INTSIG_TUNINGERREN_Pos       (26UL)                    /*!< TUNINGERREN (Bit 26)                                  */
#define SDIO_INTSIG_TUNINGERREN_Msk       (0x4000000UL)             /*!< TUNINGERREN (Bitfield-Mask: 0x01)                     */
#define SDIO_INTSIG_ADMAERREN_Pos         (25UL)                    /*!< ADMAERREN (Bit 25)                                    */
#define SDIO_INTSIG_ADMAERREN_Msk         (0x2000000UL)             /*!< ADMAERREN (Bitfield-Mask: 0x01)                       */
#define SDIO_INTSIG_AUTOCMD12ERREN_Pos    (24UL)                    /*!< AUTOCMD12ERREN (Bit 24)                               */
#define SDIO_INTSIG_AUTOCMD12ERREN_Msk    (0x1000000UL)             /*!< AUTOCMD12ERREN (Bitfield-Mask: 0x01)                  */
#define SDIO_INTSIG_CURRLMTERREN_Pos      (23UL)                    /*!< CURRLMTERREN (Bit 23)                                 */
#define SDIO_INTSIG_CURRLMTERREN_Msk      (0x800000UL)              /*!< CURRLMTERREN (Bitfield-Mask: 0x01)                    */
#define SDIO_INTSIG_DATAENDERREN_Pos      (22UL)                    /*!< DATAENDERREN (Bit 22)                                 */
#define SDIO_INTSIG_DATAENDERREN_Msk      (0x400000UL)              /*!< DATAENDERREN (Bitfield-Mask: 0x01)                    */
#define SDIO_INTSIG_DATACRCERREN_Pos      (21UL)                    /*!< DATACRCERREN (Bit 21)                                 */
#define SDIO_INTSIG_DATACRCERREN_Msk      (0x200000UL)              /*!< DATACRCERREN (Bitfield-Mask: 0x01)                    */
#define SDIO_INTSIG_DATATOERROREN_Pos     (20UL)                    /*!< DATATOERROREN (Bit 20)                                */
#define SDIO_INTSIG_DATATOERROREN_Msk     (0x100000UL)              /*!< DATATOERROREN (Bitfield-Mask: 0x01)                   */
#define SDIO_INTSIG_CMDIDXERREN_Pos       (19UL)                    /*!< CMDIDXERREN (Bit 19)                                  */
#define SDIO_INTSIG_CMDIDXERREN_Msk       (0x80000UL)               /*!< CMDIDXERREN (Bitfield-Mask: 0x01)                     */
#define SDIO_INTSIG_CMDENDBITERREN_Pos    (18UL)                    /*!< CMDENDBITERREN (Bit 18)                               */
#define SDIO_INTSIG_CMDENDBITERREN_Msk    (0x40000UL)               /*!< CMDENDBITERREN (Bitfield-Mask: 0x01)                  */
#define SDIO_INTSIG_CMDCRCERREN_Pos       (17UL)                    /*!< CMDCRCERREN (Bit 17)                                  */
#define SDIO_INTSIG_CMDCRCERREN_Msk       (0x20000UL)               /*!< CMDCRCERREN (Bitfield-Mask: 0x01)                     */
#define SDIO_INTSIG_CMDTOERREN_Pos        (16UL)                    /*!< CMDTOERREN (Bit 16)                                   */
#define SDIO_INTSIG_CMDTOERREN_Msk        (0x10000UL)               /*!< CMDTOERREN (Bitfield-Mask: 0x01)                      */
#define SDIO_INTSIG_FIXED0_Pos            (15UL)                    /*!< FIXED0 (Bit 15)                                       */
#define SDIO_INTSIG_FIXED0_Msk            (0x8000UL)                /*!< FIXED0 (Bitfield-Mask: 0x01)                          */
#define SDIO_INTSIG_BOOTTERM_Pos          (14UL)                    /*!< BOOTTERM (Bit 14)                                     */
#define SDIO_INTSIG_BOOTTERM_Msk          (0x4000UL)                /*!< BOOTTERM (Bitfield-Mask: 0x01)                        */
#define SDIO_INTSIG_BOOTACKEN_Pos         (13UL)                    /*!< BOOTACKEN (Bit 13)                                    */
#define SDIO_INTSIG_BOOTACKEN_Msk         (0x2000UL)                /*!< BOOTACKEN (Bitfield-Mask: 0x01)                       */
#define SDIO_INTSIG_RETUNEEVENTEN_Pos     (12UL)                    /*!< RETUNEEVENTEN (Bit 12)                                */
#define SDIO_INTSIG_RETUNEEVENTEN_Msk     (0x1000UL)                /*!< RETUNEEVENTEN (Bitfield-Mask: 0x01)                   */
#define SDIO_INTSIG_INTCEN_Pos            (11UL)                    /*!< INTCEN (Bit 11)                                       */
#define SDIO_INTSIG_INTCEN_Msk            (0x800UL)                 /*!< INTCEN (Bitfield-Mask: 0x01)                          */
#define SDIO_INTSIG_INTBEN_Pos            (10UL)                    /*!< INTBEN (Bit 10)                                       */
#define SDIO_INTSIG_INTBEN_Msk            (0x400UL)                 /*!< INTBEN (Bitfield-Mask: 0x01)                          */
#define SDIO_INTSIG_INTAEN_Pos            (9UL)                     /*!< INTAEN (Bit 9)                                        */
#define SDIO_INTSIG_INTAEN_Msk            (0x200UL)                 /*!< INTAEN (Bitfield-Mask: 0x01)                          */
#define SDIO_INTSIG_CARDINTEN_Pos         (8UL)                     /*!< CARDINTEN (Bit 8)                                     */
#define SDIO_INTSIG_CARDINTEN_Msk         (0x100UL)                 /*!< CARDINTEN (Bitfield-Mask: 0x01)                       */
#define SDIO_INTSIG_CARDREMOVALEN_Pos     (7UL)                     /*!< CARDREMOVALEN (Bit 7)                                 */
#define SDIO_INTSIG_CARDREMOVALEN_Msk     (0x80UL)                  /*!< CARDREMOVALEN (Bitfield-Mask: 0x01)                   */
#define SDIO_INTSIG_CARDINSERTEN_Pos      (6UL)                     /*!< CARDINSERTEN (Bit 6)                                  */
#define SDIO_INTSIG_CARDINSERTEN_Msk      (0x40UL)                  /*!< CARDINSERTEN (Bitfield-Mask: 0x01)                    */
#define SDIO_INTSIG_BUFFERRDEN_Pos        (5UL)                     /*!< BUFFERRDEN (Bit 5)                                    */
#define SDIO_INTSIG_BUFFERRDEN_Msk        (0x20UL)                  /*!< BUFFERRDEN (Bitfield-Mask: 0x01)                      */
#define SDIO_INTSIG_BUFFERWREN_Pos        (4UL)                     /*!< BUFFERWREN (Bit 4)                                    */
#define SDIO_INTSIG_BUFFERWREN_Msk        (0x10UL)                  /*!< BUFFERWREN (Bitfield-Mask: 0x01)                      */
#define SDIO_INTSIG_DMAINTEN_Pos          (3UL)                     /*!< DMAINTEN (Bit 3)                                      */
#define SDIO_INTSIG_DMAINTEN_Msk          (0x8UL)                   /*!< DMAINTEN (Bitfield-Mask: 0x01)                        */
#define SDIO_INTSIG_BLOCKGAPEN_Pos        (2UL)                     /*!< BLOCKGAPEN (Bit 2)                                    */
#define SDIO_INTSIG_BLOCKGAPEN_Msk        (0x4UL)                   /*!< BLOCKGAPEN (Bitfield-Mask: 0x01)                      */
#define SDIO_INTSIG_XFERCMPEN_Pos         (1UL)                     /*!< XFERCMPEN (Bit 1)                                     */
#define SDIO_INTSIG_XFERCMPEN_Msk         (0x2UL)                   /*!< XFERCMPEN (Bitfield-Mask: 0x01)                       */
#define SDIO_INTSIG_CMDCMPEN_Pos          (0UL)                     /*!< CMDCMPEN (Bit 0)                                      */
#define SDIO_INTSIG_CMDCMPEN_Msk          (0x1UL)                   /*!< CMDCMPEN (Bitfield-Mask: 0x01)                        */
/* =========================================================  AUTO  ========================================================== */
#define SDIO_AUTO_PRESETEN_Pos            (31UL)                    /*!< PRESETEN (Bit 31)                                     */
#define SDIO_AUTO_PRESETEN_Msk            (0x80000000UL)            /*!< PRESETEN (Bitfield-Mask: 0x01)                        */
#define SDIO_AUTO_ASYNCINTEN_Pos          (30UL)                    /*!< ASYNCINTEN (Bit 30)                                   */
#define SDIO_AUTO_ASYNCINTEN_Msk          (0x40000000UL)            /*!< ASYNCINTEN (Bitfield-Mask: 0x01)                      */
#define SDIO_AUTO_SAMPLCLKSEL_Pos         (23UL)                    /*!< SAMPLCLKSEL (Bit 23)                                  */
#define SDIO_AUTO_SAMPLCLKSEL_Msk         (0x800000UL)              /*!< SAMPLCLKSEL (Bitfield-Mask: 0x01)                     */
#define SDIO_AUTO_STARTTUNING_Pos         (22UL)                    /*!< STARTTUNING (Bit 22)                                  */
#define SDIO_AUTO_STARTTUNING_Msk         (0x400000UL)              /*!< STARTTUNING (Bitfield-Mask: 0x01)                     */
#define SDIO_AUTO_DRVRSTRSEL_Pos          (20UL)                    /*!< DRVRSTRSEL (Bit 20)                                   */
#define SDIO_AUTO_DRVRSTRSEL_Msk          (0x300000UL)              /*!< DRVRSTRSEL (Bitfield-Mask: 0x03)                      */
#define SDIO_AUTO_SIGNALVOLT_Pos          (19UL)                    /*!< SIGNALVOLT (Bit 19)                                   */
#define SDIO_AUTO_SIGNALVOLT_Msk          (0x80000UL)               /*!< SIGNALVOLT (Bitfield-Mask: 0x01)                      */
#define SDIO_AUTO_UHSMODESEL_Pos          (16UL)                    /*!< UHSMODESEL (Bit 16)                                   */
#define SDIO_AUTO_UHSMODESEL_Msk          (0x70000UL)               /*!< UHSMODESEL (Bitfield-Mask: 0x07)                      */
#define SDIO_AUTO_NOTAUTOCMD12ERR_Pos     (7UL)                     /*!< NOTAUTOCMD12ERR (Bit 7)                               */
#define SDIO_AUTO_NOTAUTOCMD12ERR_Msk     (0x80UL)                  /*!< NOTAUTOCMD12ERR (Bitfield-Mask: 0x01)                 */
#define SDIO_AUTO_CMDIDXERR_Pos           (4UL)                     /*!< CMDIDXERR (Bit 4)                                     */
#define SDIO_AUTO_CMDIDXERR_Msk           (0x10UL)                  /*!< CMDIDXERR (Bitfield-Mask: 0x01)                       */
#define SDIO_AUTO_CMDENDERR_Pos           (3UL)                     /*!< CMDENDERR (Bit 3)                                     */
#define SDIO_AUTO_CMDENDERR_Msk           (0x8UL)                   /*!< CMDENDERR (Bitfield-Mask: 0x01)                       */
#define SDIO_AUTO_CMDCRCERR_Pos           (2UL)                     /*!< CMDCRCERR (Bit 2)                                     */
#define SDIO_AUTO_CMDCRCERR_Msk           (0x4UL)                   /*!< CMDCRCERR (Bitfield-Mask: 0x01)                       */
#define SDIO_AUTO_CMDTOERR_Pos            (1UL)                     /*!< CMDTOERR (Bit 1)                                      */
#define SDIO_AUTO_CMDTOERR_Msk            (0x2UL)                   /*!< CMDTOERR (Bitfield-Mask: 0x01)                        */
#define SDIO_AUTO_CMD12NOTEXEC_Pos        (0UL)                     /*!< CMD12NOTEXEC (Bit 0)                                  */
#define SDIO_AUTO_CMD12NOTEXEC_Msk        (0x1UL)                   /*!< CMD12NOTEXEC (Bitfield-Mask: 0x01)                    */
/* =====================================================  CAPABILITIES0  ===================================================== */
#define SDIO_CAPABILITIES0_SLOTTYPE_Pos   (30UL)                    /*!< SLOTTYPE (Bit 30)                                     */
#define SDIO_CAPABILITIES0_SLOTTYPE_Msk   (0xc0000000UL)            /*!< SLOTTYPE (Bitfield-Mask: 0x03)                        */
#define SDIO_CAPABILITIES0_ASYNCINT_Pos   (29UL)                    /*!< ASYNCINT (Bit 29)                                     */
#define SDIO_CAPABILITIES0_ASYNCINT_Msk   (0x20000000UL)            /*!< ASYNCINT (Bitfield-Mask: 0x01)                        */
#define SDIO_CAPABILITIES0_SYSBUS64_Pos   (28UL)                    /*!< SYSBUS64 (Bit 28)                                     */
#define SDIO_CAPABILITIES0_SYSBUS64_Msk   (0x10000000UL)            /*!< SYSBUS64 (Bitfield-Mask: 0x01)                        */
#define SDIO_CAPABILITIES0_VOLT18V_Pos    (26UL)                    /*!< VOLT18V (Bit 26)                                      */
#define SDIO_CAPABILITIES0_VOLT18V_Msk    (0x4000000UL)             /*!< VOLT18V (Bitfield-Mask: 0x01)                         */
#define SDIO_CAPABILITIES0_VOLT30V_Pos    (25UL)                    /*!< VOLT30V (Bit 25)                                      */
#define SDIO_CAPABILITIES0_VOLT30V_Msk    (0x2000000UL)             /*!< VOLT30V (Bitfield-Mask: 0x01)                         */
#define SDIO_CAPABILITIES0_VOLT33V_Pos    (24UL)                    /*!< VOLT33V (Bit 24)                                      */
#define SDIO_CAPABILITIES0_VOLT33V_Msk    (0x1000000UL)             /*!< VOLT33V (Bitfield-Mask: 0x01)                         */
#define SDIO_CAPABILITIES0_SUSPRES_Pos    (23UL)                    /*!< SUSPRES (Bit 23)                                      */
#define SDIO_CAPABILITIES0_SUSPRES_Msk    (0x800000UL)              /*!< SUSPRES (Bitfield-Mask: 0x01)                         */
#define SDIO_CAPABILITIES0_SDMA_Pos       (22UL)                    /*!< SDMA (Bit 22)                                         */
#define SDIO_CAPABILITIES0_SDMA_Msk       (0x400000UL)              /*!< SDMA (Bitfield-Mask: 0x01)                            */
#define SDIO_CAPABILITIES0_HIGHSPEED_Pos  (21UL)                    /*!< HIGHSPEED (Bit 21)                                    */
#define SDIO_CAPABILITIES0_HIGHSPEED_Msk  (0x200000UL)              /*!< HIGHSPEED (Bitfield-Mask: 0x01)                       */
#define SDIO_CAPABILITIES0_ADMA2_Pos      (19UL)                    /*!< ADMA2 (Bit 19)                                        */
#define SDIO_CAPABILITIES0_ADMA2_Msk      (0x80000UL)               /*!< ADMA2 (Bitfield-Mask: 0x01)                           */
#define SDIO_CAPABILITIES0_EXTMEDIA_Pos   (18UL)                    /*!< EXTMEDIA (Bit 18)                                     */
#define SDIO_CAPABILITIES0_EXTMEDIA_Msk   (0x40000UL)               /*!< EXTMEDIA (Bitfield-Mask: 0x01)                        */
#define SDIO_CAPABILITIES0_MAXBLKLEN_Pos  (16UL)                    /*!< MAXBLKLEN (Bit 16)                                    */
#define SDIO_CAPABILITIES0_MAXBLKLEN_Msk  (0x30000UL)               /*!< MAXBLKLEN (Bitfield-Mask: 0x03)                       */
#define SDIO_CAPABILITIES0_SDCLKFREQ_Pos  (8UL)                     /*!< SDCLKFREQ (Bit 8)                                     */
#define SDIO_CAPABILITIES0_SDCLKFREQ_Msk  (0xff00UL)                /*!< SDCLKFREQ (Bitfield-Mask: 0xff)                       */
#define SDIO_CAPABILITIES0_TOCLKUNIT_Pos  (7UL)                     /*!< TOCLKUNIT (Bit 7)                                     */
#define SDIO_CAPABILITIES0_TOCLKUNIT_Msk  (0x80UL)                  /*!< TOCLKUNIT (Bitfield-Mask: 0x01)                       */
#define SDIO_CAPABILITIES0_TOCLKFREQ_Pos  (0UL)                     /*!< TOCLKFREQ (Bit 0)                                     */
#define SDIO_CAPABILITIES0_TOCLKFREQ_Msk  (0x3fUL)                  /*!< TOCLKFREQ (Bitfield-Mask: 0x3f)                       */
/* =====================================================  CAPABILITIES1  ===================================================== */
#define SDIO_CAPABILITIES1_SPIBLOCKMODE_Pos (25UL)                  /*!< SPIBLOCKMODE (Bit 25)                                 */
#define SDIO_CAPABILITIES1_SPIBLOCKMODE_Msk (0x2000000UL)           /*!< SPIBLOCKMODE (Bitfield-Mask: 0x01)                    */
#define SDIO_CAPABILITIES1_SPIMODE_Pos    (24UL)                    /*!< SPIMODE (Bit 24)                                      */
#define SDIO_CAPABILITIES1_SPIMODE_Msk    (0x1000000UL)             /*!< SPIMODE (Bitfield-Mask: 0x01)                         */
#define SDIO_CAPABILITIES1_CLKMULT_Pos    (16UL)                    /*!< CLKMULT (Bit 16)                                      */
#define SDIO_CAPABILITIES1_CLKMULT_Msk    (0xff0000UL)              /*!< CLKMULT (Bitfield-Mask: 0xff)                         */
#define SDIO_CAPABILITIES1_RETUNINGMODES_Pos (14UL)                 /*!< RETUNINGMODES (Bit 14)                                */
#define SDIO_CAPABILITIES1_RETUNINGMODES_Msk (0xc000UL)             /*!< RETUNINGMODES (Bitfield-Mask: 0x03)                   */
#define SDIO_CAPABILITIES1_TUNINGSDR50_Pos (13UL)                   /*!< TUNINGSDR50 (Bit 13)                                  */
#define SDIO_CAPABILITIES1_TUNINGSDR50_Msk (0x2000UL)               /*!< TUNINGSDR50 (Bitfield-Mask: 0x01)                     */
#define SDIO_CAPABILITIES1_RETUNINGTMRCNT_Pos (8UL)                 /*!< RETUNINGTMRCNT (Bit 8)                                */
#define SDIO_CAPABILITIES1_RETUNINGTMRCNT_Msk (0xf00UL)             /*!< RETUNINGTMRCNT (Bitfield-Mask: 0x0f)                  */
#define SDIO_CAPABILITIES1_TYPED_Pos      (6UL)                     /*!< TYPED (Bit 6)                                         */
#define SDIO_CAPABILITIES1_TYPED_Msk      (0x40UL)                  /*!< TYPED (Bitfield-Mask: 0x01)                           */
#define SDIO_CAPABILITIES1_TYPEC_Pos      (5UL)                     /*!< TYPEC (Bit 5)                                         */
#define SDIO_CAPABILITIES1_TYPEC_Msk      (0x20UL)                  /*!< TYPEC (Bitfield-Mask: 0x01)                           */
#define SDIO_CAPABILITIES1_TYPEA_Pos      (4UL)                     /*!< TYPEA (Bit 4)                                         */
#define SDIO_CAPABILITIES1_TYPEA_Msk      (0x10UL)                  /*!< TYPEA (Bitfield-Mask: 0x01)                           */
#define SDIO_CAPABILITIES1_DDR50_Pos      (2UL)                     /*!< DDR50 (Bit 2)                                         */
#define SDIO_CAPABILITIES1_DDR50_Msk      (0x4UL)                   /*!< DDR50 (Bitfield-Mask: 0x01)                           */
#define SDIO_CAPABILITIES1_SDR104_Pos     (1UL)                     /*!< SDR104 (Bit 1)                                        */
#define SDIO_CAPABILITIES1_SDR104_Msk     (0x2UL)                   /*!< SDR104 (Bitfield-Mask: 0x01)                          */
#define SDIO_CAPABILITIES1_SDR50_Pos      (0UL)                     /*!< SDR50 (Bit 0)                                         */
#define SDIO_CAPABILITIES1_SDR50_Msk      (0x1UL)                   /*!< SDR50 (Bitfield-Mask: 0x01)                           */
/* =======================================================  MAXIMUM0  ======================================================== */
#define SDIO_MAXIMUM0_ALLBITSRSVD_Pos     (0UL)                     /*!< ALLBITSRSVD (Bit 0)                                   */
#define SDIO_MAXIMUM0_ALLBITSRSVD_Msk     (0xffffffffUL)            /*!< ALLBITSRSVD (Bitfield-Mask: 0xffffffff)               */
/* =======================================================  MAXIMUM1  ======================================================== */
#define SDIO_MAXIMUM1_MAXCURR18V_Pos      (16UL)                    /*!< MAXCURR18V (Bit 16)                                   */
#define SDIO_MAXIMUM1_MAXCURR18V_Msk      (0xff0000UL)              /*!< MAXCURR18V (Bitfield-Mask: 0xff)                      */
#define SDIO_MAXIMUM1_MAXCURR30V_Pos      (8UL)                     /*!< MAXCURR30V (Bit 8)                                    */
#define SDIO_MAXIMUM1_MAXCURR30V_Msk      (0xff00UL)                /*!< MAXCURR30V (Bitfield-Mask: 0xff)                      */
#define SDIO_MAXIMUM1_MAXCURR33V_Pos      (0UL)                     /*!< MAXCURR33V (Bit 0)                                    */
#define SDIO_MAXIMUM1_MAXCURR33V_Msk      (0xffUL)                  /*!< MAXCURR33V (Bitfield-Mask: 0xff)                      */
/* =========================================================  FORCE  ========================================================= */
#define SDIO_FORCE_FORCEADMAERR_Pos       (25UL)                    /*!< FORCEADMAERR (Bit 25)                                 */
#define SDIO_FORCE_FORCEADMAERR_Msk       (0x2000000UL)             /*!< FORCEADMAERR (Bitfield-Mask: 0x01)                    */
#define SDIO_FORCE_FORCEACMDERR_Pos       (24UL)                    /*!< FORCEACMDERR (Bit 24)                                 */
#define SDIO_FORCE_FORCEACMDERR_Msk       (0x1000000UL)             /*!< FORCEACMDERR (Bitfield-Mask: 0x01)                    */
#define SDIO_FORCE_FORCECURRLIMITERR_Pos  (23UL)                    /*!< FORCECURRLIMITERR (Bit 23)                            */
#define SDIO_FORCE_FORCECURRLIMITERR_Msk  (0x800000UL)              /*!< FORCECURRLIMITERR (Bitfield-Mask: 0x01)               */
#define SDIO_FORCE_FORCEDATAENDERR_Pos    (22UL)                    /*!< FORCEDATAENDERR (Bit 22)                              */
#define SDIO_FORCE_FORCEDATAENDERR_Msk    (0x400000UL)              /*!< FORCEDATAENDERR (Bitfield-Mask: 0x01)                 */
#define SDIO_FORCE_FORCEDATACRCERR_Pos    (21UL)                    /*!< FORCEDATACRCERR (Bit 21)                              */
#define SDIO_FORCE_FORCEDATACRCERR_Msk    (0x200000UL)              /*!< FORCEDATACRCERR (Bitfield-Mask: 0x01)                 */
#define SDIO_FORCE_FORCEDATATOERR_Pos     (20UL)                    /*!< FORCEDATATOERR (Bit 20)                               */
#define SDIO_FORCE_FORCEDATATOERR_Msk     (0x100000UL)              /*!< FORCEDATATOERR (Bitfield-Mask: 0x01)                  */
#define SDIO_FORCE_FORCECMDIDXERR_Pos     (19UL)                    /*!< FORCECMDIDXERR (Bit 19)                               */
#define SDIO_FORCE_FORCECMDIDXERR_Msk     (0x80000UL)               /*!< FORCECMDIDXERR (Bitfield-Mask: 0x01)                  */
#define SDIO_FORCE_FORCECMDENDERR_Pos     (18UL)                    /*!< FORCECMDENDERR (Bit 18)                               */
#define SDIO_FORCE_FORCECMDENDERR_Msk     (0x40000UL)               /*!< FORCECMDENDERR (Bitfield-Mask: 0x01)                  */
#define SDIO_FORCE_FORCECMDCRCERR_Pos     (17UL)                    /*!< FORCECMDCRCERR (Bit 17)                               */
#define SDIO_FORCE_FORCECMDCRCERR_Msk     (0x20000UL)               /*!< FORCECMDCRCERR (Bitfield-Mask: 0x01)                  */
#define SDIO_FORCE_FORCECMDTOERR_Pos      (16UL)                    /*!< FORCECMDTOERR (Bit 16)                                */
#define SDIO_FORCE_FORCECMDTOERR_Msk      (0x10000UL)               /*!< FORCECMDTOERR (Bitfield-Mask: 0x01)                   */
#define SDIO_FORCE_FORCEACMDISSUEDERR_Pos (7UL)                     /*!< FORCEACMDISSUEDERR (Bit 7)                            */
#define SDIO_FORCE_FORCEACMDISSUEDERR_Msk (0x80UL)                  /*!< FORCEACMDISSUEDERR (Bitfield-Mask: 0x01)              */
#define SDIO_FORCE_FORCEACMDIDXERR_Pos    (4UL)                     /*!< FORCEACMDIDXERR (Bit 4)                               */
#define SDIO_FORCE_FORCEACMDIDXERR_Msk    (0x10UL)                  /*!< FORCEACMDIDXERR (Bitfield-Mask: 0x01)                 */
#define SDIO_FORCE_FORCEACMDENDERR_Pos    (3UL)                     /*!< FORCEACMDENDERR (Bit 3)                               */
#define SDIO_FORCE_FORCEACMDENDERR_Msk    (0x8UL)                   /*!< FORCEACMDENDERR (Bitfield-Mask: 0x01)                 */
#define SDIO_FORCE_FORCEACMDCRCERR_Pos    (2UL)                     /*!< FORCEACMDCRCERR (Bit 2)                               */
#define SDIO_FORCE_FORCEACMDCRCERR_Msk    (0x4UL)                   /*!< FORCEACMDCRCERR (Bitfield-Mask: 0x01)                 */
#define SDIO_FORCE_FORCEACMDTOERR_Pos     (1UL)                     /*!< FORCEACMDTOERR (Bit 1)                                */
#define SDIO_FORCE_FORCEACMDTOERR_Msk     (0x2UL)                   /*!< FORCEACMDTOERR (Bitfield-Mask: 0x01)                  */
#define SDIO_FORCE_FORCEACMD12NOT_Pos     (0UL)                     /*!< FORCEACMD12NOT (Bit 0)                                */
#define SDIO_FORCE_FORCEACMD12NOT_Msk     (0x1UL)                   /*!< FORCEACMD12NOT (Bitfield-Mask: 0x01)                  */
/* =========================================================  ADMA  ========================================================== */
#define SDIO_ADMA_ADMALENMISMATCHERR_Pos  (2UL)                     /*!< ADMALENMISMATCHERR (Bit 2)                            */
#define SDIO_ADMA_ADMALENMISMATCHERR_Msk  (0x4UL)                   /*!< ADMALENMISMATCHERR (Bitfield-Mask: 0x01)              */
#define SDIO_ADMA_ADMAERRORSTATE_Pos      (0UL)                     /*!< ADMAERRORSTATE (Bit 0)                                */
#define SDIO_ADMA_ADMAERRORSTATE_Msk      (0x3UL)                   /*!< ADMAERRORSTATE (Bitfield-Mask: 0x03)                  */
/* =======================================================  ADMALOWD  ======================================================== */
#define SDIO_ADMALOWD_LOWD_Pos            (0UL)                     /*!< LOWD (Bit 0)                                          */
#define SDIO_ADMALOWD_LOWD_Msk            (0xffffffffUL)            /*!< LOWD (Bitfield-Mask: 0xffffffff)                      */
/* =======================================================  ADMAHIWD  ======================================================== */
#define SDIO_ADMAHIWD_HIWD_Pos            (0UL)                     /*!< HIWD (Bit 0)                                          */
#define SDIO_ADMAHIWD_HIWD_Msk            (0xffffffffUL)            /*!< HIWD (Bitfield-Mask: 0xffffffff)                      */
/* ========================================================  PRESET0  ======================================================== */
#define SDIO_PRESET0_DEFSPDRVRSTRSEL_Pos  (30UL)                    /*!< DEFSPDRVRSTRSEL (Bit 30)                              */
#define SDIO_PRESET0_DEFSPDRVRSTRSEL_Msk  (0xc0000000UL)            /*!< DEFSPDRVRSTRSEL (Bitfield-Mask: 0x03)                 */
#define SDIO_PRESET0_DEFSPCLKGENSEL_Pos   (26UL)                    /*!< DEFSPCLKGENSEL (Bit 26)                               */
#define SDIO_PRESET0_DEFSPCLKGENSEL_Msk   (0x4000000UL)             /*!< DEFSPCLKGENSEL (Bitfield-Mask: 0x01)                  */
#define SDIO_PRESET0_DEFSPSDCLKFREQSEL_Pos (16UL)                   /*!< DEFSPSDCLKFREQSEL (Bit 16)                            */
#define SDIO_PRESET0_DEFSPSDCLKFREQSEL_Msk (0x3ff0000UL)            /*!< DEFSPSDCLKFREQSEL (Bitfield-Mask: 0x3ff)              */
#define SDIO_PRESET0_HISPDRVRSTRSEL_Pos   (14UL)                    /*!< HISPDRVRSTRSEL (Bit 14)                               */
#define SDIO_PRESET0_HISPDRVRSTRSEL_Msk   (0xc000UL)                /*!< HISPDRVRSTRSEL (Bitfield-Mask: 0x03)                  */
#define SDIO_PRESET0_HISPCLKGENSEL_Pos    (10UL)                    /*!< HISPCLKGENSEL (Bit 10)                                */
#define SDIO_PRESET0_HISPCLKGENSEL_Msk    (0x400UL)                 /*!< HISPCLKGENSEL (Bitfield-Mask: 0x01)                   */
#define SDIO_PRESET0_HISPSDCLKFREQSEL_Pos (0UL)                     /*!< HISPSDCLKFREQSEL (Bit 0)                              */
#define SDIO_PRESET0_HISPSDCLKFREQSEL_Msk (0x3ffUL)                 /*!< HISPSDCLKFREQSEL (Bitfield-Mask: 0x3ff)               */
/* ========================================================  PRESET1  ======================================================== */
#define SDIO_PRESET1_SDR12DRVRSTRSEL_Pos  (30UL)                    /*!< SDR12DRVRSTRSEL (Bit 30)                              */
#define SDIO_PRESET1_SDR12DRVRSTRSEL_Msk  (0xc0000000UL)            /*!< SDR12DRVRSTRSEL (Bitfield-Mask: 0x03)                 */
#define SDIO_PRESET1_SDR12CLKGENSEL_Pos   (26UL)                    /*!< SDR12CLKGENSEL (Bit 26)                               */
#define SDIO_PRESET1_SDR12CLKGENSEL_Msk   (0x4000000UL)             /*!< SDR12CLKGENSEL (Bitfield-Mask: 0x01)                  */
#define SDIO_PRESET1_SDR12SDCLKFREQSEL_Pos (16UL)                   /*!< SDR12SDCLKFREQSEL (Bit 16)                            */
#define SDIO_PRESET1_SDR12SDCLKFREQSEL_Msk (0x3ff0000UL)            /*!< SDR12SDCLKFREQSEL (Bitfield-Mask: 0x3ff)              */
#define SDIO_PRESET1_HSDRVRSTRSEL_Pos     (14UL)                    /*!< HSDRVRSTRSEL (Bit 14)                                 */
#define SDIO_PRESET1_HSDRVRSTRSEL_Msk     (0xc000UL)                /*!< HSDRVRSTRSEL (Bitfield-Mask: 0x03)                    */
#define SDIO_PRESET1_HSCLKGENSEL_Pos      (10UL)                    /*!< HSCLKGENSEL (Bit 10)                                  */
#define SDIO_PRESET1_HSCLKGENSEL_Msk      (0x400UL)                 /*!< HSCLKGENSEL (Bitfield-Mask: 0x01)                     */
#define SDIO_PRESET1_HSSDCLKFREQSEL_Pos   (0UL)                     /*!< HSSDCLKFREQSEL (Bit 0)                                */
#define SDIO_PRESET1_HSSDCLKFREQSEL_Msk   (0x3ffUL)                 /*!< HSSDCLKFREQSEL (Bitfield-Mask: 0x3ff)                 */
/* ========================================================  PRESET2  ======================================================== */
#define SDIO_PRESET2_SDR50DRVRSTRSEL_Pos  (30UL)                    /*!< SDR50DRVRSTRSEL (Bit 30)                              */
#define SDIO_PRESET2_SDR50DRVRSTRSEL_Msk  (0xc0000000UL)            /*!< SDR50DRVRSTRSEL (Bitfield-Mask: 0x03)                 */
#define SDIO_PRESET2_SDR50CLKGENSEL_Pos   (26UL)                    /*!< SDR50CLKGENSEL (Bit 26)                               */
#define SDIO_PRESET2_SDR50CLKGENSEL_Msk   (0x4000000UL)             /*!< SDR50CLKGENSEL (Bitfield-Mask: 0x01)                  */
#define SDIO_PRESET2_SDR50SDCLKFREQSEL_Pos (16UL)                   /*!< SDR50SDCLKFREQSEL (Bit 16)                            */
#define SDIO_PRESET2_SDR50SDCLKFREQSEL_Msk (0x3ff0000UL)            /*!< SDR50SDCLKFREQSEL (Bitfield-Mask: 0x3ff)              */
#define SDIO_PRESET2_SDR25DRVRSTRSEL_Pos  (14UL)                    /*!< SDR25DRVRSTRSEL (Bit 14)                              */
#define SDIO_PRESET2_SDR25DRVRSTRSEL_Msk  (0xc000UL)                /*!< SDR25DRVRSTRSEL (Bitfield-Mask: 0x03)                 */
#define SDIO_PRESET2_SDR25CLKGENSEL_Pos   (10UL)                    /*!< SDR25CLKGENSEL (Bit 10)                               */
#define SDIO_PRESET2_SDR25CLKGENSEL_Msk   (0x400UL)                 /*!< SDR25CLKGENSEL (Bitfield-Mask: 0x01)                  */
#define SDIO_PRESET2_SDR25SDCLKFREQSEL_Pos (0UL)                    /*!< SDR25SDCLKFREQSEL (Bit 0)                             */
#define SDIO_PRESET2_SDR25SDCLKFREQSEL_Msk (0x3ffUL)                /*!< SDR25SDCLKFREQSEL (Bitfield-Mask: 0x3ff)              */
/* ========================================================  PRESET3  ======================================================== */
#define SDIO_PRESET3_DDR50DRVRSTRSEL_Pos  (30UL)                    /*!< DDR50DRVRSTRSEL (Bit 30)                              */
#define SDIO_PRESET3_DDR50DRVRSTRSEL_Msk  (0xc0000000UL)            /*!< DDR50DRVRSTRSEL (Bitfield-Mask: 0x03)                 */
#define SDIO_PRESET3_DDR50CLKGENSEL_Pos   (26UL)                    /*!< DDR50CLKGENSEL (Bit 26)                               */
#define SDIO_PRESET3_DDR50CLKGENSEL_Msk   (0x4000000UL)             /*!< DDR50CLKGENSEL (Bitfield-Mask: 0x01)                  */
#define SDIO_PRESET3_DDR50SDCLKFREQSEL_Pos (16UL)                   /*!< DDR50SDCLKFREQSEL (Bit 16)                            */
#define SDIO_PRESET3_DDR50SDCLKFREQSEL_Msk (0x3ff0000UL)            /*!< DDR50SDCLKFREQSEL (Bitfield-Mask: 0x3ff)              */
#define SDIO_PRESET3_SDR104DRVRSTRSEL_Pos (14UL)                    /*!< SDR104DRVRSTRSEL (Bit 14)                             */
#define SDIO_PRESET3_SDR104DRVRSTRSEL_Msk (0xc000UL)                /*!< SDR104DRVRSTRSEL (Bitfield-Mask: 0x03)                */
#define SDIO_PRESET3_SDR104CLKGENSEL_Pos  (10UL)                    /*!< SDR104CLKGENSEL (Bit 10)                              */
#define SDIO_PRESET3_SDR104CLKGENSEL_Msk  (0x400UL)                 /*!< SDR104CLKGENSEL (Bitfield-Mask: 0x01)                 */
#define SDIO_PRESET3_SDR104SDCLKFREQSEL_Pos (0UL)                   /*!< SDR104SDCLKFREQSEL (Bit 0)                            */
#define SDIO_PRESET3_SDR104SDCLKFREQSEL_Msk (0x3ffUL)               /*!< SDR104SDCLKFREQSEL (Bitfield-Mask: 0x3ff)             */
/* ======================================================  BOOTTOCTRL  ======================================================= */
#define SDIO_BOOTTOCTRL_BOOTDATATO_Pos    (0UL)                     /*!< BOOTDATATO (Bit 0)                                    */
#define SDIO_BOOTTOCTRL_BOOTDATATO_Msk    (0xffffffffUL)            /*!< BOOTDATATO (Bitfield-Mask: 0xffffffff)                */
/* ========================================================  VENDOR  ========================================================= */
#define SDIO_VENDOR_DLYDIS_Pos            (1UL)                     /*!< DLYDIS (Bit 1)                                        */
#define SDIO_VENDOR_DLYDIS_Msk            (0x2UL)                   /*!< DLYDIS (Bitfield-Mask: 0x01)                          */
#define SDIO_VENDOR_GATESDCLKEN_Pos       (0UL)                     /*!< GATESDCLKEN (Bit 0)                                   */
#define SDIO_VENDOR_GATESDCLKEN_Msk       (0x1UL)                   /*!< GATESDCLKEN (Bitfield-Mask: 0x01)                     */
/* =======================================================  SLOTSTAT  ======================================================== */
#define SDIO_SLOTSTAT_VENDORVER_Pos       (24UL)                    /*!< VENDORVER (Bit 24)                                    */
#define SDIO_SLOTSTAT_VENDORVER_Msk       (0xff000000UL)            /*!< VENDORVER (Bitfield-Mask: 0xff)                       */
#define SDIO_SLOTSTAT_SPECVER_Pos         (16UL)                    /*!< SPECVER (Bit 16)                                      */
#define SDIO_SLOTSTAT_SPECVER_Msk         (0xff0000UL)              /*!< SPECVER (Bitfield-Mask: 0xff)                         */
#define SDIO_SLOTSTAT_INTSLOT0_Pos        (0UL)                     /*!< INTSLOT0 (Bit 0)                                      */
#define SDIO_SLOTSTAT_INTSLOT0_Msk        (0x1UL)                   /*!< INTSLOT0 (Bitfield-Mask: 0x01)                        */


/* =========================================================================================================================== */
/* ================                                         SECURITY                                          ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
#define SECURITY_CTRL_CRCERROR_Pos        (31UL)                    /*!< CRCERROR (Bit 31)                                     */
#define SECURITY_CTRL_CRCERROR_Msk        (0x80000000UL)            /*!< CRCERROR (Bitfield-Mask: 0x01)                        */
#define SECURITY_CTRL_FUNCTION_Pos        (4UL)                     /*!< FUNCTION (Bit 4)                                      */
#define SECURITY_CTRL_FUNCTION_Msk        (0xf0UL)                  /*!< FUNCTION (Bitfield-Mask: 0x0f)                        */
#define SECURITY_CTRL_ENABLE_Pos          (0UL)                     /*!< ENABLE (Bit 0)                                        */
#define SECURITY_CTRL_ENABLE_Msk          (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
/* ========================================================  SRCADDR  ======================================================== */
#define SECURITY_SRCADDR_ADDR_Pos         (0UL)                     /*!< ADDR (Bit 0)                                          */
#define SECURITY_SRCADDR_ADDR_Msk         (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* ==========================================================  LEN  ========================================================== */
#define SECURITY_LEN_LEN_Pos              (2UL)                     /*!< LEN (Bit 2)                                           */
#define SECURITY_LEN_LEN_Msk              (0xfffffcUL)              /*!< LEN (Bitfield-Mask: 0x3fffff)                         */
/* ========================================================  RESULT  ========================================================= */
#define SECURITY_RESULT_CRC_Pos           (0UL)                     /*!< CRC (Bit 0)                                           */
#define SECURITY_RESULT_CRC_Msk           (0xffffffffUL)            /*!< CRC (Bitfield-Mask: 0xffffffff)                       */
/* =======================================================  LOCKCTRL  ======================================================== */
#define SECURITY_LOCKCTRL_SELECT_Pos      (0UL)                     /*!< SELECT (Bit 0)                                        */
#define SECURITY_LOCKCTRL_SELECT_Msk      (0xffUL)                  /*!< SELECT (Bitfield-Mask: 0xff)                          */
/* =======================================================  LOCKSTAT  ======================================================== */
#define SECURITY_LOCKSTAT_STATUS_Pos      (0UL)                     /*!< STATUS (Bit 0)                                        */
#define SECURITY_LOCKSTAT_STATUS_Msk      (0xffffffffUL)            /*!< STATUS (Bitfield-Mask: 0xffffffff)                    */
/* =========================================================  KEY0  ========================================================== */
#define SECURITY_KEY0_KEY0_Pos            (0UL)                     /*!< KEY0 (Bit 0)                                          */
#define SECURITY_KEY0_KEY0_Msk            (0xffffffffUL)            /*!< KEY0 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  KEY1  ========================================================== */
#define SECURITY_KEY1_KEY1_Pos            (0UL)                     /*!< KEY1 (Bit 0)                                          */
#define SECURITY_KEY1_KEY1_Msk            (0xffffffffUL)            /*!< KEY1 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  KEY2  ========================================================== */
#define SECURITY_KEY2_KEY2_Pos            (0UL)                     /*!< KEY2 (Bit 0)                                          */
#define SECURITY_KEY2_KEY2_Msk            (0xffffffffUL)            /*!< KEY2 (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  KEY3  ========================================================== */
#define SECURITY_KEY3_KEY3_Pos            (0UL)                     /*!< KEY3 (Bit 0)                                          */
#define SECURITY_KEY3_KEY3_Msk            (0xffffffffUL)            /*!< KEY3 (Bitfield-Mask: 0xffffffff)                      */


/* =========================================================================================================================== */
/* ================                                          STIMER                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  STCFG  ========================================================= */
#define STIMER_STCFG_FREEZE_Pos           (31UL)                    /*!< FREEZE (Bit 31)                                       */
#define STIMER_STCFG_FREEZE_Msk           (0x80000000UL)            /*!< FREEZE (Bitfield-Mask: 0x01)                          */
#define STIMER_STCFG_CLEAR_Pos            (30UL)                    /*!< CLEAR (Bit 30)                                        */
#define STIMER_STCFG_CLEAR_Msk            (0x40000000UL)            /*!< CLEAR (Bitfield-Mask: 0x01)                           */
#define STIMER_STCFG_COMPAREHEN_Pos       (15UL)                    /*!< COMPAREHEN (Bit 15)                                   */
#define STIMER_STCFG_COMPAREHEN_Msk       (0x8000UL)                /*!< COMPAREHEN (Bitfield-Mask: 0x01)                      */
#define STIMER_STCFG_COMPAREGEN_Pos       (14UL)                    /*!< COMPAREGEN (Bit 14)                                   */
#define STIMER_STCFG_COMPAREGEN_Msk       (0x4000UL)                /*!< COMPAREGEN (Bitfield-Mask: 0x01)                      */
#define STIMER_STCFG_COMPAREFEN_Pos       (13UL)                    /*!< COMPAREFEN (Bit 13)                                   */
#define STIMER_STCFG_COMPAREFEN_Msk       (0x2000UL)                /*!< COMPAREFEN (Bitfield-Mask: 0x01)                      */
#define STIMER_STCFG_COMPAREEEN_Pos       (12UL)                    /*!< COMPAREEEN (Bit 12)                                   */
#define STIMER_STCFG_COMPAREEEN_Msk       (0x1000UL)                /*!< COMPAREEEN (Bitfield-Mask: 0x01)                      */
#define STIMER_STCFG_COMPAREDEN_Pos       (11UL)                    /*!< COMPAREDEN (Bit 11)                                   */
#define STIMER_STCFG_COMPAREDEN_Msk       (0x800UL)                 /*!< COMPAREDEN (Bitfield-Mask: 0x01)                      */
#define STIMER_STCFG_COMPARECEN_Pos       (10UL)                    /*!< COMPARECEN (Bit 10)                                   */
#define STIMER_STCFG_COMPARECEN_Msk       (0x400UL)                 /*!< COMPARECEN (Bitfield-Mask: 0x01)                      */
#define STIMER_STCFG_COMPAREBEN_Pos       (9UL)                     /*!< COMPAREBEN (Bit 9)                                    */
#define STIMER_STCFG_COMPAREBEN_Msk       (0x200UL)                 /*!< COMPAREBEN (Bitfield-Mask: 0x01)                      */
#define STIMER_STCFG_COMPAREAEN_Pos       (8UL)                     /*!< COMPAREAEN (Bit 8)                                    */
#define STIMER_STCFG_COMPAREAEN_Msk       (0x100UL)                 /*!< COMPAREAEN (Bitfield-Mask: 0x01)                      */
#define STIMER_STCFG_CLKSEL_Pos           (0UL)                     /*!< CLKSEL (Bit 0)                                        */
#define STIMER_STCFG_CLKSEL_Msk           (0xfUL)                   /*!< CLKSEL (Bitfield-Mask: 0x0f)                          */
/* =========================================================  STTMR  ========================================================= */
#define STIMER_STTMR_STTMR_Pos            (0UL)                     /*!< STTMR (Bit 0)                                         */
#define STIMER_STTMR_STTMR_Msk            (0xffffffffUL)            /*!< STTMR (Bitfield-Mask: 0xffffffff)                     */
/* =======================================================  SCAPCTRL0  ======================================================= */
#define STIMER_SCAPCTRL0_CAPTURE0_Pos     (9UL)                     /*!< CAPTURE0 (Bit 9)                                      */
#define STIMER_SCAPCTRL0_CAPTURE0_Msk     (0x200UL)                 /*!< CAPTURE0 (Bitfield-Mask: 0x01)                        */
#define STIMER_SCAPCTRL0_STPOL0_Pos       (8UL)                     /*!< STPOL0 (Bit 8)                                        */
#define STIMER_SCAPCTRL0_STPOL0_Msk       (0x100UL)                 /*!< STPOL0 (Bitfield-Mask: 0x01)                          */
#define STIMER_SCAPCTRL0_STSEL0_Pos       (0UL)                     /*!< STSEL0 (Bit 0)                                        */
#define STIMER_SCAPCTRL0_STSEL0_Msk       (0x7fUL)                  /*!< STSEL0 (Bitfield-Mask: 0x7f)                          */
/* =======================================================  SCAPCTRL1  ======================================================= */
#define STIMER_SCAPCTRL1_CAPTURE1_Pos     (9UL)                     /*!< CAPTURE1 (Bit 9)                                      */
#define STIMER_SCAPCTRL1_CAPTURE1_Msk     (0x200UL)                 /*!< CAPTURE1 (Bitfield-Mask: 0x01)                        */
#define STIMER_SCAPCTRL1_STPOL1_Pos       (8UL)                     /*!< STPOL1 (Bit 8)                                        */
#define STIMER_SCAPCTRL1_STPOL1_Msk       (0x100UL)                 /*!< STPOL1 (Bitfield-Mask: 0x01)                          */
#define STIMER_SCAPCTRL1_STSEL1_Pos       (0UL)                     /*!< STSEL1 (Bit 0)                                        */
#define STIMER_SCAPCTRL1_STSEL1_Msk       (0x7fUL)                  /*!< STSEL1 (Bitfield-Mask: 0x7f)                          */
/* =======================================================  SCAPCTRL2  ======================================================= */
#define STIMER_SCAPCTRL2_CAPTURE2_Pos     (9UL)                     /*!< CAPTURE2 (Bit 9)                                      */
#define STIMER_SCAPCTRL2_CAPTURE2_Msk     (0x200UL)                 /*!< CAPTURE2 (Bitfield-Mask: 0x01)                        */
#define STIMER_SCAPCTRL2_STPOL2_Pos       (8UL)                     /*!< STPOL2 (Bit 8)                                        */
#define STIMER_SCAPCTRL2_STPOL2_Msk       (0x100UL)                 /*!< STPOL2 (Bitfield-Mask: 0x01)                          */
#define STIMER_SCAPCTRL2_STSEL2_Pos       (0UL)                     /*!< STSEL2 (Bit 0)                                        */
#define STIMER_SCAPCTRL2_STSEL2_Msk       (0x7fUL)                  /*!< STSEL2 (Bitfield-Mask: 0x7f)                          */
/* =======================================================  SCAPCTRL3  ======================================================= */
#define STIMER_SCAPCTRL3_CAPTURE3_Pos     (9UL)                     /*!< CAPTURE3 (Bit 9)                                      */
#define STIMER_SCAPCTRL3_CAPTURE3_Msk     (0x200UL)                 /*!< CAPTURE3 (Bitfield-Mask: 0x01)                        */
#define STIMER_SCAPCTRL3_STPOL3_Pos       (8UL)                     /*!< STPOL3 (Bit 8)                                        */
#define STIMER_SCAPCTRL3_STPOL3_Msk       (0x100UL)                 /*!< STPOL3 (Bitfield-Mask: 0x01)                          */
#define STIMER_SCAPCTRL3_STSEL3_Pos       (0UL)                     /*!< STSEL3 (Bit 0)                                        */
#define STIMER_SCAPCTRL3_STSEL3_Msk       (0x7fUL)                  /*!< STSEL3 (Bitfield-Mask: 0x7f)                          */
/* ========================================================  SCMPR0  ========================================================= */
#define STIMER_SCMPR0_SCMPR0_Pos          (0UL)                     /*!< SCMPR0 (Bit 0)                                        */
#define STIMER_SCMPR0_SCMPR0_Msk          (0xffffffffUL)            /*!< SCMPR0 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  SCMPR1  ========================================================= */
#define STIMER_SCMPR1_SCMPR1_Pos          (0UL)                     /*!< SCMPR1 (Bit 0)                                        */
#define STIMER_SCMPR1_SCMPR1_Msk          (0xffffffffUL)            /*!< SCMPR1 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  SCMPR2  ========================================================= */
#define STIMER_SCMPR2_SCMPR2_Pos          (0UL)                     /*!< SCMPR2 (Bit 0)                                        */
#define STIMER_SCMPR2_SCMPR2_Msk          (0xffffffffUL)            /*!< SCMPR2 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  SCMPR3  ========================================================= */
#define STIMER_SCMPR3_SCMPR3_Pos          (0UL)                     /*!< SCMPR3 (Bit 0)                                        */
#define STIMER_SCMPR3_SCMPR3_Msk          (0xffffffffUL)            /*!< SCMPR3 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  SCMPR4  ========================================================= */
#define STIMER_SCMPR4_SCMPR4_Pos          (0UL)                     /*!< SCMPR4 (Bit 0)                                        */
#define STIMER_SCMPR4_SCMPR4_Msk          (0xffffffffUL)            /*!< SCMPR4 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  SCMPR5  ========================================================= */
#define STIMER_SCMPR5_SCMPR5_Pos          (0UL)                     /*!< SCMPR5 (Bit 0)                                        */
#define STIMER_SCMPR5_SCMPR5_Msk          (0xffffffffUL)            /*!< SCMPR5 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  SCMPR6  ========================================================= */
#define STIMER_SCMPR6_SCMPR6_Pos          (0UL)                     /*!< SCMPR6 (Bit 0)                                        */
#define STIMER_SCMPR6_SCMPR6_Msk          (0xffffffffUL)            /*!< SCMPR6 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  SCMPR7  ========================================================= */
#define STIMER_SCMPR7_SCMPR7_Pos          (0UL)                     /*!< SCMPR7 (Bit 0)                                        */
#define STIMER_SCMPR7_SCMPR7_Msk          (0xffffffffUL)            /*!< SCMPR7 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  SCAPT0  ========================================================= */
#define STIMER_SCAPT0_SCAPT0_Pos          (0UL)                     /*!< SCAPT0 (Bit 0)                                        */
#define STIMER_SCAPT0_SCAPT0_Msk          (0xffffffffUL)            /*!< SCAPT0 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  SCAPT1  ========================================================= */
#define STIMER_SCAPT1_SCAPT1_Pos          (0UL)                     /*!< SCAPT1 (Bit 0)                                        */
#define STIMER_SCAPT1_SCAPT1_Msk          (0xffffffffUL)            /*!< SCAPT1 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  SCAPT2  ========================================================= */
#define STIMER_SCAPT2_SCAPT2_Pos          (0UL)                     /*!< SCAPT2 (Bit 0)                                        */
#define STIMER_SCAPT2_SCAPT2_Msk          (0xffffffffUL)            /*!< SCAPT2 (Bitfield-Mask: 0xffffffff)                    */
/* ========================================================  SCAPT3  ========================================================= */
#define STIMER_SCAPT3_SCAPT3_Pos          (0UL)                     /*!< SCAPT3 (Bit 0)                                        */
#define STIMER_SCAPT3_SCAPT3_Msk          (0xffffffffUL)            /*!< SCAPT3 (Bitfield-Mask: 0xffffffff)                    */
/* =========================================================  SNVR0  ========================================================= */
#define STIMER_SNVR0_SNVR0_Pos            (0UL)                     /*!< SNVR0 (Bit 0)                                         */
#define STIMER_SNVR0_SNVR0_Msk            (0xffffffffUL)            /*!< SNVR0 (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  SNVR1  ========================================================= */
#define STIMER_SNVR1_SNVR1_Pos            (0UL)                     /*!< SNVR1 (Bit 0)                                         */
#define STIMER_SNVR1_SNVR1_Msk            (0xffffffffUL)            /*!< SNVR1 (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  SNVR2  ========================================================= */
#define STIMER_SNVR2_SNVR2_Pos            (0UL)                     /*!< SNVR2 (Bit 0)                                         */
#define STIMER_SNVR2_SNVR2_Msk            (0xffffffffUL)            /*!< SNVR2 (Bitfield-Mask: 0xffffffff)                     */
/* =======================================================  STMINTEN  ======================================================== */
#define STIMER_STMINTEN_CAPTURED_Pos      (12UL)                    /*!< CAPTURED (Bit 12)                                     */
#define STIMER_STMINTEN_CAPTURED_Msk      (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTEN_CAPTUREC_Pos      (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
#define STIMER_STMINTEN_CAPTUREC_Msk      (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTEN_CAPTUREB_Pos      (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
#define STIMER_STMINTEN_CAPTUREB_Msk      (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTEN_CAPTUREA_Pos      (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
#define STIMER_STMINTEN_CAPTUREA_Msk      (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTEN_OVERFLOW_Pos      (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
#define STIMER_STMINTEN_OVERFLOW_Msk      (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTEN_COMPAREH_Pos      (7UL)                     /*!< COMPAREH (Bit 7)                                      */
#define STIMER_STMINTEN_COMPAREH_Msk      (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTEN_COMPAREG_Pos      (6UL)                     /*!< COMPAREG (Bit 6)                                      */
#define STIMER_STMINTEN_COMPAREG_Msk      (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTEN_COMPAREF_Pos      (5UL)                     /*!< COMPAREF (Bit 5)                                      */
#define STIMER_STMINTEN_COMPAREF_Msk      (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTEN_COMPAREE_Pos      (4UL)                     /*!< COMPAREE (Bit 4)                                      */
#define STIMER_STMINTEN_COMPAREE_Msk      (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTEN_COMPARED_Pos      (3UL)                     /*!< COMPARED (Bit 3)                                      */
#define STIMER_STMINTEN_COMPARED_Msk      (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTEN_COMPAREC_Pos      (2UL)                     /*!< COMPAREC (Bit 2)                                      */
#define STIMER_STMINTEN_COMPAREC_Msk      (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTEN_COMPAREB_Pos      (1UL)                     /*!< COMPAREB (Bit 1)                                      */
#define STIMER_STMINTEN_COMPAREB_Msk      (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTEN_COMPAREA_Pos      (0UL)                     /*!< COMPAREA (Bit 0)                                      */
#define STIMER_STMINTEN_COMPAREA_Msk      (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
/* ======================================================  STMINTSTAT  ======================================================= */
#define STIMER_STMINTSTAT_CAPTURED_Pos    (12UL)                    /*!< CAPTURED (Bit 12)                                     */
#define STIMER_STMINTSTAT_CAPTURED_Msk    (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSTAT_CAPTUREC_Pos    (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
#define STIMER_STMINTSTAT_CAPTUREC_Msk    (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSTAT_CAPTUREB_Pos    (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
#define STIMER_STMINTSTAT_CAPTUREB_Msk    (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSTAT_CAPTUREA_Pos    (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
#define STIMER_STMINTSTAT_CAPTUREA_Msk    (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSTAT_OVERFLOW_Pos    (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
#define STIMER_STMINTSTAT_OVERFLOW_Msk    (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSTAT_COMPAREH_Pos    (7UL)                     /*!< COMPAREH (Bit 7)                                      */
#define STIMER_STMINTSTAT_COMPAREH_Msk    (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSTAT_COMPAREG_Pos    (6UL)                     /*!< COMPAREG (Bit 6)                                      */
#define STIMER_STMINTSTAT_COMPAREG_Msk    (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSTAT_COMPAREF_Pos    (5UL)                     /*!< COMPAREF (Bit 5)                                      */
#define STIMER_STMINTSTAT_COMPAREF_Msk    (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSTAT_COMPAREE_Pos    (4UL)                     /*!< COMPAREE (Bit 4)                                      */
#define STIMER_STMINTSTAT_COMPAREE_Msk    (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSTAT_COMPARED_Pos    (3UL)                     /*!< COMPARED (Bit 3)                                      */
#define STIMER_STMINTSTAT_COMPARED_Msk    (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSTAT_COMPAREC_Pos    (2UL)                     /*!< COMPAREC (Bit 2)                                      */
#define STIMER_STMINTSTAT_COMPAREC_Msk    (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSTAT_COMPAREB_Pos    (1UL)                     /*!< COMPAREB (Bit 1)                                      */
#define STIMER_STMINTSTAT_COMPAREB_Msk    (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSTAT_COMPAREA_Pos    (0UL)                     /*!< COMPAREA (Bit 0)                                      */
#define STIMER_STMINTSTAT_COMPAREA_Msk    (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
/* =======================================================  STMINTCLR  ======================================================= */
#define STIMER_STMINTCLR_CAPTURED_Pos     (12UL)                    /*!< CAPTURED (Bit 12)                                     */
#define STIMER_STMINTCLR_CAPTURED_Msk     (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTCLR_CAPTUREC_Pos     (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
#define STIMER_STMINTCLR_CAPTUREC_Msk     (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTCLR_CAPTUREB_Pos     (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
#define STIMER_STMINTCLR_CAPTUREB_Msk     (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTCLR_CAPTUREA_Pos     (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
#define STIMER_STMINTCLR_CAPTUREA_Msk     (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTCLR_OVERFLOW_Pos     (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
#define STIMER_STMINTCLR_OVERFLOW_Msk     (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTCLR_COMPAREH_Pos     (7UL)                     /*!< COMPAREH (Bit 7)                                      */
#define STIMER_STMINTCLR_COMPAREH_Msk     (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTCLR_COMPAREG_Pos     (6UL)                     /*!< COMPAREG (Bit 6)                                      */
#define STIMER_STMINTCLR_COMPAREG_Msk     (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTCLR_COMPAREF_Pos     (5UL)                     /*!< COMPAREF (Bit 5)                                      */
#define STIMER_STMINTCLR_COMPAREF_Msk     (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTCLR_COMPAREE_Pos     (4UL)                     /*!< COMPAREE (Bit 4)                                      */
#define STIMER_STMINTCLR_COMPAREE_Msk     (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTCLR_COMPARED_Pos     (3UL)                     /*!< COMPARED (Bit 3)                                      */
#define STIMER_STMINTCLR_COMPARED_Msk     (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTCLR_COMPAREC_Pos     (2UL)                     /*!< COMPAREC (Bit 2)                                      */
#define STIMER_STMINTCLR_COMPAREC_Msk     (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTCLR_COMPAREB_Pos     (1UL)                     /*!< COMPAREB (Bit 1)                                      */
#define STIMER_STMINTCLR_COMPAREB_Msk     (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTCLR_COMPAREA_Pos     (0UL)                     /*!< COMPAREA (Bit 0)                                      */
#define STIMER_STMINTCLR_COMPAREA_Msk     (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
/* =======================================================  STMINTSET  ======================================================= */
#define STIMER_STMINTSET_CAPTURED_Pos     (12UL)                    /*!< CAPTURED (Bit 12)                                     */
#define STIMER_STMINTSET_CAPTURED_Msk     (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSET_CAPTUREC_Pos     (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
#define STIMER_STMINTSET_CAPTUREC_Msk     (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSET_CAPTUREB_Pos     (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
#define STIMER_STMINTSET_CAPTUREB_Msk     (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSET_CAPTUREA_Pos     (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
#define STIMER_STMINTSET_CAPTUREA_Msk     (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSET_OVERFLOW_Pos     (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
#define STIMER_STMINTSET_OVERFLOW_Msk     (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSET_COMPAREH_Pos     (7UL)                     /*!< COMPAREH (Bit 7)                                      */
#define STIMER_STMINTSET_COMPAREH_Msk     (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSET_COMPAREG_Pos     (6UL)                     /*!< COMPAREG (Bit 6)                                      */
#define STIMER_STMINTSET_COMPAREG_Msk     (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSET_COMPAREF_Pos     (5UL)                     /*!< COMPAREF (Bit 5)                                      */
#define STIMER_STMINTSET_COMPAREF_Msk     (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSET_COMPAREE_Pos     (4UL)                     /*!< COMPAREE (Bit 4)                                      */
#define STIMER_STMINTSET_COMPAREE_Msk     (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSET_COMPARED_Pos     (3UL)                     /*!< COMPARED (Bit 3)                                      */
#define STIMER_STMINTSET_COMPARED_Msk     (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSET_COMPAREC_Pos     (2UL)                     /*!< COMPAREC (Bit 2)                                      */
#define STIMER_STMINTSET_COMPAREC_Msk     (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSET_COMPAREB_Pos     (1UL)                     /*!< COMPAREB (Bit 1)                                      */
#define STIMER_STMINTSET_COMPAREB_Msk     (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
#define STIMER_STMINTSET_COMPAREA_Pos     (0UL)                     /*!< COMPAREA (Bit 0)                                      */
#define STIMER_STMINTSET_COMPAREA_Msk     (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */


/* =========================================================================================================================== */
/* ================                                           TIMER                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
#define TIMER_CTRL_RESET_Pos              (31UL)                    /*!< RESET (Bit 31)                                        */
#define TIMER_CTRL_RESET_Msk              (0x80000000UL)            /*!< RESET (Bitfield-Mask: 0x01)                           */
/* ========================================================  STATUS  ========================================================= */
#define TIMER_STATUS_NTIMERS_Pos          (16UL)                    /*!< NTIMERS (Bit 16)                                      */
#define TIMER_STATUS_NTIMERS_Msk          (0x1f0000UL)              /*!< NTIMERS (Bitfield-Mask: 0x1f)                         */
#define TIMER_STATUS_ACTIVE_Pos           (0UL)                     /*!< ACTIVE (Bit 0)                                        */
#define TIMER_STATUS_ACTIVE_Msk           (0xffffUL)                /*!< ACTIVE (Bitfield-Mask: 0xffff)                        */
/* ========================================================  GLOBEN  ========================================================= */
#define TIMER_GLOBEN_ADCEN_Pos            (31UL)                    /*!< ADCEN (Bit 31)                                        */
#define TIMER_GLOBEN_ADCEN_Msk            (0x80000000UL)            /*!< ADCEN (Bitfield-Mask: 0x01)                           */
#define TIMER_GLOBEN_AUDADCEN_Pos         (30UL)                    /*!< AUDADCEN (Bit 30)                                     */
#define TIMER_GLOBEN_AUDADCEN_Msk         (0x40000000UL)            /*!< AUDADCEN (Bitfield-Mask: 0x01)                        */
#define TIMER_GLOBEN_ENABLEALLINPUTS_Pos  (29UL)                    /*!< ENABLEALLINPUTS (Bit 29)                              */
#define TIMER_GLOBEN_ENABLEALLINPUTS_Msk  (0x20000000UL)            /*!< ENABLEALLINPUTS (Bitfield-Mask: 0x01)                 */
#define TIMER_GLOBEN_ENB15_Pos            (15UL)                    /*!< ENB15 (Bit 15)                                        */
#define TIMER_GLOBEN_ENB15_Msk            (0x8000UL)                /*!< ENB15 (Bitfield-Mask: 0x01)                           */
#define TIMER_GLOBEN_ENB14_Pos            (14UL)                    /*!< ENB14 (Bit 14)                                        */
#define TIMER_GLOBEN_ENB14_Msk            (0x4000UL)                /*!< ENB14 (Bitfield-Mask: 0x01)                           */
#define TIMER_GLOBEN_ENB13_Pos            (13UL)                    /*!< ENB13 (Bit 13)                                        */
#define TIMER_GLOBEN_ENB13_Msk            (0x2000UL)                /*!< ENB13 (Bitfield-Mask: 0x01)                           */
#define TIMER_GLOBEN_ENB12_Pos            (12UL)                    /*!< ENB12 (Bit 12)                                        */
#define TIMER_GLOBEN_ENB12_Msk            (0x1000UL)                /*!< ENB12 (Bitfield-Mask: 0x01)                           */
#define TIMER_GLOBEN_ENB11_Pos            (11UL)                    /*!< ENB11 (Bit 11)                                        */
#define TIMER_GLOBEN_ENB11_Msk            (0x800UL)                 /*!< ENB11 (Bitfield-Mask: 0x01)                           */
#define TIMER_GLOBEN_ENB10_Pos            (10UL)                    /*!< ENB10 (Bit 10)                                        */
#define TIMER_GLOBEN_ENB10_Msk            (0x400UL)                 /*!< ENB10 (Bitfield-Mask: 0x01)                           */
#define TIMER_GLOBEN_ENB9_Pos             (9UL)                     /*!< ENB9 (Bit 9)                                          */
#define TIMER_GLOBEN_ENB9_Msk             (0x200UL)                 /*!< ENB9 (Bitfield-Mask: 0x01)                            */
#define TIMER_GLOBEN_ENB8_Pos             (8UL)                     /*!< ENB8 (Bit 8)                                          */
#define TIMER_GLOBEN_ENB8_Msk             (0x100UL)                 /*!< ENB8 (Bitfield-Mask: 0x01)                            */
#define TIMER_GLOBEN_ENB7_Pos             (7UL)                     /*!< ENB7 (Bit 7)                                          */
#define TIMER_GLOBEN_ENB7_Msk             (0x80UL)                  /*!< ENB7 (Bitfield-Mask: 0x01)                            */
#define TIMER_GLOBEN_ENB6_Pos             (6UL)                     /*!< ENB6 (Bit 6)                                          */
#define TIMER_GLOBEN_ENB6_Msk             (0x40UL)                  /*!< ENB6 (Bitfield-Mask: 0x01)                            */
#define TIMER_GLOBEN_ENB5_Pos             (5UL)                     /*!< ENB5 (Bit 5)                                          */
#define TIMER_GLOBEN_ENB5_Msk             (0x20UL)                  /*!< ENB5 (Bitfield-Mask: 0x01)                            */
#define TIMER_GLOBEN_ENB4_Pos             (4UL)                     /*!< ENB4 (Bit 4)                                          */
#define TIMER_GLOBEN_ENB4_Msk             (0x10UL)                  /*!< ENB4 (Bitfield-Mask: 0x01)                            */
#define TIMER_GLOBEN_ENB3_Pos             (3UL)                     /*!< ENB3 (Bit 3)                                          */
#define TIMER_GLOBEN_ENB3_Msk             (0x8UL)                   /*!< ENB3 (Bitfield-Mask: 0x01)                            */
#define TIMER_GLOBEN_ENB2_Pos             (2UL)                     /*!< ENB2 (Bit 2)                                          */
#define TIMER_GLOBEN_ENB2_Msk             (0x4UL)                   /*!< ENB2 (Bitfield-Mask: 0x01)                            */
#define TIMER_GLOBEN_ENB1_Pos             (1UL)                     /*!< ENB1 (Bit 1)                                          */
#define TIMER_GLOBEN_ENB1_Msk             (0x2UL)                   /*!< ENB1 (Bitfield-Mask: 0x01)                            */
#define TIMER_GLOBEN_ENB0_Pos             (0UL)                     /*!< ENB0 (Bit 0)                                          */
#define TIMER_GLOBEN_ENB0_Msk             (0x1UL)                   /*!< ENB0 (Bitfield-Mask: 0x01)                            */
/* =========================================================  INTEN  ========================================================= */
#define TIMER_INTEN_TMR151INT_Pos         (31UL)                    /*!< TMR151INT (Bit 31)                                    */
#define TIMER_INTEN_TMR151INT_Msk         (0x80000000UL)            /*!< TMR151INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTEN_TMR150INT_Pos         (30UL)                    /*!< TMR150INT (Bit 30)                                    */
#define TIMER_INTEN_TMR150INT_Msk         (0x40000000UL)            /*!< TMR150INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTEN_TMR141INT_Pos         (29UL)                    /*!< TMR141INT (Bit 29)                                    */
#define TIMER_INTEN_TMR141INT_Msk         (0x20000000UL)            /*!< TMR141INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTEN_TMR140INT_Pos         (28UL)                    /*!< TMR140INT (Bit 28)                                    */
#define TIMER_INTEN_TMR140INT_Msk         (0x10000000UL)            /*!< TMR140INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTEN_TMR131INT_Pos         (27UL)                    /*!< TMR131INT (Bit 27)                                    */
#define TIMER_INTEN_TMR131INT_Msk         (0x8000000UL)             /*!< TMR131INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTEN_TMR130INT_Pos         (26UL)                    /*!< TMR130INT (Bit 26)                                    */
#define TIMER_INTEN_TMR130INT_Msk         (0x4000000UL)             /*!< TMR130INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTEN_TMR121INT_Pos         (25UL)                    /*!< TMR121INT (Bit 25)                                    */
#define TIMER_INTEN_TMR121INT_Msk         (0x2000000UL)             /*!< TMR121INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTEN_TMR120INT_Pos         (24UL)                    /*!< TMR120INT (Bit 24)                                    */
#define TIMER_INTEN_TMR120INT_Msk         (0x1000000UL)             /*!< TMR120INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTEN_TMR111INT_Pos         (23UL)                    /*!< TMR111INT (Bit 23)                                    */
#define TIMER_INTEN_TMR111INT_Msk         (0x800000UL)              /*!< TMR111INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTEN_TMR110INT_Pos         (22UL)                    /*!< TMR110INT (Bit 22)                                    */
#define TIMER_INTEN_TMR110INT_Msk         (0x400000UL)              /*!< TMR110INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTEN_TMR101INT_Pos         (21UL)                    /*!< TMR101INT (Bit 21)                                    */
#define TIMER_INTEN_TMR101INT_Msk         (0x200000UL)              /*!< TMR101INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTEN_TMR100INT_Pos         (20UL)                    /*!< TMR100INT (Bit 20)                                    */
#define TIMER_INTEN_TMR100INT_Msk         (0x100000UL)              /*!< TMR100INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTEN_TMR91INT_Pos          (19UL)                    /*!< TMR91INT (Bit 19)                                     */
#define TIMER_INTEN_TMR91INT_Msk          (0x80000UL)               /*!< TMR91INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR90INT_Pos          (18UL)                    /*!< TMR90INT (Bit 18)                                     */
#define TIMER_INTEN_TMR90INT_Msk          (0x40000UL)               /*!< TMR90INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR81INT_Pos          (17UL)                    /*!< TMR81INT (Bit 17)                                     */
#define TIMER_INTEN_TMR81INT_Msk          (0x20000UL)               /*!< TMR81INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR80INT_Pos          (16UL)                    /*!< TMR80INT (Bit 16)                                     */
#define TIMER_INTEN_TMR80INT_Msk          (0x10000UL)               /*!< TMR80INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR71INT_Pos          (15UL)                    /*!< TMR71INT (Bit 15)                                     */
#define TIMER_INTEN_TMR71INT_Msk          (0x8000UL)                /*!< TMR71INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR70INT_Pos          (14UL)                    /*!< TMR70INT (Bit 14)                                     */
#define TIMER_INTEN_TMR70INT_Msk          (0x4000UL)                /*!< TMR70INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR61INT_Pos          (13UL)                    /*!< TMR61INT (Bit 13)                                     */
#define TIMER_INTEN_TMR61INT_Msk          (0x2000UL)                /*!< TMR61INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR60INT_Pos          (12UL)                    /*!< TMR60INT (Bit 12)                                     */
#define TIMER_INTEN_TMR60INT_Msk          (0x1000UL)                /*!< TMR60INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR51INT_Pos          (11UL)                    /*!< TMR51INT (Bit 11)                                     */
#define TIMER_INTEN_TMR51INT_Msk          (0x800UL)                 /*!< TMR51INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR50INT_Pos          (10UL)                    /*!< TMR50INT (Bit 10)                                     */
#define TIMER_INTEN_TMR50INT_Msk          (0x400UL)                 /*!< TMR50INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR41INT_Pos          (9UL)                     /*!< TMR41INT (Bit 9)                                      */
#define TIMER_INTEN_TMR41INT_Msk          (0x200UL)                 /*!< TMR41INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR40INT_Pos          (8UL)                     /*!< TMR40INT (Bit 8)                                      */
#define TIMER_INTEN_TMR40INT_Msk          (0x100UL)                 /*!< TMR40INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR31INT_Pos          (7UL)                     /*!< TMR31INT (Bit 7)                                      */
#define TIMER_INTEN_TMR31INT_Msk          (0x80UL)                  /*!< TMR31INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR30INT_Pos          (6UL)                     /*!< TMR30INT (Bit 6)                                      */
#define TIMER_INTEN_TMR30INT_Msk          (0x40UL)                  /*!< TMR30INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR21INT_Pos          (5UL)                     /*!< TMR21INT (Bit 5)                                      */
#define TIMER_INTEN_TMR21INT_Msk          (0x20UL)                  /*!< TMR21INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR20INT_Pos          (4UL)                     /*!< TMR20INT (Bit 4)                                      */
#define TIMER_INTEN_TMR20INT_Msk          (0x10UL)                  /*!< TMR20INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR11INT_Pos          (3UL)                     /*!< TMR11INT (Bit 3)                                      */
#define TIMER_INTEN_TMR11INT_Msk          (0x8UL)                   /*!< TMR11INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR10INT_Pos          (2UL)                     /*!< TMR10INT (Bit 2)                                      */
#define TIMER_INTEN_TMR10INT_Msk          (0x4UL)                   /*!< TMR10INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR01INT_Pos          (1UL)                     /*!< TMR01INT (Bit 1)                                      */
#define TIMER_INTEN_TMR01INT_Msk          (0x2UL)                   /*!< TMR01INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTEN_TMR00INT_Pos          (0UL)                     /*!< TMR00INT (Bit 0)                                      */
#define TIMER_INTEN_TMR00INT_Msk          (0x1UL)                   /*!< TMR00INT (Bitfield-Mask: 0x01)                        */
/* ========================================================  INTSTAT  ======================================================== */
#define TIMER_INTSTAT_TMR151INT_Pos       (31UL)                    /*!< TMR151INT (Bit 31)                                    */
#define TIMER_INTSTAT_TMR151INT_Msk       (0x80000000UL)            /*!< TMR151INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSTAT_TMR150INT_Pos       (30UL)                    /*!< TMR150INT (Bit 30)                                    */
#define TIMER_INTSTAT_TMR150INT_Msk       (0x40000000UL)            /*!< TMR150INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSTAT_TMR141INT_Pos       (29UL)                    /*!< TMR141INT (Bit 29)                                    */
#define TIMER_INTSTAT_TMR141INT_Msk       (0x20000000UL)            /*!< TMR141INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSTAT_TMR140INT_Pos       (28UL)                    /*!< TMR140INT (Bit 28)                                    */
#define TIMER_INTSTAT_TMR140INT_Msk       (0x10000000UL)            /*!< TMR140INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSTAT_TMR131INT_Pos       (27UL)                    /*!< TMR131INT (Bit 27)                                    */
#define TIMER_INTSTAT_TMR131INT_Msk       (0x8000000UL)             /*!< TMR131INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSTAT_TMR130INT_Pos       (26UL)                    /*!< TMR130INT (Bit 26)                                    */
#define TIMER_INTSTAT_TMR130INT_Msk       (0x4000000UL)             /*!< TMR130INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSTAT_TMR121INT_Pos       (25UL)                    /*!< TMR121INT (Bit 25)                                    */
#define TIMER_INTSTAT_TMR121INT_Msk       (0x2000000UL)             /*!< TMR121INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSTAT_TMR120INT_Pos       (24UL)                    /*!< TMR120INT (Bit 24)                                    */
#define TIMER_INTSTAT_TMR120INT_Msk       (0x1000000UL)             /*!< TMR120INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSTAT_TMR111INT_Pos       (23UL)                    /*!< TMR111INT (Bit 23)                                    */
#define TIMER_INTSTAT_TMR111INT_Msk       (0x800000UL)              /*!< TMR111INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSTAT_TMR110INT_Pos       (22UL)                    /*!< TMR110INT (Bit 22)                                    */
#define TIMER_INTSTAT_TMR110INT_Msk       (0x400000UL)              /*!< TMR110INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSTAT_TMR101INT_Pos       (21UL)                    /*!< TMR101INT (Bit 21)                                    */
#define TIMER_INTSTAT_TMR101INT_Msk       (0x200000UL)              /*!< TMR101INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSTAT_TMR100INT_Pos       (20UL)                    /*!< TMR100INT (Bit 20)                                    */
#define TIMER_INTSTAT_TMR100INT_Msk       (0x100000UL)              /*!< TMR100INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSTAT_TMR91INT_Pos        (19UL)                    /*!< TMR91INT (Bit 19)                                     */
#define TIMER_INTSTAT_TMR91INT_Msk        (0x80000UL)               /*!< TMR91INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR90INT_Pos        (18UL)                    /*!< TMR90INT (Bit 18)                                     */
#define TIMER_INTSTAT_TMR90INT_Msk        (0x40000UL)               /*!< TMR90INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR81INT_Pos        (17UL)                    /*!< TMR81INT (Bit 17)                                     */
#define TIMER_INTSTAT_TMR81INT_Msk        (0x20000UL)               /*!< TMR81INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR80INT_Pos        (16UL)                    /*!< TMR80INT (Bit 16)                                     */
#define TIMER_INTSTAT_TMR80INT_Msk        (0x10000UL)               /*!< TMR80INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR71INT_Pos        (15UL)                    /*!< TMR71INT (Bit 15)                                     */
#define TIMER_INTSTAT_TMR71INT_Msk        (0x8000UL)                /*!< TMR71INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR70INT_Pos        (14UL)                    /*!< TMR70INT (Bit 14)                                     */
#define TIMER_INTSTAT_TMR70INT_Msk        (0x4000UL)                /*!< TMR70INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR61INT_Pos        (13UL)                    /*!< TMR61INT (Bit 13)                                     */
#define TIMER_INTSTAT_TMR61INT_Msk        (0x2000UL)                /*!< TMR61INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR60INT_Pos        (12UL)                    /*!< TMR60INT (Bit 12)                                     */
#define TIMER_INTSTAT_TMR60INT_Msk        (0x1000UL)                /*!< TMR60INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR51INT_Pos        (11UL)                    /*!< TMR51INT (Bit 11)                                     */
#define TIMER_INTSTAT_TMR51INT_Msk        (0x800UL)                 /*!< TMR51INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR50INT_Pos        (10UL)                    /*!< TMR50INT (Bit 10)                                     */
#define TIMER_INTSTAT_TMR50INT_Msk        (0x400UL)                 /*!< TMR50INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR41INT_Pos        (9UL)                     /*!< TMR41INT (Bit 9)                                      */
#define TIMER_INTSTAT_TMR41INT_Msk        (0x200UL)                 /*!< TMR41INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR40INT_Pos        (8UL)                     /*!< TMR40INT (Bit 8)                                      */
#define TIMER_INTSTAT_TMR40INT_Msk        (0x100UL)                 /*!< TMR40INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR31INT_Pos        (7UL)                     /*!< TMR31INT (Bit 7)                                      */
#define TIMER_INTSTAT_TMR31INT_Msk        (0x80UL)                  /*!< TMR31INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR30INT_Pos        (6UL)                     /*!< TMR30INT (Bit 6)                                      */
#define TIMER_INTSTAT_TMR30INT_Msk        (0x40UL)                  /*!< TMR30INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR21INT_Pos        (5UL)                     /*!< TMR21INT (Bit 5)                                      */
#define TIMER_INTSTAT_TMR21INT_Msk        (0x20UL)                  /*!< TMR21INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR20INT_Pos        (4UL)                     /*!< TMR20INT (Bit 4)                                      */
#define TIMER_INTSTAT_TMR20INT_Msk        (0x10UL)                  /*!< TMR20INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR11INT_Pos        (3UL)                     /*!< TMR11INT (Bit 3)                                      */
#define TIMER_INTSTAT_TMR11INT_Msk        (0x8UL)                   /*!< TMR11INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR10INT_Pos        (2UL)                     /*!< TMR10INT (Bit 2)                                      */
#define TIMER_INTSTAT_TMR10INT_Msk        (0x4UL)                   /*!< TMR10INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR01INT_Pos        (1UL)                     /*!< TMR01INT (Bit 1)                                      */
#define TIMER_INTSTAT_TMR01INT_Msk        (0x2UL)                   /*!< TMR01INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSTAT_TMR00INT_Pos        (0UL)                     /*!< TMR00INT (Bit 0)                                      */
#define TIMER_INTSTAT_TMR00INT_Msk        (0x1UL)                   /*!< TMR00INT (Bitfield-Mask: 0x01)                        */
/* ========================================================  INTCLR  ========================================================= */
#define TIMER_INTCLR_TMR151INT_Pos        (31UL)                    /*!< TMR151INT (Bit 31)                                    */
#define TIMER_INTCLR_TMR151INT_Msk        (0x80000000UL)            /*!< TMR151INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTCLR_TMR150INT_Pos        (30UL)                    /*!< TMR150INT (Bit 30)                                    */
#define TIMER_INTCLR_TMR150INT_Msk        (0x40000000UL)            /*!< TMR150INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTCLR_TMR141INT_Pos        (29UL)                    /*!< TMR141INT (Bit 29)                                    */
#define TIMER_INTCLR_TMR141INT_Msk        (0x20000000UL)            /*!< TMR141INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTCLR_TMR140INT_Pos        (28UL)                    /*!< TMR140INT (Bit 28)                                    */
#define TIMER_INTCLR_TMR140INT_Msk        (0x10000000UL)            /*!< TMR140INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTCLR_TMR131INT_Pos        (27UL)                    /*!< TMR131INT (Bit 27)                                    */
#define TIMER_INTCLR_TMR131INT_Msk        (0x8000000UL)             /*!< TMR131INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTCLR_TMR130INT_Pos        (26UL)                    /*!< TMR130INT (Bit 26)                                    */
#define TIMER_INTCLR_TMR130INT_Msk        (0x4000000UL)             /*!< TMR130INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTCLR_TMR121INT_Pos        (25UL)                    /*!< TMR121INT (Bit 25)                                    */
#define TIMER_INTCLR_TMR121INT_Msk        (0x2000000UL)             /*!< TMR121INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTCLR_TMR120INT_Pos        (24UL)                    /*!< TMR120INT (Bit 24)                                    */
#define TIMER_INTCLR_TMR120INT_Msk        (0x1000000UL)             /*!< TMR120INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTCLR_TMR111INT_Pos        (23UL)                    /*!< TMR111INT (Bit 23)                                    */
#define TIMER_INTCLR_TMR111INT_Msk        (0x800000UL)              /*!< TMR111INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTCLR_TMR110INT_Pos        (22UL)                    /*!< TMR110INT (Bit 22)                                    */
#define TIMER_INTCLR_TMR110INT_Msk        (0x400000UL)              /*!< TMR110INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTCLR_TMR101INT_Pos        (21UL)                    /*!< TMR101INT (Bit 21)                                    */
#define TIMER_INTCLR_TMR101INT_Msk        (0x200000UL)              /*!< TMR101INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTCLR_TMR100INT_Pos        (20UL)                    /*!< TMR100INT (Bit 20)                                    */
#define TIMER_INTCLR_TMR100INT_Msk        (0x100000UL)              /*!< TMR100INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTCLR_TMR91INT_Pos         (19UL)                    /*!< TMR91INT (Bit 19)                                     */
#define TIMER_INTCLR_TMR91INT_Msk         (0x80000UL)               /*!< TMR91INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR90INT_Pos         (18UL)                    /*!< TMR90INT (Bit 18)                                     */
#define TIMER_INTCLR_TMR90INT_Msk         (0x40000UL)               /*!< TMR90INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR81INT_Pos         (17UL)                    /*!< TMR81INT (Bit 17)                                     */
#define TIMER_INTCLR_TMR81INT_Msk         (0x20000UL)               /*!< TMR81INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR80INT_Pos         (16UL)                    /*!< TMR80INT (Bit 16)                                     */
#define TIMER_INTCLR_TMR80INT_Msk         (0x10000UL)               /*!< TMR80INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR71INT_Pos         (15UL)                    /*!< TMR71INT (Bit 15)                                     */
#define TIMER_INTCLR_TMR71INT_Msk         (0x8000UL)                /*!< TMR71INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR70INT_Pos         (14UL)                    /*!< TMR70INT (Bit 14)                                     */
#define TIMER_INTCLR_TMR70INT_Msk         (0x4000UL)                /*!< TMR70INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR61INT_Pos         (13UL)                    /*!< TMR61INT (Bit 13)                                     */
#define TIMER_INTCLR_TMR61INT_Msk         (0x2000UL)                /*!< TMR61INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR60INT_Pos         (12UL)                    /*!< TMR60INT (Bit 12)                                     */
#define TIMER_INTCLR_TMR60INT_Msk         (0x1000UL)                /*!< TMR60INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR51INT_Pos         (11UL)                    /*!< TMR51INT (Bit 11)                                     */
#define TIMER_INTCLR_TMR51INT_Msk         (0x800UL)                 /*!< TMR51INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR50INT_Pos         (10UL)                    /*!< TMR50INT (Bit 10)                                     */
#define TIMER_INTCLR_TMR50INT_Msk         (0x400UL)                 /*!< TMR50INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR41INT_Pos         (9UL)                     /*!< TMR41INT (Bit 9)                                      */
#define TIMER_INTCLR_TMR41INT_Msk         (0x200UL)                 /*!< TMR41INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR40INT_Pos         (8UL)                     /*!< TMR40INT (Bit 8)                                      */
#define TIMER_INTCLR_TMR40INT_Msk         (0x100UL)                 /*!< TMR40INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR31INT_Pos         (7UL)                     /*!< TMR31INT (Bit 7)                                      */
#define TIMER_INTCLR_TMR31INT_Msk         (0x80UL)                  /*!< TMR31INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR30INT_Pos         (6UL)                     /*!< TMR30INT (Bit 6)                                      */
#define TIMER_INTCLR_TMR30INT_Msk         (0x40UL)                  /*!< TMR30INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR21INT_Pos         (5UL)                     /*!< TMR21INT (Bit 5)                                      */
#define TIMER_INTCLR_TMR21INT_Msk         (0x20UL)                  /*!< TMR21INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR20INT_Pos         (4UL)                     /*!< TMR20INT (Bit 4)                                      */
#define TIMER_INTCLR_TMR20INT_Msk         (0x10UL)                  /*!< TMR20INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR11INT_Pos         (3UL)                     /*!< TMR11INT (Bit 3)                                      */
#define TIMER_INTCLR_TMR11INT_Msk         (0x8UL)                   /*!< TMR11INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR10INT_Pos         (2UL)                     /*!< TMR10INT (Bit 2)                                      */
#define TIMER_INTCLR_TMR10INT_Msk         (0x4UL)                   /*!< TMR10INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR01INT_Pos         (1UL)                     /*!< TMR01INT (Bit 1)                                      */
#define TIMER_INTCLR_TMR01INT_Msk         (0x2UL)                   /*!< TMR01INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTCLR_TMR00INT_Pos         (0UL)                     /*!< TMR00INT (Bit 0)                                      */
#define TIMER_INTCLR_TMR00INT_Msk         (0x1UL)                   /*!< TMR00INT (Bitfield-Mask: 0x01)                        */
/* ========================================================  INTSET  ========================================================= */
#define TIMER_INTSET_TMR151INT_Pos        (31UL)                    /*!< TMR151INT (Bit 31)                                    */
#define TIMER_INTSET_TMR151INT_Msk        (0x80000000UL)            /*!< TMR151INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSET_TMR150INT_Pos        (30UL)                    /*!< TMR150INT (Bit 30)                                    */
#define TIMER_INTSET_TMR150INT_Msk        (0x40000000UL)            /*!< TMR150INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSET_TMR141INT_Pos        (29UL)                    /*!< TMR141INT (Bit 29)                                    */
#define TIMER_INTSET_TMR141INT_Msk        (0x20000000UL)            /*!< TMR141INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSET_TMR140INT_Pos        (28UL)                    /*!< TMR140INT (Bit 28)                                    */
#define TIMER_INTSET_TMR140INT_Msk        (0x10000000UL)            /*!< TMR140INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSET_TMR131INT_Pos        (27UL)                    /*!< TMR131INT (Bit 27)                                    */
#define TIMER_INTSET_TMR131INT_Msk        (0x8000000UL)             /*!< TMR131INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSET_TMR130INT_Pos        (26UL)                    /*!< TMR130INT (Bit 26)                                    */
#define TIMER_INTSET_TMR130INT_Msk        (0x4000000UL)             /*!< TMR130INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSET_TMR121INT_Pos        (25UL)                    /*!< TMR121INT (Bit 25)                                    */
#define TIMER_INTSET_TMR121INT_Msk        (0x2000000UL)             /*!< TMR121INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSET_TMR120INT_Pos        (24UL)                    /*!< TMR120INT (Bit 24)                                    */
#define TIMER_INTSET_TMR120INT_Msk        (0x1000000UL)             /*!< TMR120INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSET_TMR111INT_Pos        (23UL)                    /*!< TMR111INT (Bit 23)                                    */
#define TIMER_INTSET_TMR111INT_Msk        (0x800000UL)              /*!< TMR111INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSET_TMR110INT_Pos        (22UL)                    /*!< TMR110INT (Bit 22)                                    */
#define TIMER_INTSET_TMR110INT_Msk        (0x400000UL)              /*!< TMR110INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSET_TMR101INT_Pos        (21UL)                    /*!< TMR101INT (Bit 21)                                    */
#define TIMER_INTSET_TMR101INT_Msk        (0x200000UL)              /*!< TMR101INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSET_TMR100INT_Pos        (20UL)                    /*!< TMR100INT (Bit 20)                                    */
#define TIMER_INTSET_TMR100INT_Msk        (0x100000UL)              /*!< TMR100INT (Bitfield-Mask: 0x01)                       */
#define TIMER_INTSET_TMR91INT_Pos         (19UL)                    /*!< TMR91INT (Bit 19)                                     */
#define TIMER_INTSET_TMR91INT_Msk         (0x80000UL)               /*!< TMR91INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR90INT_Pos         (18UL)                    /*!< TMR90INT (Bit 18)                                     */
#define TIMER_INTSET_TMR90INT_Msk         (0x40000UL)               /*!< TMR90INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR81INT_Pos         (17UL)                    /*!< TMR81INT (Bit 17)                                     */
#define TIMER_INTSET_TMR81INT_Msk         (0x20000UL)               /*!< TMR81INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR80INT_Pos         (16UL)                    /*!< TMR80INT (Bit 16)                                     */
#define TIMER_INTSET_TMR80INT_Msk         (0x10000UL)               /*!< TMR80INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR71INT_Pos         (15UL)                    /*!< TMR71INT (Bit 15)                                     */
#define TIMER_INTSET_TMR71INT_Msk         (0x8000UL)                /*!< TMR71INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR70INT_Pos         (14UL)                    /*!< TMR70INT (Bit 14)                                     */
#define TIMER_INTSET_TMR70INT_Msk         (0x4000UL)                /*!< TMR70INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR61INT_Pos         (13UL)                    /*!< TMR61INT (Bit 13)                                     */
#define TIMER_INTSET_TMR61INT_Msk         (0x2000UL)                /*!< TMR61INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR60INT_Pos         (12UL)                    /*!< TMR60INT (Bit 12)                                     */
#define TIMER_INTSET_TMR60INT_Msk         (0x1000UL)                /*!< TMR60INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR51INT_Pos         (11UL)                    /*!< TMR51INT (Bit 11)                                     */
#define TIMER_INTSET_TMR51INT_Msk         (0x800UL)                 /*!< TMR51INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR50INT_Pos         (10UL)                    /*!< TMR50INT (Bit 10)                                     */
#define TIMER_INTSET_TMR50INT_Msk         (0x400UL)                 /*!< TMR50INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR41INT_Pos         (9UL)                     /*!< TMR41INT (Bit 9)                                      */
#define TIMER_INTSET_TMR41INT_Msk         (0x200UL)                 /*!< TMR41INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR40INT_Pos         (8UL)                     /*!< TMR40INT (Bit 8)                                      */
#define TIMER_INTSET_TMR40INT_Msk         (0x100UL)                 /*!< TMR40INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR31INT_Pos         (7UL)                     /*!< TMR31INT (Bit 7)                                      */
#define TIMER_INTSET_TMR31INT_Msk         (0x80UL)                  /*!< TMR31INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR30INT_Pos         (6UL)                     /*!< TMR30INT (Bit 6)                                      */
#define TIMER_INTSET_TMR30INT_Msk         (0x40UL)                  /*!< TMR30INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR21INT_Pos         (5UL)                     /*!< TMR21INT (Bit 5)                                      */
#define TIMER_INTSET_TMR21INT_Msk         (0x20UL)                  /*!< TMR21INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR20INT_Pos         (4UL)                     /*!< TMR20INT (Bit 4)                                      */
#define TIMER_INTSET_TMR20INT_Msk         (0x10UL)                  /*!< TMR20INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR11INT_Pos         (3UL)                     /*!< TMR11INT (Bit 3)                                      */
#define TIMER_INTSET_TMR11INT_Msk         (0x8UL)                   /*!< TMR11INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR10INT_Pos         (2UL)                     /*!< TMR10INT (Bit 2)                                      */
#define TIMER_INTSET_TMR10INT_Msk         (0x4UL)                   /*!< TMR10INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR01INT_Pos         (1UL)                     /*!< TMR01INT (Bit 1)                                      */
#define TIMER_INTSET_TMR01INT_Msk         (0x2UL)                   /*!< TMR01INT (Bitfield-Mask: 0x01)                        */
#define TIMER_INTSET_TMR00INT_Pos         (0UL)                     /*!< TMR00INT (Bit 0)                                      */
#define TIMER_INTSET_TMR00INT_Msk         (0x1UL)                   /*!< TMR00INT (Bitfield-Mask: 0x01)                        */
/* ========================================================  OUTCFG0  ======================================================== */
#define TIMER_OUTCFG0_OUTCFG3_Pos         (24UL)                    /*!< OUTCFG3 (Bit 24)                                      */
#define TIMER_OUTCFG0_OUTCFG3_Msk         (0x3f000000UL)            /*!< OUTCFG3 (Bitfield-Mask: 0x3f)                         */
#define TIMER_OUTCFG0_OUTCFG2_Pos         (16UL)                    /*!< OUTCFG2 (Bit 16)                                      */
#define TIMER_OUTCFG0_OUTCFG2_Msk         (0x3f0000UL)              /*!< OUTCFG2 (Bitfield-Mask: 0x3f)                         */
#define TIMER_OUTCFG0_OUTCFG1_Pos         (8UL)                     /*!< OUTCFG1 (Bit 8)                                       */
#define TIMER_OUTCFG0_OUTCFG1_Msk         (0x3f00UL)                /*!< OUTCFG1 (Bitfield-Mask: 0x3f)                         */
#define TIMER_OUTCFG0_OUTCFG0_Pos         (0UL)                     /*!< OUTCFG0 (Bit 0)                                       */
#define TIMER_OUTCFG0_OUTCFG0_Msk         (0x3fUL)                  /*!< OUTCFG0 (Bitfield-Mask: 0x3f)                         */
/* ========================================================  OUTCFG1  ======================================================== */
#define TIMER_OUTCFG1_OUTCFG7_Pos         (24UL)                    /*!< OUTCFG7 (Bit 24)                                      */
#define TIMER_OUTCFG1_OUTCFG7_Msk         (0x3f000000UL)            /*!< OUTCFG7 (Bitfield-Mask: 0x3f)                         */
#define TIMER_OUTCFG1_OUTCFG6_Pos         (16UL)                    /*!< OUTCFG6 (Bit 16)                                      */
#define TIMER_OUTCFG1_OUTCFG6_Msk         (0x3f0000UL)              /*!< OUTCFG6 (Bitfield-Mask: 0x3f)                         */
#define TIMER_OUTCFG1_OUTCFG5_Pos         (8UL)                     /*!< OUTCFG5 (Bit 8)                                       */
#define TIMER_OUTCFG1_OUTCFG5_Msk         (0x3f00UL)                /*!< OUTCFG5 (Bitfield-Mask: 0x3f)                         */
#define TIMER_OUTCFG1_OUTCFG4_Pos         (0UL)                     /*!< OUTCFG4 (Bit 0)                                       */
#define TIMER_OUTCFG1_OUTCFG4_Msk         (0x3fUL)                  /*!< OUTCFG4 (Bitfield-Mask: 0x3f)                         */
/* ========================================================  OUTCFG2  ======================================================== */
#define TIMER_OUTCFG2_OUTCFG11_Pos        (24UL)                    /*!< OUTCFG11 (Bit 24)                                     */
#define TIMER_OUTCFG2_OUTCFG11_Msk        (0x3f000000UL)            /*!< OUTCFG11 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG2_OUTCFG10_Pos        (16UL)                    /*!< OUTCFG10 (Bit 16)                                     */
#define TIMER_OUTCFG2_OUTCFG10_Msk        (0x3f0000UL)              /*!< OUTCFG10 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG2_OUTCFG9_Pos         (8UL)                     /*!< OUTCFG9 (Bit 8)                                       */
#define TIMER_OUTCFG2_OUTCFG9_Msk         (0x3f00UL)                /*!< OUTCFG9 (Bitfield-Mask: 0x3f)                         */
#define TIMER_OUTCFG2_OUTCFG8_Pos         (0UL)                     /*!< OUTCFG8 (Bit 0)                                       */
#define TIMER_OUTCFG2_OUTCFG8_Msk         (0x3fUL)                  /*!< OUTCFG8 (Bitfield-Mask: 0x3f)                         */
/* ========================================================  OUTCFG3  ======================================================== */
#define TIMER_OUTCFG3_OUTCFG15_Pos        (24UL)                    /*!< OUTCFG15 (Bit 24)                                     */
#define TIMER_OUTCFG3_OUTCFG15_Msk        (0x3f000000UL)            /*!< OUTCFG15 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG3_OUTCFG14_Pos        (16UL)                    /*!< OUTCFG14 (Bit 16)                                     */
#define TIMER_OUTCFG3_OUTCFG14_Msk        (0x3f0000UL)              /*!< OUTCFG14 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG3_OUTCFG13_Pos        (8UL)                     /*!< OUTCFG13 (Bit 8)                                      */
#define TIMER_OUTCFG3_OUTCFG13_Msk        (0x3f00UL)                /*!< OUTCFG13 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG3_OUTCFG12_Pos        (0UL)                     /*!< OUTCFG12 (Bit 0)                                      */
#define TIMER_OUTCFG3_OUTCFG12_Msk        (0x3fUL)                  /*!< OUTCFG12 (Bitfield-Mask: 0x3f)                        */
/* ========================================================  OUTCFG4  ======================================================== */
#define TIMER_OUTCFG4_OUTCFG19_Pos        (24UL)                    /*!< OUTCFG19 (Bit 24)                                     */
#define TIMER_OUTCFG4_OUTCFG19_Msk        (0x3f000000UL)            /*!< OUTCFG19 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG4_OUTCFG18_Pos        (16UL)                    /*!< OUTCFG18 (Bit 16)                                     */
#define TIMER_OUTCFG4_OUTCFG18_Msk        (0x3f0000UL)              /*!< OUTCFG18 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG4_OUTCFG17_Pos        (8UL)                     /*!< OUTCFG17 (Bit 8)                                      */
#define TIMER_OUTCFG4_OUTCFG17_Msk        (0x3f00UL)                /*!< OUTCFG17 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG4_OUTCFG16_Pos        (0UL)                     /*!< OUTCFG16 (Bit 0)                                      */
#define TIMER_OUTCFG4_OUTCFG16_Msk        (0x3fUL)                  /*!< OUTCFG16 (Bitfield-Mask: 0x3f)                        */
/* ========================================================  OUTCFG5  ======================================================== */
#define TIMER_OUTCFG5_OUTCFG23_Pos        (24UL)                    /*!< OUTCFG23 (Bit 24)                                     */
#define TIMER_OUTCFG5_OUTCFG23_Msk        (0x3f000000UL)            /*!< OUTCFG23 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG5_OUTCFG22_Pos        (16UL)                    /*!< OUTCFG22 (Bit 16)                                     */
#define TIMER_OUTCFG5_OUTCFG22_Msk        (0x3f0000UL)              /*!< OUTCFG22 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG5_OUTCFG21_Pos        (8UL)                     /*!< OUTCFG21 (Bit 8)                                      */
#define TIMER_OUTCFG5_OUTCFG21_Msk        (0x3f00UL)                /*!< OUTCFG21 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG5_OUTCFG20_Pos        (0UL)                     /*!< OUTCFG20 (Bit 0)                                      */
#define TIMER_OUTCFG5_OUTCFG20_Msk        (0x3fUL)                  /*!< OUTCFG20 (Bitfield-Mask: 0x3f)                        */
/* ========================================================  OUTCFG6  ======================================================== */
#define TIMER_OUTCFG6_OUTCFG27_Pos        (24UL)                    /*!< OUTCFG27 (Bit 24)                                     */
#define TIMER_OUTCFG6_OUTCFG27_Msk        (0x3f000000UL)            /*!< OUTCFG27 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG6_OUTCFG26_Pos        (16UL)                    /*!< OUTCFG26 (Bit 16)                                     */
#define TIMER_OUTCFG6_OUTCFG26_Msk        (0x3f0000UL)              /*!< OUTCFG26 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG6_OUTCFG25_Pos        (8UL)                     /*!< OUTCFG25 (Bit 8)                                      */
#define TIMER_OUTCFG6_OUTCFG25_Msk        (0x3f00UL)                /*!< OUTCFG25 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG6_OUTCFG24_Pos        (0UL)                     /*!< OUTCFG24 (Bit 0)                                      */
#define TIMER_OUTCFG6_OUTCFG24_Msk        (0x3fUL)                  /*!< OUTCFG24 (Bitfield-Mask: 0x3f)                        */
/* ========================================================  OUTCFG7  ======================================================== */
#define TIMER_OUTCFG7_OUTCFG31_Pos        (24UL)                    /*!< OUTCFG31 (Bit 24)                                     */
#define TIMER_OUTCFG7_OUTCFG31_Msk        (0x3f000000UL)            /*!< OUTCFG31 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG7_OUTCFG30_Pos        (16UL)                    /*!< OUTCFG30 (Bit 16)                                     */
#define TIMER_OUTCFG7_OUTCFG30_Msk        (0x3f0000UL)              /*!< OUTCFG30 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG7_OUTCFG29_Pos        (8UL)                     /*!< OUTCFG29 (Bit 8)                                      */
#define TIMER_OUTCFG7_OUTCFG29_Msk        (0x3f00UL)                /*!< OUTCFG29 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG7_OUTCFG28_Pos        (0UL)                     /*!< OUTCFG28 (Bit 0)                                      */
#define TIMER_OUTCFG7_OUTCFG28_Msk        (0x3fUL)                  /*!< OUTCFG28 (Bitfield-Mask: 0x3f)                        */
/* ========================================================  OUTCFG8  ======================================================== */
#define TIMER_OUTCFG8_OUTCFG35_Pos        (24UL)                    /*!< OUTCFG35 (Bit 24)                                     */
#define TIMER_OUTCFG8_OUTCFG35_Msk        (0x3f000000UL)            /*!< OUTCFG35 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG8_OUTCFG34_Pos        (16UL)                    /*!< OUTCFG34 (Bit 16)                                     */
#define TIMER_OUTCFG8_OUTCFG34_Msk        (0x3f0000UL)              /*!< OUTCFG34 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG8_OUTCFG33_Pos        (8UL)                     /*!< OUTCFG33 (Bit 8)                                      */
#define TIMER_OUTCFG8_OUTCFG33_Msk        (0x3f00UL)                /*!< OUTCFG33 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG8_OUTCFG32_Pos        (0UL)                     /*!< OUTCFG32 (Bit 0)                                      */
#define TIMER_OUTCFG8_OUTCFG32_Msk        (0x3fUL)                  /*!< OUTCFG32 (Bitfield-Mask: 0x3f)                        */
/* ========================================================  OUTCFG9  ======================================================== */
#define TIMER_OUTCFG9_OUTCFG39_Pos        (24UL)                    /*!< OUTCFG39 (Bit 24)                                     */
#define TIMER_OUTCFG9_OUTCFG39_Msk        (0x3f000000UL)            /*!< OUTCFG39 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG9_OUTCFG38_Pos        (16UL)                    /*!< OUTCFG38 (Bit 16)                                     */
#define TIMER_OUTCFG9_OUTCFG38_Msk        (0x3f0000UL)              /*!< OUTCFG38 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG9_OUTCFG37_Pos        (8UL)                     /*!< OUTCFG37 (Bit 8)                                      */
#define TIMER_OUTCFG9_OUTCFG37_Msk        (0x3f00UL)                /*!< OUTCFG37 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG9_OUTCFG36_Pos        (0UL)                     /*!< OUTCFG36 (Bit 0)                                      */
#define TIMER_OUTCFG9_OUTCFG36_Msk        (0x3fUL)                  /*!< OUTCFG36 (Bitfield-Mask: 0x3f)                        */
/* =======================================================  OUTCFG10  ======================================================== */
#define TIMER_OUTCFG10_OUTCFG43_Pos       (24UL)                    /*!< OUTCFG43 (Bit 24)                                     */
#define TIMER_OUTCFG10_OUTCFG43_Msk       (0x3f000000UL)            /*!< OUTCFG43 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG10_OUTCFG42_Pos       (16UL)                    /*!< OUTCFG42 (Bit 16)                                     */
#define TIMER_OUTCFG10_OUTCFG42_Msk       (0x3f0000UL)              /*!< OUTCFG42 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG10_OUTCFG41_Pos       (8UL)                     /*!< OUTCFG41 (Bit 8)                                      */
#define TIMER_OUTCFG10_OUTCFG41_Msk       (0x3f00UL)                /*!< OUTCFG41 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG10_OUTCFG40_Pos       (0UL)                     /*!< OUTCFG40 (Bit 0)                                      */
#define TIMER_OUTCFG10_OUTCFG40_Msk       (0x3fUL)                  /*!< OUTCFG40 (Bitfield-Mask: 0x3f)                        */
/* =======================================================  OUTCFG11  ======================================================== */
#define TIMER_OUTCFG11_OUTCFG47_Pos       (24UL)                    /*!< OUTCFG47 (Bit 24)                                     */
#define TIMER_OUTCFG11_OUTCFG47_Msk       (0x3f000000UL)            /*!< OUTCFG47 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG11_OUTCFG46_Pos       (16UL)                    /*!< OUTCFG46 (Bit 16)                                     */
#define TIMER_OUTCFG11_OUTCFG46_Msk       (0x3f0000UL)              /*!< OUTCFG46 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG11_OUTCFG45_Pos       (8UL)                     /*!< OUTCFG45 (Bit 8)                                      */
#define TIMER_OUTCFG11_OUTCFG45_Msk       (0x3f00UL)                /*!< OUTCFG45 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG11_OUTCFG44_Pos       (0UL)                     /*!< OUTCFG44 (Bit 0)                                      */
#define TIMER_OUTCFG11_OUTCFG44_Msk       (0x3fUL)                  /*!< OUTCFG44 (Bitfield-Mask: 0x3f)                        */
/* =======================================================  OUTCFG12  ======================================================== */
#define TIMER_OUTCFG12_OUTCFG51_Pos       (24UL)                    /*!< OUTCFG51 (Bit 24)                                     */
#define TIMER_OUTCFG12_OUTCFG51_Msk       (0x3f000000UL)            /*!< OUTCFG51 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG12_OUTCFG50_Pos       (16UL)                    /*!< OUTCFG50 (Bit 16)                                     */
#define TIMER_OUTCFG12_OUTCFG50_Msk       (0x3f0000UL)              /*!< OUTCFG50 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG12_OUTCFG49_Pos       (8UL)                     /*!< OUTCFG49 (Bit 8)                                      */
#define TIMER_OUTCFG12_OUTCFG49_Msk       (0x3f00UL)                /*!< OUTCFG49 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG12_OUTCFG48_Pos       (0UL)                     /*!< OUTCFG48 (Bit 0)                                      */
#define TIMER_OUTCFG12_OUTCFG48_Msk       (0x3fUL)                  /*!< OUTCFG48 (Bitfield-Mask: 0x3f)                        */
/* =======================================================  OUTCFG13  ======================================================== */
#define TIMER_OUTCFG13_OUTCFG55_Pos       (24UL)                    /*!< OUTCFG55 (Bit 24)                                     */
#define TIMER_OUTCFG13_OUTCFG55_Msk       (0x3f000000UL)            /*!< OUTCFG55 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG13_OUTCFG54_Pos       (16UL)                    /*!< OUTCFG54 (Bit 16)                                     */
#define TIMER_OUTCFG13_OUTCFG54_Msk       (0x3f0000UL)              /*!< OUTCFG54 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG13_OUTCFG53_Pos       (8UL)                     /*!< OUTCFG53 (Bit 8)                                      */
#define TIMER_OUTCFG13_OUTCFG53_Msk       (0x3f00UL)                /*!< OUTCFG53 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG13_OUTCFG52_Pos       (0UL)                     /*!< OUTCFG52 (Bit 0)                                      */
#define TIMER_OUTCFG13_OUTCFG52_Msk       (0x3fUL)                  /*!< OUTCFG52 (Bitfield-Mask: 0x3f)                        */
/* =======================================================  OUTCFG14  ======================================================== */
#define TIMER_OUTCFG14_OUTCFG59_Pos       (24UL)                    /*!< OUTCFG59 (Bit 24)                                     */
#define TIMER_OUTCFG14_OUTCFG59_Msk       (0x3f000000UL)            /*!< OUTCFG59 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG14_OUTCFG58_Pos       (16UL)                    /*!< OUTCFG58 (Bit 16)                                     */
#define TIMER_OUTCFG14_OUTCFG58_Msk       (0x3f0000UL)              /*!< OUTCFG58 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG14_OUTCFG57_Pos       (8UL)                     /*!< OUTCFG57 (Bit 8)                                      */
#define TIMER_OUTCFG14_OUTCFG57_Msk       (0x3f00UL)                /*!< OUTCFG57 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG14_OUTCFG56_Pos       (0UL)                     /*!< OUTCFG56 (Bit 0)                                      */
#define TIMER_OUTCFG14_OUTCFG56_Msk       (0x3fUL)                  /*!< OUTCFG56 (Bitfield-Mask: 0x3f)                        */
/* =======================================================  OUTCFG15  ======================================================== */
#define TIMER_OUTCFG15_OUTCFG63_Pos       (24UL)                    /*!< OUTCFG63 (Bit 24)                                     */
#define TIMER_OUTCFG15_OUTCFG63_Msk       (0x3f000000UL)            /*!< OUTCFG63 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG15_OUTCFG62_Pos       (16UL)                    /*!< OUTCFG62 (Bit 16)                                     */
#define TIMER_OUTCFG15_OUTCFG62_Msk       (0x3f0000UL)              /*!< OUTCFG62 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG15_OUTCFG61_Pos       (8UL)                     /*!< OUTCFG61 (Bit 8)                                      */
#define TIMER_OUTCFG15_OUTCFG61_Msk       (0x3f00UL)                /*!< OUTCFG61 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG15_OUTCFG60_Pos       (0UL)                     /*!< OUTCFG60 (Bit 0)                                      */
#define TIMER_OUTCFG15_OUTCFG60_Msk       (0x3fUL)                  /*!< OUTCFG60 (Bitfield-Mask: 0x3f)                        */
/* =======================================================  OUTCFG16  ======================================================== */
#define TIMER_OUTCFG16_OUTCFG67_Pos       (24UL)                    /*!< OUTCFG67 (Bit 24)                                     */
#define TIMER_OUTCFG16_OUTCFG67_Msk       (0x3f000000UL)            /*!< OUTCFG67 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG16_OUTCFG66_Pos       (16UL)                    /*!< OUTCFG66 (Bit 16)                                     */
#define TIMER_OUTCFG16_OUTCFG66_Msk       (0x3f0000UL)              /*!< OUTCFG66 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG16_OUTCFG65_Pos       (8UL)                     /*!< OUTCFG65 (Bit 8)                                      */
#define TIMER_OUTCFG16_OUTCFG65_Msk       (0x3f00UL)                /*!< OUTCFG65 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG16_OUTCFG64_Pos       (0UL)                     /*!< OUTCFG64 (Bit 0)                                      */
#define TIMER_OUTCFG16_OUTCFG64_Msk       (0x3fUL)                  /*!< OUTCFG64 (Bitfield-Mask: 0x3f)                        */
/* =======================================================  OUTCFG17  ======================================================== */
#define TIMER_OUTCFG17_OUTCFG71_Pos       (24UL)                    /*!< OUTCFG71 (Bit 24)                                     */
#define TIMER_OUTCFG17_OUTCFG71_Msk       (0x3f000000UL)            /*!< OUTCFG71 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG17_OUTCFG70_Pos       (16UL)                    /*!< OUTCFG70 (Bit 16)                                     */
#define TIMER_OUTCFG17_OUTCFG70_Msk       (0x3f0000UL)              /*!< OUTCFG70 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG17_OUTCFG69_Pos       (8UL)                     /*!< OUTCFG69 (Bit 8)                                      */
#define TIMER_OUTCFG17_OUTCFG69_Msk       (0x3f00UL)                /*!< OUTCFG69 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG17_OUTCFG68_Pos       (0UL)                     /*!< OUTCFG68 (Bit 0)                                      */
#define TIMER_OUTCFG17_OUTCFG68_Msk       (0x3fUL)                  /*!< OUTCFG68 (Bitfield-Mask: 0x3f)                        */
/* =======================================================  OUTCFG18  ======================================================== */
#define TIMER_OUTCFG18_OUTCFG75_Pos       (24UL)                    /*!< OUTCFG75 (Bit 24)                                     */
#define TIMER_OUTCFG18_OUTCFG75_Msk       (0x3f000000UL)            /*!< OUTCFG75 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG18_OUTCFG74_Pos       (16UL)                    /*!< OUTCFG74 (Bit 16)                                     */
#define TIMER_OUTCFG18_OUTCFG74_Msk       (0x3f0000UL)              /*!< OUTCFG74 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG18_OUTCFG73_Pos       (8UL)                     /*!< OUTCFG73 (Bit 8)                                      */
#define TIMER_OUTCFG18_OUTCFG73_Msk       (0x3f00UL)                /*!< OUTCFG73 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG18_OUTCFG72_Pos       (0UL)                     /*!< OUTCFG72 (Bit 0)                                      */
#define TIMER_OUTCFG18_OUTCFG72_Msk       (0x3fUL)                  /*!< OUTCFG72 (Bitfield-Mask: 0x3f)                        */
/* =======================================================  OUTCFG19  ======================================================== */
#define TIMER_OUTCFG19_OUTCFG79_Pos       (24UL)                    /*!< OUTCFG79 (Bit 24)                                     */
#define TIMER_OUTCFG19_OUTCFG79_Msk       (0x3f000000UL)            /*!< OUTCFG79 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG19_OUTCFG78_Pos       (16UL)                    /*!< OUTCFG78 (Bit 16)                                     */
#define TIMER_OUTCFG19_OUTCFG78_Msk       (0x3f0000UL)              /*!< OUTCFG78 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG19_OUTCFG77_Pos       (8UL)                     /*!< OUTCFG77 (Bit 8)                                      */
#define TIMER_OUTCFG19_OUTCFG77_Msk       (0x3f00UL)                /*!< OUTCFG77 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG19_OUTCFG76_Pos       (0UL)                     /*!< OUTCFG76 (Bit 0)                                      */
#define TIMER_OUTCFG19_OUTCFG76_Msk       (0x3fUL)                  /*!< OUTCFG76 (Bitfield-Mask: 0x3f)                        */
/* =======================================================  OUTCFG20  ======================================================== */
#define TIMER_OUTCFG20_OUTCFG83_Pos       (24UL)                    /*!< OUTCFG83 (Bit 24)                                     */
#define TIMER_OUTCFG20_OUTCFG83_Msk       (0x3f000000UL)            /*!< OUTCFG83 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG20_OUTCFG82_Pos       (16UL)                    /*!< OUTCFG82 (Bit 16)                                     */
#define TIMER_OUTCFG20_OUTCFG82_Msk       (0x3f0000UL)              /*!< OUTCFG82 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG20_OUTCFG81_Pos       (8UL)                     /*!< OUTCFG81 (Bit 8)                                      */
#define TIMER_OUTCFG20_OUTCFG81_Msk       (0x3f00UL)                /*!< OUTCFG81 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG20_OUTCFG80_Pos       (0UL)                     /*!< OUTCFG80 (Bit 0)                                      */
#define TIMER_OUTCFG20_OUTCFG80_Msk       (0x3fUL)                  /*!< OUTCFG80 (Bitfield-Mask: 0x3f)                        */
/* =======================================================  OUTCFG21  ======================================================== */
#define TIMER_OUTCFG21_OUTCFG87_Pos       (24UL)                    /*!< OUTCFG87 (Bit 24)                                     */
#define TIMER_OUTCFG21_OUTCFG87_Msk       (0x3f000000UL)            /*!< OUTCFG87 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG21_OUTCFG86_Pos       (16UL)                    /*!< OUTCFG86 (Bit 16)                                     */
#define TIMER_OUTCFG21_OUTCFG86_Msk       (0x3f0000UL)              /*!< OUTCFG86 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG21_OUTCFG85_Pos       (8UL)                     /*!< OUTCFG85 (Bit 8)                                      */
#define TIMER_OUTCFG21_OUTCFG85_Msk       (0x3f00UL)                /*!< OUTCFG85 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG21_OUTCFG84_Pos       (0UL)                     /*!< OUTCFG84 (Bit 0)                                      */
#define TIMER_OUTCFG21_OUTCFG84_Msk       (0x3fUL)                  /*!< OUTCFG84 (Bitfield-Mask: 0x3f)                        */
/* =======================================================  OUTCFG22  ======================================================== */
#define TIMER_OUTCFG22_OUTCFG91_Pos       (24UL)                    /*!< OUTCFG91 (Bit 24)                                     */
#define TIMER_OUTCFG22_OUTCFG91_Msk       (0x3f000000UL)            /*!< OUTCFG91 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG22_OUTCFG90_Pos       (16UL)                    /*!< OUTCFG90 (Bit 16)                                     */
#define TIMER_OUTCFG22_OUTCFG90_Msk       (0x3f0000UL)              /*!< OUTCFG90 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG22_OUTCFG89_Pos       (8UL)                     /*!< OUTCFG89 (Bit 8)                                      */
#define TIMER_OUTCFG22_OUTCFG89_Msk       (0x3f00UL)                /*!< OUTCFG89 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG22_OUTCFG88_Pos       (0UL)                     /*!< OUTCFG88 (Bit 0)                                      */
#define TIMER_OUTCFG22_OUTCFG88_Msk       (0x3fUL)                  /*!< OUTCFG88 (Bitfield-Mask: 0x3f)                        */
/* =======================================================  OUTCFG23  ======================================================== */
#define TIMER_OUTCFG23_OUTCFG95_Pos       (24UL)                    /*!< OUTCFG95 (Bit 24)                                     */
#define TIMER_OUTCFG23_OUTCFG95_Msk       (0x3f000000UL)            /*!< OUTCFG95 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG23_OUTCFG94_Pos       (16UL)                    /*!< OUTCFG94 (Bit 16)                                     */
#define TIMER_OUTCFG23_OUTCFG94_Msk       (0x3f0000UL)              /*!< OUTCFG94 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG23_OUTCFG93_Pos       (8UL)                     /*!< OUTCFG93 (Bit 8)                                      */
#define TIMER_OUTCFG23_OUTCFG93_Msk       (0x3f00UL)                /*!< OUTCFG93 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG23_OUTCFG92_Pos       (0UL)                     /*!< OUTCFG92 (Bit 0)                                      */
#define TIMER_OUTCFG23_OUTCFG92_Msk       (0x3fUL)                  /*!< OUTCFG92 (Bitfield-Mask: 0x3f)                        */
/* =======================================================  OUTCFG24  ======================================================== */
#define TIMER_OUTCFG24_OUTCFG99_Pos       (24UL)                    /*!< OUTCFG99 (Bit 24)                                     */
#define TIMER_OUTCFG24_OUTCFG99_Msk       (0x3f000000UL)            /*!< OUTCFG99 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG24_OUTCFG98_Pos       (16UL)                    /*!< OUTCFG98 (Bit 16)                                     */
#define TIMER_OUTCFG24_OUTCFG98_Msk       (0x3f0000UL)              /*!< OUTCFG98 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG24_OUTCFG97_Pos       (8UL)                     /*!< OUTCFG97 (Bit 8)                                      */
#define TIMER_OUTCFG24_OUTCFG97_Msk       (0x3f00UL)                /*!< OUTCFG97 (Bitfield-Mask: 0x3f)                        */
#define TIMER_OUTCFG24_OUTCFG96_Pos       (0UL)                     /*!< OUTCFG96 (Bit 0)                                      */
#define TIMER_OUTCFG24_OUTCFG96_Msk       (0x3fUL)                  /*!< OUTCFG96 (Bitfield-Mask: 0x3f)                        */
/* =======================================================  OUTCFG25  ======================================================== */
#define TIMER_OUTCFG25_OUTCFG103_Pos      (24UL)                    /*!< OUTCFG103 (Bit 24)                                    */
#define TIMER_OUTCFG25_OUTCFG103_Msk      (0x3f000000UL)            /*!< OUTCFG103 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG25_OUTCFG102_Pos      (16UL)                    /*!< OUTCFG102 (Bit 16)                                    */
#define TIMER_OUTCFG25_OUTCFG102_Msk      (0x3f0000UL)              /*!< OUTCFG102 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG25_OUTCFG101_Pos      (8UL)                     /*!< OUTCFG101 (Bit 8)                                     */
#define TIMER_OUTCFG25_OUTCFG101_Msk      (0x3f00UL)                /*!< OUTCFG101 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG25_OUTCFG100_Pos      (0UL)                     /*!< OUTCFG100 (Bit 0)                                     */
#define TIMER_OUTCFG25_OUTCFG100_Msk      (0x3fUL)                  /*!< OUTCFG100 (Bitfield-Mask: 0x3f)                       */
/* =======================================================  OUTCFG26  ======================================================== */
#define TIMER_OUTCFG26_OUTCFG107_Pos      (24UL)                    /*!< OUTCFG107 (Bit 24)                                    */
#define TIMER_OUTCFG26_OUTCFG107_Msk      (0x3f000000UL)            /*!< OUTCFG107 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG26_OUTCFG106_Pos      (16UL)                    /*!< OUTCFG106 (Bit 16)                                    */
#define TIMER_OUTCFG26_OUTCFG106_Msk      (0x3f0000UL)              /*!< OUTCFG106 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG26_OUTCFG105_Pos      (8UL)                     /*!< OUTCFG105 (Bit 8)                                     */
#define TIMER_OUTCFG26_OUTCFG105_Msk      (0x3f00UL)                /*!< OUTCFG105 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG26_OUTCFG104_Pos      (0UL)                     /*!< OUTCFG104 (Bit 0)                                     */
#define TIMER_OUTCFG26_OUTCFG104_Msk      (0x3fUL)                  /*!< OUTCFG104 (Bitfield-Mask: 0x3f)                       */
/* =======================================================  OUTCFG27  ======================================================== */
#define TIMER_OUTCFG27_OUTCFG111_Pos      (24UL)                    /*!< OUTCFG111 (Bit 24)                                    */
#define TIMER_OUTCFG27_OUTCFG111_Msk      (0x3f000000UL)            /*!< OUTCFG111 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG27_OUTCFG110_Pos      (16UL)                    /*!< OUTCFG110 (Bit 16)                                    */
#define TIMER_OUTCFG27_OUTCFG110_Msk      (0x3f0000UL)              /*!< OUTCFG110 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG27_OUTCFG109_Pos      (8UL)                     /*!< OUTCFG109 (Bit 8)                                     */
#define TIMER_OUTCFG27_OUTCFG109_Msk      (0x3f00UL)                /*!< OUTCFG109 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG27_OUTCFG108_Pos      (0UL)                     /*!< OUTCFG108 (Bit 0)                                     */
#define TIMER_OUTCFG27_OUTCFG108_Msk      (0x3fUL)                  /*!< OUTCFG108 (Bitfield-Mask: 0x3f)                       */
/* =======================================================  OUTCFG28  ======================================================== */
#define TIMER_OUTCFG28_OUTCFG115_Pos      (24UL)                    /*!< OUTCFG115 (Bit 24)                                    */
#define TIMER_OUTCFG28_OUTCFG115_Msk      (0x3f000000UL)            /*!< OUTCFG115 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG28_OUTCFG114_Pos      (16UL)                    /*!< OUTCFG114 (Bit 16)                                    */
#define TIMER_OUTCFG28_OUTCFG114_Msk      (0x3f0000UL)              /*!< OUTCFG114 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG28_OUTCFG113_Pos      (8UL)                     /*!< OUTCFG113 (Bit 8)                                     */
#define TIMER_OUTCFG28_OUTCFG113_Msk      (0x3f00UL)                /*!< OUTCFG113 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG28_OUTCFG112_Pos      (0UL)                     /*!< OUTCFG112 (Bit 0)                                     */
#define TIMER_OUTCFG28_OUTCFG112_Msk      (0x3fUL)                  /*!< OUTCFG112 (Bitfield-Mask: 0x3f)                       */
/* =======================================================  OUTCFG29  ======================================================== */
#define TIMER_OUTCFG29_OUTCFG119_Pos      (24UL)                    /*!< OUTCFG119 (Bit 24)                                    */
#define TIMER_OUTCFG29_OUTCFG119_Msk      (0x3f000000UL)            /*!< OUTCFG119 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG29_OUTCFG118_Pos      (16UL)                    /*!< OUTCFG118 (Bit 16)                                    */
#define TIMER_OUTCFG29_OUTCFG118_Msk      (0x3f0000UL)              /*!< OUTCFG118 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG29_OUTCFG117_Pos      (8UL)                     /*!< OUTCFG117 (Bit 8)                                     */
#define TIMER_OUTCFG29_OUTCFG117_Msk      (0x3f00UL)                /*!< OUTCFG117 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG29_OUTCFG116_Pos      (0UL)                     /*!< OUTCFG116 (Bit 0)                                     */
#define TIMER_OUTCFG29_OUTCFG116_Msk      (0x3fUL)                  /*!< OUTCFG116 (Bitfield-Mask: 0x3f)                       */
/* =======================================================  OUTCFG30  ======================================================== */
#define TIMER_OUTCFG30_OUTCFG123_Pos      (24UL)                    /*!< OUTCFG123 (Bit 24)                                    */
#define TIMER_OUTCFG30_OUTCFG123_Msk      (0x3f000000UL)            /*!< OUTCFG123 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG30_OUTCFG122_Pos      (16UL)                    /*!< OUTCFG122 (Bit 16)                                    */
#define TIMER_OUTCFG30_OUTCFG122_Msk      (0x3f0000UL)              /*!< OUTCFG122 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG30_OUTCFG121_Pos      (8UL)                     /*!< OUTCFG121 (Bit 8)                                     */
#define TIMER_OUTCFG30_OUTCFG121_Msk      (0x3f00UL)                /*!< OUTCFG121 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG30_OUTCFG120_Pos      (0UL)                     /*!< OUTCFG120 (Bit 0)                                     */
#define TIMER_OUTCFG30_OUTCFG120_Msk      (0x3fUL)                  /*!< OUTCFG120 (Bitfield-Mask: 0x3f)                       */
/* =======================================================  OUTCFG31  ======================================================== */
#define TIMER_OUTCFG31_OUTCFG127_Pos      (24UL)                    /*!< OUTCFG127 (Bit 24)                                    */
#define TIMER_OUTCFG31_OUTCFG127_Msk      (0x3f000000UL)            /*!< OUTCFG127 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG31_OUTCFG126_Pos      (16UL)                    /*!< OUTCFG126 (Bit 16)                                    */
#define TIMER_OUTCFG31_OUTCFG126_Msk      (0x3f0000UL)              /*!< OUTCFG126 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG31_OUTCFG125_Pos      (8UL)                     /*!< OUTCFG125 (Bit 8)                                     */
#define TIMER_OUTCFG31_OUTCFG125_Msk      (0x3f00UL)                /*!< OUTCFG125 (Bitfield-Mask: 0x3f)                       */
#define TIMER_OUTCFG31_OUTCFG124_Pos      (0UL)                     /*!< OUTCFG124 (Bit 0)                                     */
#define TIMER_OUTCFG31_OUTCFG124_Msk      (0x3fUL)                  /*!< OUTCFG124 (Bitfield-Mask: 0x3f)                       */
/* =========================================================  CTRL0  ========================================================= */
#define TIMER_CTRL0_TMR0LMT_Pos           (24UL)                    /*!< TMR0LMT (Bit 24)                                      */
#define TIMER_CTRL0_TMR0LMT_Msk           (0xff000000UL)            /*!< TMR0LMT (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL0_TMR0TMODE_Pos         (16UL)                    /*!< TMR0TMODE (Bit 16)                                    */
#define TIMER_CTRL0_TMR0TMODE_Msk         (0x30000UL)               /*!< TMR0TMODE (Bitfield-Mask: 0x03)                       */
#define TIMER_CTRL0_TMR0CLK_Pos           (8UL)                     /*!< TMR0CLK (Bit 8)                                       */
#define TIMER_CTRL0_TMR0CLK_Msk           (0xff00UL)                /*!< TMR0CLK (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL0_TMR0FN_Pos            (4UL)                     /*!< TMR0FN (Bit 4)                                        */
#define TIMER_CTRL0_TMR0FN_Msk            (0xf0UL)                  /*!< TMR0FN (Bitfield-Mask: 0x0f)                          */
#define TIMER_CTRL0_TMR0POL1_Pos          (3UL)                     /*!< TMR0POL1 (Bit 3)                                      */
#define TIMER_CTRL0_TMR0POL1_Msk          (0x8UL)                   /*!< TMR0POL1 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL0_TMR0POL0_Pos          (2UL)                     /*!< TMR0POL0 (Bit 2)                                      */
#define TIMER_CTRL0_TMR0POL0_Msk          (0x4UL)                   /*!< TMR0POL0 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL0_TMR0CLR_Pos           (1UL)                     /*!< TMR0CLR (Bit 1)                                       */
#define TIMER_CTRL0_TMR0CLR_Msk           (0x2UL)                   /*!< TMR0CLR (Bitfield-Mask: 0x01)                         */
#define TIMER_CTRL0_TMR0EN_Pos            (0UL)                     /*!< TMR0EN (Bit 0)                                        */
#define TIMER_CTRL0_TMR0EN_Msk            (0x1UL)                   /*!< TMR0EN (Bitfield-Mask: 0x01)                          */
/* ========================================================  TIMER0  ========================================================= */
#define TIMER_TIMER0_TIMER0_Pos           (0UL)                     /*!< TIMER0 (Bit 0)                                        */
#define TIMER_TIMER0_TIMER0_Msk           (0xffffffffUL)            /*!< TIMER0 (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  TMR0CMP0  ======================================================== */
#define TIMER_TMR0CMP0_TMR0CMP0_Pos       (0UL)                     /*!< TMR0CMP0 (Bit 0)                                      */
#define TIMER_TMR0CMP0_TMR0CMP0_Msk       (0xffffffffUL)            /*!< TMR0CMP0 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  TMR0CMP1  ======================================================== */
#define TIMER_TMR0CMP1_TMR0CMP1_Pos       (0UL)                     /*!< TMR0CMP1 (Bit 0)                                      */
#define TIMER_TMR0CMP1_TMR0CMP1_Msk       (0xffffffffUL)            /*!< TMR0CMP1 (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  MODE0  ========================================================= */
#define TIMER_MODE0_TMR0TRIGSEL_Pos       (8UL)                     /*!< TMR0TRIGSEL (Bit 8)                                   */
#define TIMER_MODE0_TMR0TRIGSEL_Msk       (0xff00UL)                /*!< TMR0TRIGSEL (Bitfield-Mask: 0xff)                     */
/* ======================================================  TMR0LMTVAL  ======================================================= */
#define TIMER_TMR0LMTVAL_TMR0LMTVAL_Pos   (0UL)                     /*!< TMR0LMTVAL (Bit 0)                                    */
#define TIMER_TMR0LMTVAL_TMR0LMTVAL_Msk   (0xffUL)                  /*!< TMR0LMTVAL (Bitfield-Mask: 0xff)                      */
/* =========================================================  CTRL1  ========================================================= */
#define TIMER_CTRL1_TMR1LMT_Pos           (24UL)                    /*!< TMR1LMT (Bit 24)                                      */
#define TIMER_CTRL1_TMR1LMT_Msk           (0xff000000UL)            /*!< TMR1LMT (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL1_TMR1TMODE_Pos         (16UL)                    /*!< TMR1TMODE (Bit 16)                                    */
#define TIMER_CTRL1_TMR1TMODE_Msk         (0x30000UL)               /*!< TMR1TMODE (Bitfield-Mask: 0x03)                       */
#define TIMER_CTRL1_TMR1CLK_Pos           (8UL)                     /*!< TMR1CLK (Bit 8)                                       */
#define TIMER_CTRL1_TMR1CLK_Msk           (0xff00UL)                /*!< TMR1CLK (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL1_TMR1FN_Pos            (4UL)                     /*!< TMR1FN (Bit 4)                                        */
#define TIMER_CTRL1_TMR1FN_Msk            (0xf0UL)                  /*!< TMR1FN (Bitfield-Mask: 0x0f)                          */
#define TIMER_CTRL1_TMR1POL1_Pos          (3UL)                     /*!< TMR1POL1 (Bit 3)                                      */
#define TIMER_CTRL1_TMR1POL1_Msk          (0x8UL)                   /*!< TMR1POL1 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL1_TMR1POL0_Pos          (2UL)                     /*!< TMR1POL0 (Bit 2)                                      */
#define TIMER_CTRL1_TMR1POL0_Msk          (0x4UL)                   /*!< TMR1POL0 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL1_TMR1CLR_Pos           (1UL)                     /*!< TMR1CLR (Bit 1)                                       */
#define TIMER_CTRL1_TMR1CLR_Msk           (0x2UL)                   /*!< TMR1CLR (Bitfield-Mask: 0x01)                         */
#define TIMER_CTRL1_TMR1EN_Pos            (0UL)                     /*!< TMR1EN (Bit 0)                                        */
#define TIMER_CTRL1_TMR1EN_Msk            (0x1UL)                   /*!< TMR1EN (Bitfield-Mask: 0x01)                          */
/* ========================================================  TIMER1  ========================================================= */
#define TIMER_TIMER1_TIMER1_Pos           (0UL)                     /*!< TIMER1 (Bit 0)                                        */
#define TIMER_TIMER1_TIMER1_Msk           (0xffffffffUL)            /*!< TIMER1 (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  TMR1CMP0  ======================================================== */
#define TIMER_TMR1CMP0_TMR1CMP0_Pos       (0UL)                     /*!< TMR1CMP0 (Bit 0)                                      */
#define TIMER_TMR1CMP0_TMR1CMP0_Msk       (0xffffffffUL)            /*!< TMR1CMP0 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  TMR1CMP1  ======================================================== */
#define TIMER_TMR1CMP1_TMR1CMP1_Pos       (0UL)                     /*!< TMR1CMP1 (Bit 0)                                      */
#define TIMER_TMR1CMP1_TMR1CMP1_Msk       (0xffffffffUL)            /*!< TMR1CMP1 (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  MODE1  ========================================================= */
#define TIMER_MODE1_TMR1TRIGSEL_Pos       (8UL)                     /*!< TMR1TRIGSEL (Bit 8)                                   */
#define TIMER_MODE1_TMR1TRIGSEL_Msk       (0xff00UL)                /*!< TMR1TRIGSEL (Bitfield-Mask: 0xff)                     */
/* ======================================================  TMR1LMTVAL  ======================================================= */
#define TIMER_TMR1LMTVAL_TMR1LMTVAL_Pos   (0UL)                     /*!< TMR1LMTVAL (Bit 0)                                    */
#define TIMER_TMR1LMTVAL_TMR1LMTVAL_Msk   (0xffUL)                  /*!< TMR1LMTVAL (Bitfield-Mask: 0xff)                      */
/* =========================================================  CTRL2  ========================================================= */
#define TIMER_CTRL2_TMR2LMT_Pos           (24UL)                    /*!< TMR2LMT (Bit 24)                                      */
#define TIMER_CTRL2_TMR2LMT_Msk           (0xff000000UL)            /*!< TMR2LMT (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL2_TMR2TMODE_Pos         (16UL)                    /*!< TMR2TMODE (Bit 16)                                    */
#define TIMER_CTRL2_TMR2TMODE_Msk         (0x30000UL)               /*!< TMR2TMODE (Bitfield-Mask: 0x03)                       */
#define TIMER_CTRL2_TMR2CLK_Pos           (8UL)                     /*!< TMR2CLK (Bit 8)                                       */
#define TIMER_CTRL2_TMR2CLK_Msk           (0xff00UL)                /*!< TMR2CLK (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL2_TMR2FN_Pos            (4UL)                     /*!< TMR2FN (Bit 4)                                        */
#define TIMER_CTRL2_TMR2FN_Msk            (0xf0UL)                  /*!< TMR2FN (Bitfield-Mask: 0x0f)                          */
#define TIMER_CTRL2_TMR2POL1_Pos          (3UL)                     /*!< TMR2POL1 (Bit 3)                                      */
#define TIMER_CTRL2_TMR2POL1_Msk          (0x8UL)                   /*!< TMR2POL1 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL2_TMR2POL0_Pos          (2UL)                     /*!< TMR2POL0 (Bit 2)                                      */
#define TIMER_CTRL2_TMR2POL0_Msk          (0x4UL)                   /*!< TMR2POL0 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL2_TMR2CLR_Pos           (1UL)                     /*!< TMR2CLR (Bit 1)                                       */
#define TIMER_CTRL2_TMR2CLR_Msk           (0x2UL)                   /*!< TMR2CLR (Bitfield-Mask: 0x01)                         */
#define TIMER_CTRL2_TMR2EN_Pos            (0UL)                     /*!< TMR2EN (Bit 0)                                        */
#define TIMER_CTRL2_TMR2EN_Msk            (0x1UL)                   /*!< TMR2EN (Bitfield-Mask: 0x01)                          */
/* ========================================================  TIMER2  ========================================================= */
#define TIMER_TIMER2_TIMER2_Pos           (0UL)                     /*!< TIMER2 (Bit 0)                                        */
#define TIMER_TIMER2_TIMER2_Msk           (0xffffffffUL)            /*!< TIMER2 (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  TMR2CMP0  ======================================================== */
#define TIMER_TMR2CMP0_TMR2CMP0_Pos       (0UL)                     /*!< TMR2CMP0 (Bit 0)                                      */
#define TIMER_TMR2CMP0_TMR2CMP0_Msk       (0xffffffffUL)            /*!< TMR2CMP0 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  TMR2CMP1  ======================================================== */
#define TIMER_TMR2CMP1_TMR2CMP1_Pos       (0UL)                     /*!< TMR2CMP1 (Bit 0)                                      */
#define TIMER_TMR2CMP1_TMR2CMP1_Msk       (0xffffffffUL)            /*!< TMR2CMP1 (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  MODE2  ========================================================= */
#define TIMER_MODE2_TMR2TRIGSEL_Pos       (8UL)                     /*!< TMR2TRIGSEL (Bit 8)                                   */
#define TIMER_MODE2_TMR2TRIGSEL_Msk       (0xff00UL)                /*!< TMR2TRIGSEL (Bitfield-Mask: 0xff)                     */
/* ======================================================  TMR2LMTVAL  ======================================================= */
#define TIMER_TMR2LMTVAL_TMR2LMTVAL_Pos   (0UL)                     /*!< TMR2LMTVAL (Bit 0)                                    */
#define TIMER_TMR2LMTVAL_TMR2LMTVAL_Msk   (0xffUL)                  /*!< TMR2LMTVAL (Bitfield-Mask: 0xff)                      */
/* =========================================================  CTRL3  ========================================================= */
#define TIMER_CTRL3_TMR3LMT_Pos           (24UL)                    /*!< TMR3LMT (Bit 24)                                      */
#define TIMER_CTRL3_TMR3LMT_Msk           (0xff000000UL)            /*!< TMR3LMT (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL3_TMR3TMODE_Pos         (16UL)                    /*!< TMR3TMODE (Bit 16)                                    */
#define TIMER_CTRL3_TMR3TMODE_Msk         (0x30000UL)               /*!< TMR3TMODE (Bitfield-Mask: 0x03)                       */
#define TIMER_CTRL3_TMR3CLK_Pos           (8UL)                     /*!< TMR3CLK (Bit 8)                                       */
#define TIMER_CTRL3_TMR3CLK_Msk           (0xff00UL)                /*!< TMR3CLK (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL3_TMR3FN_Pos            (4UL)                     /*!< TMR3FN (Bit 4)                                        */
#define TIMER_CTRL3_TMR3FN_Msk            (0xf0UL)                  /*!< TMR3FN (Bitfield-Mask: 0x0f)                          */
#define TIMER_CTRL3_TMR3POL1_Pos          (3UL)                     /*!< TMR3POL1 (Bit 3)                                      */
#define TIMER_CTRL3_TMR3POL1_Msk          (0x8UL)                   /*!< TMR3POL1 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL3_TMR3POL0_Pos          (2UL)                     /*!< TMR3POL0 (Bit 2)                                      */
#define TIMER_CTRL3_TMR3POL0_Msk          (0x4UL)                   /*!< TMR3POL0 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL3_TMR3CLR_Pos           (1UL)                     /*!< TMR3CLR (Bit 1)                                       */
#define TIMER_CTRL3_TMR3CLR_Msk           (0x2UL)                   /*!< TMR3CLR (Bitfield-Mask: 0x01)                         */
#define TIMER_CTRL3_TMR3EN_Pos            (0UL)                     /*!< TMR3EN (Bit 0)                                        */
#define TIMER_CTRL3_TMR3EN_Msk            (0x1UL)                   /*!< TMR3EN (Bitfield-Mask: 0x01)                          */
/* ========================================================  TIMER3  ========================================================= */
#define TIMER_TIMER3_TIMER3_Pos           (0UL)                     /*!< TIMER3 (Bit 0)                                        */
#define TIMER_TIMER3_TIMER3_Msk           (0xffffffffUL)            /*!< TIMER3 (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  TMR3CMP0  ======================================================== */
#define TIMER_TMR3CMP0_TMR3CMP0_Pos       (0UL)                     /*!< TMR3CMP0 (Bit 0)                                      */
#define TIMER_TMR3CMP0_TMR3CMP0_Msk       (0xffffffffUL)            /*!< TMR3CMP0 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  TMR3CMP1  ======================================================== */
#define TIMER_TMR3CMP1_TMR3CMP1_Pos       (0UL)                     /*!< TMR3CMP1 (Bit 0)                                      */
#define TIMER_TMR3CMP1_TMR3CMP1_Msk       (0xffffffffUL)            /*!< TMR3CMP1 (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  MODE3  ========================================================= */
#define TIMER_MODE3_TMR3TRIGSEL_Pos       (8UL)                     /*!< TMR3TRIGSEL (Bit 8)                                   */
#define TIMER_MODE3_TMR3TRIGSEL_Msk       (0xff00UL)                /*!< TMR3TRIGSEL (Bitfield-Mask: 0xff)                     */
/* ======================================================  TMR3LMTVAL  ======================================================= */
#define TIMER_TMR3LMTVAL_TMR3LMTVAL_Pos   (0UL)                     /*!< TMR3LMTVAL (Bit 0)                                    */
#define TIMER_TMR3LMTVAL_TMR3LMTVAL_Msk   (0xffUL)                  /*!< TMR3LMTVAL (Bitfield-Mask: 0xff)                      */
/* =========================================================  CTRL4  ========================================================= */
#define TIMER_CTRL4_TMR4LMT_Pos           (24UL)                    /*!< TMR4LMT (Bit 24)                                      */
#define TIMER_CTRL4_TMR4LMT_Msk           (0xff000000UL)            /*!< TMR4LMT (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL4_TMR4TMODE_Pos         (16UL)                    /*!< TMR4TMODE (Bit 16)                                    */
#define TIMER_CTRL4_TMR4TMODE_Msk         (0x30000UL)               /*!< TMR4TMODE (Bitfield-Mask: 0x03)                       */
#define TIMER_CTRL4_TMR4CLK_Pos           (8UL)                     /*!< TMR4CLK (Bit 8)                                       */
#define TIMER_CTRL4_TMR4CLK_Msk           (0xff00UL)                /*!< TMR4CLK (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL4_TMR4FN_Pos            (4UL)                     /*!< TMR4FN (Bit 4)                                        */
#define TIMER_CTRL4_TMR4FN_Msk            (0xf0UL)                  /*!< TMR4FN (Bitfield-Mask: 0x0f)                          */
#define TIMER_CTRL4_TMR4POL1_Pos          (3UL)                     /*!< TMR4POL1 (Bit 3)                                      */
#define TIMER_CTRL4_TMR4POL1_Msk          (0x8UL)                   /*!< TMR4POL1 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL4_TMR4POL0_Pos          (2UL)                     /*!< TMR4POL0 (Bit 2)                                      */
#define TIMER_CTRL4_TMR4POL0_Msk          (0x4UL)                   /*!< TMR4POL0 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL4_TMR4CLR_Pos           (1UL)                     /*!< TMR4CLR (Bit 1)                                       */
#define TIMER_CTRL4_TMR4CLR_Msk           (0x2UL)                   /*!< TMR4CLR (Bitfield-Mask: 0x01)                         */
#define TIMER_CTRL4_TMR4EN_Pos            (0UL)                     /*!< TMR4EN (Bit 0)                                        */
#define TIMER_CTRL4_TMR4EN_Msk            (0x1UL)                   /*!< TMR4EN (Bitfield-Mask: 0x01)                          */
/* ========================================================  TIMER4  ========================================================= */
#define TIMER_TIMER4_TIMER4_Pos           (0UL)                     /*!< TIMER4 (Bit 0)                                        */
#define TIMER_TIMER4_TIMER4_Msk           (0xffffffffUL)            /*!< TIMER4 (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  TMR4CMP0  ======================================================== */
#define TIMER_TMR4CMP0_TMR4CMP0_Pos       (0UL)                     /*!< TMR4CMP0 (Bit 0)                                      */
#define TIMER_TMR4CMP0_TMR4CMP0_Msk       (0xffffffffUL)            /*!< TMR4CMP0 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  TMR4CMP1  ======================================================== */
#define TIMER_TMR4CMP1_TMR4CMP1_Pos       (0UL)                     /*!< TMR4CMP1 (Bit 0)                                      */
#define TIMER_TMR4CMP1_TMR4CMP1_Msk       (0xffffffffUL)            /*!< TMR4CMP1 (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  MODE4  ========================================================= */
#define TIMER_MODE4_TMR4TRIGSEL_Pos       (8UL)                     /*!< TMR4TRIGSEL (Bit 8)                                   */
#define TIMER_MODE4_TMR4TRIGSEL_Msk       (0xff00UL)                /*!< TMR4TRIGSEL (Bitfield-Mask: 0xff)                     */
/* ======================================================  TMR4LMTVAL  ======================================================= */
#define TIMER_TMR4LMTVAL_TMR4LMTVAL_Pos   (0UL)                     /*!< TMR4LMTVAL (Bit 0)                                    */
#define TIMER_TMR4LMTVAL_TMR4LMTVAL_Msk   (0xffUL)                  /*!< TMR4LMTVAL (Bitfield-Mask: 0xff)                      */
/* =========================================================  CTRL5  ========================================================= */
#define TIMER_CTRL5_TMR5LMT_Pos           (24UL)                    /*!< TMR5LMT (Bit 24)                                      */
#define TIMER_CTRL5_TMR5LMT_Msk           (0xff000000UL)            /*!< TMR5LMT (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL5_TMR5TMODE_Pos         (16UL)                    /*!< TMR5TMODE (Bit 16)                                    */
#define TIMER_CTRL5_TMR5TMODE_Msk         (0x30000UL)               /*!< TMR5TMODE (Bitfield-Mask: 0x03)                       */
#define TIMER_CTRL5_TMR5CLK_Pos           (8UL)                     /*!< TMR5CLK (Bit 8)                                       */
#define TIMER_CTRL5_TMR5CLK_Msk           (0xff00UL)                /*!< TMR5CLK (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL5_TMR5FN_Pos            (4UL)                     /*!< TMR5FN (Bit 4)                                        */
#define TIMER_CTRL5_TMR5FN_Msk            (0xf0UL)                  /*!< TMR5FN (Bitfield-Mask: 0x0f)                          */
#define TIMER_CTRL5_TMR5POL1_Pos          (3UL)                     /*!< TMR5POL1 (Bit 3)                                      */
#define TIMER_CTRL5_TMR5POL1_Msk          (0x8UL)                   /*!< TMR5POL1 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL5_TMR5POL0_Pos          (2UL)                     /*!< TMR5POL0 (Bit 2)                                      */
#define TIMER_CTRL5_TMR5POL0_Msk          (0x4UL)                   /*!< TMR5POL0 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL5_TMR5CLR_Pos           (1UL)                     /*!< TMR5CLR (Bit 1)                                       */
#define TIMER_CTRL5_TMR5CLR_Msk           (0x2UL)                   /*!< TMR5CLR (Bitfield-Mask: 0x01)                         */
#define TIMER_CTRL5_TMR5EN_Pos            (0UL)                     /*!< TMR5EN (Bit 0)                                        */
#define TIMER_CTRL5_TMR5EN_Msk            (0x1UL)                   /*!< TMR5EN (Bitfield-Mask: 0x01)                          */
/* ========================================================  TIMER5  ========================================================= */
#define TIMER_TIMER5_TIMER5_Pos           (0UL)                     /*!< TIMER5 (Bit 0)                                        */
#define TIMER_TIMER5_TIMER5_Msk           (0xffffffffUL)            /*!< TIMER5 (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  TMR5CMP0  ======================================================== */
#define TIMER_TMR5CMP0_TMR5CMP0_Pos       (0UL)                     /*!< TMR5CMP0 (Bit 0)                                      */
#define TIMER_TMR5CMP0_TMR5CMP0_Msk       (0xffffffffUL)            /*!< TMR5CMP0 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  TMR5CMP1  ======================================================== */
#define TIMER_TMR5CMP1_TMR5CMP1_Pos       (0UL)                     /*!< TMR5CMP1 (Bit 0)                                      */
#define TIMER_TMR5CMP1_TMR5CMP1_Msk       (0xffffffffUL)            /*!< TMR5CMP1 (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  MODE5  ========================================================= */
#define TIMER_MODE5_TMR5TRIGSEL_Pos       (8UL)                     /*!< TMR5TRIGSEL (Bit 8)                                   */
#define TIMER_MODE5_TMR5TRIGSEL_Msk       (0xff00UL)                /*!< TMR5TRIGSEL (Bitfield-Mask: 0xff)                     */
/* ======================================================  TMR5LMTVAL  ======================================================= */
#define TIMER_TMR5LMTVAL_TMR5LMTVAL_Pos   (0UL)                     /*!< TMR5LMTVAL (Bit 0)                                    */
#define TIMER_TMR5LMTVAL_TMR5LMTVAL_Msk   (0xffUL)                  /*!< TMR5LMTVAL (Bitfield-Mask: 0xff)                      */
/* =========================================================  CTRL6  ========================================================= */
#define TIMER_CTRL6_TMR6LMT_Pos           (24UL)                    /*!< TMR6LMT (Bit 24)                                      */
#define TIMER_CTRL6_TMR6LMT_Msk           (0xff000000UL)            /*!< TMR6LMT (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL6_TMR6TMODE_Pos         (16UL)                    /*!< TMR6TMODE (Bit 16)                                    */
#define TIMER_CTRL6_TMR6TMODE_Msk         (0x30000UL)               /*!< TMR6TMODE (Bitfield-Mask: 0x03)                       */
#define TIMER_CTRL6_TMR6CLK_Pos           (8UL)                     /*!< TMR6CLK (Bit 8)                                       */
#define TIMER_CTRL6_TMR6CLK_Msk           (0xff00UL)                /*!< TMR6CLK (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL6_TMR6FN_Pos            (4UL)                     /*!< TMR6FN (Bit 4)                                        */
#define TIMER_CTRL6_TMR6FN_Msk            (0xf0UL)                  /*!< TMR6FN (Bitfield-Mask: 0x0f)                          */
#define TIMER_CTRL6_TMR6POL1_Pos          (3UL)                     /*!< TMR6POL1 (Bit 3)                                      */
#define TIMER_CTRL6_TMR6POL1_Msk          (0x8UL)                   /*!< TMR6POL1 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL6_TMR6POL0_Pos          (2UL)                     /*!< TMR6POL0 (Bit 2)                                      */
#define TIMER_CTRL6_TMR6POL0_Msk          (0x4UL)                   /*!< TMR6POL0 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL6_TMR6CLR_Pos           (1UL)                     /*!< TMR6CLR (Bit 1)                                       */
#define TIMER_CTRL6_TMR6CLR_Msk           (0x2UL)                   /*!< TMR6CLR (Bitfield-Mask: 0x01)                         */
#define TIMER_CTRL6_TMR6EN_Pos            (0UL)                     /*!< TMR6EN (Bit 0)                                        */
#define TIMER_CTRL6_TMR6EN_Msk            (0x1UL)                   /*!< TMR6EN (Bitfield-Mask: 0x01)                          */
/* ========================================================  TIMER6  ========================================================= */
#define TIMER_TIMER6_TIMER6_Pos           (0UL)                     /*!< TIMER6 (Bit 0)                                        */
#define TIMER_TIMER6_TIMER6_Msk           (0xffffffffUL)            /*!< TIMER6 (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  TMR6CMP0  ======================================================== */
#define TIMER_TMR6CMP0_TMR6CMP0_Pos       (0UL)                     /*!< TMR6CMP0 (Bit 0)                                      */
#define TIMER_TMR6CMP0_TMR6CMP0_Msk       (0xffffffffUL)            /*!< TMR6CMP0 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  TMR6CMP1  ======================================================== */
#define TIMER_TMR6CMP1_TMR6CMP1_Pos       (0UL)                     /*!< TMR6CMP1 (Bit 0)                                      */
#define TIMER_TMR6CMP1_TMR6CMP1_Msk       (0xffffffffUL)            /*!< TMR6CMP1 (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  MODE6  ========================================================= */
#define TIMER_MODE6_TMR6TRIGSEL_Pos       (8UL)                     /*!< TMR6TRIGSEL (Bit 8)                                   */
#define TIMER_MODE6_TMR6TRIGSEL_Msk       (0xff00UL)                /*!< TMR6TRIGSEL (Bitfield-Mask: 0xff)                     */
/* ======================================================  TMR6LMTVAL  ======================================================= */
#define TIMER_TMR6LMTVAL_TMR6LMTVAL_Pos   (0UL)                     /*!< TMR6LMTVAL (Bit 0)                                    */
#define TIMER_TMR6LMTVAL_TMR6LMTVAL_Msk   (0xffUL)                  /*!< TMR6LMTVAL (Bitfield-Mask: 0xff)                      */
/* =========================================================  CTRL7  ========================================================= */
#define TIMER_CTRL7_TMR7LMT_Pos           (24UL)                    /*!< TMR7LMT (Bit 24)                                      */
#define TIMER_CTRL7_TMR7LMT_Msk           (0xff000000UL)            /*!< TMR7LMT (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL7_TMR7TMODE_Pos         (16UL)                    /*!< TMR7TMODE (Bit 16)                                    */
#define TIMER_CTRL7_TMR7TMODE_Msk         (0x30000UL)               /*!< TMR7TMODE (Bitfield-Mask: 0x03)                       */
#define TIMER_CTRL7_TMR7CLK_Pos           (8UL)                     /*!< TMR7CLK (Bit 8)                                       */
#define TIMER_CTRL7_TMR7CLK_Msk           (0xff00UL)                /*!< TMR7CLK (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL7_TMR7FN_Pos            (4UL)                     /*!< TMR7FN (Bit 4)                                        */
#define TIMER_CTRL7_TMR7FN_Msk            (0xf0UL)                  /*!< TMR7FN (Bitfield-Mask: 0x0f)                          */
#define TIMER_CTRL7_TMR7POL1_Pos          (3UL)                     /*!< TMR7POL1 (Bit 3)                                      */
#define TIMER_CTRL7_TMR7POL1_Msk          (0x8UL)                   /*!< TMR7POL1 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL7_TMR7POL0_Pos          (2UL)                     /*!< TMR7POL0 (Bit 2)                                      */
#define TIMER_CTRL7_TMR7POL0_Msk          (0x4UL)                   /*!< TMR7POL0 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL7_TMR7CLR_Pos           (1UL)                     /*!< TMR7CLR (Bit 1)                                       */
#define TIMER_CTRL7_TMR7CLR_Msk           (0x2UL)                   /*!< TMR7CLR (Bitfield-Mask: 0x01)                         */
#define TIMER_CTRL7_TMR7EN_Pos            (0UL)                     /*!< TMR7EN (Bit 0)                                        */
#define TIMER_CTRL7_TMR7EN_Msk            (0x1UL)                   /*!< TMR7EN (Bitfield-Mask: 0x01)                          */
/* ========================================================  TIMER7  ========================================================= */
#define TIMER_TIMER7_TIMER7_Pos           (0UL)                     /*!< TIMER7 (Bit 0)                                        */
#define TIMER_TIMER7_TIMER7_Msk           (0xffffffffUL)            /*!< TIMER7 (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  TMR7CMP0  ======================================================== */
#define TIMER_TMR7CMP0_TMR7CMP0_Pos       (0UL)                     /*!< TMR7CMP0 (Bit 0)                                      */
#define TIMER_TMR7CMP0_TMR7CMP0_Msk       (0xffffffffUL)            /*!< TMR7CMP0 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  TMR7CMP1  ======================================================== */
#define TIMER_TMR7CMP1_TMR7CMP1_Pos       (0UL)                     /*!< TMR7CMP1 (Bit 0)                                      */
#define TIMER_TMR7CMP1_TMR7CMP1_Msk       (0xffffffffUL)            /*!< TMR7CMP1 (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  MODE7  ========================================================= */
#define TIMER_MODE7_TMR7TRIGSEL_Pos       (8UL)                     /*!< TMR7TRIGSEL (Bit 8)                                   */
#define TIMER_MODE7_TMR7TRIGSEL_Msk       (0xff00UL)                /*!< TMR7TRIGSEL (Bitfield-Mask: 0xff)                     */
/* ======================================================  TMR7LMTVAL  ======================================================= */
#define TIMER_TMR7LMTVAL_TMR7LMTVAL_Pos   (0UL)                     /*!< TMR7LMTVAL (Bit 0)                                    */
#define TIMER_TMR7LMTVAL_TMR7LMTVAL_Msk   (0xffUL)                  /*!< TMR7LMTVAL (Bitfield-Mask: 0xff)                      */
/* =========================================================  CTRL8  ========================================================= */
#define TIMER_CTRL8_TMR8LMT_Pos           (24UL)                    /*!< TMR8LMT (Bit 24)                                      */
#define TIMER_CTRL8_TMR8LMT_Msk           (0xff000000UL)            /*!< TMR8LMT (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL8_TMR8TMODE_Pos         (16UL)                    /*!< TMR8TMODE (Bit 16)                                    */
#define TIMER_CTRL8_TMR8TMODE_Msk         (0x30000UL)               /*!< TMR8TMODE (Bitfield-Mask: 0x03)                       */
#define TIMER_CTRL8_TMR8CLK_Pos           (8UL)                     /*!< TMR8CLK (Bit 8)                                       */
#define TIMER_CTRL8_TMR8CLK_Msk           (0xff00UL)                /*!< TMR8CLK (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL8_TMR8FN_Pos            (4UL)                     /*!< TMR8FN (Bit 4)                                        */
#define TIMER_CTRL8_TMR8FN_Msk            (0xf0UL)                  /*!< TMR8FN (Bitfield-Mask: 0x0f)                          */
#define TIMER_CTRL8_TMR8POL1_Pos          (3UL)                     /*!< TMR8POL1 (Bit 3)                                      */
#define TIMER_CTRL8_TMR8POL1_Msk          (0x8UL)                   /*!< TMR8POL1 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL8_TMR8POL0_Pos          (2UL)                     /*!< TMR8POL0 (Bit 2)                                      */
#define TIMER_CTRL8_TMR8POL0_Msk          (0x4UL)                   /*!< TMR8POL0 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL8_TMR8CLR_Pos           (1UL)                     /*!< TMR8CLR (Bit 1)                                       */
#define TIMER_CTRL8_TMR8CLR_Msk           (0x2UL)                   /*!< TMR8CLR (Bitfield-Mask: 0x01)                         */
#define TIMER_CTRL8_TMR8EN_Pos            (0UL)                     /*!< TMR8EN (Bit 0)                                        */
#define TIMER_CTRL8_TMR8EN_Msk            (0x1UL)                   /*!< TMR8EN (Bitfield-Mask: 0x01)                          */
/* ========================================================  TIMER8  ========================================================= */
#define TIMER_TIMER8_TIMER8_Pos           (0UL)                     /*!< TIMER8 (Bit 0)                                        */
#define TIMER_TIMER8_TIMER8_Msk           (0xffffffffUL)            /*!< TIMER8 (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  TMR8CMP0  ======================================================== */
#define TIMER_TMR8CMP0_TMR8CMP0_Pos       (0UL)                     /*!< TMR8CMP0 (Bit 0)                                      */
#define TIMER_TMR8CMP0_TMR8CMP0_Msk       (0xffffffffUL)            /*!< TMR8CMP0 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  TMR8CMP1  ======================================================== */
#define TIMER_TMR8CMP1_TMR8CMP1_Pos       (0UL)                     /*!< TMR8CMP1 (Bit 0)                                      */
#define TIMER_TMR8CMP1_TMR8CMP1_Msk       (0xffffffffUL)            /*!< TMR8CMP1 (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  MODE8  ========================================================= */
#define TIMER_MODE8_TMR8TRIGSEL_Pos       (8UL)                     /*!< TMR8TRIGSEL (Bit 8)                                   */
#define TIMER_MODE8_TMR8TRIGSEL_Msk       (0xff00UL)                /*!< TMR8TRIGSEL (Bitfield-Mask: 0xff)                     */
/* ======================================================  TMR8LMTVAL  ======================================================= */
#define TIMER_TMR8LMTVAL_TMR8LMTVAL_Pos   (0UL)                     /*!< TMR8LMTVAL (Bit 0)                                    */
#define TIMER_TMR8LMTVAL_TMR8LMTVAL_Msk   (0xffUL)                  /*!< TMR8LMTVAL (Bitfield-Mask: 0xff)                      */
/* =========================================================  CTRL9  ========================================================= */
#define TIMER_CTRL9_TMR9LMT_Pos           (24UL)                    /*!< TMR9LMT (Bit 24)                                      */
#define TIMER_CTRL9_TMR9LMT_Msk           (0xff000000UL)            /*!< TMR9LMT (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL9_TMR9TMODE_Pos         (16UL)                    /*!< TMR9TMODE (Bit 16)                                    */
#define TIMER_CTRL9_TMR9TMODE_Msk         (0x30000UL)               /*!< TMR9TMODE (Bitfield-Mask: 0x03)                       */
#define TIMER_CTRL9_TMR9CLK_Pos           (8UL)                     /*!< TMR9CLK (Bit 8)                                       */
#define TIMER_CTRL9_TMR9CLK_Msk           (0xff00UL)                /*!< TMR9CLK (Bitfield-Mask: 0xff)                         */
#define TIMER_CTRL9_TMR9FN_Pos            (4UL)                     /*!< TMR9FN (Bit 4)                                        */
#define TIMER_CTRL9_TMR9FN_Msk            (0xf0UL)                  /*!< TMR9FN (Bitfield-Mask: 0x0f)                          */
#define TIMER_CTRL9_TMR9POL1_Pos          (3UL)                     /*!< TMR9POL1 (Bit 3)                                      */
#define TIMER_CTRL9_TMR9POL1_Msk          (0x8UL)                   /*!< TMR9POL1 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL9_TMR9POL0_Pos          (2UL)                     /*!< TMR9POL0 (Bit 2)                                      */
#define TIMER_CTRL9_TMR9POL0_Msk          (0x4UL)                   /*!< TMR9POL0 (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL9_TMR9CLR_Pos           (1UL)                     /*!< TMR9CLR (Bit 1)                                       */
#define TIMER_CTRL9_TMR9CLR_Msk           (0x2UL)                   /*!< TMR9CLR (Bitfield-Mask: 0x01)                         */
#define TIMER_CTRL9_TMR9EN_Pos            (0UL)                     /*!< TMR9EN (Bit 0)                                        */
#define TIMER_CTRL9_TMR9EN_Msk            (0x1UL)                   /*!< TMR9EN (Bitfield-Mask: 0x01)                          */
/* ========================================================  TIMER9  ========================================================= */
#define TIMER_TIMER9_TIMER9_Pos           (0UL)                     /*!< TIMER9 (Bit 0)                                        */
#define TIMER_TIMER9_TIMER9_Msk           (0xffffffffUL)            /*!< TIMER9 (Bitfield-Mask: 0xffffffff)                    */
/* =======================================================  TMR9CMP0  ======================================================== */
#define TIMER_TMR9CMP0_TMR9CMP0_Pos       (0UL)                     /*!< TMR9CMP0 (Bit 0)                                      */
#define TIMER_TMR9CMP0_TMR9CMP0_Msk       (0xffffffffUL)            /*!< TMR9CMP0 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  TMR9CMP1  ======================================================== */
#define TIMER_TMR9CMP1_TMR9CMP1_Pos       (0UL)                     /*!< TMR9CMP1 (Bit 0)                                      */
#define TIMER_TMR9CMP1_TMR9CMP1_Msk       (0xffffffffUL)            /*!< TMR9CMP1 (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  MODE9  ========================================================= */
#define TIMER_MODE9_TMR9TRIGSEL_Pos       (8UL)                     /*!< TMR9TRIGSEL (Bit 8)                                   */
#define TIMER_MODE9_TMR9TRIGSEL_Msk       (0xff00UL)                /*!< TMR9TRIGSEL (Bitfield-Mask: 0xff)                     */
/* ======================================================  TMR9LMTVAL  ======================================================= */
#define TIMER_TMR9LMTVAL_TMR9LMTVAL_Pos   (0UL)                     /*!< TMR9LMTVAL (Bit 0)                                    */
#define TIMER_TMR9LMTVAL_TMR9LMTVAL_Msk   (0xffUL)                  /*!< TMR9LMTVAL (Bitfield-Mask: 0xff)                      */
/* ========================================================  CTRL10  ========================================================= */
#define TIMER_CTRL10_TMR10LMT_Pos         (24UL)                    /*!< TMR10LMT (Bit 24)                                     */
#define TIMER_CTRL10_TMR10LMT_Msk         (0xff000000UL)            /*!< TMR10LMT (Bitfield-Mask: 0xff)                        */
#define TIMER_CTRL10_TMR10TMODE_Pos       (16UL)                    /*!< TMR10TMODE (Bit 16)                                   */
#define TIMER_CTRL10_TMR10TMODE_Msk       (0x30000UL)               /*!< TMR10TMODE (Bitfield-Mask: 0x03)                      */
#define TIMER_CTRL10_TMR10CLK_Pos         (8UL)                     /*!< TMR10CLK (Bit 8)                                      */
#define TIMER_CTRL10_TMR10CLK_Msk         (0xff00UL)                /*!< TMR10CLK (Bitfield-Mask: 0xff)                        */
#define TIMER_CTRL10_TMR10FN_Pos          (4UL)                     /*!< TMR10FN (Bit 4)                                       */
#define TIMER_CTRL10_TMR10FN_Msk          (0xf0UL)                  /*!< TMR10FN (Bitfield-Mask: 0x0f)                         */
#define TIMER_CTRL10_TMR10POL1_Pos        (3UL)                     /*!< TMR10POL1 (Bit 3)                                     */
#define TIMER_CTRL10_TMR10POL1_Msk        (0x8UL)                   /*!< TMR10POL1 (Bitfield-Mask: 0x01)                       */
#define TIMER_CTRL10_TMR10POL0_Pos        (2UL)                     /*!< TMR10POL0 (Bit 2)                                     */
#define TIMER_CTRL10_TMR10POL0_Msk        (0x4UL)                   /*!< TMR10POL0 (Bitfield-Mask: 0x01)                       */
#define TIMER_CTRL10_TMR10CLR_Pos         (1UL)                     /*!< TMR10CLR (Bit 1)                                      */
#define TIMER_CTRL10_TMR10CLR_Msk         (0x2UL)                   /*!< TMR10CLR (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL10_TMR10EN_Pos          (0UL)                     /*!< TMR10EN (Bit 0)                                       */
#define TIMER_CTRL10_TMR10EN_Msk          (0x1UL)                   /*!< TMR10EN (Bitfield-Mask: 0x01)                         */
/* ========================================================  TIMER10  ======================================================== */
#define TIMER_TIMER10_TIMER10_Pos         (0UL)                     /*!< TIMER10 (Bit 0)                                       */
#define TIMER_TIMER10_TIMER10_Msk         (0xffffffffUL)            /*!< TIMER10 (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  TMR10CMP0  ======================================================= */
#define TIMER_TMR10CMP0_TMR10CMP0_Pos     (0UL)                     /*!< TMR10CMP0 (Bit 0)                                     */
#define TIMER_TMR10CMP0_TMR10CMP0_Msk     (0xffffffffUL)            /*!< TMR10CMP0 (Bitfield-Mask: 0xffffffff)                 */
/* =======================================================  TMR10CMP1  ======================================================= */
#define TIMER_TMR10CMP1_TMR10CMP1_Pos     (0UL)                     /*!< TMR10CMP1 (Bit 0)                                     */
#define TIMER_TMR10CMP1_TMR10CMP1_Msk     (0xffffffffUL)            /*!< TMR10CMP1 (Bitfield-Mask: 0xffffffff)                 */
/* ========================================================  MODE10  ========================================================= */
#define TIMER_MODE10_TMR10TRIGSEL_Pos     (8UL)                     /*!< TMR10TRIGSEL (Bit 8)                                  */
#define TIMER_MODE10_TMR10TRIGSEL_Msk     (0xff00UL)                /*!< TMR10TRIGSEL (Bitfield-Mask: 0xff)                    */
/* ======================================================  TMR10LMTVAL  ====================================================== */
#define TIMER_TMR10LMTVAL_TMR10LMTVAL_Pos (0UL)                     /*!< TMR10LMTVAL (Bit 0)                                   */
#define TIMER_TMR10LMTVAL_TMR10LMTVAL_Msk (0xffUL)                  /*!< TMR10LMTVAL (Bitfield-Mask: 0xff)                     */
/* ========================================================  CTRL11  ========================================================= */
#define TIMER_CTRL11_TMR11LMT_Pos         (24UL)                    /*!< TMR11LMT (Bit 24)                                     */
#define TIMER_CTRL11_TMR11LMT_Msk         (0xff000000UL)            /*!< TMR11LMT (Bitfield-Mask: 0xff)                        */
#define TIMER_CTRL11_TMR11TMODE_Pos       (16UL)                    /*!< TMR11TMODE (Bit 16)                                   */
#define TIMER_CTRL11_TMR11TMODE_Msk       (0x30000UL)               /*!< TMR11TMODE (Bitfield-Mask: 0x03)                      */
#define TIMER_CTRL11_TMR11CLK_Pos         (8UL)                     /*!< TMR11CLK (Bit 8)                                      */
#define TIMER_CTRL11_TMR11CLK_Msk         (0xff00UL)                /*!< TMR11CLK (Bitfield-Mask: 0xff)                        */
#define TIMER_CTRL11_TMR11FN_Pos          (4UL)                     /*!< TMR11FN (Bit 4)                                       */
#define TIMER_CTRL11_TMR11FN_Msk          (0xf0UL)                  /*!< TMR11FN (Bitfield-Mask: 0x0f)                         */
#define TIMER_CTRL11_TMR11POL1_Pos        (3UL)                     /*!< TMR11POL1 (Bit 3)                                     */
#define TIMER_CTRL11_TMR11POL1_Msk        (0x8UL)                   /*!< TMR11POL1 (Bitfield-Mask: 0x01)                       */
#define TIMER_CTRL11_TMR11POL0_Pos        (2UL)                     /*!< TMR11POL0 (Bit 2)                                     */
#define TIMER_CTRL11_TMR11POL0_Msk        (0x4UL)                   /*!< TMR11POL0 (Bitfield-Mask: 0x01)                       */
#define TIMER_CTRL11_TMR11CLR_Pos         (1UL)                     /*!< TMR11CLR (Bit 1)                                      */
#define TIMER_CTRL11_TMR11CLR_Msk         (0x2UL)                   /*!< TMR11CLR (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL11_TMR11EN_Pos          (0UL)                     /*!< TMR11EN (Bit 0)                                       */
#define TIMER_CTRL11_TMR11EN_Msk          (0x1UL)                   /*!< TMR11EN (Bitfield-Mask: 0x01)                         */
/* ========================================================  TIMER11  ======================================================== */
#define TIMER_TIMER11_TIMER11_Pos         (0UL)                     /*!< TIMER11 (Bit 0)                                       */
#define TIMER_TIMER11_TIMER11_Msk         (0xffffffffUL)            /*!< TIMER11 (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  TMR11CMP0  ======================================================= */
#define TIMER_TMR11CMP0_TMR11CMP0_Pos     (0UL)                     /*!< TMR11CMP0 (Bit 0)                                     */
#define TIMER_TMR11CMP0_TMR11CMP0_Msk     (0xffffffffUL)            /*!< TMR11CMP0 (Bitfield-Mask: 0xffffffff)                 */
/* =======================================================  TMR11CMP1  ======================================================= */
#define TIMER_TMR11CMP1_TMR11CMP1_Pos     (0UL)                     /*!< TMR11CMP1 (Bit 0)                                     */
#define TIMER_TMR11CMP1_TMR11CMP1_Msk     (0xffffffffUL)            /*!< TMR11CMP1 (Bitfield-Mask: 0xffffffff)                 */
/* ========================================================  MODE11  ========================================================= */
#define TIMER_MODE11_TMR11TRIGSEL_Pos     (8UL)                     /*!< TMR11TRIGSEL (Bit 8)                                  */
#define TIMER_MODE11_TMR11TRIGSEL_Msk     (0xff00UL)                /*!< TMR11TRIGSEL (Bitfield-Mask: 0xff)                    */
/* ======================================================  TMR11LMTVAL  ====================================================== */
#define TIMER_TMR11LMTVAL_TMR11LMTVAL_Pos (0UL)                     /*!< TMR11LMTVAL (Bit 0)                                   */
#define TIMER_TMR11LMTVAL_TMR11LMTVAL_Msk (0xffUL)                  /*!< TMR11LMTVAL (Bitfield-Mask: 0xff)                     */
/* ========================================================  CTRL12  ========================================================= */
#define TIMER_CTRL12_TMR12LMT_Pos         (24UL)                    /*!< TMR12LMT (Bit 24)                                     */
#define TIMER_CTRL12_TMR12LMT_Msk         (0xff000000UL)            /*!< TMR12LMT (Bitfield-Mask: 0xff)                        */
#define TIMER_CTRL12_TMR12TMODE_Pos       (16UL)                    /*!< TMR12TMODE (Bit 16)                                   */
#define TIMER_CTRL12_TMR12TMODE_Msk       (0x30000UL)               /*!< TMR12TMODE (Bitfield-Mask: 0x03)                      */
#define TIMER_CTRL12_TMR12CLK_Pos         (8UL)                     /*!< TMR12CLK (Bit 8)                                      */
#define TIMER_CTRL12_TMR12CLK_Msk         (0xff00UL)                /*!< TMR12CLK (Bitfield-Mask: 0xff)                        */
#define TIMER_CTRL12_TMR12FN_Pos          (4UL)                     /*!< TMR12FN (Bit 4)                                       */
#define TIMER_CTRL12_TMR12FN_Msk          (0xf0UL)                  /*!< TMR12FN (Bitfield-Mask: 0x0f)                         */
#define TIMER_CTRL12_TMR12POL1_Pos        (3UL)                     /*!< TMR12POL1 (Bit 3)                                     */
#define TIMER_CTRL12_TMR12POL1_Msk        (0x8UL)                   /*!< TMR12POL1 (Bitfield-Mask: 0x01)                       */
#define TIMER_CTRL12_TMR12POL0_Pos        (2UL)                     /*!< TMR12POL0 (Bit 2)                                     */
#define TIMER_CTRL12_TMR12POL0_Msk        (0x4UL)                   /*!< TMR12POL0 (Bitfield-Mask: 0x01)                       */
#define TIMER_CTRL12_TMR12CLR_Pos         (1UL)                     /*!< TMR12CLR (Bit 1)                                      */
#define TIMER_CTRL12_TMR12CLR_Msk         (0x2UL)                   /*!< TMR12CLR (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL12_TMR12EN_Pos          (0UL)                     /*!< TMR12EN (Bit 0)                                       */
#define TIMER_CTRL12_TMR12EN_Msk          (0x1UL)                   /*!< TMR12EN (Bitfield-Mask: 0x01)                         */
/* ========================================================  TIMER12  ======================================================== */
#define TIMER_TIMER12_TIMER12_Pos         (0UL)                     /*!< TIMER12 (Bit 0)                                       */
#define TIMER_TIMER12_TIMER12_Msk         (0xffffffffUL)            /*!< TIMER12 (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  TMR12CMP0  ======================================================= */
#define TIMER_TMR12CMP0_TMR12CMP0_Pos     (0UL)                     /*!< TMR12CMP0 (Bit 0)                                     */
#define TIMER_TMR12CMP0_TMR12CMP0_Msk     (0xffffffffUL)            /*!< TMR12CMP0 (Bitfield-Mask: 0xffffffff)                 */
/* =======================================================  TMR12CMP1  ======================================================= */
#define TIMER_TMR12CMP1_TMR12CMP1_Pos     (0UL)                     /*!< TMR12CMP1 (Bit 0)                                     */
#define TIMER_TMR12CMP1_TMR12CMP1_Msk     (0xffffffffUL)            /*!< TMR12CMP1 (Bitfield-Mask: 0xffffffff)                 */
/* ========================================================  MODE12  ========================================================= */
#define TIMER_MODE12_TMR12TRIGSEL_Pos     (8UL)                     /*!< TMR12TRIGSEL (Bit 8)                                  */
#define TIMER_MODE12_TMR12TRIGSEL_Msk     (0xff00UL)                /*!< TMR12TRIGSEL (Bitfield-Mask: 0xff)                    */
/* ======================================================  TMR12LMTVAL  ====================================================== */
#define TIMER_TMR12LMTVAL_TMR12LMTVAL_Pos (0UL)                     /*!< TMR12LMTVAL (Bit 0)                                   */
#define TIMER_TMR12LMTVAL_TMR12LMTVAL_Msk (0xffUL)                  /*!< TMR12LMTVAL (Bitfield-Mask: 0xff)                     */
/* ========================================================  CTRL13  ========================================================= */
#define TIMER_CTRL13_TMR13LMT_Pos         (24UL)                    /*!< TMR13LMT (Bit 24)                                     */
#define TIMER_CTRL13_TMR13LMT_Msk         (0xff000000UL)            /*!< TMR13LMT (Bitfield-Mask: 0xff)                        */
#define TIMER_CTRL13_TMR13TMODE_Pos       (16UL)                    /*!< TMR13TMODE (Bit 16)                                   */
#define TIMER_CTRL13_TMR13TMODE_Msk       (0x30000UL)               /*!< TMR13TMODE (Bitfield-Mask: 0x03)                      */
#define TIMER_CTRL13_TMR13CLK_Pos         (8UL)                     /*!< TMR13CLK (Bit 8)                                      */
#define TIMER_CTRL13_TMR13CLK_Msk         (0xff00UL)                /*!< TMR13CLK (Bitfield-Mask: 0xff)                        */
#define TIMER_CTRL13_TMR13FN_Pos          (4UL)                     /*!< TMR13FN (Bit 4)                                       */
#define TIMER_CTRL13_TMR13FN_Msk          (0xf0UL)                  /*!< TMR13FN (Bitfield-Mask: 0x0f)                         */
#define TIMER_CTRL13_TMR13POL1_Pos        (3UL)                     /*!< TMR13POL1 (Bit 3)                                     */
#define TIMER_CTRL13_TMR13POL1_Msk        (0x8UL)                   /*!< TMR13POL1 (Bitfield-Mask: 0x01)                       */
#define TIMER_CTRL13_TMR13POL0_Pos        (2UL)                     /*!< TMR13POL0 (Bit 2)                                     */
#define TIMER_CTRL13_TMR13POL0_Msk        (0x4UL)                   /*!< TMR13POL0 (Bitfield-Mask: 0x01)                       */
#define TIMER_CTRL13_TMR13CLR_Pos         (1UL)                     /*!< TMR13CLR (Bit 1)                                      */
#define TIMER_CTRL13_TMR13CLR_Msk         (0x2UL)                   /*!< TMR13CLR (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL13_TMR13EN_Pos          (0UL)                     /*!< TMR13EN (Bit 0)                                       */
#define TIMER_CTRL13_TMR13EN_Msk          (0x1UL)                   /*!< TMR13EN (Bitfield-Mask: 0x01)                         */
/* ========================================================  TIMER13  ======================================================== */
#define TIMER_TIMER13_TIMER13_Pos         (0UL)                     /*!< TIMER13 (Bit 0)                                       */
#define TIMER_TIMER13_TIMER13_Msk         (0xffffffffUL)            /*!< TIMER13 (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  TMR13CMP0  ======================================================= */
#define TIMER_TMR13CMP0_TMR13CMP0_Pos     (0UL)                     /*!< TMR13CMP0 (Bit 0)                                     */
#define TIMER_TMR13CMP0_TMR13CMP0_Msk     (0xffffffffUL)            /*!< TMR13CMP0 (Bitfield-Mask: 0xffffffff)                 */
/* =======================================================  TMR13CMP1  ======================================================= */
#define TIMER_TMR13CMP1_TMR13CMP1_Pos     (0UL)                     /*!< TMR13CMP1 (Bit 0)                                     */
#define TIMER_TMR13CMP1_TMR13CMP1_Msk     (0xffffffffUL)            /*!< TMR13CMP1 (Bitfield-Mask: 0xffffffff)                 */
/* ========================================================  MODE13  ========================================================= */
#define TIMER_MODE13_TMR13TRIGSEL_Pos     (8UL)                     /*!< TMR13TRIGSEL (Bit 8)                                  */
#define TIMER_MODE13_TMR13TRIGSEL_Msk     (0xff00UL)                /*!< TMR13TRIGSEL (Bitfield-Mask: 0xff)                    */
/* ======================================================  TMR13LMTVAL  ====================================================== */
#define TIMER_TMR13LMTVAL_TMR13LMTVAL_Pos (0UL)                     /*!< TMR13LMTVAL (Bit 0)                                   */
#define TIMER_TMR13LMTVAL_TMR13LMTVAL_Msk (0xffUL)                  /*!< TMR13LMTVAL (Bitfield-Mask: 0xff)                     */
/* ========================================================  CTRL14  ========================================================= */
#define TIMER_CTRL14_TMR14LMT_Pos         (24UL)                    /*!< TMR14LMT (Bit 24)                                     */
#define TIMER_CTRL14_TMR14LMT_Msk         (0xff000000UL)            /*!< TMR14LMT (Bitfield-Mask: 0xff)                        */
#define TIMER_CTRL14_TMR14TMODE_Pos       (16UL)                    /*!< TMR14TMODE (Bit 16)                                   */
#define TIMER_CTRL14_TMR14TMODE_Msk       (0x30000UL)               /*!< TMR14TMODE (Bitfield-Mask: 0x03)                      */
#define TIMER_CTRL14_TMR14CLK_Pos         (8UL)                     /*!< TMR14CLK (Bit 8)                                      */
#define TIMER_CTRL14_TMR14CLK_Msk         (0xff00UL)                /*!< TMR14CLK (Bitfield-Mask: 0xff)                        */
#define TIMER_CTRL14_TMR14FN_Pos          (4UL)                     /*!< TMR14FN (Bit 4)                                       */
#define TIMER_CTRL14_TMR14FN_Msk          (0xf0UL)                  /*!< TMR14FN (Bitfield-Mask: 0x0f)                         */
#define TIMER_CTRL14_TMR14POL1_Pos        (3UL)                     /*!< TMR14POL1 (Bit 3)                                     */
#define TIMER_CTRL14_TMR14POL1_Msk        (0x8UL)                   /*!< TMR14POL1 (Bitfield-Mask: 0x01)                       */
#define TIMER_CTRL14_TMR14POL0_Pos        (2UL)                     /*!< TMR14POL0 (Bit 2)                                     */
#define TIMER_CTRL14_TMR14POL0_Msk        (0x4UL)                   /*!< TMR14POL0 (Bitfield-Mask: 0x01)                       */
#define TIMER_CTRL14_TMR14CLR_Pos         (1UL)                     /*!< TMR14CLR (Bit 1)                                      */
#define TIMER_CTRL14_TMR14CLR_Msk         (0x2UL)                   /*!< TMR14CLR (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL14_TMR14EN_Pos          (0UL)                     /*!< TMR14EN (Bit 0)                                       */
#define TIMER_CTRL14_TMR14EN_Msk          (0x1UL)                   /*!< TMR14EN (Bitfield-Mask: 0x01)                         */
/* ========================================================  TIMER14  ======================================================== */
#define TIMER_TIMER14_TIMER14_Pos         (0UL)                     /*!< TIMER14 (Bit 0)                                       */
#define TIMER_TIMER14_TIMER14_Msk         (0xffffffffUL)            /*!< TIMER14 (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  TMR14CMP0  ======================================================= */
#define TIMER_TMR14CMP0_TMR14CMP0_Pos     (0UL)                     /*!< TMR14CMP0 (Bit 0)                                     */
#define TIMER_TMR14CMP0_TMR14CMP0_Msk     (0xffffffffUL)            /*!< TMR14CMP0 (Bitfield-Mask: 0xffffffff)                 */
/* =======================================================  TMR14CMP1  ======================================================= */
#define TIMER_TMR14CMP1_TMR14CMP1_Pos     (0UL)                     /*!< TMR14CMP1 (Bit 0)                                     */
#define TIMER_TMR14CMP1_TMR14CMP1_Msk     (0xffffffffUL)            /*!< TMR14CMP1 (Bitfield-Mask: 0xffffffff)                 */
/* ========================================================  MODE14  ========================================================= */
#define TIMER_MODE14_TMR14TRIGSEL_Pos     (8UL)                     /*!< TMR14TRIGSEL (Bit 8)                                  */
#define TIMER_MODE14_TMR14TRIGSEL_Msk     (0xff00UL)                /*!< TMR14TRIGSEL (Bitfield-Mask: 0xff)                    */
/* ======================================================  TMR14LMTVAL  ====================================================== */
#define TIMER_TMR14LMTVAL_TMR14LMTVAL_Pos (0UL)                     /*!< TMR14LMTVAL (Bit 0)                                   */
#define TIMER_TMR14LMTVAL_TMR14LMTVAL_Msk (0xffUL)                  /*!< TMR14LMTVAL (Bitfield-Mask: 0xff)                     */
/* ========================================================  CTRL15  ========================================================= */
#define TIMER_CTRL15_TMR15LMT_Pos         (24UL)                    /*!< TMR15LMT (Bit 24)                                     */
#define TIMER_CTRL15_TMR15LMT_Msk         (0xff000000UL)            /*!< TMR15LMT (Bitfield-Mask: 0xff)                        */
#define TIMER_CTRL15_TMR15TMODE_Pos       (16UL)                    /*!< TMR15TMODE (Bit 16)                                   */
#define TIMER_CTRL15_TMR15TMODE_Msk       (0x30000UL)               /*!< TMR15TMODE (Bitfield-Mask: 0x03)                      */
#define TIMER_CTRL15_TMR15CLK_Pos         (8UL)                     /*!< TMR15CLK (Bit 8)                                      */
#define TIMER_CTRL15_TMR15CLK_Msk         (0xff00UL)                /*!< TMR15CLK (Bitfield-Mask: 0xff)                        */
#define TIMER_CTRL15_TMR15FN_Pos          (4UL)                     /*!< TMR15FN (Bit 4)                                       */
#define TIMER_CTRL15_TMR15FN_Msk          (0xf0UL)                  /*!< TMR15FN (Bitfield-Mask: 0x0f)                         */
#define TIMER_CTRL15_TMR15POL1_Pos        (3UL)                     /*!< TMR15POL1 (Bit 3)                                     */
#define TIMER_CTRL15_TMR15POL1_Msk        (0x8UL)                   /*!< TMR15POL1 (Bitfield-Mask: 0x01)                       */
#define TIMER_CTRL15_TMR15POL0_Pos        (2UL)                     /*!< TMR15POL0 (Bit 2)                                     */
#define TIMER_CTRL15_TMR15POL0_Msk        (0x4UL)                   /*!< TMR15POL0 (Bitfield-Mask: 0x01)                       */
#define TIMER_CTRL15_TMR15CLR_Pos         (1UL)                     /*!< TMR15CLR (Bit 1)                                      */
#define TIMER_CTRL15_TMR15CLR_Msk         (0x2UL)                   /*!< TMR15CLR (Bitfield-Mask: 0x01)                        */
#define TIMER_CTRL15_TMR15EN_Pos          (0UL)                     /*!< TMR15EN (Bit 0)                                       */
#define TIMER_CTRL15_TMR15EN_Msk          (0x1UL)                   /*!< TMR15EN (Bitfield-Mask: 0x01)                         */
/* ========================================================  TIMER15  ======================================================== */
#define TIMER_TIMER15_TIMER15_Pos         (0UL)                     /*!< TIMER15 (Bit 0)                                       */
#define TIMER_TIMER15_TIMER15_Msk         (0xffffffffUL)            /*!< TIMER15 (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  TMR15CMP0  ======================================================= */
#define TIMER_TMR15CMP0_TMR15CMP0_Pos     (0UL)                     /*!< TMR15CMP0 (Bit 0)                                     */
#define TIMER_TMR15CMP0_TMR15CMP0_Msk     (0xffffffffUL)            /*!< TMR15CMP0 (Bitfield-Mask: 0xffffffff)                 */
/* =======================================================  TMR15CMP1  ======================================================= */
#define TIMER_TMR15CMP1_TMR15CMP1_Pos     (0UL)                     /*!< TMR15CMP1 (Bit 0)                                     */
#define TIMER_TMR15CMP1_TMR15CMP1_Msk     (0xffffffffUL)            /*!< TMR15CMP1 (Bitfield-Mask: 0xffffffff)                 */
/* ========================================================  MODE15  ========================================================= */
#define TIMER_MODE15_TMR15TRIGSEL_Pos     (8UL)                     /*!< TMR15TRIGSEL (Bit 8)                                  */
#define TIMER_MODE15_TMR15TRIGSEL_Msk     (0xff00UL)                /*!< TMR15TRIGSEL (Bitfield-Mask: 0xff)                    */
/* ======================================================  TMR15LMTVAL  ====================================================== */
#define TIMER_TMR15LMTVAL_TMR15LMTVAL_Pos (0UL)                     /*!< TMR15LMTVAL (Bit 0)                                   */
#define TIMER_TMR15LMTVAL_TMR15LMTVAL_Msk (0xffUL)                  /*!< TMR15LMTVAL (Bitfield-Mask: 0xff)                     */
/* ======================================================  TIMERSPARES  ====================================================== */
#define TIMER_TIMERSPARES_TMRSPARES_Pos   (0UL)                     /*!< TMRSPARES (Bit 0)                                     */
#define TIMER_TIMERSPARES_TMRSPARES_Msk   (0xffffffffUL)            /*!< TMRSPARES (Bitfield-Mask: 0xffffffff)                 */


/* =========================================================================================================================== */
/* ================                                           UART0                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  DR  =========================================================== */
#define UART0_DR_OEDATA_Pos               (11UL)                    /*!< OEDATA (Bit 11)                                       */
#define UART0_DR_OEDATA_Msk               (0x800UL)                 /*!< OEDATA (Bitfield-Mask: 0x01)                          */
#define UART0_DR_BEDATA_Pos               (10UL)                    /*!< BEDATA (Bit 10)                                       */
#define UART0_DR_BEDATA_Msk               (0x400UL)                 /*!< BEDATA (Bitfield-Mask: 0x01)                          */
#define UART0_DR_PEDATA_Pos               (9UL)                     /*!< PEDATA (Bit 9)                                        */
#define UART0_DR_PEDATA_Msk               (0x200UL)                 /*!< PEDATA (Bitfield-Mask: 0x01)                          */
#define UART0_DR_FEDATA_Pos               (8UL)                     /*!< FEDATA (Bit 8)                                        */
#define UART0_DR_FEDATA_Msk               (0x100UL)                 /*!< FEDATA (Bitfield-Mask: 0x01)                          */
#define UART0_DR_DATA_Pos                 (0UL)                     /*!< DATA (Bit 0)                                          */
#define UART0_DR_DATA_Msk                 (0xffUL)                  /*!< DATA (Bitfield-Mask: 0xff)                            */
/* ==========================================================  RSR  ========================================================== */
#define UART0_RSR_OESTAT_Pos              (3UL)                     /*!< OESTAT (Bit 3)                                        */
#define UART0_RSR_OESTAT_Msk              (0x8UL)                   /*!< OESTAT (Bitfield-Mask: 0x01)                          */
#define UART0_RSR_BESTAT_Pos              (2UL)                     /*!< BESTAT (Bit 2)                                        */
#define UART0_RSR_BESTAT_Msk              (0x4UL)                   /*!< BESTAT (Bitfield-Mask: 0x01)                          */
#define UART0_RSR_PESTAT_Pos              (1UL)                     /*!< PESTAT (Bit 1)                                        */
#define UART0_RSR_PESTAT_Msk              (0x2UL)                   /*!< PESTAT (Bitfield-Mask: 0x01)                          */
#define UART0_RSR_FESTAT_Pos              (0UL)                     /*!< FESTAT (Bit 0)                                        */
#define UART0_RSR_FESTAT_Msk              (0x1UL)                   /*!< FESTAT (Bitfield-Mask: 0x01)                          */
/* ==========================================================  FR  =========================================================== */
#define UART0_FR_TXBUSY_Pos               (8UL)                     /*!< TXBUSY (Bit 8)                                        */
#define UART0_FR_TXBUSY_Msk               (0x100UL)                 /*!< TXBUSY (Bitfield-Mask: 0x01)                          */
#define UART0_FR_TXFE_Pos                 (7UL)                     /*!< TXFE (Bit 7)                                          */
#define UART0_FR_TXFE_Msk                 (0x80UL)                  /*!< TXFE (Bitfield-Mask: 0x01)                            */
#define UART0_FR_RXFF_Pos                 (6UL)                     /*!< RXFF (Bit 6)                                          */
#define UART0_FR_RXFF_Msk                 (0x40UL)                  /*!< RXFF (Bitfield-Mask: 0x01)                            */
#define UART0_FR_TXFF_Pos                 (5UL)                     /*!< TXFF (Bit 5)                                          */
#define UART0_FR_TXFF_Msk                 (0x20UL)                  /*!< TXFF (Bitfield-Mask: 0x01)                            */
#define UART0_FR_RXFE_Pos                 (4UL)                     /*!< RXFE (Bit 4)                                          */
#define UART0_FR_RXFE_Msk                 (0x10UL)                  /*!< RXFE (Bitfield-Mask: 0x01)                            */
#define UART0_FR_BUSY_Pos                 (3UL)                     /*!< BUSY (Bit 3)                                          */
#define UART0_FR_BUSY_Msk                 (0x8UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
#define UART0_FR_DCD_Pos                  (2UL)                     /*!< DCD (Bit 2)                                           */
#define UART0_FR_DCD_Msk                  (0x4UL)                   /*!< DCD (Bitfield-Mask: 0x01)                             */
#define UART0_FR_DSR_Pos                  (1UL)                     /*!< DSR (Bit 1)                                           */
#define UART0_FR_DSR_Msk                  (0x2UL)                   /*!< DSR (Bitfield-Mask: 0x01)                             */
#define UART0_FR_CTS_Pos                  (0UL)                     /*!< CTS (Bit 0)                                           */
#define UART0_FR_CTS_Msk                  (0x1UL)                   /*!< CTS (Bitfield-Mask: 0x01)                             */
/* =========================================================  ILPR  ========================================================== */
#define UART0_ILPR_ILPDVSR_Pos            (0UL)                     /*!< ILPDVSR (Bit 0)                                       */
#define UART0_ILPR_ILPDVSR_Msk            (0xffUL)                  /*!< ILPDVSR (Bitfield-Mask: 0xff)                         */
/* =========================================================  IBRD  ========================================================== */
#define UART0_IBRD_DIVINT_Pos             (0UL)                     /*!< DIVINT (Bit 0)                                        */
#define UART0_IBRD_DIVINT_Msk             (0xffffUL)                /*!< DIVINT (Bitfield-Mask: 0xffff)                        */
/* =========================================================  FBRD  ========================================================== */
#define UART0_FBRD_DIVFRAC_Pos            (0UL)                     /*!< DIVFRAC (Bit 0)                                       */
#define UART0_FBRD_DIVFRAC_Msk            (0x3fUL)                  /*!< DIVFRAC (Bitfield-Mask: 0x3f)                         */
/* =========================================================  LCRH  ========================================================== */
#define UART0_LCRH_SPS_Pos                (7UL)                     /*!< SPS (Bit 7)                                           */
#define UART0_LCRH_SPS_Msk                (0x80UL)                  /*!< SPS (Bitfield-Mask: 0x01)                             */
#define UART0_LCRH_WLEN_Pos               (5UL)                     /*!< WLEN (Bit 5)                                          */
#define UART0_LCRH_WLEN_Msk               (0x60UL)                  /*!< WLEN (Bitfield-Mask: 0x03)                            */
#define UART0_LCRH_FEN_Pos                (4UL)                     /*!< FEN (Bit 4)                                           */
#define UART0_LCRH_FEN_Msk                (0x10UL)                  /*!< FEN (Bitfield-Mask: 0x01)                             */
#define UART0_LCRH_STP2_Pos               (3UL)                     /*!< STP2 (Bit 3)                                          */
#define UART0_LCRH_STP2_Msk               (0x8UL)                   /*!< STP2 (Bitfield-Mask: 0x01)                            */
#define UART0_LCRH_EPS_Pos                (2UL)                     /*!< EPS (Bit 2)                                           */
#define UART0_LCRH_EPS_Msk                (0x4UL)                   /*!< EPS (Bitfield-Mask: 0x01)                             */
#define UART0_LCRH_PEN_Pos                (1UL)                     /*!< PEN (Bit 1)                                           */
#define UART0_LCRH_PEN_Msk                (0x2UL)                   /*!< PEN (Bitfield-Mask: 0x01)                             */
#define UART0_LCRH_BRK_Pos                (0UL)                     /*!< BRK (Bit 0)                                           */
#define UART0_LCRH_BRK_Msk                (0x1UL)                   /*!< BRK (Bitfield-Mask: 0x01)                             */
/* ==========================================================  CR  =========================================================== */
#define UART0_CR_CTSEN_Pos                (15UL)                    /*!< CTSEN (Bit 15)                                        */
#define UART0_CR_CTSEN_Msk                (0x8000UL)                /*!< CTSEN (Bitfield-Mask: 0x01)                           */
#define UART0_CR_RTSEN_Pos                (14UL)                    /*!< RTSEN (Bit 14)                                        */
#define UART0_CR_RTSEN_Msk                (0x4000UL)                /*!< RTSEN (Bitfield-Mask: 0x01)                           */
#define UART0_CR_OUT2_Pos                 (13UL)                    /*!< OUT2 (Bit 13)                                         */
#define UART0_CR_OUT2_Msk                 (0x2000UL)                /*!< OUT2 (Bitfield-Mask: 0x01)                            */
#define UART0_CR_OUT1_Pos                 (12UL)                    /*!< OUT1 (Bit 12)                                         */
#define UART0_CR_OUT1_Msk                 (0x1000UL)                /*!< OUT1 (Bitfield-Mask: 0x01)                            */
#define UART0_CR_RTS_Pos                  (11UL)                    /*!< RTS (Bit 11)                                          */
#define UART0_CR_RTS_Msk                  (0x800UL)                 /*!< RTS (Bitfield-Mask: 0x01)                             */
#define UART0_CR_DTR_Pos                  (10UL)                    /*!< DTR (Bit 10)                                          */
#define UART0_CR_DTR_Msk                  (0x400UL)                 /*!< DTR (Bitfield-Mask: 0x01)                             */
#define UART0_CR_RXE_Pos                  (9UL)                     /*!< RXE (Bit 9)                                           */
#define UART0_CR_RXE_Msk                  (0x200UL)                 /*!< RXE (Bitfield-Mask: 0x01)                             */
#define UART0_CR_TXE_Pos                  (8UL)                     /*!< TXE (Bit 8)                                           */
#define UART0_CR_TXE_Msk                  (0x100UL)                 /*!< TXE (Bitfield-Mask: 0x01)                             */
#define UART0_CR_LBE_Pos                  (7UL)                     /*!< LBE (Bit 7)                                           */
#define UART0_CR_LBE_Msk                  (0x80UL)                  /*!< LBE (Bitfield-Mask: 0x01)                             */
#define UART0_CR_CLKSEL_Pos               (4UL)                     /*!< CLKSEL (Bit 4)                                        */
#define UART0_CR_CLKSEL_Msk               (0x70UL)                  /*!< CLKSEL (Bitfield-Mask: 0x07)                          */
#define UART0_CR_CLKEN_Pos                (3UL)                     /*!< CLKEN (Bit 3)                                         */
#define UART0_CR_CLKEN_Msk                (0x8UL)                   /*!< CLKEN (Bitfield-Mask: 0x01)                           */
#define UART0_CR_SIRLP_Pos                (2UL)                     /*!< SIRLP (Bit 2)                                         */
#define UART0_CR_SIRLP_Msk                (0x4UL)                   /*!< SIRLP (Bitfield-Mask: 0x01)                           */
#define UART0_CR_SIREN_Pos                (1UL)                     /*!< SIREN (Bit 1)                                         */
#define UART0_CR_SIREN_Msk                (0x2UL)                   /*!< SIREN (Bitfield-Mask: 0x01)                           */
#define UART0_CR_UARTEN_Pos               (0UL)                     /*!< UARTEN (Bit 0)                                        */
#define UART0_CR_UARTEN_Msk               (0x1UL)                   /*!< UARTEN (Bitfield-Mask: 0x01)                          */
/* =========================================================  IFLS  ========================================================== */
#define UART0_IFLS_RXIFLSEL_Pos           (3UL)                     /*!< RXIFLSEL (Bit 3)                                      */
#define UART0_IFLS_RXIFLSEL_Msk           (0x38UL)                  /*!< RXIFLSEL (Bitfield-Mask: 0x07)                        */
#define UART0_IFLS_TXIFLSEL_Pos           (0UL)                     /*!< TXIFLSEL (Bit 0)                                      */
#define UART0_IFLS_TXIFLSEL_Msk           (0x7UL)                   /*!< TXIFLSEL (Bitfield-Mask: 0x07)                        */
/* ==========================================================  IER  ========================================================== */
#define UART0_IER_OEIM_Pos                (10UL)                    /*!< OEIM (Bit 10)                                         */
#define UART0_IER_OEIM_Msk                (0x400UL)                 /*!< OEIM (Bitfield-Mask: 0x01)                            */
#define UART0_IER_BEIM_Pos                (9UL)                     /*!< BEIM (Bit 9)                                          */
#define UART0_IER_BEIM_Msk                (0x200UL)                 /*!< BEIM (Bitfield-Mask: 0x01)                            */
#define UART0_IER_PEIM_Pos                (8UL)                     /*!< PEIM (Bit 8)                                          */
#define UART0_IER_PEIM_Msk                (0x100UL)                 /*!< PEIM (Bitfield-Mask: 0x01)                            */
#define UART0_IER_FEIM_Pos                (7UL)                     /*!< FEIM (Bit 7)                                          */
#define UART0_IER_FEIM_Msk                (0x80UL)                  /*!< FEIM (Bitfield-Mask: 0x01)                            */
#define UART0_IER_RTIM_Pos                (6UL)                     /*!< RTIM (Bit 6)                                          */
#define UART0_IER_RTIM_Msk                (0x40UL)                  /*!< RTIM (Bitfield-Mask: 0x01)                            */
#define UART0_IER_TXIM_Pos                (5UL)                     /*!< TXIM (Bit 5)                                          */
#define UART0_IER_TXIM_Msk                (0x20UL)                  /*!< TXIM (Bitfield-Mask: 0x01)                            */
#define UART0_IER_RXIM_Pos                (4UL)                     /*!< RXIM (Bit 4)                                          */
#define UART0_IER_RXIM_Msk                (0x10UL)                  /*!< RXIM (Bitfield-Mask: 0x01)                            */
#define UART0_IER_DSRMIM_Pos              (3UL)                     /*!< DSRMIM (Bit 3)                                        */
#define UART0_IER_DSRMIM_Msk              (0x8UL)                   /*!< DSRMIM (Bitfield-Mask: 0x01)                          */
#define UART0_IER_DCDMIM_Pos              (2UL)                     /*!< DCDMIM (Bit 2)                                        */
#define UART0_IER_DCDMIM_Msk              (0x4UL)                   /*!< DCDMIM (Bitfield-Mask: 0x01)                          */
#define UART0_IER_CTSMIM_Pos              (1UL)                     /*!< CTSMIM (Bit 1)                                        */
#define UART0_IER_CTSMIM_Msk              (0x2UL)                   /*!< CTSMIM (Bitfield-Mask: 0x01)                          */
#define UART0_IER_TXCMPMIM_Pos            (0UL)                     /*!< TXCMPMIM (Bit 0)                                      */
#define UART0_IER_TXCMPMIM_Msk            (0x1UL)                   /*!< TXCMPMIM (Bitfield-Mask: 0x01)                        */
/* ==========================================================  IES  ========================================================== */
#define UART0_IES_OERIS_Pos               (10UL)                    /*!< OERIS (Bit 10)                                        */
#define UART0_IES_OERIS_Msk               (0x400UL)                 /*!< OERIS (Bitfield-Mask: 0x01)                           */
#define UART0_IES_BERIS_Pos               (9UL)                     /*!< BERIS (Bit 9)                                         */
#define UART0_IES_BERIS_Msk               (0x200UL)                 /*!< BERIS (Bitfield-Mask: 0x01)                           */
#define UART0_IES_PERIS_Pos               (8UL)                     /*!< PERIS (Bit 8)                                         */
#define UART0_IES_PERIS_Msk               (0x100UL)                 /*!< PERIS (Bitfield-Mask: 0x01)                           */
#define UART0_IES_FERIS_Pos               (7UL)                     /*!< FERIS (Bit 7)                                         */
#define UART0_IES_FERIS_Msk               (0x80UL)                  /*!< FERIS (Bitfield-Mask: 0x01)                           */
#define UART0_IES_RTRIS_Pos               (6UL)                     /*!< RTRIS (Bit 6)                                         */
#define UART0_IES_RTRIS_Msk               (0x40UL)                  /*!< RTRIS (Bitfield-Mask: 0x01)                           */
#define UART0_IES_TXRIS_Pos               (5UL)                     /*!< TXRIS (Bit 5)                                         */
#define UART0_IES_TXRIS_Msk               (0x20UL)                  /*!< TXRIS (Bitfield-Mask: 0x01)                           */
#define UART0_IES_RXRIS_Pos               (4UL)                     /*!< RXRIS (Bit 4)                                         */
#define UART0_IES_RXRIS_Msk               (0x10UL)                  /*!< RXRIS (Bitfield-Mask: 0x01)                           */
#define UART0_IES_DSRMRIS_Pos             (3UL)                     /*!< DSRMRIS (Bit 3)                                       */
#define UART0_IES_DSRMRIS_Msk             (0x8UL)                   /*!< DSRMRIS (Bitfield-Mask: 0x01)                         */
#define UART0_IES_DCDMRIS_Pos             (2UL)                     /*!< DCDMRIS (Bit 2)                                       */
#define UART0_IES_DCDMRIS_Msk             (0x4UL)                   /*!< DCDMRIS (Bitfield-Mask: 0x01)                         */
#define UART0_IES_CTSMRIS_Pos             (1UL)                     /*!< CTSMRIS (Bit 1)                                       */
#define UART0_IES_CTSMRIS_Msk             (0x2UL)                   /*!< CTSMRIS (Bitfield-Mask: 0x01)                         */
#define UART0_IES_TXCMPMRIS_Pos           (0UL)                     /*!< TXCMPMRIS (Bit 0)                                     */
#define UART0_IES_TXCMPMRIS_Msk           (0x1UL)                   /*!< TXCMPMRIS (Bitfield-Mask: 0x01)                       */
/* ==========================================================  MIS  ========================================================== */
#define UART0_MIS_OEMIS_Pos               (10UL)                    /*!< OEMIS (Bit 10)                                        */
#define UART0_MIS_OEMIS_Msk               (0x400UL)                 /*!< OEMIS (Bitfield-Mask: 0x01)                           */
#define UART0_MIS_BEMIS_Pos               (9UL)                     /*!< BEMIS (Bit 9)                                         */
#define UART0_MIS_BEMIS_Msk               (0x200UL)                 /*!< BEMIS (Bitfield-Mask: 0x01)                           */
#define UART0_MIS_PEMIS_Pos               (8UL)                     /*!< PEMIS (Bit 8)                                         */
#define UART0_MIS_PEMIS_Msk               (0x100UL)                 /*!< PEMIS (Bitfield-Mask: 0x01)                           */
#define UART0_MIS_FEMIS_Pos               (7UL)                     /*!< FEMIS (Bit 7)                                         */
#define UART0_MIS_FEMIS_Msk               (0x80UL)                  /*!< FEMIS (Bitfield-Mask: 0x01)                           */
#define UART0_MIS_RTMIS_Pos               (6UL)                     /*!< RTMIS (Bit 6)                                         */
#define UART0_MIS_RTMIS_Msk               (0x40UL)                  /*!< RTMIS (Bitfield-Mask: 0x01)                           */
#define UART0_MIS_TXMIS_Pos               (5UL)                     /*!< TXMIS (Bit 5)                                         */
#define UART0_MIS_TXMIS_Msk               (0x20UL)                  /*!< TXMIS (Bitfield-Mask: 0x01)                           */
#define UART0_MIS_RXMIS_Pos               (4UL)                     /*!< RXMIS (Bit 4)                                         */
#define UART0_MIS_RXMIS_Msk               (0x10UL)                  /*!< RXMIS (Bitfield-Mask: 0x01)                           */
#define UART0_MIS_DSRMMIS_Pos             (3UL)                     /*!< DSRMMIS (Bit 3)                                       */
#define UART0_MIS_DSRMMIS_Msk             (0x8UL)                   /*!< DSRMMIS (Bitfield-Mask: 0x01)                         */
#define UART0_MIS_DCDMMIS_Pos             (2UL)                     /*!< DCDMMIS (Bit 2)                                       */
#define UART0_MIS_DCDMMIS_Msk             (0x4UL)                   /*!< DCDMMIS (Bitfield-Mask: 0x01)                         */
#define UART0_MIS_CTSMMIS_Pos             (1UL)                     /*!< CTSMMIS (Bit 1)                                       */
#define UART0_MIS_CTSMMIS_Msk             (0x2UL)                   /*!< CTSMMIS (Bitfield-Mask: 0x01)                         */
#define UART0_MIS_TXCMPMMIS_Pos           (0UL)                     /*!< TXCMPMMIS (Bit 0)                                     */
#define UART0_MIS_TXCMPMMIS_Msk           (0x1UL)                   /*!< TXCMPMMIS (Bitfield-Mask: 0x01)                       */
/* ==========================================================  IEC  ========================================================== */
#define UART0_IEC_OEIC_Pos                (10UL)                    /*!< OEIC (Bit 10)                                         */
#define UART0_IEC_OEIC_Msk                (0x400UL)                 /*!< OEIC (Bitfield-Mask: 0x01)                            */
#define UART0_IEC_BEIC_Pos                (9UL)                     /*!< BEIC (Bit 9)                                          */
#define UART0_IEC_BEIC_Msk                (0x200UL)                 /*!< BEIC (Bitfield-Mask: 0x01)                            */
#define UART0_IEC_PEIC_Pos                (8UL)                     /*!< PEIC (Bit 8)                                          */
#define UART0_IEC_PEIC_Msk                (0x100UL)                 /*!< PEIC (Bitfield-Mask: 0x01)                            */
#define UART0_IEC_FEIC_Pos                (7UL)                     /*!< FEIC (Bit 7)                                          */
#define UART0_IEC_FEIC_Msk                (0x80UL)                  /*!< FEIC (Bitfield-Mask: 0x01)                            */
#define UART0_IEC_RTIC_Pos                (6UL)                     /*!< RTIC (Bit 6)                                          */
#define UART0_IEC_RTIC_Msk                (0x40UL)                  /*!< RTIC (Bitfield-Mask: 0x01)                            */
#define UART0_IEC_TXIC_Pos                (5UL)                     /*!< TXIC (Bit 5)                                          */
#define UART0_IEC_TXIC_Msk                (0x20UL)                  /*!< TXIC (Bitfield-Mask: 0x01)                            */
#define UART0_IEC_RXIC_Pos                (4UL)                     /*!< RXIC (Bit 4)                                          */
#define UART0_IEC_RXIC_Msk                (0x10UL)                  /*!< RXIC (Bitfield-Mask: 0x01)                            */
#define UART0_IEC_DSRMIC_Pos              (3UL)                     /*!< DSRMIC (Bit 3)                                        */
#define UART0_IEC_DSRMIC_Msk              (0x8UL)                   /*!< DSRMIC (Bitfield-Mask: 0x01)                          */
#define UART0_IEC_DCDMIC_Pos              (2UL)                     /*!< DCDMIC (Bit 2)                                        */
#define UART0_IEC_DCDMIC_Msk              (0x4UL)                   /*!< DCDMIC (Bitfield-Mask: 0x01)                          */
#define UART0_IEC_CTSMIC_Pos              (1UL)                     /*!< CTSMIC (Bit 1)                                        */
#define UART0_IEC_CTSMIC_Msk              (0x2UL)                   /*!< CTSMIC (Bitfield-Mask: 0x01)                          */
#define UART0_IEC_TXCMPMIC_Pos            (0UL)                     /*!< TXCMPMIC (Bit 0)                                      */
#define UART0_IEC_TXCMPMIC_Msk            (0x1UL)                   /*!< TXCMPMIC (Bitfield-Mask: 0x01)                        */


/* =========================================================================================================================== */
/* ================                                           VCOMP                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  CFG  ========================================================== */
#define VCOMP_CFG_LVLSEL_Pos              (16UL)                    /*!< LVLSEL (Bit 16)                                       */
#define VCOMP_CFG_LVLSEL_Msk              (0xf0000UL)               /*!< LVLSEL (Bitfield-Mask: 0x0f)                          */
#define VCOMP_CFG_NSEL_Pos                (8UL)                     /*!< NSEL (Bit 8)                                          */
#define VCOMP_CFG_NSEL_Msk                (0x300UL)                 /*!< NSEL (Bitfield-Mask: 0x03)                            */
#define VCOMP_CFG_PSEL_Pos                (0UL)                     /*!< PSEL (Bit 0)                                          */
#define VCOMP_CFG_PSEL_Msk                (0x3UL)                   /*!< PSEL (Bitfield-Mask: 0x03)                            */
/* =========================================================  STAT  ========================================================== */
#define VCOMP_STAT_PWDSTAT_Pos            (1UL)                     /*!< PWDSTAT (Bit 1)                                       */
#define VCOMP_STAT_PWDSTAT_Msk            (0x2UL)                   /*!< PWDSTAT (Bitfield-Mask: 0x01)                         */
#define VCOMP_STAT_CMPOUT_Pos             (0UL)                     /*!< CMPOUT (Bit 0)                                        */
#define VCOMP_STAT_CMPOUT_Msk             (0x1UL)                   /*!< CMPOUT (Bitfield-Mask: 0x01)                          */
/* ========================================================  PWDKEY  ========================================================= */
#define VCOMP_PWDKEY_PWDKEY_Pos           (0UL)                     /*!< PWDKEY (Bit 0)                                        */
#define VCOMP_PWDKEY_PWDKEY_Msk           (0xffffffffUL)            /*!< PWDKEY (Bitfield-Mask: 0xffffffff)                    */
/* =========================================================  INTEN  ========================================================= */
#define VCOMP_INTEN_OUTHI_Pos             (1UL)                     /*!< OUTHI (Bit 1)                                         */
#define VCOMP_INTEN_OUTHI_Msk             (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
#define VCOMP_INTEN_OUTLOW_Pos            (0UL)                     /*!< OUTLOW (Bit 0)                                        */
#define VCOMP_INTEN_OUTLOW_Msk            (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
/* ========================================================  INTSTAT  ======================================================== */
#define VCOMP_INTSTAT_OUTHI_Pos           (1UL)                     /*!< OUTHI (Bit 1)                                         */
#define VCOMP_INTSTAT_OUTHI_Msk           (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
#define VCOMP_INTSTAT_OUTLOW_Pos          (0UL)                     /*!< OUTLOW (Bit 0)                                        */
#define VCOMP_INTSTAT_OUTLOW_Msk          (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
/* ========================================================  INTCLR  ========================================================= */
#define VCOMP_INTCLR_OUTHI_Pos            (1UL)                     /*!< OUTHI (Bit 1)                                         */
#define VCOMP_INTCLR_OUTHI_Msk            (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
#define VCOMP_INTCLR_OUTLOW_Pos           (0UL)                     /*!< OUTLOW (Bit 0)                                        */
#define VCOMP_INTCLR_OUTLOW_Msk           (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
/* ========================================================  INTSET  ========================================================= */
#define VCOMP_INTSET_OUTHI_Pos            (1UL)                     /*!< OUTHI (Bit 1)                                         */
#define VCOMP_INTSET_OUTHI_Msk            (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
#define VCOMP_INTSET_OUTLOW_Pos           (0UL)                     /*!< OUTLOW (Bit 0)                                        */
#define VCOMP_INTSET_OUTLOW_Msk           (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */


/* =========================================================================================================================== */
/* ================                                            WDT                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CFG  ========================================================== */
#define WDT_CFG_CLKSEL_Pos                (24UL)                    /*!< CLKSEL (Bit 24)                                       */
#define WDT_CFG_CLKSEL_Msk                (0x7000000UL)             /*!< CLKSEL (Bitfield-Mask: 0x07)                          */
#define WDT_CFG_INTVAL_Pos                (16UL)                    /*!< INTVAL (Bit 16)                                       */
#define WDT_CFG_INTVAL_Msk                (0xff0000UL)              /*!< INTVAL (Bitfield-Mask: 0xff)                          */
#define WDT_CFG_RESVAL_Pos                (8UL)                     /*!< RESVAL (Bit 8)                                        */
#define WDT_CFG_RESVAL_Msk                (0xff00UL)                /*!< RESVAL (Bitfield-Mask: 0xff)                          */
#define WDT_CFG_RESEN_Pos                 (2UL)                     /*!< RESEN (Bit 2)                                         */
#define WDT_CFG_RESEN_Msk                 (0x4UL)                   /*!< RESEN (Bitfield-Mask: 0x01)                           */
#define WDT_CFG_INTEN_Pos                 (1UL)                     /*!< INTEN (Bit 1)                                         */
#define WDT_CFG_INTEN_Msk                 (0x2UL)                   /*!< INTEN (Bitfield-Mask: 0x01)                           */
#define WDT_CFG_WDTEN_Pos                 (0UL)                     /*!< WDTEN (Bit 0)                                         */
#define WDT_CFG_WDTEN_Msk                 (0x1UL)                   /*!< WDTEN (Bitfield-Mask: 0x01)                           */
/* =========================================================  RSTRT  ========================================================= */
#define WDT_RSTRT_RSTRT_Pos               (0UL)                     /*!< RSTRT (Bit 0)                                         */
#define WDT_RSTRT_RSTRT_Msk               (0xffUL)                  /*!< RSTRT (Bitfield-Mask: 0xff)                           */
/* =========================================================  LOCK  ========================================================== */
#define WDT_LOCK_LOCK_Pos                 (0UL)                     /*!< LOCK (Bit 0)                                          */
#define WDT_LOCK_LOCK_Msk                 (0xffUL)                  /*!< LOCK (Bitfield-Mask: 0xff)                            */
/* =========================================================  COUNT  ========================================================= */
#define WDT_COUNT_COUNT_Pos               (0UL)                     /*!< COUNT (Bit 0)                                         */
#define WDT_COUNT_COUNT_Msk               (0xffUL)                  /*!< COUNT (Bitfield-Mask: 0xff)                           */
/* =======================================================  WDTIEREN  ======================================================== */
#define WDT_WDTIEREN_WDTINT_Pos           (0UL)                     /*!< WDTINT (Bit 0)                                        */
#define WDT_WDTIEREN_WDTINT_Msk           (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
/* ======================================================  WDTIERSTAT  ======================================================= */
#define WDT_WDTIERSTAT_WDTINT_Pos         (0UL)                     /*!< WDTINT (Bit 0)                                        */
#define WDT_WDTIERSTAT_WDTINT_Msk         (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
/* =======================================================  WDTIERCLR  ======================================================= */
#define WDT_WDTIERCLR_WDTINT_Pos          (0UL)                     /*!< WDTINT (Bit 0)                                        */
#define WDT_WDTIERCLR_WDTINT_Msk          (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
/* =======================================================  WDTIERSET  ======================================================= */
#define WDT_WDTIERSET_WDTINT_Pos          (0UL)                     /*!< WDTINT (Bit 0)                                        */
#define WDT_WDTIERSET_WDTINT_Msk          (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */

/** @} */ /* End of group PosMask_peripherals */


/* =========================================================================================================================== */
/* ================                           Enumerated Values Peripheral Section                            ================ */
/* =========================================================================================================================== */


/** @addtogroup EnumValue_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                            ADC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CFG  ========================================================== */
/* ================================================  ADC CFG CLKSEL [24..25]  ================================================ */
typedef enum {                                  /*!< ADC_CFG_CLKSEL                                                            */
  ADC_CFG_CLKSEL_HFRC_48MHZ            = 0,     /*!< HFRC_48MHZ : This setting must not be used for CLKSEL for the
                                                     GP ADC even though it is the default setting. Software
                                                     must set CLKSEL to HFRC_24MHZ after any reset event and
                                                     before enabling the ADC.                                                  */
  ADC_CFG_CLKSEL_HFRC_48MHZ1           = 1,     /*!< HFRC_48MHZ1 : This setting must not be used for CLKSEL for the
                                                     GP ADC.                                                                   */
  ADC_CFG_CLKSEL_HFRC_24MHZ            = 2,     /*!< HFRC_24MHZ : HFRC clock at 24 MHz. This setting is the only
                                                     valid setting for the GP ADC.                                             */
  ADC_CFG_CLKSEL_HFRC2_48MHZ           = 3,     /*!< HFRC2_48MHZ : This setting must not be used for CLKSEL for the
                                                     GP ADC.                                                                   */
} ADC_CFG_CLKSEL_Enum;

/* ==============================================  ADC CFG RPTTRIGSEL [20..20]  ============================================== */
typedef enum {                                  /*!< ADC_CFG_RPTTRIGSEL                                                        */
  ADC_CFG_RPTTRIGSEL_TMR               = 0,     /*!< TMR : Trigger from on-chip timer.                                         */
  ADC_CFG_RPTTRIGSEL_INT               = 1,     /*!< INT : Trigger from ADC-internal timer.                                    */
} ADC_CFG_RPTTRIGSEL_Enum;

/* ===============================================  ADC CFG TRIGPOL [19..19]  ================================================ */
typedef enum {                                  /*!< ADC_CFG_TRIGPOL                                                           */
  ADC_CFG_TRIGPOL_RISING_EDGE          = 0,     /*!< RISING_EDGE : Trigger on rising edge.                                     */
  ADC_CFG_TRIGPOL_FALLING_EDGE         = 1,     /*!< FALLING_EDGE : Trigger on falling edge.                                   */
} ADC_CFG_TRIGPOL_Enum;

/* ===============================================  ADC CFG TRIGSEL [16..18]  ================================================ */
typedef enum {                                  /*!< ADC_CFG_TRIGSEL                                                           */
  ADC_CFG_TRIGSEL_EXT0                 = 0,     /*!< EXT0 : Off chip External Trigger0 (ADC_ET0)                               */
  ADC_CFG_TRIGSEL_EXT1                 = 1,     /*!< EXT1 : Off chip External Trigger1 (ADC_ET1)                               */
  ADC_CFG_TRIGSEL_EXT2                 = 2,     /*!< EXT2 : Off chip External Trigger2 (ADC_ET2)                               */
  ADC_CFG_TRIGSEL_EXT3                 = 3,     /*!< EXT3 : Off chip External Trigger3 (ADC_ET3)                               */
  ADC_CFG_TRIGSEL_VCOMP                = 4,     /*!< VCOMP : Voltage Comparator Output                                         */
  ADC_CFG_TRIGSEL_SWT                  = 7,     /*!< SWT : Software Trigger                                                    */
} ADC_CFG_TRIGSEL_Enum;

/* ==============================================  ADC CFG DFIFORDEN [12..12]  =============================================== */
typedef enum {                                  /*!< ADC_CFG_DFIFORDEN                                                         */
  ADC_CFG_DFIFORDEN_DIS                = 0,     /*!< DIS : Destructive Reads are prevented. Reads to the FIFOPR register
                                                     will not POP an entry off the FIFO.                                       */
  ADC_CFG_DFIFORDEN_EN                 = 1,     /*!< EN : Reads to the FIFOPR registger will automatically pop an
                                                     entry off the FIFO.                                                       */
} ADC_CFG_DFIFORDEN_Enum;

/* =================================================  ADC CFG CKMODE [4..4]  ================================================= */
typedef enum {                                  /*!< ADC_CFG_CKMODE                                                            */
  ADC_CFG_CKMODE_LPCKMODE              = 0,     /*!< LPCKMODE : Disable the clock between scans for LPMODE0. Set
                                                     LPCKMODE to 0x1 while configuring the ADC.                                */
  ADC_CFG_CKMODE_LLCKMODE              = 1,     /*!< LLCKMODE : Low Latency Clock Mode. When set, HFRC and the adc_clk
                                                     will remain on while in functioning in LPMODE0.                           */
} ADC_CFG_CKMODE_Enum;

/* =================================================  ADC CFG LPMODE [3..3]  ================================================= */
typedef enum {                                  /*!< ADC_CFG_LPMODE                                                            */
  ADC_CFG_LPMODE_MODE0                 = 0,     /*!< MODE0 : Low Power Mode 0. Leaves the ADC fully powered between
                                                     scans with minimum latency between a trigger event and
                                                     sample data collection.                                                   */
  ADC_CFG_LPMODE_MODE1                 = 1,     /*!< MODE1 : Low Power Mode 1. Powers down all circuity and clocks
                                                     associated with the ADC until the next trigger event. Between
                                                     scans, the reference buffer requires up to 50us of delay
                                                     from a scan trigger event before the conversion will commence
                                                     while operating in this mode.                                             */
} ADC_CFG_LPMODE_Enum;

/* =================================================  ADC CFG RPTEN [2..2]  ================================================== */
typedef enum {                                  /*!< ADC_CFG_RPTEN                                                             */
  ADC_CFG_RPTEN_SINGLE_SCAN            = 0,     /*!< SINGLE_SCAN : In Single Scan Mode, the ADC will complete a single
                                                     scan upon each trigger event.                                             */
  ADC_CFG_RPTEN_REPEATING_SCAN         = 1,     /*!< REPEATING_SCAN : In Repeating Scan Mode, the ADC will complete
                                                     its first scan upon the initial trigger event and all subsequent
                                                     scans will occur at regular intervals defined by the configuration
                                                     programmed for the CTTMRA3 timer or the ADC-internal timer
                                                     (see the RPTTRIGSEL field) until the timer is disabled
                                                     or the ADC is disabled. When disabling the ADC (setting
                                                     ADCEN to '0'), the RPTEN bit should be cleared.                           */
} ADC_CFG_RPTEN_Enum;

/* =================================================  ADC CFG ADCEN [0..0]  ================================================== */
typedef enum {                                  /*!< ADC_CFG_ADCEN                                                             */
  ADC_CFG_ADCEN_DIS                    = 0,     /*!< DIS : Disable the ADC module.                                             */
  ADC_CFG_ADCEN_EN                     = 1,     /*!< EN : Enable the ADC module.                                               */
} ADC_CFG_ADCEN_Enum;

/* =========================================================  STAT  ========================================================== */
/* ================================================  ADC STAT PWDSTAT [0..0]  ================================================ */
typedef enum {                                  /*!< ADC_STAT_PWDSTAT                                                          */
  ADC_STAT_PWDSTAT_ON                  = 0,     /*!< ON : Powered on.                                                          */
  ADC_STAT_PWDSTAT_POWERED_DOWN        = 1,     /*!< POWERED_DOWN : ADC Low Power Mode 1.                                      */
} ADC_STAT_PWDSTAT_Enum;

/* ==========================================================  SWT  ========================================================== */
/* ==================================================  ADC SWT SWT [0..7]  =================================================== */
typedef enum {                                  /*!< ADC_SWT_SWT                                                               */
  ADC_SWT_SWT_GEN_SW_TRIGGER           = 55,    /*!< GEN_SW_TRIGGER : Writing this value generates a software trigger.         */
  ADC_SWT_SWT_NO_SW_TRIGGER            = 0,     /*!< NO_SW_TRIGGER : Default value.                                            */
} ADC_SWT_SWT_Enum;

/* ========================================================  SL0CFG  ========================================================= */
/* ==============================================  ADC SL0CFG ADSEL0 [24..26]  =============================================== */
typedef enum {                                  /*!< ADC_SL0CFG_ADSEL0                                                         */
  ADC_SL0CFG_ADSEL0_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL0CFG_ADSEL0_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL0CFG_ADSEL0_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL0CFG_ADSEL0_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL0CFG_ADSEL0_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL0CFG_ADSEL0_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL0CFG_ADSEL0_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL0CFG_ADSEL0_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
                                                     divide module for this slot.                                              */
} ADC_SL0CFG_ADSEL0_Enum;

/* ==============================================  ADC SL0CFG PRMODE0 [16..17]  ============================================== */
typedef enum {                                  /*!< ADC_SL0CFG_PRMODE0                                                        */
  ADC_SL0CFG_PRMODE0_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
  ADC_SL0CFG_PRMODE0_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
  ADC_SL0CFG_PRMODE0_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
  ADC_SL0CFG_PRMODE0_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
} ADC_SL0CFG_PRMODE0_Enum;

/* ===============================================  ADC SL0CFG CHSEL0 [8..11]  =============================================== */
typedef enum {                                  /*!< ADC_SL0CFG_CHSEL0                                                         */
  ADC_SL0CFG_CHSEL0_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection.                              */
  ADC_SL0CFG_CHSEL0_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection.                              */
  ADC_SL0CFG_CHSEL0_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection.                              */
  ADC_SL0CFG_CHSEL0_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection.                              */
  ADC_SL0CFG_CHSEL0_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection.                              */
  ADC_SL0CFG_CHSEL0_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection.                              */
  ADC_SL0CFG_CHSEL0_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection.                              */
  ADC_SL0CFG_CHSEL0_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection.                              */
  ADC_SL0CFG_CHSEL0_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
  ADC_SL0CFG_CHSEL0_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
  ADC_SL0CFG_CHSEL0_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
} ADC_SL0CFG_CHSEL0_Enum;

/* ================================================  ADC SL0CFG WCEN0 [1..1]  ================================================ */
typedef enum {                                  /*!< ADC_SL0CFG_WCEN0                                                          */
  ADC_SL0CFG_WCEN0_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 0.                              */
  ADC_SL0CFG_WCEN0_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 0.                            */
} ADC_SL0CFG_WCEN0_Enum;

/* ================================================  ADC SL0CFG SLEN0 [0..0]  ================================================ */
typedef enum {                                  /*!< ADC_SL0CFG_SLEN0                                                          */
  ADC_SL0CFG_SLEN0_SLEN                = 1,     /*!< SLEN : Enable slot 0 for ADC conversions.                                 */
  ADC_SL0CFG_SLEN0_SLDIS               = 0,     /*!< SLDIS : Disable slot 0 for ADC conversions.                               */
} ADC_SL0CFG_SLEN0_Enum;

/* ========================================================  SL1CFG  ========================================================= */
/* ==============================================  ADC SL1CFG ADSEL1 [24..26]  =============================================== */
typedef enum {                                  /*!< ADC_SL1CFG_ADSEL1                                                         */
  ADC_SL1CFG_ADSEL1_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL1CFG_ADSEL1_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL1CFG_ADSEL1_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL1CFG_ADSEL1_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL1CFG_ADSEL1_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL1CFG_ADSEL1_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL1CFG_ADSEL1_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL1CFG_ADSEL1_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
                                                     divide module for this slot.                                              */
} ADC_SL1CFG_ADSEL1_Enum;

/* ==============================================  ADC SL1CFG PRMODE1 [16..17]  ============================================== */
typedef enum {                                  /*!< ADC_SL1CFG_PRMODE1                                                        */
  ADC_SL1CFG_PRMODE1_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
  ADC_SL1CFG_PRMODE1_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
  ADC_SL1CFG_PRMODE1_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
  ADC_SL1CFG_PRMODE1_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
} ADC_SL1CFG_PRMODE1_Enum;

/* ===============================================  ADC SL1CFG CHSEL1 [8..11]  =============================================== */
typedef enum {                                  /*!< ADC_SL1CFG_CHSEL1                                                         */
  ADC_SL1CFG_CHSEL1_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection.                              */
  ADC_SL1CFG_CHSEL1_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection.                              */
  ADC_SL1CFG_CHSEL1_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection.                              */
  ADC_SL1CFG_CHSEL1_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection.                              */
  ADC_SL1CFG_CHSEL1_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection.                              */
  ADC_SL1CFG_CHSEL1_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection.                              */
  ADC_SL1CFG_CHSEL1_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection.                              */
  ADC_SL1CFG_CHSEL1_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection.                              */
  ADC_SL1CFG_CHSEL1_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
  ADC_SL1CFG_CHSEL1_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
  ADC_SL1CFG_CHSEL1_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
} ADC_SL1CFG_CHSEL1_Enum;

/* ================================================  ADC SL1CFG WCEN1 [1..1]  ================================================ */
typedef enum {                                  /*!< ADC_SL1CFG_WCEN1                                                          */
  ADC_SL1CFG_WCEN1_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 1.                              */
  ADC_SL1CFG_WCEN1_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 1.                            */
} ADC_SL1CFG_WCEN1_Enum;

/* ================================================  ADC SL1CFG SLEN1 [0..0]  ================================================ */
typedef enum {                                  /*!< ADC_SL1CFG_SLEN1                                                          */
  ADC_SL1CFG_SLEN1_SLEN                = 1,     /*!< SLEN : Enable slot 1 for ADC conversions.                                 */
  ADC_SL1CFG_SLEN1_SLDIS               = 0,     /*!< SLDIS : Disable slot 1 for ADC conversions.                               */
} ADC_SL1CFG_SLEN1_Enum;

/* ========================================================  SL2CFG  ========================================================= */
/* ==============================================  ADC SL2CFG ADSEL2 [24..26]  =============================================== */
typedef enum {                                  /*!< ADC_SL2CFG_ADSEL2                                                         */
  ADC_SL2CFG_ADSEL2_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL2CFG_ADSEL2_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL2CFG_ADSEL2_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL2CFG_ADSEL2_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL2CFG_ADSEL2_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL2CFG_ADSEL2_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL2CFG_ADSEL2_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL2CFG_ADSEL2_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
                                                     divide module for this slot.                                              */
} ADC_SL2CFG_ADSEL2_Enum;

/* ==============================================  ADC SL2CFG PRMODE2 [16..17]  ============================================== */
typedef enum {                                  /*!< ADC_SL2CFG_PRMODE2                                                        */
  ADC_SL2CFG_PRMODE2_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
  ADC_SL2CFG_PRMODE2_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
  ADC_SL2CFG_PRMODE2_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
  ADC_SL2CFG_PRMODE2_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
} ADC_SL2CFG_PRMODE2_Enum;

/* ===============================================  ADC SL2CFG CHSEL2 [8..11]  =============================================== */
typedef enum {                                  /*!< ADC_SL2CFG_CHSEL2                                                         */
  ADC_SL2CFG_CHSEL2_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection.                              */
  ADC_SL2CFG_CHSEL2_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection.                              */
  ADC_SL2CFG_CHSEL2_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection.                              */
  ADC_SL2CFG_CHSEL2_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection.                              */
  ADC_SL2CFG_CHSEL2_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection.                              */
  ADC_SL2CFG_CHSEL2_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection.                              */
  ADC_SL2CFG_CHSEL2_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection.                              */
  ADC_SL2CFG_CHSEL2_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection.                              */
  ADC_SL2CFG_CHSEL2_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
  ADC_SL2CFG_CHSEL2_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
  ADC_SL2CFG_CHSEL2_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
} ADC_SL2CFG_CHSEL2_Enum;

/* ================================================  ADC SL2CFG WCEN2 [1..1]  ================================================ */
typedef enum {                                  /*!< ADC_SL2CFG_WCEN2                                                          */
  ADC_SL2CFG_WCEN2_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 2.                              */
  ADC_SL2CFG_WCEN2_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 2.                            */
} ADC_SL2CFG_WCEN2_Enum;

/* ================================================  ADC SL2CFG SLEN2 [0..0]  ================================================ */
typedef enum {                                  /*!< ADC_SL2CFG_SLEN2                                                          */
  ADC_SL2CFG_SLEN2_SLEN                = 1,     /*!< SLEN : Enable slot 2 for ADC conversions.                                 */
  ADC_SL2CFG_SLEN2_SLDIS               = 0,     /*!< SLDIS : Disable slot 2 for ADC conversions.                               */
} ADC_SL2CFG_SLEN2_Enum;

/* ========================================================  SL3CFG  ========================================================= */
/* ==============================================  ADC SL3CFG ADSEL3 [24..26]  =============================================== */
typedef enum {                                  /*!< ADC_SL3CFG_ADSEL3                                                         */
  ADC_SL3CFG_ADSEL3_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL3CFG_ADSEL3_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL3CFG_ADSEL3_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL3CFG_ADSEL3_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL3CFG_ADSEL3_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL3CFG_ADSEL3_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL3CFG_ADSEL3_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL3CFG_ADSEL3_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
                                                     divide module for this slot.                                              */
} ADC_SL3CFG_ADSEL3_Enum;

/* ==============================================  ADC SL3CFG PRMODE3 [16..17]  ============================================== */
typedef enum {                                  /*!< ADC_SL3CFG_PRMODE3                                                        */
  ADC_SL3CFG_PRMODE3_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
  ADC_SL3CFG_PRMODE3_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
  ADC_SL3CFG_PRMODE3_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
  ADC_SL3CFG_PRMODE3_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
} ADC_SL3CFG_PRMODE3_Enum;

/* ===============================================  ADC SL3CFG CHSEL3 [8..11]  =============================================== */
typedef enum {                                  /*!< ADC_SL3CFG_CHSEL3                                                         */
  ADC_SL3CFG_CHSEL3_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection.                              */
  ADC_SL3CFG_CHSEL3_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection.                              */
  ADC_SL3CFG_CHSEL3_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection.                              */
  ADC_SL3CFG_CHSEL3_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection.                              */
  ADC_SL3CFG_CHSEL3_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection.                              */
  ADC_SL3CFG_CHSEL3_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection.                              */
  ADC_SL3CFG_CHSEL3_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection.                              */
  ADC_SL3CFG_CHSEL3_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection.                              */
  ADC_SL3CFG_CHSEL3_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
  ADC_SL3CFG_CHSEL3_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
  ADC_SL3CFG_CHSEL3_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
} ADC_SL3CFG_CHSEL3_Enum;

/* ================================================  ADC SL3CFG WCEN3 [1..1]  ================================================ */
typedef enum {                                  /*!< ADC_SL3CFG_WCEN3                                                          */
  ADC_SL3CFG_WCEN3_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 3.                              */
  ADC_SL3CFG_WCEN3_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 3.                            */
} ADC_SL3CFG_WCEN3_Enum;

/* ================================================  ADC SL3CFG SLEN3 [0..0]  ================================================ */
typedef enum {                                  /*!< ADC_SL3CFG_SLEN3                                                          */
  ADC_SL3CFG_SLEN3_SLEN                = 1,     /*!< SLEN : Enable slot 3 for ADC conversions.                                 */
  ADC_SL3CFG_SLEN3_SLDIS               = 0,     /*!< SLDIS : Disable slot 3 for ADC conversions.                               */
} ADC_SL3CFG_SLEN3_Enum;

/* ========================================================  SL4CFG  ========================================================= */
/* ==============================================  ADC SL4CFG ADSEL4 [24..26]  =============================================== */
typedef enum {                                  /*!< ADC_SL4CFG_ADSEL4                                                         */
  ADC_SL4CFG_ADSEL4_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL4CFG_ADSEL4_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL4CFG_ADSEL4_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL4CFG_ADSEL4_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL4CFG_ADSEL4_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL4CFG_ADSEL4_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL4CFG_ADSEL4_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL4CFG_ADSEL4_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
                                                     divide module for this slot.                                              */
} ADC_SL4CFG_ADSEL4_Enum;

/* ==============================================  ADC SL4CFG PRMODE4 [16..17]  ============================================== */
typedef enum {                                  /*!< ADC_SL4CFG_PRMODE4                                                        */
  ADC_SL4CFG_PRMODE4_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
  ADC_SL4CFG_PRMODE4_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
  ADC_SL4CFG_PRMODE4_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
  ADC_SL4CFG_PRMODE4_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
} ADC_SL4CFG_PRMODE4_Enum;

/* ===============================================  ADC SL4CFG CHSEL4 [8..11]  =============================================== */
typedef enum {                                  /*!< ADC_SL4CFG_CHSEL4                                                         */
  ADC_SL4CFG_CHSEL4_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection.                              */
  ADC_SL4CFG_CHSEL4_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection.                              */
  ADC_SL4CFG_CHSEL4_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection.                              */
  ADC_SL4CFG_CHSEL4_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection.                              */
  ADC_SL4CFG_CHSEL4_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection.                              */
  ADC_SL4CFG_CHSEL4_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection.                              */
  ADC_SL4CFG_CHSEL4_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection.                              */
  ADC_SL4CFG_CHSEL4_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection.                              */
  ADC_SL4CFG_CHSEL4_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
  ADC_SL4CFG_CHSEL4_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
  ADC_SL4CFG_CHSEL4_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
} ADC_SL4CFG_CHSEL4_Enum;

/* ================================================  ADC SL4CFG WCEN4 [1..1]  ================================================ */
typedef enum {                                  /*!< ADC_SL4CFG_WCEN4                                                          */
  ADC_SL4CFG_WCEN4_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 4.                              */
  ADC_SL4CFG_WCEN4_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 4.                            */
} ADC_SL4CFG_WCEN4_Enum;

/* ================================================  ADC SL4CFG SLEN4 [0..0]  ================================================ */
typedef enum {                                  /*!< ADC_SL4CFG_SLEN4                                                          */
  ADC_SL4CFG_SLEN4_SLEN                = 1,     /*!< SLEN : Enable slot 4 for ADC conversions.                                 */
  ADC_SL4CFG_SLEN4_SLDIS               = 0,     /*!< SLDIS : Disable slot 4 for ADC conversions.                               */
} ADC_SL4CFG_SLEN4_Enum;

/* ========================================================  SL5CFG  ========================================================= */
/* ==============================================  ADC SL5CFG ADSEL5 [24..26]  =============================================== */
typedef enum {                                  /*!< ADC_SL5CFG_ADSEL5                                                         */
  ADC_SL5CFG_ADSEL5_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL5CFG_ADSEL5_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL5CFG_ADSEL5_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL5CFG_ADSEL5_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL5CFG_ADSEL5_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL5CFG_ADSEL5_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL5CFG_ADSEL5_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL5CFG_ADSEL5_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
                                                     divide module for this slot.                                              */
} ADC_SL5CFG_ADSEL5_Enum;

/* ==============================================  ADC SL5CFG PRMODE5 [16..17]  ============================================== */
typedef enum {                                  /*!< ADC_SL5CFG_PRMODE5                                                        */
  ADC_SL5CFG_PRMODE5_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
  ADC_SL5CFG_PRMODE5_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
  ADC_SL5CFG_PRMODE5_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
  ADC_SL5CFG_PRMODE5_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
} ADC_SL5CFG_PRMODE5_Enum;

/* ===============================================  ADC SL5CFG CHSEL5 [8..11]  =============================================== */
typedef enum {                                  /*!< ADC_SL5CFG_CHSEL5                                                         */
  ADC_SL5CFG_CHSEL5_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection.                              */
  ADC_SL5CFG_CHSEL5_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection.                              */
  ADC_SL5CFG_CHSEL5_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection.                              */
  ADC_SL5CFG_CHSEL5_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection.                              */
  ADC_SL5CFG_CHSEL5_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection.                              */
  ADC_SL5CFG_CHSEL5_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection.                              */
  ADC_SL5CFG_CHSEL5_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection.                              */
  ADC_SL5CFG_CHSEL5_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection.                              */
  ADC_SL5CFG_CHSEL5_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
  ADC_SL5CFG_CHSEL5_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
  ADC_SL5CFG_CHSEL5_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
} ADC_SL5CFG_CHSEL5_Enum;

/* ================================================  ADC SL5CFG WCEN5 [1..1]  ================================================ */
typedef enum {                                  /*!< ADC_SL5CFG_WCEN5                                                          */
  ADC_SL5CFG_WCEN5_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 5.                              */
  ADC_SL5CFG_WCEN5_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 5.                            */
} ADC_SL5CFG_WCEN5_Enum;

/* ================================================  ADC SL5CFG SLEN5 [0..0]  ================================================ */
typedef enum {                                  /*!< ADC_SL5CFG_SLEN5                                                          */
  ADC_SL5CFG_SLEN5_SLEN                = 1,     /*!< SLEN : Enable slot 5 for ADC conversions.                                 */
  ADC_SL5CFG_SLEN5_SLDIS               = 0,     /*!< SLDIS : Disable slot 5 for ADC conversions.                               */
} ADC_SL5CFG_SLEN5_Enum;

/* ========================================================  SL6CFG  ========================================================= */
/* ==============================================  ADC SL6CFG ADSEL6 [24..26]  =============================================== */
typedef enum {                                  /*!< ADC_SL6CFG_ADSEL6                                                         */
  ADC_SL6CFG_ADSEL6_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL6CFG_ADSEL6_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL6CFG_ADSEL6_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL6CFG_ADSEL6_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL6CFG_ADSEL6_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL6CFG_ADSEL6_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL6CFG_ADSEL6_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL6CFG_ADSEL6_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
                                                     divide module for this slot.                                              */
} ADC_SL6CFG_ADSEL6_Enum;

/* ==============================================  ADC SL6CFG PRMODE6 [16..17]  ============================================== */
typedef enum {                                  /*!< ADC_SL6CFG_PRMODE6                                                        */
  ADC_SL6CFG_PRMODE6_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
  ADC_SL6CFG_PRMODE6_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
  ADC_SL6CFG_PRMODE6_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
  ADC_SL6CFG_PRMODE6_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
} ADC_SL6CFG_PRMODE6_Enum;

/* ===============================================  ADC SL6CFG CHSEL6 [8..11]  =============================================== */
typedef enum {                                  /*!< ADC_SL6CFG_CHSEL6                                                         */
  ADC_SL6CFG_CHSEL6_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection.                              */
  ADC_SL6CFG_CHSEL6_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection.                              */
  ADC_SL6CFG_CHSEL6_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection.                              */
  ADC_SL6CFG_CHSEL6_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection.                              */
  ADC_SL6CFG_CHSEL6_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection.                              */
  ADC_SL6CFG_CHSEL6_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection.                              */
  ADC_SL6CFG_CHSEL6_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection.                              */
  ADC_SL6CFG_CHSEL6_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection.                              */
  ADC_SL6CFG_CHSEL6_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
  ADC_SL6CFG_CHSEL6_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
  ADC_SL6CFG_CHSEL6_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
} ADC_SL6CFG_CHSEL6_Enum;

/* ================================================  ADC SL6CFG WCEN6 [1..1]  ================================================ */
typedef enum {                                  /*!< ADC_SL6CFG_WCEN6                                                          */
  ADC_SL6CFG_WCEN6_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 6.                              */
  ADC_SL6CFG_WCEN6_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 6.                            */
} ADC_SL6CFG_WCEN6_Enum;

/* ================================================  ADC SL6CFG SLEN6 [0..0]  ================================================ */
typedef enum {                                  /*!< ADC_SL6CFG_SLEN6                                                          */
  ADC_SL6CFG_SLEN6_SLEN                = 1,     /*!< SLEN : Enable slot 6 for ADC conversions.                                 */
  ADC_SL6CFG_SLEN6_SLDIS               = 0,     /*!< SLDIS : Disable slot 6 for ADC conversions.                               */
} ADC_SL6CFG_SLEN6_Enum;

/* ========================================================  SL7CFG  ========================================================= */
/* ==============================================  ADC SL7CFG ADSEL7 [24..26]  =============================================== */
typedef enum {                                  /*!< ADC_SL7CFG_ADSEL7                                                         */
  ADC_SL7CFG_ADSEL7_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL7CFG_ADSEL7_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL7CFG_ADSEL7_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL7CFG_ADSEL7_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
                                                     module for this slot.                                                     */
  ADC_SL7CFG_ADSEL7_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL7CFG_ADSEL7_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL7CFG_ADSEL7_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
                                                     divide module for this slot.                                              */
  ADC_SL7CFG_ADSEL7_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
                                                     divide module for this slot.                                              */
} ADC_SL7CFG_ADSEL7_Enum;

/* ==============================================  ADC SL7CFG PRMODE7 [16..17]  ============================================== */
typedef enum {                                  /*!< ADC_SL7CFG_PRMODE7                                                        */
  ADC_SL7CFG_PRMODE7_P12B0             = 0,     /*!< P12B0 : 12-bit precision mode                                             */
  ADC_SL7CFG_PRMODE7_P12B1             = 1,     /*!< P12B1 : 12-bit precision mode                                             */
  ADC_SL7CFG_PRMODE7_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
  ADC_SL7CFG_PRMODE7_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
} ADC_SL7CFG_PRMODE7_Enum;

/* ===============================================  ADC SL7CFG CHSEL7 [8..11]  =============================================== */
typedef enum {                                  /*!< ADC_SL7CFG_CHSEL7                                                         */
  ADC_SL7CFG_CHSEL7_SE0                = 0,     /*!< SE0 : Single ended external GPIO connection.                              */
  ADC_SL7CFG_CHSEL7_SE1                = 1,     /*!< SE1 : Single ended external GPIO connection.                              */
  ADC_SL7CFG_CHSEL7_SE2                = 2,     /*!< SE2 : Single ended external GPIO connection.                              */
  ADC_SL7CFG_CHSEL7_SE3                = 3,     /*!< SE3 : Single ended external GPIO connection.                              */
  ADC_SL7CFG_CHSEL7_SE4                = 4,     /*!< SE4 : Single ended external GPIO connection.                              */
  ADC_SL7CFG_CHSEL7_SE5                = 5,     /*!< SE5 : Single ended external GPIO connection.                              */
  ADC_SL7CFG_CHSEL7_SE6                = 6,     /*!< SE6 : Single ended external GPIO connection.                              */
  ADC_SL7CFG_CHSEL7_SE7                = 7,     /*!< SE7 : Single ended external GPIO connection.                              */
  ADC_SL7CFG_CHSEL7_TEMP               = 8,     /*!< TEMP : Internal temperature sensor.                                       */
  ADC_SL7CFG_CHSEL7_BATT               = 9,     /*!< BATT : Internal voltage divide-by-3 connection.                           */
  ADC_SL7CFG_CHSEL7_VSS                = 11,    /*!< VSS : Input VSS.                                                          */
} ADC_SL7CFG_CHSEL7_Enum;

/* ================================================  ADC SL7CFG WCEN7 [1..1]  ================================================ */
typedef enum {                                  /*!< ADC_SL7CFG_WCEN7                                                          */
  ADC_SL7CFG_WCEN7_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 7.                              */
  ADC_SL7CFG_WCEN7_WCDIS               = 0,     /*!< WCDIS : Disable the window compare for slot 7.                            */
} ADC_SL7CFG_WCEN7_Enum;

/* ================================================  ADC SL7CFG SLEN7 [0..0]  ================================================ */
typedef enum {                                  /*!< ADC_SL7CFG_SLEN7                                                          */
  ADC_SL7CFG_SLEN7_SLEN                = 1,     /*!< SLEN : Enable slot 7 for ADC conversions.                                 */
  ADC_SL7CFG_SLEN7_SLDIS               = 0,     /*!< SLDIS : Disable slot 7 for ADC conversions.                               */
} ADC_SL7CFG_SLEN7_Enum;

/* =========================================================  WULIM  ========================================================= */
/* =========================================================  WLLIM  ========================================================= */
/* ========================================================  SCWLIM  ========================================================= */
/* =========================================================  FIFO  ========================================================== */
/* ========================================================  FIFOPR  ========================================================= */
/* =====================================================  INTTRIGTIMER  ====================================================== */
/* ===========================================  ADC INTTRIGTIMER TIMEREN [31..31]  =========================================== */
typedef enum {                                  /*!< ADC_INTTRIGTIMER_TIMEREN                                                  */
  ADC_INTTRIGTIMER_TIMEREN_DIS         = 0,     /*!< DIS : Disable the ADC-internal trigger timer.                             */
  ADC_INTTRIGTIMER_TIMEREN_EN          = 1,     /*!< EN : Enable the ADC-internal trigger timer.                               */
} ADC_INTTRIGTIMER_TIMEREN_Enum;

/* =========================================================  ZXCFG  ========================================================= */
/* =========================================================  ZXLIM  ========================================================= */
/* ========================================================  GAINCFG  ======================================================== */
/* =============================================  ADC GAINCFG UPDATEMODE [4..4]  ============================================= */
typedef enum {                                  /*!< ADC_GAINCFG_UPDATEMODE                                                    */
  ADC_GAINCFG_UPDATEMODE_IMMED         = 0,     /*!< IMMED : Immediate update mode. Once gain is written, it is immediately
                                                     encoded and provided to the PGA.                                          */
  ADC_GAINCFG_UPDATEMODE_ZX            = 1,     /*!< ZX : Update gain only at detected zero crossing as configured
                                                     by ZX registers.                                                          */
} ADC_GAINCFG_UPDATEMODE_Enum;

/* =========================================================  GAIN  ========================================================== */
/* ========================================================  SATCFG  ========================================================= */
/* ========================================================  SATLIM  ========================================================= */
/* ========================================================  SATMAX  ========================================================= */
/* ========================================================  SATCLR  ========================================================= */
/* ========================================================  CALCTRL  ======================================================== */
/* =========================================================  INTEN  ========================================================= */
/* ===============================================  ADC INTEN SATCB [11..11]  ================================================ */
typedef enum {                                  /*!< ADC_INTEN_SATCB                                                           */
  ADC_INTEN_SATCB_SATCBINT             = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
                                                     occurred on either slot 2 or 3 (channel B)                                */
  ADC_INTEN_SATCB_NONSATCBINT          = 0,     /*!< NONSATCBINT : No-Saturation                                               */
} ADC_INTEN_SATCB_Enum;

/* ===============================================  ADC INTEN SATCA [10..10]  ================================================ */
typedef enum {                                  /*!< ADC_INTEN_SATCA                                                           */
  ADC_INTEN_SATCA_SATCAINT             = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
                                                     occurred on either slot 0 or 1 (channel A)                                */
  ADC_INTEN_SATCA_NONSATCAINT          = 0,     /*!< NONSATCAINT : No Saturation                                               */
} ADC_INTEN_SATCA_Enum;

/* =================================================  ADC INTEN ZXCB [9..9]  ================================================= */
typedef enum {                                  /*!< ADC_INTEN_ZXCB                                                            */
  ADC_INTEN_ZXCB_ZXCBINT               = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
                                                     occurred on either slot 2 or 3 (channel B)                                */
  ADC_INTEN_ZXCB_NONZXCBINT            = 0,     /*!< NONZXCBINT : Non Zero Crossing                                            */
} ADC_INTEN_ZXCB_Enum;

/* =================================================  ADC INTEN ZXCA [8..8]  ================================================= */
typedef enum {                                  /*!< ADC_INTEN_ZXCA                                                            */
  ADC_INTEN_ZXCA_ZXCAINT               = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
                                                     occurred on either slot 0 or 1 (channel A)                                */
  ADC_INTEN_ZXCA_NONZXCAINT            = 0,     /*!< NONZXCAINT : Non Zero Crossing                                            */
} ADC_INTEN_ZXCA_Enum;

/* =================================================  ADC INTEN DERR [7..7]  ================================================= */
typedef enum {                                  /*!< ADC_INTEN_DERR                                                            */
  ADC_INTEN_DERR_DMAERROR              = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
  ADC_INTEN_DERR_NODMAERROR            = 0,     /*!< NODMAERROR : DMA Error Condition did not Occurred                         */
} ADC_INTEN_DERR_Enum;

/* =================================================  ADC INTEN DCMP [6..6]  ================================================= */
typedef enum {                                  /*!< ADC_INTEN_DCMP                                                            */
  ADC_INTEN_DCMP_DMACOMPLETE           = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
  ADC_INTEN_DCMP_DMAON                 = 0,     /*!< DMAON : DMA completion is pending or not triggered.                       */
} ADC_INTEN_DCMP_Enum;

/* ================================================  ADC INTEN WCINC [5..5]  ================================================= */
typedef enum {                                  /*!< ADC_INTEN_WCINC                                                           */
  ADC_INTEN_WCINC_WCINCINT             = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
  ADC_INTEN_WCINC_WCINCNOINT           = 0,     /*!< WCINCNOINT : Not a Window comparator voltage incursion interrupt.         */
} ADC_INTEN_WCINC_Enum;

/* ================================================  ADC INTEN WCEXC [4..4]  ================================================= */
typedef enum {                                  /*!< ADC_INTEN_WCEXC                                                           */
  ADC_INTEN_WCEXC_WCEXCINT             = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
  ADC_INTEN_WCEXC_WCEXCNOINT           = 0,     /*!< WCEXCNOINT : Not a Window comparator voltage excursion interrupt.         */
} ADC_INTEN_WCEXC_Enum;

/* ===============================================  ADC INTEN FIFOOVR2 [3..3]  =============================================== */
typedef enum {                                  /*!< ADC_INTEN_FIFOOVR2                                                        */
  ADC_INTEN_FIFOOVR2_FIFOFULLINT       = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
  ADC_INTEN_FIFOOVR2_FIFOFULLNOINT     = 0,     /*!< FIFOFULLNOINT : Not a FIFO 100 percent full interrupt.                    */
} ADC_INTEN_FIFOOVR2_Enum;

/* ===============================================  ADC INTEN FIFOOVR1 [2..2]  =============================================== */
typedef enum {                                  /*!< ADC_INTEN_FIFOOVR1                                                        */
  ADC_INTEN_FIFOOVR1_FIFO75INT         = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
  ADC_INTEN_FIFOOVR1_FIFO75NOINT       = 0,     /*!< FIFO75NOINT : Not FIFO 75 percent full interrupt.                         */
} ADC_INTEN_FIFOOVR1_Enum;

/* ================================================  ADC INTEN SCNCMP [1..1]  ================================================ */
typedef enum {                                  /*!< ADC_INTEN_SCNCMP                                                          */
  ADC_INTEN_SCNCMP_SCNCMPINT           = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
  ADC_INTEN_SCNCMP_SCNCMPNOINT         = 0,     /*!< SCNCMPNOINT : No ADC scan complete interrupt.                             */
} ADC_INTEN_SCNCMP_Enum;

/* ================================================  ADC INTEN CNVCMP [0..0]  ================================================ */
typedef enum {                                  /*!< ADC_INTEN_CNVCMP                                                          */
  ADC_INTEN_CNVCMP_CNVCMPINT           = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
  ADC_INTEN_CNVCMP_CNVCMPNOINT         = 0,     /*!< CNVCMPNOINT : No ADC conversion complete interrupt.                       */
} ADC_INTEN_CNVCMP_Enum;

/* ========================================================  INTSTAT  ======================================================== */
/* ==============================================  ADC INTSTAT SATCB [11..11]  =============================================== */
typedef enum {                                  /*!< ADC_INTSTAT_SATCB                                                         */
  ADC_INTSTAT_SATCB_SATCBINT           = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
                                                     occurred on either slot 2 or 3 (channel B)                                */
  ADC_INTSTAT_SATCB_NONSATCBINT        = 0,     /*!< NONSATCBINT : No-Saturation                                               */
} ADC_INTSTAT_SATCB_Enum;

/* ==============================================  ADC INTSTAT SATCA [10..10]  =============================================== */
typedef enum {                                  /*!< ADC_INTSTAT_SATCA                                                         */
  ADC_INTSTAT_SATCA_SATCAINT           = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
                                                     occurred on either slot 0 or 1 (channel A)                                */
  ADC_INTSTAT_SATCA_NONSATCAINT        = 0,     /*!< NONSATCAINT : No Saturation                                               */
} ADC_INTSTAT_SATCA_Enum;

/* ================================================  ADC INTSTAT ZXCB [9..9]  ================================================ */
typedef enum {                                  /*!< ADC_INTSTAT_ZXCB                                                          */
  ADC_INTSTAT_ZXCB_ZXCBINT             = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
                                                     occurred on either slot 2 or 3 (channel B)                                */
  ADC_INTSTAT_ZXCB_NONZXCBINT          = 0,     /*!< NONZXCBINT : Non Zero Crossing                                            */
} ADC_INTSTAT_ZXCB_Enum;

/* ================================================  ADC INTSTAT ZXCA [8..8]  ================================================ */
typedef enum {                                  /*!< ADC_INTSTAT_ZXCA                                                          */
  ADC_INTSTAT_ZXCA_ZXCAINT             = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
                                                     occurred on either slot 0 or 1 (channel A)                                */
  ADC_INTSTAT_ZXCA_NONZXCAINT          = 0,     /*!< NONZXCAINT : Non Zero Crossing                                            */
} ADC_INTSTAT_ZXCA_Enum;

/* ================================================  ADC INTSTAT DERR [7..7]  ================================================ */
typedef enum {                                  /*!< ADC_INTSTAT_DERR                                                          */
  ADC_INTSTAT_DERR_DMAERROR            = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
  ADC_INTSTAT_DERR_NODMAERROR          = 0,     /*!< NODMAERROR : DMA Error Condition did not Occurred                         */
} ADC_INTSTAT_DERR_Enum;

/* ================================================  ADC INTSTAT DCMP [6..6]  ================================================ */
typedef enum {                                  /*!< ADC_INTSTAT_DCMP                                                          */
  ADC_INTSTAT_DCMP_DMACOMPLETE         = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
  ADC_INTSTAT_DCMP_DMAON               = 0,     /*!< DMAON : DMA completion is pending or not triggered.                       */
} ADC_INTSTAT_DCMP_Enum;

/* ===============================================  ADC INTSTAT WCINC [5..5]  ================================================ */
typedef enum {                                  /*!< ADC_INTSTAT_WCINC                                                         */
  ADC_INTSTAT_WCINC_WCINCINT           = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
  ADC_INTSTAT_WCINC_WCINCNOINT         = 0,     /*!< WCINCNOINT : Not a Window comparator voltage incursion interrupt.         */
} ADC_INTSTAT_WCINC_Enum;

/* ===============================================  ADC INTSTAT WCEXC [4..4]  ================================================ */
typedef enum {                                  /*!< ADC_INTSTAT_WCEXC                                                         */
  ADC_INTSTAT_WCEXC_WCEXCINT           = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
  ADC_INTSTAT_WCEXC_WCEXCNOINT         = 0,     /*!< WCEXCNOINT : Not a Window comparator voltage excursion interrupt.         */
} ADC_INTSTAT_WCEXC_Enum;

/* ==============================================  ADC INTSTAT FIFOOVR2 [3..3]  ============================================== */
typedef enum {                                  /*!< ADC_INTSTAT_FIFOOVR2                                                      */
  ADC_INTSTAT_FIFOOVR2_FIFOFULLINT     = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
  ADC_INTSTAT_FIFOOVR2_FIFOFULLNOINT   = 0,     /*!< FIFOFULLNOINT : Not a FIFO 100 percent full interrupt.                    */
} ADC_INTSTAT_FIFOOVR2_Enum;

/* ==============================================  ADC INTSTAT FIFOOVR1 [2..2]  ============================================== */
typedef enum {                                  /*!< ADC_INTSTAT_FIFOOVR1                                                      */
  ADC_INTSTAT_FIFOOVR1_FIFO75INT       = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
  ADC_INTSTAT_FIFOOVR1_FIFO75NOINT     = 0,     /*!< FIFO75NOINT : Not FIFO 75 percent full interrupt.                         */
} ADC_INTSTAT_FIFOOVR1_Enum;

/* ===============================================  ADC INTSTAT SCNCMP [1..1]  =============================================== */
typedef enum {                                  /*!< ADC_INTSTAT_SCNCMP                                                        */
  ADC_INTSTAT_SCNCMP_SCNCMPINT         = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
  ADC_INTSTAT_SCNCMP_SCNCMPNOINT       = 0,     /*!< SCNCMPNOINT : No ADC scan complete interrupt.                             */
} ADC_INTSTAT_SCNCMP_Enum;

/* ===============================================  ADC INTSTAT CNVCMP [0..0]  =============================================== */
typedef enum {                                  /*!< ADC_INTSTAT_CNVCMP                                                        */
  ADC_INTSTAT_CNVCMP_CNVCMPINT         = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
  ADC_INTSTAT_CNVCMP_CNVCMPNOINT       = 0,     /*!< CNVCMPNOINT : No ADC conversion complete interrupt.                       */
} ADC_INTSTAT_CNVCMP_Enum;

/* ========================================================  INTCLR  ========================================================= */
/* ===============================================  ADC INTCLR SATCB [11..11]  =============================================== */
typedef enum {                                  /*!< ADC_INTCLR_SATCB                                                          */
  ADC_INTCLR_SATCB_SATCBINT            = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
                                                     occurred on either slot 2 or 3 (channel B)                                */
  ADC_INTCLR_SATCB_NONSATCBINT         = 0,     /*!< NONSATCBINT : No-Saturation                                               */
} ADC_INTCLR_SATCB_Enum;

/* ===============================================  ADC INTCLR SATCA [10..10]  =============================================== */
typedef enum {                                  /*!< ADC_INTCLR_SATCA                                                          */
  ADC_INTCLR_SATCA_SATCAINT            = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
                                                     occurred on either slot 0 or 1 (channel A)                                */
  ADC_INTCLR_SATCA_NONSATCAINT         = 0,     /*!< NONSATCAINT : No Saturation                                               */
} ADC_INTCLR_SATCA_Enum;

/* ================================================  ADC INTCLR ZXCB [9..9]  ================================================= */
typedef enum {                                  /*!< ADC_INTCLR_ZXCB                                                           */
  ADC_INTCLR_ZXCB_ZXCBINT              = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
                                                     occurred on either slot 2 or 3 (channel B)                                */
  ADC_INTCLR_ZXCB_NONZXCBINT           = 0,     /*!< NONZXCBINT : Non Zero Crossing                                            */
} ADC_INTCLR_ZXCB_Enum;

/* ================================================  ADC INTCLR ZXCA [8..8]  ================================================= */
typedef enum {                                  /*!< ADC_INTCLR_ZXCA                                                           */
  ADC_INTCLR_ZXCA_ZXCAINT              = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
                                                     occurred on either slot 0 or 1 (channel A)                                */
  ADC_INTCLR_ZXCA_NONZXCAINT           = 0,     /*!< NONZXCAINT : Non Zero Crossing                                            */
} ADC_INTCLR_ZXCA_Enum;

/* ================================================  ADC INTCLR DERR [7..7]  ================================================= */
typedef enum {                                  /*!< ADC_INTCLR_DERR                                                           */
  ADC_INTCLR_DERR_DMAERROR             = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
  ADC_INTCLR_DERR_NODMAERROR           = 0,     /*!< NODMAERROR : DMA Error Condition did not Occurred                         */
} ADC_INTCLR_DERR_Enum;

/* ================================================  ADC INTCLR DCMP [6..6]  ================================================= */
typedef enum {                                  /*!< ADC_INTCLR_DCMP                                                           */
  ADC_INTCLR_DCMP_DMACOMPLETE          = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
  ADC_INTCLR_DCMP_DMAON                = 0,     /*!< DMAON : DMA completion is pending or not triggered.                       */
} ADC_INTCLR_DCMP_Enum;

/* ================================================  ADC INTCLR WCINC [5..5]  ================================================ */
typedef enum {                                  /*!< ADC_INTCLR_WCINC                                                          */
  ADC_INTCLR_WCINC_WCINCINT            = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
  ADC_INTCLR_WCINC_WCINCNOINT          = 0,     /*!< WCINCNOINT : Not a Window comparator voltage incursion interrupt.         */
} ADC_INTCLR_WCINC_Enum;

/* ================================================  ADC INTCLR WCEXC [4..4]  ================================================ */
typedef enum {                                  /*!< ADC_INTCLR_WCEXC                                                          */
  ADC_INTCLR_WCEXC_WCEXCINT            = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
  ADC_INTCLR_WCEXC_WCEXCNOINT          = 0,     /*!< WCEXCNOINT : Not a Window comparator voltage excursion interrupt.         */
} ADC_INTCLR_WCEXC_Enum;

/* ==============================================  ADC INTCLR FIFOOVR2 [3..3]  =============================================== */
typedef enum {                                  /*!< ADC_INTCLR_FIFOOVR2                                                       */
  ADC_INTCLR_FIFOOVR2_FIFOFULLINT      = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
  ADC_INTCLR_FIFOOVR2_FIFOFULLNOINT    = 0,     /*!< FIFOFULLNOINT : Not a FIFO 100 percent full interrupt.                    */
} ADC_INTCLR_FIFOOVR2_Enum;

/* ==============================================  ADC INTCLR FIFOOVR1 [2..2]  =============================================== */
typedef enum {                                  /*!< ADC_INTCLR_FIFOOVR1                                                       */
  ADC_INTCLR_FIFOOVR1_FIFO75INT        = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
  ADC_INTCLR_FIFOOVR1_FIFO75NOINT      = 0,     /*!< FIFO75NOINT : Not FIFO 75 percent full interrupt.                         */
} ADC_INTCLR_FIFOOVR1_Enum;

/* ===============================================  ADC INTCLR SCNCMP [1..1]  ================================================ */
typedef enum {                                  /*!< ADC_INTCLR_SCNCMP                                                         */
  ADC_INTCLR_SCNCMP_SCNCMPINT          = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
  ADC_INTCLR_SCNCMP_SCNCMPNOINT        = 0,     /*!< SCNCMPNOINT : No ADC scan complete interrupt.                             */
} ADC_INTCLR_SCNCMP_Enum;

/* ===============================================  ADC INTCLR CNVCMP [0..0]  ================================================ */
typedef enum {                                  /*!< ADC_INTCLR_CNVCMP                                                         */
  ADC_INTCLR_CNVCMP_CNVCMPINT          = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
  ADC_INTCLR_CNVCMP_CNVCMPNOINT        = 0,     /*!< CNVCMPNOINT : No ADC conversion complete interrupt.                       */
} ADC_INTCLR_CNVCMP_Enum;

/* ========================================================  INTSET  ========================================================= */
/* ===============================================  ADC INTSET SATCB [11..11]  =============================================== */
typedef enum {                                  /*!< ADC_INTSET_SATCB                                                          */
  ADC_INTSET_SATCB_SATCBINT            = 1,     /*!< SATCBINT : Saturation, as specified by SAT configuration registers,
                                                     occurred on either slot 2 or 3 (channel B)                                */
  ADC_INTSET_SATCB_NONSATCBINT         = 0,     /*!< NONSATCBINT : No-Saturation                                               */
} ADC_INTSET_SATCB_Enum;

/* ===============================================  ADC INTSET SATCA [10..10]  =============================================== */
typedef enum {                                  /*!< ADC_INTSET_SATCA                                                          */
  ADC_INTSET_SATCA_SATCAINT            = 1,     /*!< SATCAINT : Saturation, as specified by SAT configuration registers,
                                                     occurred on either slot 0 or 1 (channel A)                                */
  ADC_INTSET_SATCA_NONSATCAINT         = 0,     /*!< NONSATCAINT : No Saturation                                               */
} ADC_INTSET_SATCA_Enum;

/* ================================================  ADC INTSET ZXCB [9..9]  ================================================= */
typedef enum {                                  /*!< ADC_INTSET_ZXCB                                                           */
  ADC_INTSET_ZXCB_ZXCBINT              = 1,     /*!< ZXCBINT : Zero Crossing, as specified by ZX configuration registers,
                                                     occurred on either slot 2 or 3 (channel B)                                */
  ADC_INTSET_ZXCB_NONZXCBINT           = 0,     /*!< NONZXCBINT : Non Zero Crossing                                            */
} ADC_INTSET_ZXCB_Enum;

/* ================================================  ADC INTSET ZXCA [8..8]  ================================================= */
typedef enum {                                  /*!< ADC_INTSET_ZXCA                                                           */
  ADC_INTSET_ZXCA_ZXCAINT              = 1,     /*!< ZXCAINT : Zero Crossing, as specified by ZX configuration registers,
                                                     occurred on either slot 0 or 1 (channel A)                                */
  ADC_INTSET_ZXCA_NONZXCAINT           = 0,     /*!< NONZXCAINT : Non Zero Crossing                                            */
} ADC_INTSET_ZXCA_Enum;

/* ================================================  ADC INTSET DERR [7..7]  ================================================= */
typedef enum {                                  /*!< ADC_INTSET_DERR                                                           */
  ADC_INTSET_DERR_DMAERROR             = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
  ADC_INTSET_DERR_NODMAERROR           = 0,     /*!< NODMAERROR : DMA Error Condition did not Occurred                         */
} ADC_INTSET_DERR_Enum;

/* ================================================  ADC INTSET DCMP [6..6]  ================================================= */
typedef enum {                                  /*!< ADC_INTSET_DCMP                                                           */
  ADC_INTSET_DCMP_DMACOMPLETE          = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
  ADC_INTSET_DCMP_DMAON                = 0,     /*!< DMAON : DMA completion is pending or not triggered.                       */
} ADC_INTSET_DCMP_Enum;

/* ================================================  ADC INTSET WCINC [5..5]  ================================================ */
typedef enum {                                  /*!< ADC_INTSET_WCINC                                                          */
  ADC_INTSET_WCINC_WCINCINT            = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
  ADC_INTSET_WCINC_WCINCNOINT          = 0,     /*!< WCINCNOINT : Not a Window comparator voltage incursion interrupt.         */
} ADC_INTSET_WCINC_Enum;

/* ================================================  ADC INTSET WCEXC [4..4]  ================================================ */
typedef enum {                                  /*!< ADC_INTSET_WCEXC                                                          */
  ADC_INTSET_WCEXC_WCEXCINT            = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
  ADC_INTSET_WCEXC_WCEXCNOINT          = 0,     /*!< WCEXCNOINT : Not a Window comparator voltage excursion interrupt.         */
} ADC_INTSET_WCEXC_Enum;

/* ==============================================  ADC INTSET FIFOOVR2 [3..3]  =============================================== */
typedef enum {                                  /*!< ADC_INTSET_FIFOOVR2                                                       */
  ADC_INTSET_FIFOOVR2_FIFOFULLINT      = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
  ADC_INTSET_FIFOOVR2_FIFOFULLNOINT    = 0,     /*!< FIFOFULLNOINT : Not a FIFO 100 percent full interrupt.                    */
} ADC_INTSET_FIFOOVR2_Enum;

/* ==============================================  ADC INTSET FIFOOVR1 [2..2]  =============================================== */
typedef enum {                                  /*!< ADC_INTSET_FIFOOVR1                                                       */
  ADC_INTSET_FIFOOVR1_FIFO75INT        = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
  ADC_INTSET_FIFOOVR1_FIFO75NOINT      = 0,     /*!< FIFO75NOINT : Not FIFO 75 percent full interrupt.                         */
} ADC_INTSET_FIFOOVR1_Enum;

/* ===============================================  ADC INTSET SCNCMP [1..1]  ================================================ */
typedef enum {                                  /*!< ADC_INTSET_SCNCMP                                                         */
  ADC_INTSET_SCNCMP_SCNCMPINT          = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
  ADC_INTSET_SCNCMP_SCNCMPNOINT        = 0,     /*!< SCNCMPNOINT : No ADC scan complete interrupt.                             */
} ADC_INTSET_SCNCMP_Enum;

/* ===============================================  ADC INTSET CNVCMP [0..0]  ================================================ */
typedef enum {                                  /*!< ADC_INTSET_CNVCMP                                                         */
  ADC_INTSET_CNVCMP_CNVCMPINT          = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
  ADC_INTSET_CNVCMP_CNVCMPNOINT        = 0,     /*!< CNVCMPNOINT : No ADC conversion complete interrupt.                       */
} ADC_INTSET_CNVCMP_Enum;

/* =======================================================  DMATRIGEN  ======================================================= */
/* ======================================================  DMATRIGSTAT  ====================================================== */
/* ========================================================  DMACFG  ========================================================= */
/* ==============================================  ADC DMACFG DMAMSK [17..17]  =============================================== */
typedef enum {                                  /*!< ADC_DMACFG_DMAMSK                                                         */
  ADC_DMACFG_DMAMSK_DIS                = 0,     /*!< DIS : FIFO Contents are copied directly to memory without modification.   */
  ADC_DMACFG_DMAMSK_EN                 = 1,     /*!< EN : Only the FIFODATA contents are copied to memory on DMA
                                                     transfers. The SLOTNUM and FIFOCNT contents are cleared
                                                     to zero.                                                                  */
} ADC_DMACFG_DMAMSK_Enum;

/* ==============================================  ADC DMACFG DMADYNPRI [9..9]  ============================================== */
typedef enum {                                  /*!< ADC_DMACFG_DMADYNPRI                                                      */
  ADC_DMACFG_DMADYNPRI_DIS             = 0,     /*!< DIS : Disable dynamic priority (use DMAPRI setting only)                  */
  ADC_DMACFG_DMADYNPRI_EN              = 1,     /*!< EN : Enable dynamic priority                                              */
} ADC_DMACFG_DMADYNPRI_Enum;

/* ===============================================  ADC DMACFG DMAPRI [8..8]  ================================================ */
typedef enum {                                  /*!< ADC_DMACFG_DMAPRI                                                         */
  ADC_DMACFG_DMAPRI_LOW                = 0,     /*!< LOW : Low Priority (service as best effort)                               */
  ADC_DMACFG_DMAPRI_HIGH               = 1,     /*!< HIGH : High Priority (service immediately)                                */
} ADC_DMACFG_DMAPRI_Enum;

/* ===============================================  ADC DMACFG DMADIR [2..2]  ================================================ */
typedef enum {                                  /*!< ADC_DMACFG_DMADIR                                                         */
  ADC_DMACFG_DMADIR_P2M                = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction                             */
  ADC_DMACFG_DMADIR_M2P                = 1,     /*!< M2P : Memory to Peripheral transaction                                    */
} ADC_DMACFG_DMADIR_Enum;

/* ================================================  ADC DMACFG DMAEN [0..0]  ================================================ */
typedef enum {                                  /*!< ADC_DMACFG_DMAEN                                                          */
  ADC_DMACFG_DMAEN_DIS                 = 0,     /*!< DIS : Disable DMA Function                                                */
  ADC_DMACFG_DMAEN_EN                  = 1,     /*!< EN : Enable DMA Function                                                  */
} ADC_DMACFG_DMAEN_Enum;

/* ======================================================  DMATOTCOUNT  ====================================================== */
/* ======================================================  DMATARGADDR  ====================================================== */
/* ========================================================  DMASTAT  ======================================================== */


/* =========================================================================================================================== */
/* ================                                          APBDMA                                           ================ */
/* =========================================================================================================================== */

/* ========================================================  BBVALUE  ======================================================== */
/* ======================================================  BBSETCLEAR  ======================================================= */
/* ========================================================  BBINPUT  ======================================================== */
/* =======================================================  DEBUGDATA  ======================================================= */
/* =========================================================  DEBUG  ========================================================= */
/* ==============================================  APBDMA DEBUG DEBUGEN [0..3]  ============================================== */
typedef enum {                                  /*!< APBDMA_DEBUG_DEBUGEN                                                      */
  APBDMA_DEBUG_DEBUGEN_OFF             = 0,     /*!< OFF : Debug Disabled                                                      */
  APBDMA_DEBUG_DEBUGEN_ARB             = 1,     /*!< ARB : Debug Arb values                                                    */
} APBDMA_DEBUG_DEBUGEN_Enum;



/* =========================================================================================================================== */
/* ================                                          CLKGEN                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  OCTRL  ========================================================= */
/* ===============================================  CLKGEN OCTRL OSEL [7..7]  ================================================ */
typedef enum {                                  /*!< CLKGEN_OCTRL_OSEL                                                         */
  CLKGEN_OCTRL_OSEL_RTC_XT             = 0,     /*!< RTC_XT : RTC uses the XT                                                  */
  CLKGEN_OCTRL_OSEL_RTC_LFRC           = 1,     /*!< RTC_LFRC : RTC uses the LFRC                                              */
} CLKGEN_OCTRL_OSEL_Enum;

/* ========================================================  CLKOUT  ========================================================= */
/* ===============================================  CLKGEN CLKOUT CKEN [7..7]  =============================================== */
typedef enum {                                  /*!< CLKGEN_CLKOUT_CKEN                                                        */
  CLKGEN_CLKOUT_CKEN_DIS               = 0,     /*!< DIS : Disable CLKOUT                                                      */
  CLKGEN_CLKOUT_CKEN_EN                = 1,     /*!< EN : Enable CLKOUT                                                        */
} CLKGEN_CLKOUT_CKEN_Enum;

/* ==============================================  CLKGEN CLKOUT CKSEL [0..5]  =============================================== */
typedef enum {                                  /*!< CLKGEN_CLKOUT_CKSEL                                                       */
  CLKGEN_CLKOUT_CKSEL_LFRC             = 0,     /*!< LFRC : LFRC clock source selection                                        */
  CLKGEN_CLKOUT_CKSEL_XT_DIV2          = 1,     /*!< XT_DIV2 : XT / 2 clock source selection                                   */
  CLKGEN_CLKOUT_CKSEL_XT_DIV4          = 2,     /*!< XT_DIV4 : XT / 4 clock source selection                                   */
  CLKGEN_CLKOUT_CKSEL_XT_DIV8          = 3,     /*!< XT_DIV8 : XT / 8 clock source selection                                   */
  CLKGEN_CLKOUT_CKSEL_XT_DIV16         = 4,     /*!< XT_DIV16 : XT / 16 clock source selection                                 */
  CLKGEN_CLKOUT_CKSEL_XT_DIV32         = 5,     /*!< XT_DIV32 : XT / 32 clock source selection                                 */
  CLKGEN_CLKOUT_CKSEL_RTC_1Hz          = 16,    /*!< RTC_1Hz : 1 Hz as selected in RTC                                         */
  CLKGEN_CLKOUT_CKSEL_XT_DIV2M         = 22,    /*!< XT_DIV2M : XT / 2097152 (2^21) clock source selection                     */
  CLKGEN_CLKOUT_CKSEL_XT               = 23,    /*!< XT : XT clock source selection                                            */
  CLKGEN_CLKOUT_CKSEL_CG_100Hz         = 24,    /*!< CG_100Hz : 100 Hz as selected in CLKGEN                                   */
  CLKGEN_CLKOUT_CKSEL_HFRC_DIV2        = 25,    /*!< HFRC_DIV2 : HFRC / 2 clock source selection                               */
  CLKGEN_CLKOUT_CKSEL_HFRC_DIV8        = 26,    /*!< HFRC_DIV8 : HFRC / 8 clock source selection                               */
  CLKGEN_CLKOUT_CKSEL_HFRC_DIV16       = 27,    /*!< HFRC_DIV16 : HFRC / 16 clock source selection                             */
  CLKGEN_CLKOUT_CKSEL_HFRC_DIV32       = 28,    /*!< HFRC_DIV32 : HFRC / 32 clock source selection                             */
  CLKGEN_CLKOUT_CKSEL_HFRC_DIV128      = 29,    /*!< HFRC_DIV128 : HFRC / 128 clock source selection                           */
  CLKGEN_CLKOUT_CKSEL_HFRC_DIV256      = 30,    /*!< HFRC_DIV256 : HFRC / 256 clock source selection                           */
  CLKGEN_CLKOUT_CKSEL_HFRC_DIV512      = 31,    /*!< HFRC_DIV512 : HFRC / 512 clock source selection                           */
  CLKGEN_CLKOUT_CKSEL_HFRC_DIV1024     = 32,    /*!< HFRC_DIV1024 : HFRC / 1024 clock source selection                         */
  CLKGEN_CLKOUT_CKSEL_LFRC_DIV2        = 35,    /*!< LFRC_DIV2 : LFRC / 2 clock source selection                               */
  CLKGEN_CLKOUT_CKSEL_LFRC_DIV32       = 36,    /*!< LFRC_DIV32 : LFRC / 32 clock source selection                             */
  CLKGEN_CLKOUT_CKSEL_LFRC_DIV512      = 37,    /*!< LFRC_DIV512 : LFRC / 512 clock source selection                           */
  CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K      = 38,    /*!< LFRC_DIV32K : LFRC / 32768 clock source selection                         */
  CLKGEN_CLKOUT_CKSEL_XT_DIV256        = 39,    /*!< XT_DIV256 : XT / 256 clock source selection                               */
  CLKGEN_CLKOUT_CKSEL_XT_DIV8K         = 40,    /*!< XT_DIV8K : XT / 8192 clock source selection                               */
  CLKGEN_CLKOUT_CKSEL_XT_DIV64K        = 41,    /*!< XT_DIV64K : XT / 65536 (2^16) clock source selection                      */
  CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16      = 42,    /*!< ULFRC_DIV16 : Uncal LFRC / 16 clock source selection                      */
  CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128     = 43,    /*!< ULFRC_DIV128 : Uncal LFRC / 128 clock source selection                    */
  CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz        = 44,    /*!< ULFRC_1Hz : Uncal LFRC / 1024 clock source selection                      */
  CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K      = 45,    /*!< ULFRC_DIV4K : Uncal LFRC / 4096 clock source selection                    */
  CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M      = 46,    /*!< ULFRC_DIV1M : Uncal LFRC / 1048576 (2^20) clock source selection          */
  CLKGEN_CLKOUT_CKSEL_HFRC_DIV256K     = 47,    /*!< HFRC_DIV256K : HFRC / 262144 (2^18) clock source selection                */
  CLKGEN_CLKOUT_CKSEL_HFRC_DIV64M      = 48,    /*!< HFRC_DIV64M : HFRC / 67108864 (2^26) clock source selection               */
  CLKGEN_CLKOUT_CKSEL_LFRC_DIV1M       = 49,    /*!< LFRC_DIV1M : LFRC / 1048576 (2^20) clock source selection                 */
  CLKGEN_CLKOUT_CKSEL_XTNE             = 53,    /*!< XTNE : XT (not autoenabled)                                               */
  CLKGEN_CLKOUT_CKSEL_XTNE_DIV16       = 54,    /*!< XTNE_DIV16 : XT / 16 (not autoenabled)                                    */
  CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32     = 55,    /*!< LFRCNE_DIV32 : LFRC / 32 (not autoenabled)                                */
  CLKGEN_CLKOUT_CKSEL_LFRCNE           = 57,    /*!< LFRCNE : LFRC (not autoenabled) - Default for undefined values            */
  CLKGEN_CLKOUT_CKSEL_HFRC2_6MHz       = 58,    /*!< HFRC2_6MHz : HFRC2 6MHz clock source selection                            */
  CLKGEN_CLKOUT_CKSEL_HFRC2_12MHz      = 59,    /*!< HFRC2_12MHz : HFRC2 24MHz clock source selection                          */
  CLKGEN_CLKOUT_CKSEL_HFRC2_24MHz      = 60,    /*!< HFRC2_24MHz : HFRC2 24MHz clock source selection                          */
} CLKGEN_CLKOUT_CKSEL_Enum;

/* =========================================================  HFADJ  ========================================================= */
/* ==========================================  CLKGEN HFADJ HFADJMAXDELTA [24..28]  ========================================== */
typedef enum {                                  /*!< CLKGEN_HFADJ_HFADJMAXDELTA                                                */
  CLKGEN_HFADJ_HFADJMAXDELTA_DISABLED  = 0,     /*!< DISABLED : Maximum Delta function is disabled                             */
  CLKGEN_HFADJ_HFADJMAXDELTA_ENABLED   = 1,     /*!< ENABLED : Maximum Delta function is enabled                               */
} CLKGEN_HFADJ_HFADJMAXDELTA_Enum;

/* ============================================  CLKGEN HFADJ HFADJGAIN [21..23]  ============================================ */
typedef enum {                                  /*!< CLKGEN_HFADJ_HFADJGAIN                                                    */
  CLKGEN_HFADJ_HFADJGAIN_Gain_of_1     = 0,     /*!< Gain_of_1 : HF Adjust with Gain of 1                                      */
  CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_2 = 1,    /*!< Gain_of_1_in_2 : HF Adjust with Gain of 0.5                               */
  CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_4 = 2,    /*!< Gain_of_1_in_4 : HF Adjust with Gain of 0.25                              */
  CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_8 = 3,    /*!< Gain_of_1_in_8 : HF Adjust with Gain of 0.125                             */
  CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_16 = 4,   /*!< Gain_of_1_in_16 : HF Adjust with Gain of 0.0625                           */
  CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_32 = 5,   /*!< Gain_of_1_in_32 : HF Adjust with Gain of 0.03125                          */
} CLKGEN_HFADJ_HFADJGAIN_Enum;

/* ============================================  CLKGEN HFADJ HFWARMUP [20..20]  ============================================= */
typedef enum {                                  /*!< CLKGEN_HFADJ_HFWARMUP                                                     */
  CLKGEN_HFADJ_HFWARMUP_1SEC           = 0,     /*!< 1SEC : Autoadjust XT warmup period = 1-2 seconds                          */
  CLKGEN_HFADJ_HFWARMUP_2SEC           = 1,     /*!< 2SEC : Autoadjust XT warmup period = 2-4 seconds                          */
} CLKGEN_HFADJ_HFWARMUP_Enum;

/* ==============================================  CLKGEN HFADJ HFADJCK [1..3]  ============================================== */
typedef enum {                                  /*!< CLKGEN_HFADJ_HFADJCK                                                      */
  CLKGEN_HFADJ_HFADJCK_4SEC            = 0,     /*!< 4SEC : Autoadjust repeat period = 4 seconds                               */
  CLKGEN_HFADJ_HFADJCK_16SEC           = 1,     /*!< 16SEC : Autoadjust repeat period = 16 seconds                             */
  CLKGEN_HFADJ_HFADJCK_32SEC           = 2,     /*!< 32SEC : Autoadjust repeat period = 32 seconds                             */
  CLKGEN_HFADJ_HFADJCK_64SEC           = 3,     /*!< 64SEC : Autoadjust repeat period = 64 seconds                             */
  CLKGEN_HFADJ_HFADJCK_128SEC          = 4,     /*!< 128SEC : Autoadjust repeat period = 128 seconds                           */
  CLKGEN_HFADJ_HFADJCK_256SEC          = 5,     /*!< 256SEC : Autoadjust repeat period = 256 seconds                           */
  CLKGEN_HFADJ_HFADJCK_512SEC          = 6,     /*!< 512SEC : Autoadjust repeat period = 512 seconds                           */
  CLKGEN_HFADJ_HFADJCK_1024SEC         = 7,     /*!< 1024SEC : Autoadjust repeat period = 1024 seconds                         */
} CLKGEN_HFADJ_HFADJCK_Enum;

/* ==============================================  CLKGEN HFADJ HFADJEN [0..0]  ============================================== */
typedef enum {                                  /*!< CLKGEN_HFADJ_HFADJEN                                                      */
  CLKGEN_HFADJ_HFADJEN_DIS             = 0,     /*!< DIS : Disable the HFRC adjustment                                         */
  CLKGEN_HFADJ_HFADJEN_EN              = 1,     /*!< EN : Enable the HFRC adjustment                                           */
} CLKGEN_HFADJ_HFADJEN_Enum;

/* ======================================================  CLOCKENSTAT  ====================================================== */
/* ========================================  CLKGEN CLOCKENSTAT CLOCKENSTAT [0..31]  ========================================= */
typedef enum {                                  /*!< CLKGEN_CLOCKENSTAT_CLOCKENSTAT                                            */
  CLKGEN_CLOCKENSTAT_CLOCKENSTAT_PERIPH_ALL_XTAL_EN = 16777216,/*!< PERIPH_ALL_XTAL_EN : [24] Clock enable for PERIPH_ALL_XTAL_EN */
  CLKGEN_CLOCKENSTAT_CLOCKENSTAT_PERIPH_ALL_HFRC_EN = 33554432,/*!< PERIPH_ALL_HFRC_EN : [25] Clock enable for PERIPH_ALL_HFRC_EN */
  CLKGEN_CLOCKENSTAT_CLOCKENSTAT_HFADJEN = 67108864,/*!< HFADJEN : [26] HFRC Adjust enabled                                    */
  CLKGEN_CLOCKENSTAT_CLOCKENSTAT_HFRC_EN_HFADJ = 134217728,/*!< HFRC_EN_HFADJ : [27] HFRC HFADJ enabled                        */
  CLKGEN_CLOCKENSTAT_CLOCKENSTAT_nOSEL = 268435456,/*!< nOSEL : [28] ~OSEL                                                     */
  CLKGEN_CLOCKENSTAT_CLOCKENSTAT_clkout_xtal_en = 536870912,/*!< clkout_xtal_en : [29] XTAL clkout enabled                     */
  CLKGEN_CLOCKENSTAT_CLOCKENSTAT_clkout_hfrc_en = 1073741824,/*!< clkout_hfrc_en : [30] HFRC clkout enabled                    */
} CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Enum;

/* =====================================================  CLOCKEN2STAT  ====================================================== */
/* =======================================  CLKGEN CLOCKEN2STAT CLOCKEN2STAT [0..31]  ======================================== */
typedef enum {                                  /*!< CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT                                          */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_ADC_CLKEN = 1,/*!< ADC_CLKEN : [0] Clock enable for the ADC.                                */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_ACTIVITY_CLKEN = 2,/*!< APBDMA_ACTIVITY_CLKEN : [1] Clock enable for the APBDMA ACTIVITY */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_AOH_CLKEN = 4,/*!< APBDMA_AOH_CLKEN : [2] Clock enable for the APBDMA AOH DOMAIN     */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_AOL_CLKEN = 8,/*!< APBDMA_AOL_CLKEN : [3] Clock enable for the APBDMA AOL DOMAIN     */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_APB_CLKEN = 16,/*!< APBDMA_APB_CLKEN : [4] Clock enable for the APBDMA_APB           */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_AUD_CLKEN = 32,/*!< APBDMA_AUD_CLKEN : [5] Clock enable for the APBDMA_AUD           */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_CRYPTO_CLKEN = 64,/*!< APBDMA_CRYPTO_CLKEN : [6] Clock enable for the APBDMA_HCPA    */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_DBG_CLKEN = 128,/*!< APBDMA_DBG_CLKEN : [7] Clock enable for the APBDMA_DBG          */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_DISP_CLKEN = 256,/*!< APBDMA_DISP_CLKEN : [8] Clock enable for the APBDMA_DISP       */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_DISPPHY_CLKEN = 512,/*!< APBDMA_DISPPHY_CLKEN : [9] Clock enable for the APBDMA_DISPPHY */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_DSPA_CLKEN = 1024,/*!< APBDMA_DSPA_CLKEN : [10] Clock enable for the APBDMA_DSPA     */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_GFX_CLKEN = 2048,/*!< APBDMA_GFX_CLKEN : [11] Clock enable for the APBDMA_GFX        */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_HSPA_CLKEN = 4096,/*!< APBDMA_HSPA_CLKEN : [12] Clock enable for the APBDMA_HSPA     */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_HSPB_CLKEN = 8192,/*!< APBDMA_HSPB_CLKEN : [13] Clock enable for the APBDMA_HSPB     */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_HSPC_CLKEN = 16384,/*!< APBDMA_HSPC_CLKEN : [14] Clock enable for the APBDMA_HSPC    */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_IOS_CLKEN = 32768,/*!< APBDMA_IOS_CLKEN : [15] Clock enable for the APBDMA_IOS       */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_MSPI0_CLKEN = 65536,/*!< APBDMA_MSPI0_CLKEN : [16] Clock enable for the APBDMA_MSPI0 */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_MSPI1_CLKEN = 131072,/*!< APBDMA_MSPI1_CLKEN : [17] Clock enable for the APBDMA_MSPI1 */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_MSPI2_CLKEN = 262144,/*!< APBDMA_MSPI2_CLKEN : [18] Clock enable for the APBDMA_MSPI2 */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_SDIO_CLKEN = 524288,/*!< APBDMA_SDIO_CLKEN : [19] Clock enable for the APBDMA_SDIO   */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_APBDMA_USB_CLKEN = 1048576,/*!< APBDMA_USB_CLKEN : [20] Clock enable for the APBDMA_USB     */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_AUDADC_CLKEN = 2097152,/*!< AUDADC_CLKEN : [21] Clock enable for the AUDADC                 */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_CM4_TPIU_CLKEN = 4194304,/*!< CM4_TPIU_CLKEN : [22] Clock enable for the CM4_TPIU           */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DBG_TPIU_CLKEN = 8388608,/*!< DBG_TPIU_CLKEN : [23] Clock enable for the DBG_TPIU           */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DBG_TS_CLKEN = 16777216,/*!< DBG_TS_CLKEN : [24] Clock enable for the DBG_TS                */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DISP_CLK_CLKEN = 33554432,/*!< DISP_CLK_CLKEN : [25] Clock enable for the DISP_CLK          */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DPHY_PLL_REF_CLKEN = 67108864,/*!< DPHY_PLL_REF_CLKEN : [26] Clock enable for the DPHY_PLL_REF */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_I2S0_CLKEN = 134217728,/*!< DSP_I2S0_CLKEN : [27] Clock enable for the DSP_I2S0         */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_I2S0_REFCLK_CLKEN = 268435456,/*!< DSP_I2S0_REFCLK_CLKEN : [28] Clock enable for the DSP_I2S0_REFCLK */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_I2S1_CLKEN = 536870912,/*!< DSP_I2S1_CLKEN : [29] Clock enable for the DSP_I2S1         */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_I2S1_REFCLK_CLKEN = 1073741824,/*!< DSP_I2S1_REFCLK_CLKEN : [30] Clock enable for the DSP_I2S1_REFCLK */
  CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_DSP_MILLI_CLKEN = -2147483648,/*!< DSP_MILLI_CLKEN : [31] Clock enable for the DSP_MILLI    */
} CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Enum;

/* =====================================================  CLOCKEN3STAT  ====================================================== */
/* =======================================  CLKGEN CLOCKEN3STAT CLOCKEN3STAT [0..31]  ======================================== */
typedef enum {                                  /*!< CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT                                          */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DSP_PDM0_CLKEN = 1,/*!< DSP_PDM0_CLKEN : [0] Clock enable for the DSP_PDM0                  */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DSP_PDM1_CLKEN = 2,/*!< DSP_PDM1_CLKEN : [1] Clock enable for the DSP_PDM1                  */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DSP_PDM2_CLKEN = 4,/*!< DSP_PDM2_CLKEN : [2] Clock enable for the DSP_PDM2                  */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DSP_PDM3_CLKEN = 8,/*!< DSP_PDM3_CLKEN : [3] Clock enable for the DSP_PDM3                  */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RESERVED16 = 16,/*!< RESERVED16 : Reserved selection. Operation unknown if selected.        */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RESERVED32 = 32,/*!< RESERVED32 : Reserved selection. Operation unknown if selected.        */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC0_CLKEN = 64,/*!< IOMSTRIFC0_CLKEN : [6] Clock enable for the IOMSTRIFC0           */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC1_CLKEN = 128,/*!< IOMSTRIFC1_CLKEN : [7] Clock enable for the IO MASTER 1 IFC
                                                     INTERFACE                                                                 */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC2_CLKEN = 256,/*!< IOMSTRIFC2_CLKEN : [8] Clock enable for the IO MASTER 2 IFC
                                                     INTERFACE                                                                 */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC3_CLKEN = 512,/*!< IOMSTRIFC3_CLKEN : [9] Clock enable for the IO MASTER 3 IFC
                                                     INTERFACE                                                                 */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC4_CLKEN = 1024,/*!< IOMSTRIFC4_CLKEN : [10] Clock enable for the IO MASTER 4 IFC
                                                     INTERFACE                                                                 */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC5_CLKEN = 2048,/*!< IOMSTRIFC5_CLKEN : [11] Clock enable for the IO MASTER 5 IFC
                                                     INTERFACE                                                                 */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC6_CLKEN = 4096,/*!< IOMSTRIFC6_CLKEN : [12] Clock enable for the IO MASTER 6 IFC
                                                     INTERFACE                                                                 */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_IOMSTRIFC7_CLKEN = 8192,/*!< IOMSTRIFC7_CLKEN : [13] Clock enable for the IO MASTER 7 IFC
                                                     INTERFACE                                                                 */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RSTGEN_CLKEN = 16384,/*!< RSTGEN_CLKEN : [14] Clock enable for the RSTGEN                   */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RSTGEN_POS_CLKEN = 32768,/*!< RSTGEN_POS_CLKEN : [15] Clock enable for the RSTGEN           */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RTC_CLKEN = 65536,/*!< RTC_CLKEN : [16] Clock enable for the RTC                            */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_SDIO_XIN_CLKEN = 131072,/*!< SDIO_XIN_CLKEN : [17] Clock enable for the SDIO_XIN            */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_UART0HF_CLKEN = 262144,/*!< UART0HF_CLKEN : [18] Clock enable for the UART0 HF              */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_UART1HF_CLKEN = 524288,/*!< UART1HF_CLKEN : [19] Clock enable for the UART1 HF              */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_UART2HF_CLKEN = 1048576,/*!< UART2HF_CLKEN : [20] Clock enable for the UART2 HF             */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_UART3HF_CLKEN = 2097152,/*!< UART3HF_CLKEN : [21] Clock enable for the UART3 HF             */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_USB_REFCLK_CLKEN = 4194304,/*!< USB_REFCLK_CLKEN : [22] Clock enable for the USB_REFCLK     */
  CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_WDT_CLKEN = 8388608,/*!< WDT_CLKEN : [23] Clock enable for the WDT                          */
} CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Enum;

/* =========================================================  MISC  ========================================================== */
/* =========================================  CLKGEN MISC HFRC96TRUNKGATE [24..24]  ========================================== */
typedef enum {                                  /*!< CLKGEN_MISC_HFRC96TRUNKGATE                                               */
  CLKGEN_MISC_HFRC96TRUNKGATE_DIS      = 0,     /*!< DIS : Disable HFRC96_TRUNK_GATE                                           */
  CLKGEN_MISC_HFRC96TRUNKGATE_EN       = 1,     /*!< EN : DO NOT USE. HFRC96_TRUNK_GATE. Setting this bit when BIT23=0,
                                                     will kill HFRC root clock.                                                */
} CLKGEN_MISC_HFRC96TRUNKGATE_Enum;

/* ========================================  CLKGEN MISC HFRCFUNCCLKGATEEN [23..23]  ========================================= */
typedef enum {                                  /*!< CLKGEN_MISC_HFRCFUNCCLKGATEEN                                             */
  CLKGEN_MISC_HFRCFUNCCLKGATEEN_DIS    = 0,     /*!< DIS : Disable clock gate                                                  */
  CLKGEN_MISC_HFRCFUNCCLKGATEEN_EN     = 1,     /*!< EN : Enable clock gate                                                    */
} CLKGEN_MISC_HFRCFUNCCLKGATEEN_Enum;

/* =======================================  CLKGEN MISC ETMTRACECLKCLKGATEEN [22..22]  ======================================= */
typedef enum {                                  /*!< CLKGEN_MISC_ETMTRACECLKCLKGATEEN                                          */
  CLKGEN_MISC_ETMTRACECLKCLKGATEEN_DIS = 0,     /*!< DIS : Disable clock gate                                                  */
  CLKGEN_MISC_ETMTRACECLKCLKGATEEN_EN  = 1,     /*!< EN : Enable clock gate                                                    */
} CLKGEN_MISC_ETMTRACECLKCLKGATEEN_Enum;

/* ======================================  CLKGEN MISC APBDMACPUCLKCLKGATEEN [21..21]  ======================================= */
typedef enum {                                  /*!< CLKGEN_MISC_APBDMACPUCLKCLKGATEEN                                         */
  CLKGEN_MISC_APBDMACPUCLKCLKGATEEN_DIS = 0,    /*!< DIS : Disable clock gate                                                  */
  CLKGEN_MISC_APBDMACPUCLKCLKGATEEN_EN = 1,     /*!< EN : Enable clock gate                                                    */
} CLKGEN_MISC_APBDMACPUCLKCLKGATEEN_Enum;

/* ========================================  CLKGEN MISC GFXAXICLKCLKGATEEN [20..20]  ======================================== */
typedef enum {                                  /*!< CLKGEN_MISC_GFXAXICLKCLKGATEEN                                            */
  CLKGEN_MISC_GFXAXICLKCLKGATEEN_DIS   = 0,     /*!< DIS : Disable clock gate                                                  */
  CLKGEN_MISC_GFXAXICLKCLKGATEEN_EN    = 1,     /*!< EN : Enable clock gate                                                    */
} CLKGEN_MISC_GFXAXICLKCLKGATEEN_Enum;

/* =========================================  CLKGEN MISC GFXCLKCLKGATEEN [19..19]  ========================================== */
typedef enum {                                  /*!< CLKGEN_MISC_GFXCLKCLKGATEEN                                               */
  CLKGEN_MISC_GFXCLKCLKGATEEN_DIS      = 0,     /*!< DIS : Disable clock gate                                                  */
  CLKGEN_MISC_GFXCLKCLKGATEEN_EN       = 1,     /*!< EN : Enable clock gate                                                    */
} CLKGEN_MISC_GFXCLKCLKGATEEN_Enum;

/* =========================================  CLKGEN MISC CM4DAXICLKGATEEN [18..18]  ========================================= */
typedef enum {                                  /*!< CLKGEN_MISC_CM4DAXICLKGATEEN                                              */
  CLKGEN_MISC_CM4DAXICLKGATEEN_DIS     = 0,     /*!< DIS : Disable clock gate                                                  */
  CLKGEN_MISC_CM4DAXICLKGATEEN_EN      = 1,     /*!< EN : Enable clock gate                                                    */
} CLKGEN_MISC_CM4DAXICLKGATEEN_Enum;

/* =======================================  CLKGEN MISC PWRONCLKENI2S1REFCLK [16..16]  ======================================= */
typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENI2S1REFCLK                                          */
  CLKGEN_MISC_PWRONCLKENI2S1REFCLK_I2S1REFCLKENRST = 0,/*!< I2S1REFCLKENRST : Enable I2S instance 1 Clock to run during
                                                     reset                                                                     */
  CLKGEN_MISC_PWRONCLKENI2S1REFCLK_DEFEATURE = 1,/*!< DEFEATURE : Chicken bit to revert to rev A                               */
} CLKGEN_MISC_PWRONCLKENI2S1REFCLK_Enum;

/* =======================================  CLKGEN MISC PWRONCLKENI2S0REFCLK [15..15]  ======================================= */
typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENI2S0REFCLK                                          */
  CLKGEN_MISC_PWRONCLKENI2S0REFCLK_I2S0REFCLKENRST = 0,/*!< I2S0REFCLKENRST : Enable I2S instance 0 Clock to run during
                                                     reset                                                                     */
  CLKGEN_MISC_PWRONCLKENI2S0REFCLK_DEFEATURE = 1,/*!< DEFEATURE : Chicken bit to revert to rev A                               */
} CLKGEN_MISC_PWRONCLKENI2S0REFCLK_Enum;

/* ========================================  CLKGEN MISC AXIXACLKENOVRRIDE [14..14]  ========================================= */
typedef enum {                                  /*!< CLKGEN_MISC_AXIXACLKENOVRRIDE                                             */
  CLKGEN_MISC_AXIXACLKENOVRRIDE_DEFEATURE_DISABLED = 0,/*!< DEFEATURE_DISABLED : Fine grain clock gating enabled               */
  CLKGEN_MISC_AXIXACLKENOVRRIDE_DEFEATURE = 1,  /*!< DEFEATURE : AXI Clock enabled when core is not in Sleep mode              */
} CLKGEN_MISC_AXIXACLKENOVRRIDE_Enum;

/* ==========================================  CLKGEN MISC PWRONCLKENI2S1 [13..13]  ========================================== */
typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENI2S1                                                */
  CLKGEN_MISC_PWRONCLKENI2S1_I2S1CLKENRST = 0,  /*!< I2S1CLKENRST : Enable I2S instance 1 engine Clock to run during
                                                     reset                                                                     */
  CLKGEN_MISC_PWRONCLKENI2S1_DEFEATURE = 1,     /*!< DEFEATURE : Chicken bit to revert to rev A                                */
} CLKGEN_MISC_PWRONCLKENI2S1_Enum;

/* ==========================================  CLKGEN MISC PWRONCLKENI2S0 [12..12]  ========================================== */
typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENI2S0                                                */
  CLKGEN_MISC_PWRONCLKENI2S0_I2S0CLKENRST = 0,  /*!< I2S0CLKENRST : Enable I2S instance 0 engine Clock to run during
                                                     reset                                                                     */
  CLKGEN_MISC_PWRONCLKENI2S0_DEFEATURE = 1,     /*!< DEFEATURE : Chicken bit to revert to rev A                                */
} CLKGEN_MISC_PWRONCLKENI2S0_Enum;

/* =========================================  CLKGEN MISC PWRONCLKENCRYPTO [11..11]  ========================================= */
typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENCRYPTO                                              */
  CLKGEN_MISC_PWRONCLKENCRYPTO_CRYPTOCLKENRST = 0,/*!< CRYPTOCLKENRST : Enable Cryto engine Clock to run during reset          */
  CLKGEN_MISC_PWRONCLKENCRYPTO_DEFEATURE = 1,   /*!< DEFEATURE : Chicken bit to revert to rev A                                */
} CLKGEN_MISC_PWRONCLKENCRYPTO_Enum;

/* ==========================================  CLKGEN MISC PWRONCLKENSDIO [10..10]  ========================================== */
typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENSDIO                                                */
  CLKGEN_MISC_PWRONCLKENSDIO_SDIOCLKENRST = 0,  /*!< SDIOCLKENRST : Enable SDIO Clock to run during reset                      */
  CLKGEN_MISC_PWRONCLKENSDIO_DEFEATURE = 1,     /*!< DEFEATURE : Chicken bit to revert to rev A                                */
} CLKGEN_MISC_PWRONCLKENSDIO_Enum;

/* ===========================================  CLKGEN MISC PWRONCLKENGFX [8..8]  ============================================ */
typedef enum {                                  /*!< CLKGEN_MISC_PWRONCLKENGFX                                                 */
  CLKGEN_MISC_PWRONCLKENGFX_GFXCLKENRST = 0,    /*!< GFXCLKENRST : Enable GFX Clock to run during reset                        */
  CLKGEN_MISC_PWRONCLKENGFX_DEFEATURE  = 1,     /*!< DEFEATURE : Chicken bit to revert to rev A                                */
} CLKGEN_MISC_PWRONCLKENGFX_Enum;

/* ==============================================  CLKGEN MISC FRCHFRC2 [5..5]  ============================================== */
typedef enum {                                  /*!< CLKGEN_MISC_FRCHFRC2                                                      */
  CLKGEN_MISC_FRCHFRC2_NOFRC           = 0,     /*!< NOFRC : Do not force HFRC2 on; stops in deep sleep mode.                  */
  CLKGEN_MISC_FRCHFRC2_FRC             = 1,     /*!< FRC : Force HFRC2 on; runs in deep sleep mode.                            */
} CLKGEN_MISC_FRCHFRC2_Enum;

/* ==========================================  CLKGEN MISC USEHFRC2FQ192MHZ [4..4]  ========================================== */
typedef enum {                                  /*!< CLKGEN_MISC_USEHFRC2FQ192MHZ                                              */
  CLKGEN_MISC_USEHFRC2FQ192MHZ_HFRCFQ192MHz = 0,/*!< HFRCFQ192MHz : Use HFRC-192MHz                                            */
  CLKGEN_MISC_USEHFRC2FQ192MHZ_HFRC2FQ192MHz = 1,/*!< HFRC2FQ192MHz : Use HFRC2-192MHz                                         */
} CLKGEN_MISC_USEHFRC2FQ192MHZ_Enum;

/* ==========================================  CLKGEN MISC USEHFRC2FQ96MHZ [3..3]  =========================================== */
typedef enum {                                  /*!< CLKGEN_MISC_USEHFRC2FQ96MHZ                                               */
  CLKGEN_MISC_USEHFRC2FQ96MHZ_HFRCFQ96MHz = 0,  /*!< HFRCFQ96MHz : Use HFRC-96MHz                                              */
  CLKGEN_MISC_USEHFRC2FQ96MHZ_HFRC2FQ96MHz = 1, /*!< HFRC2FQ96MHz : Use HFRC2-96MHz                                            */
} CLKGEN_MISC_USEHFRC2FQ96MHZ_Enum;

/* ==========================================  CLKGEN MISC USEHFRC2FQ48MHZ [2..2]  =========================================== */
typedef enum {                                  /*!< CLKGEN_MISC_USEHFRC2FQ48MHZ                                               */
  CLKGEN_MISC_USEHFRC2FQ48MHZ_HFRCFQ48MHz = 0,  /*!< HFRCFQ48MHz : Use HFRC-48MHz                                              */
  CLKGEN_MISC_USEHFRC2FQ48MHZ_HFRC2FQ48MHz = 1, /*!< HFRC2FQ48MHz : Use HFRC2-48MHz                                            */
} CLKGEN_MISC_USEHFRC2FQ48MHZ_Enum;

/* ============================================  CLKGEN MISC FRCBURSTOFF [1..1]  ============================================= */
typedef enum {                                  /*!< CLKGEN_MISC_FRCBURSTOFF                                                   */
  CLKGEN_MISC_FRCBURSTOFF_BURSTCLKON   = 0,     /*!< BURSTCLKON : fclk, hclk and fclk_wic are turned on during the
                                                     burst transition                                                          */
  CLKGEN_MISC_FRCBURSTOFF_BURSTCLKOFF  = 1,     /*!< BURSTCLKOFF : fclk, hclk and fclk are turned off during burst
                                                     transition                                                                */
} CLKGEN_MISC_FRCBURSTOFF_Enum;

/* ==============================================  CLKGEN MISC FRCHFRC [0..0]  =============================================== */
typedef enum {                                  /*!< CLKGEN_MISC_FRCHFRC                                                       */
  CLKGEN_MISC_FRCHFRC_NOFRC            = 0,     /*!< NOFRC : HFRC stops in deep sleep mode                                     */
  CLKGEN_MISC_FRCHFRC_FRC              = 1,     /*!< FRC : HFRC runs in deep sleep mode                                        */
} CLKGEN_MISC_FRCHFRC_Enum;

/* ========================================================  HF2ADJ0  ======================================================== */
/* =========================================  CLKGEN HF2ADJ0 HF2ADJFASTSTREN [1..1]  ========================================= */
typedef enum {                                  /*!< CLKGEN_HF2ADJ0_HF2ADJFASTSTREN                                            */
  CLKGEN_HF2ADJ0_HF2ADJFASTSTREN_DIS   = 0,     /*!< DIS : Fast_start_delay disable                                            */
  CLKGEN_HF2ADJ0_HF2ADJFASTSTREN_EN    = 1,     /*!< EN : Fast_start_delay enable                                              */
} CLKGEN_HF2ADJ0_HF2ADJFASTSTREN_Enum;

/* ============================================  CLKGEN HF2ADJ0 HF2ADJEN [0..0]  ============================================= */
typedef enum {                                  /*!< CLKGEN_HF2ADJ0_HF2ADJEN                                                   */
  CLKGEN_HF2ADJ0_HF2ADJEN_DIS          = 0,     /*!< DIS : HF2ADJ disable                                                      */
  CLKGEN_HF2ADJ0_HF2ADJEN_EN           = 1,     /*!< EN : HF2ADJ enable                                                        */
} CLKGEN_HF2ADJ0_HF2ADJEN_Enum;

/* ========================================================  HF2ADJ1  ======================================================== */
/* ==========================================  CLKGEN HF2ADJ1 HF2ADJTRIMEN [0..2]  =========================================== */
typedef enum {                                  /*!< CLKGEN_HF2ADJ1_HF2ADJTRIMEN                                               */
  CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN0 = 0,     /*!< TRIM_EN0 : 0                                                              */
  CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN1 = 1,     /*!< TRIM_EN1 : HF2ADJTRIMOUT                                                  */
  CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN2 = 2,     /*!< TRIM_EN2 : HF2ADJTRIMOFFSET                                               */
  CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN3 = 3,     /*!< TRIM_EN3 : HF2ADJTRIMOUT + HF2ADJTRIMOFFSET                               */
  CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN4 = 4,     /*!< TRIM_EN4 : HF2TUNE                                                        */
  CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN5 = 5,     /*!< TRIM_EN5 : HF2ADJTRIMOUT + HF2TUNE                                        */
  CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN6 = 6,     /*!< TRIM_EN6 : HF2ADJTRIMOFFSET + HF2TUNE                                     */
  CLKGEN_HF2ADJ1_HF2ADJTRIMEN_TRIM_EN7 = 7,     /*!< TRIM_EN7 : HF2ADJTRIMOUT + HF2ADJTRIMOFFSET + HF2TUNE                     */
} CLKGEN_HF2ADJ1_HF2ADJTRIMEN_Enum;

/* ========================================================  HF2ADJ2  ======================================================== */
/* =======================================  CLKGEN HF2ADJ2 HF2ADJXTALDIVRATIO [0..1]  ======================================== */
typedef enum {                                  /*!< CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO                                         */
  CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_XTAL32M = 0,/*!< XTAL32M : XTAL32MHz                                                       */
  CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_XTAL32M_DIV2 = 1,/*!< XTAL32M_DIV2 : XTAL32MHz / 2                                         */
  CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_XTAL32M_DIV4 = 2,/*!< XTAL32M_DIV4 : XTAL32MHz / 4                                         */
  CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_XTAL32M_DIV8 = 3,/*!< XTAL32M_DIV8 : XTAL32MHz / 8                                         */
} CLKGEN_HF2ADJ2_HF2ADJXTALDIVRATIO_Enum;

/* ========================================================  HF2VAL  ========================================================= */
/* =======================================================  LFRCCTRL  ======================================================== */
/* ======================================================  DISPCLKCTRL  ====================================================== */
/* =========================================  CLKGEN DISPCLKCTRL DISPCLKSEL [4..5]  ========================================== */
typedef enum {                                  /*!< CLKGEN_DISPCLKCTRL_DISPCLKSEL                                             */
  CLKGEN_DISPCLKCTRL_DISPCLKSEL_OFF    = 0,     /*!< OFF : Static value of 0 selected for DPHY clock input                     */
  CLKGEN_DISPCLKCTRL_DISPCLKSEL_HFRC48 = 1,     /*!< HFRC48 : 48MHz sourced from the HFRC                                      */
  CLKGEN_DISPCLKCTRL_DISPCLKSEL_HFRC96 = 2,     /*!< HFRC96 : 96MHz sourced from the HFRC                                      */
  CLKGEN_DISPCLKCTRL_DISPCLKSEL_DPHYPLL = 3,    /*!< DPHYPLL : DPHY PLL                                                        */
} CLKGEN_DISPCLKCTRL_DISPCLKSEL_Enum;

/* ==========================================  CLKGEN DISPCLKCTRL PLLCLKSEL [0..1]  ========================================== */
typedef enum {                                  /*!< CLKGEN_DISPCLKCTRL_PLLCLKSEL                                              */
  CLKGEN_DISPCLKCTRL_PLLCLKSEL_OFF     = 0,     /*!< OFF : Static value of 0 selected for DPHY clock input                     */
  CLKGEN_DISPCLKCTRL_PLLCLKSEL_HFRC12  = 1,     /*!< HFRC12 : 12MHz sourced from the HFRC                                      */
  CLKGEN_DISPCLKCTRL_PLLCLKSEL_HFRC6   = 2,     /*!< HFRC6 : 6MHz sourced from the HFRC                                        */
  CLKGEN_DISPCLKCTRL_PLLCLKSEL_HFXT_16 = 3,     /*!< HFXT_16 : High Frequency XTAL input (16MHz)                               */
} CLKGEN_DISPCLKCTRL_PLLCLKSEL_Enum;

/* =====================================================  CLKGENSPARES  ====================================================== */
/* ===================================================  HFRCIDLECOUNTERS  ==================================================== */
/* =======================================================  INTRPTEN  ======================================================== */
/* ======================================================  INTRPTSTAT  ======================================================= */
/* =======================================================  INTRPTCLR  ======================================================= */
/* =======================================================  INTRPTSET  ======================================================= */


/* =========================================================================================================================== */
/* ================                                            CPU                                            ================ */
/* =========================================================================================================================== */

/* =======================================================  CACHECFG  ======================================================== */
/* ==============================================  CPU CACHECFG CONFIG [4..7]  =============================================== */
typedef enum {                                  /*!< CPU_CACHECFG_CONFIG                                                       */
  CPU_CACHECFG_CONFIG_W1_128B_512E     = 4,     /*!< W1_128B_512E : Direct mapped, 128-bit linesize, 512 entries
                                                     (4 SRAMs active)                                                          */
  CPU_CACHECFG_CONFIG_W2_128B_512E     = 5,     /*!< W2_128B_512E : Two-way set associative, 128-bit linesize, 512
                                                     entries (8 SRAMs active)                                                  */
  CPU_CACHECFG_CONFIG_W1_128B_1024E    = 8,     /*!< W1_128B_1024E : Direct mapped, 128-bit linesize, 1024 entries
                                                     (8 SRAMs active)                                                          */
  CPU_CACHECFG_CONFIG_W1_128B_2048E    = 12,    /*!< W1_128B_2048E : Direct mapped, 128-bit linesize, 2048 entries
                                                     (4 SRAMs active)                                                          */
  CPU_CACHECFG_CONFIG_W2_128B_2048E    = 13,    /*!< W2_128B_2048E : Two-way set associative, 128-bit linesize, 2048
                                                     entries (8 SRAMs active)                                                  */
  CPU_CACHECFG_CONFIG_W1_128B_4096E    = 14,    /*!< W1_128B_4096E : Direct mapped, 128-bit linesize, 4096 entries
                                                     (8 SRAMs active)                                                          */
} CPU_CACHECFG_CONFIG_Enum;

/* =======================================================  CACHECTRL  ======================================================= */
/* ============================================  CPU CACHECTRL RESETSTAT [1..1]  ============================================= */
typedef enum {                                  /*!< CPU_CACHECTRL_RESETSTAT                                                   */
  CPU_CACHECTRL_RESETSTAT_CLEAR        = 1,     /*!< CLEAR : Clear Cache Stats                                                 */
  CPU_CACHECTRL_RESETSTAT_DEFAULT      = 0,     /*!< DEFAULT : default Cache Stats                                             */
} CPU_CACHECTRL_RESETSTAT_Enum;

/* =======================================================  NCR0START  ======================================================= */
/* ========================================================  NCR0END  ======================================================== */
/* =======================================================  NCR1START  ======================================================= */
/* ========================================================  NCR1END  ======================================================== */
/* ========================================================  DAXICFG  ======================================================== */
/* ==========================================  CPU DAXICFG MRUGROUPLEVEL [24..25]  =========================================== */
typedef enum {                                  /*!< CPU_DAXICFG_MRUGROUPLEVEL                                                 */
  CPU_DAXICFG_MRUGROUPLEVEL_MAX        = 0,     /*!< MAX : Maximum level for current number of buffers enabled.                */
  CPU_DAXICFG_MRUGROUPLEVEL_ONELESSTHANMAX = 1, /*!< ONELESSTHANMAX : One less than maximum level or zero for current
                                                     number of buffers enabled.                                                */
  CPU_DAXICFG_MRUGROUPLEVEL_TWOLESSTHANMAX = 2, /*!< TWOLESSTHANMAX : Two less than maximum level or zero for current
                                                     number of buffers enabled.                                                */
  CPU_DAXICFG_MRUGROUPLEVEL_THREELESSTHANMAX = 3,/*!< THREELESSTHANMAX : Three less than maximum level or zero for
                                                     current number of buffers enabled.                                        */
} CPU_DAXICFG_MRUGROUPLEVEL_Enum;

/* ===========================================  CPU DAXICFG AGINGCOUNTER [16..20]  =========================================== */
typedef enum {                                  /*!< CPU_DAXICFG_AGINGCOUNTER                                                  */
  CPU_DAXICFG_AGINGCOUNTER_ONE         = 0,     /*!< ONE : One step per age                                                    */
  CPU_DAXICFG_AGINGCOUNTER_TWO         = 1,     /*!< TWO : Two steps per age                                                   */
  CPU_DAXICFG_AGINGCOUNTER_FOUR        = 2,     /*!< FOUR : Four steps per age                                                 */
  CPU_DAXICFG_AGINGCOUNTER_EIGHT       = 3,     /*!< EIGHT : EIGHT steps per age                                               */
  CPU_DAXICFG_AGINGCOUNTER_SIXTEEN     = 4,     /*!< SIXTEEN : Sixteen steps per age                                           */
  CPU_DAXICFG_AGINGCOUNTER_THIRTYTWO   = 5,     /*!< THIRTYTWO : Thirty-two steps per age                                      */
  CPU_DAXICFG_AGINGCOUNTER_SIXTYFOUR   = 6,     /*!< SIXTYFOUR : 64 steps per age                                              */
  CPU_DAXICFG_AGINGCOUNTER_ONEHUNDREDTWENTYEIGHT = 7,/*!< ONEHUNDREDTWENTYEIGHT : One hundred twenty-eight steps per age       */
  CPU_DAXICFG_AGINGCOUNTER_TWOHUNDEREDFIFTYSIX = 8,/*!< TWOHUNDEREDFIFTYSIX : Two hundred fifty-six steps per age              */
  CPU_DAXICFG_AGINGCOUNTER_FIVEHUNDREDTWELVE = 9,/*!< FIVEHUNDREDTWELVE : Five hundred twelve steps per age                    */
  CPU_DAXICFG_AGINGCOUNTER_ONEK        = 10,    /*!< ONEK : One thousand twenty-four steps per age                             */
  CPU_DAXICFG_AGINGCOUNTER_TWOK        = 11,    /*!< TWOK : Two thousand forty-eight steps per age                             */
  CPU_DAXICFG_AGINGCOUNTER_FOURK       = 12,    /*!< FOURK : Four thousand ninety-six steps per age                            */
  CPU_DAXICFG_AGINGCOUNTER_EIGHTK      = 13,    /*!< EIGHTK : Eight thousand one hundred ninety-two steps per age              */
  CPU_DAXICFG_AGINGCOUNTER_SIXTEENK    = 14,    /*!< SIXTEENK : Sixteen thousand three hundred eighty-four steps
                                                     per age                                                                   */
  CPU_DAXICFG_AGINGCOUNTER_THIRTYTWOK  = 15,    /*!< THIRTYTWOK : Thirty-two thousand seven hundred sixty-eight steps
                                                     per age                                                                   */
  CPU_DAXICFG_AGINGCOUNTER_SIXTYFOURK  = 16,    /*!< SIXTYFOURK : Sixty-fix thousand five hundred thirty-six steps
                                                     per age                                                                   */
} CPU_DAXICFG_AGINGCOUNTER_Enum;

/* ===========================================  CPU DAXICFG BUFFERENABLE [8..11]  ============================================ */
typedef enum {                                  /*!< CPU_DAXICFG_BUFFERENABLE                                                  */
  CPU_DAXICFG_BUFFERENABLE_ONE         = 0,     /*!< ONE : One buffer mode enabled.                                            */
  CPU_DAXICFG_BUFFERENABLE_TWO         = 1,     /*!< TWO : Two buffers enabled.                                                */
  CPU_DAXICFG_BUFFERENABLE_THREE       = 2,     /*!< THREE : Three buffers enabled.                                            */
  CPU_DAXICFG_BUFFERENABLE_FOUR        = 3,     /*!< FOUR : Four buffers enabled.                                              */
  CPU_DAXICFG_BUFFERENABLE_FIVE        = 4,     /*!< FIVE : Five buffers enabled.                                              */
  CPU_DAXICFG_BUFFERENABLE_SIX         = 5,     /*!< SIX : Six buffers enabled.                                                */
  CPU_DAXICFG_BUFFERENABLE_SEVEN       = 6,     /*!< SEVEN : Seven buffers enabled.                                            */
  CPU_DAXICFG_BUFFERENABLE_EIGHT       = 7,     /*!< EIGHT : Eight buffers enabled.                                            */
  CPU_DAXICFG_BUFFERENABLE_THIRTEEN    = 8,     /*!< THIRTEEN : Eight buffers enabled.                                         */
  CPU_DAXICFG_BUFFERENABLE_FOURTEEN    = 9,     /*!< FOURTEEN : Eight buffers enabled.                                         */
  CPU_DAXICFG_BUFFERENABLE_FIFTEEN     = 10,    /*!< FIFTEEN : Eight buffers enabled.                                          */
  CPU_DAXICFG_BUFFERENABLE_SIXTEEN     = 11,    /*!< SIXTEEN : Eight buffers enabled.                                          */
  CPU_DAXICFG_BUFFERENABLE_TWENTYNINE  = 12,    /*!< TWENTYNINE : Twenty-nine buffers enabled.                                 */
  CPU_DAXICFG_BUFFERENABLE_THIRTY      = 13,    /*!< THIRTY : Thirty buffers enabled.                                          */
  CPU_DAXICFG_BUFFERENABLE_THIRTYONE   = 14,    /*!< THIRTYONE : Thirty-one buffers enabled.                                   */
  CPU_DAXICFG_BUFFERENABLE_THIRTYTWO   = 15,    /*!< THIRTYTWO : Thirty-two buffers enabled.                                   */
} CPU_DAXICFG_BUFFERENABLE_Enum;

/* =========================================  CPU DAXICFG DAXISTATECLKGATEEN [5..5]  ========================================= */
typedef enum {                                  /*!< CPU_DAXICFG_DAXISTATECLKGATEEN                                            */
  CPU_DAXICFG_DAXISTATECLKGATEEN_EN    = 0,     /*!< EN : Enable clock gating of DAXI state.                                   */
  CPU_DAXICFG_DAXISTATECLKGATEEN_DIS   = 1,     /*!< DIS : Disable clock gating of DAXI state.                                 */
} CPU_DAXICFG_DAXISTATECLKGATEEN_Enum;

/* =========================================  CPU DAXICFG DAXIDATACLKGATEEN [4..4]  ========================================== */
typedef enum {                                  /*!< CPU_DAXICFG_DAXIDATACLKGATEEN                                             */
  CPU_DAXICFG_DAXIDATACLKGATEEN_EN     = 0,     /*!< EN : Enable clock gating of DAXI line buffer data.                        */
  CPU_DAXICFG_DAXIDATACLKGATEEN_DIS    = 1,     /*!< DIS : Disable clock gating of DAXI line buffer data.                      */
} CPU_DAXICFG_DAXIDATACLKGATEEN_Enum;

/* ==========================================  CPU DAXICFG DAXIBECLKGATEEN [3..3]  =========================================== */
typedef enum {                                  /*!< CPU_DAXICFG_DAXIBECLKGATEEN                                               */
  CPU_DAXICFG_DAXIBECLKGATEEN_EN       = 0,     /*!< EN : Enable clock gating of DAXI line buffer byte enables.                */
  CPU_DAXICFG_DAXIBECLKGATEEN_DIS      = 1,     /*!< DIS : Disable clock gating of DAXI line buffer byte enables.              */
} CPU_DAXICFG_DAXIBECLKGATEEN_Enum;

/* ==========================================  CPU DAXICFG DAXIPASSTHROUGH [2..2]  =========================================== */
typedef enum {                                  /*!< CPU_DAXICFG_DAXIPASSTHROUGH                                               */
  CPU_DAXICFG_DAXIPASSTHROUGH_DIS      = 0,     /*!< DIS : Disable pass through mode, caching lines in DAXI enabled.           */
  CPU_DAXICFG_DAXIPASSTHROUGH_EN       = 1,     /*!< EN : Enable pass through mode, caching lines in DAXI disabled.            */
} CPU_DAXICFG_DAXIPASSTHROUGH_Enum;

/* ============================================  CPU DAXICFG AGINGSENABLE [1..1]  ============================================ */
typedef enum {                                  /*!< CPU_DAXICFG_AGINGSENABLE                                                  */
  CPU_DAXICFG_AGINGSENABLE_DIS         = 0,     /*!< DIS : Flushing out shared entries using aging mechanism disabled.         */
  CPU_DAXICFG_AGINGSENABLE_EN          = 1,     /*!< EN : Flushing out shared entries using aging mechanism enabled.           */
} CPU_DAXICFG_AGINGSENABLE_Enum;

/* =============================================  CPU DAXICFG FLUSHLEVEL [0..0]  ============================================= */
typedef enum {                                  /*!< CPU_DAXICFG_FLUSHLEVEL                                                    */
  CPU_DAXICFG_FLUSHLEVEL_TWO           = 0,     /*!< TWO : Flush out dirty buffers if 3 or more ane enabled and less
                                                     than two are free or if 2 are enabled and none are free.                  */
  CPU_DAXICFG_FLUSHLEVEL_THREE         = 1,     /*!< THREE : Flush out dirty buffers if 3 or more are enabled less
                                                     than three are free or if 2 are enabled and less then two
                                                     are free.                                                                 */
} CPU_DAXICFG_FLUSHLEVEL_Enum;

/* =======================================================  DAXICTRL  ======================================================== */
/* ====================================================  ICODEFAULTADDR  ===================================================== */
/* ====================================================  DCODEFAULTADDR  ===================================================== */
/* =====================================================  SYSFAULTADDR  ====================================================== */
/* ======================================================  FAULTSTATUS  ====================================================== */
/* ============================================  CPU FAULTSTATUS SYSFAULT [2..2]  ============================================ */
typedef enum {                                  /*!< CPU_FAULTSTATUS_SYSFAULT                                                  */
  CPU_FAULTSTATUS_SYSFAULT_NOFAULT     = 0,     /*!< NOFAULT : No bus fault has been detected.                                 */
  CPU_FAULTSTATUS_SYSFAULT_FAULT       = 1,     /*!< FAULT : Bus fault detected.                                               */
} CPU_FAULTSTATUS_SYSFAULT_Enum;

/* ===========================================  CPU FAULTSTATUS DCODEFAULT [1..1]  =========================================== */
typedef enum {                                  /*!< CPU_FAULTSTATUS_DCODEFAULT                                                */
  CPU_FAULTSTATUS_DCODEFAULT_NOFAULT   = 0,     /*!< NOFAULT : No DCODE fault has been detected.                               */
  CPU_FAULTSTATUS_DCODEFAULT_FAULT     = 1,     /*!< FAULT : DCODE fault detected.                                             */
} CPU_FAULTSTATUS_DCODEFAULT_Enum;

/* ===========================================  CPU FAULTSTATUS ICODEFAULT [0..0]  =========================================== */
typedef enum {                                  /*!< CPU_FAULTSTATUS_ICODEFAULT                                                */
  CPU_FAULTSTATUS_ICODEFAULT_NOFAULT   = 0,     /*!< NOFAULT : No ICODE fault has been detected.                               */
  CPU_FAULTSTATUS_ICODEFAULT_FAULT     = 1,     /*!< FAULT : ICODE fault detected.                                             */
} CPU_FAULTSTATUS_ICODEFAULT_Enum;

/* ====================================================  FAULTCAPTUREEN  ===================================================== */
/* =======================================  CPU FAULTCAPTUREEN FAULTCAPTUREEN [0..0]  ======================================== */
typedef enum {                                  /*!< CPU_FAULTCAPTUREEN_FAULTCAPTUREEN                                         */
  CPU_FAULTCAPTUREEN_FAULTCAPTUREEN_DIS = 0,    /*!< DIS : Disable fault capture.                                              */
  CPU_FAULTCAPTUREEN_FAULTCAPTUREEN_EN = 1,     /*!< EN : Enable fault capture.                                                */
} CPU_FAULTCAPTUREEN_FAULTCAPTUREEN_Enum;

/* =========================================================  INTEN  ========================================================= */
/* ========================================================  INTSTAT  ======================================================== */
/* ========================================================  INTCLR  ========================================================= */
/* ========================================================  INTSET  ========================================================= */
/* =====================================================  WRITEERRADDR  ====================================================== */
/* =========================================================  DMON0  ========================================================= */
/* =========================================================  DMON1  ========================================================= */
/* =========================================================  DMON2  ========================================================= */
/* =========================================================  DMON3  ========================================================= */
/* =========================================================  IMON0  ========================================================= */
/* =========================================================  IMON1  ========================================================= */
/* =========================================================  IMON2  ========================================================= */
/* =========================================================  IMON3  ========================================================= */


/* =========================================================================================================================== */
/* ================                                          CRYPTO                                           ================ */
/* =========================================================================================================================== */

/* ======================================================  MEMORYMAP0  ======================================================= */
/* ======================================================  MEMORYMAP1  ======================================================= */
/* ======================================================  MEMORYMAP2  ======================================================= */
/* ======================================================  MEMORYMAP3  ======================================================= */
/* ======================================================  MEMORYMAP4  ======================================================= */
/* ======================================================  MEMORYMAP5  ======================================================= */
/* ======================================================  MEMORYMAP6  ======================================================= */
/* ======================================================  MEMORYMAP7  ======================================================= */
/* ======================================================  MEMORYMAP8  ======================================================= */
/* ======================================================  MEMORYMAP9  ======================================================= */
/* ======================================================  MEMORYMAP10  ====================================================== */
/* ======================================================  MEMORYMAP11  ====================================================== */
/* ======================================================  MEMORYMAP12  ====================================================== */
/* ======================================================  MEMORYMAP13  ====================================================== */
/* ======================================================  MEMORYMAP14  ====================================================== */
/* ======================================================  MEMORYMAP15  ====================================================== */
/* ======================================================  MEMORYMAP16  ====================================================== */
/* ======================================================  MEMORYMAP17  ====================================================== */
/* ======================================================  MEMORYMAP18  ====================================================== */
/* ======================================================  MEMORYMAP19  ====================================================== */
/* ======================================================  MEMORYMAP20  ====================================================== */
/* ======================================================  MEMORYMAP21  ====================================================== */
/* ======================================================  MEMORYMAP22  ====================================================== */
/* ======================================================  MEMORYMAP23  ====================================================== */
/* ======================================================  MEMORYMAP24  ====================================================== */
/* ======================================================  MEMORYMAP25  ====================================================== */
/* ======================================================  MEMORYMAP26  ====================================================== */
/* ======================================================  MEMORYMAP27  ====================================================== */
/* ======================================================  MEMORYMAP28  ====================================================== */
/* ======================================================  MEMORYMAP29  ====================================================== */
/* ======================================================  MEMORYMAP30  ====================================================== */
/* ======================================================  MEMORYMAP31  ====================================================== */
/* ========================================================  OPCODE  ========================================================= */
/* =============================================  CRYPTO OPCODE OPCODE [27..31]  ============================================= */
typedef enum {                                  /*!< CRYPTO_OPCODE_OPCODE                                                      */
  CRYPTO_OPCODE_OPCODE_ADD             = 4,     /*!< ADD : Add,Inc opcode                                                      */
  CRYPTO_OPCODE_OPCODE_SUB             = 5,     /*!< SUB : Sub,Dec,Neg opcode                                                  */
  CRYPTO_OPCODE_OPCODE_MODADD          = 6,     /*!< MODADD : ModAdd,ModInc opcode                                             */
  CRYPTO_OPCODE_OPCODE_MODSUB          = 7,     /*!< MODSUB : ModSub,ModDec,ModNeg opcode                                      */
  CRYPTO_OPCODE_OPCODE_AND             = 8,     /*!< AND : AND,TST0,CLR0 opcode                                                */
  CRYPTO_OPCODE_OPCODE_OR              = 9,     /*!< OR : OR,COPY,SET0 opcode                                                  */
  CRYPTO_OPCODE_OPCODE_XOR             = 10,    /*!< XOR : XOR,FLIP0,INVERT,COMPARE opcode                                     */
  CRYPTO_OPCODE_OPCODE_SHR0            = 12,    /*!< SHR0 : SHR0 opcode                                                        */
  CRYPTO_OPCODE_OPCODE_SHR1            = 13,    /*!< SHR1 : SHR1 opcode                                                        */
  CRYPTO_OPCODE_OPCODE_SHL0            = 14,    /*!< SHL0 : SHL0 opcode                                                        */
  CRYPTO_OPCODE_OPCODE_SHL1            = 15,    /*!< SHL1 : SHL1 opcode                                                        */
  CRYPTO_OPCODE_OPCODE_MULLOW          = 16,    /*!< MULLOW : MulLow opcode                                                    */
  CRYPTO_OPCODE_OPCODE_MODMUL          = 17,    /*!< MODMUL : ModMul opcode                                                    */
  CRYPTO_OPCODE_OPCODE_MODMULN         = 18,    /*!< MODMULN : ModMulN opcode                                                  */
  CRYPTO_OPCODE_OPCODE_MODEXP          = 19,    /*!< MODEXP : ModExp opcode                                                    */
  CRYPTO_OPCODE_OPCODE_DIVISION        = 20,    /*!< DIVISION : Division opcode                                                */
  CRYPTO_OPCODE_OPCODE_DIV             = 21,    /*!< DIV : Div opcode                                                          */
  CRYPTO_OPCODE_OPCODE_MODDIV          = 22,    /*!< MODDIV : ModDiv opcode                                                    */
  CRYPTO_OPCODE_OPCODE_TERMINATE       = 0,     /*!< TERMINATE : Terminate opcode                                              */
} CRYPTO_OPCODE_OPCODE_Enum;

/* ======================================================  NNPT0T1ADDR  ====================================================== */
/* =======================================================  PKASTATUS  ======================================================= */
/* ======================================================  PKASWRESET  ======================================================= */
/* =========================================================  PKAL0  ========================================================= */
/* =========================================================  PKAL1  ========================================================= */
/* =========================================================  PKAL2  ========================================================= */
/* =========================================================  PKAL3  ========================================================= */
/* =========================================================  PKAL4  ========================================================= */
/* =========================================================  PKAL5  ========================================================= */
/* =========================================================  PKAL6  ========================================================= */
/* =========================================================  PKAL7  ========================================================= */
/* ======================================================  PKAPIPERDY  ======================================================= */
/* ========================================================  PKADONE  ======================================================== */
/* =====================================================  PKAMONSELECT  ====================================================== */
/* ======================================================  PKAVERSION  ======================================================= */
/* ======================================================  PKAMONREAD  ======================================================= */
/* ======================================================  PKASRAMADDR  ====================================================== */
/* =====================================================  PKASRAMWDATA  ====================================================== */
/* =====================================================  PKASRAMRDATA  ====================================================== */
/* =====================================================  PKASRAMWRCLR  ====================================================== */
/* =====================================================  PKASRAMRADDR  ====================================================== */
/* =====================================================  PKAWORDACCESS  ===================================================== */
/* ======================================================  PKABUFFADDR  ====================================================== */
/* ========================================================  RNGIMR  ========================================================= */
/* ========================================================  RNGISR  ========================================================= */
/* ==========================================  CRYPTO RNGISR WHICHKATERR [25..26]  =========================================== */
typedef enum {                                  /*!< CRYPTO_RNGISR_WHICHKATERR                                                 */
  CRYPTO_RNGISR_WHICHKATERR_INSTANT_1  = 0,     /*!< INSTANT_1 : first test of instantiation                                   */
  CRYPTO_RNGISR_WHICHKATERR_INSTANT_2  = 1,     /*!< INSTANT_2 : second test of instantiation                                  */
  CRYPTO_RNGISR_WHICHKATERR_RESEED_1   = 2,     /*!< RESEED_1 : first test of reseeding                                        */
  CRYPTO_RNGISR_WHICHKATERR_RESEED_2   = 3,     /*!< RESEED_2 : second test of reseeding                                       */
} CRYPTO_RNGISR_WHICHKATERR_Enum;

/* ========================================================  RNGICR  ========================================================= */
/* ======================================================  TRNGCONFIG  ======================================================= */
/* ============================================  CRYPTO TRNGCONFIG SOPSEL [2..2]  ============================================ */
typedef enum {                                  /*!< CRYPTO_TRNGCONFIG_SOPSEL                                                  */
  CRYPTO_TRNGCONFIG_SOPSEL_SOP_DATA_1  = 1,     /*!< SOP_DATA_1 : sop_data port reflects TRNG output (EHR_DATA).               */
  CRYPTO_TRNGCONFIG_SOPSEL_SOP_DATA_2  = 0,     /*!< SOP_DATA_2 : sop_data port reflects PRNG output (RNG_READOUT).
                                                     Note: Secure output is used for direct connection of the
                                                     RNG block outputs to an engine input key.                                 */
} CRYPTO_TRNGCONFIG_SOPSEL_Enum;

/* =======================================================  TRNGVALID  ======================================================= */
/* =======================================================  EHRDATA0  ======================================================== */
/* =======================================================  EHRDATA1  ======================================================== */
/* =======================================================  EHRDATA2  ======================================================== */
/* =======================================================  EHRDATA3  ======================================================== */
/* =======================================================  EHRDATA4  ======================================================== */
/* =======================================================  EHRDATA5  ======================================================== */
/* ====================================================  RNDSOURCEENABLE  ==================================================== */
/* ======================================================  SAMPLECNT1  ======================================================= */
/* ===================================================  AUTOCORRSTATISTIC  =================================================== */
/* ===================================================  TRNGDEBUGCONTROL  ==================================================== */
/* ======================================================  RNGSWRESET  ======================================================= */
/* ====================================================  RNGDEBUGENINPUT  ==================================================== */
/* ========================================================  RNGBUSY  ======================================================== */
/* ====================================================  RSTBITSCOUNTER  ===================================================== */
/* ======================================================  RNGVERSION  ======================================================= */
/* ========================================  CRYPTO RNGVERSION RNGUSE5SBOXES [7..7]  ========================================= */
typedef enum {                                  /*!< CRYPTO_RNGVERSION_RNGUSE5SBOXES                                           */
  CRYPTO_RNGVERSION_RNGUSE5SBOXES_20_SBOX_AES = 0,/*!< 20_SBOX_AES : 20 SBOX AES                                               */
  CRYPTO_RNGVERSION_RNGUSE5SBOXES_5_SBOX_AES = 1,/*!< 5_SBOX_AES : 5 SBOX AES                                                  */
} CRYPTO_RNGVERSION_RNGUSE5SBOXES_Enum;

/* =======================================  CRYPTO RNGVERSION RESEEDINGEXISTS [6..6]  ======================================== */
typedef enum {                                  /*!< CRYPTO_RNGVERSION_RESEEDINGEXISTS                                         */
  CRYPTO_RNGVERSION_RESEEDINGEXISTS_EXISTS = 1, /*!< EXISTS : exists                                                           */
  CRYPTO_RNGVERSION_RESEEDINGEXISTS_NORESEED = 0,/*!< NORESEED : Reseed does not exists                                        */
} CRYPTO_RNGVERSION_RESEEDINGEXISTS_Enum;

/* ==========================================  CRYPTO RNGVERSION KATEXISTS [5..5]  =========================================== */
typedef enum {                                  /*!< CRYPTO_RNGVERSION_KATEXISTS                                               */
  CRYPTO_RNGVERSION_KATEXISTS_NO_EXIST = 0,     /*!< NO_EXIST : does not exist                                                 */
  CRYPTO_RNGVERSION_KATEXISTS_EXISTS   = 1,     /*!< EXISTS : exists                                                           */
} CRYPTO_RNGVERSION_KATEXISTS_Enum;

/* ==========================================  CRYPTO RNGVERSION PRNGEXISTS [4..4]  ========================================== */
typedef enum {                                  /*!< CRYPTO_RNGVERSION_PRNGEXISTS                                              */
  CRYPTO_RNGVERSION_PRNGEXISTS_NO_EXIST = 0,    /*!< NO_EXIST : does not exist                                                 */
  CRYPTO_RNGVERSION_PRNGEXISTS_EXISTS  = 1,     /*!< EXISTS : exists                                                           */
} CRYPTO_RNGVERSION_PRNGEXISTS_Enum;

/* ======================================  CRYPTO RNGVERSION TRNGTESTSBYPASSEN [3..3]  ======================================= */
typedef enum {                                  /*!< CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN                                       */
  CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN_TRNG_NE = 0,/*!< TRNG_NE : trng tests bypass not enabled                                 */
  CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN_TRNG_E = 1,/*!< TRNG_E : trng tests bypass enabled                                       */
} CRYPTO_RNGVERSION_TRNGTESTSBYPASSEN_Enum;

/* ========================================  CRYPTO RNGVERSION AUTOCORREXISTS [2..2]  ======================================== */
typedef enum {                                  /*!< CRYPTO_RNGVERSION_AUTOCORREXISTS                                          */
  CRYPTO_RNGVERSION_AUTOCORREXISTS_NO_EXIST = 0,/*!< NO_EXIST : does not exist                                                 */
  CRYPTO_RNGVERSION_AUTOCORREXISTS_EXISTS = 1,  /*!< EXISTS : exists                                                           */
} CRYPTO_RNGVERSION_AUTOCORREXISTS_Enum;

/* =========================================  CRYPTO RNGVERSION CRNGTEXISTS [1..1]  ========================================== */
typedef enum {                                  /*!< CRYPTO_RNGVERSION_CRNGTEXISTS                                             */
  CRYPTO_RNGVERSION_CRNGTEXISTS_NO_EXIST = 0,   /*!< NO_EXIST : does not exist                                                 */
  CRYPTO_RNGVERSION_CRNGTEXISTS_EXISTS = 1,     /*!< EXISTS : exists                                                           */
} CRYPTO_RNGVERSION_CRNGTEXISTS_Enum;

/* =========================================  CRYPTO RNGVERSION EHRWIDTH192 [0..0]  ========================================== */
typedef enum {                                  /*!< CRYPTO_RNGVERSION_EHRWIDTH192                                             */
  CRYPTO_RNGVERSION_EHRWIDTH192_128_EHR = 0,    /*!< 128_EHR : 128 bit EHR                                                     */
  CRYPTO_RNGVERSION_EHRWIDTH192_192_EHR = 1,    /*!< 192_EHR : 192 bit EHR                                                     */
} CRYPTO_RNGVERSION_EHRWIDTH192_Enum;

/* =====================================================  RNGCLKENABLE  ====================================================== */
/* =====================================================  RNGDMAENABLE  ====================================================== */
/* =====================================================  RNGDMASRCMASK  ===================================================== */
/* ====================================================  RNGDMASRAMADDR  ===================================================== */
/* ====================================================  RNGWATCHDOGVAL  ===================================================== */
/* =====================================================  RNGDMASTATUS  ====================================================== */
/* ===================================================  CHACHACONTROLREG  ==================================================== */
/* ======================================  CRYPTO CHACHACONTROLREG NUMOFROUNDS [4..5]  ======================================= */
typedef enum {                                  /*!< CRYPTO_CHACHACONTROLREG_NUMOFROUNDS                                       */
  CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_20_ROUNDS = 0,/*!< 20_ROUNDS : 20 rounds                                                 */
  CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_12_ROUNDS = 1,/*!< 12_ROUNDS : 12 rounds                                                 */
  CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_8_ROUNDS = 2,/*!< 8_ROUNDS : 8 rounds                                                    */
  CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_N_A = 3,  /*!< N_A : Not applicable                                                      */
} CRYPTO_CHACHACONTROLREG_NUMOFROUNDS_Enum;

/* =========================================  CRYPTO CHACHACONTROLREG KEYLEN [3..3]  ========================================= */
typedef enum {                                  /*!< CRYPTO_CHACHACONTROLREG_KEYLEN                                            */
  CRYPTO_CHACHACONTROLREG_KEYLEN_256_BIT = 0,   /*!< 256_BIT : 256 bit.                                                        */
  CRYPTO_CHACHACONTROLREG_KEYLEN_128_BIT = 1,   /*!< 128_BIT : 128 bit.                                                        */
} CRYPTO_CHACHACONTROLREG_KEYLEN_Enum;

/* ===================================  CRYPTO CHACHACONTROLREG CALCKEYFORPOLY1305 [2..2]  =================================== */
typedef enum {                                  /*!< CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305                                */
  CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305_DISABLE = 0,/*!< DISABLE : disable.                                               */
  CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305_ENABLE = 1,/*!< ENABLE : enable.                                                  */
} CRYPTO_CHACHACONTROLREG_CALCKEYFORPOLY1305_Enum;

/* ======================================  CRYPTO CHACHACONTROLREG INITFROMHOST [1..1]  ====================================== */
typedef enum {                                  /*!< CRYPTO_CHACHACONTROLREG_INITFROMHOST                                      */
  CRYPTO_CHACHACONTROLREG_INITFROMHOST_DISABLE = 0,/*!< DISABLE : disable.                                                     */
  CRYPTO_CHACHACONTROLREG_INITFROMHOST_ENABLE = 1,/*!< ENABLE : enable.                                                        */
} CRYPTO_CHACHACONTROLREG_INITFROMHOST_Enum;

/* =====================================  CRYPTO CHACHACONTROLREG CHACHAORSALSA [0..0]  ====================================== */
typedef enum {                                  /*!< CRYPTO_CHACHACONTROLREG_CHACHAORSALSA                                     */
  CRYPTO_CHACHACONTROLREG_CHACHAORSALSA_CHACHA = 0,/*!< CHACHA : ChaCha mode,                                                  */
  CRYPTO_CHACHACONTROLREG_CHACHAORSALSA_SALSA = 1,/*!< SALSA : Salsa mode.                                                     */
} CRYPTO_CHACHACONTROLREG_CHACHAORSALSA_Enum;

/* =====================================================  CHACHAVERSION  ===================================================== */
/* ======================================================  CHACHAKEY0  ======================================================= */
/* ======================================================  CHACHAKEY1  ======================================================= */
/* ======================================================  CHACHAKEY2  ======================================================= */
/* ======================================================  CHACHAKEY3  ======================================================= */
/* ======================================================  CHACHAKEY4  ======================================================= */
/* ======================================================  CHACHAKEY5  ======================================================= */
/* ======================================================  CHACHAKEY6  ======================================================= */
/* ======================================================  CHACHAKEY7  ======================================================= */
/* =======================================================  CHACHAIV0  ======================================================= */
/* =======================================================  CHACHAIV1  ======================================================= */
/* ======================================================  CHACHABUSY  ======================================================= */
/* =====================================================  CHACHAHWFLAGS  ===================================================== */
/* ========================================  CRYPTO CHACHAHWFLAGS FASTCHACHA [2..2]  ========================================= */
typedef enum {                                  /*!< CRYPTO_CHACHAHWFLAGS_FASTCHACHA                                           */
  CRYPTO_CHACHAHWFLAGS_FASTCHACHA_DISABLE = 0,  /*!< DISABLE : disable.                                                        */
  CRYPTO_CHACHAHWFLAGS_FASTCHACHA_ENABLE = 1,   /*!< ENABLE : enable.                                                          */
} CRYPTO_CHACHAHWFLAGS_FASTCHACHA_Enum;

/* ========================================  CRYPTO CHACHAHWFLAGS SALSAEXISTS [1..1]  ======================================== */
typedef enum {                                  /*!< CRYPTO_CHACHAHWFLAGS_SALSAEXISTS                                          */
  CRYPTO_CHACHAHWFLAGS_SALSAEXISTS_DISABLE = 0, /*!< DISABLE : disable.                                                        */
  CRYPTO_CHACHAHWFLAGS_SALSAEXISTS_ENABLE = 1,  /*!< ENABLE : enable.                                                          */
} CRYPTO_CHACHAHWFLAGS_SALSAEXISTS_Enum;

/* =======================================  CRYPTO CHACHAHWFLAGS CHACHAEXISTS [0..0]  ======================================== */
typedef enum {                                  /*!< CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS                                         */
  CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS_DISABLE = 0,/*!< DISABLE : disable.                                                        */
  CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS_ENABLE = 1, /*!< ENABLE : enable.                                                          */
} CRYPTO_CHACHAHWFLAGS_CHACHAEXISTS_Enum;

/* ===================================================  CHACHABLOCKCNTLSB  =================================================== */
/* ===================================================  CHACHABLOCKCNTMSB  =================================================== */
/* =====================================================  CHACHASWRESET  ===================================================== */
/* ===================================================  CHACHAFORPOLYKEY0  =================================================== */
/* ===================================================  CHACHAFORPOLYKEY1  =================================================== */
/* ===================================================  CHACHAFORPOLYKEY2  =================================================== */
/* ===================================================  CHACHAFORPOLYKEY3  =================================================== */
/* ===================================================  CHACHAFORPOLYKEY4  =================================================== */
/* ===================================================  CHACHAFORPOLYKEY5  =================================================== */
/* ===================================================  CHACHAFORPOLYKEY6  =================================================== */
/* ===================================================  CHACHAFORPOLYKEY7  =================================================== */
/* ==============================================  CHACHABYTEWORDORDERCNTLREG  =============================================== */
/* =============================  CRYPTO CHACHABYTEWORDORDERCNTLREG CHACHADOUTBYTEORDER [4..4]  ============================== */
typedef enum {                                  /*!< CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER                     */
  CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER_DISABLE = 0,/*!< DISABLE : disable.                                    */
  CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER_ENABLE = 1,/*!< ENABLE : enable. (reverse each byte in each word output (b0->b3,
                                                     b1->b2, b2->b1,b3->b0))                                                   */
} CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTBYTEORDER_Enum;

/* =============================  CRYPTO CHACHABYTEWORDORDERCNTLREG CHACHADOUTWORDORDER [3..3]  ============================== */
typedef enum {                                  /*!< CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER                     */
  CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER_DISABLE = 0,/*!< DISABLE : disable.                                    */
  CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER_ENABLE = 1,/*!< ENABLE : enable. (reverse each word in 128 bit output ( w0->w3,
                                                     w1->w2, w2->w1,w3-w0))                                                    */
} CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADOUTWORDORDER_Enum;

/* ===========================  CRYPTO CHACHABYTEWORDORDERCNTLREG CHACHACOREMATRIXLBEORDER [2..2]  =========================== */
typedef enum {                                  /*!< CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER                */
  CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER_DISABLE = 0,/*!< DISABLE : disable.                               */
  CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER_ENABLE = 1,/*!< ENABLE : enable. (reverse each quarter of a matrix (m[0-127]->m[384-511],
                                                     m[128-255]->m[256-383], m[256-383]->m[128-255], m[384-511]->m[0-127]))    */
} CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHACOREMATRIXLBEORDER_Enum;

/* ==============================  CRYPTO CHACHABYTEWORDORDERCNTLREG CHACHADINBYTEORDER [1..1]  ============================== */
typedef enum {                                  /*!< CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER                      */
  CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER_DISABLE = 0,/*!< DISABLE : disable.                                     */
  CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER_ENABLE = 1,/*!< ENABLE : enable. (reverse each byte in each word input (b0->b3,
                                                     b1->b2, b2->b1,b3->b0))                                                   */
} CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINBYTEORDER_Enum;

/* ==============================  CRYPTO CHACHABYTEWORDORDERCNTLREG CHACHADINWORDORDER [0..0]  ============================== */
typedef enum {                                  /*!< CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER                      */
  CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER_DISABLE = 0,/*!< DISABLE : disable.                                     */
  CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER_ENABLE = 1,/*!< ENABLE : enable. (reverse each word in 128 bit input ( w0->w3,
                                                     w1->w2, w2->w1,w3-w0))                                                    */
} CRYPTO_CHACHABYTEWORDORDERCNTLREG_CHACHADINWORDORDER_Enum;

/* ====================================================  CHACHADEBUGREG  ===================================================== */
/* ===================================  CRYPTO CHACHADEBUGREG CHACHADEBUGFSMSTATE [0..1]  ==================================== */
typedef enum {                                  /*!< CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE                                 */
  CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE_IDLE_STATE = 0,/*!< IDLE_STATE : The idle state.                                   */
  CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE_INIT_STATE = 1,/*!< INIT_STATE : The init state.                                   */
} CRYPTO_CHACHADEBUGREG_CHACHADEBUGFSMSTATE_Enum;

/* =======================================================  AESKEY00  ======================================================== */
/* =======================================================  AESKEY01  ======================================================== */
/* =======================================================  AESKEY02  ======================================================== */
/* =======================================================  AESKEY03  ======================================================== */
/* =======================================================  AESKEY04  ======================================================== */
/* =======================================================  AESKEY05  ======================================================== */
/* =======================================================  AESKEY06  ======================================================== */
/* =======================================================  AESKEY07  ======================================================== */
/* =======================================================  AESKEY10  ======================================================== */
/* =======================================================  AESKEY11  ======================================================== */
/* =======================================================  AESKEY12  ======================================================== */
/* =======================================================  AESKEY13  ======================================================== */
/* =======================================================  AESKEY14  ======================================================== */
/* =======================================================  AESKEY15  ======================================================== */
/* =======================================================  AESKEY16  ======================================================== */
/* =======================================================  AESKEY17  ======================================================== */
/* ========================================================  AESIV00  ======================================================== */
/* ========================================================  AESIV01  ======================================================== */
/* ========================================================  AESIV02  ======================================================== */
/* ========================================================  AESIV03  ======================================================== */
/* ========================================================  AESIV10  ======================================================== */
/* ========================================================  AESIV11  ======================================================== */
/* ========================================================  AESIV12  ======================================================== */
/* ========================================================  AESIV13  ======================================================== */
/* =======================================================  AESCTR00  ======================================================== */
/* =======================================================  AESCTR01  ======================================================== */
/* =======================================================  AESCTR02  ======================================================== */
/* =======================================================  AESCTR03  ======================================================== */
/* ========================================================  AESBUSY  ======================================================== */
/* =========================================================  AESSK  ========================================================= */
/* ======================================================  AESCMACINIT  ====================================================== */
/* ========================================================  AESSK1  ========================================================= */
/* ===================================================  AESREMAININGBYTES  =================================================== */
/* ======================================================  AESCONTROL  ======================================================= */
/* ======================================  CRYPTO AESCONTROL AESXORCRYPTOKEY [29..29]  ======================================= */
typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESXORCRYPTOKEY                                         */
  CRYPTO_AESCONTROL_AESXORCRYPTOKEY_CRYPTOKEY = 0,/*!< CRYPTOKEY : The value that is written to AES_KEY0 is the value
                                                     of the HW cryptokey, as is.                                               */
  CRYPTO_AESCONTROL_AESXORCRYPTOKEY_CRYPTOKEY_XOR = 1,/*!< CRYPTOKEY_XOR : The value that is written to AES_KEY0 is the
                                                     value of the HW cryptokey xored with the current value
                                                     of AES_KEY0.                                                              */
} CRYPTO_AESCONTROL_AESXORCRYPTOKEY_Enum;

/* =====================================  CRYPTO AESCONTROL AESOUTMIDTUNTOHASH [28..28]  ===================================== */
typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH                                      */
  CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH_HASH_2 = 0,/*!< HASH_2 : The AES engine writes to the hash the result of the
                                                     second tunnel stage.                                                      */
  CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH_HASH_1 = 1,/*!< HASH_1 : The AES engine writes to the hash the result of the
                                                     first tunnel stage.                                                       */
} CRYPTO_AESCONTROL_AESOUTMIDTUNTOHASH_Enum;

/* ======================================  CRYPTO AESCONTROL AESTUNNELB1PADEN [26..26]  ====================================== */
typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESTUNNELB1PADEN                                        */
  CRYPTO_AESCONTROL_AESTUNNELB1PADEN_DATA_NO_PAD = 0,/*!< DATA_NO_PAD : The data input to the second tunnel block is not
                                                     padded with zeros.                                                        */
  CRYPTO_AESCONTROL_AESTUNNELB1PADEN_DATA_IS_PAD = 1,/*!< DATA_IS_PAD : The data input to the second tunnel block is padded
                                                     with zeros.                                                               */
} CRYPTO_AESCONTROL_AESTUNNELB1PADEN_Enum;

/* ===================================  CRYPTO AESCONTROL AESOUTPUTMIDTUNNELDATA [25..25]  =================================== */
typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA                                  */
  CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA_ENGINE_RSLT_2 = 0,/*!< ENGINE_RSLT_2 : The AES engine outputs the result of the second
                                                     tunnel stage (standard tunneling).                                        */
  CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA_ENGINE_RSLT_1 = 1,/*!< ENGINE_RSLT_1 : The AES engine outputs the result of the first
                                                     tunnel stage.                                                             */
} CRYPTO_AESCONTROL_AESOUTPUTMIDTUNNELDATA_Enum;

/* =====================================  CRYPTO AESCONTROL AESTUNNEL0ENCRYPT [24..24]  ====================================== */
typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT                                       */
  CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT_TUNNEL_1_D = 0,/*!< TUNNEL_1_D : the first tunnel stage performs decrypt operations.     */
  CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT_TUNNEL_1_E = 1,/*!< TUNNEL_1_E : the first tunnel stage performs encrypt operations.     */
} CRYPTO_AESCONTROL_AESTUNNEL0ENCRYPT_Enum;

/* ==================================  CRYPTO AESCONTROL AESTUNB1USESPADDEDDATAIN [23..23]  ================================== */
typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN                                */
  CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN_BLOCK_1 = 0,/*!< BLOCK_1 : the output of the first block (standard tunneling
                                                     operation).                                                               */
  CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN_AFTER_PAD = 1,/*!< AFTER_PAD : data_in after padding rather than the output of
                                                     the first block.                                                          */
} CRYPTO_AESCONTROL_AESTUNB1USESPADDEDDATAIN_Enum;

/* =====================================  CRYPTO AESCONTROL AESTUNNEL1DECRYPT [22..22]  ====================================== */
typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT                                       */
  CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT_TUNNEL_2_E = 0,/*!< TUNNEL_2_E : the second tunnel stage performs encrypt operations.    */
  CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT_TUNNEL_2_D = 1,/*!< TUNNEL_2_D : the second tunnel stage performs decrypt operations.    */
} CRYPTO_AESCONTROL_AESTUNNEL1DECRYPT_Enum;

/* ===========================================  CRYPTO AESCONTROL NKKEY1 [14..15]  =========================================== */
typedef enum {                                  /*!< CRYPTO_AESCONTROL_NKKEY1                                                  */
  CRYPTO_AESCONTROL_NKKEY1_128_BITS_KEY = 0,    /*!< 128_BITS_KEY : 128 bits key                                               */
  CRYPTO_AESCONTROL_NKKEY1_192_BITS_KEY = 1,    /*!< 192_BITS_KEY : 192 bits key                                               */
  CRYPTO_AESCONTROL_NKKEY1_256_BITS_KEY = 2,    /*!< 256_BITS_KEY : 256 bits key                                               */
  CRYPTO_AESCONTROL_NKKEY1_N_A         = 3,     /*!< N_A : Not applicable                                                      */
} CRYPTO_AESCONTROL_NKKEY1_Enum;

/* ===========================================  CRYPTO AESCONTROL NKKEY0 [12..13]  =========================================== */
typedef enum {                                  /*!< CRYPTO_AESCONTROL_NKKEY0                                                  */
  CRYPTO_AESCONTROL_NKKEY0_128_BITS_KEY = 0,    /*!< 128_BITS_KEY : 128 bits key                                               */
  CRYPTO_AESCONTROL_NKKEY0_192_BITS_KEY = 1,    /*!< 192_BITS_KEY : 192 bits key                                               */
  CRYPTO_AESCONTROL_NKKEY0_256_BITS_KEY = 2,    /*!< 256_BITS_KEY : 256 bits key                                               */
  CRYPTO_AESCONTROL_NKKEY0_N_A         = 3,     /*!< N_A : Not applicable                                                      */
} CRYPTO_AESCONTROL_NKKEY0_Enum;

/* =======================================  CRYPTO AESCONTROL AESTUNNELISON [10..10]  ======================================== */
typedef enum {                                  /*!< CRYPTO_AESCONTROL_AESTUNNELISON                                           */
  CRYPTO_AESCONTROL_AESTUNNELISON_STD_NONTUNNEL = 0,/*!< STD_NONTUNNEL : standard non-tunneling operations                     */
  CRYPTO_AESCONTROL_AESTUNNELISON_TUNNEL = 1,   /*!< TUNNEL : tunneling operations.                                            */
} CRYPTO_AESCONTROL_AESTUNNELISON_Enum;

/* ===========================================  CRYPTO AESCONTROL MODEKEY1 [5..7]  =========================================== */
typedef enum {                                  /*!< CRYPTO_AESCONTROL_MODEKEY1                                                */
  CRYPTO_AESCONTROL_MODEKEY1_ECB       = 0,     /*!< ECB : ECB modekey1                                                        */
  CRYPTO_AESCONTROL_MODEKEY1_CBC       = 1,     /*!< CBC : CBC modekey1                                                        */
  CRYPTO_AESCONTROL_MODEKEY1_CTR       = 2,     /*!< CTR : CTR modekey1                                                        */
  CRYPTO_AESCONTROL_MODEKEY1_CBC_MAC   = 3,     /*!< CBC_MAC : CBC MAC modekey1                                                */
  CRYPTO_AESCONTROL_MODEKEY1_XEX_XTS   = 4,     /*!< XEX_XTS : XEX_XTS modekey1                                                */
  CRYPTO_AESCONTROL_MODEKEY1_XCBC_MAC  = 5,     /*!< XCBC_MAC : XCBC MAC modekey1                                              */
  CRYPTO_AESCONTROL_MODEKEY1_OFB       = 6,     /*!< OFB : OFB modekey1                                                        */
  CRYPTO_AESCONTROL_MODEKEY1_CMAC      = 7,     /*!< CMAC : CMAC modekey1                                                      */
} CRYPTO_AESCONTROL_MODEKEY1_Enum;

/* ===========================================  CRYPTO AESCONTROL MODEKEY0 [2..4]  =========================================== */
typedef enum {                                  /*!< CRYPTO_AESCONTROL_MODEKEY0                                                */
  CRYPTO_AESCONTROL_MODEKEY0_ECB       = 0,     /*!< ECB : ECB modekey0                                                        */
  CRYPTO_AESCONTROL_MODEKEY0_CBC       = 1,     /*!< CBC : CBC modekey0                                                        */
  CRYPTO_AESCONTROL_MODEKEY0_CTR       = 2,     /*!< CTR : CTR modekey0                                                        */
  CRYPTO_AESCONTROL_MODEKEY0_CBCMAC    = 3,     /*!< CBCMAC : CBCMAC modekey0                                                  */
  CRYPTO_AESCONTROL_MODEKEY0_XEX_XTS   = 4,     /*!< XEX_XTS : XEX XTS modekey0                                                */
  CRYPTO_AESCONTROL_MODEKEY0_XCBC_MAC  = 5,     /*!< XCBC_MAC : XCBC MAC modekey0                                              */
  CRYPTO_AESCONTROL_MODEKEY0_OFB       = 6,     /*!< OFB : OFB modekey0                                                        */
  CRYPTO_AESCONTROL_MODEKEY0_CMAC      = 7,     /*!< CMAC : CMAC modekey0                                                      */
} CRYPTO_AESCONTROL_MODEKEY0_Enum;

/* ===========================================  CRYPTO AESCONTROL DECKEY0 [0..0]  ============================================ */
typedef enum {                                  /*!< CRYPTO_AESCONTROL_DECKEY0                                                 */
  CRYPTO_AESCONTROL_DECKEY0_ENCRYPT    = 0,     /*!< ENCRYPT : Encrypt                                                         */
  CRYPTO_AESCONTROL_DECKEY0_DECRYPT    = 1,     /*!< DECRYPT : Decrypt                                                         */
} CRYPTO_AESCONTROL_DECKEY0_Enum;

/* ======================================================  AESHWFLAGS  ======================================================= */
/* ===================================================  AESCTRNOINCREMENT  =================================================== */
/* ======================================================  AESDFAISON  ======================================================= */
/* ====================================================  AESDFAERRSTATUS  ==================================================== */
/* ===================================================  AESCMACSIZE0KICK  ==================================================== */
/* ========================================================  HASHH0  ========================================================= */
/* ========================================================  HASHH1  ========================================================= */
/* ========================================================  HASHH2  ========================================================= */
/* ========================================================  HASHH3  ========================================================= */
/* ========================================================  HASHH4  ========================================================= */
/* ========================================================  HASHH5  ========================================================= */
/* ========================================================  HASHH6  ========================================================= */
/* ========================================================  HASHH7  ========================================================= */
/* ========================================================  HASHH8  ========================================================= */
/* =====================================================  AUTOHWPADDING  ===================================================== */
/* ======================================================  HASHXORDIN  ======================================================= */
/* =====================================================  LOADINITSTATE  ===================================================== */
/* =====================================================  HASHSELAESMAC  ===================================================== */
/* =========================================  CRYPTO HASHSELAESMAC GHASHSEL [1..1]  ========================================== */
typedef enum {                                  /*!< CRYPTO_HASHSELAESMAC_GHASHSEL                                             */
  CRYPTO_HASHSELAESMAC_GHASHSEL_HASH_MOD = 0,   /*!< HASH_MOD : select the hash module                                         */
  CRYPTO_HASHSELAESMAC_GHASHSEL_GHASH_MOD = 1,  /*!< GHASH_MOD : select the ghash module                                       */
} CRYPTO_HASHSELAESMAC_GHASHSEL_Enum;

/* =======================================  CRYPTO HASHSELAESMAC HASHSELAESMAC [0..0]  ======================================= */
typedef enum {                                  /*!< CRYPTO_HASHSELAESMAC_HASHSELAESMAC                                        */
  CRYPTO_HASHSELAESMAC_HASHSELAESMAC_HASH_MOD = 0,/*!< HASH_MOD : select the hash module                                       */
  CRYPTO_HASHSELAESMAC_HASHSELAESMAC_MAC_MOD = 1,/*!< MAC_MOD : select the AES mac module                                      */
} CRYPTO_HASHSELAESMAC_HASHSELAESMAC_Enum;

/* ======================================================  HASHVERSION  ====================================================== */
/* ======================================================  HASHCONTROL  ====================================================== */
/* ===========================================  CRYPTO HASHCONTROL MODE01 [0..1]  ============================================ */
typedef enum {                                  /*!< CRYPTO_HASHCONTROL_MODE01                                                 */
  CRYPTO_HASHCONTROL_MODE01_MD5        = 0,     /*!< MD5 : MD5 if present                                                      */
  CRYPTO_HASHCONTROL_MODE01_SHA_1      = 1,     /*!< SHA_1 : SHA-1                                                             */
  CRYPTO_HASHCONTROL_MODE01_SHA_256    = 2,     /*!< SHA_256 : SHA-256                                                         */
} CRYPTO_HASHCONTROL_MODE01_Enum;

/* =======================================================  HASHPADEN  ======================================================= */
/* ======================================================  HASHPADCFG  ======================================================= */
/* ======================================================  HASHCURLEN0  ====================================================== */
/* ======================================================  HASHCURLEN1  ====================================================== */
/* =======================================================  HASHPARAM  ======================================================= */
/* ====================================================  HASHAESSWRESET  ===================================================== */
/* =====================================================  HASHENDIANESS  ===================================================== */
/* =====================================================  AESCLKENABLE  ====================================================== */
/* =============================================  CRYPTO AESCLKENABLE EN [0..0]  ============================================= */
typedef enum {                                  /*!< CRYPTO_AESCLKENABLE_EN                                                    */
  CRYPTO_AESCLKENABLE_EN_CLK_E         = 1,     /*!< CLK_E : the AES clock is enabled.                                         */
  CRYPTO_AESCLKENABLE_EN_CLK_D         = 0,     /*!< CLK_D : the AES clock is disabled.                                        */
} CRYPTO_AESCLKENABLE_EN_Enum;

/* =====================================================  HASHCLKENABLE  ===================================================== */
/* ============================================  CRYPTO HASHCLKENABLE EN [0..0]  ============================================= */
typedef enum {                                  /*!< CRYPTO_HASHCLKENABLE_EN                                                   */
  CRYPTO_HASHCLKENABLE_EN_HASH_E       = 1,     /*!< HASH_E : the HASH clock is enabled.                                       */
  CRYPTO_HASHCLKENABLE_EN_HASH_D       = 0,     /*!< HASH_D : the HASH clock is disabled.                                      */
} CRYPTO_HASHCLKENABLE_EN_Enum;

/* =====================================================  PKACLKENABLE  ====================================================== */
/* =============================================  CRYPTO PKACLKENABLE EN [0..0]  ============================================= */
typedef enum {                                  /*!< CRYPTO_PKACLKENABLE_EN                                                    */
  CRYPTO_PKACLKENABLE_EN_PKA_E         = 1,     /*!< PKA_E : the PKA clock is enabled.                                         */
  CRYPTO_PKACLKENABLE_EN_PKA_D         = 0,     /*!< PKA_D : the PKA clock is disabled.                                        */
} CRYPTO_PKACLKENABLE_EN_Enum;

/* =====================================================  DMACLKENABLE  ====================================================== */
/* =============================================  CRYPTO DMACLKENABLE EN [0..0]  ============================================= */
typedef enum {                                  /*!< CRYPTO_DMACLKENABLE_EN                                                    */
  CRYPTO_DMACLKENABLE_EN_DMA_E         = 1,     /*!< DMA_E : the DMA clock is enabled.                                         */
  CRYPTO_DMACLKENABLE_EN_DMA_D         = 0,     /*!< DMA_D : the DMA clock is disabled.                                        */
} CRYPTO_DMACLKENABLE_EN_Enum;

/* =======================================================  CLKSTATUS  ======================================================= */
/* =========================================  CRYPTO CLKSTATUS DMACLKSTATUS [8..8]  ========================================== */
typedef enum {                                  /*!< CRYPTO_CLKSTATUS_DMACLKSTATUS                                             */
  CRYPTO_CLKSTATUS_DMACLKSTATUS_DMA_E  = 1,     /*!< DMA_E : the DMA clock is enabled.                                         */
  CRYPTO_CLKSTATUS_DMACLKSTATUS_DMA_D  = 0,     /*!< DMA_D : the DMA clock is disabled.                                        */
} CRYPTO_CLKSTATUS_DMACLKSTATUS_Enum;

/* ========================================  CRYPTO CLKSTATUS CHACHACLKSTATUS [7..7]  ======================================== */
typedef enum {                                  /*!< CRYPTO_CLKSTATUS_CHACHACLKSTATUS                                          */
  CRYPTO_CLKSTATUS_CHACHACLKSTATUS_CHACHA_E = 1,/*!< CHACHA_E : the CHACHA clock is enabled.                                   */
  CRYPTO_CLKSTATUS_CHACHACLKSTATUS_CHACHA_D = 0,/*!< CHACHA_D : the CHACHA clock is disabled.                                  */
} CRYPTO_CLKSTATUS_CHACHACLKSTATUS_Enum;

/* =========================================  CRYPTO CLKSTATUS PKACLKSTATUS [3..3]  ========================================== */
typedef enum {                                  /*!< CRYPTO_CLKSTATUS_PKACLKSTATUS                                             */
  CRYPTO_CLKSTATUS_PKACLKSTATUS_PKA_E  = 1,     /*!< PKA_E : the PKA clock is enabled.                                         */
  CRYPTO_CLKSTATUS_PKACLKSTATUS_PKA_D  = 0,     /*!< PKA_D : the PKA clock is disabled.                                        */
} CRYPTO_CLKSTATUS_PKACLKSTATUS_Enum;

/* =========================================  CRYPTO CLKSTATUS HASHCLKSTATUS [2..2]  ========================================= */
typedef enum {                                  /*!< CRYPTO_CLKSTATUS_HASHCLKSTATUS                                            */
  CRYPTO_CLKSTATUS_HASHCLKSTATUS_HASH_E = 1,    /*!< HASH_E : the HASH clock is enabled.                                       */
  CRYPTO_CLKSTATUS_HASHCLKSTATUS_HASH_D = 0,    /*!< HASH_D : the HASH clock is disabled.                                      */
} CRYPTO_CLKSTATUS_HASHCLKSTATUS_Enum;

/* =========================================  CRYPTO CLKSTATUS AESCLKSTATUS [0..0]  ========================================== */
typedef enum {                                  /*!< CRYPTO_CLKSTATUS_AESCLKSTATUS                                             */
  CRYPTO_CLKSTATUS_AESCLKSTATUS_CLK_E  = 1,     /*!< CLK_E : the AES clock is enabled.                                         */
  CRYPTO_CLKSTATUS_AESCLKSTATUS_CLK_D  = 0,     /*!< CLK_D : the AES clock is disabled.                                        */
} CRYPTO_CLKSTATUS_AESCLKSTATUS_Enum;

/* ====================================================  CHACHACLKENABLE  ==================================================== */
/* ===========================================  CRYPTO CHACHACLKENABLE EN [0..0]  ============================================ */
typedef enum {                                  /*!< CRYPTO_CHACHACLKENABLE_EN                                                 */
  CRYPTO_CHACHACLKENABLE_EN_CHACHA_E   = 1,     /*!< CHACHA_E : the CHACHA SALSA clock is enabled.                             */
  CRYPTO_CHACHACLKENABLE_EN_CHACHA_D   = 0,     /*!< CHACHA_D : the CHACHA SALSA clock is disabled.                            */
} CRYPTO_CHACHACLKENABLE_EN_Enum;

/* =======================================================  CRYPTOCTL  ======================================================= */
/* =============================================  CRYPTO CRYPTOCTL MODE [0..4]  ============================================== */
typedef enum {                                  /*!< CRYPTO_CRYPTOCTL_MODE                                                     */
  CRYPTO_CRYPTOCTL_MODE_BYPASS         = 0,     /*!< BYPASS : bypass                                                           */
  CRYPTO_CRYPTOCTL_MODE_AES            = 1,     /*!< AES : aes                                                                 */
  CRYPTO_CRYPTOCTL_MODE_AES_TO_HASH    = 2,     /*!< AES_TO_HASH : aes to hash                                                 */
  CRYPTO_CRYPTOCTL_MODE_AES_AND_HASH   = 3,     /*!< AES_AND_HASH : aes and hash                                               */
  CRYPTO_CRYPTOCTL_MODE_DES            = 4,     /*!< DES : des                                                                 */
  CRYPTO_CRYPTOCTL_MODE_DES_TO_HASH    = 5,     /*!< DES_TO_HASH : des to hash                                                 */
  CRYPTO_CRYPTOCTL_MODE_DES_AND_HASH   = 6,     /*!< DES_AND_HASH : des and hash                                               */
  CRYPTO_CRYPTOCTL_MODE_HASH           = 7,     /*!< HASH : hash                                                               */
  CRYPTO_CRYPTOCTL_MODE_AES_MAC_AND_BYPASS = 9, /*!< AES_MAC_AND_BYPASS : aes mac and bypass                                   */
  CRYPTO_CRYPTOCTL_MODE_AES_TO_HASH_AND_DOUT = 10,/*!< AES_TO_HASH_AND_DOUT : aes to hash and _dout                            */
  CRYPTO_CRYPTOCTL_MODE_Reserved1      = 11,    /*!< Reserved1 : reserved1                                                     */
  CRYPTO_CRYPTOCTL_MODE_Reserved2      = 8,     /*!< Reserved2 : reserved2                                                     */
} CRYPTO_CRYPTOCTL_MODE_Enum;

/* ======================================================  CRYPTOBUSY  ======================================================= */
/* ==========================================  CRYPTO CRYPTOBUSY CRYPTOBUSY [0..0]  ========================================== */
typedef enum {                                  /*!< CRYPTO_CRYPTOBUSY_CRYPTOBUSY                                              */
  CRYPTO_CRYPTOBUSY_CRYPTOBUSY_READY   = 0,     /*!< READY : Ready                                                             */
  CRYPTO_CRYPTOBUSY_CRYPTOBUSY_BUSY    = 1,     /*!< BUSY : Busy                                                               */
} CRYPTO_CRYPTOBUSY_CRYPTOBUSY_Enum;

/* =======================================================  HASHBUSY  ======================================================== */
/* ============================================  CRYPTO HASHBUSY HASHBUSY [0..0]  ============================================ */
typedef enum {                                  /*!< CRYPTO_HASHBUSY_HASHBUSY                                                  */
  CRYPTO_HASHBUSY_HASHBUSY_READY       = 0,     /*!< READY : Ready                                                             */
  CRYPTO_HASHBUSY_HASHBUSY_BUSY        = 1,     /*!< BUSY : Busy                                                               */
} CRYPTO_HASHBUSY_HASHBUSY_Enum;

/* =======================================================  CONTEXTID  ======================================================= */
/* =====================================================  GHASHSUBKEY00  ===================================================== */
/* =====================================================  GHASHSUBKEY01  ===================================================== */
/* =====================================================  GHASHSUBKEY02  ===================================================== */
/* =====================================================  GHASHSUBKEY03  ===================================================== */
/* =======================================================  GHASHIV00  ======================================================= */
/* =======================================================  GHASHIV01  ======================================================= */
/* =======================================================  GHASHIV02  ======================================================= */
/* =======================================================  GHASHIV03  ======================================================= */
/* =======================================================  GHASHBUSY  ======================================================= */
/* =======================================================  GHASHINIT  ======================================================= */
/* ======================================================  HOSTRGFIRR  ======================================================= */
/* ======================================================  HOSTRGFIMR  ======================================================= */
/* ======================================================  HOSTRGFICR  ======================================================= */
/* =====================================================  HOSTRGFENDIAN  ===================================================== */
/* ========================================  CRYPTO HOSTRGFENDIAN DINRDWBG [15..15]  ========================================= */
typedef enum {                                  /*!< CRYPTO_HOSTRGFENDIAN_DINRDWBG                                             */
  CRYPTO_HOSTRGFENDIAN_DINRDWBG_LE     = 0,     /*!< LE : little endian                                                        */
  CRYPTO_HOSTRGFENDIAN_DINRDWBG_BE     = 1,     /*!< BE : big endian                                                           */
} CRYPTO_HOSTRGFENDIAN_DINRDWBG_Enum;

/* ========================================  CRYPTO HOSTRGFENDIAN DOUTWRWBG [11..11]  ======================================== */
typedef enum {                                  /*!< CRYPTO_HOSTRGFENDIAN_DOUTWRWBG                                            */
  CRYPTO_HOSTRGFENDIAN_DOUTWRWBG_LE    = 0,     /*!< LE : little endian                                                        */
  CRYPTO_HOSTRGFENDIAN_DOUTWRWBG_BE    = 1,     /*!< BE : big endian                                                           */
} CRYPTO_HOSTRGFENDIAN_DOUTWRWBG_Enum;

/* ==========================================  CRYPTO HOSTRGFENDIAN DINRDBG [7..7]  ========================================== */
typedef enum {                                  /*!< CRYPTO_HOSTRGFENDIAN_DINRDBG                                              */
  CRYPTO_HOSTRGFENDIAN_DINRDBG_LE      = 0,     /*!< LE : little endian                                                        */
  CRYPTO_HOSTRGFENDIAN_DINRDBG_BE      = 1,     /*!< BE : big endian                                                           */
} CRYPTO_HOSTRGFENDIAN_DINRDBG_Enum;

/* =========================================  CRYPTO HOSTRGFENDIAN DOUTWRBG [3..3]  ========================================== */
typedef enum {                                  /*!< CRYPTO_HOSTRGFENDIAN_DOUTWRBG                                             */
  CRYPTO_HOSTRGFENDIAN_DOUTWRBG_LE     = 0,     /*!< LE : little endian                                                        */
  CRYPTO_HOSTRGFENDIAN_DOUTWRBG_BE     = 1,     /*!< BE : big endian                                                           */
} CRYPTO_HOSTRGFENDIAN_DOUTWRBG_Enum;

/* ===================================================  HOSTRGFSIGNATURE  ==================================================== */
/* =======================================================  HOSTBOOT  ======================================================== */
/* ===================================================  HOSTCRYPTOKEYSEL  ==================================================== */
/* ======================================  CRYPTO HOSTCRYPTOKEYSEL SELCRYPTOKEY [0..2]  ====================================== */
typedef enum {                                  /*!< CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY                                      */
  CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_RKEK = 0,/*!< RKEK : rkek                                                               */
  CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_Krtl = 1,/*!< Krtl : the Krtl.                                                          */
  CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_KCP = 2, /*!< KCP : the provision key KCP.                                              */
  CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_KCE = 3, /*!< KCE : the code encryption key KCE.                                        */
  CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_KPICV = 4,/*!< KPICV : the KPICV, The ICV provisioning key .                            */
  CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_KCEICV = 5,/*!< KCEICV : the code encryption key KCEICV Note: When 'kprtl_lock'
                                                     is set - kprtl will be masked (trying to load it will load
                                                     zeros to the AES key register. When 'kcertl_lock' is set
                                                     - kcertl will be masked (trying to load it will load zeros
                                                     to the AES key register. When scan_mode is asserted all
                                                     the RTL keys (Krtll) will be masked.                                      */
} CRYPTO_HOSTCRYPTOKEYSEL_SELCRYPTOKEY_Enum;

/* ================================================  HOSTCORECLKGATINGENABLE  ================================================ */
/* =====================================================  HOSTCCISIDLE  ====================================================== */
/* =====================================================  HOSTPOWERDOWN  ===================================================== */
/* =================================================  HOSTREMOVEGHASHENGINE  ================================================= */
/* ================================================  HOSTREMOVECHACHAENGINE  ================================================= */
/* ======================================================  AHBMSINGLES  ====================================================== */
/* =======================================================  AHBMHPROT  ======================================================= */
/* =====================================================  AHBMHMASTLOCK  ===================================================== */
/* ======================================================  AHBMHNONSEC  ====================================================== */
/* =======================================================  DINBUFFER  ======================================================= */
/* =====================================================  DINMEMDMABUSY  ===================================================== */
/* =======================================  CRYPTO DINMEMDMABUSY DINMEMDMABUSY [0..0]  ======================================= */
typedef enum {                                  /*!< CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY                                        */
  CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY_busy = 1,  /*!< busy : DMA busy                                                           */
  CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY_not = 0,   /*!< not : DMA not busy                                                        */
} CRYPTO_DINMEMDMABUSY_DINMEMDMABUSY_Enum;

/* ======================================================  SRCLLIWORD0  ====================================================== */
/* ======================================================  SRCLLIWORD1  ====================================================== */
/* ======================================================  SRAMSRCADDR  ====================================================== */
/* ====================================================  DINSRAMBYTESLEN  ==================================================== */
/* ====================================================  DINSRAMDMABUSY  ===================================================== */
/* ===========================================  CRYPTO DINSRAMDMABUSY BUSY [0..0]  =========================================== */
typedef enum {                                  /*!< CRYPTO_DINSRAMDMABUSY_BUSY                                                */
  CRYPTO_DINSRAMDMABUSY_BUSY_BUSY      = 1,     /*!< BUSY : busy                                                               */
  CRYPTO_DINSRAMDMABUSY_BUSY_NOT_BUSY  = 0,     /*!< NOT_BUSY : not busy                                                       */
} CRYPTO_DINSRAMDMABUSY_BUSY_Enum;

/* ===================================================  DINSRAMENDIANNESS  =================================================== */
/* ===================================  CRYPTO DINSRAMENDIANNESS SRAMDINENDIANNESS [0..0]  =================================== */
typedef enum {                                  /*!< CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS                                */
  CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS_BE = 1,/*!< BE : big-endianness                                                   */
  CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS_LE = 0,/*!< LE : little endianness                                                */
} CRYPTO_DINSRAMENDIANNESS_SRAMDINENDIANNESS_Enum;

/* ====================================================  DINCPUDATASIZE  ===================================================== */
/* ======================================================  FIFOINEMPTY  ====================================================== */
/* ====================================================  DINFIFORSTPNTR  ===================================================== */
/* ======================================================  DOUTBUFFER  ======================================================= */
/* ====================================================  DOUTMEMDMABUSY  ===================================================== */
/* ======================================  CRYPTO DOUTMEMDMABUSY DOUTMEMDMABUSY [0..0]  ====================================== */
typedef enum {                                  /*!< CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY                                      */
  CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY_BUSY = 1,/*!< BUSY : busy                                                               */
  CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY_NOT_BUSY = 0,/*!< NOT_BUSY : not busy                                                   */
} CRYPTO_DOUTMEMDMABUSY_DOUTMEMDMABUSY_Enum;

/* ======================================================  DSTLLIWORD0  ====================================================== */
/* ======================================================  DSTLLIWORD1  ====================================================== */
/* =====================================================  SRAMDESTADDR  ====================================================== */
/* ===================================================  DOUTSRAMBYTESLEN  ==================================================== */
/* ====================================================  DOUTSRAMDMABUSY  ==================================================== */
/* ==========================================  CRYPTO DOUTSRAMDMABUSY BUSY [0..0]  =========================================== */
typedef enum {                                  /*!< CRYPTO_DOUTSRAMDMABUSY_BUSY                                               */
  CRYPTO_DOUTSRAMDMABUSY_BUSY_DATA_SRAM = 0,    /*!< DATA_SRAM : all data was written to SRAM.                                 */
  CRYPTO_DOUTSRAMDMABUSY_BUSY_DMA_BUSY = 1,     /*!< DMA_BUSY : DOUT SRAM DMA busy.                                            */
} CRYPTO_DOUTSRAMDMABUSY_BUSY_Enum;

/* ==================================================  DOUTSRAMENDIANNESS  =================================================== */
/* ==================================  CRYPTO DOUTSRAMENDIANNESS DOUTSRAMENDIANNESS [0..0]  ================================== */
typedef enum {                                  /*!< CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS                              */
  CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS_BE = 1,/*!< BE : big-endianness                                                 */
  CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS_LE = 0,/*!< LE : little endianness                                              */
} CRYPTO_DOUTSRAMENDIANNESS_DOUTSRAMENDIANNESS_Enum;

/* =====================================================  READALIGNLAST  ===================================================== */
/* =====================================================  DOUTFIFOEMPTY  ===================================================== */
/* =======================================  CRYPTO DOUTFIFOEMPTY DOUTFIFOEMPTY [0..0]  ======================================= */
typedef enum {                                  /*!< CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY                                        */
  CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY_FIFO_NE = 0,/*!< FIFO_NE : DOUT FIFO is not empty                                         */
  CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY_FIFO_EDOUT = 1,/*!< FIFO_EDOUT : FIFO is empty                                            */
} CRYPTO_DOUTFIFOEMPTY_DOUTFIFOEMPTY_Enum;

/* =======================================================  SRAMDATA  ======================================================== */
/* =======================================================  SRAMADDR  ======================================================== */
/* =====================================================  SRAMDATAREADY  ===================================================== */
/* =====================================================  PERIPHERALID4  ===================================================== */
/* =====================================================  PERIPHERALID0  ===================================================== */
/* =====================================================  PERIPHERALID1  ===================================================== */
/* =====================================================  PERIPHERALID2  ===================================================== */
/* =====================================================  PERIPHERALID3  ===================================================== */
/* =====================================================  COMPONENTID0  ====================================================== */
/* =====================================================  COMPONENTID1  ====================================================== */
/* =====================================================  COMPONENTID2  ====================================================== */
/* =====================================================  COMPONENTID3  ====================================================== */
/* ======================================================  HOSTDCUEN0  ======================================================= */
/* ======================================================  HOSTDCUEN1  ======================================================= */
/* ======================================================  HOSTDCUEN2  ======================================================= */
/* ======================================================  HOSTDCUEN3  ======================================================= */
/* =====================================================  HOSTDCULOCK0  ====================================================== */
/* =====================================================  HOSTDCULOCK1  ====================================================== */
/* =====================================================  HOSTDCULOCK2  ====================================================== */
/* =====================================================  HOSTDCULOCK3  ====================================================== */
/* ===============================================  AOICVDCURESTRICTIONMASK0  ================================================ */
/* ===============================================  AOICVDCURESTRICTIONMASK1  ================================================ */
/* ===============================================  AOICVDCURESTRICTIONMASK2  ================================================ */
/* ===============================================  AOICVDCURESTRICTIONMASK3  ================================================ */
/* ===================================================  AOCCSECDEBUGRESET  =================================================== */
/* ====================================================  HOSTAOLOCKBITS  ===================================================== */
/* ====================================================  AOAPBFILTERING  ===================================================== */
/* =======================================================  AOCCGPPC  ======================================================== */
/* ====================================================  HOSTRGFCCSWRST  ===================================================== */
/* =================================================  AIBFUSEPROGCOMPLETED  ================================================== */
/* ====================================================  NVMDEBUGSTATUS  ===================================================== */
/* ==========================================  CRYPTO NVMDEBUGSTATUS NVMSM [1..3]  =========================================== */
typedef enum {                                  /*!< CRYPTO_NVMDEBUGSTATUS_NVMSM                                               */
  CRYPTO_NVMDEBUGSTATUS_NVMSM_IDLE     = 0,     /*!< IDLE : IDLE NVMSM                                                         */
  CRYPTO_NVMDEBUGSTATUS_NVMSM_READ_DUMMY = 1,   /*!< READ_DUMMY : READ_DUMMY NVMSM                                             */
  CRYPTO_NVMDEBUGSTATUS_NVMSM_READ_MAN_FLAG = 2,/*!< READ_MAN_FLAG : READ_MAN_FLAG NVMSM                                       */
  CRYPTO_NVMDEBUGSTATUS_NVMSM_READ_OEM_FLAG = 3,/*!< READ_OEM_FLAG : READ_OEM_FLAG NVMSM                                       */
  CRYPTO_NVMDEBUGSTATUS_NVMSM_READ_GPPC = 4,    /*!< READ_GPPC : READ_GPPC NVMSM                                               */
  CRYPTO_NVMDEBUGSTATUS_NVMSM_DECODE   = 5,     /*!< DECODE : DECODE NVMSM                                                     */
  CRYPTO_NVMDEBUGSTATUS_NVMSM_OTP_LCS_VALID = 6,/*!< OTP_LCS_VALID : OTP_LCS_VALID NVMSM                                       */
  CRYPTO_NVMDEBUGSTATUS_NVMSM_LCS_IS_VALID = 7, /*!< LCS_IS_VALID : LCS_IS_VALID NVMSM                                         */
} CRYPTO_NVMDEBUGSTATUS_NVMSM_Enum;

/* ======================================================  LCSISVALID  ======================================================= */
/* =======================================================  NVMISIDLE  ======================================================= */
/* ========================================================  LCSREG  ========================================================= */
/* ==============================================  CRYPTO LCSREG LCSREG [0..2]  ============================================== */
typedef enum {                                  /*!< CRYPTO_LCSREG_LCSREG                                                      */
  CRYPTO_LCSREG_LCSREG_CM              = 0,     /*!< CM : CM lifecycle state                                                   */
  CRYPTO_LCSREG_LCSREG_DM              = 1,     /*!< DM : DM lifecycle state                                                   */
  CRYPTO_LCSREG_LCSREG_SE              = 5,     /*!< SE : SE lifecycle state                                                   */
  CRYPTO_LCSREG_LCSREG_RMA             = 7,     /*!< RMA : RMA lifecycle state                                                 */
} CRYPTO_LCSREG_LCSREG_Enum;

/* ===================================================  HOSTSHADOWKDRREG  ==================================================== */
/* ===================================================  HOSTSHADOWKCPREG  ==================================================== */
/* ===================================================  HOSTSHADOWKCEREG  ==================================================== */
/* ==================================================  HOSTSHADOWKPICVREG  =================================================== */
/* ==================================================  HOSTSHADOWKCEICVREG  ================================================== */
/* ====================================================  OTPADDRWIDTHDEF  ==================================================== */


/* =========================================================================================================================== */
/* ================                                            DSP                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  MUTEX0  ========================================================= */
/* ===============================================  DSP MUTEX0 MUTEX0 [0..2]  ================================================ */
typedef enum {                                  /*!< DSP_MUTEX0_MUTEX0                                                         */
  DSP_MUTEX0_MUTEX0_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
  DSP_MUTEX0_MUTEX0_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
  DSP_MUTEX0_MUTEX0_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
  DSP_MUTEX0_MUTEX0_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
  DSP_MUTEX0_MUTEX0_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
  DSP_MUTEX0_MUTEX0_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
} DSP_MUTEX0_MUTEX0_Enum;

/* ========================================================  MUTEX1  ========================================================= */
/* ===============================================  DSP MUTEX1 MUTEX1 [0..2]  ================================================ */
typedef enum {                                  /*!< DSP_MUTEX1_MUTEX1                                                         */
  DSP_MUTEX1_MUTEX1_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
  DSP_MUTEX1_MUTEX1_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
  DSP_MUTEX1_MUTEX1_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
  DSP_MUTEX1_MUTEX1_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
  DSP_MUTEX1_MUTEX1_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
  DSP_MUTEX1_MUTEX1_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
} DSP_MUTEX1_MUTEX1_Enum;

/* ========================================================  MUTEX2  ========================================================= */
/* ===============================================  DSP MUTEX2 MUTEX2 [0..2]  ================================================ */
typedef enum {                                  /*!< DSP_MUTEX2_MUTEX2                                                         */
  DSP_MUTEX2_MUTEX2_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
  DSP_MUTEX2_MUTEX2_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
  DSP_MUTEX2_MUTEX2_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
  DSP_MUTEX2_MUTEX2_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
  DSP_MUTEX2_MUTEX2_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
  DSP_MUTEX2_MUTEX2_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
} DSP_MUTEX2_MUTEX2_Enum;

/* ========================================================  MUTEX3  ========================================================= */
/* ===============================================  DSP MUTEX3 MUTEX3 [0..2]  ================================================ */
typedef enum {                                  /*!< DSP_MUTEX3_MUTEX3                                                         */
  DSP_MUTEX3_MUTEX3_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
  DSP_MUTEX3_MUTEX3_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
  DSP_MUTEX3_MUTEX3_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
  DSP_MUTEX3_MUTEX3_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
  DSP_MUTEX3_MUTEX3_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
  DSP_MUTEX3_MUTEX3_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
} DSP_MUTEX3_MUTEX3_Enum;

/* ========================================================  MUTEX4  ========================================================= */
/* ===============================================  DSP MUTEX4 MUTEX4 [0..2]  ================================================ */
typedef enum {                                  /*!< DSP_MUTEX4_MUTEX4                                                         */
  DSP_MUTEX4_MUTEX4_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
  DSP_MUTEX4_MUTEX4_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
  DSP_MUTEX4_MUTEX4_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
  DSP_MUTEX4_MUTEX4_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
  DSP_MUTEX4_MUTEX4_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
  DSP_MUTEX4_MUTEX4_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
} DSP_MUTEX4_MUTEX4_Enum;

/* ========================================================  MUTEX5  ========================================================= */
/* ===============================================  DSP MUTEX5 MUTEX5 [0..2]  ================================================ */
typedef enum {                                  /*!< DSP_MUTEX5_MUTEX5                                                         */
  DSP_MUTEX5_MUTEX5_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
  DSP_MUTEX5_MUTEX5_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
  DSP_MUTEX5_MUTEX5_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
  DSP_MUTEX5_MUTEX5_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
  DSP_MUTEX5_MUTEX5_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
  DSP_MUTEX5_MUTEX5_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
} DSP_MUTEX5_MUTEX5_Enum;

/* ========================================================  MUTEX6  ========================================================= */
/* ===============================================  DSP MUTEX6 MUTEX6 [0..2]  ================================================ */
typedef enum {                                  /*!< DSP_MUTEX6_MUTEX6                                                         */
  DSP_MUTEX6_MUTEX6_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
  DSP_MUTEX6_MUTEX6_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
  DSP_MUTEX6_MUTEX6_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
  DSP_MUTEX6_MUTEX6_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
  DSP_MUTEX6_MUTEX6_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
  DSP_MUTEX6_MUTEX6_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
} DSP_MUTEX6_MUTEX6_Enum;

/* ========================================================  MUTEX7  ========================================================= */
/* ===============================================  DSP MUTEX7 MUTEX7 [0..2]  ================================================ */
typedef enum {                                  /*!< DSP_MUTEX7_MUTEX7                                                         */
  DSP_MUTEX7_MUTEX7_NONE               = 0,     /*!< NONE : Mutex is free                                                      */
  DSP_MUTEX7_MUTEX7_CPU                = 1,     /*!< CPU : CPU Owns Mutex                                                      */
  DSP_MUTEX7_MUTEX7_DSP0               = 2,     /*!< DSP0 : DSP0 Owns Mutex                                                    */
  DSP_MUTEX7_MUTEX7_DSP1               = 4,     /*!< DSP1 : DSP1 Owns Mutex                                                    */
  DSP_MUTEX7_MUTEX7_CLEAR              = 6,     /*!< CLEAR : Clear Mutex (conditional)                                         */
  DSP_MUTEX7_MUTEX7_SET                = 7,     /*!< SET : Set Mutex (conditional)                                             */
} DSP_MUTEX7_MUTEX7_Enum;

/* ======================================================  CPUMBINTSET  ====================================================== */
/* ======================================================  CPUMBINTCLR  ====================================================== */
/* =====================================================  CPUMBINTSTAT  ====================================================== */
/* =====================================================  CPUCPUMBDATA  ====================================================== */
/* =====================================================  DSP0CPUMBDATA  ===================================================== */
/* =====================================================  DSP1CPUMBDATA  ===================================================== */
/* =====================================================  DSP0MBINTSET  ====================================================== */
/* =====================================================  DSP0MBINTCLR  ====================================================== */
/* =====================================================  DSP0MBINTSTAT  ===================================================== */
/* =====================================================  CPUDSP0MBDATA  ===================================================== */
/* ====================================================  DSP0DSP0MBDATA  ===================================================== */
/* ====================================================  DSP1DSP0MBDATA  ===================================================== */
/* =====================================================  DSP1MBINTSET  ====================================================== */
/* =====================================================  DSP1MBINTCLR  ====================================================== */
/* =====================================================  DSP1MBINTSTAT  ===================================================== */
/* =====================================================  CPUDSP1MBDATA  ===================================================== */
/* ====================================================  DSP0DSP1MBDATA  ===================================================== */
/* ====================================================  DSP1DSP1MBDATA  ===================================================== */
/* ======================================================  DSP0CONTROL  ====================================================== */
/* ==========================================  DSP DSP0CONTROL DSP0IDMATRIG [4..5]  ========================================== */
typedef enum {                                  /*!< DSP_DSP0CONTROL_DSP0IDMATRIG                                              */
  DSP_DSP0CONTROL_DSP0IDMATRIG_XTRIG   = 3,     /*!< XTRIG : Trigger is disabled until a cross trigger pulse is asserted.
                                                     This will allow another source (determined by the XTRIGSRC
                                                     register) to allow the DMA descriptor chain to proceed.                   */
  DSP_DSP0CONTROL_DSP0IDMATRIG_SSTEP   = 2,     /*!< SSTEP : Trigger is disabled until a trigger pulse (PULSE in
                                                     IDMATRIG register) is asserted. This will allow a single
                                                     step in the DMA descriptor chain to be enabled until next
                                                     completion.                                                               */
  DSP_DSP0CONTROL_DSP0IDMATRIG_AON     = 1,     /*!< AON : Trigger is always enabled. With this set, any trigger
                                                     out will immediately generate a trigger in                                */
  DSP_DSP0CONTROL_DSP0IDMATRIG_DISABLE = 0,     /*!< DISABLE : Trigger is disabled. This will pause the iDMA indefinitely
                                                     until enabled.                                                            */
} DSP_DSP0CONTROL_DSP0IDMATRIG_Enum;

/* =====================================================  DSP0RESETVEC  ====================================================== */
/* ======================================================  DSP0IRQMASK  ====================================================== */
/* =====================================================  DSP0WAKEMASK  ====================================================== */
/* ==================================================  DSP0RAWIRQSTAT31to0  ================================================== */
/* =================================================  DSP0RAWIRQSTAT63to32  ================================================== */
/* =================================================  DSP0RAWIRQSTAT95to64  ================================================== */
/* =====================================================  DSP0L2LVLINT  ====================================================== */
/* =====================================================  DSP0L3LVLINT  ====================================================== */
/* =====================================================  DSP0L4LVLINT  ====================================================== */
/* =====================================================  DSP0L5LVLINT  ====================================================== */
/* ====================================================  DSP0IDMATRIGCTL  ==================================================== */
/* ==================================================  DSP0INTORMASK31TO0A  ================================================== */
/* =================================================  DSP0INTORMASK63TO32A  ================================================== */
/* =================================================  DSP0INTORMASK95TO64A  ================================================== */
/* ==================================================  DSP0INTORMASK31to0B  ================================================== */
/* =================================================  DSP0INTORMASK63TO32B  ================================================== */
/* =================================================  DSP0INTORMASK95TO64B  ================================================== */
/* ===================================================  DSP0INTENIRQ31TO0  =================================================== */
/* ==================================================  DSP0INTENIRQ63TO32  =================================================== */
/* ==================================================  DSP0INTENIRQ95TO64  =================================================== */
/* ======================================================  DSP1CONTROL  ====================================================== */
/* ==========================================  DSP DSP1CONTROL DSP1IDMATRIG [4..5]  ========================================== */
typedef enum {                                  /*!< DSP_DSP1CONTROL_DSP1IDMATRIG                                              */
  DSP_DSP1CONTROL_DSP1IDMATRIG_XTRIG   = 3,     /*!< XTRIG : Trigger is disabled until a cross trigger pulse is asserted.
                                                     This will allow another source (determined by the XTRIGSRC
                                                     register) to allow the DMA descriptor chain to proceed.                   */
  DSP_DSP1CONTROL_DSP1IDMATRIG_SSTEP   = 2,     /*!< SSTEP : Trigger is disabled until a trigger pulse (PULSE in
                                                     IDMATRIG register) is asserted. This will allow a single
                                                     step in the DMA descriptor chain to be enabled until next
                                                     completion.                                                               */
  DSP_DSP1CONTROL_DSP1IDMATRIG_AON     = 1,     /*!< AON : Trigger is always enabled. With this set, any trigger
                                                     out will immediately generate a trigger in                                */
  DSP_DSP1CONTROL_DSP1IDMATRIG_DISABLE = 0,     /*!< DISABLE : Trigger is disabled. This will pause the iDMA indefinitely
                                                     until enabled.                                                            */
} DSP_DSP1CONTROL_DSP1IDMATRIG_Enum;

/* =====================================================  DSP1RESETVEC  ====================================================== */
/* ======================================================  DSP1IRQMASK  ====================================================== */
/* =====================================================  DSP1WAKEMASK  ====================================================== */
/* ==================================================  DSP1RAWIRQSTAT31to0  ================================================== */
/* =================================================  DSP1RAWIRQSTAT63to32  ================================================== */
/* =================================================  DSP1RAWIRQSTAT95to64  ================================================== */
/* =====================================================  DSP1L2LVLINT  ====================================================== */
/* =====================================================  DSP1L3LVLINT  ====================================================== */
/* =====================================================  DSP1L4LVLINT  ====================================================== */
/* =====================================================  DSP1L5LVLINT  ====================================================== */
/* ====================================================  DSP1IDMATRIGCTL  ==================================================== */
/* ==================================================  DSP1INTORMASK31TO0A  ================================================== */
/* =================================================  DSP1INTORMASK63TO32A  ================================================== */
/* =================================================  DSP1INTORMASK95TO64A  ================================================== */
/* ==================================================  DSP1INTORMASK31to0B  ================================================== */
/* =================================================  DSP1INTORMASK63TO32B  ================================================== */
/* =================================================  DSP1INTORMASK95TO64B  ================================================== */
/* ===================================================  DSP1INTENIRQ31TO0  =================================================== */
/* ==================================================  DSP1INTENIRQ63TO32  =================================================== */
/* ==================================================  DSP1INTENIRQ95TO64  =================================================== */


/* =========================================================================================================================== */
/* ================                                           FPIO                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  RD0  ========================================================== */
/* ==========================================================  RD1  ========================================================== */
/* ==========================================================  RD2  ========================================================== */
/* ==========================================================  RD3  ========================================================== */
/* ==========================================================  WT0  ========================================================== */
/* ==========================================================  WT1  ========================================================== */
/* ==========================================================  WT2  ========================================================== */
/* ==========================================================  WT3  ========================================================== */
/* =========================================================  WTS0  ========================================================== */
/* =========================================================  WTS1  ========================================================== */
/* =========================================================  WTS2  ========================================================== */
/* =========================================================  WTS3  ========================================================== */
/* =========================================================  WTC0  ========================================================== */
/* =========================================================  WTC1  ========================================================== */
/* =========================================================  WTC2  ========================================================== */
/* =========================================================  WTC3  ========================================================== */
/* ==========================================================  EN0  ========================================================== */
/* ==========================================================  EN1  ========================================================== */
/* ==========================================================  EN2  ========================================================== */
/* ==========================================================  EN3  ========================================================== */
/* =========================================================  ENS0  ========================================================== */
/* =========================================================  ENS1  ========================================================== */
/* =========================================================  ENS2  ========================================================== */
/* =========================================================  ENS3  ========================================================== */
/* =========================================================  ENC0  ========================================================== */
/* =========================================================  ENC1  ========================================================== */
/* =========================================================  ENC2  ========================================================== */
/* =========================================================  ENC3  ========================================================== */


/* =========================================================================================================================== */
/* ================                                           GPIO                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  PINCFG0  ======================================================== */
/* =============================================  GPIO PINCFG0 NCEPOL0 [22..22]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG0_NCEPOL0                                                      */
  GPIO_PINCFG0_NCEPOL0_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG0_NCEPOL0_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG0_NCEPOL0_Enum;

/* =============================================  GPIO PINCFG0 NCESRC0 [16..21]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG0_NCESRC0                                                      */
  GPIO_PINCFG0_NCESRC0_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG0_NCESRC0_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG0_NCESRC0_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG0_NCESRC0_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG0_NCESRC0_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG0_NCESRC0_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG0_NCESRC0_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG0_NCESRC0_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG0_NCESRC0_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG0_NCESRC0_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG0_NCESRC0_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG0_NCESRC0_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG0_NCESRC0_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG0_NCESRC0_Enum;

/* ============================================  GPIO PINCFG0 PULLCFG0 [13..15]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG0_PULLCFG0                                                     */
  GPIO_PINCFG0_PULLCFG0_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG0_PULLCFG0_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG0_PULLCFG0_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG0_PULLCFG0_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG0_PULLCFG0_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG0_PULLCFG0_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG0_PULLCFG0_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG0_PULLCFG0_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG0_PULLCFG0_Enum;

/* ===============================================  GPIO PINCFG0 DS0 [10..11]  =============================================== */
typedef enum {                                  /*!< GPIO_PINCFG0_DS0                                                          */
  GPIO_PINCFG0_DS0_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG0_DS0_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG0_DS0_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG0_DS0_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG0_DS0_Enum;

/* ==============================================  GPIO PINCFG0 OUTCFG0 [8..9]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG0_OUTCFG0                                                      */
  GPIO_PINCFG0_OUTCFG0_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG0_OUTCFG0_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG0_OUTCFG0_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG0_OUTCFG0_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG0_OUTCFG0_Enum;

/* ==============================================  GPIO PINCFG0 IRPTEN0 [6..7]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG0_IRPTEN0                                                      */
  GPIO_PINCFG0_IRPTEN0_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG0_IRPTEN0_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG0_IRPTEN0_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG0_IRPTEN0_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG0_IRPTEN0_Enum;

/* ==============================================  GPIO PINCFG0 FNCSEL0 [0..3]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG0_FNCSEL0                                                      */
  GPIO_PINCFG0_FNCSEL0_SWTRACECLK      = 0,     /*!< SWTRACECLK : Serial Wire Debug Trace Clock                                */
  GPIO_PINCFG0_FNCSEL0_SLSCL           = 1,     /*!< SLSCL : I2C Slave clock                                                   */
  GPIO_PINCFG0_FNCSEL0_SLSCK           = 2,     /*!< SLSCK : SPI Slave clock                                                   */
  GPIO_PINCFG0_FNCSEL0_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG0_FNCSEL0_UART0TX         = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
  GPIO_PINCFG0_FNCSEL0_UART1TX         = 5,     /*!< UART1TX : UART transmit output (UART 1)                                   */
  GPIO_PINCFG0_FNCSEL0_CT0             = 6,     /*!< CT0 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG0_FNCSEL0_NCE0            = 7,     /*!< NCE0 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG0_FNCSEL0_OBSBUS0         = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
  GPIO_PINCFG0_FNCSEL0_VCMPO           = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG0_FNCSEL0_RESERVED10      = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG0_FNCSEL0_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG0_FNCSEL0_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG0_FNCSEL0_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG0_FNCSEL0_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG0_FNCSEL0_RESERVED15      = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG0_FNCSEL0_Enum;

/* ========================================================  PINCFG1  ======================================================== */
/* =============================================  GPIO PINCFG1 NCEPOL1 [22..22]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG1_NCEPOL1                                                      */
  GPIO_PINCFG1_NCEPOL1_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG1_NCEPOL1_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG1_NCEPOL1_Enum;

/* =============================================  GPIO PINCFG1 NCESRC1 [16..21]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG1_NCESRC1                                                      */
  GPIO_PINCFG1_NCESRC1_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG1_NCESRC1_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG1_NCESRC1_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG1_NCESRC1_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG1_NCESRC1_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG1_NCESRC1_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG1_NCESRC1_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG1_NCESRC1_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG1_NCESRC1_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG1_NCESRC1_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG1_NCESRC1_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG1_NCESRC1_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG1_NCESRC1_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG1_NCESRC1_Enum;

/* ============================================  GPIO PINCFG1 PULLCFG1 [13..15]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG1_PULLCFG1                                                     */
  GPIO_PINCFG1_PULLCFG1_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG1_PULLCFG1_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG1_PULLCFG1_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG1_PULLCFG1_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG1_PULLCFG1_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG1_PULLCFG1_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG1_PULLCFG1_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG1_PULLCFG1_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG1_PULLCFG1_Enum;

/* ===============================================  GPIO PINCFG1 DS1 [10..11]  =============================================== */
typedef enum {                                  /*!< GPIO_PINCFG1_DS1                                                          */
  GPIO_PINCFG1_DS1_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG1_DS1_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG1_DS1_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG1_DS1_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG1_DS1_Enum;

/* ==============================================  GPIO PINCFG1 OUTCFG1 [8..9]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG1_OUTCFG1                                                      */
  GPIO_PINCFG1_OUTCFG1_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG1_OUTCFG1_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG1_OUTCFG1_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG1_OUTCFG1_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG1_OUTCFG1_Enum;

/* ==============================================  GPIO PINCFG1 IRPTEN1 [6..7]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG1_IRPTEN1                                                      */
  GPIO_PINCFG1_IRPTEN1_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG1_IRPTEN1_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG1_IRPTEN1_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG1_IRPTEN1_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG1_IRPTEN1_Enum;

/* ==============================================  GPIO PINCFG1 FNCSEL1 [0..3]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG1_FNCSEL1                                                      */
  GPIO_PINCFG1_FNCSEL1_SWTRACE0        = 0,     /*!< SWTRACE0 : Serial Wire Debug Trace Output 0                               */
  GPIO_PINCFG1_FNCSEL1_SLSDAWIR3       = 1,     /*!< SLSDAWIR3 : I2C Slave I/O data (I2C) 3 Wire Data (SPI)                    */
  GPIO_PINCFG1_FNCSEL1_SLMOSI          = 2,     /*!< SLMOSI : SPI Slave input data                                             */
  GPIO_PINCFG1_FNCSEL1_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG1_FNCSEL1_UART2TX         = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
  GPIO_PINCFG1_FNCSEL1_UART3TX         = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
  GPIO_PINCFG1_FNCSEL1_CT1             = 6,     /*!< CT1 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG1_FNCSEL1_NCE1            = 7,     /*!< NCE1 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG1_FNCSEL1_OBSBUS1         = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
  GPIO_PINCFG1_FNCSEL1_VCMPO           = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG1_FNCSEL1_RESERVED10      = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG1_FNCSEL1_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG1_FNCSEL1_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG1_FNCSEL1_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG1_FNCSEL1_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG1_FNCSEL1_SCANIN4         = 15,    /*!< SCANIN4 : Internal function (SCAN)                                        */
} GPIO_PINCFG1_FNCSEL1_Enum;

/* ========================================================  PINCFG2  ======================================================== */
/* =============================================  GPIO PINCFG2 NCEPOL2 [22..22]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG2_NCEPOL2                                                      */
  GPIO_PINCFG2_NCEPOL2_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG2_NCEPOL2_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG2_NCEPOL2_Enum;

/* =============================================  GPIO PINCFG2 NCESRC2 [16..21]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG2_NCESRC2                                                      */
  GPIO_PINCFG2_NCESRC2_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG2_NCESRC2_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG2_NCESRC2_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG2_NCESRC2_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG2_NCESRC2_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG2_NCESRC2_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG2_NCESRC2_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG2_NCESRC2_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG2_NCESRC2_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG2_NCESRC2_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG2_NCESRC2_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG2_NCESRC2_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG2_NCESRC2_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG2_NCESRC2_Enum;

/* ============================================  GPIO PINCFG2 PULLCFG2 [13..15]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG2_PULLCFG2                                                     */
  GPIO_PINCFG2_PULLCFG2_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG2_PULLCFG2_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG2_PULLCFG2_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG2_PULLCFG2_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG2_PULLCFG2_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG2_PULLCFG2_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG2_PULLCFG2_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG2_PULLCFG2_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG2_PULLCFG2_Enum;

/* ===============================================  GPIO PINCFG2 DS2 [10..11]  =============================================== */
typedef enum {                                  /*!< GPIO_PINCFG2_DS2                                                          */
  GPIO_PINCFG2_DS2_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG2_DS2_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG2_DS2_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG2_DS2_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG2_DS2_Enum;

/* ==============================================  GPIO PINCFG2 OUTCFG2 [8..9]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG2_OUTCFG2                                                      */
  GPIO_PINCFG2_OUTCFG2_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG2_OUTCFG2_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG2_OUTCFG2_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG2_OUTCFG2_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG2_OUTCFG2_Enum;

/* ==============================================  GPIO PINCFG2 IRPTEN2 [6..7]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG2_IRPTEN2                                                      */
  GPIO_PINCFG2_IRPTEN2_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG2_IRPTEN2_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG2_IRPTEN2_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG2_IRPTEN2_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG2_IRPTEN2_Enum;

/* ==============================================  GPIO PINCFG2 FNCSEL2 [0..3]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG2_FNCSEL2                                                      */
  GPIO_PINCFG2_FNCSEL2_SWTRACE1        = 0,     /*!< SWTRACE1 : Serial Wire Debug Trace Output 1                               */
  GPIO_PINCFG2_FNCSEL2_SLMISO          = 1,     /*!< SLMISO : SPI Slave output data                                            */
  GPIO_PINCFG2_FNCSEL2_TRIG1           = 2,     /*!< TRIG1 : ADC trigger input                                                 */
  GPIO_PINCFG2_FNCSEL2_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG2_FNCSEL2_UART0RX         = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
  GPIO_PINCFG2_FNCSEL2_UART1RX         = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
  GPIO_PINCFG2_FNCSEL2_CT2             = 6,     /*!< CT2 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG2_FNCSEL2_NCE2            = 7,     /*!< NCE2 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG2_FNCSEL2_OBSBUS2         = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
  GPIO_PINCFG2_FNCSEL2_VCMPO           = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG2_FNCSEL2_RESERVED10      = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG2_FNCSEL2_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG2_FNCSEL2_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG2_FNCSEL2_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG2_FNCSEL2_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG2_FNCSEL2_SCANRSTN        = 15,    /*!< SCANRSTN : Internal function (SCAN)                                       */
} GPIO_PINCFG2_FNCSEL2_Enum;

/* ========================================================  PINCFG3  ======================================================== */
/* =============================================  GPIO PINCFG3 NCEPOL3 [22..22]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG3_NCEPOL3                                                      */
  GPIO_PINCFG3_NCEPOL3_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG3_NCEPOL3_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG3_NCEPOL3_Enum;

/* =============================================  GPIO PINCFG3 NCESRC3 [16..21]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG3_NCESRC3                                                      */
  GPIO_PINCFG3_NCESRC3_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG3_NCESRC3_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG3_NCESRC3_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG3_NCESRC3_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG3_NCESRC3_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG3_NCESRC3_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG3_NCESRC3_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG3_NCESRC3_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG3_NCESRC3_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG3_NCESRC3_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG3_NCESRC3_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG3_NCESRC3_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG3_NCESRC3_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG3_NCESRC3_Enum;

/* ============================================  GPIO PINCFG3 PULLCFG3 [13..15]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG3_PULLCFG3                                                     */
  GPIO_PINCFG3_PULLCFG3_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG3_PULLCFG3_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG3_PULLCFG3_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG3_PULLCFG3_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG3_PULLCFG3_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG3_PULLCFG3_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG3_PULLCFG3_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG3_PULLCFG3_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG3_PULLCFG3_Enum;

/* ===============================================  GPIO PINCFG3 DS3 [10..11]  =============================================== */
typedef enum {                                  /*!< GPIO_PINCFG3_DS3                                                          */
  GPIO_PINCFG3_DS3_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG3_DS3_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG3_DS3_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG3_DS3_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG3_DS3_Enum;

/* ==============================================  GPIO PINCFG3 OUTCFG3 [8..9]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG3_OUTCFG3                                                      */
  GPIO_PINCFG3_OUTCFG3_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG3_OUTCFG3_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG3_OUTCFG3_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG3_OUTCFG3_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG3_OUTCFG3_Enum;

/* ==============================================  GPIO PINCFG3 IRPTEN3 [6..7]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG3_IRPTEN3                                                      */
  GPIO_PINCFG3_IRPTEN3_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG3_IRPTEN3_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG3_IRPTEN3_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG3_IRPTEN3_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG3_IRPTEN3_Enum;

/* ==============================================  GPIO PINCFG3 FNCSEL3 [0..3]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG3_FNCSEL3                                                      */
  GPIO_PINCFG3_FNCSEL3_SWTRACE2        = 0,     /*!< SWTRACE2 : Serial Wire Debug Trace Output 2                               */
  GPIO_PINCFG3_FNCSEL3_SLnCE           = 1,     /*!< SLnCE : SPI Slave chip enable                                             */
  GPIO_PINCFG3_FNCSEL3_SWO             = 2,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG3_FNCSEL3_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG3_FNCSEL3_UART2RX         = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
  GPIO_PINCFG3_FNCSEL3_UART3RX         = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
  GPIO_PINCFG3_FNCSEL3_CT3             = 6,     /*!< CT3 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG3_FNCSEL3_NCE3            = 7,     /*!< NCE3 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG3_FNCSEL3_OBSBUS3         = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
  GPIO_PINCFG3_FNCSEL3_RESERVED9       = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG3_FNCSEL3_RESERVED10      = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG3_FNCSEL3_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG3_FNCSEL3_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG3_FNCSEL3_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG3_FNCSEL3_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG3_FNCSEL3_SCANIN5         = 15,    /*!< SCANIN5 : Internal function (SCAN)                                        */
} GPIO_PINCFG3_FNCSEL3_Enum;

/* ========================================================  PINCFG4  ======================================================== */
/* =============================================  GPIO PINCFG4 NCEPOL4 [22..22]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG4_NCEPOL4                                                      */
  GPIO_PINCFG4_NCEPOL4_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG4_NCEPOL4_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG4_NCEPOL4_Enum;

/* =============================================  GPIO PINCFG4 NCESRC4 [16..21]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG4_NCESRC4                                                      */
  GPIO_PINCFG4_NCESRC4_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG4_NCESRC4_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG4_NCESRC4_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG4_NCESRC4_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG4_NCESRC4_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG4_NCESRC4_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG4_NCESRC4_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG4_NCESRC4_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG4_NCESRC4_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG4_NCESRC4_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG4_NCESRC4_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG4_NCESRC4_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG4_NCESRC4_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG4_NCESRC4_Enum;

/* ============================================  GPIO PINCFG4 PULLCFG4 [13..15]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG4_PULLCFG4                                                     */
  GPIO_PINCFG4_PULLCFG4_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG4_PULLCFG4_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG4_PULLCFG4_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG4_PULLCFG4_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG4_PULLCFG4_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG4_PULLCFG4_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG4_PULLCFG4_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG4_PULLCFG4_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG4_PULLCFG4_Enum;

/* ===============================================  GPIO PINCFG4 DS4 [10..11]  =============================================== */
typedef enum {                                  /*!< GPIO_PINCFG4_DS4                                                          */
  GPIO_PINCFG4_DS4_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG4_DS4_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG4_DS4_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG4_DS4_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG4_DS4_Enum;

/* ==============================================  GPIO PINCFG4 OUTCFG4 [8..9]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG4_OUTCFG4                                                      */
  GPIO_PINCFG4_OUTCFG4_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG4_OUTCFG4_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG4_OUTCFG4_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG4_OUTCFG4_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG4_OUTCFG4_Enum;

/* ==============================================  GPIO PINCFG4 IRPTEN4 [6..7]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG4_IRPTEN4                                                      */
  GPIO_PINCFG4_IRPTEN4_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG4_IRPTEN4_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG4_IRPTEN4_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG4_IRPTEN4_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG4_IRPTEN4_Enum;

/* ==============================================  GPIO PINCFG4 FNCSEL4 [0..3]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG4_FNCSEL4                                                      */
  GPIO_PINCFG4_FNCSEL4_SWTRACE3        = 0,     /*!< SWTRACE3 : Serial Wire Debug Trace Output 3                               */
  GPIO_PINCFG4_FNCSEL4_SLINT           = 1,     /*!< SLINT : Configurable Slave Interrupt                                      */
  GPIO_PINCFG4_FNCSEL4_32KHzXT         = 2,     /*!< 32KHzXT : 32kHZ from analog                                               */
  GPIO_PINCFG4_FNCSEL4_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG4_FNCSEL4_UART0RTS        = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
  GPIO_PINCFG4_FNCSEL4_UART1RTS        = 5,     /*!< UART1RTS : UART Request to Send (RTS) (UART 1)                            */
  GPIO_PINCFG4_FNCSEL4_CT4             = 6,     /*!< CT4 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG4_FNCSEL4_NCE4            = 7,     /*!< NCE4 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG4_FNCSEL4_OBSBUS4         = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
  GPIO_PINCFG4_FNCSEL4_I2S0_SDIN       = 9,     /*!< I2S0_SDIN : I2S Data input (I2S Master/Slave 2)                           */
  GPIO_PINCFG4_FNCSEL4_I2S1_SDIN       = 10,    /*!< I2S1_SDIN : I2S Data input (I2S Master/Slave 2)                           */
  GPIO_PINCFG4_FNCSEL4_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG4_FNCSEL4_FLB_TDO         = 12,    /*!< FLB_TDO : Internal function (Flash Bist)                                  */
  GPIO_PINCFG4_FNCSEL4_FLLOAD_DIR      = 13,    /*!< FLLOAD_DIR : Internal function (Flash parallel load)                      */
  GPIO_PINCFG4_FNCSEL4_MDA_TDO         = 14,    /*!< MDA_TDO : Internal function (MBIST)                                       */
  GPIO_PINCFG4_FNCSEL4_OPCG_TRIG       = 15,    /*!< OPCG_TRIG : Internal function (SCAN)                                      */
} GPIO_PINCFG4_FNCSEL4_Enum;

/* ========================================================  PINCFG5  ======================================================== */
/* =============================================  GPIO PINCFG5 NCEPOL5 [22..22]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG5_NCEPOL5                                                      */
  GPIO_PINCFG5_NCEPOL5_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG5_NCEPOL5_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG5_NCEPOL5_Enum;

/* =============================================  GPIO PINCFG5 NCESRC5 [16..21]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG5_NCESRC5                                                      */
  GPIO_PINCFG5_NCESRC5_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG5_NCESRC5_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG5_NCESRC5_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG5_NCESRC5_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG5_NCESRC5_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG5_NCESRC5_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG5_NCESRC5_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG5_NCESRC5_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG5_NCESRC5_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG5_NCESRC5_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG5_NCESRC5_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG5_NCESRC5_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG5_NCESRC5_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG5_NCESRC5_Enum;

/* ============================================  GPIO PINCFG5 PULLCFG5 [13..15]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG5_PULLCFG5                                                     */
  GPIO_PINCFG5_PULLCFG5_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG5_PULLCFG5_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG5_PULLCFG5_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG5_PULLCFG5_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG5_PULLCFG5_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG5_PULLCFG5_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG5_PULLCFG5_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG5_PULLCFG5_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG5_PULLCFG5_Enum;

/* ===============================================  GPIO PINCFG5 DS5 [10..11]  =============================================== */
typedef enum {                                  /*!< GPIO_PINCFG5_DS5                                                          */
  GPIO_PINCFG5_DS5_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG5_DS5_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG5_DS5_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG5_DS5_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG5_DS5_Enum;

/* ==============================================  GPIO PINCFG5 OUTCFG5 [8..9]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG5_OUTCFG5                                                      */
  GPIO_PINCFG5_OUTCFG5_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG5_OUTCFG5_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG5_OUTCFG5_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG5_OUTCFG5_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG5_OUTCFG5_Enum;

/* ==============================================  GPIO PINCFG5 IRPTEN5 [6..7]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG5_IRPTEN5                                                      */
  GPIO_PINCFG5_IRPTEN5_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG5_IRPTEN5_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG5_IRPTEN5_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG5_IRPTEN5_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG5_IRPTEN5_Enum;

/* ==============================================  GPIO PINCFG5 FNCSEL5 [0..3]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG5_FNCSEL5                                                      */
  GPIO_PINCFG5_FNCSEL5_M0SCL           = 0,     /*!< M0SCL : Serial I2C Master Clock output (IOM 0)                            */
  GPIO_PINCFG5_FNCSEL5_M0SCK           = 1,     /*!< M0SCK : Serial SPI Master Clock output (IOM 0)                            */
  GPIO_PINCFG5_FNCSEL5_I2S0_CLK        = 2,     /*!< I2S0_CLK : Bidirectional I2S Bit clock. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG5_FNCSEL5_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG5_FNCSEL5_UART2RTS        = 4,     /*!< UART2RTS : UART Request to Send (RTS) (UART 2)                            */
  GPIO_PINCFG5_FNCSEL5_UART3RTS        = 5,     /*!< UART3RTS : UART Request to Send (RTS) (UART 3)                            */
  GPIO_PINCFG5_FNCSEL5_CT5             = 6,     /*!< CT5 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG5_FNCSEL5_NCE5            = 7,     /*!< NCE5 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG5_FNCSEL5_OBSBUS5         = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
  GPIO_PINCFG5_FNCSEL5_RESERVED9       = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG5_FNCSEL5_I2S1_CLK        = 10,    /*!< I2S1_CLK : Bidirectional I2S Bit clock. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG5_FNCSEL5_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG5_FNCSEL5_FLB_TDI         = 12,    /*!< FLB_TDI : Internal function (Flash Bist)                                  */
  GPIO_PINCFG5_FNCSEL5_FLLOAD_DATA     = 13,    /*!< FLLOAD_DATA : Internal function (Flash parallel load)                     */
  GPIO_PINCFG5_FNCSEL5_MDA_SRST        = 14,    /*!< MDA_SRST : Internal function (MBIST)                                      */
  GPIO_PINCFG5_FNCSEL5_DFT_ISO         = 15,    /*!< DFT_ISO : Internal function (SCAN)                                        */
} GPIO_PINCFG5_FNCSEL5_Enum;

/* ========================================================  PINCFG6  ======================================================== */
/* =============================================  GPIO PINCFG6 NCEPOL6 [22..22]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG6_NCEPOL6                                                      */
  GPIO_PINCFG6_NCEPOL6_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG6_NCEPOL6_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG6_NCEPOL6_Enum;

/* =============================================  GPIO PINCFG6 NCESRC6 [16..21]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG6_NCESRC6                                                      */
  GPIO_PINCFG6_NCESRC6_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG6_NCESRC6_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG6_NCESRC6_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG6_NCESRC6_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG6_NCESRC6_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG6_NCESRC6_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG6_NCESRC6_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG6_NCESRC6_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG6_NCESRC6_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG6_NCESRC6_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG6_NCESRC6_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG6_NCESRC6_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG6_NCESRC6_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG6_NCESRC6_Enum;

/* ============================================  GPIO PINCFG6 PULLCFG6 [13..15]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG6_PULLCFG6                                                     */
  GPIO_PINCFG6_PULLCFG6_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG6_PULLCFG6_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG6_PULLCFG6_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG6_PULLCFG6_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG6_PULLCFG6_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG6_PULLCFG6_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG6_PULLCFG6_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG6_PULLCFG6_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG6_PULLCFG6_Enum;

/* ===============================================  GPIO PINCFG6 DS6 [10..11]  =============================================== */
typedef enum {                                  /*!< GPIO_PINCFG6_DS6                                                          */
  GPIO_PINCFG6_DS6_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG6_DS6_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG6_DS6_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG6_DS6_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG6_DS6_Enum;

/* ==============================================  GPIO PINCFG6 OUTCFG6 [8..9]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG6_OUTCFG6                                                      */
  GPIO_PINCFG6_OUTCFG6_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG6_OUTCFG6_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG6_OUTCFG6_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG6_OUTCFG6_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG6_OUTCFG6_Enum;

/* ==============================================  GPIO PINCFG6 IRPTEN6 [6..7]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG6_IRPTEN6                                                      */
  GPIO_PINCFG6_IRPTEN6_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG6_IRPTEN6_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG6_IRPTEN6_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG6_IRPTEN6_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG6_IRPTEN6_Enum;

/* ==============================================  GPIO PINCFG6 FNCSEL6 [0..3]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG6_FNCSEL6                                                      */
  GPIO_PINCFG6_FNCSEL6_M0SDAWIR3       = 0,     /*!< M0SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
                                                     Master Data I/O (SPI 3 wire mode) (IOM 0)                                 */
  GPIO_PINCFG6_FNCSEL6_M0MOSI          = 1,     /*!< M0MOSI : Serial SPI Master MOSI output (IOM 0)                            */
  GPIO_PINCFG6_FNCSEL6_I2S0_DATA       = 2,     /*!< I2S0_DATA : Bidirectional I2S Data. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG6_FNCSEL6_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG6_FNCSEL6_UART0CTS        = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
  GPIO_PINCFG6_FNCSEL6_UART1CTS        = 5,     /*!< UART1CTS : UART Clear to Send (CTS) (UART 1)                              */
  GPIO_PINCFG6_FNCSEL6_CT6             = 6,     /*!< CT6 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG6_FNCSEL6_NCE6            = 7,     /*!< NCE6 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG6_FNCSEL6_OBSBUS6         = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
  GPIO_PINCFG6_FNCSEL6_I2S0_SDOUT      = 9,     /*!< I2S0_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
  GPIO_PINCFG6_FNCSEL6_I2S1_SDOUT      = 10,    /*!< I2S1_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
  GPIO_PINCFG6_FNCSEL6_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG6_FNCSEL6_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG6_FNCSEL6_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG6_FNCSEL6_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG6_FNCSEL6_SCANIN6         = 15,    /*!< SCANIN6 : Internal function (SCAN)                                        */
} GPIO_PINCFG6_FNCSEL6_Enum;

/* ========================================================  PINCFG7  ======================================================== */
/* =============================================  GPIO PINCFG7 NCEPOL7 [22..22]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG7_NCEPOL7                                                      */
  GPIO_PINCFG7_NCEPOL7_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG7_NCEPOL7_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG7_NCEPOL7_Enum;

/* =============================================  GPIO PINCFG7 NCESRC7 [16..21]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG7_NCESRC7                                                      */
  GPIO_PINCFG7_NCESRC7_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG7_NCESRC7_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG7_NCESRC7_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG7_NCESRC7_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG7_NCESRC7_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG7_NCESRC7_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG7_NCESRC7_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG7_NCESRC7_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG7_NCESRC7_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG7_NCESRC7_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG7_NCESRC7_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG7_NCESRC7_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG7_NCESRC7_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG7_NCESRC7_Enum;

/* ============================================  GPIO PINCFG7 PULLCFG7 [13..15]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG7_PULLCFG7                                                     */
  GPIO_PINCFG7_PULLCFG7_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG7_PULLCFG7_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG7_PULLCFG7_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG7_PULLCFG7_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG7_PULLCFG7_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG7_PULLCFG7_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG7_PULLCFG7_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG7_PULLCFG7_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG7_PULLCFG7_Enum;

/* ===============================================  GPIO PINCFG7 DS7 [10..11]  =============================================== */
typedef enum {                                  /*!< GPIO_PINCFG7_DS7                                                          */
  GPIO_PINCFG7_DS7_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG7_DS7_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG7_DS7_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG7_DS7_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG7_DS7_Enum;

/* ==============================================  GPIO PINCFG7 OUTCFG7 [8..9]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG7_OUTCFG7                                                      */
  GPIO_PINCFG7_OUTCFG7_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG7_OUTCFG7_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG7_OUTCFG7_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG7_OUTCFG7_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG7_OUTCFG7_Enum;

/* ==============================================  GPIO PINCFG7 IRPTEN7 [6..7]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG7_IRPTEN7                                                      */
  GPIO_PINCFG7_IRPTEN7_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG7_IRPTEN7_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG7_IRPTEN7_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG7_IRPTEN7_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG7_IRPTEN7_Enum;

/* ==============================================  GPIO PINCFG7 FNCSEL7 [0..3]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG7_FNCSEL7                                                      */
  GPIO_PINCFG7_FNCSEL7_M0MISO          = 0,     /*!< M0MISO : Serial SPI MASTER MISO input (IOM 0)                             */
  GPIO_PINCFG7_FNCSEL7_TRIG0           = 1,     /*!< TRIG0 : ADC trigger input                                                 */
  GPIO_PINCFG7_FNCSEL7_I2S0_WS         = 2,     /*!< I2S0_WS : Bidirectional I2S L/R clock. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG7_FNCSEL7_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG7_FNCSEL7_UART2CTS        = 4,     /*!< UART2CTS : UART Clear to Send (CTS) (UART 2)                              */
  GPIO_PINCFG7_FNCSEL7_UART3CTS        = 5,     /*!< UART3CTS : UART Clear to Send (CTS) (UART 3)                              */
  GPIO_PINCFG7_FNCSEL7_CT7             = 6,     /*!< CT7 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG7_FNCSEL7_NCE7            = 7,     /*!< NCE7 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG7_FNCSEL7_OBSBUS7         = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
  GPIO_PINCFG7_FNCSEL7_RESERVED9       = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG7_FNCSEL7_I2S1_WS         = 10,    /*!< I2S1_WS : Bidirectional I2S L/R clock. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG7_FNCSEL7_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG7_FNCSEL7_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG7_FNCSEL7_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG7_FNCSEL7_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG7_FNCSEL7_SCANIN7         = 15,    /*!< SCANIN7 : Internal function (SCAN)                                        */
} GPIO_PINCFG7_FNCSEL7_Enum;

/* ========================================================  PINCFG8  ======================================================== */
/* =============================================  GPIO PINCFG8 NCEPOL8 [22..22]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG8_NCEPOL8                                                      */
  GPIO_PINCFG8_NCEPOL8_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG8_NCEPOL8_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG8_NCEPOL8_Enum;

/* =============================================  GPIO PINCFG8 NCESRC8 [16..21]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG8_NCESRC8                                                      */
  GPIO_PINCFG8_NCESRC8_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG8_NCESRC8_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG8_NCESRC8_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG8_NCESRC8_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG8_NCESRC8_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG8_NCESRC8_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG8_NCESRC8_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG8_NCESRC8_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG8_NCESRC8_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG8_NCESRC8_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG8_NCESRC8_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG8_NCESRC8_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG8_NCESRC8_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG8_NCESRC8_Enum;

/* ============================================  GPIO PINCFG8 PULLCFG8 [13..15]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG8_PULLCFG8                                                     */
  GPIO_PINCFG8_PULLCFG8_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG8_PULLCFG8_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG8_PULLCFG8_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG8_PULLCFG8_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG8_PULLCFG8_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG8_PULLCFG8_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG8_PULLCFG8_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG8_PULLCFG8_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG8_PULLCFG8_Enum;

/* ===============================================  GPIO PINCFG8 DS8 [10..11]  =============================================== */
typedef enum {                                  /*!< GPIO_PINCFG8_DS8                                                          */
  GPIO_PINCFG8_DS8_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG8_DS8_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG8_DS8_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG8_DS8_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG8_DS8_Enum;

/* ==============================================  GPIO PINCFG8 OUTCFG8 [8..9]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG8_OUTCFG8                                                      */
  GPIO_PINCFG8_OUTCFG8_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG8_OUTCFG8_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG8_OUTCFG8_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG8_OUTCFG8_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG8_OUTCFG8_Enum;

/* ==============================================  GPIO PINCFG8 IRPTEN8 [6..7]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG8_IRPTEN8                                                      */
  GPIO_PINCFG8_IRPTEN8_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG8_IRPTEN8_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG8_IRPTEN8_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG8_IRPTEN8_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG8_IRPTEN8_Enum;

/* ==============================================  GPIO PINCFG8 FNCSEL8 [0..3]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG8_FNCSEL8                                                      */
  GPIO_PINCFG8_FNCSEL8_CMPRF1          = 0,     /*!< CMPRF1 : Comparator reference 1                                           */
  GPIO_PINCFG8_FNCSEL8_TRIG1           = 1,     /*!< TRIG1 : ADC trigger input                                                 */
  GPIO_PINCFG8_FNCSEL8_RESERVED2       = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG8_FNCSEL8_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG8_FNCSEL8_M1SCL           = 4,     /*!< M1SCL : Serial I2C Master Clock output (IOM 1)                            */
  GPIO_PINCFG8_FNCSEL8_M1SCK           = 5,     /*!< M1SCK : Serial SPI Master Clock output (IOM 1)                            */
  GPIO_PINCFG8_FNCSEL8_CT8             = 6,     /*!< CT8 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG8_FNCSEL8_NCE8            = 7,     /*!< NCE8 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG8_FNCSEL8_OBSBUS8         = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
  GPIO_PINCFG8_FNCSEL8_RESERVED9       = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG8_FNCSEL8_RESERVED10      = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG8_FNCSEL8_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG8_FNCSEL8_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG8_FNCSEL8_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG8_FNCSEL8_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG8_FNCSEL8_SCANOUT4        = 15,    /*!< SCANOUT4 : Internal function (SCAN)                                       */
} GPIO_PINCFG8_FNCSEL8_Enum;

/* ========================================================  PINCFG9  ======================================================== */
/* =============================================  GPIO PINCFG9 NCEPOL9 [22..22]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG9_NCEPOL9                                                      */
  GPIO_PINCFG9_NCEPOL9_LOW             = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG9_NCEPOL9_HIGH            = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG9_NCEPOL9_Enum;

/* =============================================  GPIO PINCFG9 NCESRC9 [16..21]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG9_NCESRC9                                                      */
  GPIO_PINCFG9_NCESRC9_IOM0CE0         = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM0CE1         = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM0CE2         = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM0CE3         = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM1CE0         = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM1CE1         = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM1CE2         = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM1CE3         = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM2CE0         = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM2CE1         = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM2CE2         = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM2CE3         = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM3CE0         = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM3CE1         = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM3CE2         = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM3CE3         = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM4CE0         = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM4CE1         = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM4CE2         = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM4CE3         = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM5CE0         = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM5CE1         = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM5CE2         = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM5CE3         = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM6CE0         = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM6CE1         = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM6CE2         = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM6CE3         = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM7CE0         = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM7CE1         = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM7CE2         = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG9_NCESRC9_IOM7CE3         = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG9_NCESRC9_MSPI0CEN0       = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG9_NCESRC9_MSPI0CEN1       = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG9_NCESRC9_MSPI1CEN0       = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG9_NCESRC9_MSPI1CEN1       = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG9_NCESRC9_MSPI2CEN0       = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG9_NCESRC9_MSPI2CEN1       = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG9_NCESRC9_DC_DPI_DE       = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG9_NCESRC9_DISP_CONT_CSX   = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG9_NCESRC9_DC_SPI_CS_N     = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG9_NCESRC9_DC_QSPI_CS_N    = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG9_NCESRC9_DC_RESX         = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG9_NCESRC9_Enum;

/* ============================================  GPIO PINCFG9 PULLCFG9 [13..15]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG9_PULLCFG9                                                     */
  GPIO_PINCFG9_PULLCFG9_DIS            = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG9_PULLCFG9_PD50K          = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG9_PULLCFG9_PU15K          = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG9_PULLCFG9_PU6K           = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG9_PULLCFG9_PU12K          = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG9_PULLCFG9_PU24K          = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG9_PULLCFG9_PU50K          = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG9_PULLCFG9_PU100K         = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG9_PULLCFG9_Enum;

/* ===============================================  GPIO PINCFG9 DS9 [10..11]  =============================================== */
typedef enum {                                  /*!< GPIO_PINCFG9_DS9                                                          */
  GPIO_PINCFG9_DS9_0P1X                = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG9_DS9_0P5X                = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG9_DS9_0P75X               = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG9_DS9_1P0X                = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG9_DS9_Enum;

/* ==============================================  GPIO PINCFG9 OUTCFG9 [8..9]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG9_OUTCFG9                                                      */
  GPIO_PINCFG9_OUTCFG9_DIS             = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG9_OUTCFG9_PUSHPULL        = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG9_OUTCFG9_OD              = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG9_OUTCFG9_TS              = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG9_OUTCFG9_Enum;

/* ==============================================  GPIO PINCFG9 IRPTEN9 [6..7]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG9_IRPTEN9                                                      */
  GPIO_PINCFG9_IRPTEN9_DIS             = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG9_IRPTEN9_INTFALL         = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG9_IRPTEN9_INTRISE         = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG9_IRPTEN9_INTANY          = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG9_IRPTEN9_Enum;

/* ==============================================  GPIO PINCFG9 FNCSEL9 [0..3]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG9_FNCSEL9                                                      */
  GPIO_PINCFG9_FNCSEL9_CMPRF0          = 0,     /*!< CMPRF0 : Comparator reference 0                                           */
  GPIO_PINCFG9_FNCSEL9_TRIG2           = 1,     /*!< TRIG2 : ADC trigger input                                                 */
  GPIO_PINCFG9_FNCSEL9_RESERVED2       = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG9_FNCSEL9_GPIO            = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG9_FNCSEL9_M1SDAWIR3       = 4,     /*!< M1SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
                                                     Master Data I/O (SPI 3 wire mode) (IOM 1)                                 */
  GPIO_PINCFG9_FNCSEL9_M1MOSI          = 5,     /*!< M1MOSI : Serial SPI Master MOSI output (IOM 1)                            */
  GPIO_PINCFG9_FNCSEL9_CT9             = 6,     /*!< CT9 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG9_FNCSEL9_NCE9            = 7,     /*!< NCE9 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG9_FNCSEL9_OBSBUS9         = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
  GPIO_PINCFG9_FNCSEL9_RESERVED9       = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG9_FNCSEL9_RESERVED10      = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG9_FNCSEL9_FPIO            = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG9_FNCSEL9_RESERVED12      = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG9_FNCSEL9_RESERVED13      = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG9_FNCSEL9_RESERVED14      = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG9_FNCSEL9_SCANOUT5        = 15,    /*!< SCANOUT5 : Internal function (SCAN)                                       */
} GPIO_PINCFG9_FNCSEL9_Enum;

/* =======================================================  PINCFG10  ======================================================== */
/* ============================================  GPIO PINCFG10 NCEPOL10 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG10_NCEPOL10                                                    */
  GPIO_PINCFG10_NCEPOL10_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG10_NCEPOL10_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG10_NCEPOL10_Enum;

/* ============================================  GPIO PINCFG10 NCESRC10 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG10_NCESRC10                                                    */
  GPIO_PINCFG10_NCESRC10_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG10_NCESRC10_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG10_NCESRC10_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG10_NCESRC10_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG10_NCESRC10_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG10_NCESRC10_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG10_NCESRC10_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG10_NCESRC10_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG10_NCESRC10_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG10_NCESRC10_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG10_NCESRC10_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG10_NCESRC10_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG10_NCESRC10_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG10_NCESRC10_Enum;

/* ===========================================  GPIO PINCFG10 PULLCFG10 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG10_PULLCFG10                                                   */
  GPIO_PINCFG10_PULLCFG10_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG10_PULLCFG10_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG10_PULLCFG10_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG10_PULLCFG10_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG10_PULLCFG10_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG10_PULLCFG10_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG10_PULLCFG10_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG10_PULLCFG10_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG10_PULLCFG10_Enum;

/* ==============================================  GPIO PINCFG10 DS10 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG10_DS10                                                        */
  GPIO_PINCFG10_DS10_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG10_DS10_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG10_DS10_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG10_DS10_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG10_DS10_Enum;

/* =============================================  GPIO PINCFG10 OUTCFG10 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG10_OUTCFG10                                                    */
  GPIO_PINCFG10_OUTCFG10_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG10_OUTCFG10_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG10_OUTCFG10_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG10_OUTCFG10_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG10_OUTCFG10_Enum;

/* =============================================  GPIO PINCFG10 IRPTEN10 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG10_IRPTEN10                                                    */
  GPIO_PINCFG10_IRPTEN10_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG10_IRPTEN10_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG10_IRPTEN10_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG10_IRPTEN10_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG10_IRPTEN10_Enum;

/* =============================================  GPIO PINCFG10 FNCSEL10 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG10_FNCSEL10                                                    */
  GPIO_PINCFG10_FNCSEL10_CMPIN0        = 0,     /*!< CMPIN0 : Voltage comparator input 0                                       */
  GPIO_PINCFG10_FNCSEL10_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
  GPIO_PINCFG10_FNCSEL10_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG10_FNCSEL10_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG10_FNCSEL10_M1MISO        = 4,     /*!< M1MISO : Serial SPI MASTER MISO input (IOM 1)                             */
  GPIO_PINCFG10_FNCSEL10_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG10_FNCSEL10_CT10          = 6,     /*!< CT10 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG10_FNCSEL10_NCE10         = 7,     /*!< NCE10 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG10_FNCSEL10_OBSBUS10      = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
  GPIO_PINCFG10_FNCSEL10_DISP_TE       = 9,     /*!< DISP_TE : Display TE input                                                */
  GPIO_PINCFG10_FNCSEL10_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG10_FNCSEL10_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG10_FNCSEL10_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG10_FNCSEL10_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG10_FNCSEL10_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG10_FNCSEL10_OPCG_LOAD     = 15,    /*!< OPCG_LOAD : Internal function (SCAN)                                      */
} GPIO_PINCFG10_FNCSEL10_Enum;

/* =======================================================  PINCFG11  ======================================================== */
/* ============================================  GPIO PINCFG11 NCEPOL11 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG11_NCEPOL11                                                    */
  GPIO_PINCFG11_NCEPOL11_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG11_NCEPOL11_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG11_NCEPOL11_Enum;

/* ============================================  GPIO PINCFG11 NCESRC11 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG11_NCESRC11                                                    */
  GPIO_PINCFG11_NCESRC11_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG11_NCESRC11_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG11_NCESRC11_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG11_NCESRC11_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG11_NCESRC11_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG11_NCESRC11_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG11_NCESRC11_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG11_NCESRC11_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG11_NCESRC11_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG11_NCESRC11_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG11_NCESRC11_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG11_NCESRC11_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG11_NCESRC11_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG11_NCESRC11_Enum;

/* ===========================================  GPIO PINCFG11 PULLCFG11 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG11_PULLCFG11                                                   */
  GPIO_PINCFG11_PULLCFG11_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG11_PULLCFG11_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG11_PULLCFG11_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG11_PULLCFG11_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG11_PULLCFG11_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG11_PULLCFG11_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG11_PULLCFG11_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG11_PULLCFG11_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG11_PULLCFG11_Enum;

/* ==============================================  GPIO PINCFG11 DS11 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG11_DS11                                                        */
  GPIO_PINCFG11_DS11_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG11_DS11_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG11_DS11_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG11_DS11_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG11_DS11_Enum;

/* =============================================  GPIO PINCFG11 OUTCFG11 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG11_OUTCFG11                                                    */
  GPIO_PINCFG11_OUTCFG11_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG11_OUTCFG11_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG11_OUTCFG11_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG11_OUTCFG11_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG11_OUTCFG11_Enum;

/* =============================================  GPIO PINCFG11 IRPTEN11 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG11_IRPTEN11                                                    */
  GPIO_PINCFG11_IRPTEN11_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG11_IRPTEN11_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG11_IRPTEN11_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG11_IRPTEN11_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG11_IRPTEN11_Enum;

/* =============================================  GPIO PINCFG11 FNCSEL11 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG11_FNCSEL11                                                    */
  GPIO_PINCFG11_FNCSEL11_CMPIN1        = 0,     /*!< CMPIN1 : Voltage comparator input 1                                       */
  GPIO_PINCFG11_FNCSEL11_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
  GPIO_PINCFG11_FNCSEL11_I2S0_CLK      = 2,     /*!< I2S0_CLK : Bidirectional I2S Bit clock. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG11_FNCSEL11_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG11_FNCSEL11_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
  GPIO_PINCFG11_FNCSEL11_UART3RX       = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
  GPIO_PINCFG11_FNCSEL11_CT11          = 6,     /*!< CT11 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG11_FNCSEL11_NCE11         = 7,     /*!< NCE11 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG11_FNCSEL11_OBSBUS11      = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
  GPIO_PINCFG11_FNCSEL11_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG11_FNCSEL11_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG11_FNCSEL11_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG11_FNCSEL11_FLB_TCLK      = 12,    /*!< FLB_TCLK : Internal function (Flash Bist)                                 */
  GPIO_PINCFG11_FNCSEL11_FLLOAD_ADDR   = 13,    /*!< FLLOAD_ADDR : Internal function (Flash parallel load)                     */
  GPIO_PINCFG11_FNCSEL11_MDA_TCK       = 14,    /*!< MDA_TCK : Internal function (MBIST)                                       */
  GPIO_PINCFG11_FNCSEL11_SCANIN0       = 15,    /*!< SCANIN0 : Internal function (SCAN)                                        */
} GPIO_PINCFG11_FNCSEL11_Enum;

/* =======================================================  PINCFG12  ======================================================== */
/* ============================================  GPIO PINCFG12 NCEPOL12 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG12_NCEPOL12                                                    */
  GPIO_PINCFG12_NCEPOL12_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG12_NCEPOL12_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG12_NCEPOL12_Enum;

/* ============================================  GPIO PINCFG12 NCESRC12 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG12_NCESRC12                                                    */
  GPIO_PINCFG12_NCESRC12_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG12_NCESRC12_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG12_NCESRC12_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG12_NCESRC12_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG12_NCESRC12_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG12_NCESRC12_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG12_NCESRC12_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG12_NCESRC12_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG12_NCESRC12_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG12_NCESRC12_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG12_NCESRC12_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG12_NCESRC12_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG12_NCESRC12_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG12_NCESRC12_Enum;

/* ===========================================  GPIO PINCFG12 PULLCFG12 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG12_PULLCFG12                                                   */
  GPIO_PINCFG12_PULLCFG12_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG12_PULLCFG12_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG12_PULLCFG12_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG12_PULLCFG12_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG12_PULLCFG12_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG12_PULLCFG12_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG12_PULLCFG12_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG12_PULLCFG12_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG12_PULLCFG12_Enum;

/* ==============================================  GPIO PINCFG12 DS12 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG12_DS12                                                        */
  GPIO_PINCFG12_DS12_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG12_DS12_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG12_DS12_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG12_DS12_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG12_DS12_Enum;

/* =============================================  GPIO PINCFG12 OUTCFG12 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG12_OUTCFG12                                                    */
  GPIO_PINCFG12_OUTCFG12_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG12_OUTCFG12_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG12_OUTCFG12_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG12_OUTCFG12_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG12_OUTCFG12_Enum;

/* =============================================  GPIO PINCFG12 IRPTEN12 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG12_IRPTEN12                                                    */
  GPIO_PINCFG12_IRPTEN12_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG12_IRPTEN12_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG12_IRPTEN12_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG12_IRPTEN12_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG12_IRPTEN12_Enum;

/* =============================================  GPIO PINCFG12 FNCSEL12 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG12_FNCSEL12                                                    */
  GPIO_PINCFG12_FNCSEL12_ADCSE7        = 0,     /*!< ADCSE7 : Analog to Digital Converter SE IN7                               */
  GPIO_PINCFG12_FNCSEL12_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
  GPIO_PINCFG12_FNCSEL12_I2S0_DATA     = 2,     /*!< I2S0_DATA : Bidirectional I2S Data. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG12_FNCSEL12_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG12_FNCSEL12_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
  GPIO_PINCFG12_FNCSEL12_UART1TX       = 5,     /*!< UART1TX : UART transmit output (UART 1)                                   */
  GPIO_PINCFG12_FNCSEL12_CT12          = 6,     /*!< CT12 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG12_FNCSEL12_NCE12         = 7,     /*!< NCE12 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG12_FNCSEL12_OBSBUS12      = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
  GPIO_PINCFG12_FNCSEL12_CMPRF2        = 9,     /*!< CMPRF2 : Comparator reference 2                                           */
  GPIO_PINCFG12_FNCSEL12_I2S0_SDOUT    = 10,    /*!< I2S0_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
  GPIO_PINCFG12_FNCSEL12_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG12_FNCSEL12_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG12_FNCSEL12_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG12_FNCSEL12_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG12_FNCSEL12_SCANOUT3      = 15,    /*!< SCANOUT3 : Internal function (SCAN)                                       */
} GPIO_PINCFG12_FNCSEL12_Enum;

/* =======================================================  PINCFG13  ======================================================== */
/* ============================================  GPIO PINCFG13 NCEPOL13 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG13_NCEPOL13                                                    */
  GPIO_PINCFG13_NCEPOL13_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG13_NCEPOL13_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG13_NCEPOL13_Enum;

/* ============================================  GPIO PINCFG13 NCESRC13 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG13_NCESRC13                                                    */
  GPIO_PINCFG13_NCESRC13_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG13_NCESRC13_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG13_NCESRC13_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG13_NCESRC13_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG13_NCESRC13_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG13_NCESRC13_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG13_NCESRC13_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG13_NCESRC13_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG13_NCESRC13_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG13_NCESRC13_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG13_NCESRC13_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG13_NCESRC13_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG13_NCESRC13_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG13_NCESRC13_Enum;

/* ===========================================  GPIO PINCFG13 PULLCFG13 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG13_PULLCFG13                                                   */
  GPIO_PINCFG13_PULLCFG13_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG13_PULLCFG13_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG13_PULLCFG13_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG13_PULLCFG13_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG13_PULLCFG13_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG13_PULLCFG13_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG13_PULLCFG13_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG13_PULLCFG13_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG13_PULLCFG13_Enum;

/* ==============================================  GPIO PINCFG13 DS13 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG13_DS13                                                        */
  GPIO_PINCFG13_DS13_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG13_DS13_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG13_DS13_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG13_DS13_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG13_DS13_Enum;

/* =============================================  GPIO PINCFG13 OUTCFG13 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG13_OUTCFG13                                                    */
  GPIO_PINCFG13_OUTCFG13_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG13_OUTCFG13_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG13_OUTCFG13_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG13_OUTCFG13_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG13_OUTCFG13_Enum;

/* =============================================  GPIO PINCFG13 IRPTEN13 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG13_IRPTEN13                                                    */
  GPIO_PINCFG13_IRPTEN13_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG13_IRPTEN13_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG13_IRPTEN13_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG13_IRPTEN13_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG13_IRPTEN13_Enum;

/* =============================================  GPIO PINCFG13 FNCSEL13 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG13_FNCSEL13                                                    */
  GPIO_PINCFG13_FNCSEL13_ADCSE6        = 0,     /*!< ADCSE6 : Analog to Digital Converter SE IN6                               */
  GPIO_PINCFG13_FNCSEL13_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
  GPIO_PINCFG13_FNCSEL13_I2S0_WS       = 2,     /*!< I2S0_WS : Bidirectional I2S L/R clock. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG13_FNCSEL13_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG13_FNCSEL13_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
  GPIO_PINCFG13_FNCSEL13_UART3TX       = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
  GPIO_PINCFG13_FNCSEL13_CT13          = 6,     /*!< CT13 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG13_FNCSEL13_NCE13         = 7,     /*!< NCE13 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG13_FNCSEL13_OBSBUS13      = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
  GPIO_PINCFG13_FNCSEL13_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG13_FNCSEL13_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG13_FNCSEL13_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG13_FNCSEL13_FLB_FCLK      = 12,    /*!< FLB_FCLK : Internal function (Flash Bist)                                 */
  GPIO_PINCFG13_FNCSEL13_FLLOAD_DATA   = 13,    /*!< FLLOAD_DATA : Internal function (Flash parallel load)                     */
  GPIO_PINCFG13_FNCSEL13_MDA_TDI       = 14,    /*!< MDA_TDI : Internal function (MBIST)                                       */
  GPIO_PINCFG13_FNCSEL13_SCANOUT0      = 15,    /*!< SCANOUT0 : Internal function (SCAN)                                       */
} GPIO_PINCFG13_FNCSEL13_Enum;

/* =======================================================  PINCFG14  ======================================================== */
/* ============================================  GPIO PINCFG14 NCEPOL14 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG14_NCEPOL14                                                    */
  GPIO_PINCFG14_NCEPOL14_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG14_NCEPOL14_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG14_NCEPOL14_Enum;

/* ============================================  GPIO PINCFG14 NCESRC14 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG14_NCESRC14                                                    */
  GPIO_PINCFG14_NCESRC14_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG14_NCESRC14_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG14_NCESRC14_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG14_NCESRC14_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG14_NCESRC14_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG14_NCESRC14_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG14_NCESRC14_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG14_NCESRC14_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG14_NCESRC14_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG14_NCESRC14_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG14_NCESRC14_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG14_NCESRC14_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG14_NCESRC14_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG14_NCESRC14_Enum;

/* ===========================================  GPIO PINCFG14 PULLCFG14 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG14_PULLCFG14                                                   */
  GPIO_PINCFG14_PULLCFG14_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG14_PULLCFG14_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG14_PULLCFG14_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG14_PULLCFG14_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG14_PULLCFG14_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG14_PULLCFG14_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG14_PULLCFG14_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG14_PULLCFG14_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG14_PULLCFG14_Enum;

/* ==============================================  GPIO PINCFG14 DS14 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG14_DS14                                                        */
  GPIO_PINCFG14_DS14_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG14_DS14_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG14_DS14_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG14_DS14_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG14_DS14_Enum;

/* =============================================  GPIO PINCFG14 OUTCFG14 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG14_OUTCFG14                                                    */
  GPIO_PINCFG14_OUTCFG14_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG14_OUTCFG14_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG14_OUTCFG14_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG14_OUTCFG14_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG14_OUTCFG14_Enum;

/* =============================================  GPIO PINCFG14 IRPTEN14 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG14_IRPTEN14                                                    */
  GPIO_PINCFG14_IRPTEN14_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG14_IRPTEN14_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG14_IRPTEN14_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG14_IRPTEN14_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG14_IRPTEN14_Enum;

/* =============================================  GPIO PINCFG14 FNCSEL14 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG14_FNCSEL14                                                    */
  GPIO_PINCFG14_FNCSEL14_ADCSE5        = 0,     /*!< ADCSE5 : Analog to Digital Converter SE IN5                               */
  GPIO_PINCFG14_FNCSEL14_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
  GPIO_PINCFG14_FNCSEL14_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG14_FNCSEL14_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG14_FNCSEL14_MILLI_CLK     = 4,     /*!< MILLI_CLK : MILLI Clock                                                   */
  GPIO_PINCFG14_FNCSEL14_UART1RX       = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
  GPIO_PINCFG14_FNCSEL14_CT14          = 6,     /*!< CT14 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG14_FNCSEL14_NCE14         = 7,     /*!< NCE14 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG14_FNCSEL14_OBSBUS14      = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
  GPIO_PINCFG14_FNCSEL14_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG14_FNCSEL14_I2S0_SDIN     = 10,    /*!< I2S0_SDIN : I2S Data input (I2S Master/Slave 2)                           */
  GPIO_PINCFG14_FNCSEL14_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG14_FNCSEL14_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG14_FNCSEL14_FLLOAD_ADDR   = 13,    /*!< FLLOAD_ADDR : Internal function (Flash parallel load)                     */
  GPIO_PINCFG14_FNCSEL14_MDA_TRSTN     = 14,    /*!< MDA_TRSTN : Internal function (MBIST)                                     */
  GPIO_PINCFG14_FNCSEL14_SCANOUT2      = 15,    /*!< SCANOUT2 : Internal function (SCAN)                                       */
} GPIO_PINCFG14_FNCSEL14_Enum;

/* =======================================================  PINCFG15  ======================================================== */
/* ============================================  GPIO PINCFG15 NCEPOL15 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG15_NCEPOL15                                                    */
  GPIO_PINCFG15_NCEPOL15_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG15_NCEPOL15_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG15_NCEPOL15_Enum;

/* ============================================  GPIO PINCFG15 NCESRC15 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG15_NCESRC15                                                    */
  GPIO_PINCFG15_NCESRC15_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG15_NCESRC15_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG15_NCESRC15_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG15_NCESRC15_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG15_NCESRC15_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG15_NCESRC15_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG15_NCESRC15_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG15_NCESRC15_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG15_NCESRC15_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG15_NCESRC15_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG15_NCESRC15_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG15_NCESRC15_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG15_NCESRC15_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG15_NCESRC15_Enum;

/* ===========================================  GPIO PINCFG15 PULLCFG15 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG15_PULLCFG15                                                   */
  GPIO_PINCFG15_PULLCFG15_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG15_PULLCFG15_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG15_PULLCFG15_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG15_PULLCFG15_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG15_PULLCFG15_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG15_PULLCFG15_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG15_PULLCFG15_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG15_PULLCFG15_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG15_PULLCFG15_Enum;

/* ==============================================  GPIO PINCFG15 DS15 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG15_DS15                                                        */
  GPIO_PINCFG15_DS15_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG15_DS15_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG15_DS15_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG15_DS15_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG15_DS15_Enum;

/* =============================================  GPIO PINCFG15 OUTCFG15 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG15_OUTCFG15                                                    */
  GPIO_PINCFG15_OUTCFG15_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG15_OUTCFG15_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG15_OUTCFG15_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG15_OUTCFG15_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG15_OUTCFG15_Enum;

/* =============================================  GPIO PINCFG15 IRPTEN15 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG15_IRPTEN15                                                    */
  GPIO_PINCFG15_IRPTEN15_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG15_IRPTEN15_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG15_IRPTEN15_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG15_IRPTEN15_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG15_IRPTEN15_Enum;

/* =============================================  GPIO PINCFG15 FNCSEL15 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG15_FNCSEL15                                                    */
  GPIO_PINCFG15_FNCSEL15_ADCSE4        = 0,     /*!< ADCSE4 : Analog to Digital Converter SE IN4                               */
  GPIO_PINCFG15_FNCSEL15_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
  GPIO_PINCFG15_FNCSEL15_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG15_FNCSEL15_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG15_FNCSEL15_MILLI_REC_DAT = 4,     /*!< MILLI_REC_DAT : MILLI Record Data                                         */
  GPIO_PINCFG15_FNCSEL15_UART3RX       = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
  GPIO_PINCFG15_FNCSEL15_CT15          = 6,     /*!< CT15 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG15_FNCSEL15_NCE15         = 7,     /*!< NCE15 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG15_FNCSEL15_OBSBUS15      = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
  GPIO_PINCFG15_FNCSEL15_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG15_FNCSEL15_REFCLK_EXT    = 10,    /*!< REFCLK_EXT : External Reference Clock                                     */
  GPIO_PINCFG15_FNCSEL15_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG15_FNCSEL15_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG15_FNCSEL15_FLLOAD_DATA   = 13,    /*!< FLLOAD_DATA : Internal function (Flash parallel load)                     */
  GPIO_PINCFG15_FNCSEL15_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG15_FNCSEL15_SCANOUT1      = 15,    /*!< SCANOUT1 : Internal function (SCAN)                                       */
} GPIO_PINCFG15_FNCSEL15_Enum;

/* =======================================================  PINCFG16  ======================================================== */
/* ============================================  GPIO PINCFG16 NCEPOL16 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG16_NCEPOL16                                                    */
  GPIO_PINCFG16_NCEPOL16_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG16_NCEPOL16_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG16_NCEPOL16_Enum;

/* ============================================  GPIO PINCFG16 NCESRC16 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG16_NCESRC16                                                    */
  GPIO_PINCFG16_NCESRC16_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG16_NCESRC16_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG16_NCESRC16_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG16_NCESRC16_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG16_NCESRC16_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG16_NCESRC16_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG16_NCESRC16_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG16_NCESRC16_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG16_NCESRC16_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG16_NCESRC16_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG16_NCESRC16_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG16_NCESRC16_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG16_NCESRC16_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG16_NCESRC16_Enum;

/* ===========================================  GPIO PINCFG16 PULLCFG16 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG16_PULLCFG16                                                   */
  GPIO_PINCFG16_PULLCFG16_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG16_PULLCFG16_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG16_PULLCFG16_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG16_PULLCFG16_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG16_PULLCFG16_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG16_PULLCFG16_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG16_PULLCFG16_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG16_PULLCFG16_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG16_PULLCFG16_Enum;

/* ==============================================  GPIO PINCFG16 DS16 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG16_DS16                                                        */
  GPIO_PINCFG16_DS16_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG16_DS16_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG16_DS16_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG16_DS16_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG16_DS16_Enum;

/* =============================================  GPIO PINCFG16 OUTCFG16 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG16_OUTCFG16                                                    */
  GPIO_PINCFG16_OUTCFG16_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG16_OUTCFG16_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG16_OUTCFG16_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG16_OUTCFG16_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG16_OUTCFG16_Enum;

/* =============================================  GPIO PINCFG16 IRPTEN16 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG16_IRPTEN16                                                    */
  GPIO_PINCFG16_IRPTEN16_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG16_IRPTEN16_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG16_IRPTEN16_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG16_IRPTEN16_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG16_IRPTEN16_Enum;

/* =============================================  GPIO PINCFG16 FNCSEL16 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG16_FNCSEL16                                                    */
  GPIO_PINCFG16_FNCSEL16_ADCSE3        = 0,     /*!< ADCSE3 : Analog to Digital Converter SE IN3                               */
  GPIO_PINCFG16_FNCSEL16_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
  GPIO_PINCFG16_FNCSEL16_I2S1_CLK      = 2,     /*!< I2S1_CLK : Bidirectional I2S Bit clock. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG16_FNCSEL16_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG16_FNCSEL16_MILLI_PBDATA1 = 4,     /*!< MILLI_PBDATA1 : MILLI Playback Data1                                      */
  GPIO_PINCFG16_FNCSEL16_UART1RTS      = 5,     /*!< UART1RTS : UART Request to Send (RTS) (UART 1)                            */
  GPIO_PINCFG16_FNCSEL16_CT16          = 6,     /*!< CT16 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG16_FNCSEL16_NCE16         = 7,     /*!< NCE16 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG16_FNCSEL16_OBSBUS0       = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
  GPIO_PINCFG16_FNCSEL16_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG16_FNCSEL16_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG16_FNCSEL16_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG16_FNCSEL16_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG16_FNCSEL16_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG16_FNCSEL16_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG16_FNCSEL16_DFT_RET       = 15,    /*!< DFT_RET : Internal function (SCAN)                                        */
} GPIO_PINCFG16_FNCSEL16_Enum;

/* =======================================================  PINCFG17  ======================================================== */
/* ============================================  GPIO PINCFG17 NCEPOL17 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG17_NCEPOL17                                                    */
  GPIO_PINCFG17_NCEPOL17_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG17_NCEPOL17_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG17_NCEPOL17_Enum;

/* ============================================  GPIO PINCFG17 NCESRC17 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG17_NCESRC17                                                    */
  GPIO_PINCFG17_NCESRC17_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG17_NCESRC17_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG17_NCESRC17_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG17_NCESRC17_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG17_NCESRC17_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG17_NCESRC17_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG17_NCESRC17_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG17_NCESRC17_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG17_NCESRC17_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG17_NCESRC17_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG17_NCESRC17_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG17_NCESRC17_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG17_NCESRC17_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG17_NCESRC17_Enum;

/* ===========================================  GPIO PINCFG17 PULLCFG17 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG17_PULLCFG17                                                   */
  GPIO_PINCFG17_PULLCFG17_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG17_PULLCFG17_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG17_PULLCFG17_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG17_PULLCFG17_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG17_PULLCFG17_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG17_PULLCFG17_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG17_PULLCFG17_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG17_PULLCFG17_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG17_PULLCFG17_Enum;

/* ==============================================  GPIO PINCFG17 DS17 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG17_DS17                                                        */
  GPIO_PINCFG17_DS17_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG17_DS17_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG17_DS17_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG17_DS17_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG17_DS17_Enum;

/* =============================================  GPIO PINCFG17 OUTCFG17 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG17_OUTCFG17                                                    */
  GPIO_PINCFG17_OUTCFG17_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG17_OUTCFG17_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG17_OUTCFG17_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG17_OUTCFG17_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG17_OUTCFG17_Enum;

/* =============================================  GPIO PINCFG17 IRPTEN17 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG17_IRPTEN17                                                    */
  GPIO_PINCFG17_IRPTEN17_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG17_IRPTEN17_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG17_IRPTEN17_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG17_IRPTEN17_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG17_IRPTEN17_Enum;

/* =============================================  GPIO PINCFG17 FNCSEL17 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG17_FNCSEL17                                                    */
  GPIO_PINCFG17_FNCSEL17_ADCSE2        = 0,     /*!< ADCSE2 : Analog to Digital Converter SE IN2                               */
  GPIO_PINCFG17_FNCSEL17_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
  GPIO_PINCFG17_FNCSEL17_I2S1_DATA     = 2,     /*!< I2S1_DATA : Bidirectional I2S Data. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG17_FNCSEL17_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG17_FNCSEL17_MILLI_PBDATA2 = 4,     /*!< MILLI_PBDATA2 : MILLI Playback Data2                                      */
  GPIO_PINCFG17_FNCSEL17_UART3RTS      = 5,     /*!< UART3RTS : UART Request to Send (RTS) (UART 3)                            */
  GPIO_PINCFG17_FNCSEL17_CT17          = 6,     /*!< CT17 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG17_FNCSEL17_NCE17         = 7,     /*!< NCE17 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG17_FNCSEL17_OBSBUS1       = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
  GPIO_PINCFG17_FNCSEL17_I2S1_SDOUT    = 9,     /*!< I2S1_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
  GPIO_PINCFG17_FNCSEL17_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG17_FNCSEL17_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG17_FNCSEL17_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG17_FNCSEL17_FLLOAD_STRB   = 13,    /*!< FLLOAD_STRB : Internal function (Flash parallel load)                     */
  GPIO_PINCFG17_FNCSEL17_MDA_TMS       = 14,    /*!< MDA_TMS : Internal function (MBIST)                                       */
  GPIO_PINCFG17_FNCSEL17_OPCG_CLK      = 15,    /*!< OPCG_CLK : Internal function (SCAN)                                       */
} GPIO_PINCFG17_FNCSEL17_Enum;

/* =======================================================  PINCFG18  ======================================================== */
/* ============================================  GPIO PINCFG18 NCEPOL18 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG18_NCEPOL18                                                    */
  GPIO_PINCFG18_NCEPOL18_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG18_NCEPOL18_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG18_NCEPOL18_Enum;

/* ============================================  GPIO PINCFG18 NCESRC18 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG18_NCESRC18                                                    */
  GPIO_PINCFG18_NCESRC18_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG18_NCESRC18_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG18_NCESRC18_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG18_NCESRC18_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG18_NCESRC18_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG18_NCESRC18_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG18_NCESRC18_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG18_NCESRC18_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG18_NCESRC18_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG18_NCESRC18_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG18_NCESRC18_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG18_NCESRC18_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG18_NCESRC18_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG18_NCESRC18_Enum;

/* ===========================================  GPIO PINCFG18 PULLCFG18 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG18_PULLCFG18                                                   */
  GPIO_PINCFG18_PULLCFG18_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG18_PULLCFG18_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG18_PULLCFG18_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG18_PULLCFG18_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG18_PULLCFG18_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG18_PULLCFG18_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG18_PULLCFG18_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG18_PULLCFG18_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG18_PULLCFG18_Enum;

/* ==============================================  GPIO PINCFG18 DS18 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG18_DS18                                                        */
  GPIO_PINCFG18_DS18_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG18_DS18_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG18_DS18_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG18_DS18_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG18_DS18_Enum;

/* =============================================  GPIO PINCFG18 OUTCFG18 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG18_OUTCFG18                                                    */
  GPIO_PINCFG18_OUTCFG18_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG18_OUTCFG18_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG18_OUTCFG18_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG18_OUTCFG18_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG18_OUTCFG18_Enum;

/* =============================================  GPIO PINCFG18 IRPTEN18 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG18_IRPTEN18                                                    */
  GPIO_PINCFG18_IRPTEN18_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG18_IRPTEN18_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG18_IRPTEN18_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG18_IRPTEN18_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG18_IRPTEN18_Enum;

/* =============================================  GPIO PINCFG18 FNCSEL18 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG18_FNCSEL18                                                    */
  GPIO_PINCFG18_FNCSEL18_ADCSE1        = 0,     /*!< ADCSE1 : Analog to Digital Converter SE IN1                               */
  GPIO_PINCFG18_FNCSEL18_ANATEST2      = 1,     /*!< ANATEST2 : Ambiq Analog test I/O - Unbuffered                             */
  GPIO_PINCFG18_FNCSEL18_I2S1_WS       = 2,     /*!< I2S1_WS : Bidirectional I2S L/R clock. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG18_FNCSEL18_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG18_FNCSEL18_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
  GPIO_PINCFG18_FNCSEL18_UART1CTS      = 5,     /*!< UART1CTS : UART Clear to Send (CTS) (UART 1)                              */
  GPIO_PINCFG18_FNCSEL18_CT18          = 6,     /*!< CT18 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG18_FNCSEL18_NCE18         = 7,     /*!< NCE18 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG18_FNCSEL18_OBSBUS2       = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
  GPIO_PINCFG18_FNCSEL18_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG18_FNCSEL18_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG18_FNCSEL18_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG18_FNCSEL18_FLB_TMS       = 12,    /*!< FLB_TMS : Internal function (Flash Bist)                                  */
  GPIO_PINCFG18_FNCSEL18_FLLOAD_DATA   = 13,    /*!< FLLOAD_DATA : Internal function (Flash parallel load)                     */
  GPIO_PINCFG18_FNCSEL18_MDA_HFRC_EXT  = 14,    /*!< MDA_HFRC_EXT : Internal function (MBIST)                                  */
  GPIO_PINCFG18_FNCSEL18_SCANIN1       = 15,    /*!< SCANIN1 : Internal function (SCAN)                                        */
} GPIO_PINCFG18_FNCSEL18_Enum;

/* =======================================================  PINCFG19  ======================================================== */
/* ============================================  GPIO PINCFG19 NCEPOL19 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG19_NCEPOL19                                                    */
  GPIO_PINCFG19_NCEPOL19_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG19_NCEPOL19_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG19_NCEPOL19_Enum;

/* ============================================  GPIO PINCFG19 NCESRC19 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG19_NCESRC19                                                    */
  GPIO_PINCFG19_NCESRC19_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG19_NCESRC19_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG19_NCESRC19_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG19_NCESRC19_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG19_NCESRC19_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG19_NCESRC19_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG19_NCESRC19_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG19_NCESRC19_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG19_NCESRC19_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG19_NCESRC19_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG19_NCESRC19_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG19_NCESRC19_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG19_NCESRC19_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG19_NCESRC19_Enum;

/* ===========================================  GPIO PINCFG19 PULLCFG19 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG19_PULLCFG19                                                   */
  GPIO_PINCFG19_PULLCFG19_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG19_PULLCFG19_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG19_PULLCFG19_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG19_PULLCFG19_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG19_PULLCFG19_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG19_PULLCFG19_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG19_PULLCFG19_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG19_PULLCFG19_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG19_PULLCFG19_Enum;

/* ==============================================  GPIO PINCFG19 DS19 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG19_DS19                                                        */
  GPIO_PINCFG19_DS19_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG19_DS19_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG19_DS19_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG19_DS19_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG19_DS19_Enum;

/* =============================================  GPIO PINCFG19 OUTCFG19 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG19_OUTCFG19                                                    */
  GPIO_PINCFG19_OUTCFG19_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG19_OUTCFG19_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG19_OUTCFG19_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG19_OUTCFG19_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG19_OUTCFG19_Enum;

/* =============================================  GPIO PINCFG19 IRPTEN19 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG19_IRPTEN19                                                    */
  GPIO_PINCFG19_IRPTEN19_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG19_IRPTEN19_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG19_IRPTEN19_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG19_IRPTEN19_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG19_IRPTEN19_Enum;

/* =============================================  GPIO PINCFG19 FNCSEL19 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG19_FNCSEL19                                                    */
  GPIO_PINCFG19_FNCSEL19_ADCSE0        = 0,     /*!< ADCSE0 : Analog to Digital Converter SE IN0                               */
  GPIO_PINCFG19_FNCSEL19_ANATEST1      = 1,     /*!< ANATEST1 : Ambiq Analog test I/O - Buffered                               */
  GPIO_PINCFG19_FNCSEL19_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG19_FNCSEL19_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG19_FNCSEL19_UART2CTS      = 4,     /*!< UART2CTS : UART Clear to Send (CTS) (UART 2)                              */
  GPIO_PINCFG19_FNCSEL19_UART3CTS      = 5,     /*!< UART3CTS : UART Clear to Send (CTS) (UART 3)                              */
  GPIO_PINCFG19_FNCSEL19_CT19          = 6,     /*!< CT19 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG19_FNCSEL19_NCE19         = 7,     /*!< NCE19 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG19_FNCSEL19_OBSBUS3       = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
  GPIO_PINCFG19_FNCSEL19_I2S1_SDIN     = 9,     /*!< I2S1_SDIN : I2S Data input (I2S Master/Slave 2)                           */
  GPIO_PINCFG19_FNCSEL19_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG19_FNCSEL19_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG19_FNCSEL19_FLB_TRSTN     = 12,    /*!< FLB_TRSTN : Internal function (Flash Bist)                                */
  GPIO_PINCFG19_FNCSEL19_FLLOAD_ADDR   = 13,    /*!< FLLOAD_ADDR : Internal function (Flash parallel load)                     */
  GPIO_PINCFG19_FNCSEL19_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG19_FNCSEL19_SCANIN2       = 15,    /*!< SCANIN2 : Internal function (SCAN)                                        */
} GPIO_PINCFG19_FNCSEL19_Enum;

/* =======================================================  PINCFG20  ======================================================== */
/* ============================================  GPIO PINCFG20 NCEPOL20 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG20_NCEPOL20                                                    */
  GPIO_PINCFG20_NCEPOL20_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG20_NCEPOL20_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG20_NCEPOL20_Enum;

/* ============================================  GPIO PINCFG20 NCESRC20 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG20_NCESRC20                                                    */
  GPIO_PINCFG20_NCESRC20_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG20_NCESRC20_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG20_NCESRC20_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG20_NCESRC20_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG20_NCESRC20_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG20_NCESRC20_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG20_NCESRC20_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG20_NCESRC20_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG20_NCESRC20_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG20_NCESRC20_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG20_NCESRC20_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG20_NCESRC20_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG20_NCESRC20_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG20_NCESRC20_Enum;

/* ===========================================  GPIO PINCFG20 PULLCFG20 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG20_PULLCFG20                                                   */
  GPIO_PINCFG20_PULLCFG20_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG20_PULLCFG20_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG20_PULLCFG20_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG20_PULLCFG20_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG20_PULLCFG20_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG20_PULLCFG20_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG20_PULLCFG20_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG20_PULLCFG20_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG20_PULLCFG20_Enum;

/* ==============================================  GPIO PINCFG20 DS20 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG20_DS20                                                        */
  GPIO_PINCFG20_DS20_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG20_DS20_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG20_DS20_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG20_DS20_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG20_DS20_Enum;

/* =============================================  GPIO PINCFG20 OUTCFG20 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG20_OUTCFG20                                                    */
  GPIO_PINCFG20_OUTCFG20_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG20_OUTCFG20_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG20_OUTCFG20_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG20_OUTCFG20_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG20_OUTCFG20_Enum;

/* =============================================  GPIO PINCFG20 IRPTEN20 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG20_IRPTEN20                                                    */
  GPIO_PINCFG20_IRPTEN20_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG20_IRPTEN20_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG20_IRPTEN20_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG20_IRPTEN20_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG20_IRPTEN20_Enum;

/* =============================================  GPIO PINCFG20 FNCSEL20 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG20_FNCSEL20                                                    */
  GPIO_PINCFG20_FNCSEL20_SWDCK         = 0,     /*!< SWDCK : Serial Wire Debug clock input                                     */
  GPIO_PINCFG20_FNCSEL20_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
  GPIO_PINCFG20_FNCSEL20_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG20_FNCSEL20_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG20_FNCSEL20_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
  GPIO_PINCFG20_FNCSEL20_UART1TX       = 5,     /*!< UART1TX : UART transmit output (UART 1)                                   */
  GPIO_PINCFG20_FNCSEL20_CT20          = 6,     /*!< CT20 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG20_FNCSEL20_NCE20         = 7,     /*!< NCE20 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG20_FNCSEL20_OBSBUS4       = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
  GPIO_PINCFG20_FNCSEL20_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG20_FNCSEL20_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG20_FNCSEL20_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG20_FNCSEL20_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG20_FNCSEL20_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG20_FNCSEL20_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG20_FNCSEL20_SCANCLK       = 15,    /*!< SCANCLK : Internal function (SCAN)                                        */
} GPIO_PINCFG20_FNCSEL20_Enum;

/* =======================================================  PINCFG21  ======================================================== */
/* ============================================  GPIO PINCFG21 NCEPOL21 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG21_NCEPOL21                                                    */
  GPIO_PINCFG21_NCEPOL21_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG21_NCEPOL21_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG21_NCEPOL21_Enum;

/* ============================================  GPIO PINCFG21 NCESRC21 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG21_NCESRC21                                                    */
  GPIO_PINCFG21_NCESRC21_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG21_NCESRC21_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG21_NCESRC21_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG21_NCESRC21_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG21_NCESRC21_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG21_NCESRC21_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG21_NCESRC21_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG21_NCESRC21_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG21_NCESRC21_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG21_NCESRC21_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG21_NCESRC21_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG21_NCESRC21_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG21_NCESRC21_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG21_NCESRC21_Enum;

/* ===========================================  GPIO PINCFG21 PULLCFG21 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG21_PULLCFG21                                                   */
  GPIO_PINCFG21_PULLCFG21_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG21_PULLCFG21_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG21_PULLCFG21_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG21_PULLCFG21_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG21_PULLCFG21_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG21_PULLCFG21_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG21_PULLCFG21_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG21_PULLCFG21_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG21_PULLCFG21_Enum;

/* ==============================================  GPIO PINCFG21 DS21 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG21_DS21                                                        */
  GPIO_PINCFG21_DS21_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG21_DS21_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG21_DS21_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG21_DS21_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG21_DS21_Enum;

/* =============================================  GPIO PINCFG21 OUTCFG21 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG21_OUTCFG21                                                    */
  GPIO_PINCFG21_OUTCFG21_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG21_OUTCFG21_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG21_OUTCFG21_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG21_OUTCFG21_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG21_OUTCFG21_Enum;

/* =============================================  GPIO PINCFG21 IRPTEN21 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG21_IRPTEN21                                                    */
  GPIO_PINCFG21_IRPTEN21_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG21_IRPTEN21_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG21_IRPTEN21_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG21_IRPTEN21_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG21_IRPTEN21_Enum;

/* =============================================  GPIO PINCFG21 FNCSEL21 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG21_FNCSEL21                                                    */
  GPIO_PINCFG21_FNCSEL21_SWDIO         = 0,     /*!< SWDIO : Serial Wire Debug data input/output                               */
  GPIO_PINCFG21_FNCSEL21_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
  GPIO_PINCFG21_FNCSEL21_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG21_FNCSEL21_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG21_FNCSEL21_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
  GPIO_PINCFG21_FNCSEL21_UART3TX       = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
  GPIO_PINCFG21_FNCSEL21_CT21          = 6,     /*!< CT21 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG21_FNCSEL21_NCE21         = 7,     /*!< NCE21 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG21_FNCSEL21_OBSBUS5       = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
  GPIO_PINCFG21_FNCSEL21_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG21_FNCSEL21_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG21_FNCSEL21_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG21_FNCSEL21_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG21_FNCSEL21_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG21_FNCSEL21_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG21_FNCSEL21_SCANSHFT      = 15,    /*!< SCANSHFT : Internal function (SCAN)                                       */
} GPIO_PINCFG21_FNCSEL21_Enum;

/* =======================================================  PINCFG22  ======================================================== */
/* ============================================  GPIO PINCFG22 NCEPOL22 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG22_NCEPOL22                                                    */
  GPIO_PINCFG22_NCEPOL22_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG22_NCEPOL22_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG22_NCEPOL22_Enum;

/* ============================================  GPIO PINCFG22 NCESRC22 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG22_NCESRC22                                                    */
  GPIO_PINCFG22_NCESRC22_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG22_NCESRC22_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG22_NCESRC22_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG22_NCESRC22_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG22_NCESRC22_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG22_NCESRC22_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG22_NCESRC22_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG22_NCESRC22_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG22_NCESRC22_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG22_NCESRC22_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG22_NCESRC22_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG22_NCESRC22_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG22_NCESRC22_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG22_NCESRC22_Enum;

/* ===========================================  GPIO PINCFG22 PULLCFG22 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG22_PULLCFG22                                                   */
  GPIO_PINCFG22_PULLCFG22_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG22_PULLCFG22_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG22_PULLCFG22_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG22_PULLCFG22_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG22_PULLCFG22_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG22_PULLCFG22_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG22_PULLCFG22_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG22_PULLCFG22_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG22_PULLCFG22_Enum;

/* ==============================================  GPIO PINCFG22 DS22 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG22_DS22                                                        */
  GPIO_PINCFG22_DS22_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG22_DS22_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG22_DS22_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG22_DS22_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG22_DS22_Enum;

/* =============================================  GPIO PINCFG22 OUTCFG22 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG22_OUTCFG22                                                    */
  GPIO_PINCFG22_OUTCFG22_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG22_OUTCFG22_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG22_OUTCFG22_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG22_OUTCFG22_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG22_OUTCFG22_Enum;

/* =============================================  GPIO PINCFG22 IRPTEN22 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG22_IRPTEN22                                                    */
  GPIO_PINCFG22_IRPTEN22_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG22_IRPTEN22_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG22_IRPTEN22_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG22_IRPTEN22_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG22_IRPTEN22_Enum;

/* =============================================  GPIO PINCFG22 FNCSEL22 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG22_FNCSEL22                                                    */
  GPIO_PINCFG22_FNCSEL22_M7SCL         = 0,     /*!< M7SCL : Serial I2C Master Clock output (IOM 7)                            */
  GPIO_PINCFG22_FNCSEL22_M7SCK         = 1,     /*!< M7SCK : Serial SPI Master Clock output (IOM 7)                            */
  GPIO_PINCFG22_FNCSEL22_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG22_FNCSEL22_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG22_FNCSEL22_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
  GPIO_PINCFG22_FNCSEL22_UART1RX       = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
  GPIO_PINCFG22_FNCSEL22_CT22          = 6,     /*!< CT22 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG22_FNCSEL22_NCE22         = 7,     /*!< NCE22 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG22_FNCSEL22_OBSBUS6       = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
  GPIO_PINCFG22_FNCSEL22_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG22_FNCSEL22_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG22_FNCSEL22_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG22_FNCSEL22_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG22_FNCSEL22_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG22_FNCSEL22_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG22_FNCSEL22_SCANIN3       = 15,    /*!< SCANIN3 : Internal function (SCAN)                                        */
} GPIO_PINCFG22_FNCSEL22_Enum;

/* =======================================================  PINCFG23  ======================================================== */
/* ============================================  GPIO PINCFG23 NCEPOL23 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG23_NCEPOL23                                                    */
  GPIO_PINCFG23_NCEPOL23_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG23_NCEPOL23_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG23_NCEPOL23_Enum;

/* ============================================  GPIO PINCFG23 NCESRC23 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG23_NCESRC23                                                    */
  GPIO_PINCFG23_NCESRC23_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG23_NCESRC23_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG23_NCESRC23_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG23_NCESRC23_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG23_NCESRC23_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG23_NCESRC23_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG23_NCESRC23_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG23_NCESRC23_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG23_NCESRC23_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG23_NCESRC23_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG23_NCESRC23_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG23_NCESRC23_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG23_NCESRC23_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG23_NCESRC23_Enum;

/* ===========================================  GPIO PINCFG23 PULLCFG23 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG23_PULLCFG23                                                   */
  GPIO_PINCFG23_PULLCFG23_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG23_PULLCFG23_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG23_PULLCFG23_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG23_PULLCFG23_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG23_PULLCFG23_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG23_PULLCFG23_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG23_PULLCFG23_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG23_PULLCFG23_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG23_PULLCFG23_Enum;

/* ==============================================  GPIO PINCFG23 DS23 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG23_DS23                                                        */
  GPIO_PINCFG23_DS23_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG23_DS23_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG23_DS23_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG23_DS23_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG23_DS23_Enum;

/* =============================================  GPIO PINCFG23 OUTCFG23 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG23_OUTCFG23                                                    */
  GPIO_PINCFG23_OUTCFG23_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG23_OUTCFG23_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG23_OUTCFG23_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG23_OUTCFG23_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG23_OUTCFG23_Enum;

/* =============================================  GPIO PINCFG23 IRPTEN23 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG23_IRPTEN23                                                    */
  GPIO_PINCFG23_IRPTEN23_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG23_IRPTEN23_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG23_IRPTEN23_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG23_IRPTEN23_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG23_IRPTEN23_Enum;

/* =============================================  GPIO PINCFG23 FNCSEL23 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG23_FNCSEL23                                                    */
  GPIO_PINCFG23_FNCSEL23_M7SDAWIR3     = 0,     /*!< M7SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
                                                     Master Data I/O (SPI 3 wire mode) (IOM 7)                                 */
  GPIO_PINCFG23_FNCSEL23_M7MOSI        = 1,     /*!< M7MOSI : Serial SPI Master MOSI output (IOM 7)                            */
  GPIO_PINCFG23_FNCSEL23_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG23_FNCSEL23_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG23_FNCSEL23_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
  GPIO_PINCFG23_FNCSEL23_UART3RX       = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
  GPIO_PINCFG23_FNCSEL23_CT23          = 6,     /*!< CT23 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG23_FNCSEL23_NCE23         = 7,     /*!< NCE23 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG23_FNCSEL23_OBSBUS7       = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
  GPIO_PINCFG23_FNCSEL23_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG23_FNCSEL23_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG23_FNCSEL23_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG23_FNCSEL23_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG23_FNCSEL23_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG23_FNCSEL23_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG23_FNCSEL23_SCANOUT6      = 15,    /*!< SCANOUT6 : Internal function (SCAN)                                       */
} GPIO_PINCFG23_FNCSEL23_Enum;

/* =======================================================  PINCFG24  ======================================================== */
/* ============================================  GPIO PINCFG24 NCEPOL24 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG24_NCEPOL24                                                    */
  GPIO_PINCFG24_NCEPOL24_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG24_NCEPOL24_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG24_NCEPOL24_Enum;

/* ============================================  GPIO PINCFG24 NCESRC24 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG24_NCESRC24                                                    */
  GPIO_PINCFG24_NCESRC24_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG24_NCESRC24_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG24_NCESRC24_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG24_NCESRC24_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG24_NCESRC24_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG24_NCESRC24_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG24_NCESRC24_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG24_NCESRC24_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG24_NCESRC24_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG24_NCESRC24_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG24_NCESRC24_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG24_NCESRC24_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG24_NCESRC24_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG24_NCESRC24_Enum;

/* ===========================================  GPIO PINCFG24 PULLCFG24 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG24_PULLCFG24                                                   */
  GPIO_PINCFG24_PULLCFG24_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG24_PULLCFG24_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG24_PULLCFG24_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG24_PULLCFG24_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG24_PULLCFG24_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG24_PULLCFG24_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG24_PULLCFG24_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG24_PULLCFG24_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG24_PULLCFG24_Enum;

/* ==============================================  GPIO PINCFG24 DS24 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG24_DS24                                                        */
  GPIO_PINCFG24_DS24_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG24_DS24_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG24_DS24_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG24_DS24_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG24_DS24_Enum;

/* =============================================  GPIO PINCFG24 OUTCFG24 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG24_OUTCFG24                                                    */
  GPIO_PINCFG24_OUTCFG24_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG24_OUTCFG24_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG24_OUTCFG24_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG24_OUTCFG24_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG24_OUTCFG24_Enum;

/* =============================================  GPIO PINCFG24 IRPTEN24 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG24_IRPTEN24                                                    */
  GPIO_PINCFG24_IRPTEN24_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG24_IRPTEN24_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG24_IRPTEN24_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG24_IRPTEN24_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG24_IRPTEN24_Enum;

/* =============================================  GPIO PINCFG24 FNCSEL24 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG24_FNCSEL24                                                    */
  GPIO_PINCFG24_FNCSEL24_M7MISO        = 0,     /*!< M7MISO : Serial SPI MASTER MISO input (IOM 7)                             */
  GPIO_PINCFG24_FNCSEL24_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
  GPIO_PINCFG24_FNCSEL24_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG24_FNCSEL24_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG24_FNCSEL24_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
  GPIO_PINCFG24_FNCSEL24_UART1RTS      = 5,     /*!< UART1RTS : UART Request to Send (RTS) (UART 1)                            */
  GPIO_PINCFG24_FNCSEL24_CT24          = 6,     /*!< CT24 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG24_FNCSEL24_NCE24         = 7,     /*!< NCE24 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG24_FNCSEL24_OBSBUS8       = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
  GPIO_PINCFG24_FNCSEL24_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG24_FNCSEL24_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG24_FNCSEL24_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG24_FNCSEL24_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG24_FNCSEL24_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG24_FNCSEL24_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG24_FNCSEL24_SCANOUT7      = 15,    /*!< SCANOUT7 : Internal function (SCAN)                                       */
} GPIO_PINCFG24_FNCSEL24_Enum;

/* =======================================================  PINCFG25  ======================================================== */
/* ============================================  GPIO PINCFG25 NCEPOL25 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG25_NCEPOL25                                                    */
  GPIO_PINCFG25_NCEPOL25_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG25_NCEPOL25_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG25_NCEPOL25_Enum;

/* ============================================  GPIO PINCFG25 NCESRC25 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG25_NCESRC25                                                    */
  GPIO_PINCFG25_NCESRC25_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG25_NCESRC25_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG25_NCESRC25_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG25_NCESRC25_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG25_NCESRC25_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG25_NCESRC25_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG25_NCESRC25_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG25_NCESRC25_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG25_NCESRC25_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG25_NCESRC25_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG25_NCESRC25_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG25_NCESRC25_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG25_NCESRC25_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG25_NCESRC25_Enum;

/* ===========================================  GPIO PINCFG25 PULLCFG25 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG25_PULLCFG25                                                   */
  GPIO_PINCFG25_PULLCFG25_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG25_PULLCFG25_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG25_PULLCFG25_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG25_PULLCFG25_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG25_PULLCFG25_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG25_PULLCFG25_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG25_PULLCFG25_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG25_PULLCFG25_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG25_PULLCFG25_Enum;

/* ==============================================  GPIO PINCFG25 DS25 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG25_DS25                                                        */
  GPIO_PINCFG25_DS25_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG25_DS25_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG25_DS25_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG25_DS25_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG25_DS25_Enum;

/* =============================================  GPIO PINCFG25 OUTCFG25 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG25_OUTCFG25                                                    */
  GPIO_PINCFG25_OUTCFG25_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG25_OUTCFG25_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG25_OUTCFG25_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG25_OUTCFG25_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG25_OUTCFG25_Enum;

/* =============================================  GPIO PINCFG25 IRPTEN25 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG25_IRPTEN25                                                    */
  GPIO_PINCFG25_IRPTEN25_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG25_IRPTEN25_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG25_IRPTEN25_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG25_IRPTEN25_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG25_IRPTEN25_Enum;

/* =============================================  GPIO PINCFG25 FNCSEL25 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG25_FNCSEL25                                                    */
  GPIO_PINCFG25_FNCSEL25_M2SCL         = 0,     /*!< M2SCL : Serial I2C Master Clock output (IOM 2)                            */
  GPIO_PINCFG25_FNCSEL25_M2SCK         = 1,     /*!< M2SCK : Serial SPI Master Clock output (IOM 2)                            */
  GPIO_PINCFG25_FNCSEL25_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG25_FNCSEL25_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG25_FNCSEL25_LFRC_EXT      = 4,     /*!< LFRC_EXT : External LFRC Clock                                            */
  GPIO_PINCFG25_FNCSEL25_DSP_TMS       = 5,     /*!< DSP_TMS : JTAG tms input                                                  */
  GPIO_PINCFG25_FNCSEL25_CT25          = 6,     /*!< CT25 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG25_FNCSEL25_NCE25         = 7,     /*!< NCE25 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG25_FNCSEL25_OBSBUS9       = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
  GPIO_PINCFG25_FNCSEL25_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG25_FNCSEL25_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG25_FNCSEL25_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG25_FNCSEL25_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG25_FNCSEL25_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG25_FNCSEL25_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG25_FNCSEL25_SCANIN8       = 15,    /*!< SCANIN8 : Internal function (SCAN)                                        */
} GPIO_PINCFG25_FNCSEL25_Enum;

/* =======================================================  PINCFG26  ======================================================== */
/* ============================================  GPIO PINCFG26 NCEPOL26 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG26_NCEPOL26                                                    */
  GPIO_PINCFG26_NCEPOL26_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG26_NCEPOL26_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG26_NCEPOL26_Enum;

/* ============================================  GPIO PINCFG26 NCESRC26 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG26_NCESRC26                                                    */
  GPIO_PINCFG26_NCESRC26_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG26_NCESRC26_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG26_NCESRC26_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG26_NCESRC26_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG26_NCESRC26_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG26_NCESRC26_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG26_NCESRC26_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG26_NCESRC26_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG26_NCESRC26_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG26_NCESRC26_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG26_NCESRC26_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG26_NCESRC26_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG26_NCESRC26_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG26_NCESRC26_Enum;

/* ===========================================  GPIO PINCFG26 PULLCFG26 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG26_PULLCFG26                                                   */
  GPIO_PINCFG26_PULLCFG26_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG26_PULLCFG26_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG26_PULLCFG26_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG26_PULLCFG26_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG26_PULLCFG26_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG26_PULLCFG26_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG26_PULLCFG26_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG26_PULLCFG26_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG26_PULLCFG26_Enum;

/* ==============================================  GPIO PINCFG26 DS26 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG26_DS26                                                        */
  GPIO_PINCFG26_DS26_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG26_DS26_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG26_DS26_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG26_DS26_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG26_DS26_Enum;

/* =============================================  GPIO PINCFG26 OUTCFG26 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG26_OUTCFG26                                                    */
  GPIO_PINCFG26_OUTCFG26_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG26_OUTCFG26_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG26_OUTCFG26_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG26_OUTCFG26_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG26_OUTCFG26_Enum;

/* =============================================  GPIO PINCFG26 IRPTEN26 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG26_IRPTEN26                                                    */
  GPIO_PINCFG26_IRPTEN26_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG26_IRPTEN26_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG26_IRPTEN26_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG26_IRPTEN26_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG26_IRPTEN26_Enum;

/* =============================================  GPIO PINCFG26 FNCSEL26 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG26_FNCSEL26                                                    */
  GPIO_PINCFG26_FNCSEL26_M2SDAWIR3     = 0,     /*!< M2SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
                                                     Master Data I/O (SPI 3 wire mode) (IOM 2)                                 */
  GPIO_PINCFG26_FNCSEL26_M2MOSI        = 1,     /*!< M2MOSI : Serial SPI Master MOSI output (IOM 2)                            */
  GPIO_PINCFG26_FNCSEL26_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG26_FNCSEL26_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG26_FNCSEL26_HFRC_EXT      = 4,     /*!< HFRC_EXT : External HFRC Clock                                            */
  GPIO_PINCFG26_FNCSEL26_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG26_FNCSEL26_CT26          = 6,     /*!< CT26 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG26_FNCSEL26_NCE26         = 7,     /*!< NCE26 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG26_FNCSEL26_OBSBUS10      = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
  GPIO_PINCFG26_FNCSEL26_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG26_FNCSEL26_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG26_FNCSEL26_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG26_FNCSEL26_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG26_FNCSEL26_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG26_FNCSEL26_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG26_FNCSEL26_SCANIN9       = 15,    /*!< SCANIN9 : Internal function (SCAN)                                        */
} GPIO_PINCFG26_FNCSEL26_Enum;

/* =======================================================  PINCFG27  ======================================================== */
/* ============================================  GPIO PINCFG27 NCEPOL27 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG27_NCEPOL27                                                    */
  GPIO_PINCFG27_NCEPOL27_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG27_NCEPOL27_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG27_NCEPOL27_Enum;

/* ============================================  GPIO PINCFG27 NCESRC27 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG27_NCESRC27                                                    */
  GPIO_PINCFG27_NCESRC27_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG27_NCESRC27_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG27_NCESRC27_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG27_NCESRC27_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG27_NCESRC27_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG27_NCESRC27_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG27_NCESRC27_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG27_NCESRC27_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG27_NCESRC27_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG27_NCESRC27_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG27_NCESRC27_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG27_NCESRC27_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG27_NCESRC27_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG27_NCESRC27_Enum;

/* ===========================================  GPIO PINCFG27 PULLCFG27 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG27_PULLCFG27                                                   */
  GPIO_PINCFG27_PULLCFG27_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG27_PULLCFG27_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG27_PULLCFG27_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG27_PULLCFG27_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG27_PULLCFG27_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG27_PULLCFG27_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG27_PULLCFG27_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG27_PULLCFG27_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG27_PULLCFG27_Enum;

/* ==============================================  GPIO PINCFG27 DS27 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG27_DS27                                                        */
  GPIO_PINCFG27_DS27_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG27_DS27_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG27_DS27_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG27_DS27_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG27_DS27_Enum;

/* =============================================  GPIO PINCFG27 OUTCFG27 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG27_OUTCFG27                                                    */
  GPIO_PINCFG27_OUTCFG27_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG27_OUTCFG27_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG27_OUTCFG27_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG27_OUTCFG27_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG27_OUTCFG27_Enum;

/* =============================================  GPIO PINCFG27 IRPTEN27 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG27_IRPTEN27                                                    */
  GPIO_PINCFG27_IRPTEN27_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG27_IRPTEN27_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG27_IRPTEN27_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG27_IRPTEN27_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG27_IRPTEN27_Enum;

/* =============================================  GPIO PINCFG27 FNCSEL27 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG27_FNCSEL27                                                    */
  GPIO_PINCFG27_FNCSEL27_M2MISO        = 0,     /*!< M2MISO : Serial SPI MASTER MISO input (IOM 2)                             */
  GPIO_PINCFG27_FNCSEL27_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
  GPIO_PINCFG27_FNCSEL27_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG27_FNCSEL27_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG27_FNCSEL27_XT_EXT        = 4,     /*!< XT_EXT : External XT Clock                                                */
  GPIO_PINCFG27_FNCSEL27_DSP_TCK       = 5,     /*!< DSP_TCK : JTAG tck clock interface                                        */
  GPIO_PINCFG27_FNCSEL27_CT27          = 6,     /*!< CT27 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG27_FNCSEL27_NCE27         = 7,     /*!< NCE27 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG27_FNCSEL27_OBSBUS11      = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
  GPIO_PINCFG27_FNCSEL27_I2S0_SDIN     = 9,     /*!< I2S0_SDIN : I2S Data input (I2S Master/Slave 2)                           */
  GPIO_PINCFG27_FNCSEL27_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG27_FNCSEL27_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG27_FNCSEL27_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG27_FNCSEL27_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG27_FNCSEL27_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG27_FNCSEL27_SCANIN10      = 15,    /*!< SCANIN10 : Internal function (SCAN)                                       */
} GPIO_PINCFG27_FNCSEL27_Enum;

/* =======================================================  PINCFG28  ======================================================== */
/* ============================================  GPIO PINCFG28 NCEPOL28 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG28_NCEPOL28                                                    */
  GPIO_PINCFG28_NCEPOL28_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG28_NCEPOL28_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG28_NCEPOL28_Enum;

/* ============================================  GPIO PINCFG28 NCESRC28 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG28_NCESRC28                                                    */
  GPIO_PINCFG28_NCESRC28_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG28_NCESRC28_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG28_NCESRC28_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG28_NCESRC28_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG28_NCESRC28_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG28_NCESRC28_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG28_NCESRC28_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG28_NCESRC28_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG28_NCESRC28_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG28_NCESRC28_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG28_NCESRC28_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG28_NCESRC28_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG28_NCESRC28_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG28_NCESRC28_Enum;

/* ===========================================  GPIO PINCFG28 PULLCFG28 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG28_PULLCFG28                                                   */
  GPIO_PINCFG28_PULLCFG28_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG28_PULLCFG28_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG28_PULLCFG28_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG28_PULLCFG28_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG28_PULLCFG28_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG28_PULLCFG28_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG28_PULLCFG28_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG28_PULLCFG28_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG28_PULLCFG28_Enum;

/* ==============================================  GPIO PINCFG28 DS28 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG28_DS28                                                        */
  GPIO_PINCFG28_DS28_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG28_DS28_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG28_DS28_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG28_DS28_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG28_DS28_Enum;

/* =============================================  GPIO PINCFG28 OUTCFG28 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG28_OUTCFG28                                                    */
  GPIO_PINCFG28_OUTCFG28_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG28_OUTCFG28_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG28_OUTCFG28_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG28_OUTCFG28_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG28_OUTCFG28_Enum;

/* =============================================  GPIO PINCFG28 IRPTEN28 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG28_IRPTEN28                                                    */
  GPIO_PINCFG28_IRPTEN28_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG28_IRPTEN28_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG28_IRPTEN28_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG28_IRPTEN28_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG28_IRPTEN28_Enum;

/* =============================================  GPIO PINCFG28 FNCSEL28 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG28_FNCSEL28                                                    */
  GPIO_PINCFG28_FNCSEL28_SWO           = 0,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG28_FNCSEL28_VCMPO         = 1,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG28_FNCSEL28_I2S0_CLK      = 2,     /*!< I2S0_CLK : Bidirectional I2S Bit clock. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG28_FNCSEL28_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG28_FNCSEL28_UART2CTS      = 4,     /*!< UART2CTS : UART Clear to Send (CTS) (UART 2)                              */
  GPIO_PINCFG28_FNCSEL28_DSP_TDO       = 5,     /*!< DSP_TDO : JTAG tdo output                                                 */
  GPIO_PINCFG28_FNCSEL28_CT28          = 6,     /*!< CT28 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG28_FNCSEL28_NCE28         = 7,     /*!< NCE28 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG28_FNCSEL28_OBSBUS12      = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
  GPIO_PINCFG28_FNCSEL28_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG28_FNCSEL28_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG28_FNCSEL28_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG28_FNCSEL28_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG28_FNCSEL28_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG28_FNCSEL28_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG28_FNCSEL28_CME           = 15,    /*!< CME : Internal function (SCAN)                                            */
} GPIO_PINCFG28_FNCSEL28_Enum;

/* =======================================================  PINCFG29  ======================================================== */
/* ==========================================  GPIO PINCFG29 VSSPWRSWEN29 [25..25]  ========================================== */
typedef enum {                                  /*!< GPIO_PINCFG29_VSSPWRSWEN29                                                */
  GPIO_PINCFG29_VSSPWRSWEN29_DIS       = 0,     /*!< DIS : Power switch is disabled                                            */
  GPIO_PINCFG29_VSSPWRSWEN29_EN        = 1,     /*!< EN : Power switch is enabled                                              */
} GPIO_PINCFG29_VSSPWRSWEN29_Enum;

/* ============================================  GPIO PINCFG29 NCEPOL29 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG29_NCEPOL29                                                    */
  GPIO_PINCFG29_NCEPOL29_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG29_NCEPOL29_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG29_NCEPOL29_Enum;

/* ============================================  GPIO PINCFG29 NCESRC29 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG29_NCESRC29                                                    */
  GPIO_PINCFG29_NCESRC29_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG29_NCESRC29_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG29_NCESRC29_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG29_NCESRC29_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG29_NCESRC29_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG29_NCESRC29_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG29_NCESRC29_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG29_NCESRC29_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG29_NCESRC29_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG29_NCESRC29_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG29_NCESRC29_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG29_NCESRC29_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG29_NCESRC29_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG29_NCESRC29_Enum;

/* ===========================================  GPIO PINCFG29 PULLCFG29 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG29_PULLCFG29                                                   */
  GPIO_PINCFG29_PULLCFG29_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG29_PULLCFG29_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG29_PULLCFG29_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG29_PULLCFG29_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG29_PULLCFG29_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG29_PULLCFG29_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG29_PULLCFG29_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG29_PULLCFG29_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG29_PULLCFG29_Enum;

/* ==============================================  GPIO PINCFG29 DS29 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG29_DS29                                                        */
  GPIO_PINCFG29_DS29_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG29_DS29_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG29_DS29_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG29_DS29_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG29_DS29_Enum;

/* =============================================  GPIO PINCFG29 OUTCFG29 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG29_OUTCFG29                                                    */
  GPIO_PINCFG29_OUTCFG29_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG29_OUTCFG29_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG29_OUTCFG29_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG29_OUTCFG29_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG29_OUTCFG29_Enum;

/* =============================================  GPIO PINCFG29 IRPTEN29 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG29_IRPTEN29                                                    */
  GPIO_PINCFG29_IRPTEN29_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG29_IRPTEN29_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG29_IRPTEN29_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG29_IRPTEN29_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG29_IRPTEN29_Enum;

/* =============================================  GPIO PINCFG29 FNCSEL29 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG29_FNCSEL29                                                    */
  GPIO_PINCFG29_FNCSEL29_TRIG0         = 0,     /*!< TRIG0 : ADC trigger input                                                 */
  GPIO_PINCFG29_FNCSEL29_VCMPO         = 1,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG29_FNCSEL29_I2S0_DATA     = 2,     /*!< I2S0_DATA : Bidirectional I2S Data. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG29_FNCSEL29_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG29_FNCSEL29_UART1CTS      = 4,     /*!< UART1CTS : UART Clear to Send (CTS) (UART 1)                              */
  GPIO_PINCFG29_FNCSEL29_DSP_TRSTN     = 5,     /*!< DSP_TRSTN : JTAG TRSTN input                                              */
  GPIO_PINCFG29_FNCSEL29_CT29          = 6,     /*!< CT29 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG29_FNCSEL29_NCE29         = 7,     /*!< NCE29 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG29_FNCSEL29_OBSBUS13      = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
  GPIO_PINCFG29_FNCSEL29_I2S0_SDOUT    = 9,     /*!< I2S0_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
  GPIO_PINCFG29_FNCSEL29_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG29_FNCSEL29_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG29_FNCSEL29_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG29_FNCSEL29_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG29_FNCSEL29_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG29_FNCSEL29_CMLE          = 15,    /*!< CMLE : Internal function (SCAN)                                           */
} GPIO_PINCFG29_FNCSEL29_Enum;

/* =======================================================  PINCFG30  ======================================================== */
/* ==========================================  GPIO PINCFG30 VDDPWRSWEN30 [25..25]  ========================================== */
typedef enum {                                  /*!< GPIO_PINCFG30_VDDPWRSWEN30                                                */
  GPIO_PINCFG30_VDDPWRSWEN30_DIS       = 0,     /*!< DIS : Power switch is disabled                                            */
  GPIO_PINCFG30_VDDPWRSWEN30_EN        = 1,     /*!< EN : Power switch is enabled                                              */
} GPIO_PINCFG30_VDDPWRSWEN30_Enum;

/* ============================================  GPIO PINCFG30 NCEPOL30 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG30_NCEPOL30                                                    */
  GPIO_PINCFG30_NCEPOL30_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG30_NCEPOL30_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG30_NCEPOL30_Enum;

/* ============================================  GPIO PINCFG30 NCESRC30 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG30_NCESRC30                                                    */
  GPIO_PINCFG30_NCESRC30_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG30_NCESRC30_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG30_NCESRC30_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG30_NCESRC30_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG30_NCESRC30_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG30_NCESRC30_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG30_NCESRC30_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG30_NCESRC30_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG30_NCESRC30_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG30_NCESRC30_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG30_NCESRC30_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG30_NCESRC30_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG30_NCESRC30_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG30_NCESRC30_Enum;

/* ===========================================  GPIO PINCFG30 PULLCFG30 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG30_PULLCFG30                                                   */
  GPIO_PINCFG30_PULLCFG30_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG30_PULLCFG30_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG30_PULLCFG30_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG30_PULLCFG30_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG30_PULLCFG30_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG30_PULLCFG30_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG30_PULLCFG30_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG30_PULLCFG30_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG30_PULLCFG30_Enum;

/* ==============================================  GPIO PINCFG30 DS30 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG30_DS30                                                        */
  GPIO_PINCFG30_DS30_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG30_DS30_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG30_DS30_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG30_DS30_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG30_DS30_Enum;

/* =============================================  GPIO PINCFG30 OUTCFG30 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG30_OUTCFG30                                                    */
  GPIO_PINCFG30_OUTCFG30_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG30_OUTCFG30_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG30_OUTCFG30_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG30_OUTCFG30_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG30_OUTCFG30_Enum;

/* =============================================  GPIO PINCFG30 IRPTEN30 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG30_IRPTEN30                                                    */
  GPIO_PINCFG30_IRPTEN30_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG30_IRPTEN30_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG30_IRPTEN30_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG30_IRPTEN30_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG30_IRPTEN30_Enum;

/* =============================================  GPIO PINCFG30 FNCSEL30 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG30_FNCSEL30                                                    */
  GPIO_PINCFG30_FNCSEL30_TRIG1         = 0,     /*!< TRIG1 : ADC trigger input                                                 */
  GPIO_PINCFG30_FNCSEL30_VCMPO         = 1,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG30_FNCSEL30_I2S0_WS       = 2,     /*!< I2S0_WS : Bidirectional I2S L/R clock. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG30_FNCSEL30_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG30_FNCSEL30_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
  GPIO_PINCFG30_FNCSEL30_DSP_TDI       = 5,     /*!< DSP_TDI : JTAG tdi input                                                  */
  GPIO_PINCFG30_FNCSEL30_CT30          = 6,     /*!< CT30 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG30_FNCSEL30_NCE30         = 7,     /*!< NCE30 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG30_FNCSEL30_OBSBUS14      = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
  GPIO_PINCFG30_FNCSEL30_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG30_FNCSEL30_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG30_FNCSEL30_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG30_FNCSEL30_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG30_FNCSEL30_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG30_FNCSEL30_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG30_FNCSEL30_SCANOUT8      = 15,    /*!< SCANOUT8 : Internal function (SCAN)                                       */
} GPIO_PINCFG30_FNCSEL30_Enum;

/* =======================================================  PINCFG31  ======================================================== */
/* ============================================  GPIO PINCFG31 NCEPOL31 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG31_NCEPOL31                                                    */
  GPIO_PINCFG31_NCEPOL31_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG31_NCEPOL31_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG31_NCEPOL31_Enum;

/* ============================================  GPIO PINCFG31 NCESRC31 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG31_NCESRC31                                                    */
  GPIO_PINCFG31_NCESRC31_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG31_NCESRC31_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG31_NCESRC31_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG31_NCESRC31_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG31_NCESRC31_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG31_NCESRC31_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG31_NCESRC31_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG31_NCESRC31_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG31_NCESRC31_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG31_NCESRC31_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG31_NCESRC31_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG31_NCESRC31_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG31_NCESRC31_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG31_NCESRC31_Enum;

/* ===========================================  GPIO PINCFG31 PULLCFG31 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG31_PULLCFG31                                                   */
  GPIO_PINCFG31_PULLCFG31_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG31_PULLCFG31_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG31_PULLCFG31_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG31_PULLCFG31_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG31_PULLCFG31_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG31_PULLCFG31_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG31_PULLCFG31_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG31_PULLCFG31_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG31_PULLCFG31_Enum;

/* ==============================================  GPIO PINCFG31 DS31 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG31_DS31                                                        */
  GPIO_PINCFG31_DS31_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG31_DS31_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG31_DS31_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG31_DS31_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG31_DS31_Enum;

/* =============================================  GPIO PINCFG31 OUTCFG31 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG31_OUTCFG31                                                    */
  GPIO_PINCFG31_OUTCFG31_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG31_OUTCFG31_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG31_OUTCFG31_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG31_OUTCFG31_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG31_OUTCFG31_Enum;

/* =============================================  GPIO PINCFG31 IRPTEN31 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG31_IRPTEN31                                                    */
  GPIO_PINCFG31_IRPTEN31_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG31_IRPTEN31_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG31_IRPTEN31_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG31_IRPTEN31_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG31_IRPTEN31_Enum;

/* =============================================  GPIO PINCFG31 FNCSEL31 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG31_FNCSEL31                                                    */
  GPIO_PINCFG31_FNCSEL31_M3SCL         = 0,     /*!< M3SCL : Serial I2C Master Clock output (IOM 3)                            */
  GPIO_PINCFG31_FNCSEL31_M3SCK         = 1,     /*!< M3SCK : Serial SPI Master Clock output (IOM 3)                            */
  GPIO_PINCFG31_FNCSEL31_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG31_FNCSEL31_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG31_FNCSEL31_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
  GPIO_PINCFG31_FNCSEL31_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG31_FNCSEL31_CT31          = 6,     /*!< CT31 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG31_FNCSEL31_NCE31         = 7,     /*!< NCE31 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG31_FNCSEL31_OBSBUS15      = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
  GPIO_PINCFG31_FNCSEL31_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG31_FNCSEL31_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG31_FNCSEL31_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG31_FNCSEL31_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG31_FNCSEL31_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG31_FNCSEL31_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG31_FNCSEL31_SCANOUT9      = 15,    /*!< SCANOUT9 : Internal function (SCAN)                                       */
} GPIO_PINCFG31_FNCSEL31_Enum;

/* =======================================================  PINCFG32  ======================================================== */
/* ============================================  GPIO PINCFG32 NCEPOL32 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG32_NCEPOL32                                                    */
  GPIO_PINCFG32_NCEPOL32_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG32_NCEPOL32_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG32_NCEPOL32_Enum;

/* ============================================  GPIO PINCFG32 NCESRC32 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG32_NCESRC32                                                    */
  GPIO_PINCFG32_NCESRC32_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG32_NCESRC32_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG32_NCESRC32_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG32_NCESRC32_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG32_NCESRC32_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG32_NCESRC32_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG32_NCESRC32_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG32_NCESRC32_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG32_NCESRC32_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG32_NCESRC32_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG32_NCESRC32_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG32_NCESRC32_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG32_NCESRC32_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG32_NCESRC32_Enum;

/* ===========================================  GPIO PINCFG32 PULLCFG32 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG32_PULLCFG32                                                   */
  GPIO_PINCFG32_PULLCFG32_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG32_PULLCFG32_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG32_PULLCFG32_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG32_PULLCFG32_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG32_PULLCFG32_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG32_PULLCFG32_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG32_PULLCFG32_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG32_PULLCFG32_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG32_PULLCFG32_Enum;

/* ==============================================  GPIO PINCFG32 DS32 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG32_DS32                                                        */
  GPIO_PINCFG32_DS32_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG32_DS32_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG32_DS32_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG32_DS32_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG32_DS32_Enum;

/* =============================================  GPIO PINCFG32 OUTCFG32 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG32_OUTCFG32                                                    */
  GPIO_PINCFG32_OUTCFG32_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG32_OUTCFG32_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG32_OUTCFG32_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG32_OUTCFG32_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG32_OUTCFG32_Enum;

/* =============================================  GPIO PINCFG32 IRPTEN32 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG32_IRPTEN32                                                    */
  GPIO_PINCFG32_IRPTEN32_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG32_IRPTEN32_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG32_IRPTEN32_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG32_IRPTEN32_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG32_IRPTEN32_Enum;

/* =============================================  GPIO PINCFG32 FNCSEL32 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG32_FNCSEL32                                                    */
  GPIO_PINCFG32_FNCSEL32_M3SDAWIR3     = 0,     /*!< M3SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
                                                     Master Data I/O (SPI 3 wire mode) (IOM 3)                                 */
  GPIO_PINCFG32_FNCSEL32_M3MOSI        = 1,     /*!< M3MOSI : Serial SPI Master MOSI output (IOM 3)                            */
  GPIO_PINCFG32_FNCSEL32_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG32_FNCSEL32_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG32_FNCSEL32_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
  GPIO_PINCFG32_FNCSEL32_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG32_FNCSEL32_CT32          = 6,     /*!< CT32 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG32_FNCSEL32_NCE32         = 7,     /*!< NCE32 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG32_FNCSEL32_OBSBUS0       = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
  GPIO_PINCFG32_FNCSEL32_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG32_FNCSEL32_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG32_FNCSEL32_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG32_FNCSEL32_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG32_FNCSEL32_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG32_FNCSEL32_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG32_FNCSEL32_LPG_ENABLE    = 15,    /*!< LPG_ENABLE : Internal function (SCAN)                                     */
} GPIO_PINCFG32_FNCSEL32_Enum;

/* =======================================================  PINCFG33  ======================================================== */
/* ============================================  GPIO PINCFG33 NCEPOL33 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG33_NCEPOL33                                                    */
  GPIO_PINCFG33_NCEPOL33_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG33_NCEPOL33_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG33_NCEPOL33_Enum;

/* ============================================  GPIO PINCFG33 NCESRC33 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG33_NCESRC33                                                    */
  GPIO_PINCFG33_NCESRC33_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG33_NCESRC33_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG33_NCESRC33_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG33_NCESRC33_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG33_NCESRC33_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG33_NCESRC33_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG33_NCESRC33_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG33_NCESRC33_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG33_NCESRC33_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG33_NCESRC33_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG33_NCESRC33_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG33_NCESRC33_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG33_NCESRC33_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG33_NCESRC33_Enum;

/* ===========================================  GPIO PINCFG33 PULLCFG33 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG33_PULLCFG33                                                   */
  GPIO_PINCFG33_PULLCFG33_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG33_PULLCFG33_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG33_PULLCFG33_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG33_PULLCFG33_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG33_PULLCFG33_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG33_PULLCFG33_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG33_PULLCFG33_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG33_PULLCFG33_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG33_PULLCFG33_Enum;

/* ==============================================  GPIO PINCFG33 DS33 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG33_DS33                                                        */
  GPIO_PINCFG33_DS33_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG33_DS33_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG33_DS33_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG33_DS33_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG33_DS33_Enum;

/* =============================================  GPIO PINCFG33 OUTCFG33 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG33_OUTCFG33                                                    */
  GPIO_PINCFG33_OUTCFG33_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG33_OUTCFG33_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG33_OUTCFG33_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG33_OUTCFG33_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG33_OUTCFG33_Enum;

/* =============================================  GPIO PINCFG33 IRPTEN33 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG33_IRPTEN33                                                    */
  GPIO_PINCFG33_IRPTEN33_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG33_IRPTEN33_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG33_IRPTEN33_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG33_IRPTEN33_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG33_IRPTEN33_Enum;

/* =============================================  GPIO PINCFG33 FNCSEL33 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG33_FNCSEL33                                                    */
  GPIO_PINCFG33_FNCSEL33_M3MISO        = 0,     /*!< M3MISO : Serial SPI MASTER MISO input (IOM 3)                             */
  GPIO_PINCFG33_FNCSEL33_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
  GPIO_PINCFG33_FNCSEL33_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG33_FNCSEL33_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG33_FNCSEL33_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
  GPIO_PINCFG33_FNCSEL33_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG33_FNCSEL33_CT33          = 6,     /*!< CT33 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG33_FNCSEL33_NCE33         = 7,     /*!< NCE33 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG33_FNCSEL33_OBSBUS1       = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
  GPIO_PINCFG33_FNCSEL33_DISP_TE       = 9,     /*!< DISP_TE : Display TE input                                                */
  GPIO_PINCFG33_FNCSEL33_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG33_FNCSEL33_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG33_FNCSEL33_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG33_FNCSEL33_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG33_FNCSEL33_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG33_FNCSEL33_LPG_LOAD      = 15,    /*!< LPG_LOAD : Internal function (SCAN)                                       */
} GPIO_PINCFG33_FNCSEL33_Enum;

/* =======================================================  PINCFG34  ======================================================== */
/* ============================================  GPIO PINCFG34 NCEPOL34 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG34_NCEPOL34                                                    */
  GPIO_PINCFG34_NCEPOL34_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG34_NCEPOL34_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG34_NCEPOL34_Enum;

/* ============================================  GPIO PINCFG34 NCESRC34 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG34_NCESRC34                                                    */
  GPIO_PINCFG34_NCESRC34_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG34_NCESRC34_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG34_NCESRC34_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG34_NCESRC34_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG34_NCESRC34_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG34_NCESRC34_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG34_NCESRC34_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG34_NCESRC34_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG34_NCESRC34_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG34_NCESRC34_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG34_NCESRC34_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG34_NCESRC34_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG34_NCESRC34_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG34_NCESRC34_Enum;

/* ===========================================  GPIO PINCFG34 PULLCFG34 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG34_PULLCFG34                                                   */
  GPIO_PINCFG34_PULLCFG34_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG34_PULLCFG34_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG34_PULLCFG34_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG34_PULLCFG34_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG34_PULLCFG34_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG34_PULLCFG34_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG34_PULLCFG34_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG34_PULLCFG34_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG34_PULLCFG34_Enum;

/* ==============================================  GPIO PINCFG34 DS34 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG34_DS34                                                        */
  GPIO_PINCFG34_DS34_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG34_DS34_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG34_DS34_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG34_DS34_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG34_DS34_Enum;

/* =============================================  GPIO PINCFG34 OUTCFG34 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG34_OUTCFG34                                                    */
  GPIO_PINCFG34_OUTCFG34_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG34_OUTCFG34_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG34_OUTCFG34_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG34_OUTCFG34_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG34_OUTCFG34_Enum;

/* =============================================  GPIO PINCFG34 IRPTEN34 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG34_IRPTEN34                                                    */
  GPIO_PINCFG34_IRPTEN34_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG34_IRPTEN34_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG34_IRPTEN34_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG34_IRPTEN34_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG34_IRPTEN34_Enum;

/* =============================================  GPIO PINCFG34 FNCSEL34 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG34_FNCSEL34                                                    */
  GPIO_PINCFG34_FNCSEL34_M4SCL         = 0,     /*!< M4SCL : Serial I2C Master Clock output (IOM 4)                            */
  GPIO_PINCFG34_FNCSEL34_M4SCK         = 1,     /*!< M4SCK : Serial SPI Master Clock output (IOM 4)                            */
  GPIO_PINCFG34_FNCSEL34_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG34_FNCSEL34_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG34_FNCSEL34_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
  GPIO_PINCFG34_FNCSEL34_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG34_FNCSEL34_CT34          = 6,     /*!< CT34 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG34_FNCSEL34_NCE34         = 7,     /*!< NCE34 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG34_FNCSEL34_OBSBUS2       = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
  GPIO_PINCFG34_FNCSEL34_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG34_FNCSEL34_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG34_FNCSEL34_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG34_FNCSEL34_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG34_FNCSEL34_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG34_FNCSEL34_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG34_FNCSEL34_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG34_FNCSEL34_Enum;

/* =======================================================  PINCFG35  ======================================================== */
/* ============================================  GPIO PINCFG35 NCEPOL35 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG35_NCEPOL35                                                    */
  GPIO_PINCFG35_NCEPOL35_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG35_NCEPOL35_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG35_NCEPOL35_Enum;

/* ============================================  GPIO PINCFG35 NCESRC35 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG35_NCESRC35                                                    */
  GPIO_PINCFG35_NCESRC35_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG35_NCESRC35_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG35_NCESRC35_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG35_NCESRC35_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG35_NCESRC35_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG35_NCESRC35_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG35_NCESRC35_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG35_NCESRC35_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG35_NCESRC35_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG35_NCESRC35_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG35_NCESRC35_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG35_NCESRC35_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG35_NCESRC35_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG35_NCESRC35_Enum;

/* ===========================================  GPIO PINCFG35 PULLCFG35 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG35_PULLCFG35                                                   */
  GPIO_PINCFG35_PULLCFG35_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG35_PULLCFG35_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG35_PULLCFG35_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG35_PULLCFG35_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG35_PULLCFG35_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG35_PULLCFG35_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG35_PULLCFG35_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG35_PULLCFG35_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG35_PULLCFG35_Enum;

/* ==============================================  GPIO PINCFG35 DS35 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG35_DS35                                                        */
  GPIO_PINCFG35_DS35_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG35_DS35_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG35_DS35_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG35_DS35_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG35_DS35_Enum;

/* =============================================  GPIO PINCFG35 OUTCFG35 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG35_OUTCFG35                                                    */
  GPIO_PINCFG35_OUTCFG35_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG35_OUTCFG35_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG35_OUTCFG35_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG35_OUTCFG35_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG35_OUTCFG35_Enum;

/* =============================================  GPIO PINCFG35 IRPTEN35 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG35_IRPTEN35                                                    */
  GPIO_PINCFG35_IRPTEN35_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG35_IRPTEN35_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG35_IRPTEN35_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG35_IRPTEN35_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG35_IRPTEN35_Enum;

/* =============================================  GPIO PINCFG35 FNCSEL35 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG35_FNCSEL35                                                    */
  GPIO_PINCFG35_FNCSEL35_M4SDAWIR3     = 0,     /*!< M4SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
                                                     Master Data I/O (SPI 3 wire mode) (IOM 4)                                 */
  GPIO_PINCFG35_FNCSEL35_M4MOSI        = 1,     /*!< M4MOSI : Serial SPI Master MOSI output (IOM 4)                            */
  GPIO_PINCFG35_FNCSEL35_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG35_FNCSEL35_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG35_FNCSEL35_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
  GPIO_PINCFG35_FNCSEL35_UART3TX       = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
  GPIO_PINCFG35_FNCSEL35_CT35          = 6,     /*!< CT35 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG35_FNCSEL35_NCE35         = 7,     /*!< NCE35 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG35_FNCSEL35_OBSBUS3       = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
  GPIO_PINCFG35_FNCSEL35_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG35_FNCSEL35_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG35_FNCSEL35_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG35_FNCSEL35_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG35_FNCSEL35_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG35_FNCSEL35_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG35_FNCSEL35_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG35_FNCSEL35_Enum;

/* =======================================================  PINCFG36  ======================================================== */
/* ============================================  GPIO PINCFG36 NCEPOL36 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG36_NCEPOL36                                                    */
  GPIO_PINCFG36_NCEPOL36_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG36_NCEPOL36_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG36_NCEPOL36_Enum;

/* ============================================  GPIO PINCFG36 NCESRC36 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG36_NCESRC36                                                    */
  GPIO_PINCFG36_NCESRC36_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG36_NCESRC36_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG36_NCESRC36_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG36_NCESRC36_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG36_NCESRC36_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG36_NCESRC36_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG36_NCESRC36_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG36_NCESRC36_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG36_NCESRC36_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG36_NCESRC36_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG36_NCESRC36_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG36_NCESRC36_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG36_NCESRC36_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG36_NCESRC36_Enum;

/* ===========================================  GPIO PINCFG36 PULLCFG36 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG36_PULLCFG36                                                   */
  GPIO_PINCFG36_PULLCFG36_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG36_PULLCFG36_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG36_PULLCFG36_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG36_PULLCFG36_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG36_PULLCFG36_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG36_PULLCFG36_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG36_PULLCFG36_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG36_PULLCFG36_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG36_PULLCFG36_Enum;

/* ==============================================  GPIO PINCFG36 DS36 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG36_DS36                                                        */
  GPIO_PINCFG36_DS36_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG36_DS36_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG36_DS36_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG36_DS36_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG36_DS36_Enum;

/* =============================================  GPIO PINCFG36 OUTCFG36 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG36_OUTCFG36                                                    */
  GPIO_PINCFG36_OUTCFG36_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG36_OUTCFG36_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG36_OUTCFG36_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG36_OUTCFG36_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG36_OUTCFG36_Enum;

/* =============================================  GPIO PINCFG36 IRPTEN36 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG36_IRPTEN36                                                    */
  GPIO_PINCFG36_IRPTEN36_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG36_IRPTEN36_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG36_IRPTEN36_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG36_IRPTEN36_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG36_IRPTEN36_Enum;

/* =============================================  GPIO PINCFG36 FNCSEL36 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG36_FNCSEL36                                                    */
  GPIO_PINCFG36_FNCSEL36_M4MISO        = 0,     /*!< M4MISO : Serial SPI MASTER MISO input (IOM 4)                             */
  GPIO_PINCFG36_FNCSEL36_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
  GPIO_PINCFG36_FNCSEL36_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG36_FNCSEL36_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG36_FNCSEL36_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
  GPIO_PINCFG36_FNCSEL36_UART1RX       = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
  GPIO_PINCFG36_FNCSEL36_CT36          = 6,     /*!< CT36 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG36_FNCSEL36_NCE36         = 7,     /*!< NCE36 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG36_FNCSEL36_OBSBUS4       = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
  GPIO_PINCFG36_FNCSEL36_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG36_FNCSEL36_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG36_FNCSEL36_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG36_FNCSEL36_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG36_FNCSEL36_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG36_FNCSEL36_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG36_FNCSEL36_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG36_FNCSEL36_Enum;

/* =======================================================  PINCFG37  ======================================================== */
/* ============================================  GPIO PINCFG37 NCEPOL37 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG37_NCEPOL37                                                    */
  GPIO_PINCFG37_NCEPOL37_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG37_NCEPOL37_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG37_NCEPOL37_Enum;

/* ============================================  GPIO PINCFG37 NCESRC37 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG37_NCESRC37                                                    */
  GPIO_PINCFG37_NCESRC37_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG37_NCESRC37_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG37_NCESRC37_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG37_NCESRC37_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG37_NCESRC37_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG37_NCESRC37_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG37_NCESRC37_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG37_NCESRC37_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG37_NCESRC37_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG37_NCESRC37_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG37_NCESRC37_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG37_NCESRC37_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG37_NCESRC37_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG37_NCESRC37_Enum;

/* ===========================================  GPIO PINCFG37 PULLCFG37 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG37_PULLCFG37                                                   */
  GPIO_PINCFG37_PULLCFG37_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG37_PULLCFG37_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG37_PULLCFG37_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG37_PULLCFG37_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG37_PULLCFG37_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG37_PULLCFG37_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG37_PULLCFG37_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG37_PULLCFG37_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG37_PULLCFG37_Enum;

/* ==============================================  GPIO PINCFG37 DS37 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG37_DS37                                                        */
  GPIO_PINCFG37_DS37_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG37_DS37_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG37_DS37_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG37_DS37_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG37_DS37_Enum;

/* =============================================  GPIO PINCFG37 OUTCFG37 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG37_OUTCFG37                                                    */
  GPIO_PINCFG37_OUTCFG37_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG37_OUTCFG37_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG37_OUTCFG37_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG37_OUTCFG37_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG37_OUTCFG37_Enum;

/* =============================================  GPIO PINCFG37 IRPTEN37 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG37_IRPTEN37                                                    */
  GPIO_PINCFG37_IRPTEN37_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG37_IRPTEN37_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG37_IRPTEN37_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG37_IRPTEN37_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG37_IRPTEN37_Enum;

/* =============================================  GPIO PINCFG37 FNCSEL37 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG37_FNCSEL37                                                    */
  GPIO_PINCFG37_FNCSEL37_MSPI1_0       = 0,     /*!< MSPI1_0 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG37_FNCSEL37_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
  GPIO_PINCFG37_FNCSEL37_32KHzXT       = 2,     /*!< 32KHzXT : 32kHZ from analog                                               */
  GPIO_PINCFG37_FNCSEL37_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG37_FNCSEL37_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
  GPIO_PINCFG37_FNCSEL37_DISP_D15      = 5,     /*!< DISP_D15 : Display Data 15                                                */
  GPIO_PINCFG37_FNCSEL37_CT37          = 6,     /*!< CT37 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG37_FNCSEL37_NCE37         = 7,     /*!< NCE37 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG37_FNCSEL37_OBSBUS5       = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
  GPIO_PINCFG37_FNCSEL37_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG37_FNCSEL37_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG37_FNCSEL37_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG37_FNCSEL37_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG37_FNCSEL37_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG37_FNCSEL37_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG37_FNCSEL37_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG37_FNCSEL37_Enum;

/* =======================================================  PINCFG38  ======================================================== */
/* ============================================  GPIO PINCFG38 NCEPOL38 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG38_NCEPOL38                                                    */
  GPIO_PINCFG38_NCEPOL38_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG38_NCEPOL38_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG38_NCEPOL38_Enum;

/* ============================================  GPIO PINCFG38 NCESRC38 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG38_NCESRC38                                                    */
  GPIO_PINCFG38_NCESRC38_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG38_NCESRC38_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG38_NCESRC38_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG38_NCESRC38_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG38_NCESRC38_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG38_NCESRC38_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG38_NCESRC38_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG38_NCESRC38_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG38_NCESRC38_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG38_NCESRC38_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG38_NCESRC38_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG38_NCESRC38_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG38_NCESRC38_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG38_NCESRC38_Enum;

/* ===========================================  GPIO PINCFG38 PULLCFG38 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG38_PULLCFG38                                                   */
  GPIO_PINCFG38_PULLCFG38_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG38_PULLCFG38_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG38_PULLCFG38_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG38_PULLCFG38_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG38_PULLCFG38_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG38_PULLCFG38_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG38_PULLCFG38_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG38_PULLCFG38_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG38_PULLCFG38_Enum;

/* ==============================================  GPIO PINCFG38 DS38 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG38_DS38                                                        */
  GPIO_PINCFG38_DS38_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG38_DS38_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG38_DS38_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG38_DS38_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG38_DS38_Enum;

/* =============================================  GPIO PINCFG38 OUTCFG38 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG38_OUTCFG38                                                    */
  GPIO_PINCFG38_OUTCFG38_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG38_OUTCFG38_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG38_OUTCFG38_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG38_OUTCFG38_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG38_OUTCFG38_Enum;

/* =============================================  GPIO PINCFG38 IRPTEN38 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG38_IRPTEN38                                                    */
  GPIO_PINCFG38_IRPTEN38_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG38_IRPTEN38_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG38_IRPTEN38_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG38_IRPTEN38_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG38_IRPTEN38_Enum;

/* =============================================  GPIO PINCFG38 FNCSEL38 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG38_FNCSEL38                                                    */
  GPIO_PINCFG38_FNCSEL38_MSPI1_1       = 0,     /*!< MSPI1_1 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG38_FNCSEL38_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
  GPIO_PINCFG38_FNCSEL38_SWTRACECLK    = 2,     /*!< SWTRACECLK : Serial Wire Debug Trace Clock                                */
  GPIO_PINCFG38_FNCSEL38_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG38_FNCSEL38_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
  GPIO_PINCFG38_FNCSEL38_DISP_D16      = 5,     /*!< DISP_D16 : Display Data 16                                                */
  GPIO_PINCFG38_FNCSEL38_CT38          = 6,     /*!< CT38 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG38_FNCSEL38_NCE38         = 7,     /*!< NCE38 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG38_FNCSEL38_OBSBUS6       = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
  GPIO_PINCFG38_FNCSEL38_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG38_FNCSEL38_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG38_FNCSEL38_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG38_FNCSEL38_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG38_FNCSEL38_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG38_FNCSEL38_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG38_FNCSEL38_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG38_FNCSEL38_Enum;

/* =======================================================  PINCFG39  ======================================================== */
/* ============================================  GPIO PINCFG39 NCEPOL39 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG39_NCEPOL39                                                    */
  GPIO_PINCFG39_NCEPOL39_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG39_NCEPOL39_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG39_NCEPOL39_Enum;

/* ============================================  GPIO PINCFG39 NCESRC39 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG39_NCESRC39                                                    */
  GPIO_PINCFG39_NCESRC39_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG39_NCESRC39_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG39_NCESRC39_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG39_NCESRC39_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG39_NCESRC39_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG39_NCESRC39_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG39_NCESRC39_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG39_NCESRC39_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG39_NCESRC39_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG39_NCESRC39_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG39_NCESRC39_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG39_NCESRC39_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG39_NCESRC39_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG39_NCESRC39_Enum;

/* ===========================================  GPIO PINCFG39 PULLCFG39 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG39_PULLCFG39                                                   */
  GPIO_PINCFG39_PULLCFG39_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG39_PULLCFG39_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG39_PULLCFG39_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG39_PULLCFG39_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG39_PULLCFG39_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG39_PULLCFG39_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG39_PULLCFG39_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG39_PULLCFG39_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG39_PULLCFG39_Enum;

/* ==============================================  GPIO PINCFG39 DS39 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG39_DS39                                                        */
  GPIO_PINCFG39_DS39_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG39_DS39_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG39_DS39_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG39_DS39_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG39_DS39_Enum;

/* =============================================  GPIO PINCFG39 OUTCFG39 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG39_OUTCFG39                                                    */
  GPIO_PINCFG39_OUTCFG39_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG39_OUTCFG39_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG39_OUTCFG39_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG39_OUTCFG39_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG39_OUTCFG39_Enum;

/* =============================================  GPIO PINCFG39 IRPTEN39 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG39_IRPTEN39                                                    */
  GPIO_PINCFG39_IRPTEN39_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG39_IRPTEN39_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG39_IRPTEN39_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG39_IRPTEN39_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG39_IRPTEN39_Enum;

/* =============================================  GPIO PINCFG39 FNCSEL39 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG39_FNCSEL39                                                    */
  GPIO_PINCFG39_FNCSEL39_MSPI1_2       = 0,     /*!< MSPI1_2 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG39_FNCSEL39_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
  GPIO_PINCFG39_FNCSEL39_SWTRACE0      = 2,     /*!< SWTRACE0 : Serial Wire Debug Trace Output 0                               */
  GPIO_PINCFG39_FNCSEL39_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG39_FNCSEL39_UART2RTS      = 4,     /*!< UART2RTS : UART Request to Send (RTS) (UART 2)                            */
  GPIO_PINCFG39_FNCSEL39_DISP_D17      = 5,     /*!< DISP_D17 : Display Data 17                                                */
  GPIO_PINCFG39_FNCSEL39_CT39          = 6,     /*!< CT39 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG39_FNCSEL39_NCE39         = 7,     /*!< NCE39 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG39_FNCSEL39_OBSBUS7       = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
  GPIO_PINCFG39_FNCSEL39_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG39_FNCSEL39_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG39_FNCSEL39_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG39_FNCSEL39_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG39_FNCSEL39_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG39_FNCSEL39_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG39_FNCSEL39_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG39_FNCSEL39_Enum;

/* =======================================================  PINCFG40  ======================================================== */
/* ============================================  GPIO PINCFG40 NCEPOL40 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG40_NCEPOL40                                                    */
  GPIO_PINCFG40_NCEPOL40_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG40_NCEPOL40_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG40_NCEPOL40_Enum;

/* ============================================  GPIO PINCFG40 NCESRC40 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG40_NCESRC40                                                    */
  GPIO_PINCFG40_NCESRC40_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG40_NCESRC40_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG40_NCESRC40_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG40_NCESRC40_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG40_NCESRC40_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG40_NCESRC40_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG40_NCESRC40_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG40_NCESRC40_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG40_NCESRC40_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG40_NCESRC40_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG40_NCESRC40_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG40_NCESRC40_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG40_NCESRC40_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG40_NCESRC40_Enum;

/* ===========================================  GPIO PINCFG40 PULLCFG40 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG40_PULLCFG40                                                   */
  GPIO_PINCFG40_PULLCFG40_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG40_PULLCFG40_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG40_PULLCFG40_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG40_PULLCFG40_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG40_PULLCFG40_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG40_PULLCFG40_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG40_PULLCFG40_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG40_PULLCFG40_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG40_PULLCFG40_Enum;

/* ==============================================  GPIO PINCFG40 DS40 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG40_DS40                                                        */
  GPIO_PINCFG40_DS40_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG40_DS40_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG40_DS40_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG40_DS40_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG40_DS40_Enum;

/* =============================================  GPIO PINCFG40 OUTCFG40 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG40_OUTCFG40                                                    */
  GPIO_PINCFG40_OUTCFG40_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG40_OUTCFG40_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG40_OUTCFG40_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG40_OUTCFG40_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG40_OUTCFG40_Enum;

/* =============================================  GPIO PINCFG40 IRPTEN40 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG40_IRPTEN40                                                    */
  GPIO_PINCFG40_IRPTEN40_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG40_IRPTEN40_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG40_IRPTEN40_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG40_IRPTEN40_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG40_IRPTEN40_Enum;

/* =============================================  GPIO PINCFG40 FNCSEL40 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG40_FNCSEL40                                                    */
  GPIO_PINCFG40_FNCSEL40_MSPI1_3       = 0,     /*!< MSPI1_3 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG40_FNCSEL40_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
  GPIO_PINCFG40_FNCSEL40_SWTRACE1      = 2,     /*!< SWTRACE1 : Serial Wire Debug Trace Output 1                               */
  GPIO_PINCFG40_FNCSEL40_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG40_FNCSEL40_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
  GPIO_PINCFG40_FNCSEL40_DISP_D18      = 5,     /*!< DISP_D18 : Display Data 18                                                */
  GPIO_PINCFG40_FNCSEL40_CT40          = 6,     /*!< CT40 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG40_FNCSEL40_NCE40         = 7,     /*!< NCE40 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG40_FNCSEL40_OBSBUS8       = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
  GPIO_PINCFG40_FNCSEL40_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG40_FNCSEL40_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG40_FNCSEL40_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG40_FNCSEL40_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG40_FNCSEL40_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG40_FNCSEL40_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG40_FNCSEL40_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG40_FNCSEL40_Enum;

/* =======================================================  PINCFG41  ======================================================== */
/* ============================================  GPIO PINCFG41 NCEPOL41 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG41_NCEPOL41                                                    */
  GPIO_PINCFG41_NCEPOL41_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG41_NCEPOL41_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG41_NCEPOL41_Enum;

/* ============================================  GPIO PINCFG41 NCESRC41 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG41_NCESRC41                                                    */
  GPIO_PINCFG41_NCESRC41_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG41_NCESRC41_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG41_NCESRC41_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG41_NCESRC41_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG41_NCESRC41_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG41_NCESRC41_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG41_NCESRC41_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG41_NCESRC41_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG41_NCESRC41_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG41_NCESRC41_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG41_NCESRC41_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG41_NCESRC41_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG41_NCESRC41_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG41_NCESRC41_Enum;

/* ===========================================  GPIO PINCFG41 PULLCFG41 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG41_PULLCFG41                                                   */
  GPIO_PINCFG41_PULLCFG41_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG41_PULLCFG41_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG41_PULLCFG41_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG41_PULLCFG41_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG41_PULLCFG41_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG41_PULLCFG41_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG41_PULLCFG41_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG41_PULLCFG41_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG41_PULLCFG41_Enum;

/* ==============================================  GPIO PINCFG41 DS41 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG41_DS41                                                        */
  GPIO_PINCFG41_DS41_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG41_DS41_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG41_DS41_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG41_DS41_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG41_DS41_Enum;

/* =============================================  GPIO PINCFG41 OUTCFG41 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG41_OUTCFG41                                                    */
  GPIO_PINCFG41_OUTCFG41_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG41_OUTCFG41_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG41_OUTCFG41_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG41_OUTCFG41_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG41_OUTCFG41_Enum;

/* =============================================  GPIO PINCFG41 IRPTEN41 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG41_IRPTEN41                                                    */
  GPIO_PINCFG41_IRPTEN41_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG41_IRPTEN41_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG41_IRPTEN41_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG41_IRPTEN41_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG41_IRPTEN41_Enum;

/* =============================================  GPIO PINCFG41 FNCSEL41 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG41_FNCSEL41                                                    */
  GPIO_PINCFG41_FNCSEL41_MSPI1_4       = 0,     /*!< MSPI1_4 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG41_FNCSEL41_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
  GPIO_PINCFG41_FNCSEL41_SWTRACE2      = 2,     /*!< SWTRACE2 : Serial Wire Debug Trace Output 2                               */
  GPIO_PINCFG41_FNCSEL41_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG41_FNCSEL41_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
  GPIO_PINCFG41_FNCSEL41_DISP_D19      = 5,     /*!< DISP_D19 : Display Data 19                                                */
  GPIO_PINCFG41_FNCSEL41_CT41          = 6,     /*!< CT41 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG41_FNCSEL41_NCE41         = 7,     /*!< NCE41 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG41_FNCSEL41_OBSBUS9       = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
  GPIO_PINCFG41_FNCSEL41_SWO           = 9,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG41_FNCSEL41_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG41_FNCSEL41_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG41_FNCSEL41_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG41_FNCSEL41_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG41_FNCSEL41_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG41_FNCSEL41_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG41_FNCSEL41_Enum;

/* =======================================================  PINCFG42  ======================================================== */
/* ============================================  GPIO PINCFG42 NCEPOL42 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG42_NCEPOL42                                                    */
  GPIO_PINCFG42_NCEPOL42_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG42_NCEPOL42_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG42_NCEPOL42_Enum;

/* ============================================  GPIO PINCFG42 NCESRC42 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG42_NCESRC42                                                    */
  GPIO_PINCFG42_NCESRC42_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG42_NCESRC42_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG42_NCESRC42_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG42_NCESRC42_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG42_NCESRC42_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG42_NCESRC42_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG42_NCESRC42_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG42_NCESRC42_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG42_NCESRC42_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG42_NCESRC42_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG42_NCESRC42_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG42_NCESRC42_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG42_NCESRC42_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG42_NCESRC42_Enum;

/* ===========================================  GPIO PINCFG42 PULLCFG42 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG42_PULLCFG42                                                   */
  GPIO_PINCFG42_PULLCFG42_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG42_PULLCFG42_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG42_PULLCFG42_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG42_PULLCFG42_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG42_PULLCFG42_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG42_PULLCFG42_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG42_PULLCFG42_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG42_PULLCFG42_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG42_PULLCFG42_Enum;

/* ==============================================  GPIO PINCFG42 DS42 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG42_DS42                                                        */
  GPIO_PINCFG42_DS42_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG42_DS42_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG42_DS42_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG42_DS42_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG42_DS42_Enum;

/* =============================================  GPIO PINCFG42 OUTCFG42 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG42_OUTCFG42                                                    */
  GPIO_PINCFG42_OUTCFG42_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG42_OUTCFG42_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG42_OUTCFG42_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG42_OUTCFG42_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG42_OUTCFG42_Enum;

/* =============================================  GPIO PINCFG42 IRPTEN42 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG42_IRPTEN42                                                    */
  GPIO_PINCFG42_IRPTEN42_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG42_IRPTEN42_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG42_IRPTEN42_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG42_IRPTEN42_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG42_IRPTEN42_Enum;

/* =============================================  GPIO PINCFG42 FNCSEL42 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG42_FNCSEL42                                                    */
  GPIO_PINCFG42_FNCSEL42_MSPI1_5       = 0,     /*!< MSPI1_5 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG42_FNCSEL42_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
  GPIO_PINCFG42_FNCSEL42_SWTRACE3      = 2,     /*!< SWTRACE3 : Serial Wire Debug Trace Output 3                               */
  GPIO_PINCFG42_FNCSEL42_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG42_FNCSEL42_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
  GPIO_PINCFG42_FNCSEL42_DISP_D20      = 5,     /*!< DISP_D20 : Display Data 20                                                */
  GPIO_PINCFG42_FNCSEL42_CT42          = 6,     /*!< CT42 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG42_FNCSEL42_NCE42         = 7,     /*!< NCE42 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG42_FNCSEL42_OBSBUS10      = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
  GPIO_PINCFG42_FNCSEL42_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG42_FNCSEL42_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG42_FNCSEL42_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG42_FNCSEL42_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG42_FNCSEL42_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG42_FNCSEL42_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG42_FNCSEL42_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG42_FNCSEL42_Enum;

/* =======================================================  PINCFG43  ======================================================== */
/* ============================================  GPIO PINCFG43 NCEPOL43 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG43_NCEPOL43                                                    */
  GPIO_PINCFG43_NCEPOL43_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG43_NCEPOL43_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG43_NCEPOL43_Enum;

/* ============================================  GPIO PINCFG43 NCESRC43 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG43_NCESRC43                                                    */
  GPIO_PINCFG43_NCESRC43_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG43_NCESRC43_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG43_NCESRC43_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG43_NCESRC43_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG43_NCESRC43_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG43_NCESRC43_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG43_NCESRC43_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG43_NCESRC43_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG43_NCESRC43_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG43_NCESRC43_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG43_NCESRC43_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG43_NCESRC43_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG43_NCESRC43_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG43_NCESRC43_Enum;

/* ===========================================  GPIO PINCFG43 PULLCFG43 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG43_PULLCFG43                                                   */
  GPIO_PINCFG43_PULLCFG43_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG43_PULLCFG43_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG43_PULLCFG43_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG43_PULLCFG43_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG43_PULLCFG43_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG43_PULLCFG43_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG43_PULLCFG43_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG43_PULLCFG43_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG43_PULLCFG43_Enum;

/* ==============================================  GPIO PINCFG43 DS43 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG43_DS43                                                        */
  GPIO_PINCFG43_DS43_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG43_DS43_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG43_DS43_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG43_DS43_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG43_DS43_Enum;

/* =============================================  GPIO PINCFG43 OUTCFG43 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG43_OUTCFG43                                                    */
  GPIO_PINCFG43_OUTCFG43_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG43_OUTCFG43_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG43_OUTCFG43_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG43_OUTCFG43_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG43_OUTCFG43_Enum;

/* =============================================  GPIO PINCFG43 IRPTEN43 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG43_IRPTEN43                                                    */
  GPIO_PINCFG43_IRPTEN43_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG43_IRPTEN43_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG43_IRPTEN43_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG43_IRPTEN43_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG43_IRPTEN43_Enum;

/* =============================================  GPIO PINCFG43 FNCSEL43 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG43_FNCSEL43                                                    */
  GPIO_PINCFG43_FNCSEL43_MSPI1_6       = 0,     /*!< MSPI1_6 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG43_FNCSEL43_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
  GPIO_PINCFG43_FNCSEL43_SWTRACECTL    = 2,     /*!< SWTRACECTL : Serial Wire Debug Trace Control                              */
  GPIO_PINCFG43_FNCSEL43_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG43_FNCSEL43_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
  GPIO_PINCFG43_FNCSEL43_DISP_D21      = 5,     /*!< DISP_D21 : Display Data 21                                                */
  GPIO_PINCFG43_FNCSEL43_CT43          = 6,     /*!< CT43 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG43_FNCSEL43_NCE43         = 7,     /*!< NCE43 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG43_FNCSEL43_OBSBUS11      = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
  GPIO_PINCFG43_FNCSEL43_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG43_FNCSEL43_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG43_FNCSEL43_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG43_FNCSEL43_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG43_FNCSEL43_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG43_FNCSEL43_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG43_FNCSEL43_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG43_FNCSEL43_Enum;

/* =======================================================  PINCFG44  ======================================================== */
/* ============================================  GPIO PINCFG44 NCEPOL44 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG44_NCEPOL44                                                    */
  GPIO_PINCFG44_NCEPOL44_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG44_NCEPOL44_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG44_NCEPOL44_Enum;

/* ============================================  GPIO PINCFG44 NCESRC44 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG44_NCESRC44                                                    */
  GPIO_PINCFG44_NCESRC44_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG44_NCESRC44_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG44_NCESRC44_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG44_NCESRC44_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG44_NCESRC44_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG44_NCESRC44_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG44_NCESRC44_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG44_NCESRC44_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG44_NCESRC44_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG44_NCESRC44_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG44_NCESRC44_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG44_NCESRC44_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG44_NCESRC44_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG44_NCESRC44_Enum;

/* ===========================================  GPIO PINCFG44 PULLCFG44 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG44_PULLCFG44                                                   */
  GPIO_PINCFG44_PULLCFG44_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG44_PULLCFG44_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG44_PULLCFG44_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG44_PULLCFG44_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG44_PULLCFG44_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG44_PULLCFG44_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG44_PULLCFG44_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG44_PULLCFG44_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG44_PULLCFG44_Enum;

/* ==============================================  GPIO PINCFG44 DS44 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG44_DS44                                                        */
  GPIO_PINCFG44_DS44_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG44_DS44_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG44_DS44_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG44_DS44_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG44_DS44_Enum;

/* =============================================  GPIO PINCFG44 OUTCFG44 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG44_OUTCFG44                                                    */
  GPIO_PINCFG44_OUTCFG44_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG44_OUTCFG44_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG44_OUTCFG44_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG44_OUTCFG44_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG44_OUTCFG44_Enum;

/* =============================================  GPIO PINCFG44 IRPTEN44 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG44_IRPTEN44                                                    */
  GPIO_PINCFG44_IRPTEN44_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG44_IRPTEN44_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG44_IRPTEN44_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG44_IRPTEN44_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG44_IRPTEN44_Enum;

/* =============================================  GPIO PINCFG44 FNCSEL44 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG44_FNCSEL44                                                    */
  GPIO_PINCFG44_FNCSEL44_MSPI1_7       = 0,     /*!< MSPI1_7 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG44_FNCSEL44_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
  GPIO_PINCFG44_FNCSEL44_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG44_FNCSEL44_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG44_FNCSEL44_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
  GPIO_PINCFG44_FNCSEL44_DISP_D22      = 5,     /*!< DISP_D22 : Display Data 22                                                */
  GPIO_PINCFG44_FNCSEL44_CT44          = 6,     /*!< CT44 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG44_FNCSEL44_NCE44         = 7,     /*!< NCE44 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG44_FNCSEL44_OBSBUS12      = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
  GPIO_PINCFG44_FNCSEL44_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG44_FNCSEL44_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG44_FNCSEL44_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG44_FNCSEL44_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG44_FNCSEL44_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG44_FNCSEL44_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG44_FNCSEL44_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG44_FNCSEL44_Enum;

/* =======================================================  PINCFG45  ======================================================== */
/* ============================================  GPIO PINCFG45 NCEPOL45 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG45_NCEPOL45                                                    */
  GPIO_PINCFG45_NCEPOL45_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG45_NCEPOL45_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG45_NCEPOL45_Enum;

/* ============================================  GPIO PINCFG45 NCESRC45 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG45_NCESRC45                                                    */
  GPIO_PINCFG45_NCESRC45_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG45_NCESRC45_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG45_NCESRC45_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG45_NCESRC45_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG45_NCESRC45_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG45_NCESRC45_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG45_NCESRC45_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG45_NCESRC45_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG45_NCESRC45_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG45_NCESRC45_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG45_NCESRC45_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG45_NCESRC45_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG45_NCESRC45_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG45_NCESRC45_Enum;

/* ===========================================  GPIO PINCFG45 PULLCFG45 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG45_PULLCFG45                                                   */
  GPIO_PINCFG45_PULLCFG45_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG45_PULLCFG45_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG45_PULLCFG45_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG45_PULLCFG45_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG45_PULLCFG45_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG45_PULLCFG45_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG45_PULLCFG45_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG45_PULLCFG45_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG45_PULLCFG45_Enum;

/* ==============================================  GPIO PINCFG45 DS45 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG45_DS45                                                        */
  GPIO_PINCFG45_DS45_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG45_DS45_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG45_DS45_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG45_DS45_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG45_DS45_Enum;

/* =============================================  GPIO PINCFG45 OUTCFG45 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG45_OUTCFG45                                                    */
  GPIO_PINCFG45_OUTCFG45_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG45_OUTCFG45_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG45_OUTCFG45_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG45_OUTCFG45_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG45_OUTCFG45_Enum;

/* =============================================  GPIO PINCFG45 IRPTEN45 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG45_IRPTEN45                                                    */
  GPIO_PINCFG45_IRPTEN45_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG45_IRPTEN45_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG45_IRPTEN45_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG45_IRPTEN45_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG45_IRPTEN45_Enum;

/* =============================================  GPIO PINCFG45 FNCSEL45 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG45_FNCSEL45                                                    */
  GPIO_PINCFG45_FNCSEL45_MSPI1_8       = 0,     /*!< MSPI1_8 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG45_FNCSEL45_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
  GPIO_PINCFG45_FNCSEL45_32KHzXT       = 2,     /*!< 32KHzXT : 32kHZ from analog                                               */
  GPIO_PINCFG45_FNCSEL45_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG45_FNCSEL45_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
  GPIO_PINCFG45_FNCSEL45_DISP_D23      = 5,     /*!< DISP_D23 : Display Data 23                                                */
  GPIO_PINCFG45_FNCSEL45_CT45          = 6,     /*!< CT45 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG45_FNCSEL45_NCE45         = 7,     /*!< NCE45 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG45_FNCSEL45_OBSBUS13      = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
  GPIO_PINCFG45_FNCSEL45_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG45_FNCSEL45_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG45_FNCSEL45_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG45_FNCSEL45_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG45_FNCSEL45_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG45_FNCSEL45_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG45_FNCSEL45_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG45_FNCSEL45_Enum;

/* =======================================================  PINCFG46  ======================================================== */
/* ============================================  GPIO PINCFG46 NCEPOL46 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG46_NCEPOL46                                                    */
  GPIO_PINCFG46_NCEPOL46_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG46_NCEPOL46_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG46_NCEPOL46_Enum;

/* ============================================  GPIO PINCFG46 NCESRC46 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG46_NCESRC46                                                    */
  GPIO_PINCFG46_NCESRC46_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG46_NCESRC46_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG46_NCESRC46_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG46_NCESRC46_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG46_NCESRC46_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG46_NCESRC46_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG46_NCESRC46_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG46_NCESRC46_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG46_NCESRC46_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG46_NCESRC46_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG46_NCESRC46_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG46_NCESRC46_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG46_NCESRC46_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG46_NCESRC46_Enum;

/* ===========================================  GPIO PINCFG46 PULLCFG46 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG46_PULLCFG46                                                   */
  GPIO_PINCFG46_PULLCFG46_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG46_PULLCFG46_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG46_PULLCFG46_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG46_PULLCFG46_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG46_PULLCFG46_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG46_PULLCFG46_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG46_PULLCFG46_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG46_PULLCFG46_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG46_PULLCFG46_Enum;

/* ==============================================  GPIO PINCFG46 DS46 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG46_DS46                                                        */
  GPIO_PINCFG46_DS46_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG46_DS46_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG46_DS46_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG46_DS46_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG46_DS46_Enum;

/* =============================================  GPIO PINCFG46 OUTCFG46 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG46_OUTCFG46                                                    */
  GPIO_PINCFG46_OUTCFG46_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG46_OUTCFG46_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG46_OUTCFG46_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG46_OUTCFG46_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG46_OUTCFG46_Enum;

/* =============================================  GPIO PINCFG46 IRPTEN46 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG46_IRPTEN46                                                    */
  GPIO_PINCFG46_IRPTEN46_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG46_IRPTEN46_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG46_IRPTEN46_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG46_IRPTEN46_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG46_IRPTEN46_Enum;

/* =============================================  GPIO PINCFG46 FNCSEL46 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG46_FNCSEL46                                                    */
  GPIO_PINCFG46_FNCSEL46_MSPI1_9       = 0,     /*!< MSPI1_9 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG46_FNCSEL46_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
  GPIO_PINCFG46_FNCSEL46_CLKOUT_32M    = 2,     /*!< CLKOUT_32M : 32MHz Oscillator output clock                                */
  GPIO_PINCFG46_FNCSEL46_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG46_FNCSEL46_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
  GPIO_PINCFG46_FNCSEL46_UART3TX       = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
  GPIO_PINCFG46_FNCSEL46_CT46          = 6,     /*!< CT46 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG46_FNCSEL46_NCE46         = 7,     /*!< NCE46 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG46_FNCSEL46_OBSBUS14      = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
  GPIO_PINCFG46_FNCSEL46_I2S1_SDIN     = 9,     /*!< I2S1_SDIN : I2S Data input (I2S Master/Slave 2)                           */
  GPIO_PINCFG46_FNCSEL46_I2S0_SDIN     = 10,    /*!< I2S0_SDIN : I2S Data input (I2S Master/Slave 2)                           */
  GPIO_PINCFG46_FNCSEL46_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG46_FNCSEL46_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG46_FNCSEL46_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG46_FNCSEL46_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG46_FNCSEL46_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG46_FNCSEL46_Enum;

/* =======================================================  PINCFG47  ======================================================== */
/* ============================================  GPIO PINCFG47 NCEPOL47 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG47_NCEPOL47                                                    */
  GPIO_PINCFG47_NCEPOL47_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG47_NCEPOL47_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG47_NCEPOL47_Enum;

/* ============================================  GPIO PINCFG47 NCESRC47 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG47_NCESRC47                                                    */
  GPIO_PINCFG47_NCESRC47_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG47_NCESRC47_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG47_NCESRC47_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG47_NCESRC47_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG47_NCESRC47_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG47_NCESRC47_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG47_NCESRC47_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG47_NCESRC47_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG47_NCESRC47_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG47_NCESRC47_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG47_NCESRC47_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG47_NCESRC47_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG47_NCESRC47_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG47_NCESRC47_Enum;

/* ===========================================  GPIO PINCFG47 PULLCFG47 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG47_PULLCFG47                                                   */
  GPIO_PINCFG47_PULLCFG47_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG47_PULLCFG47_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG47_PULLCFG47_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG47_PULLCFG47_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG47_PULLCFG47_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG47_PULLCFG47_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG47_PULLCFG47_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG47_PULLCFG47_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG47_PULLCFG47_Enum;

/* ==============================================  GPIO PINCFG47 DS47 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG47_DS47                                                        */
  GPIO_PINCFG47_DS47_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG47_DS47_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG47_DS47_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG47_DS47_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG47_DS47_Enum;

/* =============================================  GPIO PINCFG47 OUTCFG47 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG47_OUTCFG47                                                    */
  GPIO_PINCFG47_OUTCFG47_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG47_OUTCFG47_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG47_OUTCFG47_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG47_OUTCFG47_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG47_OUTCFG47_Enum;

/* =============================================  GPIO PINCFG47 IRPTEN47 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG47_IRPTEN47                                                    */
  GPIO_PINCFG47_IRPTEN47_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG47_IRPTEN47_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG47_IRPTEN47_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG47_IRPTEN47_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG47_IRPTEN47_Enum;

/* =============================================  GPIO PINCFG47 FNCSEL47 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG47_FNCSEL47                                                    */
  GPIO_PINCFG47_FNCSEL47_M5SCL         = 0,     /*!< M5SCL : Serial I2C Master Clock output (IOM 5)                            */
  GPIO_PINCFG47_FNCSEL47_M5SCK         = 1,     /*!< M5SCK : Serial SPI Master Clock output (IOM 5)                            */
  GPIO_PINCFG47_FNCSEL47_I2S1_CLK      = 2,     /*!< I2S1_CLK : Bidirectional I2S Bit clock. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG47_FNCSEL47_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG47_FNCSEL47_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
  GPIO_PINCFG47_FNCSEL47_UART1RX       = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
  GPIO_PINCFG47_FNCSEL47_CT47          = 6,     /*!< CT47 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG47_FNCSEL47_NCE47         = 7,     /*!< NCE47 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG47_FNCSEL47_OBSBUS15      = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
  GPIO_PINCFG47_FNCSEL47_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG47_FNCSEL47_I2S0_CLK      = 10,    /*!< I2S0_CLK : Bidirectional I2S Bit clock. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG47_FNCSEL47_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG47_FNCSEL47_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG47_FNCSEL47_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG47_FNCSEL47_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG47_FNCSEL47_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG47_FNCSEL47_Enum;

/* =======================================================  PINCFG48  ======================================================== */
/* ============================================  GPIO PINCFG48 NCEPOL48 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG48_NCEPOL48                                                    */
  GPIO_PINCFG48_NCEPOL48_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG48_NCEPOL48_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG48_NCEPOL48_Enum;

/* ============================================  GPIO PINCFG48 NCESRC48 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG48_NCESRC48                                                    */
  GPIO_PINCFG48_NCESRC48_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG48_NCESRC48_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG48_NCESRC48_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG48_NCESRC48_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG48_NCESRC48_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG48_NCESRC48_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG48_NCESRC48_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG48_NCESRC48_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG48_NCESRC48_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG48_NCESRC48_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG48_NCESRC48_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG48_NCESRC48_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG48_NCESRC48_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG48_NCESRC48_Enum;

/* ===========================================  GPIO PINCFG48 PULLCFG48 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG48_PULLCFG48                                                   */
  GPIO_PINCFG48_PULLCFG48_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG48_PULLCFG48_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG48_PULLCFG48_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG48_PULLCFG48_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG48_PULLCFG48_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG48_PULLCFG48_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG48_PULLCFG48_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG48_PULLCFG48_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG48_PULLCFG48_Enum;

/* ==============================================  GPIO PINCFG48 DS48 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG48_DS48                                                        */
  GPIO_PINCFG48_DS48_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG48_DS48_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG48_DS48_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG48_DS48_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG48_DS48_Enum;

/* =============================================  GPIO PINCFG48 OUTCFG48 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG48_OUTCFG48                                                    */
  GPIO_PINCFG48_OUTCFG48_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG48_OUTCFG48_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG48_OUTCFG48_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG48_OUTCFG48_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG48_OUTCFG48_Enum;

/* =============================================  GPIO PINCFG48 IRPTEN48 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG48_IRPTEN48                                                    */
  GPIO_PINCFG48_IRPTEN48_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG48_IRPTEN48_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG48_IRPTEN48_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG48_IRPTEN48_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG48_IRPTEN48_Enum;

/* =============================================  GPIO PINCFG48 FNCSEL48 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG48_FNCSEL48                                                    */
  GPIO_PINCFG48_FNCSEL48_M5SDAWIR3     = 0,     /*!< M5SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
                                                     Master Data I/O (SPI 3 wire mode) (IOM 5)                                 */
  GPIO_PINCFG48_FNCSEL48_M5MOSI        = 1,     /*!< M5MOSI : Serial SPI Master MOSI output (IOM 5)                            */
  GPIO_PINCFG48_FNCSEL48_I2S1_DATA     = 2,     /*!< I2S1_DATA : Bidirectional I2S Data. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG48_FNCSEL48_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG48_FNCSEL48_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
  GPIO_PINCFG48_FNCSEL48_UART3RX       = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
  GPIO_PINCFG48_FNCSEL48_CT48          = 6,     /*!< CT48 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG48_FNCSEL48_NCE48         = 7,     /*!< NCE48 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG48_FNCSEL48_OBSBUS0       = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
  GPIO_PINCFG48_FNCSEL48_I2S1_SDOUT    = 9,     /*!< I2S1_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
  GPIO_PINCFG48_FNCSEL48_I2S0_SDOUT    = 10,    /*!< I2S0_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
  GPIO_PINCFG48_FNCSEL48_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG48_FNCSEL48_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG48_FNCSEL48_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG48_FNCSEL48_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG48_FNCSEL48_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG48_FNCSEL48_Enum;

/* =======================================================  PINCFG49  ======================================================== */
/* ============================================  GPIO PINCFG49 NCEPOL49 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG49_NCEPOL49                                                    */
  GPIO_PINCFG49_NCEPOL49_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG49_NCEPOL49_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG49_NCEPOL49_Enum;

/* ============================================  GPIO PINCFG49 NCESRC49 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG49_NCESRC49                                                    */
  GPIO_PINCFG49_NCESRC49_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG49_NCESRC49_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG49_NCESRC49_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG49_NCESRC49_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG49_NCESRC49_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG49_NCESRC49_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG49_NCESRC49_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG49_NCESRC49_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG49_NCESRC49_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG49_NCESRC49_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG49_NCESRC49_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG49_NCESRC49_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG49_NCESRC49_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG49_NCESRC49_Enum;

/* ===========================================  GPIO PINCFG49 PULLCFG49 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG49_PULLCFG49                                                   */
  GPIO_PINCFG49_PULLCFG49_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG49_PULLCFG49_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG49_PULLCFG49_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG49_PULLCFG49_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG49_PULLCFG49_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG49_PULLCFG49_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG49_PULLCFG49_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG49_PULLCFG49_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG49_PULLCFG49_Enum;

/* ==============================================  GPIO PINCFG49 DS49 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG49_DS49                                                        */
  GPIO_PINCFG49_DS49_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG49_DS49_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG49_DS49_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG49_DS49_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG49_DS49_Enum;

/* =============================================  GPIO PINCFG49 OUTCFG49 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG49_OUTCFG49                                                    */
  GPIO_PINCFG49_OUTCFG49_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG49_OUTCFG49_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG49_OUTCFG49_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG49_OUTCFG49_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG49_OUTCFG49_Enum;

/* =============================================  GPIO PINCFG49 IRPTEN49 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG49_IRPTEN49                                                    */
  GPIO_PINCFG49_IRPTEN49_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG49_IRPTEN49_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG49_IRPTEN49_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG49_IRPTEN49_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG49_IRPTEN49_Enum;

/* =============================================  GPIO PINCFG49 FNCSEL49 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG49_FNCSEL49                                                    */
  GPIO_PINCFG49_FNCSEL49_M5MISO        = 0,     /*!< M5MISO : Serial SPI MASTER MISO input (IOM 5)                             */
  GPIO_PINCFG49_FNCSEL49_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
  GPIO_PINCFG49_FNCSEL49_I2S1_WS       = 2,     /*!< I2S1_WS : Bidirectional I2S L/R clock. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG49_FNCSEL49_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG49_FNCSEL49_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
  GPIO_PINCFG49_FNCSEL49_UART1RTS      = 5,     /*!< UART1RTS : UART Request to Send (RTS) (UART 1)                            */
  GPIO_PINCFG49_FNCSEL49_CT49          = 6,     /*!< CT49 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG49_FNCSEL49_NCE49         = 7,     /*!< NCE49 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG49_FNCSEL49_OBSBUS1       = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
  GPIO_PINCFG49_FNCSEL49_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG49_FNCSEL49_I2S0_WS       = 10,    /*!< I2S0_WS : Bidirectional I2S L/R clock. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG49_FNCSEL49_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG49_FNCSEL49_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG49_FNCSEL49_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG49_FNCSEL49_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG49_FNCSEL49_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG49_FNCSEL49_Enum;

/* =======================================================  PINCFG50  ======================================================== */
/* ============================================  GPIO PINCFG50 NCEPOL50 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG50_NCEPOL50                                                    */
  GPIO_PINCFG50_NCEPOL50_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG50_NCEPOL50_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG50_NCEPOL50_Enum;

/* ============================================  GPIO PINCFG50 NCESRC50 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG50_NCESRC50                                                    */
  GPIO_PINCFG50_NCESRC50_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG50_NCESRC50_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG50_NCESRC50_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG50_NCESRC50_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG50_NCESRC50_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG50_NCESRC50_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG50_NCESRC50_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG50_NCESRC50_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG50_NCESRC50_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG50_NCESRC50_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG50_NCESRC50_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG50_NCESRC50_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG50_NCESRC50_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG50_NCESRC50_Enum;

/* ===========================================  GPIO PINCFG50 PULLCFG50 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG50_PULLCFG50                                                   */
  GPIO_PINCFG50_PULLCFG50_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG50_PULLCFG50_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG50_PULLCFG50_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG50_PULLCFG50_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG50_PULLCFG50_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG50_PULLCFG50_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG50_PULLCFG50_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG50_PULLCFG50_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG50_PULLCFG50_Enum;

/* ==============================================  GPIO PINCFG50 DS50 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG50_DS50                                                        */
  GPIO_PINCFG50_DS50_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG50_DS50_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG50_DS50_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG50_DS50_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG50_DS50_Enum;

/* =============================================  GPIO PINCFG50 OUTCFG50 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG50_OUTCFG50                                                    */
  GPIO_PINCFG50_OUTCFG50_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG50_OUTCFG50_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG50_OUTCFG50_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG50_OUTCFG50_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG50_OUTCFG50_Enum;

/* =============================================  GPIO PINCFG50 IRPTEN50 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG50_IRPTEN50                                                    */
  GPIO_PINCFG50_IRPTEN50_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG50_IRPTEN50_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG50_IRPTEN50_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG50_IRPTEN50_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG50_IRPTEN50_Enum;

/* =============================================  GPIO PINCFG50 FNCSEL50 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG50_FNCSEL50                                                    */
  GPIO_PINCFG50_FNCSEL50_PDM0_CLK      = 0,     /*!< PDM0_CLK : PDMx Clock output (I2C Master/Slave D)                         */
  GPIO_PINCFG50_FNCSEL50_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
  GPIO_PINCFG50_FNCSEL50_SWTRACECLK    = 2,     /*!< SWTRACECLK : Serial Wire Debug Trace Clock                                */
  GPIO_PINCFG50_FNCSEL50_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG50_FNCSEL50_UART2RTS      = 4,     /*!< UART2RTS : UART Request to Send (RTS) (UART 2)                            */
  GPIO_PINCFG50_FNCSEL50_UART3RTS      = 5,     /*!< UART3RTS : UART Request to Send (RTS) (UART 3)                            */
  GPIO_PINCFG50_FNCSEL50_CT50          = 6,     /*!< CT50 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG50_FNCSEL50_NCE50         = 7,     /*!< NCE50 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG50_FNCSEL50_OBSBUS2       = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
  GPIO_PINCFG50_FNCSEL50_DISP_TE       = 9,     /*!< DISP_TE : Display TE input                                                */
  GPIO_PINCFG50_FNCSEL50_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG50_FNCSEL50_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG50_FNCSEL50_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG50_FNCSEL50_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG50_FNCSEL50_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG50_FNCSEL50_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG50_FNCSEL50_Enum;

/* =======================================================  PINCFG51  ======================================================== */
/* ============================================  GPIO PINCFG51 NCEPOL51 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG51_NCEPOL51                                                    */
  GPIO_PINCFG51_NCEPOL51_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG51_NCEPOL51_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG51_NCEPOL51_Enum;

/* ============================================  GPIO PINCFG51 NCESRC51 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG51_NCESRC51                                                    */
  GPIO_PINCFG51_NCESRC51_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG51_NCESRC51_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG51_NCESRC51_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG51_NCESRC51_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG51_NCESRC51_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG51_NCESRC51_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG51_NCESRC51_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG51_NCESRC51_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG51_NCESRC51_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG51_NCESRC51_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG51_NCESRC51_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG51_NCESRC51_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG51_NCESRC51_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG51_NCESRC51_Enum;

/* ===========================================  GPIO PINCFG51 PULLCFG51 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG51_PULLCFG51                                                   */
  GPIO_PINCFG51_PULLCFG51_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG51_PULLCFG51_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG51_PULLCFG51_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG51_PULLCFG51_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG51_PULLCFG51_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG51_PULLCFG51_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG51_PULLCFG51_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG51_PULLCFG51_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG51_PULLCFG51_Enum;

/* ==============================================  GPIO PINCFG51 DS51 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG51_DS51                                                        */
  GPIO_PINCFG51_DS51_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG51_DS51_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG51_DS51_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG51_DS51_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG51_DS51_Enum;

/* =============================================  GPIO PINCFG51 OUTCFG51 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG51_OUTCFG51                                                    */
  GPIO_PINCFG51_OUTCFG51_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG51_OUTCFG51_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG51_OUTCFG51_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG51_OUTCFG51_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG51_OUTCFG51_Enum;

/* =============================================  GPIO PINCFG51 IRPTEN51 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG51_IRPTEN51                                                    */
  GPIO_PINCFG51_IRPTEN51_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG51_IRPTEN51_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG51_IRPTEN51_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG51_IRPTEN51_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG51_IRPTEN51_Enum;

/* =============================================  GPIO PINCFG51 FNCSEL51 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG51_FNCSEL51                                                    */
  GPIO_PINCFG51_FNCSEL51_PDM0_DATA     = 0,     /*!< PDM0_DATA : PDMx audio data input to chip (I2C Master/Slave
                                                     D)                                                                        */
  GPIO_PINCFG51_FNCSEL51_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
  GPIO_PINCFG51_FNCSEL51_SWTRACE0      = 2,     /*!< SWTRACE0 : Serial Wire Debug Trace Output 0                               */
  GPIO_PINCFG51_FNCSEL51_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG51_FNCSEL51_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
  GPIO_PINCFG51_FNCSEL51_UART1CTS      = 5,     /*!< UART1CTS : UART Clear to Send (CTS) (UART 1)                              */
  GPIO_PINCFG51_FNCSEL51_CT51          = 6,     /*!< CT51 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG51_FNCSEL51_NCE51         = 7,     /*!< NCE51 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG51_FNCSEL51_OBSBUS3       = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
  GPIO_PINCFG51_FNCSEL51_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG51_FNCSEL51_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG51_FNCSEL51_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG51_FNCSEL51_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG51_FNCSEL51_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG51_FNCSEL51_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG51_FNCSEL51_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG51_FNCSEL51_Enum;

/* =======================================================  PINCFG52  ======================================================== */
/* ============================================  GPIO PINCFG52 NCEPOL52 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG52_NCEPOL52                                                    */
  GPIO_PINCFG52_NCEPOL52_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG52_NCEPOL52_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG52_NCEPOL52_Enum;

/* ============================================  GPIO PINCFG52 NCESRC52 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG52_NCESRC52                                                    */
  GPIO_PINCFG52_NCESRC52_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG52_NCESRC52_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG52_NCESRC52_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG52_NCESRC52_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG52_NCESRC52_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG52_NCESRC52_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG52_NCESRC52_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG52_NCESRC52_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG52_NCESRC52_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG52_NCESRC52_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG52_NCESRC52_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG52_NCESRC52_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG52_NCESRC52_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG52_NCESRC52_Enum;

/* ===========================================  GPIO PINCFG52 PULLCFG52 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG52_PULLCFG52                                                   */
  GPIO_PINCFG52_PULLCFG52_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG52_PULLCFG52_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG52_PULLCFG52_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG52_PULLCFG52_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG52_PULLCFG52_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG52_PULLCFG52_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG52_PULLCFG52_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG52_PULLCFG52_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG52_PULLCFG52_Enum;

/* ==============================================  GPIO PINCFG52 DS52 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG52_DS52                                                        */
  GPIO_PINCFG52_DS52_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG52_DS52_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG52_DS52_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG52_DS52_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG52_DS52_Enum;

/* =============================================  GPIO PINCFG52 OUTCFG52 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG52_OUTCFG52                                                    */
  GPIO_PINCFG52_OUTCFG52_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG52_OUTCFG52_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG52_OUTCFG52_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG52_OUTCFG52_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG52_OUTCFG52_Enum;

/* =============================================  GPIO PINCFG52 IRPTEN52 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG52_IRPTEN52                                                    */
  GPIO_PINCFG52_IRPTEN52_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG52_IRPTEN52_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG52_IRPTEN52_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG52_IRPTEN52_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG52_IRPTEN52_Enum;

/* =============================================  GPIO PINCFG52 FNCSEL52 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG52_FNCSEL52                                                    */
  GPIO_PINCFG52_FNCSEL52_PDM1_CLK      = 0,     /*!< PDM1_CLK : PDMx Clock output (I2C Master/Slave D)                         */
  GPIO_PINCFG52_FNCSEL52_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
  GPIO_PINCFG52_FNCSEL52_SWTRACE1      = 2,     /*!< SWTRACE1 : Serial Wire Debug Trace Output 1                               */
  GPIO_PINCFG52_FNCSEL52_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG52_FNCSEL52_UART2CTS      = 4,     /*!< UART2CTS : UART Clear to Send (CTS) (UART 2)                              */
  GPIO_PINCFG52_FNCSEL52_UART3CTS      = 5,     /*!< UART3CTS : UART Clear to Send (CTS) (UART 3)                              */
  GPIO_PINCFG52_FNCSEL52_CT52          = 6,     /*!< CT52 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG52_FNCSEL52_NCE52         = 7,     /*!< NCE52 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG52_FNCSEL52_OBSBUS4       = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
  GPIO_PINCFG52_FNCSEL52_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG52_FNCSEL52_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG52_FNCSEL52_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG52_FNCSEL52_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG52_FNCSEL52_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG52_FNCSEL52_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG52_FNCSEL52_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG52_FNCSEL52_Enum;

/* =======================================================  PINCFG53  ======================================================== */
/* ============================================  GPIO PINCFG53 NCEPOL53 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG53_NCEPOL53                                                    */
  GPIO_PINCFG53_NCEPOL53_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG53_NCEPOL53_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG53_NCEPOL53_Enum;

/* ============================================  GPIO PINCFG53 NCESRC53 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG53_NCESRC53                                                    */
  GPIO_PINCFG53_NCESRC53_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG53_NCESRC53_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG53_NCESRC53_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG53_NCESRC53_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG53_NCESRC53_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG53_NCESRC53_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG53_NCESRC53_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG53_NCESRC53_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG53_NCESRC53_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG53_NCESRC53_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG53_NCESRC53_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG53_NCESRC53_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG53_NCESRC53_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG53_NCESRC53_Enum;

/* ===========================================  GPIO PINCFG53 PULLCFG53 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG53_PULLCFG53                                                   */
  GPIO_PINCFG53_PULLCFG53_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG53_PULLCFG53_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG53_PULLCFG53_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG53_PULLCFG53_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG53_PULLCFG53_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG53_PULLCFG53_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG53_PULLCFG53_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG53_PULLCFG53_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG53_PULLCFG53_Enum;

/* ==============================================  GPIO PINCFG53 DS53 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG53_DS53                                                        */
  GPIO_PINCFG53_DS53_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG53_DS53_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG53_DS53_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG53_DS53_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG53_DS53_Enum;

/* =============================================  GPIO PINCFG53 OUTCFG53 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG53_OUTCFG53                                                    */
  GPIO_PINCFG53_OUTCFG53_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG53_OUTCFG53_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG53_OUTCFG53_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG53_OUTCFG53_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG53_OUTCFG53_Enum;

/* =============================================  GPIO PINCFG53 IRPTEN53 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG53_IRPTEN53                                                    */
  GPIO_PINCFG53_IRPTEN53_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG53_IRPTEN53_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG53_IRPTEN53_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG53_IRPTEN53_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG53_IRPTEN53_Enum;

/* =============================================  GPIO PINCFG53 FNCSEL53 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG53_FNCSEL53                                                    */
  GPIO_PINCFG53_FNCSEL53_PDM1_DATA     = 0,     /*!< PDM1_DATA : PDMx audio data input to chip (I2C Master/Slave
                                                     D)                                                                        */
  GPIO_PINCFG53_FNCSEL53_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
  GPIO_PINCFG53_FNCSEL53_SWTRACE2      = 2,     /*!< SWTRACE2 : Serial Wire Debug Trace Output 2                               */
  GPIO_PINCFG53_FNCSEL53_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG53_FNCSEL53_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
  GPIO_PINCFG53_FNCSEL53_UART1TX       = 5,     /*!< UART1TX : UART transmit output (UART 1)                                   */
  GPIO_PINCFG53_FNCSEL53_CT53          = 6,     /*!< CT53 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG53_FNCSEL53_NCE53         = 7,     /*!< NCE53 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG53_FNCSEL53_OBSBUS5       = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
  GPIO_PINCFG53_FNCSEL53_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG53_FNCSEL53_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG53_FNCSEL53_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG53_FNCSEL53_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG53_FNCSEL53_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG53_FNCSEL53_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG53_FNCSEL53_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG53_FNCSEL53_Enum;

/* =======================================================  PINCFG54  ======================================================== */
/* ============================================  GPIO PINCFG54 NCEPOL54 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG54_NCEPOL54                                                    */
  GPIO_PINCFG54_NCEPOL54_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG54_NCEPOL54_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG54_NCEPOL54_Enum;

/* ============================================  GPIO PINCFG54 NCESRC54 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG54_NCESRC54                                                    */
  GPIO_PINCFG54_NCESRC54_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG54_NCESRC54_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG54_NCESRC54_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG54_NCESRC54_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG54_NCESRC54_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG54_NCESRC54_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG54_NCESRC54_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG54_NCESRC54_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG54_NCESRC54_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG54_NCESRC54_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG54_NCESRC54_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG54_NCESRC54_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG54_NCESRC54_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG54_NCESRC54_Enum;

/* ===========================================  GPIO PINCFG54 PULLCFG54 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG54_PULLCFG54                                                   */
  GPIO_PINCFG54_PULLCFG54_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG54_PULLCFG54_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG54_PULLCFG54_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG54_PULLCFG54_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG54_PULLCFG54_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG54_PULLCFG54_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG54_PULLCFG54_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG54_PULLCFG54_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG54_PULLCFG54_Enum;

/* ==============================================  GPIO PINCFG54 DS54 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG54_DS54                                                        */
  GPIO_PINCFG54_DS54_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG54_DS54_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG54_DS54_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG54_DS54_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG54_DS54_Enum;

/* =============================================  GPIO PINCFG54 OUTCFG54 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG54_OUTCFG54                                                    */
  GPIO_PINCFG54_OUTCFG54_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG54_OUTCFG54_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG54_OUTCFG54_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG54_OUTCFG54_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG54_OUTCFG54_Enum;

/* =============================================  GPIO PINCFG54 IRPTEN54 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG54_IRPTEN54                                                    */
  GPIO_PINCFG54_IRPTEN54_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG54_IRPTEN54_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG54_IRPTEN54_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG54_IRPTEN54_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG54_IRPTEN54_Enum;

/* =============================================  GPIO PINCFG54 FNCSEL54 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG54_FNCSEL54                                                    */
  GPIO_PINCFG54_FNCSEL54_PDM2_CLK      = 0,     /*!< PDM2_CLK : PDMx Clock output (I2C Master/Slave D)                         */
  GPIO_PINCFG54_FNCSEL54_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
  GPIO_PINCFG54_FNCSEL54_SWTRACE3      = 2,     /*!< SWTRACE3 : Serial Wire Debug Trace Output 3                               */
  GPIO_PINCFG54_FNCSEL54_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG54_FNCSEL54_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
  GPIO_PINCFG54_FNCSEL54_UART3TX       = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
  GPIO_PINCFG54_FNCSEL54_CT54          = 6,     /*!< CT54 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG54_FNCSEL54_NCE54         = 7,     /*!< NCE54 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG54_FNCSEL54_OBSBUS6       = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
  GPIO_PINCFG54_FNCSEL54_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG54_FNCSEL54_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG54_FNCSEL54_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG54_FNCSEL54_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG54_FNCSEL54_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG54_FNCSEL54_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG54_FNCSEL54_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG54_FNCSEL54_Enum;

/* =======================================================  PINCFG55  ======================================================== */
/* ============================================  GPIO PINCFG55 NCEPOL55 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG55_NCEPOL55                                                    */
  GPIO_PINCFG55_NCEPOL55_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG55_NCEPOL55_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG55_NCEPOL55_Enum;

/* ============================================  GPIO PINCFG55 NCESRC55 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG55_NCESRC55                                                    */
  GPIO_PINCFG55_NCESRC55_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG55_NCESRC55_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG55_NCESRC55_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG55_NCESRC55_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG55_NCESRC55_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG55_NCESRC55_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG55_NCESRC55_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG55_NCESRC55_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG55_NCESRC55_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG55_NCESRC55_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG55_NCESRC55_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG55_NCESRC55_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG55_NCESRC55_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG55_NCESRC55_Enum;

/* ===========================================  GPIO PINCFG55 PULLCFG55 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG55_PULLCFG55                                                   */
  GPIO_PINCFG55_PULLCFG55_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG55_PULLCFG55_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG55_PULLCFG55_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG55_PULLCFG55_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG55_PULLCFG55_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG55_PULLCFG55_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG55_PULLCFG55_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG55_PULLCFG55_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG55_PULLCFG55_Enum;

/* ==============================================  GPIO PINCFG55 DS55 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG55_DS55                                                        */
  GPIO_PINCFG55_DS55_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG55_DS55_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG55_DS55_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG55_DS55_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG55_DS55_Enum;

/* =============================================  GPIO PINCFG55 OUTCFG55 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG55_OUTCFG55                                                    */
  GPIO_PINCFG55_OUTCFG55_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG55_OUTCFG55_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG55_OUTCFG55_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG55_OUTCFG55_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG55_OUTCFG55_Enum;

/* =============================================  GPIO PINCFG55 IRPTEN55 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG55_IRPTEN55                                                    */
  GPIO_PINCFG55_IRPTEN55_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG55_IRPTEN55_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG55_IRPTEN55_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG55_IRPTEN55_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG55_IRPTEN55_Enum;

/* =============================================  GPIO PINCFG55 FNCSEL55 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG55_FNCSEL55                                                    */
  GPIO_PINCFG55_FNCSEL55_PDM2_DATA     = 0,     /*!< PDM2_DATA : PDMx audio data input to chip (I2C Master/Slave
                                                     D)                                                                        */
  GPIO_PINCFG55_FNCSEL55_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
  GPIO_PINCFG55_FNCSEL55_SWTRACECTL    = 2,     /*!< SWTRACECTL : Serial Wire Debug Trace Control                              */
  GPIO_PINCFG55_FNCSEL55_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG55_FNCSEL55_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
  GPIO_PINCFG55_FNCSEL55_UART1RX       = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
  GPIO_PINCFG55_FNCSEL55_CT55          = 6,     /*!< CT55 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG55_FNCSEL55_NCE55         = 7,     /*!< NCE55 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG55_FNCSEL55_OBSBUS7       = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
  GPIO_PINCFG55_FNCSEL55_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG55_FNCSEL55_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG55_FNCSEL55_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG55_FNCSEL55_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG55_FNCSEL55_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG55_FNCSEL55_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG55_FNCSEL55_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG55_FNCSEL55_Enum;

/* =======================================================  PINCFG56  ======================================================== */
/* ============================================  GPIO PINCFG56 NCEPOL56 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG56_NCEPOL56                                                    */
  GPIO_PINCFG56_NCEPOL56_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG56_NCEPOL56_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG56_NCEPOL56_Enum;

/* ============================================  GPIO PINCFG56 NCESRC56 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG56_NCESRC56                                                    */
  GPIO_PINCFG56_NCESRC56_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG56_NCESRC56_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG56_NCESRC56_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG56_NCESRC56_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG56_NCESRC56_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG56_NCESRC56_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG56_NCESRC56_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG56_NCESRC56_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG56_NCESRC56_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG56_NCESRC56_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG56_NCESRC56_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG56_NCESRC56_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG56_NCESRC56_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG56_NCESRC56_Enum;

/* ===========================================  GPIO PINCFG56 PULLCFG56 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG56_PULLCFG56                                                   */
  GPIO_PINCFG56_PULLCFG56_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG56_PULLCFG56_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG56_PULLCFG56_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG56_PULLCFG56_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG56_PULLCFG56_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG56_PULLCFG56_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG56_PULLCFG56_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG56_PULLCFG56_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG56_PULLCFG56_Enum;

/* ==============================================  GPIO PINCFG56 DS56 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG56_DS56                                                        */
  GPIO_PINCFG56_DS56_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG56_DS56_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG56_DS56_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG56_DS56_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG56_DS56_Enum;

/* =============================================  GPIO PINCFG56 OUTCFG56 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG56_OUTCFG56                                                    */
  GPIO_PINCFG56_OUTCFG56_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG56_OUTCFG56_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG56_OUTCFG56_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG56_OUTCFG56_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG56_OUTCFG56_Enum;

/* =============================================  GPIO PINCFG56 IRPTEN56 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG56_IRPTEN56                                                    */
  GPIO_PINCFG56_IRPTEN56_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG56_IRPTEN56_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG56_IRPTEN56_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG56_IRPTEN56_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG56_IRPTEN56_Enum;

/* =============================================  GPIO PINCFG56 FNCSEL56 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG56_FNCSEL56                                                    */
  GPIO_PINCFG56_FNCSEL56_PDM3_CLK      = 0,     /*!< PDM3_CLK : PDMx Clock output (I2C Master/Slave D)                         */
  GPIO_PINCFG56_FNCSEL56_TRIG2         = 1,     /*!< TRIG2 : ADC trigger input                                                 */
  GPIO_PINCFG56_FNCSEL56_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG56_FNCSEL56_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG56_FNCSEL56_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
  GPIO_PINCFG56_FNCSEL56_UART3RX       = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
  GPIO_PINCFG56_FNCSEL56_CT56          = 6,     /*!< CT56 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG56_FNCSEL56_NCE56         = 7,     /*!< NCE56 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG56_FNCSEL56_OBSBUS8       = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
  GPIO_PINCFG56_FNCSEL56_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG56_FNCSEL56_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG56_FNCSEL56_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG56_FNCSEL56_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG56_FNCSEL56_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG56_FNCSEL56_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG56_FNCSEL56_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG56_FNCSEL56_Enum;

/* =======================================================  PINCFG57  ======================================================== */
/* ============================================  GPIO PINCFG57 NCEPOL57 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG57_NCEPOL57                                                    */
  GPIO_PINCFG57_NCEPOL57_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG57_NCEPOL57_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG57_NCEPOL57_Enum;

/* ============================================  GPIO PINCFG57 NCESRC57 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG57_NCESRC57                                                    */
  GPIO_PINCFG57_NCESRC57_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG57_NCESRC57_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG57_NCESRC57_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG57_NCESRC57_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG57_NCESRC57_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG57_NCESRC57_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG57_NCESRC57_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG57_NCESRC57_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG57_NCESRC57_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG57_NCESRC57_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG57_NCESRC57_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG57_NCESRC57_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG57_NCESRC57_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG57_NCESRC57_Enum;

/* ===========================================  GPIO PINCFG57 PULLCFG57 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG57_PULLCFG57                                                   */
  GPIO_PINCFG57_PULLCFG57_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG57_PULLCFG57_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG57_PULLCFG57_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG57_PULLCFG57_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG57_PULLCFG57_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG57_PULLCFG57_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG57_PULLCFG57_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG57_PULLCFG57_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG57_PULLCFG57_Enum;

/* ==============================================  GPIO PINCFG57 DS57 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG57_DS57                                                        */
  GPIO_PINCFG57_DS57_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG57_DS57_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG57_DS57_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG57_DS57_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG57_DS57_Enum;

/* =============================================  GPIO PINCFG57 OUTCFG57 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG57_OUTCFG57                                                    */
  GPIO_PINCFG57_OUTCFG57_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG57_OUTCFG57_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG57_OUTCFG57_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG57_OUTCFG57_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG57_OUTCFG57_Enum;

/* =============================================  GPIO PINCFG57 IRPTEN57 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG57_IRPTEN57                                                    */
  GPIO_PINCFG57_IRPTEN57_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG57_IRPTEN57_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG57_IRPTEN57_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG57_IRPTEN57_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG57_IRPTEN57_Enum;

/* =============================================  GPIO PINCFG57 FNCSEL57 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG57_FNCSEL57                                                    */
  GPIO_PINCFG57_FNCSEL57_PDM3_DATA     = 0,     /*!< PDM3_DATA : PDMx audio data input to chip (I2C Master/Slave
                                                     D)                                                                        */
  GPIO_PINCFG57_FNCSEL57_TRIG3         = 1,     /*!< TRIG3 : ADC trigger input                                                 */
  GPIO_PINCFG57_FNCSEL57_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG57_FNCSEL57_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG57_FNCSEL57_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
  GPIO_PINCFG57_FNCSEL57_UART1RTS      = 5,     /*!< UART1RTS : UART Request to Send (RTS) (UART 1)                            */
  GPIO_PINCFG57_FNCSEL57_CT57          = 6,     /*!< CT57 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG57_FNCSEL57_NCE57         = 7,     /*!< NCE57 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG57_FNCSEL57_OBSBUS9       = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
  GPIO_PINCFG57_FNCSEL57_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG57_FNCSEL57_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG57_FNCSEL57_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG57_FNCSEL57_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG57_FNCSEL57_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG57_FNCSEL57_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG57_FNCSEL57_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG57_FNCSEL57_Enum;

/* =======================================================  PINCFG58  ======================================================== */
/* ============================================  GPIO PINCFG58 NCEPOL58 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG58_NCEPOL58                                                    */
  GPIO_PINCFG58_NCEPOL58_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG58_NCEPOL58_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG58_NCEPOL58_Enum;

/* ============================================  GPIO PINCFG58 NCESRC58 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG58_NCESRC58                                                    */
  GPIO_PINCFG58_NCESRC58_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG58_NCESRC58_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG58_NCESRC58_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG58_NCESRC58_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG58_NCESRC58_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG58_NCESRC58_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG58_NCESRC58_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG58_NCESRC58_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG58_NCESRC58_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG58_NCESRC58_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG58_NCESRC58_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG58_NCESRC58_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG58_NCESRC58_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG58_NCESRC58_Enum;

/* ===========================================  GPIO PINCFG58 PULLCFG58 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG58_PULLCFG58                                                   */
  GPIO_PINCFG58_PULLCFG58_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG58_PULLCFG58_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG58_PULLCFG58_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG58_PULLCFG58_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG58_PULLCFG58_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG58_PULLCFG58_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG58_PULLCFG58_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG58_PULLCFG58_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG58_PULLCFG58_Enum;

/* ==============================================  GPIO PINCFG58 DS58 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG58_DS58                                                        */
  GPIO_PINCFG58_DS58_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG58_DS58_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG58_DS58_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG58_DS58_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG58_DS58_Enum;

/* =============================================  GPIO PINCFG58 OUTCFG58 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG58_OUTCFG58                                                    */
  GPIO_PINCFG58_OUTCFG58_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG58_OUTCFG58_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG58_OUTCFG58_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG58_OUTCFG58_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG58_OUTCFG58_Enum;

/* =============================================  GPIO PINCFG58 IRPTEN58 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG58_IRPTEN58                                                    */
  GPIO_PINCFG58_IRPTEN58_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG58_IRPTEN58_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG58_IRPTEN58_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG58_IRPTEN58_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG58_IRPTEN58_Enum;

/* =============================================  GPIO PINCFG58 FNCSEL58 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG58_FNCSEL58                                                    */
  GPIO_PINCFG58_FNCSEL58_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG58_FNCSEL58_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG58_FNCSEL58_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG58_FNCSEL58_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG58_FNCSEL58_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
  GPIO_PINCFG58_FNCSEL58_UART3RTS      = 5,     /*!< UART3RTS : UART Request to Send (RTS) (UART 3)                            */
  GPIO_PINCFG58_FNCSEL58_CT58          = 6,     /*!< CT58 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG58_FNCSEL58_NCE58         = 7,     /*!< NCE58 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG58_FNCSEL58_OBSBUS10      = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
  GPIO_PINCFG58_FNCSEL58_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG58_FNCSEL58_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG58_FNCSEL58_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG58_FNCSEL58_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG58_FNCSEL58_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG58_FNCSEL58_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG58_FNCSEL58_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG58_FNCSEL58_Enum;

/* =======================================================  PINCFG59  ======================================================== */
/* ============================================  GPIO PINCFG59 NCEPOL59 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG59_NCEPOL59                                                    */
  GPIO_PINCFG59_NCEPOL59_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG59_NCEPOL59_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG59_NCEPOL59_Enum;

/* ============================================  GPIO PINCFG59 NCESRC59 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG59_NCESRC59                                                    */
  GPIO_PINCFG59_NCESRC59_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG59_NCESRC59_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG59_NCESRC59_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG59_NCESRC59_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG59_NCESRC59_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG59_NCESRC59_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG59_NCESRC59_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG59_NCESRC59_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG59_NCESRC59_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG59_NCESRC59_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG59_NCESRC59_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG59_NCESRC59_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG59_NCESRC59_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG59_NCESRC59_Enum;

/* ===========================================  GPIO PINCFG59 PULLCFG59 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG59_PULLCFG59                                                   */
  GPIO_PINCFG59_PULLCFG59_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG59_PULLCFG59_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG59_PULLCFG59_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG59_PULLCFG59_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG59_PULLCFG59_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG59_PULLCFG59_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG59_PULLCFG59_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG59_PULLCFG59_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG59_PULLCFG59_Enum;

/* ==============================================  GPIO PINCFG59 DS59 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG59_DS59                                                        */
  GPIO_PINCFG59_DS59_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG59_DS59_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG59_DS59_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG59_DS59_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG59_DS59_Enum;

/* =============================================  GPIO PINCFG59 OUTCFG59 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG59_OUTCFG59                                                    */
  GPIO_PINCFG59_OUTCFG59_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG59_OUTCFG59_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG59_OUTCFG59_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG59_OUTCFG59_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG59_OUTCFG59_Enum;

/* =============================================  GPIO PINCFG59 IRPTEN59 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG59_IRPTEN59                                                    */
  GPIO_PINCFG59_IRPTEN59_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG59_IRPTEN59_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG59_IRPTEN59_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG59_IRPTEN59_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG59_IRPTEN59_Enum;

/* =============================================  GPIO PINCFG59 FNCSEL59 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG59_FNCSEL59                                                    */
  GPIO_PINCFG59_FNCSEL59_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG59_FNCSEL59_TRIG0         = 1,     /*!< TRIG0 : ADC trigger input                                                 */
  GPIO_PINCFG59_FNCSEL59_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG59_FNCSEL59_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG59_FNCSEL59_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
  GPIO_PINCFG59_FNCSEL59_UART1CTS      = 5,     /*!< UART1CTS : UART Clear to Send (CTS) (UART 1)                              */
  GPIO_PINCFG59_FNCSEL59_CT59          = 6,     /*!< CT59 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG59_FNCSEL59_NCE59         = 7,     /*!< NCE59 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG59_FNCSEL59_OBSBUS11      = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
  GPIO_PINCFG59_FNCSEL59_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG59_FNCSEL59_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG59_FNCSEL59_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG59_FNCSEL59_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG59_FNCSEL59_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG59_FNCSEL59_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG59_FNCSEL59_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG59_FNCSEL59_Enum;

/* =======================================================  PINCFG60  ======================================================== */
/* ============================================  GPIO PINCFG60 NCEPOL60 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG60_NCEPOL60                                                    */
  GPIO_PINCFG60_NCEPOL60_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG60_NCEPOL60_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG60_NCEPOL60_Enum;

/* ============================================  GPIO PINCFG60 NCESRC60 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG60_NCESRC60                                                    */
  GPIO_PINCFG60_NCESRC60_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG60_NCESRC60_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG60_NCESRC60_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG60_NCESRC60_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG60_NCESRC60_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG60_NCESRC60_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG60_NCESRC60_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG60_NCESRC60_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG60_NCESRC60_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG60_NCESRC60_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG60_NCESRC60_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG60_NCESRC60_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG60_NCESRC60_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG60_NCESRC60_Enum;

/* ===========================================  GPIO PINCFG60 PULLCFG60 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG60_PULLCFG60                                                   */
  GPIO_PINCFG60_PULLCFG60_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG60_PULLCFG60_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG60_PULLCFG60_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG60_PULLCFG60_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG60_PULLCFG60_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG60_PULLCFG60_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG60_PULLCFG60_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG60_PULLCFG60_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG60_PULLCFG60_Enum;

/* ==============================================  GPIO PINCFG60 DS60 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG60_DS60                                                        */
  GPIO_PINCFG60_DS60_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG60_DS60_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG60_DS60_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG60_DS60_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG60_DS60_Enum;

/* =============================================  GPIO PINCFG60 OUTCFG60 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG60_OUTCFG60                                                    */
  GPIO_PINCFG60_OUTCFG60_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG60_OUTCFG60_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG60_OUTCFG60_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG60_OUTCFG60_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG60_OUTCFG60_Enum;

/* =============================================  GPIO PINCFG60 IRPTEN60 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG60_IRPTEN60                                                    */
  GPIO_PINCFG60_IRPTEN60_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG60_IRPTEN60_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG60_IRPTEN60_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG60_IRPTEN60_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG60_IRPTEN60_Enum;

/* =============================================  GPIO PINCFG60 FNCSEL60 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG60_FNCSEL60                                                    */
  GPIO_PINCFG60_FNCSEL60_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG60_FNCSEL60_TRIG1         = 1,     /*!< TRIG1 : ADC trigger input                                                 */
  GPIO_PINCFG60_FNCSEL60_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG60_FNCSEL60_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG60_FNCSEL60_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
  GPIO_PINCFG60_FNCSEL60_UART3CTS      = 5,     /*!< UART3CTS : UART Clear to Send (CTS) (UART 3)                              */
  GPIO_PINCFG60_FNCSEL60_CT60          = 6,     /*!< CT60 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG60_FNCSEL60_NCE60         = 7,     /*!< NCE60 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG60_FNCSEL60_OBSBUS12      = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
  GPIO_PINCFG60_FNCSEL60_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG60_FNCSEL60_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG60_FNCSEL60_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG60_FNCSEL60_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG60_FNCSEL60_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG60_FNCSEL60_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG60_FNCSEL60_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG60_FNCSEL60_Enum;

/* =======================================================  PINCFG61  ======================================================== */
/* ============================================  GPIO PINCFG61 NCEPOL61 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG61_NCEPOL61                                                    */
  GPIO_PINCFG61_NCEPOL61_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG61_NCEPOL61_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG61_NCEPOL61_Enum;

/* ============================================  GPIO PINCFG61 NCESRC61 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG61_NCESRC61                                                    */
  GPIO_PINCFG61_NCESRC61_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG61_NCESRC61_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG61_NCESRC61_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG61_NCESRC61_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG61_NCESRC61_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG61_NCESRC61_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG61_NCESRC61_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG61_NCESRC61_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG61_NCESRC61_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG61_NCESRC61_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG61_NCESRC61_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG61_NCESRC61_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG61_NCESRC61_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG61_NCESRC61_Enum;

/* ===========================================  GPIO PINCFG61 PULLCFG61 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG61_PULLCFG61                                                   */
  GPIO_PINCFG61_PULLCFG61_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG61_PULLCFG61_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG61_PULLCFG61_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG61_PULLCFG61_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG61_PULLCFG61_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG61_PULLCFG61_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG61_PULLCFG61_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG61_PULLCFG61_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG61_PULLCFG61_Enum;

/* ==============================================  GPIO PINCFG61 DS61 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG61_DS61                                                        */
  GPIO_PINCFG61_DS61_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG61_DS61_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG61_DS61_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG61_DS61_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG61_DS61_Enum;

/* =============================================  GPIO PINCFG61 OUTCFG61 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG61_OUTCFG61                                                    */
  GPIO_PINCFG61_OUTCFG61_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG61_OUTCFG61_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG61_OUTCFG61_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG61_OUTCFG61_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG61_OUTCFG61_Enum;

/* =============================================  GPIO PINCFG61 IRPTEN61 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG61_IRPTEN61                                                    */
  GPIO_PINCFG61_IRPTEN61_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG61_IRPTEN61_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG61_IRPTEN61_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG61_IRPTEN61_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG61_IRPTEN61_Enum;

/* =============================================  GPIO PINCFG61 FNCSEL61 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG61_FNCSEL61                                                    */
  GPIO_PINCFG61_FNCSEL61_M6SCL         = 0,     /*!< M6SCL : Serial I2C Master Clock output (IOM 6)                            */
  GPIO_PINCFG61_FNCSEL61_M6SCK         = 1,     /*!< M6SCK : Serial SPI Master Clock output (IOM 6)                            */
  GPIO_PINCFG61_FNCSEL61_I2S1_CLK      = 2,     /*!< I2S1_CLK : Bidirectional I2S Bit clock. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG61_FNCSEL61_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG61_FNCSEL61_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
  GPIO_PINCFG61_FNCSEL61_UART3TX       = 5,     /*!< UART3TX : UART transmit output (UART 3)                                   */
  GPIO_PINCFG61_FNCSEL61_CT61          = 6,     /*!< CT61 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG61_FNCSEL61_NCE61         = 7,     /*!< NCE61 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG61_FNCSEL61_OBSBUS13      = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
  GPIO_PINCFG61_FNCSEL61_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG61_FNCSEL61_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG61_FNCSEL61_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG61_FNCSEL61_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG61_FNCSEL61_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG61_FNCSEL61_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG61_FNCSEL61_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG61_FNCSEL61_Enum;

/* =======================================================  PINCFG62  ======================================================== */
/* ============================================  GPIO PINCFG62 NCEPOL62 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG62_NCEPOL62                                                    */
  GPIO_PINCFG62_NCEPOL62_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG62_NCEPOL62_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG62_NCEPOL62_Enum;

/* ============================================  GPIO PINCFG62 NCESRC62 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG62_NCESRC62                                                    */
  GPIO_PINCFG62_NCESRC62_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG62_NCESRC62_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG62_NCESRC62_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG62_NCESRC62_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG62_NCESRC62_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG62_NCESRC62_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG62_NCESRC62_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG62_NCESRC62_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG62_NCESRC62_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG62_NCESRC62_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG62_NCESRC62_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG62_NCESRC62_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG62_NCESRC62_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG62_NCESRC62_Enum;

/* ===========================================  GPIO PINCFG62 PULLCFG62 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG62_PULLCFG62                                                   */
  GPIO_PINCFG62_PULLCFG62_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG62_PULLCFG62_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG62_PULLCFG62_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG62_PULLCFG62_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG62_PULLCFG62_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG62_PULLCFG62_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG62_PULLCFG62_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG62_PULLCFG62_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG62_PULLCFG62_Enum;

/* ==============================================  GPIO PINCFG62 DS62 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG62_DS62                                                        */
  GPIO_PINCFG62_DS62_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG62_DS62_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG62_DS62_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG62_DS62_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG62_DS62_Enum;

/* =============================================  GPIO PINCFG62 OUTCFG62 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG62_OUTCFG62                                                    */
  GPIO_PINCFG62_OUTCFG62_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG62_OUTCFG62_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG62_OUTCFG62_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG62_OUTCFG62_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG62_OUTCFG62_Enum;

/* =============================================  GPIO PINCFG62 IRPTEN62 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG62_IRPTEN62                                                    */
  GPIO_PINCFG62_IRPTEN62_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG62_IRPTEN62_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG62_IRPTEN62_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG62_IRPTEN62_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG62_IRPTEN62_Enum;

/* =============================================  GPIO PINCFG62 FNCSEL62 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG62_FNCSEL62                                                    */
  GPIO_PINCFG62_FNCSEL62_M6SDAWIR3     = 0,     /*!< M6SDAWIR3 : Serial I2C Master Data I/O (I2C Mode) Serial SPI
                                                     Master Data I/O (SPI 3 wire mode) (IOM 6)                                 */
  GPIO_PINCFG62_FNCSEL62_M6MOSI        = 1,     /*!< M6MOSI : Serial SPI Master MOSI output (IOM 6)                            */
  GPIO_PINCFG62_FNCSEL62_I2S1_DATA     = 2,     /*!< I2S1_DATA : Bidirectional I2S Data. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG62_FNCSEL62_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG62_FNCSEL62_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
  GPIO_PINCFG62_FNCSEL62_UART1RX       = 5,     /*!< UART1RX : UART receive input (UART 1)                                     */
  GPIO_PINCFG62_FNCSEL62_CT62          = 6,     /*!< CT62 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG62_FNCSEL62_NCE62         = 7,     /*!< NCE62 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG62_FNCSEL62_OBSBUS14      = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
  GPIO_PINCFG62_FNCSEL62_I2S1_SDOUT    = 9,     /*!< I2S1_SDOUT : I2S Data output (I2S Master/Slave 2)                         */
  GPIO_PINCFG62_FNCSEL62_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG62_FNCSEL62_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG62_FNCSEL62_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG62_FNCSEL62_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG62_FNCSEL62_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG62_FNCSEL62_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG62_FNCSEL62_Enum;

/* =======================================================  PINCFG63  ======================================================== */
/* ============================================  GPIO PINCFG63 NCEPOL63 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG63_NCEPOL63                                                    */
  GPIO_PINCFG63_NCEPOL63_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG63_NCEPOL63_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG63_NCEPOL63_Enum;

/* ============================================  GPIO PINCFG63 NCESRC63 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG63_NCESRC63                                                    */
  GPIO_PINCFG63_NCESRC63_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG63_NCESRC63_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG63_NCESRC63_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG63_NCESRC63_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG63_NCESRC63_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG63_NCESRC63_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG63_NCESRC63_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG63_NCESRC63_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG63_NCESRC63_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG63_NCESRC63_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG63_NCESRC63_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG63_NCESRC63_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG63_NCESRC63_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG63_NCESRC63_Enum;

/* ===========================================  GPIO PINCFG63 PULLCFG63 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG63_PULLCFG63                                                   */
  GPIO_PINCFG63_PULLCFG63_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG63_PULLCFG63_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG63_PULLCFG63_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG63_PULLCFG63_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG63_PULLCFG63_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG63_PULLCFG63_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG63_PULLCFG63_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG63_PULLCFG63_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG63_PULLCFG63_Enum;

/* ==============================================  GPIO PINCFG63 DS63 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG63_DS63                                                        */
  GPIO_PINCFG63_DS63_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG63_DS63_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG63_DS63_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG63_DS63_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG63_DS63_Enum;

/* =============================================  GPIO PINCFG63 OUTCFG63 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG63_OUTCFG63                                                    */
  GPIO_PINCFG63_OUTCFG63_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG63_OUTCFG63_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG63_OUTCFG63_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG63_OUTCFG63_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG63_OUTCFG63_Enum;

/* =============================================  GPIO PINCFG63 IRPTEN63 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG63_IRPTEN63                                                    */
  GPIO_PINCFG63_IRPTEN63_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG63_IRPTEN63_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG63_IRPTEN63_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG63_IRPTEN63_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG63_IRPTEN63_Enum;

/* =============================================  GPIO PINCFG63 FNCSEL63 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG63_FNCSEL63                                                    */
  GPIO_PINCFG63_FNCSEL63_M6MISO        = 0,     /*!< M6MISO : Serial SPI MASTER MISO input (IOM 6)                             */
  GPIO_PINCFG63_FNCSEL63_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
  GPIO_PINCFG63_FNCSEL63_I2S1_WS       = 2,     /*!< I2S1_WS : Bidirectional I2S L/R clock. Operates in output mode
                                                     in master mode and input mode for slave mode. (I2S Master/Slave
                                                     2)                                                                        */
  GPIO_PINCFG63_FNCSEL63_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG63_FNCSEL63_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
  GPIO_PINCFG63_FNCSEL63_UART3RX       = 5,     /*!< UART3RX : UART receive input (UART 3)                                     */
  GPIO_PINCFG63_FNCSEL63_CT63          = 6,     /*!< CT63 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG63_FNCSEL63_NCE63         = 7,     /*!< NCE63 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG63_FNCSEL63_OBSBUS15      = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
  GPIO_PINCFG63_FNCSEL63_DISP_TE       = 9,     /*!< DISP_TE : Display TE input                                                */
  GPIO_PINCFG63_FNCSEL63_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG63_FNCSEL63_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG63_FNCSEL63_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG63_FNCSEL63_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG63_FNCSEL63_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG63_FNCSEL63_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG63_FNCSEL63_Enum;

/* =======================================================  PINCFG64  ======================================================== */
/* ============================================  GPIO PINCFG64 NCEPOL64 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG64_NCEPOL64                                                    */
  GPIO_PINCFG64_NCEPOL64_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG64_NCEPOL64_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG64_NCEPOL64_Enum;

/* ============================================  GPIO PINCFG64 NCESRC64 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG64_NCESRC64                                                    */
  GPIO_PINCFG64_NCESRC64_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG64_NCESRC64_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG64_NCESRC64_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG64_NCESRC64_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG64_NCESRC64_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG64_NCESRC64_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG64_NCESRC64_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG64_NCESRC64_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG64_NCESRC64_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG64_NCESRC64_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG64_NCESRC64_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG64_NCESRC64_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG64_NCESRC64_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG64_NCESRC64_Enum;

/* ===========================================  GPIO PINCFG64 PULLCFG64 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG64_PULLCFG64                                                   */
  GPIO_PINCFG64_PULLCFG64_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG64_PULLCFG64_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG64_PULLCFG64_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG64_PULLCFG64_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG64_PULLCFG64_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG64_PULLCFG64_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG64_PULLCFG64_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG64_PULLCFG64_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG64_PULLCFG64_Enum;

/* ==============================================  GPIO PINCFG64 DS64 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG64_DS64                                                        */
  GPIO_PINCFG64_DS64_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG64_DS64_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG64_DS64_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG64_DS64_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG64_DS64_Enum;

/* =============================================  GPIO PINCFG64 OUTCFG64 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG64_OUTCFG64                                                    */
  GPIO_PINCFG64_OUTCFG64_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG64_OUTCFG64_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG64_OUTCFG64_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG64_OUTCFG64_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG64_OUTCFG64_Enum;

/* =============================================  GPIO PINCFG64 IRPTEN64 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG64_IRPTEN64                                                    */
  GPIO_PINCFG64_IRPTEN64_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG64_IRPTEN64_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG64_IRPTEN64_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG64_IRPTEN64_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG64_IRPTEN64_Enum;

/* =============================================  GPIO PINCFG64 FNCSEL64 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG64_FNCSEL64                                                    */
  GPIO_PINCFG64_FNCSEL64_MSPI0_0       = 0,     /*!< MSPI0_0 : MSPI Master 0 Interface Signal                                  */
  GPIO_PINCFG64_FNCSEL64_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
  GPIO_PINCFG64_FNCSEL64_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG64_FNCSEL64_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG64_FNCSEL64_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
  GPIO_PINCFG64_FNCSEL64_DISP_D0       = 5,     /*!< DISP_D0 : Display Data 0                                                  */
  GPIO_PINCFG64_FNCSEL64_CT64          = 6,     /*!< CT64 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG64_FNCSEL64_NCE64         = 7,     /*!< NCE64 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG64_FNCSEL64_OBSBUS0       = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
  GPIO_PINCFG64_FNCSEL64_I2S1_SDIN     = 9,     /*!< I2S1_SDIN : I2S Data input (I2S Master/Slave 2)                           */
  GPIO_PINCFG64_FNCSEL64_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG64_FNCSEL64_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG64_FNCSEL64_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG64_FNCSEL64_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG64_FNCSEL64_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG64_FNCSEL64_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG64_FNCSEL64_Enum;

/* =======================================================  PINCFG65  ======================================================== */
/* ============================================  GPIO PINCFG65 NCEPOL65 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG65_NCEPOL65                                                    */
  GPIO_PINCFG65_NCEPOL65_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG65_NCEPOL65_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG65_NCEPOL65_Enum;

/* ============================================  GPIO PINCFG65 NCESRC65 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG65_NCESRC65                                                    */
  GPIO_PINCFG65_NCESRC65_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG65_NCESRC65_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG65_NCESRC65_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG65_NCESRC65_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG65_NCESRC65_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG65_NCESRC65_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG65_NCESRC65_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG65_NCESRC65_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG65_NCESRC65_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG65_NCESRC65_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG65_NCESRC65_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG65_NCESRC65_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG65_NCESRC65_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG65_NCESRC65_Enum;

/* ===========================================  GPIO PINCFG65 PULLCFG65 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG65_PULLCFG65                                                   */
  GPIO_PINCFG65_PULLCFG65_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG65_PULLCFG65_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG65_PULLCFG65_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG65_PULLCFG65_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG65_PULLCFG65_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG65_PULLCFG65_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG65_PULLCFG65_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG65_PULLCFG65_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG65_PULLCFG65_Enum;

/* ==============================================  GPIO PINCFG65 DS65 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG65_DS65                                                        */
  GPIO_PINCFG65_DS65_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG65_DS65_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG65_DS65_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG65_DS65_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG65_DS65_Enum;

/* =============================================  GPIO PINCFG65 OUTCFG65 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG65_OUTCFG65                                                    */
  GPIO_PINCFG65_OUTCFG65_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG65_OUTCFG65_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG65_OUTCFG65_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG65_OUTCFG65_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG65_OUTCFG65_Enum;

/* =============================================  GPIO PINCFG65 IRPTEN65 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG65_IRPTEN65                                                    */
  GPIO_PINCFG65_IRPTEN65_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG65_IRPTEN65_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG65_IRPTEN65_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG65_IRPTEN65_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG65_IRPTEN65_Enum;

/* =============================================  GPIO PINCFG65 FNCSEL65 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG65_FNCSEL65                                                    */
  GPIO_PINCFG65_FNCSEL65_MSPI0_1       = 0,     /*!< MSPI0_1 : MSPI Master 0 Interface Signal                                  */
  GPIO_PINCFG65_FNCSEL65_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
  GPIO_PINCFG65_FNCSEL65_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG65_FNCSEL65_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG65_FNCSEL65_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
  GPIO_PINCFG65_FNCSEL65_DISP_D1       = 5,     /*!< DISP_D1 : Display Data 1                                                  */
  GPIO_PINCFG65_FNCSEL65_CT65          = 6,     /*!< CT65 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG65_FNCSEL65_NCE65         = 7,     /*!< NCE65 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG65_FNCSEL65_OBSBUS1       = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
  GPIO_PINCFG65_FNCSEL65_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG65_FNCSEL65_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG65_FNCSEL65_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG65_FNCSEL65_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG65_FNCSEL65_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG65_FNCSEL65_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG65_FNCSEL65_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG65_FNCSEL65_Enum;

/* =======================================================  PINCFG66  ======================================================== */
/* ============================================  GPIO PINCFG66 NCEPOL66 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG66_NCEPOL66                                                    */
  GPIO_PINCFG66_NCEPOL66_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG66_NCEPOL66_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG66_NCEPOL66_Enum;

/* ============================================  GPIO PINCFG66 NCESRC66 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG66_NCESRC66                                                    */
  GPIO_PINCFG66_NCESRC66_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG66_NCESRC66_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG66_NCESRC66_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG66_NCESRC66_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG66_NCESRC66_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG66_NCESRC66_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG66_NCESRC66_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG66_NCESRC66_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG66_NCESRC66_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG66_NCESRC66_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG66_NCESRC66_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG66_NCESRC66_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG66_NCESRC66_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG66_NCESRC66_Enum;

/* ===========================================  GPIO PINCFG66 PULLCFG66 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG66_PULLCFG66                                                   */
  GPIO_PINCFG66_PULLCFG66_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG66_PULLCFG66_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG66_PULLCFG66_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG66_PULLCFG66_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG66_PULLCFG66_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG66_PULLCFG66_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG66_PULLCFG66_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG66_PULLCFG66_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG66_PULLCFG66_Enum;

/* ==============================================  GPIO PINCFG66 DS66 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG66_DS66                                                        */
  GPIO_PINCFG66_DS66_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG66_DS66_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG66_DS66_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG66_DS66_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG66_DS66_Enum;

/* =============================================  GPIO PINCFG66 OUTCFG66 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG66_OUTCFG66                                                    */
  GPIO_PINCFG66_OUTCFG66_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG66_OUTCFG66_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG66_OUTCFG66_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG66_OUTCFG66_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG66_OUTCFG66_Enum;

/* =============================================  GPIO PINCFG66 IRPTEN66 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG66_IRPTEN66                                                    */
  GPIO_PINCFG66_IRPTEN66_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG66_IRPTEN66_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG66_IRPTEN66_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG66_IRPTEN66_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG66_IRPTEN66_Enum;

/* =============================================  GPIO PINCFG66 FNCSEL66 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG66_FNCSEL66                                                    */
  GPIO_PINCFG66_FNCSEL66_MSPI0_2       = 0,     /*!< MSPI0_2 : MSPI Master 0 Interface Signal                                  */
  GPIO_PINCFG66_FNCSEL66_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
  GPIO_PINCFG66_FNCSEL66_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG66_FNCSEL66_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG66_FNCSEL66_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
  GPIO_PINCFG66_FNCSEL66_DISP_D2       = 5,     /*!< DISP_D2 : Display Data 2                                                  */
  GPIO_PINCFG66_FNCSEL66_CT66          = 6,     /*!< CT66 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG66_FNCSEL66_NCE66         = 7,     /*!< NCE66 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG66_FNCSEL66_OBSBUS2       = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
  GPIO_PINCFG66_FNCSEL66_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG66_FNCSEL66_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG66_FNCSEL66_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG66_FNCSEL66_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG66_FNCSEL66_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG66_FNCSEL66_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG66_FNCSEL66_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG66_FNCSEL66_Enum;

/* =======================================================  PINCFG67  ======================================================== */
/* ============================================  GPIO PINCFG67 NCEPOL67 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG67_NCEPOL67                                                    */
  GPIO_PINCFG67_NCEPOL67_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG67_NCEPOL67_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG67_NCEPOL67_Enum;

/* ============================================  GPIO PINCFG67 NCESRC67 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG67_NCESRC67                                                    */
  GPIO_PINCFG67_NCESRC67_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG67_NCESRC67_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG67_NCESRC67_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG67_NCESRC67_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG67_NCESRC67_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG67_NCESRC67_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG67_NCESRC67_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG67_NCESRC67_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG67_NCESRC67_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG67_NCESRC67_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG67_NCESRC67_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG67_NCESRC67_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG67_NCESRC67_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG67_NCESRC67_Enum;

/* ===========================================  GPIO PINCFG67 PULLCFG67 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG67_PULLCFG67                                                   */
  GPIO_PINCFG67_PULLCFG67_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG67_PULLCFG67_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG67_PULLCFG67_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG67_PULLCFG67_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG67_PULLCFG67_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG67_PULLCFG67_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG67_PULLCFG67_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG67_PULLCFG67_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG67_PULLCFG67_Enum;

/* ==============================================  GPIO PINCFG67 DS67 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG67_DS67                                                        */
  GPIO_PINCFG67_DS67_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG67_DS67_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG67_DS67_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG67_DS67_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG67_DS67_Enum;

/* =============================================  GPIO PINCFG67 OUTCFG67 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG67_OUTCFG67                                                    */
  GPIO_PINCFG67_OUTCFG67_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG67_OUTCFG67_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG67_OUTCFG67_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG67_OUTCFG67_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG67_OUTCFG67_Enum;

/* =============================================  GPIO PINCFG67 IRPTEN67 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG67_IRPTEN67                                                    */
  GPIO_PINCFG67_IRPTEN67_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG67_IRPTEN67_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG67_IRPTEN67_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG67_IRPTEN67_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG67_IRPTEN67_Enum;

/* =============================================  GPIO PINCFG67 FNCSEL67 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG67_FNCSEL67                                                    */
  GPIO_PINCFG67_FNCSEL67_MSPI0_3       = 0,     /*!< MSPI0_3 : MSPI Master 0 Interface Signal                                  */
  GPIO_PINCFG67_FNCSEL67_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
  GPIO_PINCFG67_FNCSEL67_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG67_FNCSEL67_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG67_FNCSEL67_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
  GPIO_PINCFG67_FNCSEL67_DISP_D3       = 5,     /*!< DISP_D3 : Display Data 3                                                  */
  GPIO_PINCFG67_FNCSEL67_CT67          = 6,     /*!< CT67 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG67_FNCSEL67_NCE67         = 7,     /*!< NCE67 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG67_FNCSEL67_OBSBUS3       = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
  GPIO_PINCFG67_FNCSEL67_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG67_FNCSEL67_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG67_FNCSEL67_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG67_FNCSEL67_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG67_FNCSEL67_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG67_FNCSEL67_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG67_FNCSEL67_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG67_FNCSEL67_Enum;

/* =======================================================  PINCFG68  ======================================================== */
/* ============================================  GPIO PINCFG68 NCEPOL68 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG68_NCEPOL68                                                    */
  GPIO_PINCFG68_NCEPOL68_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG68_NCEPOL68_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG68_NCEPOL68_Enum;

/* ============================================  GPIO PINCFG68 NCESRC68 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG68_NCESRC68                                                    */
  GPIO_PINCFG68_NCESRC68_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG68_NCESRC68_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG68_NCESRC68_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG68_NCESRC68_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG68_NCESRC68_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG68_NCESRC68_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG68_NCESRC68_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG68_NCESRC68_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG68_NCESRC68_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG68_NCESRC68_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG68_NCESRC68_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG68_NCESRC68_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG68_NCESRC68_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG68_NCESRC68_Enum;

/* ===========================================  GPIO PINCFG68 PULLCFG68 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG68_PULLCFG68                                                   */
  GPIO_PINCFG68_PULLCFG68_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG68_PULLCFG68_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG68_PULLCFG68_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG68_PULLCFG68_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG68_PULLCFG68_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG68_PULLCFG68_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG68_PULLCFG68_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG68_PULLCFG68_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG68_PULLCFG68_Enum;

/* ==============================================  GPIO PINCFG68 DS68 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG68_DS68                                                        */
  GPIO_PINCFG68_DS68_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG68_DS68_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG68_DS68_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG68_DS68_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG68_DS68_Enum;

/* =============================================  GPIO PINCFG68 OUTCFG68 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG68_OUTCFG68                                                    */
  GPIO_PINCFG68_OUTCFG68_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG68_OUTCFG68_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG68_OUTCFG68_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG68_OUTCFG68_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG68_OUTCFG68_Enum;

/* =============================================  GPIO PINCFG68 IRPTEN68 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG68_IRPTEN68                                                    */
  GPIO_PINCFG68_IRPTEN68_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG68_IRPTEN68_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG68_IRPTEN68_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG68_IRPTEN68_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG68_IRPTEN68_Enum;

/* =============================================  GPIO PINCFG68 FNCSEL68 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG68_FNCSEL68                                                    */
  GPIO_PINCFG68_FNCSEL68_MSPI0_4       = 0,     /*!< MSPI0_4 : MSPI Master 0 Interface Signal                                  */
  GPIO_PINCFG68_FNCSEL68_SWO           = 1,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG68_FNCSEL68_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG68_FNCSEL68_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG68_FNCSEL68_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
  GPIO_PINCFG68_FNCSEL68_DISP_D4       = 5,     /*!< DISP_D4 : Display Data 4                                                  */
  GPIO_PINCFG68_FNCSEL68_CT68          = 6,     /*!< CT68 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG68_FNCSEL68_NCE68         = 7,     /*!< NCE68 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG68_FNCSEL68_OBSBUS4       = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
  GPIO_PINCFG68_FNCSEL68_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG68_FNCSEL68_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG68_FNCSEL68_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG68_FNCSEL68_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG68_FNCSEL68_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG68_FNCSEL68_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG68_FNCSEL68_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG68_FNCSEL68_Enum;

/* =======================================================  PINCFG69  ======================================================== */
/* ============================================  GPIO PINCFG69 NCEPOL69 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG69_NCEPOL69                                                    */
  GPIO_PINCFG69_NCEPOL69_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG69_NCEPOL69_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG69_NCEPOL69_Enum;

/* ============================================  GPIO PINCFG69 NCESRC69 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG69_NCESRC69                                                    */
  GPIO_PINCFG69_NCESRC69_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG69_NCESRC69_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG69_NCESRC69_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG69_NCESRC69_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG69_NCESRC69_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG69_NCESRC69_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG69_NCESRC69_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG69_NCESRC69_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG69_NCESRC69_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG69_NCESRC69_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG69_NCESRC69_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG69_NCESRC69_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG69_NCESRC69_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG69_NCESRC69_Enum;

/* ===========================================  GPIO PINCFG69 PULLCFG69 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG69_PULLCFG69                                                   */
  GPIO_PINCFG69_PULLCFG69_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG69_PULLCFG69_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG69_PULLCFG69_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG69_PULLCFG69_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG69_PULLCFG69_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG69_PULLCFG69_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG69_PULLCFG69_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG69_PULLCFG69_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG69_PULLCFG69_Enum;

/* ==============================================  GPIO PINCFG69 DS69 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG69_DS69                                                        */
  GPIO_PINCFG69_DS69_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG69_DS69_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG69_DS69_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG69_DS69_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG69_DS69_Enum;

/* =============================================  GPIO PINCFG69 OUTCFG69 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG69_OUTCFG69                                                    */
  GPIO_PINCFG69_OUTCFG69_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG69_OUTCFG69_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG69_OUTCFG69_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG69_OUTCFG69_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG69_OUTCFG69_Enum;

/* =============================================  GPIO PINCFG69 IRPTEN69 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG69_IRPTEN69                                                    */
  GPIO_PINCFG69_IRPTEN69_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG69_IRPTEN69_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG69_IRPTEN69_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG69_IRPTEN69_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG69_IRPTEN69_Enum;

/* =============================================  GPIO PINCFG69 FNCSEL69 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG69_FNCSEL69                                                    */
  GPIO_PINCFG69_FNCSEL69_MSPI0_5       = 0,     /*!< MSPI0_5 : MSPI Master 0 Interface Signal                                  */
  GPIO_PINCFG69_FNCSEL69_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
  GPIO_PINCFG69_FNCSEL69_SWO           = 2,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG69_FNCSEL69_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG69_FNCSEL69_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
  GPIO_PINCFG69_FNCSEL69_DISP_D5       = 5,     /*!< DISP_D5 : Display Data 5                                                  */
  GPIO_PINCFG69_FNCSEL69_CT69          = 6,     /*!< CT69 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG69_FNCSEL69_NCE69         = 7,     /*!< NCE69 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG69_FNCSEL69_OBSBUS5       = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
  GPIO_PINCFG69_FNCSEL69_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG69_FNCSEL69_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG69_FNCSEL69_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG69_FNCSEL69_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG69_FNCSEL69_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG69_FNCSEL69_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG69_FNCSEL69_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG69_FNCSEL69_Enum;

/* =======================================================  PINCFG70  ======================================================== */
/* ============================================  GPIO PINCFG70 NCEPOL70 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG70_NCEPOL70                                                    */
  GPIO_PINCFG70_NCEPOL70_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG70_NCEPOL70_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG70_NCEPOL70_Enum;

/* ============================================  GPIO PINCFG70 NCESRC70 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG70_NCESRC70                                                    */
  GPIO_PINCFG70_NCESRC70_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG70_NCESRC70_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG70_NCESRC70_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG70_NCESRC70_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG70_NCESRC70_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG70_NCESRC70_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG70_NCESRC70_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG70_NCESRC70_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG70_NCESRC70_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG70_NCESRC70_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG70_NCESRC70_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG70_NCESRC70_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG70_NCESRC70_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG70_NCESRC70_Enum;

/* ===========================================  GPIO PINCFG70 PULLCFG70 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG70_PULLCFG70                                                   */
  GPIO_PINCFG70_PULLCFG70_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG70_PULLCFG70_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG70_PULLCFG70_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG70_PULLCFG70_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG70_PULLCFG70_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG70_PULLCFG70_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG70_PULLCFG70_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG70_PULLCFG70_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG70_PULLCFG70_Enum;

/* ==============================================  GPIO PINCFG70 DS70 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG70_DS70                                                        */
  GPIO_PINCFG70_DS70_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG70_DS70_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG70_DS70_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG70_DS70_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG70_DS70_Enum;

/* =============================================  GPIO PINCFG70 OUTCFG70 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG70_OUTCFG70                                                    */
  GPIO_PINCFG70_OUTCFG70_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG70_OUTCFG70_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG70_OUTCFG70_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG70_OUTCFG70_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG70_OUTCFG70_Enum;

/* =============================================  GPIO PINCFG70 IRPTEN70 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG70_IRPTEN70                                                    */
  GPIO_PINCFG70_IRPTEN70_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG70_IRPTEN70_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG70_IRPTEN70_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG70_IRPTEN70_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG70_IRPTEN70_Enum;

/* =============================================  GPIO PINCFG70 FNCSEL70 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG70_FNCSEL70                                                    */
  GPIO_PINCFG70_FNCSEL70_MSPI0_6       = 0,     /*!< MSPI0_6 : MSPI Master 0 Interface Signal                                  */
  GPIO_PINCFG70_FNCSEL70_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
  GPIO_PINCFG70_FNCSEL70_SWTRACE0      = 2,     /*!< SWTRACE0 : Serial Wire Debug Trace Output 0                               */
  GPIO_PINCFG70_FNCSEL70_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG70_FNCSEL70_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
  GPIO_PINCFG70_FNCSEL70_DISP_D6       = 5,     /*!< DISP_D6 : Display Data 6                                                  */
  GPIO_PINCFG70_FNCSEL70_CT70          = 6,     /*!< CT70 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG70_FNCSEL70_NCE70         = 7,     /*!< NCE70 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG70_FNCSEL70_OBSBUS6       = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
  GPIO_PINCFG70_FNCSEL70_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG70_FNCSEL70_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG70_FNCSEL70_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG70_FNCSEL70_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG70_FNCSEL70_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG70_FNCSEL70_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG70_FNCSEL70_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG70_FNCSEL70_Enum;

/* =======================================================  PINCFG71  ======================================================== */
/* ============================================  GPIO PINCFG71 NCEPOL71 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG71_NCEPOL71                                                    */
  GPIO_PINCFG71_NCEPOL71_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG71_NCEPOL71_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG71_NCEPOL71_Enum;

/* ============================================  GPIO PINCFG71 NCESRC71 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG71_NCESRC71                                                    */
  GPIO_PINCFG71_NCESRC71_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG71_NCESRC71_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG71_NCESRC71_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG71_NCESRC71_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG71_NCESRC71_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG71_NCESRC71_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG71_NCESRC71_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG71_NCESRC71_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG71_NCESRC71_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG71_NCESRC71_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG71_NCESRC71_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG71_NCESRC71_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG71_NCESRC71_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG71_NCESRC71_Enum;

/* ===========================================  GPIO PINCFG71 PULLCFG71 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG71_PULLCFG71                                                   */
  GPIO_PINCFG71_PULLCFG71_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG71_PULLCFG71_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG71_PULLCFG71_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG71_PULLCFG71_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG71_PULLCFG71_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG71_PULLCFG71_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG71_PULLCFG71_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG71_PULLCFG71_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG71_PULLCFG71_Enum;

/* ==============================================  GPIO PINCFG71 DS71 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG71_DS71                                                        */
  GPIO_PINCFG71_DS71_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG71_DS71_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG71_DS71_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG71_DS71_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG71_DS71_Enum;

/* =============================================  GPIO PINCFG71 OUTCFG71 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG71_OUTCFG71                                                    */
  GPIO_PINCFG71_OUTCFG71_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG71_OUTCFG71_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG71_OUTCFG71_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG71_OUTCFG71_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG71_OUTCFG71_Enum;

/* =============================================  GPIO PINCFG71 IRPTEN71 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG71_IRPTEN71                                                    */
  GPIO_PINCFG71_IRPTEN71_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG71_IRPTEN71_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG71_IRPTEN71_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG71_IRPTEN71_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG71_IRPTEN71_Enum;

/* =============================================  GPIO PINCFG71 FNCSEL71 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG71_FNCSEL71                                                    */
  GPIO_PINCFG71_FNCSEL71_MSPI0_7       = 0,     /*!< MSPI0_7 : MSPI Master 0 Interface Signal                                  */
  GPIO_PINCFG71_FNCSEL71_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
  GPIO_PINCFG71_FNCSEL71_SWTRACE1      = 2,     /*!< SWTRACE1 : Serial Wire Debug Trace Output 1                               */
  GPIO_PINCFG71_FNCSEL71_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG71_FNCSEL71_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
  GPIO_PINCFG71_FNCSEL71_DISP_D7       = 5,     /*!< DISP_D7 : Display Data 7                                                  */
  GPIO_PINCFG71_FNCSEL71_CT71          = 6,     /*!< CT71 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG71_FNCSEL71_NCE71         = 7,     /*!< NCE71 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG71_FNCSEL71_OBSBUS7       = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
  GPIO_PINCFG71_FNCSEL71_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG71_FNCSEL71_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG71_FNCSEL71_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG71_FNCSEL71_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG71_FNCSEL71_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG71_FNCSEL71_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG71_FNCSEL71_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG71_FNCSEL71_Enum;

/* =======================================================  PINCFG72  ======================================================== */
/* ============================================  GPIO PINCFG72 NCEPOL72 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG72_NCEPOL72                                                    */
  GPIO_PINCFG72_NCEPOL72_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG72_NCEPOL72_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG72_NCEPOL72_Enum;

/* ============================================  GPIO PINCFG72 NCESRC72 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG72_NCESRC72                                                    */
  GPIO_PINCFG72_NCESRC72_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG72_NCESRC72_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG72_NCESRC72_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG72_NCESRC72_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG72_NCESRC72_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG72_NCESRC72_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG72_NCESRC72_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG72_NCESRC72_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG72_NCESRC72_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG72_NCESRC72_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG72_NCESRC72_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG72_NCESRC72_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG72_NCESRC72_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG72_NCESRC72_Enum;

/* ===========================================  GPIO PINCFG72 PULLCFG72 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG72_PULLCFG72                                                   */
  GPIO_PINCFG72_PULLCFG72_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG72_PULLCFG72_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG72_PULLCFG72_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG72_PULLCFG72_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG72_PULLCFG72_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG72_PULLCFG72_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG72_PULLCFG72_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG72_PULLCFG72_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG72_PULLCFG72_Enum;

/* ==============================================  GPIO PINCFG72 DS72 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG72_DS72                                                        */
  GPIO_PINCFG72_DS72_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG72_DS72_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG72_DS72_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG72_DS72_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG72_DS72_Enum;

/* =============================================  GPIO PINCFG72 OUTCFG72 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG72_OUTCFG72                                                    */
  GPIO_PINCFG72_OUTCFG72_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG72_OUTCFG72_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG72_OUTCFG72_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG72_OUTCFG72_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG72_OUTCFG72_Enum;

/* =============================================  GPIO PINCFG72 IRPTEN72 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG72_IRPTEN72                                                    */
  GPIO_PINCFG72_IRPTEN72_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG72_IRPTEN72_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG72_IRPTEN72_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG72_IRPTEN72_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG72_IRPTEN72_Enum;

/* =============================================  GPIO PINCFG72 FNCSEL72 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG72_FNCSEL72                                                    */
  GPIO_PINCFG72_FNCSEL72_MSPI0_8       = 0,     /*!< MSPI0_8 : MSPI Master 0 Interface Signal                                  */
  GPIO_PINCFG72_FNCSEL72_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
  GPIO_PINCFG72_FNCSEL72_SWTRACE2      = 2,     /*!< SWTRACE2 : Serial Wire Debug Trace Output 2                               */
  GPIO_PINCFG72_FNCSEL72_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG72_FNCSEL72_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
  GPIO_PINCFG72_FNCSEL72_DISP_D8       = 5,     /*!< DISP_D8 : Display Data 8                                                  */
  GPIO_PINCFG72_FNCSEL72_CT72          = 6,     /*!< CT72 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG72_FNCSEL72_NCE72         = 7,     /*!< NCE72 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG72_FNCSEL72_OBSBUS8       = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
  GPIO_PINCFG72_FNCSEL72_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG72_FNCSEL72_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG72_FNCSEL72_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG72_FNCSEL72_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG72_FNCSEL72_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG72_FNCSEL72_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG72_FNCSEL72_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG72_FNCSEL72_Enum;

/* =======================================================  PINCFG73  ======================================================== */
/* ============================================  GPIO PINCFG73 NCEPOL73 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG73_NCEPOL73                                                    */
  GPIO_PINCFG73_NCEPOL73_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG73_NCEPOL73_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG73_NCEPOL73_Enum;

/* ============================================  GPIO PINCFG73 NCESRC73 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG73_NCESRC73                                                    */
  GPIO_PINCFG73_NCESRC73_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG73_NCESRC73_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG73_NCESRC73_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG73_NCESRC73_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG73_NCESRC73_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG73_NCESRC73_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG73_NCESRC73_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG73_NCESRC73_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG73_NCESRC73_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG73_NCESRC73_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG73_NCESRC73_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG73_NCESRC73_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG73_NCESRC73_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG73_NCESRC73_Enum;

/* ===========================================  GPIO PINCFG73 PULLCFG73 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG73_PULLCFG73                                                   */
  GPIO_PINCFG73_PULLCFG73_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG73_PULLCFG73_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG73_PULLCFG73_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG73_PULLCFG73_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG73_PULLCFG73_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG73_PULLCFG73_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG73_PULLCFG73_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG73_PULLCFG73_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG73_PULLCFG73_Enum;

/* ==============================================  GPIO PINCFG73 DS73 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG73_DS73                                                        */
  GPIO_PINCFG73_DS73_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG73_DS73_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG73_DS73_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG73_DS73_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG73_DS73_Enum;

/* =============================================  GPIO PINCFG73 OUTCFG73 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG73_OUTCFG73                                                    */
  GPIO_PINCFG73_OUTCFG73_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG73_OUTCFG73_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG73_OUTCFG73_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG73_OUTCFG73_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG73_OUTCFG73_Enum;

/* =============================================  GPIO PINCFG73 IRPTEN73 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG73_IRPTEN73                                                    */
  GPIO_PINCFG73_IRPTEN73_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG73_IRPTEN73_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG73_IRPTEN73_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG73_IRPTEN73_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG73_IRPTEN73_Enum;

/* =============================================  GPIO PINCFG73 FNCSEL73 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG73_FNCSEL73                                                    */
  GPIO_PINCFG73_FNCSEL73_MSPI0_9       = 0,     /*!< MSPI0_9 : MSPI Master 0 Interface Signal                                  */
  GPIO_PINCFG73_FNCSEL73_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG73_FNCSEL73_SWTRACE3      = 2,     /*!< SWTRACE3 : Serial Wire Debug Trace Output 3                               */
  GPIO_PINCFG73_FNCSEL73_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG73_FNCSEL73_UART2TX       = 4,     /*!< UART2TX : UART transmit output (UART 2)                                   */
  GPIO_PINCFG73_FNCSEL73_DISP_D9       = 5,     /*!< DISP_D9 : Display Data 9                                                  */
  GPIO_PINCFG73_FNCSEL73_CT73          = 6,     /*!< CT73 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG73_FNCSEL73_NCE73         = 7,     /*!< NCE73 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG73_FNCSEL73_OBSBUS9       = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
  GPIO_PINCFG73_FNCSEL73_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG73_FNCSEL73_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG73_FNCSEL73_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG73_FNCSEL73_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG73_FNCSEL73_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG73_FNCSEL73_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG73_FNCSEL73_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG73_FNCSEL73_Enum;

/* =======================================================  PINCFG74  ======================================================== */
/* ============================================  GPIO PINCFG74 NCEPOL74 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG74_NCEPOL74                                                    */
  GPIO_PINCFG74_NCEPOL74_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG74_NCEPOL74_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG74_NCEPOL74_Enum;

/* ============================================  GPIO PINCFG74 NCESRC74 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG74_NCESRC74                                                    */
  GPIO_PINCFG74_NCESRC74_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG74_NCESRC74_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG74_NCESRC74_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG74_NCESRC74_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG74_NCESRC74_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG74_NCESRC74_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG74_NCESRC74_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG74_NCESRC74_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG74_NCESRC74_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG74_NCESRC74_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG74_NCESRC74_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG74_NCESRC74_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG74_NCESRC74_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG74_NCESRC74_Enum;

/* ===========================================  GPIO PINCFG74 PULLCFG74 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG74_PULLCFG74                                                   */
  GPIO_PINCFG74_PULLCFG74_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG74_PULLCFG74_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG74_PULLCFG74_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG74_PULLCFG74_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG74_PULLCFG74_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG74_PULLCFG74_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG74_PULLCFG74_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG74_PULLCFG74_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG74_PULLCFG74_Enum;

/* ==============================================  GPIO PINCFG74 DS74 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG74_DS74                                                        */
  GPIO_PINCFG74_DS74_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG74_DS74_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG74_DS74_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG74_DS74_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG74_DS74_Enum;

/* =============================================  GPIO PINCFG74 OUTCFG74 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG74_OUTCFG74                                                    */
  GPIO_PINCFG74_OUTCFG74_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG74_OUTCFG74_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG74_OUTCFG74_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG74_OUTCFG74_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG74_OUTCFG74_Enum;

/* =============================================  GPIO PINCFG74 IRPTEN74 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG74_IRPTEN74                                                    */
  GPIO_PINCFG74_IRPTEN74_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG74_IRPTEN74_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG74_IRPTEN74_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG74_IRPTEN74_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG74_IRPTEN74_Enum;

/* =============================================  GPIO PINCFG74 FNCSEL74 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG74_FNCSEL74                                                    */
  GPIO_PINCFG74_FNCSEL74_MSPI2_0       = 0,     /*!< MSPI2_0 : MSPI Master 2 Interface Signal                                  */
  GPIO_PINCFG74_FNCSEL74_DISP_QSPI_D0_OUT = 1,  /*!< DISP_QSPI_D0_OUT : Display SPI Data0                                      */
  GPIO_PINCFG74_FNCSEL74_DISP_QSPI_D0  = 2,     /*!< DISP_QSPI_D0 : Display SPI Data0                                          */
  GPIO_PINCFG74_FNCSEL74_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG74_FNCSEL74_UART0RX       = 4,     /*!< UART0RX : UART receive input (UART 0)                                     */
  GPIO_PINCFG74_FNCSEL74_DISP_D10      = 5,     /*!< DISP_D10 : Display Data 10                                                */
  GPIO_PINCFG74_FNCSEL74_CT74          = 6,     /*!< CT74 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG74_FNCSEL74_NCE74         = 7,     /*!< NCE74 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG74_FNCSEL74_OBSBUS10      = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
  GPIO_PINCFG74_FNCSEL74_DISP_SPI_SD   = 9,     /*!< DISP_SPI_SD : Display SPI Data Out                                        */
  GPIO_PINCFG74_FNCSEL74_DISP_SPI_SDO  = 10,    /*!< DISP_SPI_SDO : Display SPI Data Out                                       */
  GPIO_PINCFG74_FNCSEL74_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG74_FNCSEL74_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG74_FNCSEL74_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG74_FNCSEL74_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG74_FNCSEL74_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG74_FNCSEL74_Enum;

/* =======================================================  PINCFG75  ======================================================== */
/* ============================================  GPIO PINCFG75 NCEPOL75 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG75_NCEPOL75                                                    */
  GPIO_PINCFG75_NCEPOL75_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG75_NCEPOL75_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG75_NCEPOL75_Enum;

/* ============================================  GPIO PINCFG75 NCESRC75 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG75_NCESRC75                                                    */
  GPIO_PINCFG75_NCESRC75_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG75_NCESRC75_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG75_NCESRC75_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG75_NCESRC75_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG75_NCESRC75_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG75_NCESRC75_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG75_NCESRC75_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG75_NCESRC75_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG75_NCESRC75_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG75_NCESRC75_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG75_NCESRC75_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG75_NCESRC75_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG75_NCESRC75_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG75_NCESRC75_Enum;

/* ===========================================  GPIO PINCFG75 PULLCFG75 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG75_PULLCFG75                                                   */
  GPIO_PINCFG75_PULLCFG75_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG75_PULLCFG75_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG75_PULLCFG75_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG75_PULLCFG75_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG75_PULLCFG75_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG75_PULLCFG75_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG75_PULLCFG75_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG75_PULLCFG75_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG75_PULLCFG75_Enum;

/* ==============================================  GPIO PINCFG75 DS75 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG75_DS75                                                        */
  GPIO_PINCFG75_DS75_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG75_DS75_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG75_DS75_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG75_DS75_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG75_DS75_Enum;

/* =============================================  GPIO PINCFG75 OUTCFG75 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG75_OUTCFG75                                                    */
  GPIO_PINCFG75_OUTCFG75_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG75_OUTCFG75_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG75_OUTCFG75_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG75_OUTCFG75_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG75_OUTCFG75_Enum;

/* =============================================  GPIO PINCFG75 IRPTEN75 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG75_IRPTEN75                                                    */
  GPIO_PINCFG75_IRPTEN75_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG75_IRPTEN75_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG75_IRPTEN75_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG75_IRPTEN75_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG75_IRPTEN75_Enum;

/* =============================================  GPIO PINCFG75 FNCSEL75 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG75_FNCSEL75                                                    */
  GPIO_PINCFG75_FNCSEL75_MSPI2_1       = 0,     /*!< MSPI2_1 : MSPI Master 2 Interface Signal                                  */
  GPIO_PINCFG75_FNCSEL75_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
  GPIO_PINCFG75_FNCSEL75_DISP_QSPI_D1  = 2,     /*!< DISP_QSPI_D1 : Display SPI Data1                                          */
  GPIO_PINCFG75_FNCSEL75_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG75_FNCSEL75_UART2RX       = 4,     /*!< UART2RX : UART receive input (UART 2)                                     */
  GPIO_PINCFG75_FNCSEL75_DISP_D11      = 5,     /*!< DISP_D11 : Display Data 11                                                */
  GPIO_PINCFG75_FNCSEL75_CT75          = 6,     /*!< CT75 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG75_FNCSEL75_NCE75         = 7,     /*!< NCE75 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG75_FNCSEL75_OBSBUS11      = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
  GPIO_PINCFG75_FNCSEL75_DISP_SPI_DCX  = 9,     /*!< DISP_SPI_DCX : Display SPI DCx                                            */
  GPIO_PINCFG75_FNCSEL75_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG75_FNCSEL75_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG75_FNCSEL75_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG75_FNCSEL75_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG75_FNCSEL75_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG75_FNCSEL75_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG75_FNCSEL75_Enum;

/* =======================================================  PINCFG76  ======================================================== */
/* ============================================  GPIO PINCFG76 NCEPOL76 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG76_NCEPOL76                                                    */
  GPIO_PINCFG76_NCEPOL76_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG76_NCEPOL76_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG76_NCEPOL76_Enum;

/* ============================================  GPIO PINCFG76 NCESRC76 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG76_NCESRC76                                                    */
  GPIO_PINCFG76_NCESRC76_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG76_NCESRC76_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG76_NCESRC76_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG76_NCESRC76_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG76_NCESRC76_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG76_NCESRC76_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG76_NCESRC76_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG76_NCESRC76_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG76_NCESRC76_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG76_NCESRC76_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG76_NCESRC76_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG76_NCESRC76_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG76_NCESRC76_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG76_NCESRC76_Enum;

/* ===========================================  GPIO PINCFG76 PULLCFG76 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG76_PULLCFG76                                                   */
  GPIO_PINCFG76_PULLCFG76_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG76_PULLCFG76_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG76_PULLCFG76_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG76_PULLCFG76_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG76_PULLCFG76_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG76_PULLCFG76_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG76_PULLCFG76_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG76_PULLCFG76_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG76_PULLCFG76_Enum;

/* ==============================================  GPIO PINCFG76 DS76 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG76_DS76                                                        */
  GPIO_PINCFG76_DS76_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG76_DS76_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG76_DS76_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG76_DS76_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG76_DS76_Enum;

/* =============================================  GPIO PINCFG76 OUTCFG76 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG76_OUTCFG76                                                    */
  GPIO_PINCFG76_OUTCFG76_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG76_OUTCFG76_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG76_OUTCFG76_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG76_OUTCFG76_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG76_OUTCFG76_Enum;

/* =============================================  GPIO PINCFG76 IRPTEN76 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG76_IRPTEN76                                                    */
  GPIO_PINCFG76_IRPTEN76_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG76_IRPTEN76_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG76_IRPTEN76_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG76_IRPTEN76_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG76_IRPTEN76_Enum;

/* =============================================  GPIO PINCFG76 FNCSEL76 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG76_FNCSEL76                                                    */
  GPIO_PINCFG76_FNCSEL76_MSPI2_2       = 0,     /*!< MSPI2_2 : MSPI Master 2 Interface Signal                                  */
  GPIO_PINCFG76_FNCSEL76_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
  GPIO_PINCFG76_FNCSEL76_DISP_QSPI_D2  = 2,     /*!< DISP_QSPI_D2 : Display SPI Data2                                          */
  GPIO_PINCFG76_FNCSEL76_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG76_FNCSEL76_UART0RTS      = 4,     /*!< UART0RTS : UART Request to Send (RTS) (UART 0)                            */
  GPIO_PINCFG76_FNCSEL76_DISP_D12      = 5,     /*!< DISP_D12 : Display Data 12                                                */
  GPIO_PINCFG76_FNCSEL76_CT76          = 6,     /*!< CT76 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG76_FNCSEL76_NCE76         = 7,     /*!< NCE76 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG76_FNCSEL76_OBSBUS12      = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
  GPIO_PINCFG76_FNCSEL76_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG76_FNCSEL76_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG76_FNCSEL76_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG76_FNCSEL76_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG76_FNCSEL76_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG76_FNCSEL76_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG76_FNCSEL76_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG76_FNCSEL76_Enum;

/* =======================================================  PINCFG77  ======================================================== */
/* ============================================  GPIO PINCFG77 NCEPOL77 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG77_NCEPOL77                                                    */
  GPIO_PINCFG77_NCEPOL77_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG77_NCEPOL77_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG77_NCEPOL77_Enum;

/* ============================================  GPIO PINCFG77 NCESRC77 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG77_NCESRC77                                                    */
  GPIO_PINCFG77_NCESRC77_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG77_NCESRC77_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG77_NCESRC77_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG77_NCESRC77_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG77_NCESRC77_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG77_NCESRC77_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG77_NCESRC77_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG77_NCESRC77_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG77_NCESRC77_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG77_NCESRC77_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG77_NCESRC77_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG77_NCESRC77_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG77_NCESRC77_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG77_NCESRC77_Enum;

/* ===========================================  GPIO PINCFG77 PULLCFG77 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG77_PULLCFG77                                                   */
  GPIO_PINCFG77_PULLCFG77_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG77_PULLCFG77_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG77_PULLCFG77_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG77_PULLCFG77_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG77_PULLCFG77_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG77_PULLCFG77_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG77_PULLCFG77_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG77_PULLCFG77_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG77_PULLCFG77_Enum;

/* ==============================================  GPIO PINCFG77 DS77 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG77_DS77                                                        */
  GPIO_PINCFG77_DS77_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG77_DS77_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG77_DS77_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG77_DS77_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG77_DS77_Enum;

/* =============================================  GPIO PINCFG77 OUTCFG77 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG77_OUTCFG77                                                    */
  GPIO_PINCFG77_OUTCFG77_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG77_OUTCFG77_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG77_OUTCFG77_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG77_OUTCFG77_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG77_OUTCFG77_Enum;

/* =============================================  GPIO PINCFG77 IRPTEN77 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG77_IRPTEN77                                                    */
  GPIO_PINCFG77_IRPTEN77_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG77_IRPTEN77_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG77_IRPTEN77_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG77_IRPTEN77_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG77_IRPTEN77_Enum;

/* =============================================  GPIO PINCFG77 FNCSEL77 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG77_FNCSEL77                                                    */
  GPIO_PINCFG77_FNCSEL77_MSPI2_3       = 0,     /*!< MSPI2_3 : MSPI Master 2 Interface Signal                                  */
  GPIO_PINCFG77_FNCSEL77_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG77_FNCSEL77_DISP_QSPI_D3  = 2,     /*!< DISP_QSPI_D3 : Display SPI Data3                                          */
  GPIO_PINCFG77_FNCSEL77_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG77_FNCSEL77_UART0CTS      = 4,     /*!< UART0CTS : UART Clear to Send (CTS) (UART 0)                              */
  GPIO_PINCFG77_FNCSEL77_DISP_D13      = 5,     /*!< DISP_D13 : Display Data 13                                                */
  GPIO_PINCFG77_FNCSEL77_CT77          = 6,     /*!< CT77 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG77_FNCSEL77_NCE77         = 7,     /*!< NCE77 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG77_FNCSEL77_OBSBUS13      = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
  GPIO_PINCFG77_FNCSEL77_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG77_FNCSEL77_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG77_FNCSEL77_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG77_FNCSEL77_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG77_FNCSEL77_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG77_FNCSEL77_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG77_FNCSEL77_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG77_FNCSEL77_Enum;

/* =======================================================  PINCFG78  ======================================================== */
/* ============================================  GPIO PINCFG78 NCEPOL78 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG78_NCEPOL78                                                    */
  GPIO_PINCFG78_NCEPOL78_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG78_NCEPOL78_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG78_NCEPOL78_Enum;

/* ============================================  GPIO PINCFG78 NCESRC78 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG78_NCESRC78                                                    */
  GPIO_PINCFG78_NCESRC78_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG78_NCESRC78_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG78_NCESRC78_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG78_NCESRC78_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG78_NCESRC78_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG78_NCESRC78_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG78_NCESRC78_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG78_NCESRC78_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG78_NCESRC78_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG78_NCESRC78_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG78_NCESRC78_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG78_NCESRC78_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG78_NCESRC78_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG78_NCESRC78_Enum;

/* ===========================================  GPIO PINCFG78 PULLCFG78 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG78_PULLCFG78                                                   */
  GPIO_PINCFG78_PULLCFG78_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG78_PULLCFG78_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG78_PULLCFG78_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG78_PULLCFG78_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG78_PULLCFG78_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG78_PULLCFG78_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG78_PULLCFG78_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG78_PULLCFG78_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG78_PULLCFG78_Enum;

/* ==============================================  GPIO PINCFG78 DS78 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG78_DS78                                                        */
  GPIO_PINCFG78_DS78_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG78_DS78_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG78_DS78_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG78_DS78_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG78_DS78_Enum;

/* =============================================  GPIO PINCFG78 OUTCFG78 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG78_OUTCFG78                                                    */
  GPIO_PINCFG78_OUTCFG78_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG78_OUTCFG78_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG78_OUTCFG78_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG78_OUTCFG78_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG78_OUTCFG78_Enum;

/* =============================================  GPIO PINCFG78 IRPTEN78 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG78_IRPTEN78                                                    */
  GPIO_PINCFG78_IRPTEN78_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG78_IRPTEN78_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG78_IRPTEN78_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG78_IRPTEN78_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG78_IRPTEN78_Enum;

/* =============================================  GPIO PINCFG78 FNCSEL78 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG78_FNCSEL78                                                    */
  GPIO_PINCFG78_FNCSEL78_MSPI2_4       = 0,     /*!< MSPI2_4 : MSPI Master 2 Interface Signal                                  */
  GPIO_PINCFG78_FNCSEL78_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG78_FNCSEL78_DISP_QSPI_SCK = 2,     /*!< DISP_QSPI_SCK : Display SPI CLK                                           */
  GPIO_PINCFG78_FNCSEL78_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG78_FNCSEL78_UART0TX       = 4,     /*!< UART0TX : UART transmit output (UART 0)                                   */
  GPIO_PINCFG78_FNCSEL78_DISP_D14      = 5,     /*!< DISP_D14 : Display Data 14                                                */
  GPIO_PINCFG78_FNCSEL78_CT78          = 6,     /*!< CT78 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG78_FNCSEL78_NCE78         = 7,     /*!< NCE78 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG78_FNCSEL78_OBSBUS14      = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
  GPIO_PINCFG78_FNCSEL78_DISP_SPI_SCK  = 9,     /*!< DISP_SPI_SCK : Display SPI Clock                                          */
  GPIO_PINCFG78_FNCSEL78_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG78_FNCSEL78_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG78_FNCSEL78_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG78_FNCSEL78_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG78_FNCSEL78_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG78_FNCSEL78_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG78_FNCSEL78_Enum;

/* =======================================================  PINCFG79  ======================================================== */
/* ============================================  GPIO PINCFG79 NCEPOL79 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG79_NCEPOL79                                                    */
  GPIO_PINCFG79_NCEPOL79_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG79_NCEPOL79_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG79_NCEPOL79_Enum;

/* ============================================  GPIO PINCFG79 NCESRC79 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG79_NCESRC79                                                    */
  GPIO_PINCFG79_NCESRC79_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG79_NCESRC79_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG79_NCESRC79_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG79_NCESRC79_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG79_NCESRC79_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG79_NCESRC79_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG79_NCESRC79_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG79_NCESRC79_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG79_NCESRC79_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG79_NCESRC79_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG79_NCESRC79_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG79_NCESRC79_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG79_NCESRC79_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG79_NCESRC79_Enum;

/* ===========================================  GPIO PINCFG79 PULLCFG79 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG79_PULLCFG79                                                   */
  GPIO_PINCFG79_PULLCFG79_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG79_PULLCFG79_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG79_PULLCFG79_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG79_PULLCFG79_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG79_PULLCFG79_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG79_PULLCFG79_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG79_PULLCFG79_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG79_PULLCFG79_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG79_PULLCFG79_Enum;

/* ==============================================  GPIO PINCFG79 DS79 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG79_DS79                                                        */
  GPIO_PINCFG79_DS79_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG79_DS79_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG79_DS79_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG79_DS79_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG79_DS79_Enum;

/* =============================================  GPIO PINCFG79 OUTCFG79 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG79_OUTCFG79                                                    */
  GPIO_PINCFG79_OUTCFG79_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG79_OUTCFG79_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG79_OUTCFG79_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG79_OUTCFG79_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG79_OUTCFG79_Enum;

/* =============================================  GPIO PINCFG79 IRPTEN79 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG79_IRPTEN79                                                    */
  GPIO_PINCFG79_IRPTEN79_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG79_IRPTEN79_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG79_IRPTEN79_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG79_IRPTEN79_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG79_IRPTEN79_Enum;

/* =============================================  GPIO PINCFG79 FNCSEL79 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG79_FNCSEL79                                                    */
  GPIO_PINCFG79_FNCSEL79_MSPI2_5       = 0,     /*!< MSPI2_5 : MSPI Master 2 Interface Signal                                  */
  GPIO_PINCFG79_FNCSEL79_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG79_FNCSEL79_SDIF_DAT4     = 2,     /*!< SDIF_DAT4 : SD/SDIO/MMC Data4 pin                                         */
  GPIO_PINCFG79_FNCSEL79_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG79_FNCSEL79_SWO           = 4,     /*!< SWO : Serial Wire Output                                                  */
  GPIO_PINCFG79_FNCSEL79_DISP_VS       = 5,     /*!< DISP_VS : Display RGB VSYNC                                               */
  GPIO_PINCFG79_FNCSEL79_CT79          = 6,     /*!< CT79 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG79_FNCSEL79_NCE79         = 7,     /*!< NCE79 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG79_FNCSEL79_OBSBUS15      = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
  GPIO_PINCFG79_FNCSEL79_DISP_SPI_SDI  = 9,     /*!< DISP_SPI_SDI : Display SPI Data IN                                        */
  GPIO_PINCFG79_FNCSEL79_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG79_FNCSEL79_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG79_FNCSEL79_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG79_FNCSEL79_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG79_FNCSEL79_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG79_FNCSEL79_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG79_FNCSEL79_Enum;

/* =======================================================  PINCFG80  ======================================================== */
/* ============================================  GPIO PINCFG80 NCEPOL80 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG80_NCEPOL80                                                    */
  GPIO_PINCFG80_NCEPOL80_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG80_NCEPOL80_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG80_NCEPOL80_Enum;

/* ============================================  GPIO PINCFG80 NCESRC80 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG80_NCESRC80                                                    */
  GPIO_PINCFG80_NCESRC80_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG80_NCESRC80_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG80_NCESRC80_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG80_NCESRC80_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG80_NCESRC80_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG80_NCESRC80_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG80_NCESRC80_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG80_NCESRC80_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG80_NCESRC80_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG80_NCESRC80_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG80_NCESRC80_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG80_NCESRC80_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG80_NCESRC80_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG80_NCESRC80_Enum;

/* ===========================================  GPIO PINCFG80 PULLCFG80 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG80_PULLCFG80                                                   */
  GPIO_PINCFG80_PULLCFG80_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG80_PULLCFG80_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG80_PULLCFG80_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG80_PULLCFG80_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG80_PULLCFG80_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG80_PULLCFG80_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG80_PULLCFG80_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG80_PULLCFG80_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG80_PULLCFG80_Enum;

/* ==============================================  GPIO PINCFG80 DS80 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG80_DS80                                                        */
  GPIO_PINCFG80_DS80_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG80_DS80_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG80_DS80_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG80_DS80_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG80_DS80_Enum;

/* =============================================  GPIO PINCFG80 OUTCFG80 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG80_OUTCFG80                                                    */
  GPIO_PINCFG80_OUTCFG80_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG80_OUTCFG80_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG80_OUTCFG80_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG80_OUTCFG80_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG80_OUTCFG80_Enum;

/* =============================================  GPIO PINCFG80 IRPTEN80 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG80_IRPTEN80                                                    */
  GPIO_PINCFG80_IRPTEN80_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG80_IRPTEN80_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG80_IRPTEN80_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG80_IRPTEN80_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG80_IRPTEN80_Enum;

/* =============================================  GPIO PINCFG80 FNCSEL80 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG80_FNCSEL80                                                    */
  GPIO_PINCFG80_FNCSEL80_MSPI2_6       = 0,     /*!< MSPI2_6 : MSPI Master 2 Interface Signal                                  */
  GPIO_PINCFG80_FNCSEL80_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
  GPIO_PINCFG80_FNCSEL80_SDIF_DAT5     = 2,     /*!< SDIF_DAT5 : SD/SDIO/MMC Data5 pin                                         */
  GPIO_PINCFG80_FNCSEL80_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG80_FNCSEL80_SWTRACE0      = 4,     /*!< SWTRACE0 : Serial Wire Debug Trace Output 0                               */
  GPIO_PINCFG80_FNCSEL80_DISP_HS       = 5,     /*!< DISP_HS : Display RGB HSYNC                                               */
  GPIO_PINCFG80_FNCSEL80_CT80          = 6,     /*!< CT80 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG80_FNCSEL80_NCE80         = 7,     /*!< NCE80 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG80_FNCSEL80_OBSBUS0       = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
  GPIO_PINCFG80_FNCSEL80_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG80_FNCSEL80_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG80_FNCSEL80_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG80_FNCSEL80_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG80_FNCSEL80_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG80_FNCSEL80_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG80_FNCSEL80_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG80_FNCSEL80_Enum;

/* =======================================================  PINCFG81  ======================================================== */
/* ============================================  GPIO PINCFG81 NCEPOL81 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG81_NCEPOL81                                                    */
  GPIO_PINCFG81_NCEPOL81_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG81_NCEPOL81_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG81_NCEPOL81_Enum;

/* ============================================  GPIO PINCFG81 NCESRC81 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG81_NCESRC81                                                    */
  GPIO_PINCFG81_NCESRC81_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG81_NCESRC81_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG81_NCESRC81_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG81_NCESRC81_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG81_NCESRC81_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG81_NCESRC81_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG81_NCESRC81_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG81_NCESRC81_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG81_NCESRC81_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG81_NCESRC81_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG81_NCESRC81_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG81_NCESRC81_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG81_NCESRC81_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG81_NCESRC81_Enum;

/* ===========================================  GPIO PINCFG81 PULLCFG81 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG81_PULLCFG81                                                   */
  GPIO_PINCFG81_PULLCFG81_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG81_PULLCFG81_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG81_PULLCFG81_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG81_PULLCFG81_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG81_PULLCFG81_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG81_PULLCFG81_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG81_PULLCFG81_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG81_PULLCFG81_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG81_PULLCFG81_Enum;

/* ==============================================  GPIO PINCFG81 DS81 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG81_DS81                                                        */
  GPIO_PINCFG81_DS81_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG81_DS81_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG81_DS81_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG81_DS81_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG81_DS81_Enum;

/* =============================================  GPIO PINCFG81 OUTCFG81 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG81_OUTCFG81                                                    */
  GPIO_PINCFG81_OUTCFG81_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG81_OUTCFG81_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG81_OUTCFG81_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG81_OUTCFG81_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG81_OUTCFG81_Enum;

/* =============================================  GPIO PINCFG81 IRPTEN81 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG81_IRPTEN81                                                    */
  GPIO_PINCFG81_IRPTEN81_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG81_IRPTEN81_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG81_IRPTEN81_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG81_IRPTEN81_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG81_IRPTEN81_Enum;

/* =============================================  GPIO PINCFG81 FNCSEL81 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG81_FNCSEL81                                                    */
  GPIO_PINCFG81_FNCSEL81_MSPI2_7       = 0,     /*!< MSPI2_7 : MSPI Master 2 Interface Signal                                  */
  GPIO_PINCFG81_FNCSEL81_CLKOUT        = 1,     /*!< CLKOUT : Oscillator output clock                                          */
  GPIO_PINCFG81_FNCSEL81_SDIF_DAT6     = 2,     /*!< SDIF_DAT6 : SD/SDIO/MMC Data6 pin                                         */
  GPIO_PINCFG81_FNCSEL81_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG81_FNCSEL81_SWTRACE1      = 4,     /*!< SWTRACE1 : Serial Wire Debug Trace Output 1                               */
  GPIO_PINCFG81_FNCSEL81_DISP_DE       = 5,     /*!< DISP_DE : Display RGB Data Enable                                         */
  GPIO_PINCFG81_FNCSEL81_CT81          = 6,     /*!< CT81 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG81_FNCSEL81_NCE81         = 7,     /*!< NCE81 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG81_FNCSEL81_OBSBUS1       = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
  GPIO_PINCFG81_FNCSEL81_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG81_FNCSEL81_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG81_FNCSEL81_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG81_FNCSEL81_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG81_FNCSEL81_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG81_FNCSEL81_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG81_FNCSEL81_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG81_FNCSEL81_Enum;

/* =======================================================  PINCFG82  ======================================================== */
/* ============================================  GPIO PINCFG82 NCEPOL82 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG82_NCEPOL82                                                    */
  GPIO_PINCFG82_NCEPOL82_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG82_NCEPOL82_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG82_NCEPOL82_Enum;

/* ============================================  GPIO PINCFG82 NCESRC82 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG82_NCESRC82                                                    */
  GPIO_PINCFG82_NCESRC82_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG82_NCESRC82_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG82_NCESRC82_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG82_NCESRC82_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG82_NCESRC82_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG82_NCESRC82_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG82_NCESRC82_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG82_NCESRC82_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG82_NCESRC82_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG82_NCESRC82_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG82_NCESRC82_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG82_NCESRC82_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG82_NCESRC82_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG82_NCESRC82_Enum;

/* ===========================================  GPIO PINCFG82 PULLCFG82 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG82_PULLCFG82                                                   */
  GPIO_PINCFG82_PULLCFG82_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG82_PULLCFG82_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG82_PULLCFG82_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG82_PULLCFG82_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG82_PULLCFG82_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG82_PULLCFG82_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG82_PULLCFG82_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG82_PULLCFG82_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG82_PULLCFG82_Enum;

/* ==============================================  GPIO PINCFG82 DS82 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG82_DS82                                                        */
  GPIO_PINCFG82_DS82_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG82_DS82_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG82_DS82_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG82_DS82_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG82_DS82_Enum;

/* =============================================  GPIO PINCFG82 OUTCFG82 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG82_OUTCFG82                                                    */
  GPIO_PINCFG82_OUTCFG82_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG82_OUTCFG82_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG82_OUTCFG82_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG82_OUTCFG82_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG82_OUTCFG82_Enum;

/* =============================================  GPIO PINCFG82 IRPTEN82 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG82_IRPTEN82                                                    */
  GPIO_PINCFG82_IRPTEN82_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG82_IRPTEN82_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG82_IRPTEN82_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG82_IRPTEN82_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG82_IRPTEN82_Enum;

/* =============================================  GPIO PINCFG82 FNCSEL82 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG82_FNCSEL82                                                    */
  GPIO_PINCFG82_FNCSEL82_MSPI2_8       = 0,     /*!< MSPI2_8 : MSPI Master 2 Interface Signal                                  */
  GPIO_PINCFG82_FNCSEL82_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
  GPIO_PINCFG82_FNCSEL82_SDIF_DAT7     = 2,     /*!< SDIF_DAT7 : SD/SDIO/MMC Data7 pin                                         */
  GPIO_PINCFG82_FNCSEL82_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG82_FNCSEL82_SWTRACE2      = 4,     /*!< SWTRACE2 : Serial Wire Debug Trace Output 2                               */
  GPIO_PINCFG82_FNCSEL82_DISP_PCLK     = 5,     /*!< DISP_PCLK : Display RGB Pixel Clock                                       */
  GPIO_PINCFG82_FNCSEL82_CT82          = 6,     /*!< CT82 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG82_FNCSEL82_NCE82         = 7,     /*!< NCE82 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG82_FNCSEL82_OBSBUS2       = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
  GPIO_PINCFG82_FNCSEL82_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG82_FNCSEL82_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG82_FNCSEL82_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG82_FNCSEL82_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG82_FNCSEL82_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG82_FNCSEL82_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG82_FNCSEL82_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG82_FNCSEL82_Enum;

/* =======================================================  PINCFG83  ======================================================== */
/* ============================================  GPIO PINCFG83 NCEPOL83 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG83_NCEPOL83                                                    */
  GPIO_PINCFG83_NCEPOL83_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG83_NCEPOL83_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG83_NCEPOL83_Enum;

/* ============================================  GPIO PINCFG83 NCESRC83 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG83_NCESRC83                                                    */
  GPIO_PINCFG83_NCESRC83_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG83_NCESRC83_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG83_NCESRC83_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG83_NCESRC83_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG83_NCESRC83_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG83_NCESRC83_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG83_NCESRC83_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG83_NCESRC83_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG83_NCESRC83_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG83_NCESRC83_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG83_NCESRC83_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG83_NCESRC83_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG83_NCESRC83_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG83_NCESRC83_Enum;

/* ===========================================  GPIO PINCFG83 PULLCFG83 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG83_PULLCFG83                                                   */
  GPIO_PINCFG83_PULLCFG83_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG83_PULLCFG83_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG83_PULLCFG83_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG83_PULLCFG83_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG83_PULLCFG83_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG83_PULLCFG83_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG83_PULLCFG83_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG83_PULLCFG83_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG83_PULLCFG83_Enum;

/* ==============================================  GPIO PINCFG83 DS83 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG83_DS83                                                        */
  GPIO_PINCFG83_DS83_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG83_DS83_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG83_DS83_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG83_DS83_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG83_DS83_Enum;

/* =============================================  GPIO PINCFG83 OUTCFG83 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG83_OUTCFG83                                                    */
  GPIO_PINCFG83_OUTCFG83_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG83_OUTCFG83_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG83_OUTCFG83_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG83_OUTCFG83_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG83_OUTCFG83_Enum;

/* =============================================  GPIO PINCFG83 IRPTEN83 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG83_IRPTEN83                                                    */
  GPIO_PINCFG83_IRPTEN83_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG83_IRPTEN83_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG83_IRPTEN83_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG83_IRPTEN83_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG83_IRPTEN83_Enum;

/* =============================================  GPIO PINCFG83 FNCSEL83 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG83_FNCSEL83                                                    */
  GPIO_PINCFG83_FNCSEL83_MSPI2_9       = 0,     /*!< MSPI2_9 : MSPI Master 2 Interface Signal                                  */
  GPIO_PINCFG83_FNCSEL83_32KHzXT       = 1,     /*!< 32KHzXT : 32kHZ from analog                                               */
  GPIO_PINCFG83_FNCSEL83_SDIF_CMD      = 2,     /*!< SDIF_CMD : SD1/SD4/MMC Command pin                                        */
  GPIO_PINCFG83_FNCSEL83_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG83_FNCSEL83_SWTRACE3      = 4,     /*!< SWTRACE3 : Serial Wire Debug Trace Output 3                               */
  GPIO_PINCFG83_FNCSEL83_DISP_SD       = 5,     /*!< DISP_SD : Display RGB Shutdown                                            */
  GPIO_PINCFG83_FNCSEL83_CT83          = 6,     /*!< CT83 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG83_FNCSEL83_NCE83         = 7,     /*!< NCE83 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG83_FNCSEL83_OBSBUS3       = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
  GPIO_PINCFG83_FNCSEL83_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG83_FNCSEL83_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG83_FNCSEL83_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG83_FNCSEL83_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG83_FNCSEL83_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG83_FNCSEL83_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG83_FNCSEL83_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG83_FNCSEL83_Enum;

/* =======================================================  PINCFG84  ======================================================== */
/* ============================================  GPIO PINCFG84 NCEPOL84 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG84_NCEPOL84                                                    */
  GPIO_PINCFG84_NCEPOL84_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG84_NCEPOL84_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG84_NCEPOL84_Enum;

/* ============================================  GPIO PINCFG84 NCESRC84 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG84_NCESRC84                                                    */
  GPIO_PINCFG84_NCESRC84_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG84_NCESRC84_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG84_NCESRC84_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG84_NCESRC84_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG84_NCESRC84_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG84_NCESRC84_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG84_NCESRC84_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG84_NCESRC84_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG84_NCESRC84_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG84_NCESRC84_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG84_NCESRC84_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG84_NCESRC84_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG84_NCESRC84_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG84_NCESRC84_Enum;

/* ===========================================  GPIO PINCFG84 PULLCFG84 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG84_PULLCFG84                                                   */
  GPIO_PINCFG84_PULLCFG84_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG84_PULLCFG84_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG84_PULLCFG84_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG84_PULLCFG84_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG84_PULLCFG84_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG84_PULLCFG84_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG84_PULLCFG84_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG84_PULLCFG84_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG84_PULLCFG84_Enum;

/* ==============================================  GPIO PINCFG84 DS84 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG84_DS84                                                        */
  GPIO_PINCFG84_DS84_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG84_DS84_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG84_DS84_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG84_DS84_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG84_DS84_Enum;

/* =============================================  GPIO PINCFG84 OUTCFG84 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG84_OUTCFG84                                                    */
  GPIO_PINCFG84_OUTCFG84_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG84_OUTCFG84_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG84_OUTCFG84_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG84_OUTCFG84_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG84_OUTCFG84_Enum;

/* =============================================  GPIO PINCFG84 IRPTEN84 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG84_IRPTEN84                                                    */
  GPIO_PINCFG84_IRPTEN84_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG84_IRPTEN84_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG84_IRPTEN84_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG84_IRPTEN84_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG84_IRPTEN84_Enum;

/* =============================================  GPIO PINCFG84 FNCSEL84 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG84_FNCSEL84                                                    */
  GPIO_PINCFG84_FNCSEL84_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG84_FNCSEL84_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG84_FNCSEL84_SDIF_DAT0     = 2,     /*!< SDIF_DAT0 : SD/SDIO/MMC Data0 pin                                         */
  GPIO_PINCFG84_FNCSEL84_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG84_FNCSEL84_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG84_FNCSEL84_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG84_FNCSEL84_CT84          = 6,     /*!< CT84 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG84_FNCSEL84_NCE84         = 7,     /*!< NCE84 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG84_FNCSEL84_OBSBUS4       = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
  GPIO_PINCFG84_FNCSEL84_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG84_FNCSEL84_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG84_FNCSEL84_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG84_FNCSEL84_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG84_FNCSEL84_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG84_FNCSEL84_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG84_FNCSEL84_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG84_FNCSEL84_Enum;

/* =======================================================  PINCFG85  ======================================================== */
/* ============================================  GPIO PINCFG85 NCEPOL85 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG85_NCEPOL85                                                    */
  GPIO_PINCFG85_NCEPOL85_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG85_NCEPOL85_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG85_NCEPOL85_Enum;

/* ============================================  GPIO PINCFG85 NCESRC85 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG85_NCESRC85                                                    */
  GPIO_PINCFG85_NCESRC85_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG85_NCESRC85_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG85_NCESRC85_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG85_NCESRC85_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG85_NCESRC85_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG85_NCESRC85_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG85_NCESRC85_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG85_NCESRC85_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG85_NCESRC85_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG85_NCESRC85_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG85_NCESRC85_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG85_NCESRC85_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG85_NCESRC85_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG85_NCESRC85_Enum;

/* ===========================================  GPIO PINCFG85 PULLCFG85 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG85_PULLCFG85                                                   */
  GPIO_PINCFG85_PULLCFG85_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG85_PULLCFG85_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG85_PULLCFG85_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG85_PULLCFG85_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG85_PULLCFG85_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG85_PULLCFG85_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG85_PULLCFG85_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG85_PULLCFG85_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG85_PULLCFG85_Enum;

/* ==============================================  GPIO PINCFG85 DS85 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG85_DS85                                                        */
  GPIO_PINCFG85_DS85_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG85_DS85_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG85_DS85_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG85_DS85_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG85_DS85_Enum;

/* =============================================  GPIO PINCFG85 OUTCFG85 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG85_OUTCFG85                                                    */
  GPIO_PINCFG85_OUTCFG85_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG85_OUTCFG85_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG85_OUTCFG85_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG85_OUTCFG85_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG85_OUTCFG85_Enum;

/* =============================================  GPIO PINCFG85 IRPTEN85 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG85_IRPTEN85                                                    */
  GPIO_PINCFG85_IRPTEN85_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG85_IRPTEN85_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG85_IRPTEN85_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG85_IRPTEN85_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG85_IRPTEN85_Enum;

/* =============================================  GPIO PINCFG85 FNCSEL85 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG85_FNCSEL85                                                    */
  GPIO_PINCFG85_FNCSEL85_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG85_FNCSEL85_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG85_FNCSEL85_SDIF_DAT1     = 2,     /*!< SDIF_DAT1 : SD/SDIO/MMC Data1 pin                                         */
  GPIO_PINCFG85_FNCSEL85_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG85_FNCSEL85_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG85_FNCSEL85_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG85_FNCSEL85_CT85          = 6,     /*!< CT85 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG85_FNCSEL85_NCE85         = 7,     /*!< NCE85 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG85_FNCSEL85_OBSBUS5       = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
  GPIO_PINCFG85_FNCSEL85_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG85_FNCSEL85_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG85_FNCSEL85_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG85_FNCSEL85_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG85_FNCSEL85_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG85_FNCSEL85_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG85_FNCSEL85_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG85_FNCSEL85_Enum;

/* =======================================================  PINCFG86  ======================================================== */
/* ============================================  GPIO PINCFG86 NCEPOL86 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG86_NCEPOL86                                                    */
  GPIO_PINCFG86_NCEPOL86_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG86_NCEPOL86_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG86_NCEPOL86_Enum;

/* ============================================  GPIO PINCFG86 NCESRC86 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG86_NCESRC86                                                    */
  GPIO_PINCFG86_NCESRC86_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG86_NCESRC86_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG86_NCESRC86_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG86_NCESRC86_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG86_NCESRC86_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG86_NCESRC86_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG86_NCESRC86_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG86_NCESRC86_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG86_NCESRC86_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG86_NCESRC86_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG86_NCESRC86_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG86_NCESRC86_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG86_NCESRC86_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG86_NCESRC86_Enum;

/* ===========================================  GPIO PINCFG86 PULLCFG86 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG86_PULLCFG86                                                   */
  GPIO_PINCFG86_PULLCFG86_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG86_PULLCFG86_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG86_PULLCFG86_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG86_PULLCFG86_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG86_PULLCFG86_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG86_PULLCFG86_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG86_PULLCFG86_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG86_PULLCFG86_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG86_PULLCFG86_Enum;

/* ==============================================  GPIO PINCFG86 DS86 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG86_DS86                                                        */
  GPIO_PINCFG86_DS86_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG86_DS86_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG86_DS86_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG86_DS86_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG86_DS86_Enum;

/* =============================================  GPIO PINCFG86 OUTCFG86 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG86_OUTCFG86                                                    */
  GPIO_PINCFG86_OUTCFG86_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG86_OUTCFG86_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG86_OUTCFG86_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG86_OUTCFG86_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG86_OUTCFG86_Enum;

/* =============================================  GPIO PINCFG86 IRPTEN86 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG86_IRPTEN86                                                    */
  GPIO_PINCFG86_IRPTEN86_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG86_IRPTEN86_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG86_IRPTEN86_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG86_IRPTEN86_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG86_IRPTEN86_Enum;

/* =============================================  GPIO PINCFG86 FNCSEL86 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG86_FNCSEL86                                                    */
  GPIO_PINCFG86_FNCSEL86_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG86_FNCSEL86_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG86_FNCSEL86_SDIF_DAT2     = 2,     /*!< SDIF_DAT2 : SD/SDIO/MMC Data2 pin                                         */
  GPIO_PINCFG86_FNCSEL86_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG86_FNCSEL86_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG86_FNCSEL86_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG86_FNCSEL86_CT86          = 6,     /*!< CT86 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG86_FNCSEL86_NCE86         = 7,     /*!< NCE86 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG86_FNCSEL86_OBSBUS6       = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
  GPIO_PINCFG86_FNCSEL86_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG86_FNCSEL86_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG86_FNCSEL86_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG86_FNCSEL86_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG86_FNCSEL86_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG86_FNCSEL86_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG86_FNCSEL86_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG86_FNCSEL86_Enum;

/* =======================================================  PINCFG87  ======================================================== */
/* ============================================  GPIO PINCFG87 NCEPOL87 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG87_NCEPOL87                                                    */
  GPIO_PINCFG87_NCEPOL87_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG87_NCEPOL87_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG87_NCEPOL87_Enum;

/* ============================================  GPIO PINCFG87 NCESRC87 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG87_NCESRC87                                                    */
  GPIO_PINCFG87_NCESRC87_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG87_NCESRC87_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG87_NCESRC87_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG87_NCESRC87_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG87_NCESRC87_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG87_NCESRC87_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG87_NCESRC87_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG87_NCESRC87_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG87_NCESRC87_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG87_NCESRC87_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG87_NCESRC87_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG87_NCESRC87_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG87_NCESRC87_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG87_NCESRC87_Enum;

/* ===========================================  GPIO PINCFG87 PULLCFG87 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG87_PULLCFG87                                                   */
  GPIO_PINCFG87_PULLCFG87_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG87_PULLCFG87_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG87_PULLCFG87_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG87_PULLCFG87_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG87_PULLCFG87_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG87_PULLCFG87_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG87_PULLCFG87_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG87_PULLCFG87_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG87_PULLCFG87_Enum;

/* ==============================================  GPIO PINCFG87 DS87 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG87_DS87                                                        */
  GPIO_PINCFG87_DS87_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG87_DS87_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG87_DS87_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG87_DS87_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG87_DS87_Enum;

/* =============================================  GPIO PINCFG87 OUTCFG87 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG87_OUTCFG87                                                    */
  GPIO_PINCFG87_OUTCFG87_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG87_OUTCFG87_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG87_OUTCFG87_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG87_OUTCFG87_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG87_OUTCFG87_Enum;

/* =============================================  GPIO PINCFG87 IRPTEN87 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG87_IRPTEN87                                                    */
  GPIO_PINCFG87_IRPTEN87_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG87_IRPTEN87_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG87_IRPTEN87_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG87_IRPTEN87_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG87_IRPTEN87_Enum;

/* =============================================  GPIO PINCFG87 FNCSEL87 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG87_FNCSEL87                                                    */
  GPIO_PINCFG87_FNCSEL87_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG87_FNCSEL87_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG87_FNCSEL87_SDIF_DAT3     = 2,     /*!< SDIF_DAT3 : SD/SDIO/MMC Data3 pin                                         */
  GPIO_PINCFG87_FNCSEL87_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG87_FNCSEL87_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG87_FNCSEL87_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG87_FNCSEL87_CT87          = 6,     /*!< CT87 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG87_FNCSEL87_NCE87         = 7,     /*!< NCE87 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG87_FNCSEL87_OBSBUS7       = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
  GPIO_PINCFG87_FNCSEL87_DISP_TE       = 9,     /*!< DISP_TE : Display TE input                                                */
  GPIO_PINCFG87_FNCSEL87_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG87_FNCSEL87_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG87_FNCSEL87_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG87_FNCSEL87_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG87_FNCSEL87_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG87_FNCSEL87_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG87_FNCSEL87_Enum;

/* =======================================================  PINCFG88  ======================================================== */
/* ============================================  GPIO PINCFG88 NCEPOL88 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG88_NCEPOL88                                                    */
  GPIO_PINCFG88_NCEPOL88_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG88_NCEPOL88_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG88_NCEPOL88_Enum;

/* ============================================  GPIO PINCFG88 NCESRC88 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG88_NCESRC88                                                    */
  GPIO_PINCFG88_NCESRC88_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG88_NCESRC88_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG88_NCESRC88_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG88_NCESRC88_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG88_NCESRC88_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG88_NCESRC88_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG88_NCESRC88_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG88_NCESRC88_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG88_NCESRC88_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG88_NCESRC88_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG88_NCESRC88_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG88_NCESRC88_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG88_NCESRC88_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG88_NCESRC88_Enum;

/* ===========================================  GPIO PINCFG88 PULLCFG88 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG88_PULLCFG88                                                   */
  GPIO_PINCFG88_PULLCFG88_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG88_PULLCFG88_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG88_PULLCFG88_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG88_PULLCFG88_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG88_PULLCFG88_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG88_PULLCFG88_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG88_PULLCFG88_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG88_PULLCFG88_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG88_PULLCFG88_Enum;

/* ==============================================  GPIO PINCFG88 DS88 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG88_DS88                                                        */
  GPIO_PINCFG88_DS88_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG88_DS88_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG88_DS88_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG88_DS88_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG88_DS88_Enum;

/* =============================================  GPIO PINCFG88 OUTCFG88 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG88_OUTCFG88                                                    */
  GPIO_PINCFG88_OUTCFG88_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG88_OUTCFG88_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG88_OUTCFG88_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG88_OUTCFG88_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG88_OUTCFG88_Enum;

/* =============================================  GPIO PINCFG88 IRPTEN88 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG88_IRPTEN88                                                    */
  GPIO_PINCFG88_IRPTEN88_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG88_IRPTEN88_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG88_IRPTEN88_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG88_IRPTEN88_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG88_IRPTEN88_Enum;

/* =============================================  GPIO PINCFG88 FNCSEL88 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG88_FNCSEL88                                                    */
  GPIO_PINCFG88_FNCSEL88_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG88_FNCSEL88_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG88_FNCSEL88_SDIF_CLKOUT   = 2,     /*!< SDIF_CLKOUT : SD/SDIO/MMC Clock to Card (CLK)                             */
  GPIO_PINCFG88_FNCSEL88_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG88_FNCSEL88_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG88_FNCSEL88_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG88_FNCSEL88_CT88          = 6,     /*!< CT88 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG88_FNCSEL88_NCE88         = 7,     /*!< NCE88 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG88_FNCSEL88_OBSBUS8       = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
  GPIO_PINCFG88_FNCSEL88_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG88_FNCSEL88_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG88_FNCSEL88_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG88_FNCSEL88_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG88_FNCSEL88_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG88_FNCSEL88_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG88_FNCSEL88_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG88_FNCSEL88_Enum;

/* =======================================================  PINCFG89  ======================================================== */
/* ============================================  GPIO PINCFG89 NCEPOL89 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG89_NCEPOL89                                                    */
  GPIO_PINCFG89_NCEPOL89_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG89_NCEPOL89_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG89_NCEPOL89_Enum;

/* ============================================  GPIO PINCFG89 NCESRC89 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG89_NCESRC89                                                    */
  GPIO_PINCFG89_NCESRC89_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG89_NCESRC89_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG89_NCESRC89_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG89_NCESRC89_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG89_NCESRC89_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG89_NCESRC89_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG89_NCESRC89_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG89_NCESRC89_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG89_NCESRC89_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG89_NCESRC89_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG89_NCESRC89_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG89_NCESRC89_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG89_NCESRC89_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG89_NCESRC89_Enum;

/* ===========================================  GPIO PINCFG89 PULLCFG89 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG89_PULLCFG89                                                   */
  GPIO_PINCFG89_PULLCFG89_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG89_PULLCFG89_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG89_PULLCFG89_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG89_PULLCFG89_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG89_PULLCFG89_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG89_PULLCFG89_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG89_PULLCFG89_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG89_PULLCFG89_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG89_PULLCFG89_Enum;

/* ==============================================  GPIO PINCFG89 DS89 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG89_DS89                                                        */
  GPIO_PINCFG89_DS89_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG89_DS89_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG89_DS89_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG89_DS89_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG89_DS89_Enum;

/* =============================================  GPIO PINCFG89 OUTCFG89 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG89_OUTCFG89                                                    */
  GPIO_PINCFG89_OUTCFG89_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG89_OUTCFG89_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG89_OUTCFG89_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG89_OUTCFG89_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG89_OUTCFG89_Enum;

/* =============================================  GPIO PINCFG89 IRPTEN89 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG89_IRPTEN89                                                    */
  GPIO_PINCFG89_IRPTEN89_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG89_IRPTEN89_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG89_IRPTEN89_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG89_IRPTEN89_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG89_IRPTEN89_Enum;

/* =============================================  GPIO PINCFG89 FNCSEL89 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG89_FNCSEL89                                                    */
  GPIO_PINCFG89_FNCSEL89_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG89_FNCSEL89_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG89_FNCSEL89_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG89_FNCSEL89_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG89_FNCSEL89_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG89_FNCSEL89_DISP_CM       = 5,     /*!< DISP_CM : Display RGB Color Mode                                          */
  GPIO_PINCFG89_FNCSEL89_CT89          = 6,     /*!< CT89 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG89_FNCSEL89_NCE89         = 7,     /*!< NCE89 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG89_FNCSEL89_OBSBUS9       = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
  GPIO_PINCFG89_FNCSEL89_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG89_FNCSEL89_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG89_FNCSEL89_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG89_FNCSEL89_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG89_FNCSEL89_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG89_FNCSEL89_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG89_FNCSEL89_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG89_FNCSEL89_Enum;

/* =======================================================  PINCFG90  ======================================================== */
/* ============================================  GPIO PINCFG90 NCEPOL90 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG90_NCEPOL90                                                    */
  GPIO_PINCFG90_NCEPOL90_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG90_NCEPOL90_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG90_NCEPOL90_Enum;

/* ============================================  GPIO PINCFG90 NCESRC90 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG90_NCESRC90                                                    */
  GPIO_PINCFG90_NCESRC90_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG90_NCESRC90_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG90_NCESRC90_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG90_NCESRC90_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG90_NCESRC90_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG90_NCESRC90_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG90_NCESRC90_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG90_NCESRC90_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG90_NCESRC90_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG90_NCESRC90_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG90_NCESRC90_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG90_NCESRC90_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG90_NCESRC90_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG90_NCESRC90_Enum;

/* ===========================================  GPIO PINCFG90 PULLCFG90 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG90_PULLCFG90                                                   */
  GPIO_PINCFG90_PULLCFG90_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG90_PULLCFG90_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG90_PULLCFG90_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG90_PULLCFG90_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG90_PULLCFG90_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG90_PULLCFG90_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG90_PULLCFG90_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG90_PULLCFG90_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG90_PULLCFG90_Enum;

/* ==============================================  GPIO PINCFG90 DS90 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG90_DS90                                                        */
  GPIO_PINCFG90_DS90_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG90_DS90_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG90_DS90_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG90_DS90_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG90_DS90_Enum;

/* =============================================  GPIO PINCFG90 OUTCFG90 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG90_OUTCFG90                                                    */
  GPIO_PINCFG90_OUTCFG90_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG90_OUTCFG90_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG90_OUTCFG90_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG90_OUTCFG90_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG90_OUTCFG90_Enum;

/* =============================================  GPIO PINCFG90 IRPTEN90 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG90_IRPTEN90                                                    */
  GPIO_PINCFG90_IRPTEN90_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG90_IRPTEN90_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG90_IRPTEN90_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG90_IRPTEN90_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG90_IRPTEN90_Enum;

/* =============================================  GPIO PINCFG90 FNCSEL90 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG90_FNCSEL90                                                    */
  GPIO_PINCFG90_FNCSEL90_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG90_FNCSEL90_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG90_FNCSEL90_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG90_FNCSEL90_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG90_FNCSEL90_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG90_FNCSEL90_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG90_FNCSEL90_CT90          = 6,     /*!< CT90 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG90_FNCSEL90_NCE90         = 7,     /*!< NCE90 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG90_FNCSEL90_OBSBUS10      = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
  GPIO_PINCFG90_FNCSEL90_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG90_FNCSEL90_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG90_FNCSEL90_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG90_FNCSEL90_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG90_FNCSEL90_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG90_FNCSEL90_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG90_FNCSEL90_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG90_FNCSEL90_Enum;

/* =======================================================  PINCFG91  ======================================================== */
/* ============================================  GPIO PINCFG91 NCEPOL91 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG91_NCEPOL91                                                    */
  GPIO_PINCFG91_NCEPOL91_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG91_NCEPOL91_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG91_NCEPOL91_Enum;

/* ============================================  GPIO PINCFG91 NCESRC91 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG91_NCESRC91                                                    */
  GPIO_PINCFG91_NCESRC91_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG91_NCESRC91_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG91_NCESRC91_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG91_NCESRC91_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG91_NCESRC91_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG91_NCESRC91_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG91_NCESRC91_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG91_NCESRC91_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG91_NCESRC91_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG91_NCESRC91_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG91_NCESRC91_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG91_NCESRC91_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG91_NCESRC91_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG91_NCESRC91_Enum;

/* ===========================================  GPIO PINCFG91 PULLCFG91 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG91_PULLCFG91                                                   */
  GPIO_PINCFG91_PULLCFG91_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG91_PULLCFG91_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG91_PULLCFG91_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG91_PULLCFG91_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG91_PULLCFG91_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG91_PULLCFG91_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG91_PULLCFG91_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG91_PULLCFG91_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG91_PULLCFG91_Enum;

/* ==============================================  GPIO PINCFG91 DS91 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG91_DS91                                                        */
  GPIO_PINCFG91_DS91_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG91_DS91_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG91_DS91_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG91_DS91_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG91_DS91_Enum;

/* =============================================  GPIO PINCFG91 OUTCFG91 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG91_OUTCFG91                                                    */
  GPIO_PINCFG91_OUTCFG91_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG91_OUTCFG91_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG91_OUTCFG91_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG91_OUTCFG91_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG91_OUTCFG91_Enum;

/* =============================================  GPIO PINCFG91 IRPTEN91 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG91_IRPTEN91                                                    */
  GPIO_PINCFG91_IRPTEN91_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG91_IRPTEN91_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG91_IRPTEN91_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG91_IRPTEN91_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG91_IRPTEN91_Enum;

/* =============================================  GPIO PINCFG91 FNCSEL91 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG91_FNCSEL91                                                    */
  GPIO_PINCFG91_FNCSEL91_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG91_FNCSEL91_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG91_FNCSEL91_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG91_FNCSEL91_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG91_FNCSEL91_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG91_FNCSEL91_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG91_FNCSEL91_CT91          = 6,     /*!< CT91 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG91_FNCSEL91_NCE91         = 7,     /*!< NCE91 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG91_FNCSEL91_OBSBUS11      = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
  GPIO_PINCFG91_FNCSEL91_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG91_FNCSEL91_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG91_FNCSEL91_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG91_FNCSEL91_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG91_FNCSEL91_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG91_FNCSEL91_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG91_FNCSEL91_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG91_FNCSEL91_Enum;

/* =======================================================  PINCFG92  ======================================================== */
/* ============================================  GPIO PINCFG92 NCEPOL92 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG92_NCEPOL92                                                    */
  GPIO_PINCFG92_NCEPOL92_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG92_NCEPOL92_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG92_NCEPOL92_Enum;

/* ============================================  GPIO PINCFG92 NCESRC92 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG92_NCESRC92                                                    */
  GPIO_PINCFG92_NCESRC92_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG92_NCESRC92_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG92_NCESRC92_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG92_NCESRC92_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG92_NCESRC92_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG92_NCESRC92_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG92_NCESRC92_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG92_NCESRC92_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG92_NCESRC92_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG92_NCESRC92_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG92_NCESRC92_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG92_NCESRC92_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG92_NCESRC92_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG92_NCESRC92_Enum;

/* ===========================================  GPIO PINCFG92 PULLCFG92 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG92_PULLCFG92                                                   */
  GPIO_PINCFG92_PULLCFG92_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG92_PULLCFG92_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG92_PULLCFG92_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG92_PULLCFG92_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG92_PULLCFG92_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG92_PULLCFG92_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG92_PULLCFG92_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG92_PULLCFG92_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG92_PULLCFG92_Enum;

/* ==============================================  GPIO PINCFG92 DS92 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG92_DS92                                                        */
  GPIO_PINCFG92_DS92_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG92_DS92_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG92_DS92_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG92_DS92_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG92_DS92_Enum;

/* =============================================  GPIO PINCFG92 OUTCFG92 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG92_OUTCFG92                                                    */
  GPIO_PINCFG92_OUTCFG92_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG92_OUTCFG92_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG92_OUTCFG92_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG92_OUTCFG92_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG92_OUTCFG92_Enum;

/* =============================================  GPIO PINCFG92 IRPTEN92 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG92_IRPTEN92                                                    */
  GPIO_PINCFG92_IRPTEN92_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG92_IRPTEN92_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG92_IRPTEN92_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG92_IRPTEN92_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG92_IRPTEN92_Enum;

/* =============================================  GPIO PINCFG92 FNCSEL92 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG92_FNCSEL92                                                    */
  GPIO_PINCFG92_FNCSEL92_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG92_FNCSEL92_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG92_FNCSEL92_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG92_FNCSEL92_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG92_FNCSEL92_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG92_FNCSEL92_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG92_FNCSEL92_CT92          = 6,     /*!< CT92 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG92_FNCSEL92_NCE92         = 7,     /*!< NCE92 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG92_FNCSEL92_OBSBUS12      = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
  GPIO_PINCFG92_FNCSEL92_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG92_FNCSEL92_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG92_FNCSEL92_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG92_FNCSEL92_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG92_FNCSEL92_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG92_FNCSEL92_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG92_FNCSEL92_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG92_FNCSEL92_Enum;

/* =======================================================  PINCFG93  ======================================================== */
/* ============================================  GPIO PINCFG93 NCEPOL93 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG93_NCEPOL93                                                    */
  GPIO_PINCFG93_NCEPOL93_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG93_NCEPOL93_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG93_NCEPOL93_Enum;

/* ============================================  GPIO PINCFG93 NCESRC93 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG93_NCESRC93                                                    */
  GPIO_PINCFG93_NCESRC93_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG93_NCESRC93_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG93_NCESRC93_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG93_NCESRC93_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG93_NCESRC93_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG93_NCESRC93_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG93_NCESRC93_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG93_NCESRC93_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG93_NCESRC93_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG93_NCESRC93_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG93_NCESRC93_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG93_NCESRC93_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG93_NCESRC93_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG93_NCESRC93_Enum;

/* ===========================================  GPIO PINCFG93 PULLCFG93 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG93_PULLCFG93                                                   */
  GPIO_PINCFG93_PULLCFG93_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG93_PULLCFG93_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG93_PULLCFG93_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG93_PULLCFG93_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG93_PULLCFG93_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG93_PULLCFG93_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG93_PULLCFG93_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG93_PULLCFG93_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG93_PULLCFG93_Enum;

/* ==============================================  GPIO PINCFG93 DS93 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG93_DS93                                                        */
  GPIO_PINCFG93_DS93_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG93_DS93_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG93_DS93_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG93_DS93_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG93_DS93_Enum;

/* =============================================  GPIO PINCFG93 OUTCFG93 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG93_OUTCFG93                                                    */
  GPIO_PINCFG93_OUTCFG93_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG93_OUTCFG93_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG93_OUTCFG93_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG93_OUTCFG93_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG93_OUTCFG93_Enum;

/* =============================================  GPIO PINCFG93 IRPTEN93 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG93_IRPTEN93                                                    */
  GPIO_PINCFG93_IRPTEN93_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG93_IRPTEN93_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG93_IRPTEN93_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG93_IRPTEN93_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG93_IRPTEN93_Enum;

/* =============================================  GPIO PINCFG93 FNCSEL93 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG93_FNCSEL93                                                    */
  GPIO_PINCFG93_FNCSEL93_MSPI2_9       = 0,     /*!< MSPI2_9 : MSPI Master 2 Interface Signal                                  */
  GPIO_PINCFG93_FNCSEL93_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG93_FNCSEL93_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG93_FNCSEL93_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG93_FNCSEL93_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG93_FNCSEL93_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG93_FNCSEL93_CT93          = 6,     /*!< CT93 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG93_FNCSEL93_NCE93         = 7,     /*!< NCE93 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG93_FNCSEL93_OBSBUS13      = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
  GPIO_PINCFG93_FNCSEL93_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG93_FNCSEL93_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG93_FNCSEL93_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG93_FNCSEL93_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG93_FNCSEL93_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG93_FNCSEL93_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG93_FNCSEL93_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG93_FNCSEL93_Enum;

/* =======================================================  PINCFG94  ======================================================== */
/* ============================================  GPIO PINCFG94 NCEPOL94 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG94_NCEPOL94                                                    */
  GPIO_PINCFG94_NCEPOL94_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG94_NCEPOL94_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG94_NCEPOL94_Enum;

/* ============================================  GPIO PINCFG94 NCESRC94 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG94_NCESRC94                                                    */
  GPIO_PINCFG94_NCESRC94_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG94_NCESRC94_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG94_NCESRC94_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG94_NCESRC94_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG94_NCESRC94_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG94_NCESRC94_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG94_NCESRC94_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG94_NCESRC94_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG94_NCESRC94_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG94_NCESRC94_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG94_NCESRC94_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG94_NCESRC94_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG94_NCESRC94_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG94_NCESRC94_Enum;

/* ===========================================  GPIO PINCFG94 PULLCFG94 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG94_PULLCFG94                                                   */
  GPIO_PINCFG94_PULLCFG94_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG94_PULLCFG94_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG94_PULLCFG94_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG94_PULLCFG94_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG94_PULLCFG94_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG94_PULLCFG94_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG94_PULLCFG94_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG94_PULLCFG94_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG94_PULLCFG94_Enum;

/* ==============================================  GPIO PINCFG94 DS94 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG94_DS94                                                        */
  GPIO_PINCFG94_DS94_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG94_DS94_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG94_DS94_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG94_DS94_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG94_DS94_Enum;

/* =============================================  GPIO PINCFG94 OUTCFG94 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG94_OUTCFG94                                                    */
  GPIO_PINCFG94_OUTCFG94_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG94_OUTCFG94_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG94_OUTCFG94_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG94_OUTCFG94_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG94_OUTCFG94_Enum;

/* =============================================  GPIO PINCFG94 IRPTEN94 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG94_IRPTEN94                                                    */
  GPIO_PINCFG94_IRPTEN94_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG94_IRPTEN94_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG94_IRPTEN94_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG94_IRPTEN94_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG94_IRPTEN94_Enum;

/* =============================================  GPIO PINCFG94 FNCSEL94 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG94_FNCSEL94                                                    */
  GPIO_PINCFG94_FNCSEL94_RESERVED0     = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG94_FNCSEL94_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG94_FNCSEL94_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG94_FNCSEL94_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG94_FNCSEL94_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG94_FNCSEL94_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG94_FNCSEL94_CT94          = 6,     /*!< CT94 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG94_FNCSEL94_NCE94         = 7,     /*!< NCE94 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG94_FNCSEL94_OBSBUS14      = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
  GPIO_PINCFG94_FNCSEL94_VCMPO         = 9,     /*!< VCMPO : Output of the voltage comparator signal                           */
  GPIO_PINCFG94_FNCSEL94_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG94_FNCSEL94_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG94_FNCSEL94_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG94_FNCSEL94_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG94_FNCSEL94_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG94_FNCSEL94_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG94_FNCSEL94_Enum;

/* =======================================================  PINCFG95  ======================================================== */
/* ============================================  GPIO PINCFG95 NCEPOL95 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG95_NCEPOL95                                                    */
  GPIO_PINCFG95_NCEPOL95_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG95_NCEPOL95_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG95_NCEPOL95_Enum;

/* ============================================  GPIO PINCFG95 NCESRC95 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG95_NCESRC95                                                    */
  GPIO_PINCFG95_NCESRC95_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG95_NCESRC95_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG95_NCESRC95_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG95_NCESRC95_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG95_NCESRC95_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG95_NCESRC95_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG95_NCESRC95_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG95_NCESRC95_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG95_NCESRC95_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG95_NCESRC95_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG95_NCESRC95_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG95_NCESRC95_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG95_NCESRC95_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG95_NCESRC95_Enum;

/* ===========================================  GPIO PINCFG95 PULLCFG95 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG95_PULLCFG95                                                   */
  GPIO_PINCFG95_PULLCFG95_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG95_PULLCFG95_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG95_PULLCFG95_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG95_PULLCFG95_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG95_PULLCFG95_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG95_PULLCFG95_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG95_PULLCFG95_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG95_PULLCFG95_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG95_PULLCFG95_Enum;

/* ==============================================  GPIO PINCFG95 DS95 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG95_DS95                                                        */
  GPIO_PINCFG95_DS95_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG95_DS95_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG95_DS95_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG95_DS95_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG95_DS95_Enum;

/* =============================================  GPIO PINCFG95 OUTCFG95 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG95_OUTCFG95                                                    */
  GPIO_PINCFG95_OUTCFG95_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG95_OUTCFG95_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG95_OUTCFG95_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG95_OUTCFG95_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG95_OUTCFG95_Enum;

/* =============================================  GPIO PINCFG95 IRPTEN95 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG95_IRPTEN95                                                    */
  GPIO_PINCFG95_IRPTEN95_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG95_IRPTEN95_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG95_IRPTEN95_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG95_IRPTEN95_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG95_IRPTEN95_Enum;

/* =============================================  GPIO PINCFG95 FNCSEL95 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG95_FNCSEL95                                                    */
  GPIO_PINCFG95_FNCSEL95_MSPI1_0       = 0,     /*!< MSPI1_0 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG95_FNCSEL95_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG95_FNCSEL95_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG95_FNCSEL95_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG95_FNCSEL95_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG95_FNCSEL95_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG95_FNCSEL95_CT95          = 6,     /*!< CT95 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG95_FNCSEL95_NCE95         = 7,     /*!< NCE95 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG95_FNCSEL95_OBSBUS15      = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
  GPIO_PINCFG95_FNCSEL95_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG95_FNCSEL95_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG95_FNCSEL95_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG95_FNCSEL95_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG95_FNCSEL95_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG95_FNCSEL95_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG95_FNCSEL95_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG95_FNCSEL95_Enum;

/* =======================================================  PINCFG96  ======================================================== */
/* ============================================  GPIO PINCFG96 NCEPOL96 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG96_NCEPOL96                                                    */
  GPIO_PINCFG96_NCEPOL96_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG96_NCEPOL96_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG96_NCEPOL96_Enum;

/* ============================================  GPIO PINCFG96 NCESRC96 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG96_NCESRC96                                                    */
  GPIO_PINCFG96_NCESRC96_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG96_NCESRC96_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG96_NCESRC96_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG96_NCESRC96_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG96_NCESRC96_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG96_NCESRC96_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG96_NCESRC96_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG96_NCESRC96_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG96_NCESRC96_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG96_NCESRC96_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG96_NCESRC96_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG96_NCESRC96_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG96_NCESRC96_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG96_NCESRC96_Enum;

/* ===========================================  GPIO PINCFG96 PULLCFG96 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG96_PULLCFG96                                                   */
  GPIO_PINCFG96_PULLCFG96_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG96_PULLCFG96_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG96_PULLCFG96_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG96_PULLCFG96_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG96_PULLCFG96_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG96_PULLCFG96_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG96_PULLCFG96_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG96_PULLCFG96_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG96_PULLCFG96_Enum;

/* ==============================================  GPIO PINCFG96 DS96 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG96_DS96                                                        */
  GPIO_PINCFG96_DS96_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG96_DS96_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG96_DS96_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG96_DS96_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG96_DS96_Enum;

/* =============================================  GPIO PINCFG96 OUTCFG96 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG96_OUTCFG96                                                    */
  GPIO_PINCFG96_OUTCFG96_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG96_OUTCFG96_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG96_OUTCFG96_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG96_OUTCFG96_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG96_OUTCFG96_Enum;

/* =============================================  GPIO PINCFG96 IRPTEN96 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG96_IRPTEN96                                                    */
  GPIO_PINCFG96_IRPTEN96_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG96_IRPTEN96_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG96_IRPTEN96_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG96_IRPTEN96_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG96_IRPTEN96_Enum;

/* =============================================  GPIO PINCFG96 FNCSEL96 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG96_FNCSEL96                                                    */
  GPIO_PINCFG96_FNCSEL96_MSPI1_1       = 0,     /*!< MSPI1_1 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG96_FNCSEL96_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG96_FNCSEL96_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG96_FNCSEL96_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG96_FNCSEL96_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG96_FNCSEL96_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG96_FNCSEL96_CT96          = 6,     /*!< CT96 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG96_FNCSEL96_NCE96         = 7,     /*!< NCE96 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG96_FNCSEL96_OBSBUS0       = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
  GPIO_PINCFG96_FNCSEL96_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG96_FNCSEL96_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG96_FNCSEL96_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG96_FNCSEL96_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG96_FNCSEL96_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG96_FNCSEL96_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG96_FNCSEL96_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG96_FNCSEL96_Enum;

/* =======================================================  PINCFG97  ======================================================== */
/* ============================================  GPIO PINCFG97 NCEPOL97 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG97_NCEPOL97                                                    */
  GPIO_PINCFG97_NCEPOL97_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG97_NCEPOL97_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG97_NCEPOL97_Enum;

/* ============================================  GPIO PINCFG97 NCESRC97 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG97_NCESRC97                                                    */
  GPIO_PINCFG97_NCESRC97_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG97_NCESRC97_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG97_NCESRC97_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG97_NCESRC97_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG97_NCESRC97_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG97_NCESRC97_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG97_NCESRC97_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG97_NCESRC97_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG97_NCESRC97_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG97_NCESRC97_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG97_NCESRC97_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG97_NCESRC97_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG97_NCESRC97_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG97_NCESRC97_Enum;

/* ===========================================  GPIO PINCFG97 PULLCFG97 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG97_PULLCFG97                                                   */
  GPIO_PINCFG97_PULLCFG97_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG97_PULLCFG97_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG97_PULLCFG97_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG97_PULLCFG97_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG97_PULLCFG97_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG97_PULLCFG97_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG97_PULLCFG97_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG97_PULLCFG97_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG97_PULLCFG97_Enum;

/* ==============================================  GPIO PINCFG97 DS97 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG97_DS97                                                        */
  GPIO_PINCFG97_DS97_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG97_DS97_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG97_DS97_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG97_DS97_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG97_DS97_Enum;

/* =============================================  GPIO PINCFG97 OUTCFG97 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG97_OUTCFG97                                                    */
  GPIO_PINCFG97_OUTCFG97_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG97_OUTCFG97_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG97_OUTCFG97_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG97_OUTCFG97_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG97_OUTCFG97_Enum;

/* =============================================  GPIO PINCFG97 IRPTEN97 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG97_IRPTEN97                                                    */
  GPIO_PINCFG97_IRPTEN97_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG97_IRPTEN97_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG97_IRPTEN97_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG97_IRPTEN97_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG97_IRPTEN97_Enum;

/* =============================================  GPIO PINCFG97 FNCSEL97 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG97_FNCSEL97                                                    */
  GPIO_PINCFG97_FNCSEL97_MSPI1_2       = 0,     /*!< MSPI1_2 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG97_FNCSEL97_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG97_FNCSEL97_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG97_FNCSEL97_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG97_FNCSEL97_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG97_FNCSEL97_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG97_FNCSEL97_CT97          = 6,     /*!< CT97 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG97_FNCSEL97_NCE97         = 7,     /*!< NCE97 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG97_FNCSEL97_OBSBUS1       = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
  GPIO_PINCFG97_FNCSEL97_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG97_FNCSEL97_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG97_FNCSEL97_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG97_FNCSEL97_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG97_FNCSEL97_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG97_FNCSEL97_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG97_FNCSEL97_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG97_FNCSEL97_Enum;

/* =======================================================  PINCFG98  ======================================================== */
/* ============================================  GPIO PINCFG98 NCEPOL98 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG98_NCEPOL98                                                    */
  GPIO_PINCFG98_NCEPOL98_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG98_NCEPOL98_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG98_NCEPOL98_Enum;

/* ============================================  GPIO PINCFG98 NCESRC98 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG98_NCESRC98                                                    */
  GPIO_PINCFG98_NCESRC98_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG98_NCESRC98_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG98_NCESRC98_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG98_NCESRC98_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG98_NCESRC98_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG98_NCESRC98_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG98_NCESRC98_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG98_NCESRC98_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG98_NCESRC98_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG98_NCESRC98_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG98_NCESRC98_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG98_NCESRC98_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG98_NCESRC98_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG98_NCESRC98_Enum;

/* ===========================================  GPIO PINCFG98 PULLCFG98 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG98_PULLCFG98                                                   */
  GPIO_PINCFG98_PULLCFG98_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG98_PULLCFG98_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG98_PULLCFG98_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG98_PULLCFG98_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG98_PULLCFG98_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG98_PULLCFG98_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG98_PULLCFG98_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG98_PULLCFG98_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG98_PULLCFG98_Enum;

/* ==============================================  GPIO PINCFG98 DS98 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG98_DS98                                                        */
  GPIO_PINCFG98_DS98_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG98_DS98_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG98_DS98_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG98_DS98_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG98_DS98_Enum;

/* =============================================  GPIO PINCFG98 OUTCFG98 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG98_OUTCFG98                                                    */
  GPIO_PINCFG98_OUTCFG98_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG98_OUTCFG98_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG98_OUTCFG98_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG98_OUTCFG98_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG98_OUTCFG98_Enum;

/* =============================================  GPIO PINCFG98 IRPTEN98 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG98_IRPTEN98                                                    */
  GPIO_PINCFG98_IRPTEN98_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG98_IRPTEN98_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG98_IRPTEN98_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG98_IRPTEN98_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG98_IRPTEN98_Enum;

/* =============================================  GPIO PINCFG98 FNCSEL98 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG98_FNCSEL98                                                    */
  GPIO_PINCFG98_FNCSEL98_MSPI1_3       = 0,     /*!< MSPI1_3 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG98_FNCSEL98_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG98_FNCSEL98_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG98_FNCSEL98_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG98_FNCSEL98_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG98_FNCSEL98_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG98_FNCSEL98_CT98          = 6,     /*!< CT98 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG98_FNCSEL98_NCE98         = 7,     /*!< NCE98 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG98_FNCSEL98_OBSBUS2       = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
  GPIO_PINCFG98_FNCSEL98_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG98_FNCSEL98_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG98_FNCSEL98_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG98_FNCSEL98_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG98_FNCSEL98_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG98_FNCSEL98_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG98_FNCSEL98_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG98_FNCSEL98_Enum;

/* =======================================================  PINCFG99  ======================================================== */
/* ============================================  GPIO PINCFG99 NCEPOL99 [22..22]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG99_NCEPOL99                                                    */
  GPIO_PINCFG99_NCEPOL99_LOW           = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG99_NCEPOL99_HIGH          = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG99_NCEPOL99_Enum;

/* ============================================  GPIO PINCFG99 NCESRC99 [16..21]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG99_NCESRC99                                                    */
  GPIO_PINCFG99_NCESRC99_IOM0CE0       = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM0CE1       = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM0CE2       = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM0CE3       = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM1CE0       = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM1CE1       = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM1CE2       = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM1CE3       = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM2CE0       = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM2CE1       = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM2CE2       = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM2CE3       = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM3CE0       = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM3CE1       = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM3CE2       = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM3CE3       = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM4CE0       = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM4CE1       = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM4CE2       = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM4CE3       = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM5CE0       = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM5CE1       = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM5CE2       = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM5CE3       = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM6CE0       = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM6CE1       = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM6CE2       = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM6CE3       = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM7CE0       = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM7CE1       = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM7CE2       = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG99_NCESRC99_IOM7CE3       = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG99_NCESRC99_MSPI0CEN0     = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG99_NCESRC99_MSPI0CEN1     = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG99_NCESRC99_MSPI1CEN0     = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG99_NCESRC99_MSPI1CEN1     = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG99_NCESRC99_MSPI2CEN0     = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG99_NCESRC99_MSPI2CEN1     = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG99_NCESRC99_DC_DPI_DE     = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG99_NCESRC99_DISP_CONT_CSX = 39,    /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG99_NCESRC99_DC_SPI_CS_N   = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG99_NCESRC99_DC_QSPI_CS_N  = 41,    /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG99_NCESRC99_DC_RESX       = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG99_NCESRC99_Enum;

/* ===========================================  GPIO PINCFG99 PULLCFG99 [13..15]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG99_PULLCFG99                                                   */
  GPIO_PINCFG99_PULLCFG99_DIS          = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG99_PULLCFG99_PD50K        = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG99_PULLCFG99_PU15K        = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG99_PULLCFG99_PU6K         = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG99_PULLCFG99_PU12K        = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG99_PULLCFG99_PU24K        = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG99_PULLCFG99_PU50K        = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG99_PULLCFG99_PU100K       = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG99_PULLCFG99_Enum;

/* ==============================================  GPIO PINCFG99 DS99 [10..11]  ============================================== */
typedef enum {                                  /*!< GPIO_PINCFG99_DS99                                                        */
  GPIO_PINCFG99_DS99_0P1X              = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG99_DS99_0P5X              = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG99_DS99_0P75X             = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG99_DS99_1P0X              = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG99_DS99_Enum;

/* =============================================  GPIO PINCFG99 OUTCFG99 [8..9]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG99_OUTCFG99                                                    */
  GPIO_PINCFG99_OUTCFG99_DIS           = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG99_OUTCFG99_PUSHPULL      = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG99_OUTCFG99_OD            = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG99_OUTCFG99_TS            = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG99_OUTCFG99_Enum;

/* =============================================  GPIO PINCFG99 IRPTEN99 [6..7]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG99_IRPTEN99                                                    */
  GPIO_PINCFG99_IRPTEN99_DIS           = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG99_IRPTEN99_INTFALL       = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG99_IRPTEN99_INTRISE       = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG99_IRPTEN99_INTANY        = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG99_IRPTEN99_Enum;

/* =============================================  GPIO PINCFG99 FNCSEL99 [0..3]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG99_FNCSEL99                                                    */
  GPIO_PINCFG99_FNCSEL99_MSPI1_4       = 0,     /*!< MSPI1_4 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG99_FNCSEL99_RESERVED1     = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG99_FNCSEL99_RESERVED2     = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG99_FNCSEL99_GPIO          = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG99_FNCSEL99_RESERVED4     = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG99_FNCSEL99_RESERVED5     = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG99_FNCSEL99_CT99          = 6,     /*!< CT99 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG99_FNCSEL99_NCE99         = 7,     /*!< NCE99 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG99_FNCSEL99_OBSBUS3       = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
  GPIO_PINCFG99_FNCSEL99_RESERVED9     = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG99_FNCSEL99_RESERVED10    = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG99_FNCSEL99_FPIO          = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG99_FNCSEL99_RESERVED12    = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG99_FNCSEL99_RESERVED13    = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG99_FNCSEL99_RESERVED14    = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG99_FNCSEL99_RESERVED15    = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG99_FNCSEL99_Enum;

/* =======================================================  PINCFG100  ======================================================= */
/* ===========================================  GPIO PINCFG100 NCEPOL100 [22..22]  =========================================== */
typedef enum {                                  /*!< GPIO_PINCFG100_NCEPOL100                                                  */
  GPIO_PINCFG100_NCEPOL100_LOW         = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG100_NCEPOL100_HIGH        = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG100_NCEPOL100_Enum;

/* ===========================================  GPIO PINCFG100 NCESRC100 [16..21]  =========================================== */
typedef enum {                                  /*!< GPIO_PINCFG100_NCESRC100                                                  */
  GPIO_PINCFG100_NCESRC100_IOM0CE0     = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM0CE1     = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM0CE2     = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM0CE3     = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM1CE0     = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM1CE1     = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM1CE2     = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM1CE3     = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM2CE0     = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM2CE1     = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM2CE2     = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM2CE3     = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM3CE0     = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM3CE1     = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM3CE2     = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM3CE3     = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM4CE0     = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM4CE1     = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM4CE2     = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM4CE3     = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM5CE0     = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM5CE1     = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM5CE2     = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM5CE3     = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM6CE0     = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM6CE1     = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM6CE2     = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM6CE3     = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM7CE0     = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM7CE1     = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM7CE2     = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG100_NCESRC100_IOM7CE3     = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG100_NCESRC100_MSPI0CEN0   = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG100_NCESRC100_MSPI0CEN1   = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG100_NCESRC100_MSPI1CEN0   = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG100_NCESRC100_MSPI1CEN1   = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG100_NCESRC100_MSPI2CEN0   = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG100_NCESRC100_MSPI2CEN1   = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG100_NCESRC100_DC_DPI_DE   = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG100_NCESRC100_DISP_CONT_CSX = 39,  /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG100_NCESRC100_DC_SPI_CS_N = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG100_NCESRC100_DC_QSPI_CS_N = 41,   /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG100_NCESRC100_DC_RESX     = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG100_NCESRC100_Enum;

/* ==========================================  GPIO PINCFG100 PULLCFG100 [13..15]  =========================================== */
typedef enum {                                  /*!< GPIO_PINCFG100_PULLCFG100                                                 */
  GPIO_PINCFG100_PULLCFG100_DIS        = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG100_PULLCFG100_PD50K      = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG100_PULLCFG100_PU15K      = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG100_PULLCFG100_PU6K       = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG100_PULLCFG100_PU12K      = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG100_PULLCFG100_PU24K      = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG100_PULLCFG100_PU50K      = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG100_PULLCFG100_PU100K     = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG100_PULLCFG100_Enum;

/* =============================================  GPIO PINCFG100 DS100 [10..11]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG100_DS100                                                      */
  GPIO_PINCFG100_DS100_0P1X            = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG100_DS100_0P5X            = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG100_DS100_0P75X           = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG100_DS100_1P0X            = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG100_DS100_Enum;

/* ============================================  GPIO PINCFG100 OUTCFG100 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG100_OUTCFG100                                                  */
  GPIO_PINCFG100_OUTCFG100_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG100_OUTCFG100_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG100_OUTCFG100_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG100_OUTCFG100_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG100_OUTCFG100_Enum;

/* ============================================  GPIO PINCFG100 IRPTEN100 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG100_IRPTEN100                                                  */
  GPIO_PINCFG100_IRPTEN100_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG100_IRPTEN100_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG100_IRPTEN100_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG100_IRPTEN100_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG100_IRPTEN100_Enum;

/* ============================================  GPIO PINCFG100 FNCSEL100 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG100_FNCSEL100                                                  */
  GPIO_PINCFG100_FNCSEL100_MSPI1_5     = 0,     /*!< MSPI1_5 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG100_FNCSEL100_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG100_FNCSEL100_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG100_FNCSEL100_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG100_FNCSEL100_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG100_FNCSEL100_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG100_FNCSEL100_CT100       = 6,     /*!< CT100 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG100_FNCSEL100_NCE100      = 7,     /*!< NCE100 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG100_FNCSEL100_OBSBUS4     = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
  GPIO_PINCFG100_FNCSEL100_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG100_FNCSEL100_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG100_FNCSEL100_FPIO        = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG100_FNCSEL100_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG100_FNCSEL100_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG100_FNCSEL100_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG100_FNCSEL100_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG100_FNCSEL100_Enum;

/* =======================================================  PINCFG101  ======================================================= */
/* ===========================================  GPIO PINCFG101 NCEPOL101 [22..22]  =========================================== */
typedef enum {                                  /*!< GPIO_PINCFG101_NCEPOL101                                                  */
  GPIO_PINCFG101_NCEPOL101_LOW         = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG101_NCEPOL101_HIGH        = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG101_NCEPOL101_Enum;

/* ===========================================  GPIO PINCFG101 NCESRC101 [16..21]  =========================================== */
typedef enum {                                  /*!< GPIO_PINCFG101_NCESRC101                                                  */
  GPIO_PINCFG101_NCESRC101_IOM0CE0     = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM0CE1     = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM0CE2     = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM0CE3     = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM1CE0     = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM1CE1     = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM1CE2     = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM1CE3     = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM2CE0     = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM2CE1     = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM2CE2     = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM2CE3     = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM3CE0     = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM3CE1     = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM3CE2     = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM3CE3     = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM4CE0     = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM4CE1     = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM4CE2     = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM4CE3     = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM5CE0     = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM5CE1     = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM5CE2     = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM5CE3     = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM6CE0     = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM6CE1     = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM6CE2     = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM6CE3     = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM7CE0     = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM7CE1     = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM7CE2     = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG101_NCESRC101_IOM7CE3     = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG101_NCESRC101_MSPI0CEN0   = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG101_NCESRC101_MSPI0CEN1   = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG101_NCESRC101_MSPI1CEN0   = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG101_NCESRC101_MSPI1CEN1   = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG101_NCESRC101_MSPI2CEN0   = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG101_NCESRC101_MSPI2CEN1   = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG101_NCESRC101_DC_DPI_DE   = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG101_NCESRC101_DISP_CONT_CSX = 39,  /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG101_NCESRC101_DC_SPI_CS_N = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG101_NCESRC101_DC_QSPI_CS_N = 41,   /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG101_NCESRC101_DC_RESX     = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG101_NCESRC101_Enum;

/* ==========================================  GPIO PINCFG101 PULLCFG101 [13..15]  =========================================== */
typedef enum {                                  /*!< GPIO_PINCFG101_PULLCFG101                                                 */
  GPIO_PINCFG101_PULLCFG101_DIS        = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG101_PULLCFG101_PD50K      = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG101_PULLCFG101_PU15K      = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG101_PULLCFG101_PU6K       = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG101_PULLCFG101_PU12K      = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG101_PULLCFG101_PU24K      = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG101_PULLCFG101_PU50K      = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG101_PULLCFG101_PU100K     = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG101_PULLCFG101_Enum;

/* =============================================  GPIO PINCFG101 DS101 [10..11]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG101_DS101                                                      */
  GPIO_PINCFG101_DS101_0P1X            = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG101_DS101_0P5X            = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG101_DS101_0P75X           = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG101_DS101_1P0X            = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG101_DS101_Enum;

/* ============================================  GPIO PINCFG101 OUTCFG101 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG101_OUTCFG101                                                  */
  GPIO_PINCFG101_OUTCFG101_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG101_OUTCFG101_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG101_OUTCFG101_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG101_OUTCFG101_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG101_OUTCFG101_Enum;

/* ============================================  GPIO PINCFG101 IRPTEN101 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG101_IRPTEN101                                                  */
  GPIO_PINCFG101_IRPTEN101_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG101_IRPTEN101_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG101_IRPTEN101_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG101_IRPTEN101_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG101_IRPTEN101_Enum;

/* ============================================  GPIO PINCFG101 FNCSEL101 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG101_FNCSEL101                                                  */
  GPIO_PINCFG101_FNCSEL101_MSPI1_6     = 0,     /*!< MSPI1_6 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG101_FNCSEL101_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG101_FNCSEL101_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG101_FNCSEL101_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG101_FNCSEL101_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG101_FNCSEL101_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG101_FNCSEL101_CT101       = 6,     /*!< CT101 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG101_FNCSEL101_NCE101      = 7,     /*!< NCE101 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG101_FNCSEL101_OBSBUS5     = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
  GPIO_PINCFG101_FNCSEL101_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG101_FNCSEL101_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG101_FNCSEL101_FPIO        = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG101_FNCSEL101_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG101_FNCSEL101_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG101_FNCSEL101_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG101_FNCSEL101_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG101_FNCSEL101_Enum;

/* =======================================================  PINCFG102  ======================================================= */
/* ===========================================  GPIO PINCFG102 NCEPOL102 [22..22]  =========================================== */
typedef enum {                                  /*!< GPIO_PINCFG102_NCEPOL102                                                  */
  GPIO_PINCFG102_NCEPOL102_LOW         = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG102_NCEPOL102_HIGH        = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG102_NCEPOL102_Enum;

/* ===========================================  GPIO PINCFG102 NCESRC102 [16..21]  =========================================== */
typedef enum {                                  /*!< GPIO_PINCFG102_NCESRC102                                                  */
  GPIO_PINCFG102_NCESRC102_IOM0CE0     = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM0CE1     = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM0CE2     = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM0CE3     = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM1CE0     = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM1CE1     = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM1CE2     = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM1CE3     = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM2CE0     = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM2CE1     = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM2CE2     = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM2CE3     = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM3CE0     = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM3CE1     = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM3CE2     = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM3CE3     = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM4CE0     = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM4CE1     = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM4CE2     = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM4CE3     = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM5CE0     = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM5CE1     = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM5CE2     = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM5CE3     = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM6CE0     = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM6CE1     = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM6CE2     = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM6CE3     = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM7CE0     = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM7CE1     = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM7CE2     = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG102_NCESRC102_IOM7CE3     = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG102_NCESRC102_MSPI0CEN0   = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG102_NCESRC102_MSPI0CEN1   = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG102_NCESRC102_MSPI1CEN0   = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG102_NCESRC102_MSPI1CEN1   = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG102_NCESRC102_MSPI2CEN0   = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG102_NCESRC102_MSPI2CEN1   = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG102_NCESRC102_DC_DPI_DE   = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG102_NCESRC102_DISP_CONT_CSX = 39,  /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG102_NCESRC102_DC_SPI_CS_N = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG102_NCESRC102_DC_QSPI_CS_N = 41,   /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG102_NCESRC102_DC_RESX     = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG102_NCESRC102_Enum;

/* ==========================================  GPIO PINCFG102 PULLCFG102 [13..15]  =========================================== */
typedef enum {                                  /*!< GPIO_PINCFG102_PULLCFG102                                                 */
  GPIO_PINCFG102_PULLCFG102_DIS        = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG102_PULLCFG102_PD50K      = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG102_PULLCFG102_PU15K      = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG102_PULLCFG102_PU6K       = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG102_PULLCFG102_PU12K      = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG102_PULLCFG102_PU24K      = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG102_PULLCFG102_PU50K      = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG102_PULLCFG102_PU100K     = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG102_PULLCFG102_Enum;

/* =============================================  GPIO PINCFG102 DS102 [10..11]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG102_DS102                                                      */
  GPIO_PINCFG102_DS102_0P1X            = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG102_DS102_0P5X            = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG102_DS102_0P75X           = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG102_DS102_1P0X            = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG102_DS102_Enum;

/* ============================================  GPIO PINCFG102 OUTCFG102 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG102_OUTCFG102                                                  */
  GPIO_PINCFG102_OUTCFG102_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG102_OUTCFG102_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG102_OUTCFG102_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG102_OUTCFG102_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG102_OUTCFG102_Enum;

/* ============================================  GPIO PINCFG102 IRPTEN102 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG102_IRPTEN102                                                  */
  GPIO_PINCFG102_IRPTEN102_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG102_IRPTEN102_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG102_IRPTEN102_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG102_IRPTEN102_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG102_IRPTEN102_Enum;

/* ============================================  GPIO PINCFG102 FNCSEL102 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG102_FNCSEL102                                                  */
  GPIO_PINCFG102_FNCSEL102_MSPI1_7     = 0,     /*!< MSPI1_7 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG102_FNCSEL102_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG102_FNCSEL102_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG102_FNCSEL102_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG102_FNCSEL102_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG102_FNCSEL102_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG102_FNCSEL102_CT102       = 6,     /*!< CT102 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG102_FNCSEL102_NCE102      = 7,     /*!< NCE102 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG102_FNCSEL102_OBSBUS6     = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
  GPIO_PINCFG102_FNCSEL102_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG102_FNCSEL102_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG102_FNCSEL102_FPIO        = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG102_FNCSEL102_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG102_FNCSEL102_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG102_FNCSEL102_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG102_FNCSEL102_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG102_FNCSEL102_Enum;

/* =======================================================  PINCFG103  ======================================================= */
/* ===========================================  GPIO PINCFG103 NCEPOL103 [22..22]  =========================================== */
typedef enum {                                  /*!< GPIO_PINCFG103_NCEPOL103                                                  */
  GPIO_PINCFG103_NCEPOL103_LOW         = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG103_NCEPOL103_HIGH        = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG103_NCEPOL103_Enum;

/* ===========================================  GPIO PINCFG103 NCESRC103 [16..21]  =========================================== */
typedef enum {                                  /*!< GPIO_PINCFG103_NCESRC103                                                  */
  GPIO_PINCFG103_NCESRC103_IOM0CE0     = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM0CE1     = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM0CE2     = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM0CE3     = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM1CE0     = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM1CE1     = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM1CE2     = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM1CE3     = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM2CE0     = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM2CE1     = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM2CE2     = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM2CE3     = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM3CE0     = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM3CE1     = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM3CE2     = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM3CE3     = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM4CE0     = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM4CE1     = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM4CE2     = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM4CE3     = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM5CE0     = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM5CE1     = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM5CE2     = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM5CE3     = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM6CE0     = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM6CE1     = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM6CE2     = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM6CE3     = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM7CE0     = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM7CE1     = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM7CE2     = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG103_NCESRC103_IOM7CE3     = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG103_NCESRC103_MSPI0CEN0   = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG103_NCESRC103_MSPI0CEN1   = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG103_NCESRC103_MSPI1CEN0   = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG103_NCESRC103_MSPI1CEN1   = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG103_NCESRC103_MSPI2CEN0   = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG103_NCESRC103_MSPI2CEN1   = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG103_NCESRC103_DC_DPI_DE   = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG103_NCESRC103_DISP_CONT_CSX = 39,  /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG103_NCESRC103_DC_SPI_CS_N = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG103_NCESRC103_DC_QSPI_CS_N = 41,   /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG103_NCESRC103_DC_RESX     = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG103_NCESRC103_Enum;

/* ==========================================  GPIO PINCFG103 PULLCFG103 [13..15]  =========================================== */
typedef enum {                                  /*!< GPIO_PINCFG103_PULLCFG103                                                 */
  GPIO_PINCFG103_PULLCFG103_DIS        = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG103_PULLCFG103_PD50K      = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG103_PULLCFG103_PU15K      = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG103_PULLCFG103_PU6K       = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG103_PULLCFG103_PU12K      = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG103_PULLCFG103_PU24K      = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG103_PULLCFG103_PU50K      = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG103_PULLCFG103_PU100K     = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG103_PULLCFG103_Enum;

/* =============================================  GPIO PINCFG103 DS103 [10..11]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG103_DS103                                                      */
  GPIO_PINCFG103_DS103_0P1X            = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG103_DS103_0P5X            = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG103_DS103_0P75X           = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG103_DS103_1P0X            = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG103_DS103_Enum;

/* ============================================  GPIO PINCFG103 OUTCFG103 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG103_OUTCFG103                                                  */
  GPIO_PINCFG103_OUTCFG103_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG103_OUTCFG103_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG103_OUTCFG103_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG103_OUTCFG103_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG103_OUTCFG103_Enum;

/* ============================================  GPIO PINCFG103 IRPTEN103 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG103_IRPTEN103                                                  */
  GPIO_PINCFG103_IRPTEN103_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG103_IRPTEN103_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG103_IRPTEN103_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG103_IRPTEN103_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG103_IRPTEN103_Enum;

/* ============================================  GPIO PINCFG103 FNCSEL103 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG103_FNCSEL103                                                  */
  GPIO_PINCFG103_FNCSEL103_MSPI1_8     = 0,     /*!< MSPI1_8 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG103_FNCSEL103_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG103_FNCSEL103_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG103_FNCSEL103_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG103_FNCSEL103_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG103_FNCSEL103_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG103_FNCSEL103_CT103       = 6,     /*!< CT103 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG103_FNCSEL103_NCE103      = 7,     /*!< NCE103 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG103_FNCSEL103_OBSBUS7     = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
  GPIO_PINCFG103_FNCSEL103_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG103_FNCSEL103_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG103_FNCSEL103_FPIO        = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG103_FNCSEL103_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG103_FNCSEL103_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG103_FNCSEL103_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG103_FNCSEL103_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG103_FNCSEL103_Enum;

/* =======================================================  PINCFG104  ======================================================= */
/* ===========================================  GPIO PINCFG104 NCEPOL104 [22..22]  =========================================== */
typedef enum {                                  /*!< GPIO_PINCFG104_NCEPOL104                                                  */
  GPIO_PINCFG104_NCEPOL104_LOW         = 0,     /*!< LOW : Polarity is active low                                              */
  GPIO_PINCFG104_NCEPOL104_HIGH        = 1,     /*!< HIGH : Polarity is active high                                            */
} GPIO_PINCFG104_NCEPOL104_Enum;

/* ===========================================  GPIO PINCFG104 NCESRC104 [16..21]  =========================================== */
typedef enum {                                  /*!< GPIO_PINCFG104_NCESRC104                                                  */
  GPIO_PINCFG104_NCESRC104_IOM0CE0     = 0,     /*!< IOM0CE0 : IOM 0 NCE 0 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM0CE1     = 1,     /*!< IOM0CE1 : IOM 0 NCE 1 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM0CE2     = 2,     /*!< IOM0CE2 : IOM 0 NCE 2 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM0CE3     = 3,     /*!< IOM0CE3 : IOM 0 NCE 3 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM1CE0     = 4,     /*!< IOM1CE0 : IOM 1 NCE 0 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM1CE1     = 5,     /*!< IOM1CE1 : IOM 1 NCE 1 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM1CE2     = 6,     /*!< IOM1CE2 : IOM 1 NCE 2 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM1CE3     = 7,     /*!< IOM1CE3 : IOM 1 NCE 3 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM2CE0     = 8,     /*!< IOM2CE0 : IOM 2 NCE 0 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM2CE1     = 9,     /*!< IOM2CE1 : IOM 2 NCE 1 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM2CE2     = 10,    /*!< IOM2CE2 : IOM 2 NCE 2 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM2CE3     = 11,    /*!< IOM2CE3 : IOM 2 NCE 3 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM3CE0     = 12,    /*!< IOM3CE0 : IOM 3 NCE 0 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM3CE1     = 13,    /*!< IOM3CE1 : IOM 3 NCE 1 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM3CE2     = 14,    /*!< IOM3CE2 : IOM 3 NCE 2 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM3CE3     = 15,    /*!< IOM3CE3 : IOM 3 NCE 3 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM4CE0     = 16,    /*!< IOM4CE0 : IOM 4 NCE 0 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM4CE1     = 17,    /*!< IOM4CE1 : IOM 4 NCE 1 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM4CE2     = 18,    /*!< IOM4CE2 : IOM 4 NCE 2 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM4CE3     = 19,    /*!< IOM4CE3 : IOM 4 NCE 3 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM5CE0     = 20,    /*!< IOM5CE0 : IOM 5 NCE 0 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM5CE1     = 21,    /*!< IOM5CE1 : IOM 5 NCE 1 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM5CE2     = 22,    /*!< IOM5CE2 : IOM 5 NCE 2 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM5CE3     = 23,    /*!< IOM5CE3 : IOM 5 NCE 3 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM6CE0     = 24,    /*!< IOM6CE0 : IOM 6 NCE 0 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM6CE1     = 25,    /*!< IOM6CE1 : IOM 6 NCE 1 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM6CE2     = 26,    /*!< IOM6CE2 : IOM 6 NCE 2 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM6CE3     = 27,    /*!< IOM6CE3 : IOM 6 NCE 3 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM7CE0     = 28,    /*!< IOM7CE0 : IOM 7 NCE 0 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM7CE1     = 29,    /*!< IOM7CE1 : IOM 7 NCE 1 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM7CE2     = 30,    /*!< IOM7CE2 : IOM 7 NCE 2 module                                              */
  GPIO_PINCFG104_NCESRC104_IOM7CE3     = 31,    /*!< IOM7CE3 : IOM 7 NCE 3 module                                              */
  GPIO_PINCFG104_NCESRC104_MSPI0CEN0   = 32,    /*!< MSPI0CEN0 : MSPI 0 NCE 0 module                                           */
  GPIO_PINCFG104_NCESRC104_MSPI0CEN1   = 33,    /*!< MSPI0CEN1 : MSPI 0 NCE 1 module                                           */
  GPIO_PINCFG104_NCESRC104_MSPI1CEN0   = 34,    /*!< MSPI1CEN0 : MSPI 1 NCE 0 module                                           */
  GPIO_PINCFG104_NCESRC104_MSPI1CEN1   = 35,    /*!< MSPI1CEN1 : MSPI 1 NCE 1 module                                           */
  GPIO_PINCFG104_NCESRC104_MSPI2CEN0   = 36,    /*!< MSPI2CEN0 : MSPI 2 NCE 0 module                                           */
  GPIO_PINCFG104_NCESRC104_MSPI2CEN1   = 37,    /*!< MSPI2CEN1 : MSPI 2 NCE 1 module                                           */
  GPIO_PINCFG104_NCESRC104_DC_DPI_DE   = 38,    /*!< DC_DPI_DE : DC DPI DE module                                              */
  GPIO_PINCFG104_NCESRC104_DISP_CONT_CSX = 39,  /*!< DISP_CONT_CSX : DISP CONT CSX module                                      */
  GPIO_PINCFG104_NCESRC104_DC_SPI_CS_N = 40,    /*!< DC_SPI_CS_N : DC SPI CS_N module                                          */
  GPIO_PINCFG104_NCESRC104_DC_QSPI_CS_N = 41,   /*!< DC_QSPI_CS_N : DC QSPI CS_N module                                        */
  GPIO_PINCFG104_NCESRC104_DC_RESX     = 42,    /*!< DC_RESX : DC module RESX                                                  */
} GPIO_PINCFG104_NCESRC104_Enum;

/* ==========================================  GPIO PINCFG104 PULLCFG104 [13..15]  =========================================== */
typedef enum {                                  /*!< GPIO_PINCFG104_PULLCFG104                                                 */
  GPIO_PINCFG104_PULLCFG104_DIS        = 0,     /*!< DIS : No pullup or pulldown selected                                      */
  GPIO_PINCFG104_PULLCFG104_PD50K      = 1,     /*!< PD50K : 50K Pulldown selected                                             */
  GPIO_PINCFG104_PULLCFG104_PU15K      = 2,     /*!< PU15K : 1.5K Pullup selected                                              */
  GPIO_PINCFG104_PULLCFG104_PU6K       = 3,     /*!< PU6K : 6K Pullup selected                                                 */
  GPIO_PINCFG104_PULLCFG104_PU12K      = 4,     /*!< PU12K : 12K Pullup selected                                               */
  GPIO_PINCFG104_PULLCFG104_PU24K      = 5,     /*!< PU24K : 24K Pullup selected                                               */
  GPIO_PINCFG104_PULLCFG104_PU50K      = 6,     /*!< PU50K : 50K Pullup selected                                               */
  GPIO_PINCFG104_PULLCFG104_PU100K     = 7,     /*!< PU100K : 100K Pullup selected                                             */
} GPIO_PINCFG104_PULLCFG104_Enum;

/* =============================================  GPIO PINCFG104 DS104 [10..11]  ============================================= */
typedef enum {                                  /*!< GPIO_PINCFG104_DS104                                                      */
  GPIO_PINCFG104_DS104_0P1X            = 0,     /*!< 0P1X : 0.1x output driver selected                                        */
  GPIO_PINCFG104_DS104_0P5X            = 1,     /*!< 0P5X : 0.5x output driver selected                                        */
  GPIO_PINCFG104_DS104_0P75X           = 2,     /*!< 0P75X : 0.75x output driver selected                                      */
  GPIO_PINCFG104_DS104_1P0X            = 3,     /*!< 1P0X : 1.0x output driver selected                                        */
} GPIO_PINCFG104_DS104_Enum;

/* ============================================  GPIO PINCFG104 OUTCFG104 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG104_OUTCFG104                                                  */
  GPIO_PINCFG104_OUTCFG104_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG104_OUTCFG104_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG104_OUTCFG104_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG104_OUTCFG104_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG104_OUTCFG104_Enum;

/* ============================================  GPIO PINCFG104 IRPTEN104 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG104_IRPTEN104                                                  */
  GPIO_PINCFG104_IRPTEN104_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG104_IRPTEN104_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG104_IRPTEN104_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG104_IRPTEN104_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG104_IRPTEN104_Enum;

/* ============================================  GPIO PINCFG104 FNCSEL104 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG104_FNCSEL104                                                  */
  GPIO_PINCFG104_FNCSEL104_MSPI1_9     = 0,     /*!< MSPI1_9 : MSPI Master 1 Interface Signal                                  */
  GPIO_PINCFG104_FNCSEL104_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG104_FNCSEL104_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG104_FNCSEL104_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG104_FNCSEL104_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG104_FNCSEL104_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG104_FNCSEL104_CT104       = 6,     /*!< CT104 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG104_FNCSEL104_NCE104      = 7,     /*!< NCE104 : IOMSTR/MSPI N Chip Select. Polarity is determined by
                                                     CE_POLARITY field                                                         */
  GPIO_PINCFG104_FNCSEL104_OBSBUS8     = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
  GPIO_PINCFG104_FNCSEL104_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG104_FNCSEL104_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG104_FNCSEL104_FPIO        = 11,    /*!< FPIO : Fast PIO                                                           */
  GPIO_PINCFG104_FNCSEL104_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG104_FNCSEL104_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG104_FNCSEL104_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG104_FNCSEL104_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG104_FNCSEL104_Enum;

/* =======================================================  PINCFG105  ======================================================= */
/* ============================================  GPIO PINCFG105 OUTCFG105 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG105_OUTCFG105                                                  */
  GPIO_PINCFG105_OUTCFG105_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG105_OUTCFG105_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG105_OUTCFG105_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG105_OUTCFG105_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG105_OUTCFG105_Enum;

/* ============================================  GPIO PINCFG105 IRPTEN105 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG105_IRPTEN105                                                  */
  GPIO_PINCFG105_IRPTEN105_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG105_IRPTEN105_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG105_IRPTEN105_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG105_IRPTEN105_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG105_IRPTEN105_Enum;

/* ============================================  GPIO PINCFG105 FNCSEL105 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG105_FNCSEL105                                                  */
  GPIO_PINCFG105_FNCSEL105_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG105_FNCSEL105_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG105_FNCSEL105_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG105_FNCSEL105_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG105_FNCSEL105_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG105_FNCSEL105_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG105_FNCSEL105_CT105       = 6,     /*!< CT105 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG105_FNCSEL105_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG105_FNCSEL105_OBSBUS9     = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
  GPIO_PINCFG105_FNCSEL105_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG105_FNCSEL105_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG105_FNCSEL105_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG105_FNCSEL105_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG105_FNCSEL105_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG105_FNCSEL105_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG105_FNCSEL105_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG105_FNCSEL105_Enum;

/* =======================================================  PINCFG106  ======================================================= */
/* ============================================  GPIO PINCFG106 OUTCFG106 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG106_OUTCFG106                                                  */
  GPIO_PINCFG106_OUTCFG106_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG106_OUTCFG106_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG106_OUTCFG106_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG106_OUTCFG106_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG106_OUTCFG106_Enum;

/* ============================================  GPIO PINCFG106 IRPTEN106 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG106_IRPTEN106                                                  */
  GPIO_PINCFG106_IRPTEN106_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG106_IRPTEN106_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG106_IRPTEN106_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG106_IRPTEN106_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG106_IRPTEN106_Enum;

/* ============================================  GPIO PINCFG106 FNCSEL106 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG106_FNCSEL106                                                  */
  GPIO_PINCFG106_FNCSEL106_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG106_FNCSEL106_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG106_FNCSEL106_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG106_FNCSEL106_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG106_FNCSEL106_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG106_FNCSEL106_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG106_FNCSEL106_CT106       = 6,     /*!< CT106 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG106_FNCSEL106_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG106_FNCSEL106_OBSBUS10    = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
  GPIO_PINCFG106_FNCSEL106_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG106_FNCSEL106_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG106_FNCSEL106_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG106_FNCSEL106_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG106_FNCSEL106_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG106_FNCSEL106_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG106_FNCSEL106_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG106_FNCSEL106_Enum;

/* =======================================================  PINCFG107  ======================================================= */
/* ============================================  GPIO PINCFG107 OUTCFG107 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG107_OUTCFG107                                                  */
  GPIO_PINCFG107_OUTCFG107_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG107_OUTCFG107_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG107_OUTCFG107_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG107_OUTCFG107_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG107_OUTCFG107_Enum;

/* ============================================  GPIO PINCFG107 IRPTEN107 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG107_IRPTEN107                                                  */
  GPIO_PINCFG107_IRPTEN107_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG107_IRPTEN107_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG107_IRPTEN107_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG107_IRPTEN107_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG107_IRPTEN107_Enum;

/* ============================================  GPIO PINCFG107 FNCSEL107 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG107_FNCSEL107                                                  */
  GPIO_PINCFG107_FNCSEL107_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG107_FNCSEL107_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG107_FNCSEL107_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG107_FNCSEL107_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG107_FNCSEL107_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG107_FNCSEL107_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG107_FNCSEL107_CT107       = 6,     /*!< CT107 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG107_FNCSEL107_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG107_FNCSEL107_OBSBUS11    = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
  GPIO_PINCFG107_FNCSEL107_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG107_FNCSEL107_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG107_FNCSEL107_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG107_FNCSEL107_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG107_FNCSEL107_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG107_FNCSEL107_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG107_FNCSEL107_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG107_FNCSEL107_Enum;

/* =======================================================  PINCFG108  ======================================================= */
/* ============================================  GPIO PINCFG108 OUTCFG108 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG108_OUTCFG108                                                  */
  GPIO_PINCFG108_OUTCFG108_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG108_OUTCFG108_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG108_OUTCFG108_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG108_OUTCFG108_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG108_OUTCFG108_Enum;

/* ============================================  GPIO PINCFG108 IRPTEN108 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG108_IRPTEN108                                                  */
  GPIO_PINCFG108_IRPTEN108_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG108_IRPTEN108_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG108_IRPTEN108_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG108_IRPTEN108_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG108_IRPTEN108_Enum;

/* ============================================  GPIO PINCFG108 FNCSEL108 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG108_FNCSEL108                                                  */
  GPIO_PINCFG108_FNCSEL108_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG108_FNCSEL108_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG108_FNCSEL108_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG108_FNCSEL108_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG108_FNCSEL108_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG108_FNCSEL108_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG108_FNCSEL108_CT108       = 6,     /*!< CT108 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG108_FNCSEL108_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG108_FNCSEL108_OBSBUS12    = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
  GPIO_PINCFG108_FNCSEL108_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG108_FNCSEL108_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG108_FNCSEL108_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG108_FNCSEL108_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG108_FNCSEL108_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG108_FNCSEL108_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG108_FNCSEL108_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG108_FNCSEL108_Enum;

/* =======================================================  PINCFG109  ======================================================= */
/* ============================================  GPIO PINCFG109 OUTCFG109 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG109_OUTCFG109                                                  */
  GPIO_PINCFG109_OUTCFG109_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG109_OUTCFG109_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG109_OUTCFG109_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG109_OUTCFG109_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG109_OUTCFG109_Enum;

/* ============================================  GPIO PINCFG109 IRPTEN109 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG109_IRPTEN109                                                  */
  GPIO_PINCFG109_IRPTEN109_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG109_IRPTEN109_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG109_IRPTEN109_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG109_IRPTEN109_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG109_IRPTEN109_Enum;

/* ============================================  GPIO PINCFG109 FNCSEL109 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG109_FNCSEL109                                                  */
  GPIO_PINCFG109_FNCSEL109_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG109_FNCSEL109_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG109_FNCSEL109_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG109_FNCSEL109_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG109_FNCSEL109_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG109_FNCSEL109_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG109_FNCSEL109_CT109       = 6,     /*!< CT109 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG109_FNCSEL109_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG109_FNCSEL109_OBSBUS13    = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
  GPIO_PINCFG109_FNCSEL109_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG109_FNCSEL109_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG109_FNCSEL109_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG109_FNCSEL109_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG109_FNCSEL109_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG109_FNCSEL109_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG109_FNCSEL109_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG109_FNCSEL109_Enum;

/* =======================================================  PINCFG110  ======================================================= */
/* ============================================  GPIO PINCFG110 OUTCFG110 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG110_OUTCFG110                                                  */
  GPIO_PINCFG110_OUTCFG110_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG110_OUTCFG110_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG110_OUTCFG110_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG110_OUTCFG110_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG110_OUTCFG110_Enum;

/* ============================================  GPIO PINCFG110 IRPTEN110 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG110_IRPTEN110                                                  */
  GPIO_PINCFG110_IRPTEN110_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG110_IRPTEN110_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG110_IRPTEN110_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG110_IRPTEN110_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG110_IRPTEN110_Enum;

/* ============================================  GPIO PINCFG110 FNCSEL110 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG110_FNCSEL110                                                  */
  GPIO_PINCFG110_FNCSEL110_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG110_FNCSEL110_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG110_FNCSEL110_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG110_FNCSEL110_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG110_FNCSEL110_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG110_FNCSEL110_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG110_FNCSEL110_CT110       = 6,     /*!< CT110 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG110_FNCSEL110_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG110_FNCSEL110_OBSBUS14    = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
  GPIO_PINCFG110_FNCSEL110_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG110_FNCSEL110_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG110_FNCSEL110_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG110_FNCSEL110_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG110_FNCSEL110_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG110_FNCSEL110_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG110_FNCSEL110_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG110_FNCSEL110_Enum;

/* =======================================================  PINCFG111  ======================================================= */
/* ============================================  GPIO PINCFG111 OUTCFG111 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG111_OUTCFG111                                                  */
  GPIO_PINCFG111_OUTCFG111_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG111_OUTCFG111_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG111_OUTCFG111_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG111_OUTCFG111_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG111_OUTCFG111_Enum;

/* ============================================  GPIO PINCFG111 IRPTEN111 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG111_IRPTEN111                                                  */
  GPIO_PINCFG111_IRPTEN111_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG111_IRPTEN111_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG111_IRPTEN111_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG111_IRPTEN111_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG111_IRPTEN111_Enum;

/* ============================================  GPIO PINCFG111 FNCSEL111 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG111_FNCSEL111                                                  */
  GPIO_PINCFG111_FNCSEL111_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG111_FNCSEL111_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG111_FNCSEL111_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG111_FNCSEL111_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG111_FNCSEL111_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG111_FNCSEL111_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG111_FNCSEL111_CT111       = 6,     /*!< CT111 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG111_FNCSEL111_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG111_FNCSEL111_OBSBUS15    = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
  GPIO_PINCFG111_FNCSEL111_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG111_FNCSEL111_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG111_FNCSEL111_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG111_FNCSEL111_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG111_FNCSEL111_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG111_FNCSEL111_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG111_FNCSEL111_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG111_FNCSEL111_Enum;

/* =======================================================  PINCFG112  ======================================================= */
/* ============================================  GPIO PINCFG112 OUTCFG112 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG112_OUTCFG112                                                  */
  GPIO_PINCFG112_OUTCFG112_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG112_OUTCFG112_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG112_OUTCFG112_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG112_OUTCFG112_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG112_OUTCFG112_Enum;

/* ============================================  GPIO PINCFG112 IRPTEN112 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG112_IRPTEN112                                                  */
  GPIO_PINCFG112_IRPTEN112_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG112_IRPTEN112_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG112_IRPTEN112_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG112_IRPTEN112_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG112_IRPTEN112_Enum;

/* ============================================  GPIO PINCFG112 FNCSEL112 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG112_FNCSEL112                                                  */
  GPIO_PINCFG112_FNCSEL112_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG112_FNCSEL112_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG112_FNCSEL112_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG112_FNCSEL112_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG112_FNCSEL112_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG112_FNCSEL112_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG112_FNCSEL112_CT112       = 6,     /*!< CT112 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG112_FNCSEL112_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG112_FNCSEL112_OBSBUS0     = 8,     /*!< OBSBUS0 : Observation bus bit 0                                           */
  GPIO_PINCFG112_FNCSEL112_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG112_FNCSEL112_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG112_FNCSEL112_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG112_FNCSEL112_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG112_FNCSEL112_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG112_FNCSEL112_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG112_FNCSEL112_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG112_FNCSEL112_Enum;

/* =======================================================  PINCFG113  ======================================================= */
/* ============================================  GPIO PINCFG113 OUTCFG113 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG113_OUTCFG113                                                  */
  GPIO_PINCFG113_OUTCFG113_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG113_OUTCFG113_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG113_OUTCFG113_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG113_OUTCFG113_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG113_OUTCFG113_Enum;

/* ============================================  GPIO PINCFG113 IRPTEN113 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG113_IRPTEN113                                                  */
  GPIO_PINCFG113_IRPTEN113_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG113_IRPTEN113_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG113_IRPTEN113_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG113_IRPTEN113_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG113_IRPTEN113_Enum;

/* ============================================  GPIO PINCFG113 FNCSEL113 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG113_FNCSEL113                                                  */
  GPIO_PINCFG113_FNCSEL113_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG113_FNCSEL113_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG113_FNCSEL113_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG113_FNCSEL113_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG113_FNCSEL113_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG113_FNCSEL113_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG113_FNCSEL113_CT113       = 6,     /*!< CT113 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG113_FNCSEL113_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG113_FNCSEL113_OBSBUS1     = 8,     /*!< OBSBUS1 : Observation bus bit 1                                           */
  GPIO_PINCFG113_FNCSEL113_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG113_FNCSEL113_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG113_FNCSEL113_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG113_FNCSEL113_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG113_FNCSEL113_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG113_FNCSEL113_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG113_FNCSEL113_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG113_FNCSEL113_Enum;

/* =======================================================  PINCFG114  ======================================================= */
/* ============================================  GPIO PINCFG114 OUTCFG114 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG114_OUTCFG114                                                  */
  GPIO_PINCFG114_OUTCFG114_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG114_OUTCFG114_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG114_OUTCFG114_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG114_OUTCFG114_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG114_OUTCFG114_Enum;

/* ============================================  GPIO PINCFG114 IRPTEN114 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG114_IRPTEN114                                                  */
  GPIO_PINCFG114_IRPTEN114_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG114_IRPTEN114_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG114_IRPTEN114_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG114_IRPTEN114_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG114_IRPTEN114_Enum;

/* ============================================  GPIO PINCFG114 FNCSEL114 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG114_FNCSEL114                                                  */
  GPIO_PINCFG114_FNCSEL114_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG114_FNCSEL114_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG114_FNCSEL114_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG114_FNCSEL114_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG114_FNCSEL114_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG114_FNCSEL114_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG114_FNCSEL114_CT114       = 6,     /*!< CT114 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG114_FNCSEL114_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG114_FNCSEL114_OBSBUS2     = 8,     /*!< OBSBUS2 : Observation bus bit 2                                           */
  GPIO_PINCFG114_FNCSEL114_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG114_FNCSEL114_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG114_FNCSEL114_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG114_FNCSEL114_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG114_FNCSEL114_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG114_FNCSEL114_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG114_FNCSEL114_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG114_FNCSEL114_Enum;

/* =======================================================  PINCFG115  ======================================================= */
/* ============================================  GPIO PINCFG115 OUTCFG115 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG115_OUTCFG115                                                  */
  GPIO_PINCFG115_OUTCFG115_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG115_OUTCFG115_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG115_OUTCFG115_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG115_OUTCFG115_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG115_OUTCFG115_Enum;

/* ============================================  GPIO PINCFG115 IRPTEN115 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG115_IRPTEN115                                                  */
  GPIO_PINCFG115_IRPTEN115_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG115_IRPTEN115_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG115_IRPTEN115_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG115_IRPTEN115_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG115_IRPTEN115_Enum;

/* ============================================  GPIO PINCFG115 FNCSEL115 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG115_FNCSEL115                                                  */
  GPIO_PINCFG115_FNCSEL115_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG115_FNCSEL115_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG115_FNCSEL115_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG115_FNCSEL115_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG115_FNCSEL115_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG115_FNCSEL115_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG115_FNCSEL115_CT115       = 6,     /*!< CT115 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG115_FNCSEL115_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG115_FNCSEL115_OBSBUS3     = 8,     /*!< OBSBUS3 : Observation bus bit 3                                           */
  GPIO_PINCFG115_FNCSEL115_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG115_FNCSEL115_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG115_FNCSEL115_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG115_FNCSEL115_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG115_FNCSEL115_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG115_FNCSEL115_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG115_FNCSEL115_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG115_FNCSEL115_Enum;

/* =======================================================  PINCFG116  ======================================================= */
/* ============================================  GPIO PINCFG116 OUTCFG116 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG116_OUTCFG116                                                  */
  GPIO_PINCFG116_OUTCFG116_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG116_OUTCFG116_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG116_OUTCFG116_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG116_OUTCFG116_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG116_OUTCFG116_Enum;

/* ============================================  GPIO PINCFG116 IRPTEN116 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG116_IRPTEN116                                                  */
  GPIO_PINCFG116_IRPTEN116_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG116_IRPTEN116_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG116_IRPTEN116_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG116_IRPTEN116_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG116_IRPTEN116_Enum;

/* ============================================  GPIO PINCFG116 FNCSEL116 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG116_FNCSEL116                                                  */
  GPIO_PINCFG116_FNCSEL116_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG116_FNCSEL116_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG116_FNCSEL116_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG116_FNCSEL116_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG116_FNCSEL116_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG116_FNCSEL116_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG116_FNCSEL116_CT116       = 6,     /*!< CT116 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG116_FNCSEL116_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG116_FNCSEL116_OBSBUS4     = 8,     /*!< OBSBUS4 : Observation bus bit 4                                           */
  GPIO_PINCFG116_FNCSEL116_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG116_FNCSEL116_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG116_FNCSEL116_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG116_FNCSEL116_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG116_FNCSEL116_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG116_FNCSEL116_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG116_FNCSEL116_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG116_FNCSEL116_Enum;

/* =======================================================  PINCFG117  ======================================================= */
/* ============================================  GPIO PINCFG117 OUTCFG117 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG117_OUTCFG117                                                  */
  GPIO_PINCFG117_OUTCFG117_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG117_OUTCFG117_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG117_OUTCFG117_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG117_OUTCFG117_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG117_OUTCFG117_Enum;

/* ============================================  GPIO PINCFG117 IRPTEN117 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG117_IRPTEN117                                                  */
  GPIO_PINCFG117_IRPTEN117_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG117_IRPTEN117_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG117_IRPTEN117_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG117_IRPTEN117_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG117_IRPTEN117_Enum;

/* ============================================  GPIO PINCFG117 FNCSEL117 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG117_FNCSEL117                                                  */
  GPIO_PINCFG117_FNCSEL117_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG117_FNCSEL117_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG117_FNCSEL117_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG117_FNCSEL117_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG117_FNCSEL117_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG117_FNCSEL117_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG117_FNCSEL117_CT117       = 6,     /*!< CT117 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG117_FNCSEL117_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG117_FNCSEL117_OBSBUS5     = 8,     /*!< OBSBUS5 : Observation bus bit 5                                           */
  GPIO_PINCFG117_FNCSEL117_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG117_FNCSEL117_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG117_FNCSEL117_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG117_FNCSEL117_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG117_FNCSEL117_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG117_FNCSEL117_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG117_FNCSEL117_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG117_FNCSEL117_Enum;

/* =======================================================  PINCFG118  ======================================================= */
/* ============================================  GPIO PINCFG118 OUTCFG118 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG118_OUTCFG118                                                  */
  GPIO_PINCFG118_OUTCFG118_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG118_OUTCFG118_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG118_OUTCFG118_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG118_OUTCFG118_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG118_OUTCFG118_Enum;

/* ============================================  GPIO PINCFG118 IRPTEN118 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG118_IRPTEN118                                                  */
  GPIO_PINCFG118_IRPTEN118_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG118_IRPTEN118_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG118_IRPTEN118_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG118_IRPTEN118_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG118_IRPTEN118_Enum;

/* ============================================  GPIO PINCFG118 FNCSEL118 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG118_FNCSEL118                                                  */
  GPIO_PINCFG118_FNCSEL118_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG118_FNCSEL118_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG118_FNCSEL118_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG118_FNCSEL118_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG118_FNCSEL118_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG118_FNCSEL118_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG118_FNCSEL118_CT118       = 6,     /*!< CT118 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG118_FNCSEL118_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG118_FNCSEL118_OBSBUS6     = 8,     /*!< OBSBUS6 : Observation bus bit 6                                           */
  GPIO_PINCFG118_FNCSEL118_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG118_FNCSEL118_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG118_FNCSEL118_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG118_FNCSEL118_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG118_FNCSEL118_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG118_FNCSEL118_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG118_FNCSEL118_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG118_FNCSEL118_Enum;

/* =======================================================  PINCFG119  ======================================================= */
/* ============================================  GPIO PINCFG119 OUTCFG119 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG119_OUTCFG119                                                  */
  GPIO_PINCFG119_OUTCFG119_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG119_OUTCFG119_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG119_OUTCFG119_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG119_OUTCFG119_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG119_OUTCFG119_Enum;

/* ============================================  GPIO PINCFG119 IRPTEN119 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG119_IRPTEN119                                                  */
  GPIO_PINCFG119_IRPTEN119_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG119_IRPTEN119_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG119_IRPTEN119_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG119_IRPTEN119_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG119_IRPTEN119_Enum;

/* ============================================  GPIO PINCFG119 FNCSEL119 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG119_FNCSEL119                                                  */
  GPIO_PINCFG119_FNCSEL119_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG119_FNCSEL119_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG119_FNCSEL119_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG119_FNCSEL119_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG119_FNCSEL119_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG119_FNCSEL119_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG119_FNCSEL119_CT119       = 6,     /*!< CT119 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG119_FNCSEL119_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG119_FNCSEL119_OBSBUS7     = 8,     /*!< OBSBUS7 : Observation bus bit 7                                           */
  GPIO_PINCFG119_FNCSEL119_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG119_FNCSEL119_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG119_FNCSEL119_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG119_FNCSEL119_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG119_FNCSEL119_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG119_FNCSEL119_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG119_FNCSEL119_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG119_FNCSEL119_Enum;

/* =======================================================  PINCFG120  ======================================================= */
/* ============================================  GPIO PINCFG120 OUTCFG120 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG120_OUTCFG120                                                  */
  GPIO_PINCFG120_OUTCFG120_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG120_OUTCFG120_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG120_OUTCFG120_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG120_OUTCFG120_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG120_OUTCFG120_Enum;

/* ============================================  GPIO PINCFG120 IRPTEN120 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG120_IRPTEN120                                                  */
  GPIO_PINCFG120_IRPTEN120_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG120_IRPTEN120_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG120_IRPTEN120_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG120_IRPTEN120_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG120_IRPTEN120_Enum;

/* ============================================  GPIO PINCFG120 FNCSEL120 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG120_FNCSEL120                                                  */
  GPIO_PINCFG120_FNCSEL120_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG120_FNCSEL120_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG120_FNCSEL120_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG120_FNCSEL120_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG120_FNCSEL120_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG120_FNCSEL120_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG120_FNCSEL120_CT120       = 6,     /*!< CT120 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG120_FNCSEL120_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG120_FNCSEL120_OBSBUS8     = 8,     /*!< OBSBUS8 : Observation bus bit 8                                           */
  GPIO_PINCFG120_FNCSEL120_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG120_FNCSEL120_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG120_FNCSEL120_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG120_FNCSEL120_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG120_FNCSEL120_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG120_FNCSEL120_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG120_FNCSEL120_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG120_FNCSEL120_Enum;

/* =======================================================  PINCFG121  ======================================================= */
/* ============================================  GPIO PINCFG121 OUTCFG121 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG121_OUTCFG121                                                  */
  GPIO_PINCFG121_OUTCFG121_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG121_OUTCFG121_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG121_OUTCFG121_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG121_OUTCFG121_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG121_OUTCFG121_Enum;

/* ============================================  GPIO PINCFG121 IRPTEN121 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG121_IRPTEN121                                                  */
  GPIO_PINCFG121_IRPTEN121_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG121_IRPTEN121_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG121_IRPTEN121_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG121_IRPTEN121_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG121_IRPTEN121_Enum;

/* ============================================  GPIO PINCFG121 FNCSEL121 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG121_FNCSEL121                                                  */
  GPIO_PINCFG121_FNCSEL121_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG121_FNCSEL121_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG121_FNCSEL121_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG121_FNCSEL121_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG121_FNCSEL121_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG121_FNCSEL121_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG121_FNCSEL121_CT121       = 6,     /*!< CT121 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG121_FNCSEL121_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG121_FNCSEL121_OBSBUS9     = 8,     /*!< OBSBUS9 : Observation bus bit 9                                           */
  GPIO_PINCFG121_FNCSEL121_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG121_FNCSEL121_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG121_FNCSEL121_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG121_FNCSEL121_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG121_FNCSEL121_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG121_FNCSEL121_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG121_FNCSEL121_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG121_FNCSEL121_Enum;

/* =======================================================  PINCFG122  ======================================================= */
/* ============================================  GPIO PINCFG122 OUTCFG122 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG122_OUTCFG122                                                  */
  GPIO_PINCFG122_OUTCFG122_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG122_OUTCFG122_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG122_OUTCFG122_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG122_OUTCFG122_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG122_OUTCFG122_Enum;

/* ============================================  GPIO PINCFG122 IRPTEN122 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG122_IRPTEN122                                                  */
  GPIO_PINCFG122_IRPTEN122_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG122_IRPTEN122_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG122_IRPTEN122_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG122_IRPTEN122_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG122_IRPTEN122_Enum;

/* ============================================  GPIO PINCFG122 FNCSEL122 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG122_FNCSEL122                                                  */
  GPIO_PINCFG122_FNCSEL122_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG122_FNCSEL122_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG122_FNCSEL122_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG122_FNCSEL122_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG122_FNCSEL122_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG122_FNCSEL122_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG122_FNCSEL122_CT122       = 6,     /*!< CT122 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG122_FNCSEL122_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG122_FNCSEL122_OBSBUS10    = 8,     /*!< OBSBUS10 : Observation bus bit 10                                         */
  GPIO_PINCFG122_FNCSEL122_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG122_FNCSEL122_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG122_FNCSEL122_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG122_FNCSEL122_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG122_FNCSEL122_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG122_FNCSEL122_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG122_FNCSEL122_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG122_FNCSEL122_Enum;

/* =======================================================  PINCFG123  ======================================================= */
/* ============================================  GPIO PINCFG123 OUTCFG123 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG123_OUTCFG123                                                  */
  GPIO_PINCFG123_OUTCFG123_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG123_OUTCFG123_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG123_OUTCFG123_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG123_OUTCFG123_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG123_OUTCFG123_Enum;

/* ============================================  GPIO PINCFG123 IRPTEN123 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG123_IRPTEN123                                                  */
  GPIO_PINCFG123_IRPTEN123_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG123_IRPTEN123_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG123_IRPTEN123_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG123_IRPTEN123_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG123_IRPTEN123_Enum;

/* ============================================  GPIO PINCFG123 FNCSEL123 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG123_FNCSEL123                                                  */
  GPIO_PINCFG123_FNCSEL123_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG123_FNCSEL123_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG123_FNCSEL123_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG123_FNCSEL123_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG123_FNCSEL123_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG123_FNCSEL123_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG123_FNCSEL123_CT123       = 6,     /*!< CT123 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG123_FNCSEL123_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG123_FNCSEL123_OBSBUS11    = 8,     /*!< OBSBUS11 : Observation bus bit 11                                         */
  GPIO_PINCFG123_FNCSEL123_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG123_FNCSEL123_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG123_FNCSEL123_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG123_FNCSEL123_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG123_FNCSEL123_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG123_FNCSEL123_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG123_FNCSEL123_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG123_FNCSEL123_Enum;

/* =======================================================  PINCFG124  ======================================================= */
/* ============================================  GPIO PINCFG124 OUTCFG124 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG124_OUTCFG124                                                  */
  GPIO_PINCFG124_OUTCFG124_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG124_OUTCFG124_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG124_OUTCFG124_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG124_OUTCFG124_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG124_OUTCFG124_Enum;

/* ============================================  GPIO PINCFG124 IRPTEN124 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG124_IRPTEN124                                                  */
  GPIO_PINCFG124_IRPTEN124_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG124_IRPTEN124_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG124_IRPTEN124_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG124_IRPTEN124_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG124_IRPTEN124_Enum;

/* ============================================  GPIO PINCFG124 FNCSEL124 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG124_FNCSEL124                                                  */
  GPIO_PINCFG124_FNCSEL124_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG124_FNCSEL124_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG124_FNCSEL124_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG124_FNCSEL124_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG124_FNCSEL124_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG124_FNCSEL124_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG124_FNCSEL124_CT124       = 6,     /*!< CT124 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG124_FNCSEL124_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG124_FNCSEL124_OBSBUS12    = 8,     /*!< OBSBUS12 : Observation bus bit 12                                         */
  GPIO_PINCFG124_FNCSEL124_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG124_FNCSEL124_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG124_FNCSEL124_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG124_FNCSEL124_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG124_FNCSEL124_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG124_FNCSEL124_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG124_FNCSEL124_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG124_FNCSEL124_Enum;

/* =======================================================  PINCFG125  ======================================================= */
/* ============================================  GPIO PINCFG125 OUTCFG125 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG125_OUTCFG125                                                  */
  GPIO_PINCFG125_OUTCFG125_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG125_OUTCFG125_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG125_OUTCFG125_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG125_OUTCFG125_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG125_OUTCFG125_Enum;

/* ============================================  GPIO PINCFG125 IRPTEN125 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG125_IRPTEN125                                                  */
  GPIO_PINCFG125_IRPTEN125_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG125_IRPTEN125_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG125_IRPTEN125_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG125_IRPTEN125_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG125_IRPTEN125_Enum;

/* ============================================  GPIO PINCFG125 FNCSEL125 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG125_FNCSEL125                                                  */
  GPIO_PINCFG125_FNCSEL125_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG125_FNCSEL125_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG125_FNCSEL125_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG125_FNCSEL125_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG125_FNCSEL125_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG125_FNCSEL125_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG125_FNCSEL125_CT125       = 6,     /*!< CT125 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG125_FNCSEL125_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG125_FNCSEL125_OBSBUS13    = 8,     /*!< OBSBUS13 : Observation bus bit 13                                         */
  GPIO_PINCFG125_FNCSEL125_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG125_FNCSEL125_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG125_FNCSEL125_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG125_FNCSEL125_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG125_FNCSEL125_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG125_FNCSEL125_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG125_FNCSEL125_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG125_FNCSEL125_Enum;

/* =======================================================  PINCFG126  ======================================================= */
/* ============================================  GPIO PINCFG126 OUTCFG126 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG126_OUTCFG126                                                  */
  GPIO_PINCFG126_OUTCFG126_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG126_OUTCFG126_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG126_OUTCFG126_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG126_OUTCFG126_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG126_OUTCFG126_Enum;

/* ============================================  GPIO PINCFG126 IRPTEN126 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG126_IRPTEN126                                                  */
  GPIO_PINCFG126_IRPTEN126_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG126_IRPTEN126_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG126_IRPTEN126_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG126_IRPTEN126_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG126_IRPTEN126_Enum;

/* ============================================  GPIO PINCFG126 FNCSEL126 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG126_FNCSEL126                                                  */
  GPIO_PINCFG126_FNCSEL126_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG126_FNCSEL126_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG126_FNCSEL126_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG126_FNCSEL126_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG126_FNCSEL126_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG126_FNCSEL126_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG126_FNCSEL126_CT126       = 6,     /*!< CT126 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG126_FNCSEL126_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG126_FNCSEL126_OBSBUS14    = 8,     /*!< OBSBUS14 : Observation bus bit 14                                         */
  GPIO_PINCFG126_FNCSEL126_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG126_FNCSEL126_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG126_FNCSEL126_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG126_FNCSEL126_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG126_FNCSEL126_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG126_FNCSEL126_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG126_FNCSEL126_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG126_FNCSEL126_Enum;

/* =======================================================  PINCFG127  ======================================================= */
/* ============================================  GPIO PINCFG127 OUTCFG127 [8..9]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG127_OUTCFG127                                                  */
  GPIO_PINCFG127_OUTCFG127_DIS         = 0,     /*!< DIS : Output Disabled                                                     */
  GPIO_PINCFG127_OUTCFG127_PUSHPULL    = 1,     /*!< PUSHPULL : Output configured in push pull mode. Will drive 0
                                                     and 1 values on pin.                                                      */
  GPIO_PINCFG127_OUTCFG127_OD          = 2,     /*!< OD : Output configured in open drain mode. Will only drive pin
                                                     low, tristate otherwise.                                                  */
  GPIO_PINCFG127_OUTCFG127_TS          = 3,     /*!< TS : Output configured in Tristate-able push pull mode. Will
                                                     drive 0, 1 of HiZ on pin.                                                 */
} GPIO_PINCFG127_OUTCFG127_Enum;

/* ============================================  GPIO PINCFG127 IRPTEN127 [6..7]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG127_IRPTEN127                                                  */
  GPIO_PINCFG127_IRPTEN127_DIS         = 0,     /*!< DIS : Interrupts are disabled for this GPIO                               */
  GPIO_PINCFG127_IRPTEN127_INTFALL     = 1,     /*!< INTFALL : Interrupts are enabled for falling edge transition
                                                     on this GPIO                                                              */
  GPIO_PINCFG127_IRPTEN127_INTRISE     = 2,     /*!< INTRISE : Interrupts are enabled for rising edge transitions
                                                     on this GPIO                                                              */
  GPIO_PINCFG127_IRPTEN127_INTANY      = 3,     /*!< INTANY : Interrupts are enabled for any edge transition on this
                                                     GPIO                                                                      */
} GPIO_PINCFG127_IRPTEN127_Enum;

/* ============================================  GPIO PINCFG127 FNCSEL127 [0..3]  ============================================ */
typedef enum {                                  /*!< GPIO_PINCFG127_FNCSEL127                                                  */
  GPIO_PINCFG127_FNCSEL127_RESERVED0   = 0,     /*!< RESERVED0 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG127_FNCSEL127_RESERVED1   = 1,     /*!< RESERVED1 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG127_FNCSEL127_RESERVED2   = 2,     /*!< RESERVED2 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG127_FNCSEL127_GPIO        = 3,     /*!< GPIO : General purpose I/O                                                */
  GPIO_PINCFG127_FNCSEL127_RESERVED4   = 4,     /*!< RESERVED4 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG127_FNCSEL127_RESERVED5   = 5,     /*!< RESERVED5 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG127_FNCSEL127_CT127       = 6,     /*!< CT127 : Timer/Counter input or output; Selection of direction
                                                     is done via CTIMER register settings.                                     */
  GPIO_PINCFG127_FNCSEL127_RESERVED7   = 7,     /*!< RESERVED7 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG127_FNCSEL127_OBSBUS15    = 8,     /*!< OBSBUS15 : Observation bus bit 15                                         */
  GPIO_PINCFG127_FNCSEL127_RESERVED9   = 9,     /*!< RESERVED9 : Reserved selection. Operation unknown if selected.            */
  GPIO_PINCFG127_FNCSEL127_RESERVED10  = 10,    /*!< RESERVED10 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG127_FNCSEL127_RESERVED11  = 11,    /*!< RESERVED11 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG127_FNCSEL127_RESERVED12  = 12,    /*!< RESERVED12 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG127_FNCSEL127_RESERVED13  = 13,    /*!< RESERVED13 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG127_FNCSEL127_RESERVED14  = 14,    /*!< RESERVED14 : Reserved selection. Operation unknown if selected.           */
  GPIO_PINCFG127_FNCSEL127_RESERVED15  = 15,    /*!< RESERVED15 : Reserved selection. Operation unknown if selected.           */
} GPIO_PINCFG127_FNCSEL127_Enum;

/* ========================================================  PADKEY  ========================================================= */
/* ==============================================  GPIO PADKEY PADKEY [0..31]  =============================================== */
typedef enum {                                  /*!< GPIO_PADKEY_PADKEY                                                        */
  GPIO_PADKEY_PADKEY_Key               = 115,   /*!< Key : Key value to unlock the register.                                   */
} GPIO_PADKEY_PADKEY_Enum;

/* ==========================================================  RD0  ========================================================== */
/* ==========================================================  RD1  ========================================================== */
/* ==========================================================  RD2  ========================================================== */
/* ==========================================================  RD3  ========================================================== */
/* ==========================================================  WT0  ========================================================== */
/* ==========================================================  WT1  ========================================================== */
/* ==========================================================  WT2  ========================================================== */
/* ==========================================================  WT3  ========================================================== */
/* =========================================================  WTS0  ========================================================== */
/* =========================================================  WTS1  ========================================================== */
/* =========================================================  WTS2  ========================================================== */
/* =========================================================  WTS3  ========================================================== */
/* =========================================================  WTC0  ========================================================== */
/* =========================================================  WTC1  ========================================================== */
/* =========================================================  WTC2  ========================================================== */
/* =========================================================  WTC3  ========================================================== */
/* ==========================================================  EN0  ========================================================== */
/* ==========================================================  EN1  ========================================================== */
/* ==========================================================  EN2  ========================================================== */
/* ==========================================================  EN3  ========================================================== */
/* =========================================================  ENS0  ========================================================== */
/* =========================================================  ENS1  ========================================================== */
/* =========================================================  ENS2  ========================================================== */
/* =========================================================  ENS3  ========================================================== */
/* =========================================================  ENC0  ========================================================== */
/* =========================================================  ENC1  ========================================================== */
/* =========================================================  ENC2  ========================================================== */
/* =========================================================  ENC3  ========================================================== */
/* ========================================================  IOM0IRQ  ======================================================== */
/* ========================================================  IOM1IRQ  ======================================================== */
/* ========================================================  IOM2IRQ  ======================================================== */
/* ========================================================  IOM3IRQ  ======================================================== */
/* ========================================================  IOM4IRQ  ======================================================== */
/* ========================================================  IOM5IRQ  ======================================================== */
/* ========================================================  IOM6IRQ  ======================================================== */
/* ========================================================  IOM7IRQ  ======================================================== */
/* =======================================================  SDIFCDWP  ======================================================== */
/* ========================================================  OBSDATA  ======================================================== */
/* ========================================================  IEOBS0  ========================================================= */
/* ========================================================  IEOBS1  ========================================================= */
/* ========================================================  IEOBS2  ========================================================= */
/* ========================================================  IEOBS3  ========================================================= */
/* ========================================================  OEOBS0  ========================================================= */
/* ========================================================  OEOBS1  ========================================================= */
/* ========================================================  OEOBS2  ========================================================= */
/* ========================================================  OEOBS3  ========================================================= */
/* ======================================================  MCUN0INT0EN  ====================================================== */
/* =====================================================  MCUN0INT0STAT  ===================================================== */
/* =====================================================  MCUN0INT0CLR  ====================================================== */
/* =====================================================  MCUN0INT0SET  ====================================================== */
/* ======================================================  MCUN0INT1EN  ====================================================== */
/* =====================================================  MCUN0INT1STAT  ===================================================== */
/* =====================================================  MCUN0INT1CLR  ====================================================== */
/* =====================================================  MCUN0INT1SET  ====================================================== */
/* ======================================================  MCUN0INT2EN  ====================================================== */
/* =====================================================  MCUN0INT2STAT  ===================================================== */
/* =====================================================  MCUN0INT2CLR  ====================================================== */
/* =====================================================  MCUN0INT2SET  ====================================================== */
/* ======================================================  MCUN0INT3EN  ====================================================== */
/* =====================================================  MCUN0INT3STAT  ===================================================== */
/* =====================================================  MCUN0INT3CLR  ====================================================== */
/* =====================================================  MCUN0INT3SET  ====================================================== */
/* ======================================================  MCUN1INT0EN  ====================================================== */
/* =====================================================  MCUN1INT0STAT  ===================================================== */
/* =====================================================  MCUN1INT0CLR  ====================================================== */
/* =====================================================  MCUN1INT0SET  ====================================================== */
/* ======================================================  MCUN1INT1EN  ====================================================== */
/* =====================================================  MCUN1INT1STAT  ===================================================== */
/* =====================================================  MCUN1INT1CLR  ====================================================== */
/* =====================================================  MCUN1INT1SET  ====================================================== */
/* ======================================================  MCUN1INT2EN  ====================================================== */
/* =====================================================  MCUN1INT2STAT  ===================================================== */
/* =====================================================  MCUN1INT2CLR  ====================================================== */
/* =====================================================  MCUN1INT2SET  ====================================================== */
/* ======================================================  MCUN1INT3EN  ====================================================== */
/* =====================================================  MCUN1INT3STAT  ===================================================== */
/* =====================================================  MCUN1INT3CLR  ====================================================== */
/* =====================================================  MCUN1INT3SET  ====================================================== */
/* =====================================================  DSP0N0INT0EN  ====================================================== */
/* ====================================================  DSP0N0INT0STAT  ===================================================== */
/* =====================================================  DSP0N0INT0CLR  ===================================================== */
/* =====================================================  DSP0N0INT0SET  ===================================================== */
/* =====================================================  DSP0N0INT1EN  ====================================================== */
/* ====================================================  DSP0N0INT1STAT  ===================================================== */
/* =====================================================  DSP0N0INT1CLR  ===================================================== */
/* =====================================================  DSP0N0INT1SET  ===================================================== */
/* =====================================================  DSP0N0INT2EN  ====================================================== */
/* ====================================================  DSP0N0INT2STAT  ===================================================== */
/* =====================================================  DSP0N0INT2CLR  ===================================================== */
/* =====================================================  DSP0N0INT2SET  ===================================================== */
/* =====================================================  DSP0N0INT3EN  ====================================================== */
/* ====================================================  DSP0N0INT3STAT  ===================================================== */
/* =====================================================  DSP0N0INT3CLR  ===================================================== */
/* =====================================================  DSP0N0INT3SET  ===================================================== */
/* =====================================================  DSP0N1INT0EN  ====================================================== */
/* ====================================================  DSP0N1INT0STAT  ===================================================== */
/* =====================================================  DSP0N1INT0CLR  ===================================================== */
/* =====================================================  DSP0N1INT0SET  ===================================================== */
/* =====================================================  DSP0N1INT1EN  ====================================================== */
/* ====================================================  DSP0N1INT1STAT  ===================================================== */
/* =====================================================  DSP0N1INT1CLR  ===================================================== */
/* =====================================================  DSP0N1INT1SET  ===================================================== */
/* =====================================================  DSP0N1INT2EN  ====================================================== */
/* ====================================================  DSP0N1INT2STAT  ===================================================== */
/* =====================================================  DSP0N1INT2CLR  ===================================================== */
/* =====================================================  DSP0N1INT2SET  ===================================================== */
/* =====================================================  DSP0N1INT3EN  ====================================================== */
/* ====================================================  DSP0N1INT3STAT  ===================================================== */
/* =====================================================  DSP0N1INT3CLR  ===================================================== */
/* =====================================================  DSP0N1INT3SET  ===================================================== */
/* =====================================================  DSP1N0INT0EN  ====================================================== */
/* ====================================================  DSP1N0INT0STAT  ===================================================== */
/* =====================================================  DSP1N0INT0CLR  ===================================================== */
/* =====================================================  DSP1N0INT0SET  ===================================================== */
/* =====================================================  DSP1N0INT1EN  ====================================================== */
/* ====================================================  DSP1N0INT1STAT  ===================================================== */
/* =====================================================  DSP1N0INT1CLR  ===================================================== */
/* =====================================================  DSP1N0INT1SET  ===================================================== */
/* =====================================================  DSP1N0INT2EN  ====================================================== */
/* ====================================================  DSP1N0INT2STAT  ===================================================== */
/* =====================================================  DSP1N0INT2CLR  ===================================================== */
/* =====================================================  DSP1N0INT2SET  ===================================================== */
/* =====================================================  DSP1N0INT3EN  ====================================================== */
/* ====================================================  DSP1N0INT3STAT  ===================================================== */
/* =====================================================  DSP1N0INT3CLR  ===================================================== */
/* =====================================================  DSP1N0INT3SET  ===================================================== */
/* =====================================================  DSP1N1INT0EN  ====================================================== */
/* ====================================================  DSP1N1INT0STAT  ===================================================== */
/* =====================================================  DSP1N1INT0CLR  ===================================================== */
/* =====================================================  DSP1N1INT0SET  ===================================================== */
/* =====================================================  DSP1N1INT1EN  ====================================================== */
/* ====================================================  DSP1N1INT1STAT  ===================================================== */
/* =====================================================  DSP1N1INT1CLR  ===================================================== */
/* =====================================================  DSP1N1INT1SET  ===================================================== */
/* =====================================================  DSP1N1INT2EN  ====================================================== */
/* ====================================================  DSP1N1INT2STAT  ===================================================== */
/* =====================================================  DSP1N1INT2CLR  ===================================================== */
/* =====================================================  DSP1N1INT2SET  ===================================================== */
/* =====================================================  DSP1N1INT3EN  ====================================================== */
/* ====================================================  DSP1N1INT3STAT  ===================================================== */
/* =====================================================  DSP1N1INT3CLR  ===================================================== */
/* =====================================================  DSP1N1INT3SET  ===================================================== */


/* =========================================================================================================================== */
/* ================                                            GPU                                            ================ */
/* =========================================================================================================================== */

/* =======================================================  TEX0BASE  ======================================================== */
/* ======================================================  TEX0STRIDE  ======================================================= */
/* ============================================  GPU TEX0STRIDE IMGFMT [24..31]  ============================================= */
typedef enum {                                  /*!< GPU_TEX0STRIDE_IMGFMT                                                     */
  GPU_TEX0STRIDE_IMGFMT_RGBX8888       = 0,     /*!< RGBX8888 : Color Space RGBX means, that the pixel format still
                                                     has an alpha channel, but it is ignored, and is always
                                                     set to 255. The RGBX 32 bit RGB format is stored in memory
                                                     as 8 red bits, 8 green bits, 8 blue bits, and 8 ignored
                                                     bits.                                                                     */
  GPU_TEX0STRIDE_IMGFMT_RGBA8888       = 1,     /*!< RGBA8888 : Color Space RED GREEN BLUE ALPHA (internal format
                                                     is always on: 32-bit)                                                     */
  GPU_TEX0STRIDE_IMGFMT_XRGB8888       = 2,     /*!< XRGB8888 : Color Space                                                    */
  GPU_TEX0STRIDE_IMGFMT_ARGB8888       = 3,     /*!< ARGB8888 : Color Space In the ARGB (word-order) encoding the
                                                     intensity of each channel sample is defined by 8 bits,
                                                     and are arranged in memory in such manner that a single
                                                     32-bit unsigned integer has the alpha sample in the highest
                                                     8 bits, followed by the red sample, green sample and finally
                                                     the blue sample in the lowest 8 bits                                      */
  GPU_TEX0STRIDE_IMGFMT_RGBA565        = 4,     /*!< RGBA565 : Color Space RED(5-bits) GREEN(6-bits) BLUE (5-bits)             */
  GPU_TEX0STRIDE_IMGFMT_RGBA5551       = 5,     /*!< RGBA5551 : Color Space Red,green,blue,alpha (transparency).               */
  GPU_TEX0STRIDE_IMGFMT_L8             = 9,     /*!< L8 : Color Space Lum8 grayscale                                           */
  GPU_TEX0STRIDE_IMGFMT_TSC4           = 18,    /*!< TSC4 : Color Space Proprietary texture compression                        */
  GPU_TEX0STRIDE_IMGFMT_TSC6           = 22,    /*!< TSC6 : Color Space Optional proprietary texture compression               */
  GPU_TEX0STRIDE_IMGFMT_TSC6A          = 23,    /*!< TSC6A : Color Space Optional proprietary texture compression              */
} GPU_TEX0STRIDE_IMGFMT_Enum;

/* ============================================  GPU TEX0STRIDE IMGMODE [16..23]  ============================================ */
typedef enum {                                  /*!< GPU_TEX0STRIDE_IMGMODE                                                    */
  GPU_TEX0STRIDE_IMGMODE_POINTSAMPLE   = 0,     /*!< POINTSAMPLE : Texture mapping: rotate, resize and distort a
                                                     bitmap image. Nearest neighbor sampling.                                  */
  GPU_TEX0STRIDE_IMGMODE_BILINEARFILTERING = 1, /*!< BILINEARFILTERING : Texture mapping: rotate, resize and distort
                                                     a bitmap image. A method used to smooth textures when displayed
                                                     larger or smaller than they actually are.                                 */
} GPU_TEX0STRIDE_IMGMODE_Enum;

/* ========================================================  TEX0RES  ======================================================== */
/* =======================================================  TEX1BASE  ======================================================== */
/* ======================================================  TEX1STRIDE  ======================================================= */
/* ============================================  GPU TEX1STRIDE IMGFMT [24..31]  ============================================= */
typedef enum {                                  /*!< GPU_TEX1STRIDE_IMGFMT                                                     */
  GPU_TEX1STRIDE_IMGFMT_RGBX8888       = 0,     /*!< RGBX8888 : Color Space RGBX means, that the pixel format still
                                                     has an alpha channel, but it is ignored, and is always
                                                     set to 255. The RGBX 32 bit RGB format is stored in memory
                                                     as 8 red bits, 8 green bits, 8 blue bits, and 8 ignored
                                                     bits.                                                                     */
  GPU_TEX1STRIDE_IMGFMT_RGBA8888       = 1,     /*!< RGBA8888 : Color Space RED GREEN BLUE ALPHA (internal format
                                                     is always on: 32-bit)                                                     */
  GPU_TEX1STRIDE_IMGFMT_XRGB8888       = 2,     /*!< XRGB8888 : Color Space                                                    */
  GPU_TEX1STRIDE_IMGFMT_ARGB8888       = 3,     /*!< ARGB8888 : Color Space In the ARGB (word-order) encoding the
                                                     intensity of each channel sample is defined by 8 bits,
                                                     and are arranged in memory in such manner that a single
                                                     32-bit unsigned integer has the alpha sample in the highest
                                                     8 bits, followed by the red sample, green sample and finally
                                                     the blue sample in the lowest 8 bits                                      */
  GPU_TEX1STRIDE_IMGFMT_RGBA565        = 4,     /*!< RGBA565 : Color Space RED(5-bits) GREEN(6-bits) BLUE (5-bits)             */
  GPU_TEX1STRIDE_IMGFMT_RGBA5551       = 5,     /*!< RGBA5551 : Color Space Red,green,blue,alpha (transparency).               */
  GPU_TEX1STRIDE_IMGFMT_L8             = 9,     /*!< L8 : Color Space Lum8 grayscale                                           */
  GPU_TEX1STRIDE_IMGFMT_TSC4           = 18,    /*!< TSC4 : Color Space Proprietary texture compression                        */
  GPU_TEX1STRIDE_IMGFMT_TSC6           = 22,    /*!< TSC6 : Color Space Optional proprietary texture compression               */
  GPU_TEX1STRIDE_IMGFMT_TSC6A          = 23,    /*!< TSC6A : Color Space Optional proprietary texture compression              */
} GPU_TEX1STRIDE_IMGFMT_Enum;

/* ============================================  GPU TEX1STRIDE IMGMODE [16..23]  ============================================ */
typedef enum {                                  /*!< GPU_TEX1STRIDE_IMGMODE                                                    */
  GPU_TEX1STRIDE_IMGMODE_POINTSAMPLE   = 0,     /*!< POINTSAMPLE : Texture mapping: rotate, resize and distort a
                                                     bitmap image. Nearest neighbor sampling.                                  */
  GPU_TEX1STRIDE_IMGMODE_BILINEARFILTERING = 1, /*!< BILINEARFILTERING : Texture mapping: rotate, resize and distort
                                                     a bitmap image. A method used to smooth textures when displayed
                                                     larger or smaller than they actually are.                                 */
} GPU_TEX1STRIDE_IMGMODE_Enum;

/* ========================================================  TEX1RES  ======================================================== */
/* =======================================================  TEX1COLOR  ======================================================= */
/* =======================================================  TEX2BASE  ======================================================== */
/* ======================================================  TEX2STRIDE  ======================================================= */
/* ============================================  GPU TEX2STRIDE IMGFMT [24..31]  ============================================= */
typedef enum {                                  /*!< GPU_TEX2STRIDE_IMGFMT                                                     */
  GPU_TEX2STRIDE_IMGFMT_RGBX8888       = 0,     /*!< RGBX8888 : Color Space RGBX means, that the pixel format still
                                                     has an alpha channel, but it is ignored, and is always
                                                     set to 255. The RGBX 32 bit RGB format is stored in memory
                                                     as 8 red bits, 8 green bits, 8 blue bits, and 8 ignored
                                                     bits.                                                                     */
  GPU_TEX2STRIDE_IMGFMT_RGBA8888       = 1,     /*!< RGBA8888 : Color Space RED GREEN BLUE ALPHA (internal format
                                                     is always on: 32-bit)                                                     */
  GPU_TEX2STRIDE_IMGFMT_XRGB8888       = 2,     /*!< XRGB8888 : Color Space                                                    */
  GPU_TEX2STRIDE_IMGFMT_ARGB8888       = 3,     /*!< ARGB8888 : Color Space In the ARGB (word-order) encoding the
                                                     intensity of each channel sample is defined by 8 bits,
                                                     and are arranged in memory in such manner that a single
                                                     32-bit unsigned integer has the alpha sample in the highest
                                                     8 bits, followed by the red sample, green sample and finally
                                                     the blue sample in the lowest 8 bits                                      */
  GPU_TEX2STRIDE_IMGFMT_RGBA565        = 4,     /*!< RGBA565 : Color Space RED(5-bits) GREEN(6-bits) BLUE (5-bits)             */
  GPU_TEX2STRIDE_IMGFMT_RGBA5551       = 5,     /*!< RGBA5551 : Color Space Red,green,blue,alpha (transparency).               */
  GPU_TEX2STRIDE_IMGFMT_L8             = 9,     /*!< L8 : Color Space Lum8 grayscale                                           */
  GPU_TEX2STRIDE_IMGFMT_TSC4           = 18,    /*!< TSC4 : Color Space Proprietary texture compression                        */
  GPU_TEX2STRIDE_IMGFMT_TSC6           = 22,    /*!< TSC6 : Color Space Optional proprietary texture compression               */
  GPU_TEX2STRIDE_IMGFMT_TSC6A          = 23,    /*!< TSC6A : Color Space Optional proprietary texture compression              */
} GPU_TEX2STRIDE_IMGFMT_Enum;

/* ============================================  GPU TEX2STRIDE IMGMODE [16..23]  ============================================ */
typedef enum {                                  /*!< GPU_TEX2STRIDE_IMGMODE                                                    */
  GPU_TEX2STRIDE_IMGMODE_POINTSAMPLE   = 0,     /*!< POINTSAMPLE : Texture mapping: rotate, resize and distort a
                                                     bitmap image. Nearest neighbor sampling.                                  */
  GPU_TEX2STRIDE_IMGMODE_BILINEARFILTERING = 1, /*!< BILINEARFILTERING : Texture mapping: rotate, resize and distort
                                                     a bitmap image. A method used to smooth textures when displayed
                                                     larger or smaller than they actually are.                                 */
} GPU_TEX2STRIDE_IMGMODE_Enum;

/* ========================================================  TEX2RES  ======================================================== */
/* =======================================================  TEX3BASE  ======================================================== */
/* ======================================================  TEX3STRIDE  ======================================================= */
/* ============================================  GPU TEX3STRIDE IMGFMT [24..31]  ============================================= */
typedef enum {                                  /*!< GPU_TEX3STRIDE_IMGFMT                                                     */
  GPU_TEX3STRIDE_IMGFMT_RGBX8888       = 0,     /*!< RGBX8888 : Color Space RGBX means, that the pixel format still
                                                     has an alpha channel, but it is ignored, and is always
                                                     set to 255. The RGBX 32 bit RGB format is stored in memory
                                                     as 8 red bits, 8 green bits, 8 blue bits, and 8 ignored
                                                     bits.                                                                     */
  GPU_TEX3STRIDE_IMGFMT_RGBA8888       = 1,     /*!< RGBA8888 : Color Space RED GREEN BLUE ALPHA (internal format
                                                     is always on: 32-bit)                                                     */
  GPU_TEX3STRIDE_IMGFMT_XRGB8888       = 2,     /*!< XRGB8888 : Color Space                                                    */
  GPU_TEX3STRIDE_IMGFMT_ARGB8888       = 3,     /*!< ARGB8888 : Color Space In the ARGB (word-order) encoding the
                                                     intensity of each channel sample is defined by 8 bits,
                                                     and are arranged in memory in such manner that a single
                                                     32-bit unsigned integer has the alpha sample in the highest
                                                     8 bits, followed by the red sample, green sample and finally
                                                     the blue sample in the lowest 8 bits                                      */
  GPU_TEX3STRIDE_IMGFMT_RGBA565        = 4,     /*!< RGBA565 : Color Space RED(5-bits) GREEN(6-bits) BLUE (5-bits)             */
  GPU_TEX3STRIDE_IMGFMT_RGBA5551       = 5,     /*!< RGBA5551 : Color Space Red,green,blue,alpha (transparency).               */
  GPU_TEX3STRIDE_IMGFMT_L8             = 9,     /*!< L8 : Color Space Lum8 grayscale                                           */
  GPU_TEX3STRIDE_IMGFMT_TSC4           = 18,    /*!< TSC4 : Color Space Proprietary texture compression                        */
  GPU_TEX3STRIDE_IMGFMT_TSC6           = 22,    /*!< TSC6 : Color Space Optional proprietary texture compression               */
  GPU_TEX3STRIDE_IMGFMT_TSC6A          = 23,    /*!< TSC6A : Color Space Optional proprietary texture compression              */
} GPU_TEX3STRIDE_IMGFMT_Enum;

/* ============================================  GPU TEX3STRIDE IMGMODE [16..23]  ============================================ */
typedef enum {                                  /*!< GPU_TEX3STRIDE_IMGMODE                                                    */
  GPU_TEX3STRIDE_IMGMODE_POINTSAMPLE   = 0,     /*!< POINTSAMPLE : Texture mapping: rotate, resize and distort a
                                                     bitmap image.                                                             */
  GPU_TEX3STRIDE_IMGMODE_BILINEARFILTERING = 1, /*!< BILINEARFILTERING : Texture mapping: rotate, resize and distort
                                                     a bitmap image. A method used to smooth textures when displayed
                                                     larger or smaller than they actually are.                                 */
} GPU_TEX3STRIDE_IMGMODE_Enum;

/* ========================================================  TEX3RES  ======================================================== */
/* =========================================================  CGCMD  ========================================================= */
/* ========================================================  CGCTRL  ========================================================= */
/* =====================================================  DIRTYTRIGMIN  ====================================================== */
/* =====================================================  DIRTYTRIGMAX  ====================================================== */
/* ========================================================  STATUS  ========================================================= */
/* ========================================================  BUSCTRL  ======================================================== */
/* ======================================================  IMEMLDIADDR  ====================================================== */
/* =====================================================  IMEMLDIDATAHL  ===================================================== */
/* =====================================================  IMEMLDIDATAHH  ===================================================== */
/* =====================================================  CMDLISTSTATUS  ===================================================== */
/* ====================================================  CMDLISTRINGSTOP  ==================================================== */
/* ======================================================  CMDLISTADDR  ====================================================== */
/* ======================================================  CMDLISTSIZE  ====================================================== */
/* =====================================================  INTERRUPTCTRL  ===================================================== */
/* =======================================================  SYSCLEAR  ======================================================== */
/* ========================================================  DRAWCMD  ======================================================== */
/* ===============================================  GPU DRAWCMD START [0..2]  ================================================ */
typedef enum {                                  /*!< GPU_DRAWCMD_START                                                         */
  GPU_DRAWCMD_START_PIXEL              = 0,     /*!< PIXEL : draw pixel using STARTXY                                          */
  GPU_DRAWCMD_START_LINE               = 1,     /*!< LINE : draw line from STARTXY to ENDXY                                    */
  GPU_DRAWCMD_START_RECT               = 2,     /*!< RECT : fill rectangle from STARTXY to ENDXY                               */
  GPU_DRAWCMD_START_TRI                = 3,     /*!< TRI : draw triangle (if enabled)                                          */
  GPU_DRAWCMD_START_QUAD               = 4,     /*!< QUAD : draw quadrilateral (if enabled)                                    */
} GPU_DRAWCMD_START_Enum;

/* ========================================================  DRAWPT0  ======================================================== */
/* ========================================================  DRAWPT1  ======================================================== */
/* ========================================================  CLIPMIN  ======================================================== */
/* ========================================================  CLIPMAX  ======================================================== */
/* =======================================================  RASTCTRL  ======================================================== */
/* ======================================================  DRAWCODEPTR  ====================================================== */
/* =======================================================  DRAWPT0X  ======================================================== */
/* =======================================================  DRAWPT0Y  ======================================================== */
/* =======================================================  DRAWPT0Z  ======================================================== */
/* =======================================================  DRAWCOLOR  ======================================================= */
/* =======================================================  DRAWPT1X  ======================================================== */
/* =======================================================  DRAWPT1Y  ======================================================== */
/* =======================================================  DRAWPT1Z  ======================================================== */
/* =======================================================  DRAWPT2X  ======================================================== */
/* =======================================================  DRAWPT2Y  ======================================================== */
/* =======================================================  DRAWPT2Z  ======================================================== */
/* =======================================================  DRAWPT3X  ======================================================== */
/* =======================================================  DRAWPT3Y  ======================================================== */
/* =======================================================  DRAWPT3Z  ======================================================== */
/* =========================================================  MM00  ========================================================== */
/* =========================================================  MM01  ========================================================== */
/* =========================================================  MM02  ========================================================== */
/* =========================================================  MM10  ========================================================== */
/* =========================================================  MM11  ========================================================== */
/* =========================================================  MM12  ========================================================== */
/* =========================================================  MM20  ========================================================== */
/* =========================================================  MM21  ========================================================== */
/* =========================================================  MM22  ========================================================== */
/* ======================================================  DEPTHSTARTL  ====================================================== */
/* ======================================================  DEPTHSTARTH  ====================================================== */
/* =======================================================  DEPTHDXL  ======================================================== */
/* =======================================================  DEPTHDXH  ======================================================== */
/* =======================================================  DEPTHDYL  ======================================================== */
/* =======================================================  DEPTHDYH  ======================================================== */
/* =========================================================  REDX  ========================================================== */
/* =========================================================  REDY  ========================================================== */
/* ========================================================  GREENX  ========================================================= */
/* ========================================================  GREENY  ========================================================= */
/* =========================================================  BLUEX  ========================================================= */
/* =========================================================  BLUEY  ========================================================= */
/* =========================================================  ALFX  ========================================================== */
/* =========================================================  ALFY  ========================================================== */
/* ========================================================  REDINIT  ======================================================== */
/* ========================================================  GREINIT  ======================================================== */
/* ========================================================  BLUINIT  ======================================================== */
/* ========================================================  ALFINIT  ======================================================== */
/* =========================================================  IDREG  ========================================================= */
/* =======================================================  LOADCTRL  ======================================================== */
/* =========================================================  C0REG  ========================================================= */
/* =========================================================  C1REG  ========================================================= */
/* =========================================================  C2REG  ========================================================= */
/* =========================================================  C3REG  ========================================================= */
/* =========================================================  IRQID  ========================================================= */


/* =========================================================================================================================== */
/* ================                                           I2S0                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  RXDATA  ========================================================= */
/* =======================================================  RXCHANID  ======================================================== */
/* =====================================================  RXFIFOSTATUS  ====================================================== */
/* ======================================================  RXFIFOSIZE  ======================================================= */
/* =====================================================  RXUPPERLIMIT  ====================================================== */
/* ========================================================  TXDATA  ========================================================= */
/* =======================================================  TXCHANID  ======================================================== */
/* =====================================================  TXFIFOSTATUS  ====================================================== */
/* ======================================================  TXFIFOSIZE  ======================================================= */
/* =====================================================  TXLOWERLIMIT  ====================================================== */
/* ======================================================  I2SDATACFG  ======================================================= */
/* ============================================  I2S0 I2SDATACFG FRLEN2 [24..30]  ============================================ */
typedef enum {                                  /*!< I2S0_I2SDATACFG_FRLEN2                                                    */
  I2S0_I2SDATACFG_FRLEN2_1CHLS         = 0,     /*!< 1CHLS : One channel in phase 2.                                           */
  I2S0_I2SDATACFG_FRLEN2_2CHLS         = 1,     /*!< 2CHLS : Two channels in phase 2.                                          */
  I2S0_I2SDATACFG_FRLEN2_3CHLS         = 2,     /*!< 3CHLS : Three channels in phase 2.                                        */
  I2S0_I2SDATACFG_FRLEN2_4CHLS         = 3,     /*!< 4CHLS : Four channels in phase 2.                                         */
  I2S0_I2SDATACFG_FRLEN2_5CHLS         = 4,     /*!< 5CHLS : Five channels in phase 2.                                         */
  I2S0_I2SDATACFG_FRLEN2_6CHLS         = 5,     /*!< 6CHLS : Six channels in phase 2.                                          */
  I2S0_I2SDATACFG_FRLEN2_7CHLS         = 6,     /*!< 7CHLS : Seven channels in phase 2.                                        */
  I2S0_I2SDATACFG_FRLEN2_8CHLS         = 7,     /*!< 8CHLS : Eight channels in phase 2.                                        */
} I2S0_I2SDATACFG_FRLEN2_Enum;

/* ============================================  I2S0 I2SDATACFG WDLEN2 [21..23]  ============================================ */
typedef enum {                                  /*!< I2S0_I2SDATACFG_WDLEN2                                                    */
  I2S0_I2SDATACFG_WDLEN2_8b            = 0,     /*!< 8b : Receive channel length is 8 bits for phase 2.                        */
  I2S0_I2SDATACFG_WDLEN2_16b           = 2,     /*!< 16b : Receive channel length is 16 bits for phase 2.                      */
  I2S0_I2SDATACFG_WDLEN2_24b           = 4,     /*!< 24b : Receive channel length is 24 bits for phase 2.                      */
  I2S0_I2SDATACFG_WDLEN2_32b           = 5,     /*!< 32b : Receive channel length is 32 bits for phase 2.                      */
} I2S0_I2SDATACFG_WDLEN2_Enum;

/* =============================================  I2S0 I2SDATACFG SSZ2 [16..18]  ============================================= */
typedef enum {                                  /*!< I2S0_I2SDATACFG_SSZ2                                                      */
  I2S0_I2SDATACFG_SSZ2_8b              = 0,     /*!< 8b : Receive audio sample length is 8 bits for phase 2.                   */
  I2S0_I2SDATACFG_SSZ2_16b             = 2,     /*!< 16b : Receive audio sample length is 16 bits for phase 2.                 */
  I2S0_I2SDATACFG_SSZ2_24b             = 4,     /*!< 24b : Receive audio sample length is 24 bits for phase 2.                 */
  I2S0_I2SDATACFG_SSZ2_32b             = 5,     /*!< 32b : Receive audio sample length is 32 bits for phase 2.                 */
} I2S0_I2SDATACFG_SSZ2_Enum;

/* ============================================  I2S0 I2SDATACFG FRLEN1 [8..14]  ============================================= */
typedef enum {                                  /*!< I2S0_I2SDATACFG_FRLEN1                                                    */
  I2S0_I2SDATACFG_FRLEN1_1CHLS         = 0,     /*!< 1CHLS : One channel in phase 1.                                           */
  I2S0_I2SDATACFG_FRLEN1_2CHLS         = 1,     /*!< 2CHLS : Two channels in phase 1.                                          */
  I2S0_I2SDATACFG_FRLEN1_3CHLS         = 2,     /*!< 3CHLS : Three channels in phase 1.                                        */
  I2S0_I2SDATACFG_FRLEN1_4CHLS         = 3,     /*!< 4CHLS : Four channels in phase 1.                                         */
  I2S0_I2SDATACFG_FRLEN1_5CHLS         = 4,     /*!< 5CHLS : Five channels in phase 1.                                         */
  I2S0_I2SDATACFG_FRLEN1_6CHLS         = 5,     /*!< 6CHLS : Six channels in phase 1.                                          */
  I2S0_I2SDATACFG_FRLEN1_7CHLS         = 6,     /*!< 7CHLS : Seven channels in phase 1.                                        */
  I2S0_I2SDATACFG_FRLEN1_8CHLS         = 7,     /*!< 8CHLS : Eight channels in phase 1.                                        */
} I2S0_I2SDATACFG_FRLEN1_Enum;

/* =============================================  I2S0 I2SDATACFG WDLEN1 [5..7]  ============================================= */
typedef enum {                                  /*!< I2S0_I2SDATACFG_WDLEN1                                                    */
  I2S0_I2SDATACFG_WDLEN1_8b            = 0,     /*!< 8b : Receive channel length is 8 bits for phase 1.                        */
  I2S0_I2SDATACFG_WDLEN1_16b           = 2,     /*!< 16b : Receive channel length is 16 bits for phase 1.                      */
  I2S0_I2SDATACFG_WDLEN1_24b           = 4,     /*!< 24b : Receive channel length is 24 bits for phase 1.                      */
  I2S0_I2SDATACFG_WDLEN1_32b           = 5,     /*!< 32b : Receive channel length is 32 bits for phase 1.                      */
} I2S0_I2SDATACFG_WDLEN1_Enum;

/* ==============================================  I2S0 I2SDATACFG SSZ1 [0..2]  ============================================== */
typedef enum {                                  /*!< I2S0_I2SDATACFG_SSZ1                                                      */
  I2S0_I2SDATACFG_SSZ1_8b              = 0,     /*!< 8b : Receive audio sample length is 8 bits for phase 1.                   */
  I2S0_I2SDATACFG_SSZ1_16b             = 2,     /*!< 16b : Receive audio sample length is 16 bits for phase 1.                 */
  I2S0_I2SDATACFG_SSZ1_24b             = 4,     /*!< 24b : Receive audio sample length is 24 bits for phase 1.                 */
  I2S0_I2SDATACFG_SSZ1_32b             = 5,     /*!< 32b : Receive audio sample length is 32 bits for phase 1.                 */
} I2S0_I2SDATACFG_SSZ1_Enum;

/* =======================================================  I2SIOCFG  ======================================================== */
/* ========================================================  I2SCTL  ========================================================= */
/* ========================================================  IPBIRPT  ======================================================== */
/* =======================================================  IPCOREID  ======================================================== */
/* ========================================================  AMQCFG  ========================================================= */
/* ========================================================  CLKCFG  ========================================================= */
/* ========================================================  DMACFG  ========================================================= */
/* ==============================================  I2S0 DMACFG TXDMAPRI [5..5]  ============================================== */
typedef enum {                                  /*!< I2S0_DMACFG_TXDMAPRI                                                      */
  I2S0_DMACFG_TXDMAPRI_LOW             = 0,     /*!< LOW : Low Priority (service as best effort)                               */
  I2S0_DMACFG_TXDMAPRI_HIGH            = 1,     /*!< HIGH : High Priority (service immediately)                                */
} I2S0_DMACFG_TXDMAPRI_Enum;

/* ==============================================  I2S0 DMACFG TXDMAEN [4..4]  =============================================== */
typedef enum {                                  /*!< I2S0_DMACFG_TXDMAEN                                                       */
  I2S0_DMACFG_TXDMAEN_DIS              = 0,     /*!< DIS : Disable TXDMA Function                                              */
  I2S0_DMACFG_TXDMAEN_EN               = 1,     /*!< EN : Enable TXDMA Function                                                */
} I2S0_DMACFG_TXDMAEN_Enum;

/* ==============================================  I2S0 DMACFG RXDMAPRI [1..1]  ============================================== */
typedef enum {                                  /*!< I2S0_DMACFG_RXDMAPRI                                                      */
  I2S0_DMACFG_RXDMAPRI_LOW             = 0,     /*!< LOW : Low Priority (service as best effort)                               */
  I2S0_DMACFG_RXDMAPRI_HIGH            = 1,     /*!< HIGH : High Priority (service immediately)                                */
} I2S0_DMACFG_RXDMAPRI_Enum;

/* ==============================================  I2S0 DMACFG RXDMAEN [0..0]  =============================================== */
typedef enum {                                  /*!< I2S0_DMACFG_RXDMAEN                                                       */
  I2S0_DMACFG_RXDMAEN_DIS              = 0,     /*!< DIS : Disable RXDMA Function                                              */
  I2S0_DMACFG_RXDMAEN_EN               = 1,     /*!< EN : Enable RXDMA Function                                                */
} I2S0_DMACFG_RXDMAEN_Enum;

/* ======================================================  RXDMATOTCNT  ====================================================== */
/* =======================================================  RXDMAADDR  ======================================================= */
/* =======================================================  RXDMASTAT  ======================================================= */
/* ======================================================  TXDMATOTCNT  ====================================================== */
/* =======================================================  TXDMAADDR  ======================================================= */
/* =======================================================  TXDMASTAT  ======================================================= */
/* ========================================================  STATUS  ========================================================= */
/* =========================================================  INTEN  ========================================================= */
/* ========================================================  INTSTAT  ======================================================== */
/* ========================================================  INTCLR  ========================================================= */
/* ========================================================  INTSET  ========================================================= */
/* ========================================================  I2SDBG  ========================================================= */


/* =========================================================================================================================== */
/* ================                                           IOM0                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  FIFO  ========================================================== */
/* ========================================================  FIFOPTR  ======================================================== */
/* ========================================================  FIFOTHR  ======================================================== */
/* ========================================================  FIFOPOP  ======================================================== */
/* =======================================================  FIFOPUSH  ======================================================== */
/* =======================================================  FIFOCTRL  ======================================================== */
/* ========================================================  FIFOLOC  ======================================================== */
/* ========================================================  CLKCFG  ========================================================= */
/* ==============================================  IOM0 CLKCFG DIVEN [12..12]  =============================================== */
typedef enum {                                  /*!< IOM0_CLKCFG_DIVEN                                                         */
  IOM0_CLKCFG_DIVEN_DIS                = 0,     /*!< DIS : Disable TOTPER division.                                            */
  IOM0_CLKCFG_DIVEN_EN                 = 1,     /*!< EN : Enable TOTPER division.                                              */
} IOM0_CLKCFG_DIVEN_Enum;

/* ===============================================  IOM0 CLKCFG DIV3 [11..11]  =============================================== */
typedef enum {                                  /*!< IOM0_CLKCFG_DIV3                                                          */
  IOM0_CLKCFG_DIV3_DIS                 = 0,     /*!< DIS : Select divide by 1.                                                 */
  IOM0_CLKCFG_DIV3_EN                  = 1,     /*!< EN : Select divide by 3.                                                  */
} IOM0_CLKCFG_DIV3_Enum;

/* ===============================================  IOM0 CLKCFG FSEL [8..10]  ================================================ */
typedef enum {                                  /*!< IOM0_CLKCFG_FSEL                                                          */
  IOM0_CLKCFG_FSEL_MIN_PWR             = 0,     /*!< MIN_PWR : Selects the minimum power clock. This setting should
                                                     be used whenever the IOM is not active.                                   */
  IOM0_CLKCFG_FSEL_OFF                 = 1,     /*!< OFF : Selects static 0 as the input clock. Previously 96Mhz
                                                     setting                                                                   */
  IOM0_CLKCFG_FSEL_HFRC48MHZ           = 2,     /*!< HFRC48MHZ : Selects the HFRC 48MHz as the input clock.                    */
  IOM0_CLKCFG_FSEL_HFRC24MHZ           = 3,     /*!< HFRC24MHZ : Selects the HFRC 24MHz as the input clock.                    */
  IOM0_CLKCFG_FSEL_HFRC12MHZ           = 4,     /*!< HFRC12MHZ : Selects the HFRC 12MHz as the input clock.                    */
  IOM0_CLKCFG_FSEL_HFRC6MHZ            = 5,     /*!< HFRC6MHZ : Selects the HFRC 6MHz as the input clock.                      */
  IOM0_CLKCFG_FSEL_HFRC3MHZ            = 6,     /*!< HFRC3MHZ : Selects the HFRC 3MHz as the input clock.                      */
  IOM0_CLKCFG_FSEL_HFRC1p5MHZ          = 7,     /*!< HFRC1p5MHZ : Selects the HFRC 1.5MHz as the input clock.                  */
} IOM0_CLKCFG_FSEL_Enum;

/* ======================================================  SUBMODCTRL  ======================================================= */
/* ===========================================  IOM0 SUBMODCTRL SMOD2TYPE [9..11]  =========================================== */
typedef enum {                                  /*!< IOM0_SUBMODCTRL_SMOD2TYPE                                                 */
  IOM0_SUBMODCTRL_SMOD2TYPE_MSPI       = 0,     /*!< MSPI : SPI Master submodule                                               */
  IOM0_SUBMODCTRL_SMOD2TYPE_MI2C       = 1,     /*!< MI2C : MI2C submodule                                                     */
  IOM0_SUBMODCTRL_SMOD2TYPE_SSPI       = 2,     /*!< SSPI : SPI Slave submodule                                                */
  IOM0_SUBMODCTRL_SMOD2TYPE_SI2C       = 3,     /*!< SI2C : I2C Slave submodule                                                */
  IOM0_SUBMODCTRL_SMOD2TYPE_MSI2S      = 4,     /*!< MSI2S : Master/Slave submodule                                            */
  IOM0_SUBMODCTRL_SMOD2TYPE_NA         = 7,     /*!< NA : NOT INSTALLED                                                        */
} IOM0_SUBMODCTRL_SMOD2TYPE_Enum;

/* ===========================================  IOM0 SUBMODCTRL SMOD1TYPE [5..7]  ============================================ */
typedef enum {                                  /*!< IOM0_SUBMODCTRL_SMOD1TYPE                                                 */
  IOM0_SUBMODCTRL_SMOD1TYPE_MSPI       = 0,     /*!< MSPI : SPI Master submodule                                               */
  IOM0_SUBMODCTRL_SMOD1TYPE_MI2C       = 1,     /*!< MI2C : MI2C submodule                                                     */
  IOM0_SUBMODCTRL_SMOD1TYPE_SSPI       = 2,     /*!< SSPI : SPI Slave submodule                                                */
  IOM0_SUBMODCTRL_SMOD1TYPE_SI2C       = 3,     /*!< SI2C : I2C Slave submodule                                                */
  IOM0_SUBMODCTRL_SMOD1TYPE_MSI2S      = 4,     /*!< MSI2S : Master/Slave submodule                                            */
  IOM0_SUBMODCTRL_SMOD1TYPE_NA         = 7,     /*!< NA : NOT INSTALLED                                                        */
} IOM0_SUBMODCTRL_SMOD1TYPE_Enum;

/* ===========================================  IOM0 SUBMODCTRL SMOD0TYPE [1..3]  ============================================ */
typedef enum {                                  /*!< IOM0_SUBMODCTRL_SMOD0TYPE                                                 */
  IOM0_SUBMODCTRL_SMOD0TYPE_MSPI       = 0,     /*!< MSPI : MSPI submodule                                                     */
  IOM0_SUBMODCTRL_SMOD0TYPE_MI2C       = 1,     /*!< MI2C : I2C Master submodule                                               */
  IOM0_SUBMODCTRL_SMOD0TYPE_MSI2S      = 2,     /*!< MSI2S : I2S Master/Slave Module                                           */
  IOM0_SUBMODCTRL_SMOD0TYPE_NA         = 7,     /*!< NA : NOT INSTALLED                                                        */
} IOM0_SUBMODCTRL_SMOD0TYPE_Enum;

/* ==========================================================  CMD  ========================================================== */
/* ==================================================  IOM0 CMD CMD [0..3]  ================================================== */
typedef enum {                                  /*!< IOM0_CMD_CMD                                                              */
  IOM0_CMD_CMD_WRITE                   = 1,     /*!< WRITE : Write command using count of offset bytes specified
                                                     in the OFFSETCNT field                                                    */
  IOM0_CMD_CMD_READ                    = 2,     /*!< READ : Read command using count of offset bytes specified in
                                                     the OFFSETCNT field                                                       */
  IOM0_CMD_CMD_TMW                     = 3,     /*!< TMW : SPI only. Test mode to do constant write operations. Useful
                                                     for debug and power measurements. Will continually send
                                                     data in OFFSET field                                                      */
  IOM0_CMD_CMD_TMR                     = 4,     /*!< TMR : SPI Only. Test mode to do constant read operations. Useful
                                                     for debug and power measurements. Will continually read
                                                     data from external input                                                  */
} IOM0_CMD_CMD_Enum;

/* ========================================================  DCXCTRL  ======================================================== */
/* =======================================================  OFFSETHI  ======================================================== */
/* ========================================================  CMDSTAT  ======================================================== */
/* ==============================================  IOM0 CMDSTAT CMDSTAT [5..7]  ============================================== */
typedef enum {                                  /*!< IOM0_CMDSTAT_CMDSTAT                                                      */
  IOM0_CMDSTAT_CMDSTAT_ERR             = 1,     /*!< ERR : Error encountered with command                                      */
  IOM0_CMDSTAT_CMDSTAT_ACTIVE          = 2,     /*!< ACTIVE : Actively processing command                                      */
  IOM0_CMDSTAT_CMDSTAT_IDLE            = 4,     /*!< IDLE : Idle state, no active command, no error                            */
  IOM0_CMDSTAT_CMDSTAT_WAIT            = 6,     /*!< WAIT : Command in progress, but waiting on data from host                 */
} IOM0_CMDSTAT_CMDSTAT_Enum;

/* =========================================================  INTEN  ========================================================= */
/* ========================================================  INTSTAT  ======================================================== */
/* ========================================================  INTCLR  ========================================================= */
/* ========================================================  INTSET  ========================================================= */
/* =======================================================  DMATRIGEN  ======================================================= */
/* ======================================================  DMATRIGSTAT  ====================================================== */
/* ========================================================  DMACFG  ========================================================= */
/* ==============================================  IOM0 DMACFG DPWROFF [9..9]  =============================================== */
typedef enum {                                  /*!< IOM0_DMACFG_DPWROFF                                                       */
  IOM0_DMACFG_DPWROFF_DIS              = 0,     /*!< DIS : Power off disabled                                                  */
  IOM0_DMACFG_DPWROFF_EN               = 1,     /*!< EN : Power off enabled                                                    */
} IOM0_DMACFG_DPWROFF_Enum;

/* ===============================================  IOM0 DMACFG DMAPRI [8..8]  =============================================== */
typedef enum {                                  /*!< IOM0_DMACFG_DMAPRI                                                        */
  IOM0_DMACFG_DMAPRI_LOW               = 0,     /*!< LOW : Low Priority (service as best effort)                               */
  IOM0_DMACFG_DMAPRI_HIGH              = 1,     /*!< HIGH : High Priority (service immediately)                                */
} IOM0_DMACFG_DMAPRI_Enum;

/* ===============================================  IOM0 DMACFG DMADIR [1..1]  =============================================== */
typedef enum {                                  /*!< IOM0_DMACFG_DMADIR                                                        */
  IOM0_DMACFG_DMADIR_P2M               = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction. To be set when
                                                     doing IOM read operations, ie reading data from external
                                                     devices.                                                                  */
  IOM0_DMACFG_DMADIR_M2P               = 1,     /*!< M2P : Memory to Peripheral transaction. To be set when doing
                                                     IOM write operations, ie writing data to external devices.                */
} IOM0_DMACFG_DMADIR_Enum;

/* ===============================================  IOM0 DMACFG DMAEN [0..0]  ================================================ */
typedef enum {                                  /*!< IOM0_DMACFG_DMAEN                                                         */
  IOM0_DMACFG_DMAEN_DIS                = 0,     /*!< DIS : Disable DMA Function                                                */
  IOM0_DMACFG_DMAEN_EN                 = 1,     /*!< EN : Enable DMA Function                                                  */
} IOM0_DMACFG_DMAEN_Enum;

/* ======================================================  DMATOTCOUNT  ====================================================== */
/* ======================================================  DMATARGADDR  ====================================================== */
/* ========================================================  DMASTAT  ======================================================== */
/* =========================================================  CQCFG  ========================================================= */
/* =============================================  IOM0 CQCFG MSPIFLGSEL [2..3]  ============================================== */
typedef enum {                                  /*!< IOM0_CQCFG_MSPIFLGSEL                                                     */
  IOM0_CQCFG_MSPIFLGSEL_MSPI0FLGSEL    = 0,     /*!< MSPI0FLGSEL : Selects MPSI0 as source of signals used in CGFLAG[11:8].    */
  IOM0_CQCFG_MSPIFLGSEL_MSPI1FLGSEL    = 1,     /*!< MSPI1FLGSEL : Selects MPSI1 as source of signals used in CGFLAG[11:8].    */
  IOM0_CQCFG_MSPIFLGSEL_MSPI2FLGSEL    = 2,     /*!< MSPI2FLGSEL : Selects MPSI2 as source of signals used in CGFLAG[11:8].    */
} IOM0_CQCFG_MSPIFLGSEL_Enum;

/* ================================================  IOM0 CQCFG CQPRI [1..1]  ================================================ */
typedef enum {                                  /*!< IOM0_CQCFG_CQPRI                                                          */
  IOM0_CQCFG_CQPRI_LOW                 = 0,     /*!< LOW : Low Priority (service as best effort)                               */
  IOM0_CQCFG_CQPRI_HIGH                = 1,     /*!< HIGH : High Priority (service immediately)                                */
} IOM0_CQCFG_CQPRI_Enum;

/* ================================================  IOM0 CQCFG CQEN [0..0]  ================================================= */
typedef enum {                                  /*!< IOM0_CQCFG_CQEN                                                           */
  IOM0_CQCFG_CQEN_DIS                  = 0,     /*!< DIS : Disable CQ Function                                                 */
  IOM0_CQCFG_CQEN_EN                   = 1,     /*!< EN : Enable CQ Function                                                   */
} IOM0_CQCFG_CQEN_Enum;

/* ========================================================  CQADDR  ========================================================= */
/* ========================================================  CQSTAT  ========================================================= */
/* ========================================================  CQFLAGS  ======================================================== */
/* ======================================================  CQSETCLEAR  ======================================================= */
/* =======================================================  CQPAUSEEN  ======================================================= */
/* =============================================  IOM0 CQPAUSEEN CQPEN [0..15]  ============================================== */
typedef enum {                                  /*!< IOM0_CQPAUSEEN_CQPEN                                                      */
  IOM0_CQPAUSEEN_CQPEN_IDXEQ           = 32768, /*!< IDXEQ : Pauses the command queue when the current index matches
                                                     the last index                                                            */
  IOM0_CQPAUSEEN_CQPEN_BLEXOREN        = 16384, /*!< BLEXOREN : Pause command queue when input BLE bit XORed with
                                                     SWFLAG4 is '1'                                                            */
  IOM0_CQPAUSEEN_CQPEN_IOMXOREN        = 8192,  /*!< IOMXOREN : Pause command queue when input IOM bit XORed with
                                                     SWFLAG3 is '1'                                                            */
  IOM0_CQPAUSEEN_CQPEN_GPIOXOREN       = 4096,  /*!< GPIOXOREN : Pause command queue when input GPIO irq_bit XORed
                                                     with SWFLAG2 is '1'                                                       */
  IOM0_CQPAUSEEN_CQPEN_MSPI1XNOREN     = 2048,  /*!< MSPI1XNOREN : Pause command queue when input MSPI1 bit XNORed
                                                     with SWFLAG1 is '1'                                                       */
  IOM0_CQPAUSEEN_CQPEN_MSPI0XNOREN     = 1024,  /*!< MSPI0XNOREN : Pause command queue when input MSPI0 bit XNORed
                                                     with SWFLAG0 is '1'                                                       */
  IOM0_CQPAUSEEN_CQPEN_MSPI1XOREN      = 512,   /*!< MSPI1XOREN : Pause command queue when input MSPI1 bit XORed
                                                     with SWFLAG1 is '1'                                                       */
  IOM0_CQPAUSEEN_CQPEN_MSPI0XOREN      = 256,   /*!< MSPI0XOREN : Pause command queue when input MSPI0 bit XORed
                                                     with SWFLAG0 is '1'                                                       */
  IOM0_CQPAUSEEN_CQPEN_SWFLAGEN7       = 128,   /*!< SWFLAGEN7 : Pause the command queue when software flag bit 7
                                                     is '1'.                                                                   */
  IOM0_CQPAUSEEN_CQPEN_SWFLAGEN6       = 64,    /*!< SWFLAGEN6 : Pause the command queue when software flag bit 6
                                                     is '1'                                                                    */
  IOM0_CQPAUSEEN_CQPEN_SWFLAGEN5       = 32,    /*!< SWFLAGEN5 : Pause the command queue when software flag bit 5
                                                     is '1'                                                                    */
  IOM0_CQPAUSEEN_CQPEN_SWFLAGEN4       = 16,    /*!< SWFLAGEN4 : Pause the command queue when software flag bit 4
                                                     is '1'                                                                    */
  IOM0_CQPAUSEEN_CQPEN_SWFLAGEN3       = 8,     /*!< SWFLAGEN3 : Pause the command queue when software flag bit 3
                                                     is '1'                                                                    */
  IOM0_CQPAUSEEN_CQPEN_SWFLAGEN2       = 4,     /*!< SWFLAGEN2 : Pause the command queue when software flag bit 2
                                                     is '1'                                                                    */
  IOM0_CQPAUSEEN_CQPEN_SWFLAGEN1       = 2,     /*!< SWFLAGEN1 : Pause the command queue when software flag bit 1
                                                     is '1'                                                                    */
  IOM0_CQPAUSEEN_CQPEN_SWFLAGEN0       = 1,     /*!< SWFLAGEN0 : Pause the command queue when software flag bit 0
                                                     is '1'                                                                    */
} IOM0_CQPAUSEEN_CQPEN_Enum;

/* =======================================================  CQCURIDX  ======================================================== */
/* =======================================================  CQENDIDX  ======================================================== */
/* ========================================================  STATUS  ========================================================= */
/* ===============================================  IOM0 STATUS IDLEST [2..2]  =============================================== */
typedef enum {                                  /*!< IOM0_STATUS_IDLEST                                                        */
  IOM0_STATUS_IDLEST_IDLE              = 1,     /*!< IDLE : The I/O state machine is in the idle state.                        */
  IOM0_STATUS_IDLEST_RUN               = 0,     /*!< RUN : The I/O state machine is in the non-idle/run state.                 */
} IOM0_STATUS_IDLEST_Enum;

/* ===============================================  IOM0 STATUS CMDACT [1..1]  =============================================== */
typedef enum {                                  /*!< IOM0_STATUS_CMDACT                                                        */
  IOM0_STATUS_CMDACT_ACTIVE            = 1,     /*!< ACTIVE : An I/O command is active. Indicates the active module
                                                     has an active command and is processing this. De-asserted
                                                     when the command is completed.                                            */
  IOM0_STATUS_CMDACT_INACTIVE          = 0,     /*!< INACTIVE : An I/O command is inactive. Indicating that the command
                                                     is complete.                                                              */
} IOM0_STATUS_CMDACT_Enum;

/* ================================================  IOM0 STATUS ERR [0..0]  ================================================= */
typedef enum {                                  /*!< IOM0_STATUS_ERR                                                           */
  IOM0_STATUS_ERR_ERROR                = 1,     /*!< ERROR : Bit has been deprecated and will always return 0.                 */
  IOM0_STATUS_ERR_DEFAULT              = 0,     /*!< DEFAULT : Default value.                                                  */
} IOM0_STATUS_ERR_Enum;

/* ========================================================  MSPICFG  ======================================================== */
/* =============================================  IOM0 MSPICFG SPILSB [23..23]  ============================================== */
typedef enum {                                  /*!< IOM0_MSPICFG_SPILSB                                                       */
  IOM0_MSPICFG_SPILSB_MSB              = 0,     /*!< MSB : Send and receive MSB bit first                                      */
  IOM0_MSPICFG_SPILSB_LSB              = 1,     /*!< LSB : Send and receive LSB bit first                                      */
} IOM0_MSPICFG_SPILSB_Enum;

/* =============================================  IOM0 MSPICFG RDFCPOL [22..22]  ============================================= */
typedef enum {                                  /*!< IOM0_MSPICFG_RDFCPOL                                                      */
  IOM0_MSPICFG_RDFCPOL_HIGH            = 0,     /*!< HIGH : Flow control signal high creates flow control.                     */
  IOM0_MSPICFG_RDFCPOL_LOW             = 1,     /*!< LOW : Flow control signal low creates flow control.                       */
} IOM0_MSPICFG_RDFCPOL_Enum;

/* =============================================  IOM0 MSPICFG WTFCPOL [21..21]  ============================================= */
typedef enum {                                  /*!< IOM0_MSPICFG_WTFCPOL                                                      */
  IOM0_MSPICFG_WTFCPOL_HIGH            = 0,     /*!< HIGH : Flow control signal high(1) creates flow control and
                                                     byte transfers will stop until the flow control signal
                                                     goes low.                                                                 */
  IOM0_MSPICFG_WTFCPOL_LOW             = 1,     /*!< LOW : Flow control signal low(0) creates flow control and byte
                                                     transfers will stop until the flow control signal goes
                                                     high(1).                                                                  */
} IOM0_MSPICFG_WTFCPOL_Enum;

/* =============================================  IOM0 MSPICFG WTFCIRQ [20..20]  ============================================= */
typedef enum {                                  /*!< IOM0_MSPICFG_WTFCIRQ                                                      */
  IOM0_MSPICFG_WTFCIRQ_MISO            = 0,     /*!< MISO : MISO is used as the write mode flow control signal.                */
  IOM0_MSPICFG_WTFCIRQ_IRQ             = 1,     /*!< IRQ : IRQ is used as the write mode flow control signal.                  */
} IOM0_MSPICFG_WTFCIRQ_Enum;

/* =============================================  IOM0 MSPICFG MOSIINV [18..18]  ============================================= */
typedef enum {                                  /*!< IOM0_MSPICFG_MOSIINV                                                      */
  IOM0_MSPICFG_MOSIINV_NORMAL          = 0,     /*!< NORMAL : MOSI is set to 0 in read mode and 1 in write mode.               */
  IOM0_MSPICFG_MOSIINV_INVERT          = 1,     /*!< INVERT : MOSI is set to 1 in read mode and 0 in write mode.               */
} IOM0_MSPICFG_MOSIINV_Enum;

/* ==============================================  IOM0 MSPICFG RDFC [17..17]  =============================================== */
typedef enum {                                  /*!< IOM0_MSPICFG_RDFC                                                         */
  IOM0_MSPICFG_RDFC_DIS                = 0,     /*!< DIS : Read mode flow control disabled.                                    */
  IOM0_MSPICFG_RDFC_EN                 = 1,     /*!< EN : Read mode flow control enabled.                                      */
} IOM0_MSPICFG_RDFC_Enum;

/* ==============================================  IOM0 MSPICFG WTFC [16..16]  =============================================== */
typedef enum {                                  /*!< IOM0_MSPICFG_WTFC                                                         */
  IOM0_MSPICFG_WTFC_DIS                = 0,     /*!< DIS : Write mode flow control disabled.                                   */
  IOM0_MSPICFG_WTFC_EN                 = 1,     /*!< EN : Write mode flow control enabled.                                     */
} IOM0_MSPICFG_WTFC_Enum;

/* ===============================================  IOM0 MSPICFG SPHA [1..1]  ================================================ */
typedef enum {                                  /*!< IOM0_MSPICFG_SPHA                                                         */
  IOM0_MSPICFG_SPHA_SAMPLE_LEADING_EDGE = 0,    /*!< SAMPLE_LEADING_EDGE : Sample on the leading (first) clock edge.           */
  IOM0_MSPICFG_SPHA_SAMPLE_TRAILING_EDGE = 1,   /*!< SAMPLE_TRAILING_EDGE : Sample on the trailing (second) clock
                                                     edge.                                                                     */
} IOM0_MSPICFG_SPHA_Enum;

/* ===============================================  IOM0 MSPICFG SPOL [0..0]  ================================================ */
typedef enum {                                  /*!< IOM0_MSPICFG_SPOL                                                         */
  IOM0_MSPICFG_SPOL_CLK_BASE_0         = 0,     /*!< CLK_BASE_0 : The base value of the clock is 0.                            */
  IOM0_MSPICFG_SPOL_CLK_BASE_1         = 1,     /*!< CLK_BASE_1 : The base value of the clock is 1.                            */
} IOM0_MSPICFG_SPOL_Enum;

/* ========================================================  MI2CCFG  ======================================================== */
/* ===============================================  IOM0 MI2CCFG ARBEN [2..2]  =============================================== */
typedef enum {                                  /*!< IOM0_MI2CCFG_ARBEN                                                        */
  IOM0_MI2CCFG_ARBEN_ARBENABLE         = 1,     /*!< ARBENABLE : Enable multi-master bus arbitration support for
                                                     this i2c master                                                           */
  IOM0_MI2CCFG_ARBEN_ARBDISABLE        = 0,     /*!< ARBDISABLE : Disable multi-master bus arbitration support for
                                                     this i2c master                                                           */
} IOM0_MI2CCFG_ARBEN_Enum;

/* ==============================================  IOM0 MI2CCFG I2CLSB [1..1]  =============================================== */
typedef enum {                                  /*!< IOM0_MI2CCFG_I2CLSB                                                       */
  IOM0_MI2CCFG_I2CLSB_MSBFIRST         = 0,     /*!< MSBFIRST : Byte data is transmitted MSB first onto the bus/read
                                                     from the bus                                                              */
  IOM0_MI2CCFG_I2CLSB_LSBFIRST         = 1,     /*!< LSBFIRST : Byte data is transmitted LSB first onto the bus/read
                                                     from the bus                                                              */
} IOM0_MI2CCFG_I2CLSB_Enum;

/* ==============================================  IOM0 MI2CCFG ADDRSZ [0..0]  =============================================== */
typedef enum {                                  /*!< IOM0_MI2CCFG_ADDRSZ                                                       */
  IOM0_MI2CCFG_ADDRSZ_ADDRSZ7          = 0,     /*!< ADDRSZ7 : Use 7b addressing for I2C master transactions                   */
  IOM0_MI2CCFG_ADDRSZ_ADDRSZ10         = 1,     /*!< ADDRSZ10 : Use 10b addressing for I2C master transactions                 */
} IOM0_MI2CCFG_ADDRSZ_Enum;

/* ========================================================  DEVCFG  ========================================================= */
/* ========================================================  IOMDBG  ========================================================= */


/* =========================================================================================================================== */
/* ================                                          IOSLAVE                                          ================ */
/* =========================================================================================================================== */

/* ========================================================  FIFOPTR  ======================================================== */
/* ========================================================  FIFOCFG  ======================================================== */
/* ========================================================  FIFOTHR  ======================================================== */
/* =========================================================  FUPD  ========================================================== */
/* ========================================================  FIFOCTR  ======================================================== */
/* ========================================================  FIFOINC  ======================================================== */
/* ==========================================================  CFG  ========================================================== */
/* ==============================================  IOSLAVE CFG IFCEN [31..31]  =============================================== */
typedef enum {                                  /*!< IOSLAVE_CFG_IFCEN                                                         */
  IOSLAVE_CFG_IFCEN_DIS                = 0,     /*!< DIS : Disable the IOSLAVE                                                 */
  IOSLAVE_CFG_IFCEN_EN                 = 1,     /*!< EN : Enable the IOSLAVE                                                   */
} IOSLAVE_CFG_IFCEN_Enum;

/* =============================================  IOSLAVE CFG WRAPPTR [20..20]  ============================================== */
typedef enum {                                  /*!< IOSLAVE_CFG_WRAPPTR                                                       */
  IOSLAVE_CFG_WRAPPTR_NOWRAP           = 0,     /*!< NOWRAP : Address pointer does not wrap around to FIFOBASE*8
                                                     after it reaches FIFOMAX*8-1. Additionally, the address
                                                     pointer does not automatically skip Direct Area locations
                                                     0x78 to 0x7F, so care must be taken that the host does
                                                     not inadvertently write to the Host Registers during a
                                                     data transfer.                                                            */
  IOSLAVE_CFG_WRAPPTR_WRAP             = 1,     /*!< WRAP : Address pointer wraps around to FIFOBASE*8 after it reaches
                                                     FIFOMAX*8-1 to accommodate any length transfers. In addition,
                                                     the address pointer automatically skips Direct Area locations
                                                     0x78 to 0x7F (if the FIFO Area encompasses these locations)
                                                     to avoid writing to the Host Registers.                                   */
} IOSLAVE_CFG_WRAPPTR_Enum;

/* ==============================================  IOSLAVE CFG STARTRD [4..4]  =============================================== */
typedef enum {                                  /*!< IOSLAVE_CFG_STARTRD                                                       */
  IOSLAVE_CFG_STARTRD_LATE             = 0,     /*!< LATE : Initiate I/O RAM read late in each transferred byte.               */
  IOSLAVE_CFG_STARTRD_EARLY            = 1,     /*!< EARLY : Initiate I/O RAM read early in each transferred byte.             */
} IOSLAVE_CFG_STARTRD_Enum;

/* ================================================  IOSLAVE CFG LSB [2..2]  ================================================= */
typedef enum {                                  /*!< IOSLAVE_CFG_LSB                                                           */
  IOSLAVE_CFG_LSB_MSB_FIRST            = 0,     /*!< MSB_FIRST : Data is assumed to be sent and received with MSB
                                                     first.                                                                    */
  IOSLAVE_CFG_LSB_LSB_FIRST            = 1,     /*!< LSB_FIRST : Data is assumed to be sent and received with LSB
                                                     first.                                                                    */
} IOSLAVE_CFG_LSB_Enum;

/* ================================================  IOSLAVE CFG SPOL [1..1]  ================================================ */
typedef enum {                                  /*!< IOSLAVE_CFG_SPOL                                                          */
  IOSLAVE_CFG_SPOL_SPI_MODES_0_3       = 0,     /*!< SPI_MODES_0_3 : Polarity 0, handles SPI modes 0 and 3.                    */
  IOSLAVE_CFG_SPOL_SPI_MODES_1_2       = 1,     /*!< SPI_MODES_1_2 : Polarity 1, handles SPI modes 1 and 2.                    */
} IOSLAVE_CFG_SPOL_Enum;

/* ===============================================  IOSLAVE CFG IFCSEL [0..0]  =============================================== */
typedef enum {                                  /*!< IOSLAVE_CFG_IFCSEL                                                        */
  IOSLAVE_CFG_IFCSEL_I2C               = 0,     /*!< I2C : Selects I2C interface for the IO Slave.                             */
  IOSLAVE_CFG_IFCSEL_SPI               = 1,     /*!< SPI : Selects SPI interface for the IO Slave.                             */
} IOSLAVE_CFG_IFCSEL_Enum;

/* =========================================================  PRENC  ========================================================= */
/* =======================================================  IOINTCTL  ======================================================== */
/* ========================================================  GENADD  ========================================================= */
/* ========================================================  ADDPTR  ========================================================= */
/* =========================================================  INTEN  ========================================================= */
/* ========================================================  INTSTAT  ======================================================== */
/* ========================================================  INTCLR  ========================================================= */
/* ========================================================  INTSET  ========================================================= */
/* ======================================================  REGACCINTEN  ====================================================== */
/* =====================================================  REGACCINTSTAT  ===================================================== */
/* =====================================================  REGACCINTCLR  ====================================================== */
/* =====================================================  REGACCINTSET  ====================================================== */


/* =========================================================================================================================== */
/* ================                                          MCUCTRL                                          ================ */
/* =========================================================================================================================== */

/* ========================================================  CHIPPN  ========================================================= */
/* ==============================================  MCUCTRL CHIPPN PN [24..31]  =============================================== */
typedef enum {                                  /*!< MCUCTRL_CHIPPN_PN                                                         */
  MCUCTRL_CHIPPN_PN_APOLLO4L           = 9,     /*!< APOLLO4L : Apollo4L part number is 0x09xxxxxx.                            */
  MCUCTRL_CHIPPN_PN_APOLLO4            = 8,     /*!< APOLLO4 : Apollo4 part number is 0x08xxxxxx.                              */
  MCUCTRL_CHIPPN_PN_APOLLO3P           = 7,     /*!< APOLLO3P : Apollo3P part number is 0x07xxxxxx.                            */
  MCUCTRL_CHIPPN_PN_APOLLO3            = 6,     /*!< APOLLO3 : Apollo3 part number is 0x06xxxxxx.                              */
  MCUCTRL_CHIPPN_PN_APOLLO2            = 3,     /*!< APOLLO2 : Apollo2 part number is 0x03xxxxxx.                              */
  MCUCTRL_CHIPPN_PN_APOLLO             = 1,     /*!< APOLLO : Apollo part number is 0x01xxxxxx.                                */
} MCUCTRL_CHIPPN_PN_Enum;

/* ===========================================  MCUCTRL CHIPPN MRAMSIZE [20..23]  ============================================ */
typedef enum {                                  /*!< MCUCTRL_CHIPPN_MRAMSIZE                                                   */
  MCUCTRL_CHIPPN_MRAMSIZE_0P5MB        = 0,     /*!< 0P5MB : MRAM size is 0.5MB                                                */
  MCUCTRL_CHIPPN_MRAMSIZE_1P0MB        = 1,     /*!< 1P0MB : MRAM size is 1.0MB                                                */
  MCUCTRL_CHIPPN_MRAMSIZE_1P5MB        = 2,     /*!< 1P5MB : MRAM size is 1.5MB                                                */
  MCUCTRL_CHIPPN_MRAMSIZE_2P0MB        = 3,     /*!< 2P0MB : MRAM size is 2.0MB                                                */
} MCUCTRL_CHIPPN_MRAMSIZE_Enum;

/* ===========================================  MCUCTRL CHIPPN SRAMSIZE [16..19]  ============================================ */
typedef enum {                                  /*!< MCUCTRL_CHIPPN_SRAMSIZE                                                   */
  MCUCTRL_CHIPPN_SRAMSIZE_384_512      = 0,     /*!< 384_512 : SRAM size is 384KB+512KB                                        */
  MCUCTRL_CHIPPN_SRAMSIZE_384_1024     = 1,     /*!< 384_1024 : SRAM size is 384KB+1MB                                         */
  MCUCTRL_CHIPPN_SRAMSIZE_384_1024_384_96 = 2,  /*!< 384_1024_384_96 : SRAM size is 384KB+1MB+384KB+96KB                       */
} MCUCTRL_CHIPPN_SRAMSIZE_Enum;

/* ============================================  MCUCTRL CHIPPN REVMAJ [12..15]  ============================================= */
typedef enum {                                  /*!< MCUCTRL_CHIPPN_REVMAJ                                                     */
  MCUCTRL_CHIPPN_REVMAJ_A              = 0,     /*!< A : Major Rev A                                                           */
  MCUCTRL_CHIPPN_REVMAJ_B              = 1,     /*!< B : Major Rev B                                                           */
  MCUCTRL_CHIPPN_REVMAJ_C              = 2,     /*!< C : Major Rev C                                                           */
} MCUCTRL_CHIPPN_REVMAJ_Enum;

/* =============================================  MCUCTRL CHIPPN REVMIN [8..11]  ============================================= */
typedef enum {                                  /*!< MCUCTRL_CHIPPN_REVMIN                                                     */
  MCUCTRL_CHIPPN_REVMIN_0              = 0,     /*!< 0 : Minor Rev 0                                                           */
  MCUCTRL_CHIPPN_REVMIN_1              = 1,     /*!< 1 : Minor Rev 1                                                           */
} MCUCTRL_CHIPPN_REVMIN_Enum;

/* ===============================================  MCUCTRL CHIPPN PKG [6..7]  =============================================== */
typedef enum {                                  /*!< MCUCTRL_CHIPPN_PKG                                                        */
  MCUCTRL_CHIPPN_PKG_SIP               = 0,     /*!< SIP : SIP package.                                                        */
  MCUCTRL_CHIPPN_PKG_QFN               = 1,     /*!< QFN : QFN package.                                                        */
  MCUCTRL_CHIPPN_PKG_BGA               = 2,     /*!< BGA : BGA package.                                                        */
  MCUCTRL_CHIPPN_PKG_CSP               = 3,     /*!< CSP : CSP package.                                                        */
} MCUCTRL_CHIPPN_PKG_Enum;

/* ==============================================  MCUCTRL CHIPPN PINS [3..5]  =============================================== */
typedef enum {                                  /*!< MCUCTRL_CHIPPN_PINS                                                       */
  MCUCTRL_CHIPPN_PINS_25               = 0,     /*!< 25 : 25 pins                                                              */
  MCUCTRL_CHIPPN_PINS_49               = 1,     /*!< 49 : 49 pins                                                              */
  MCUCTRL_CHIPPN_PINS_64               = 2,     /*!< 64 : 64 pins                                                              */
  MCUCTRL_CHIPPN_PINS_81               = 3,     /*!< 81 : 81 pins                                                              */
} MCUCTRL_CHIPPN_PINS_Enum;

/* ==============================================  MCUCTRL CHIPPN TEMP [1..2]  =============================================== */
typedef enum {                                  /*!< MCUCTRL_CHIPPN_TEMP                                                       */
  MCUCTRL_CHIPPN_TEMP_COM              = 0,     /*!< COM : Commercial temperature                                              */
  MCUCTRL_CHIPPN_TEMP_MIL              = 1,     /*!< MIL : Military temperature                                                */
  MCUCTRL_CHIPPN_TEMP_AUTO             = 2,     /*!< AUTO : Automotive temperature                                             */
  MCUCTRL_CHIPPN_TEMP_IND              = 3,     /*!< IND : Industrial temperature                                              */
} MCUCTRL_CHIPPN_TEMP_Enum;

/* ========================================================  CHIPID0  ======================================================== */
/* ========================================================  CHIPID1  ======================================================== */
/* ========================================================  CHIPREV  ======================================================== */
/* =============================================  MCUCTRL CHIPREV REVMAJ [4..7]  ============================================= */
typedef enum {                                  /*!< MCUCTRL_CHIPREV_REVMAJ                                                    */
  MCUCTRL_CHIPREV_REVMAJ_C             = 3,     /*!< C : Apollo4 revision C                                                    */
  MCUCTRL_CHIPREV_REVMAJ_B             = 2,     /*!< B : Apollo4 revision B                                                    */
  MCUCTRL_CHIPREV_REVMAJ_A             = 1,     /*!< A : Apollo4 revision A                                                    */
} MCUCTRL_CHIPREV_REVMAJ_Enum;

/* =============================================  MCUCTRL CHIPREV REVMIN [0..3]  ============================================= */
typedef enum {                                  /*!< MCUCTRL_CHIPREV_REVMIN                                                    */
  MCUCTRL_CHIPREV_REVMIN_REV2          = 3,     /*!< REV2 : Apollo4 minor rev 2.                                               */
  MCUCTRL_CHIPREV_REVMIN_REV1          = 2,     /*!< REV1 : Apollo4 minor rev 1.                                               */
  MCUCTRL_CHIPREV_REVMIN_REV0          = 1,     /*!< REV0 : Apollo4 minor rev 0. Minor revision value, succeeding
                                                     minor revisions will increment from this value.                           */
} MCUCTRL_CHIPREV_REVMIN_Enum;

/* =======================================================  VENDORID  ======================================================== */
/* ===========================================  MCUCTRL VENDORID VENDORID [0..31]  =========================================== */
typedef enum {                                  /*!< MCUCTRL_VENDORID_VENDORID                                                 */
  MCUCTRL_VENDORID_VENDORID_AMBIQ      = 1095582289,/*!< AMBIQ : Ambiq Vendor ID 'AMBQ'                                        */
  MCUCTRL_VENDORID_VENDORID_DEFAULT    = 0,     /*!< DEFAULT : Default Vendor ID                                               */
} MCUCTRL_VENDORID_VENDORID_Enum;

/* ==========================================================  SKU  ========================================================== */
/* =======================================================  DEBUGGER  ======================================================== */
/* =========================================================  ACRG  ========================================================== */
/* ===========================================  MCUCTRL ACRG ACRGIBIASSEL [2..2]  ============================================ */
typedef enum {                                  /*!< MCUCTRL_ACRG_ACRGIBIASSEL                                                 */
  MCUCTRL_ACRG_ACRGIBIASSEL_BGSEL      = 0,     /*!< BGSEL : Selects the bandgap                                               */
  MCUCTRL_ACRG_ACRGIBIASSEL_CCRGSEL    = 1,     /*!< CCRGSEL : Selects the CCRG                                                */
} MCUCTRL_ACRG_ACRGIBIASSEL_Enum;

/* ==============================================  MCUCTRL ACRG ACRGPWD [1..1]  ============================================== */
typedef enum {                                  /*!< MCUCTRL_ACRG_ACRGPWD                                                      */
  MCUCTRL_ACRG_ACRGPWD_ACRG_PWR_DN     = 1,     /*!< ACRG_PWR_DN : Powers down the ACRG trim.                                  */
  MCUCTRL_ACRG_ACRGPWD_ACRG_PWR_UP     = 0,     /*!< ACRG_PWR_UP : Power up the ACRG trim.                                     */
} MCUCTRL_ACRG_ACRGPWD_Enum;

/* =======================================================  VREFGEN2  ======================================================== */
/* ==========================================  MCUCTRL VREFGEN2 TVRG2PWD [19..19]  =========================================== */
typedef enum {                                  /*!< MCUCTRL_VREFGEN2_TVRG2PWD                                                 */
  MCUCTRL_VREFGEN2_TVRG2PWD_PWR_DN     = 1,     /*!< PWR_DN : Powers down the CVRG.                                            */
  MCUCTRL_VREFGEN2_TVRG2PWD_PWR_UP     = 0,     /*!< PWR_UP : Power up the CVRG.                                               */
} MCUCTRL_VREFGEN2_TVRG2PWD_Enum;

/* ============================================  MCUCTRL VREFGEN2 TVRGPWD [5..5]  ============================================ */
typedef enum {                                  /*!< MCUCTRL_VREFGEN2_TVRGPWD                                                  */
  MCUCTRL_VREFGEN2_TVRGPWD_PWR_DN      = 1,     /*!< PWR_DN : Powers down the CVRG.                                            */
  MCUCTRL_VREFGEN2_TVRGPWD_PWR_UP      = 0,     /*!< PWR_UP : Power up the CVRG.                                               */
} MCUCTRL_VREFGEN2_TVRGPWD_Enum;

/* ========================================================  VRCTRL  ========================================================= */
/* ========================================================  LDOREG1  ======================================================== */
/* ========================================================  LDOREG2  ======================================================== */
/* =========================================================  HFRC2  ========================================================= */
/* =========================================================  LFRC  ========================================================== */
/* =========================================  MCUCTRL LFRC LFRCSIMOCLKDIV [10..12]  ========================================== */
typedef enum {                                  /*!< MCUCTRL_LFRC_LFRCSIMOCLKDIV                                               */
  MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV1     = 0,     /*!< DIV1 : Divide by 1                                                        */
  MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV2     = 1,     /*!< DIV2 : Divide by 2                                                        */
  MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV4     = 2,     /*!< DIV4 : Divide by 4                                                        */
  MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV8     = 3,     /*!< DIV8 : Divide by 8                                                        */
  MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV16    = 4,     /*!< DIV16 : Divide by 16                                                      */
  MCUCTRL_LFRC_LFRCSIMOCLKDIV_DIV32    = 5,     /*!< DIV32 : Divide by 32                                                      */
} MCUCTRL_LFRC_LFRCSIMOCLKDIV_Enum;

/* =============================================  MCUCTRL LFRC RESETLFRC [7..7]  ============================================= */
typedef enum {                                  /*!< MCUCTRL_LFRC_RESETLFRC                                                    */
  MCUCTRL_LFRC_RESETLFRC_EN            = 0,     /*!< EN : Enable LFRC.                                                         */
  MCUCTRL_LFRC_RESETLFRC_RESET         = 1,     /*!< RESET : Reset LFRC.                                                       */
} MCUCTRL_LFRC_RESETLFRC_Enum;

/* ==============================================  MCUCTRL LFRC PWDLFRC [6..6]  ============================================== */
typedef enum {                                  /*!< MCUCTRL_LFRC_PWDLFRC                                                      */
  MCUCTRL_LFRC_PWDLFRC_PWRUP           = 0,     /*!< PWRUP : Power up LFRC.                                                    */
  MCUCTRL_LFRC_PWDLFRC_PWRDN           = 1,     /*!< PWRDN : Power down LFRC.                                                  */
} MCUCTRL_LFRC_PWDLFRC_Enum;

/* ==============================================  MCUCTRL LFRC LFRCSWE [0..0]  ============================================== */
typedef enum {                                  /*!< MCUCTRL_LFRC_LFRCSWE                                                      */
  MCUCTRL_LFRC_LFRCSWE_OVERRIDE_DIS    = 0,     /*!< OVERRIDE_DIS : LFRC Software Override Disable.                            */
  MCUCTRL_LFRC_LFRCSWE_OVERRIDE_EN     = 1,     /*!< OVERRIDE_EN : LFRC Software Override Enable.                              */
} MCUCTRL_LFRC_LFRCSWE_Enum;

/* ========================================================  BODCTRL  ======================================================== */
/* =======================================================  ADCPWRDLY  ======================================================= */
/* ======================================================  ADCPWRCTRL  ======================================================= */
/* ========================================  MCUCTRL ADCPWRCTRL VDDADCRESETN [9..9]  ========================================= */
typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_VDDADCRESETN                                           */
  MCUCTRL_ADCPWRCTRL_VDDADCRESETN_ASSERT = 0,   /*!< ASSERT : Resetn is asserted                                               */
  MCUCTRL_ADCPWRCTRL_VDDADCRESETN_DEASSERT = 1, /*!< DEASSERT : Resetn is de-asserted                                          */
} MCUCTRL_ADCPWRCTRL_VDDADCRESETN_Enum;

/* ======================================  MCUCTRL ADCPWRCTRL VDDADCDIGISOLATE [8..8]  ======================================= */
typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE                                       */
  MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE_DIS = 0,  /*!< DIS : No Isolation                                                        */
  MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE_EN = 1,   /*!< EN : Isolate                                                              */
} MCUCTRL_ADCPWRCTRL_VDDADCDIGISOLATE_Enum;

/* ======================================  MCUCTRL ADCPWRCTRL VDDADCSARISOLATE [7..7]  ======================================= */
typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE                                       */
  MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE_DIS = 0,  /*!< DIS : No Isolation                                                        */
  MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE_EN = 1,   /*!< EN : Isolate                                                              */
} MCUCTRL_ADCPWRCTRL_VDDADCSARISOLATE_Enum;

/* =========================================  MCUCTRL ADCPWRCTRL REFKEEPPEN [6..6]  ========================================== */
typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_REFKEEPPEN                                             */
  MCUCTRL_ADCPWRCTRL_REFKEEPPEN_DIS    = 0,     /*!< DIS : Reference Buffer Keeper Power Switch disable.                       */
  MCUCTRL_ADCPWRCTRL_REFKEEPPEN_EN     = 1,     /*!< EN : Reference Buffer Keeper Power Switch enable.                         */
} MCUCTRL_ADCPWRCTRL_REFKEEPPEN_Enum;

/* ==========================================  MCUCTRL ADCPWRCTRL REFBUFPEN [5..5]  ========================================== */
typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_REFBUFPEN                                              */
  MCUCTRL_ADCPWRCTRL_REFBUFPEN_DIS     = 0,     /*!< DIS : Reference Buffer Power Switch disable.                              */
  MCUCTRL_ADCPWRCTRL_REFBUFPEN_EN      = 1,     /*!< EN : Reference Buffer Power Switch enable.                                */
} MCUCTRL_ADCPWRCTRL_REFBUFPEN_Enum;

/* ==========================================  MCUCTRL ADCPWRCTRL BGTLPPEN [4..4]  =========================================== */
typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_BGTLPPEN                                               */
  MCUCTRL_ADCPWRCTRL_BGTLPPEN_DIS      = 0,     /*!< DIS : Bandgap and temperature sensor disable.                             */
  MCUCTRL_ADCPWRCTRL_BGTLPPEN_EN       = 1,     /*!< EN : Bandgap and temperature sensor enable.                               */
} MCUCTRL_ADCPWRCTRL_BGTLPPEN_Enum;

/* ===========================================  MCUCTRL ADCPWRCTRL BGTPEN [3..3]  ============================================ */
typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_BGTPEN                                                 */
  MCUCTRL_ADCPWRCTRL_BGTPEN_DIS        = 0,     /*!< DIS : Bandgap and temperature sensor disable.                             */
  MCUCTRL_ADCPWRCTRL_BGTPEN_EN         = 1,     /*!< EN : Bandgap and temperature sensor enable.                               */
} MCUCTRL_ADCPWRCTRL_BGTPEN_Enum;

/* ==========================================  MCUCTRL ADCPWRCTRL ADCBPSEN [2..2]  =========================================== */
typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_ADCBPSEN                                               */
  MCUCTRL_ADCPWRCTRL_ADCBPSEN_DIS      = 0,     /*!< DIS : ADC power switch software power disable.                            */
  MCUCTRL_ADCPWRCTRL_ADCBPSEN_EN       = 1,     /*!< EN : ADC power switch software power enable.                              */
} MCUCTRL_ADCPWRCTRL_ADCBPSEN_Enum;

/* ==========================================  MCUCTRL ADCPWRCTRL ADCAPSEN [1..1]  =========================================== */
typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_ADCAPSEN                                               */
  MCUCTRL_ADCPWRCTRL_ADCAPSEN_DIS      = 0,     /*!< DIS : ADC power switch software power disable.                            */
  MCUCTRL_ADCPWRCTRL_ADCAPSEN_EN       = 1,     /*!< EN : ADC power switch software power enable.                              */
} MCUCTRL_ADCPWRCTRL_ADCAPSEN_Enum;

/* ========================================  MCUCTRL ADCPWRCTRL ADCPWRCTRLSWE [0..0]  ======================================== */
typedef enum {                                  /*!< MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE                                          */
  MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE_OVERRIDE_DIS = 0,/*!< OVERRIDE_DIS : ADC temperature sensor and bandgap Software Override
                                                     Disable.                                                                  */
  MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE_OVERRIDE_EN = 1,/*!< OVERRIDE_EN : ADC temperature sensor and bandgap Software Override
                                                     Enable.                                                                   */
} MCUCTRL_ADCPWRCTRL_ADCPWRCTRLSWE_Enum;

/* ========================================================  ADCCAL  ========================================================= */
/* ==========================================  MCUCTRL ADCCAL ADCCALIBRATED [1..1]  ========================================== */
typedef enum {                                  /*!< MCUCTRL_ADCCAL_ADCCALIBRATED                                              */
  MCUCTRL_ADCCAL_ADCCALIBRATED_FALSE   = 0,     /*!< FALSE : ADC is not calibrated                                             */
  MCUCTRL_ADCCAL_ADCCALIBRATED_TRUE    = 1,     /*!< TRUE : ADC is calibrated                                                  */
} MCUCTRL_ADCCAL_ADCCALIBRATED_Enum;

/* ===========================================  MCUCTRL ADCCAL CALONPWRUP [0..0]  ============================================ */
typedef enum {                                  /*!< MCUCTRL_ADCCAL_CALONPWRUP                                                 */
  MCUCTRL_ADCCAL_CALONPWRUP_DIS        = 0,     /*!< DIS : Disable automatic calibration on initial power up                   */
  MCUCTRL_ADCCAL_CALONPWRUP_EN         = 1,     /*!< EN : Enable automatic calibration on initial power up                     */
} MCUCTRL_ADCCAL_CALONPWRUP_Enum;

/* ======================================================  ADCBATTLOAD  ====================================================== */
/* ==========================================  MCUCTRL ADCBATTLOAD BATTLOAD [0..0]  ========================================== */
typedef enum {                                  /*!< MCUCTRL_ADCBATTLOAD_BATTLOAD                                              */
  MCUCTRL_ADCBATTLOAD_BATTLOAD_DIS     = 0,     /*!< DIS : Battery load is disconnected                                        */
  MCUCTRL_ADCBATTLOAD_BATTLOAD_EN      = 1,     /*!< EN : Battery load is enabled                                              */
} MCUCTRL_ADCBATTLOAD_BATTLOAD_Enum;

/* =======================================================  XTALCTRL  ======================================================== */
/* =========================================  MCUCTRL XTALCTRL XTALCOMPPDNB [4..4]  ========================================== */
typedef enum {                                  /*!< MCUCTRL_XTALCTRL_XTALCOMPPDNB                                             */
  MCUCTRL_XTALCTRL_XTALCOMPPDNB_PWRUPCOMP = 1,  /*!< PWRUPCOMP : Power up XTAL oscillator comparator.                          */
  MCUCTRL_XTALCTRL_XTALCOMPPDNB_PWRDNCOMP = 0,  /*!< PWRDNCOMP : Power down XTAL oscillator comparator.                        */
} MCUCTRL_XTALCTRL_XTALCOMPPDNB_Enum;

/* ===========================================  MCUCTRL XTALCTRL XTALPDNB [3..3]  ============================================ */
typedef enum {                                  /*!< MCUCTRL_XTALCTRL_XTALPDNB                                                 */
  MCUCTRL_XTALCTRL_XTALPDNB_PWRUPCORE  = 1,     /*!< PWRUPCORE : Power up XTAL oscillator core.                                */
  MCUCTRL_XTALCTRL_XTALPDNB_PWRDNCORE  = 0,     /*!< PWRDNCORE : Power down XTAL oscillator core.                              */
} MCUCTRL_XTALCTRL_XTALPDNB_Enum;

/* ========================================  MCUCTRL XTALCTRL XTALCOMPBYPASS [2..2]  ========================================= */
typedef enum {                                  /*!< MCUCTRL_XTALCTRL_XTALCOMPBYPASS                                           */
  MCUCTRL_XTALCTRL_XTALCOMPBYPASS_USECOMP = 0,  /*!< USECOMP : Use the XTAL oscillator comparator.                             */
  MCUCTRL_XTALCTRL_XTALCOMPBYPASS_BYPCOMP = 1,  /*!< BYPCOMP : Bypass the XTAL oscillator comparator.                          */
} MCUCTRL_XTALCTRL_XTALCOMPBYPASS_Enum;

/* =========================================  MCUCTRL XTALCTRL XTALCOREDISFB [1..1]  ========================================= */
typedef enum {                                  /*!< MCUCTRL_XTALCTRL_XTALCOREDISFB                                            */
  MCUCTRL_XTALCTRL_XTALCOREDISFB_EN    = 0,     /*!< EN : Enable XTAL oscillator comparator.                                   */
  MCUCTRL_XTALCTRL_XTALCOREDISFB_DIS   = 1,     /*!< DIS : Disable XTAL oscillator comparator.                                 */
} MCUCTRL_XTALCTRL_XTALCOREDISFB_Enum;

/* ============================================  MCUCTRL XTALCTRL XTALSWE [0..0]  ============================================ */
typedef enum {                                  /*!< MCUCTRL_XTALCTRL_XTALSWE                                                  */
  MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_DIS = 0,    /*!< OVERRIDE_DIS : XTAL Software Override Disable.                            */
  MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_EN = 1,     /*!< OVERRIDE_EN : XTAL Software Override Enable.                              */
} MCUCTRL_XTALCTRL_XTALSWE_Enum;

/* ======================================================  XTALGENCTRL  ====================================================== */
/* ==========================================  MCUCTRL XTALGENCTRL ACWARMUP [0..1]  ========================================== */
typedef enum {                                  /*!< MCUCTRL_XTALGENCTRL_ACWARMUP                                              */
  MCUCTRL_XTALGENCTRL_ACWARMUP_SEC1    = 0,     /*!< SEC1 : Warmup period of 1-2 seconds                                       */
  MCUCTRL_XTALGENCTRL_ACWARMUP_SEC2    = 1,     /*!< SEC2 : Warmup period of 2-4 seconds                                       */
  MCUCTRL_XTALGENCTRL_ACWARMUP_SEC4    = 2,     /*!< SEC4 : Warmup period of 4-8 seconds                                       */
  MCUCTRL_XTALGENCTRL_ACWARMUP_SEC8    = 3,     /*!< SEC8 : Warmup period of 8-16 seconds                                      */
} MCUCTRL_XTALGENCTRL_ACWARMUP_Enum;

/* ======================================================  XTALHSTRIMS  ====================================================== */
/* ======================================================  XTALHSCTRL  ======================================================= */
/* ======================================================  MRAMPWRCTRL  ====================================================== */
/* =======================================================  BODISABLE  ======================================================= */
/* ==========================================  MCUCTRL BODISABLE BODCLVREN [4..4]  =========================================== */
typedef enum {                                  /*!< MCUCTRL_BODISABLE_BODCLVREN                                               */
  MCUCTRL_BODISABLE_BODCLVREN_EN       = 1,     /*!< EN : Enable VDDC_LV Brown Out reset.                                      */
  MCUCTRL_BODISABLE_BODCLVREN_DIS      = 0,     /*!< DIS : Disable VDDC_LV Brown Out reset.                                    */
} MCUCTRL_BODISABLE_BODCLVREN_Enum;

/* ===========================================  MCUCTRL BODISABLE BODSREN [3..3]  ============================================ */
typedef enum {                                  /*!< MCUCTRL_BODISABLE_BODSREN                                                 */
  MCUCTRL_BODISABLE_BODSREN_EN         = 1,     /*!< EN : Enable VDDS Brown Out reset.                                         */
  MCUCTRL_BODISABLE_BODSREN_DIS        = 0,     /*!< DIS : Disable VDDS Brown Out reset.                                       */
} MCUCTRL_BODISABLE_BODSREN_Enum;

/* ===========================================  MCUCTRL BODISABLE BODFREN [2..2]  ============================================ */
typedef enum {                                  /*!< MCUCTRL_BODISABLE_BODFREN                                                 */
  MCUCTRL_BODISABLE_BODFREN_EN         = 1,     /*!< EN : Enable VDDF Brown Out reset.                                         */
  MCUCTRL_BODISABLE_BODFREN_DIS        = 0,     /*!< DIS : Disable VDDF Brown Out reset.                                       */
} MCUCTRL_BODISABLE_BODFREN_Enum;

/* ===========================================  MCUCTRL BODISABLE BODCREN [1..1]  ============================================ */
typedef enum {                                  /*!< MCUCTRL_BODISABLE_BODCREN                                                 */
  MCUCTRL_BODISABLE_BODCREN_EN         = 1,     /*!< EN : Enable VDDC Brown Out reset.                                         */
  MCUCTRL_BODISABLE_BODCREN_DIS        = 0,     /*!< DIS : Disable VDDC Brown Out reset.                                       */
} MCUCTRL_BODISABLE_BODCREN_Enum;

/* ===========================================  MCUCTRL BODISABLE BODLRDE [0..0]  ============================================ */
typedef enum {                                  /*!< MCUCTRL_BODISABLE_BODLRDE                                                 */
  MCUCTRL_BODISABLE_BODLRDE_EN         = 0,     /*!< EN : Enable Unregulated 1.8v brown out reset.                             */
  MCUCTRL_BODISABLE_BODLRDE_DIS        = 1,     /*!< DIS : Disable Unregulated 1.8v brown out reset.                           */
} MCUCTRL_BODISABLE_BODLRDE_Enum;

/* ======================================================  BOOTLOADER  ======================================================= */
/* =======================================  MCUCTRL BOOTLOADER SECBOOTONRST [30..31]  ======================================== */
typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SECBOOTONRST                                           */
  MCUCTRL_BOOTLOADER_SECBOOTONRST_DISABLED = 0, /*!< DISABLED : Secure boot disabled                                           */
  MCUCTRL_BOOTLOADER_SECBOOTONRST_ENABLED = 1,  /*!< ENABLED : Secure boot enabled                                             */
  MCUCTRL_BOOTLOADER_SECBOOTONRST_ERROR = 2,    /*!< ERROR : Error in secure boot configuration                                */
} MCUCTRL_BOOTLOADER_SECBOOTONRST_Enum;

/* ==========================================  MCUCTRL BOOTLOADER SECBOOT [28..29]  ========================================== */
typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SECBOOT                                                */
  MCUCTRL_BOOTLOADER_SECBOOT_DISABLED  = 0,     /*!< DISABLED : Secure boot disabled                                           */
  MCUCTRL_BOOTLOADER_SECBOOT_ENABLED   = 1,     /*!< ENABLED : Secure boot enabled                                             */
  MCUCTRL_BOOTLOADER_SECBOOT_ERROR     = 2,     /*!< ERROR : Error in secure boot configuration                                */
} MCUCTRL_BOOTLOADER_SECBOOT_Enum;

/* ======================================  MCUCTRL BOOTLOADER SECBOOTFEATURE [26..27]  ======================================= */
typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SECBOOTFEATURE                                         */
  MCUCTRL_BOOTLOADER_SECBOOTFEATURE_DISABLED = 0,/*!< DISABLED : Secure boot disabled                                          */
  MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ENABLED = 1,/*!< ENABLED : Secure boot enabled                                             */
  MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ERROR = 2,  /*!< ERROR : Error in secure boot configuration                                */
} MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Enum;

/* ===========================================  MCUCTRL BOOTLOADER SBLLOCK [3..3]  =========================================== */
typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SBLLOCK                                                */
  MCUCTRL_BOOTLOADER_SBLLOCK_LOCK      = 1,     /*!< LOCK : Enable the secure boot lock                                        */
  MCUCTRL_BOOTLOADER_SBLLOCK_UNLOCK    = 0,     /*!< UNLOCK : Disable the secure boot lock                                     */
} MCUCTRL_BOOTLOADER_SBLLOCK_Enum;

/* ==========================================  MCUCTRL BOOTLOADER PROTLOCK [2..2]  =========================================== */
typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_PROTLOCK                                               */
  MCUCTRL_BOOTLOADER_PROTLOCK_LOCK     = 1,     /*!< LOCK : On write, this value asserts the lock. On read, see above
                                                     description.                                                              */
  MCUCTRL_BOOTLOADER_PROTLOCK_DEFAULT  = 0,     /*!< DEFAULT : On write, this value (writing 0) has no effect. On
                                                     read, see above description.                                              */
} MCUCTRL_BOOTLOADER_PROTLOCK_Enum;

/* ===========================================  MCUCTRL BOOTLOADER SBRLOCK [1..1]  =========================================== */
typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SBRLOCK                                                */
  MCUCTRL_BOOTLOADER_SBRLOCK_LOCK      = 1,     /*!< LOCK : Enable the secure boot lock                                        */
  MCUCTRL_BOOTLOADER_SBRLOCK_DEFAULT   = 0,     /*!< DEFAULT : Default value.                                                  */
} MCUCTRL_BOOTLOADER_SBRLOCK_Enum;

/* ========================================  MCUCTRL BOOTLOADER BOOTLOADERLOW [0..0]  ======================================== */
typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_BOOTLOADERLOW                                          */
  MCUCTRL_BOOTLOADER_BOOTLOADERLOW_ADDR0 = 1,   /*!< ADDR0 : Bootloader code at 0x00000000.                                    */
  MCUCTRL_BOOTLOADER_BOOTLOADERLOW_NOADDR0 = 0, /*!< NOADDR0 : Bootloader code is not visible at address                       */
} MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Enum;

/* ======================================================  SHADOWVALID  ====================================================== */
/* =========================================  MCUCTRL SHADOWVALID INFO0VALID [2..2]  ========================================= */
typedef enum {                                  /*!< MCUCTRL_SHADOWVALID_INFO0VALID                                            */
  MCUCTRL_SHADOWVALID_INFO0VALID_VALID = 1,     /*!< VALID : Flash info0 (customer) space contains valid data.                 */
  MCUCTRL_SHADOWVALID_INFO0VALID_DEFAULT = 0,   /*!< DEFAULT : Default value.                                                  */
} MCUCTRL_SHADOWVALID_INFO0VALID_Enum;

/* ==========================================  MCUCTRL SHADOWVALID BLDSLEEP [1..1]  ========================================== */
typedef enum {                                  /*!< MCUCTRL_SHADOWVALID_BLDSLEEP                                              */
  MCUCTRL_SHADOWVALID_BLDSLEEP_DEEPSLEEP = 1,   /*!< DEEPSLEEP : Bootloader will go to deep sleep if no flash image
                                                     loaded                                                                    */
  MCUCTRL_SHADOWVALID_BLDSLEEP_SLEEP   = 0,     /*!< SLEEP : Bootloader will go to normalsleep if no flash image
                                                     loaded                                                                    */
} MCUCTRL_SHADOWVALID_BLDSLEEP_Enum;

/* ===========================================  MCUCTRL SHADOWVALID VALID [0..0]  ============================================ */
typedef enum {                                  /*!< MCUCTRL_SHADOWVALID_VALID                                                 */
  MCUCTRL_SHADOWVALID_VALID_VALID      = 1,     /*!< VALID : Flash information space contains valid data.                      */
  MCUCTRL_SHADOWVALID_VALID_DEFAULT    = 0,     /*!< DEFAULT : Default value.                                                  */
} MCUCTRL_SHADOWVALID_VALID_Enum;

/* =======================================================  SCRATCH0  ======================================================== */
/* =======================================================  SCRATCH1  ======================================================== */
/* =========================================================  DBGR1  ========================================================= */
/* =========================================================  DBGR2  ========================================================= */
/* =======================================================  PMUENABLE  ======================================================= */
/* ============================================  MCUCTRL PMUENABLE ENABLE [0..0]  ============================================ */
typedef enum {                                  /*!< MCUCTRL_PMUENABLE_ENABLE                                                  */
  MCUCTRL_PMUENABLE_ENABLE_DIS         = 0,     /*!< DIS : Disable MCU power management.                                       */
  MCUCTRL_PMUENABLE_ENABLE_EN          = 1,     /*!< EN : Enable MCU power management.                                         */
} MCUCTRL_PMUENABLE_ENABLE_Enum;

/* ========================================================  DBGCTRL  ======================================================== */
/* =====================================  MCUCTRL DBGCTRL DBGDSP1OCDHALTONRST [17..17]  ====================================== */
typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST                                       */
  MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST_DIS = 0,  /*!< DIS : Disable DSP1 OCD Halt on Reset.                                     */
  MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST_EN = 1,   /*!< EN : Enable DSP1 OCD Halt on Reset.                                       */
} MCUCTRL_DBGCTRL_DBGDSP1OCDHALTONRST_Enum;

/* =====================================  MCUCTRL DBGCTRL DBGDSP0OCDHALTONRST [16..16]  ====================================== */
typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST                                       */
  MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST_DIS = 0,  /*!< DIS : Disable DSP0 OCD Halt on Reset.                                     */
  MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST_EN = 1,   /*!< EN : Enable DSP0 OCD Halt on Reset.                                       */
} MCUCTRL_DBGCTRL_DBGDSP0OCDHALTONRST_Enum;

/* =========================================  MCUCTRL DBGCTRL DBGTSCLKSEL [12..14]  ========================================== */
typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGTSCLKSEL                                               */
  MCUCTRL_DBGCTRL_DBGTSCLKSEL_LOWPWR   = 0,     /*!< LOWPWR : Low power state.                                                 */
  MCUCTRL_DBGCTRL_DBGTSCLKSEL_HFRCDIV2 = 1,     /*!< HFRCDIV2 : Selects HFRC divided by 2 as the source dbg ts clk             */
  MCUCTRL_DBGCTRL_DBGTSCLKSEL_HFRCDIV8 = 2,     /*!< HFRCDIV8 : Selects HFRC divided by 8 as the source dbg ts clk             */
  MCUCTRL_DBGCTRL_DBGTSCLKSEL_HFRCDIV16 = 3,    /*!< HFRCDIV16 : Selects HFRC divided by 16 as the source dbg ts
                                                     clk                                                                       */
  MCUCTRL_DBGCTRL_DBGTSCLKSEL_HFRCDIV32 = 4,    /*!< HFRCDIV32 : Selects HFRC divided by 32 as the source dbg ts
                                                     clk                                                                       */
} MCUCTRL_DBGCTRL_DBGTSCLKSEL_Enum;

/* ========================================  MCUCTRL DBGCTRL DBGDSP1TRACEEN [11..11]  ======================================== */
typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGDSP1TRACEEN                                            */
  MCUCTRL_DBGCTRL_DBGDSP1TRACEEN_DIS   = 0,     /*!< DIS : Disable DSP1 trace.                                                 */
  MCUCTRL_DBGCTRL_DBGDSP1TRACEEN_EN    = 1,     /*!< EN : Enable DSP1 trace.                                                   */
} MCUCTRL_DBGCTRL_DBGDSP1TRACEEN_Enum;

/* ========================================  MCUCTRL DBGCTRL DBGDSP0TRACEEN [10..10]  ======================================== */
typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGDSP0TRACEEN                                            */
  MCUCTRL_DBGCTRL_DBGDSP0TRACEEN_DIS   = 0,     /*!< DIS : Disable DSP0 trace.                                                 */
  MCUCTRL_DBGCTRL_DBGDSP0TRACEEN_EN    = 1,     /*!< EN : Enable DSP0 trace.                                                   */
} MCUCTRL_DBGCTRL_DBGDSP0TRACEEN_Enum;

/* =========================================  MCUCTRL DBGCTRL DBGETMTRACEEN [9..9]  ========================================== */
typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGETMTRACEEN                                             */
  MCUCTRL_DBGCTRL_DBGETMTRACEEN_DIS    = 0,     /*!< DIS : Disable ETM trace.                                                  */
  MCUCTRL_DBGCTRL_DBGETMTRACEEN_EN     = 1,     /*!< EN : Enable ETM trace.                                                    */
} MCUCTRL_DBGCTRL_DBGETMTRACEEN_Enum;

/* ==========================================  MCUCTRL DBGCTRL DBGETBENABLE [8..8]  ========================================== */
typedef enum {                                  /*!< MCUCTRL_DBGCTRL_DBGETBENABLE                                              */
  MCUCTRL_DBGCTRL_DBGETBENABLE_DIS     = 0,     /*!< DIS : Disable ETB.                                                        */
  MCUCTRL_DBGCTRL_DBGETBENABLE_EN      = 1,     /*!< EN : Enable ETB.                                                          */
} MCUCTRL_DBGCTRL_DBGETBENABLE_Enum;

/* ===========================================  MCUCTRL DBGCTRL CM4CLKSEL [1..3]  ============================================ */
typedef enum {                                  /*!< MCUCTRL_DBGCTRL_CM4CLKSEL                                                 */
  MCUCTRL_DBGCTRL_CM4CLKSEL_LOWPWR     = 0,     /*!< LOWPWR : Low power state.                                                 */
  MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC96     = 1,     /*!< HFRC96 : Selects HFRC 96Mhz as the source TPIU clk                        */
  MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC48     = 2,     /*!< HFRC48 : Selects HFRC 48Mhz as the source TPIU clk                        */
  MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC24     = 3,     /*!< HFRC24 : Selects HFRC 24Mhz as the source TPIU clk                        */
  MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC6      = 4,     /*!< HFRC6 : Selects HFRC 6Mhz as the source TPIU clk                          */
  MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC3      = 5,     /*!< HFRC3 : Selects HFRC 3Mhz as the source TPIU clk                          */
  MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC1P5    = 6,     /*!< HFRC1P5 : Selects HFRC 1.5Mhz as the source TPIU clk                      */
  MCUCTRL_DBGCTRL_CM4CLKSEL_HFRC2_192  = 7,     /*!< HFRC2_192 : Selects HFRC2 192Mhz as the source TPIU clk. Note
                                                     that this setting requires CLKGEN.MISC.HFRC2 be enabled.                  */
} MCUCTRL_DBGCTRL_CM4CLKSEL_Enum;

/* =========================================  MCUCTRL DBGCTRL CM4TPIUENABLE [0..0]  ========================================== */
typedef enum {                                  /*!< MCUCTRL_DBGCTRL_CM4TPIUENABLE                                             */
  MCUCTRL_DBGCTRL_CM4TPIUENABLE_DIS    = 0,     /*!< DIS : Disable the TPIU.                                                   */
  MCUCTRL_DBGCTRL_CM4TPIUENABLE_EN     = 1,     /*!< EN : Enable the TPIU.                                                     */
} MCUCTRL_DBGCTRL_CM4TPIUENABLE_Enum;

/* ======================================================  OTAPOINTER  ======================================================= */
/* ======================================================  APBDMACTRL  ======================================================= */
/* =========================================  MCUCTRL APBDMACTRL DECODEABORT [1..1]  ========================================= */
typedef enum {                                  /*!< MCUCTRL_APBDMACTRL_DECODEABORT                                            */
  MCUCTRL_APBDMACTRL_DECODEABORT_DISABLE = 0,   /*!< DISABLE : Bus operations to powered down peripherals are quietly
                                                     discarded                                                                 */
  MCUCTRL_APBDMACTRL_DECODEABORT_ENABLE = 1,    /*!< ENABLE : Bus operations to powered down peripherals result in
                                                     a bus fault.                                                              */
} MCUCTRL_APBDMACTRL_DECODEABORT_Enum;

/* ==========================================  MCUCTRL APBDMACTRL DMAENABLE [0..0]  ========================================== */
typedef enum {                                  /*!< MCUCTRL_APBDMACTRL_DMAENABLE                                              */
  MCUCTRL_APBDMACTRL_DMAENABLE_DISABLE = 0,     /*!< DISABLE : DMA operations disabled                                         */
  MCUCTRL_APBDMACTRL_DMAENABLE_ENABLE  = 1,     /*!< ENABLE : DMA operations enabled                                           */
} MCUCTRL_APBDMACTRL_DMAENABLE_Enum;

/* ======================================================  KEXTCLKSEL  ======================================================= */
/* =========================================  MCUCTRL KEXTCLKSEL KEXTCLKSEL [0..31]  ========================================= */
typedef enum {                                  /*!< MCUCTRL_KEXTCLKSEL_KEXTCLKSEL                                             */
  MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Key    = 83,    /*!< Key : Key value to unlock the register.                                   */
} MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Enum;

/* =======================================================  SIMOBUCK0  ======================================================= */
/* =======================================================  SIMOBUCK1  ======================================================= */
/* =======================================================  SIMOBUCK2  ======================================================= */
/* =======================================================  SIMOBUCK3  ======================================================= */
/* =======================================================  SIMOBUCK6  ======================================================= */
/* =======================================================  SIMOBUCK7  ======================================================= */
/* =======================================================  SIMOBUCK8  ======================================================= */
/* =======================================================  SIMOBUCK9  ======================================================= */
/* ======================================================  SIMOBUCK12  ======================================================= */
/* ======================================================  SIMOBUCK13  ======================================================= */
/* ======================================================  SIMOBUCK15  ======================================================= */
/* ========================================================  PWRSW0  ========================================================= */
/* ======================================  MCUCTRL PWRSW0 PWRSWVDDRCPUSTATSEL [30..30]  ====================================== */
typedef enum {                                  /*!< MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL                                        */
  MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL_VDDC = 1,  /*!< VDDC : Select VDDC rail                                                   */
  MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL_VDDFLP = 0,/*!< VDDFLP : Select VDDFLP rail                                               */
} MCUCTRL_PWRSW0_PWRSWVDDRCPUSTATSEL_Enum;

/* =======================================  MCUCTRL PWRSW0 PWRSWVDDMLSTATSEL [25..25]  ======================================= */
typedef enum {                                  /*!< MCUCTRL_PWRSW0_PWRSWVDDMLSTATSEL                                          */
  MCUCTRL_PWRSW0_PWRSWVDDMLSTATSEL_VDDC = 0,    /*!< VDDC : Select VDDC rail                                                   */
  MCUCTRL_PWRSW0_PWRSWVDDMLSTATSEL_VDDF = 1,    /*!< VDDF : Select VDDF rail                                                   */
} MCUCTRL_PWRSW0_PWRSWVDDMLSTATSEL_Enum;

/* =====================================  MCUCTRL PWRSW0 PWRSWVDDMDSP1STATSEL [22..22]  ====================================== */
typedef enum {                                  /*!< MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL                                       */
  MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL_VDDC = 0, /*!< VDDC : Select VDDC rail                                                   */
  MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL_VDDF = 1, /*!< VDDF : Select VDDF rail                                                   */
} MCUCTRL_PWRSW0_PWRSWVDDMDSP1STATSEL_Enum;

/* =====================================  MCUCTRL PWRSW0 PWRSWVDDMDSP0STATSEL [19..19]  ====================================== */
typedef enum {                                  /*!< MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL                                       */
  MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL_VDDC = 0, /*!< VDDC : Select VDDC rail                                                   */
  MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL_VDDF = 1, /*!< VDDF : Select VDDF rail                                                   */
} MCUCTRL_PWRSW0_PWRSWVDDMDSP0STATSEL_Enum;

/* ======================================  MCUCTRL PWRSW0 PWRSWVDDMCPUSTATSEL [16..16]  ====================================== */
typedef enum {                                  /*!< MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL                                        */
  MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL_VDDC = 0,  /*!< VDDC : Select VDDC rail                                                   */
  MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL_VDDF = 1,  /*!< VDDF : Select VDDF rail                                                   */
} MCUCTRL_PWRSW0_PWRSWVDDMCPUSTATSEL_Enum;

/* ========================================================  PWRSW1  ========================================================= */
/* =======================================  MCUCTRL PWRSW1 PWRSWVDDRMSTATSEL [16..16]  ======================================= */
typedef enum {                                  /*!< MCUCTRL_PWRSW1_PWRSWVDDRMSTATSEL                                          */
  MCUCTRL_PWRSW1_PWRSWVDDRMSTATSEL_VDDC = 1,    /*!< VDDC : Select VDDC rail                                                   */
  MCUCTRL_PWRSW1_PWRSWVDDRMSTATSEL_VDDFLP = 0,  /*!< VDDFLP : Select VDDFLP rail                                               */
} MCUCTRL_PWRSW1_PWRSWVDDRMSTATSEL_Enum;

/* =======================================  MCUCTRL PWRSW1 PWRSWVDDRLSTATSEL [12..12]  ======================================= */
typedef enum {                                  /*!< MCUCTRL_PWRSW1_PWRSWVDDRLSTATSEL                                          */
  MCUCTRL_PWRSW1_PWRSWVDDRLSTATSEL_VDDC = 1,    /*!< VDDC : Select VDDC rail                                                   */
  MCUCTRL_PWRSW1_PWRSWVDDRLSTATSEL_VDDFLP = 0,  /*!< VDDFLP : Select VDDFLP rail                                               */
} MCUCTRL_PWRSW1_PWRSWVDDRLSTATSEL_Enum;

/* ======================================  MCUCTRL PWRSW1 PWRSWVDDRDSP1STATSEL [8..8]  ======================================= */
typedef enum {                                  /*!< MCUCTRL_PWRSW1_PWRSWVDDRDSP1STATSEL                                       */
  MCUCTRL_PWRSW1_PWRSWVDDRDSP1STATSEL_VDDC = 1, /*!< VDDC : Select VDDC rail                                                   */
  MCUCTRL_PWRSW1_PWRSWVDDRDSP1STATSEL_VDDFLP = 0,/*!< VDDFLP : Select VDDFLP rail                                              */
} MCUCTRL_PWRSW1_PWRSWVDDRDSP1STATSEL_Enum;

/* ======================================  MCUCTRL PWRSW1 PWRSWVDDRDSP0STATSEL [3..3]  ======================================= */
typedef enum {                                  /*!< MCUCTRL_PWRSW1_PWRSWVDDRDSP0STATSEL                                       */
  MCUCTRL_PWRSW1_PWRSWVDDRDSP0STATSEL_VDDC = 1, /*!< VDDC : Select VDDC rail                                                   */
  MCUCTRL_PWRSW1_PWRSWVDDRDSP0STATSEL_VDDFLP = 0,/*!< VDDFLP : Select VDDFLP rail                                              */
} MCUCTRL_PWRSW1_PWRSWVDDRDSP0STATSEL_Enum;

/* ======================================================  USBRSTCTRL  ======================================================= */
/* ======================================================  FLASHWPROT0  ====================================================== */
/* ======================================================  FLASHWPROT1  ====================================================== */
/* ======================================================  FLASHWPROT2  ====================================================== */
/* ======================================================  FLASHWPROT3  ====================================================== */
/* ======================================================  FLASHRPROT0  ====================================================== */
/* ======================================================  FLASHRPROT1  ====================================================== */
/* ======================================================  FLASHRPROT2  ====================================================== */
/* ======================================================  FLASHRPROT3  ====================================================== */
/* =====================================================  DMASRAMWPROT0  ===================================================== */
/* =====================================================  DMASRAMWPROT1  ===================================================== */
/* =====================================================  DMASRAMRPROT0  ===================================================== */
/* =====================================================  DMASRAMRPROT1  ===================================================== */
/* ======================================================  USBPHYRESET  ====================================================== */
/* =====================================================  AUDADCPWRCTRL  ===================================================== */
/* ====================================  MCUCTRL AUDADCPWRCTRL VDDAUDADCRESETN [10..10]  ===================================== */
typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN                                     */
  MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN_ASSERT = 0,/*!< ASSERT : Resetn is asserted                                            */
  MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN_DEASSERT = 1,/*!< DEASSERT : Resetn is de-asserted                                     */
} MCUCTRL_AUDADCPWRCTRL_VDDAUDADCRESETN_Enum;

/* ===================================  MCUCTRL AUDADCPWRCTRL VDDAUDADCDIGISOLATE [9..9]  ==================================== */
typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE                                 */
  MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE_DIS = 0,/*!< DIS : No Isolation                                                    */
  MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE_EN = 1,/*!< EN : Isolate                                                           */
} MCUCTRL_AUDADCPWRCTRL_VDDAUDADCDIGISOLATE_Enum;

/* ===================================  MCUCTRL AUDADCPWRCTRL VDDAUDADCSARISOLATE [8..8]  ==================================== */
typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE                                 */
  MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE_DIS = 0,/*!< DIS : No Isolation                                                    */
  MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE_EN = 1,/*!< EN : Isolate                                                           */
} MCUCTRL_AUDADCPWRCTRL_VDDAUDADCSARISOLATE_Enum;

/* ======================================  MCUCTRL AUDADCPWRCTRL AUDREFKEEPPEN [5..5]  ======================================= */
typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN                                       */
  MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN_DIS = 0,  /*!< DIS : Reference Buffer Keeper Power Switch disable.                       */
  MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN_EN = 1,   /*!< EN : Reference Buffer Keeper Power Switch enable.                         */
} MCUCTRL_AUDADCPWRCTRL_AUDREFKEEPPEN_Enum;

/* =======================================  MCUCTRL AUDADCPWRCTRL AUDREFBUFPEN [4..4]  ======================================= */
typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN                                        */
  MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN_DIS = 0,   /*!< DIS : Reference Buffer Power Switch disable.                              */
  MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN_EN = 1,    /*!< EN : Reference Buffer Power Switch enable.                                */
} MCUCTRL_AUDADCPWRCTRL_AUDREFBUFPEN_Enum;

/* ========================================  MCUCTRL AUDADCPWRCTRL AUDBGTPEN [3..3]  ========================================= */
typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN                                           */
  MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN_DIS  = 0,     /*!< DIS : Bandgap and temperature sensor disable.                             */
  MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN_EN   = 1,     /*!< EN : Bandgap and temperature sensor enable.                               */
} MCUCTRL_AUDADCPWRCTRL_AUDBGTPEN_Enum;

/* =======================================  MCUCTRL AUDADCPWRCTRL AUDADCBPSEN [2..2]  ======================================== */
typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN                                         */
  MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN_DIS = 0,    /*!< DIS : AUDADC power switch software power disable.                         */
  MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN_EN = 1,     /*!< EN : AUDADC power switch software power enable.                           */
} MCUCTRL_AUDADCPWRCTRL_AUDADCBPSEN_Enum;

/* =======================================  MCUCTRL AUDADCPWRCTRL AUDADCAPSEN [1..1]  ======================================== */
typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN                                         */
  MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN_DIS = 0,    /*!< DIS : AUDADC power switch software power disable.                         */
  MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN_EN = 1,     /*!< EN : AUDADC power switch software power enable.                           */
} MCUCTRL_AUDADCPWRCTRL_AUDADCAPSEN_Enum;

/* =====================================  MCUCTRL AUDADCPWRCTRL AUDADCPWRCTRLSWE [0..0]  ===================================== */
typedef enum {                                  /*!< MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE                                    */
  MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE_OVERRIDE_DIS = 0,/*!< OVERRIDE_DIS : Audio ADC temperature sensor and bandgap Software
                                                     Override Disable.                                                         */
  MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE_OVERRIDE_EN = 1,/*!< OVERRIDE_EN : Audio ADC temperature sensor and bandgap Software
                                                     Override Enable.                                                          */
} MCUCTRL_AUDADCPWRCTRL_AUDADCPWRCTRLSWE_Enum;

/* ========================================================  AUDIO1  ========================================================= */
/* =====================================================  PGAADCIFCTRL  ====================================================== */
/* =======================================================  PGACTRL1  ======================================================== */
/* =======================================================  PGACTRL2  ======================================================== */
/* =====================================================  AUDADCPWRDLY  ====================================================== */
/* =======================================================  SDIOCTRL  ======================================================== */
/* ========================================================  PDMCTRL  ======================================================== */


/* =========================================================================================================================== */
/* ================                                           MSPI0                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
/* ===============================================  MSPI0 CTRL PIODEV [4..4]  ================================================ */
typedef enum {                                  /*!< MSPI0_CTRL_PIODEV                                                         */
  MSPI0_CTRL_PIODEV_DEVICE0            = 0,     /*!< DEVICE0 : Use DEVICE0 Configuration                                       */
  MSPI0_CTRL_PIODEV_DEVICE1            = 1,     /*!< DEVICE1 : Use DEVICE1 CONFIGURATION                                       */
} MSPI0_CTRL_PIODEV_Enum;

/* =========================================================  CTRL1  ========================================================= */
/* ==============================================  MSPI0 CTRL1 PIOMIXED [0..3]  ============================================== */
typedef enum {                                  /*!< MSPI0_CTRL1_PIOMIXED                                                      */
  MSPI0_CTRL1_PIOMIXED_NORMAL          = 0,     /*!< NORMAL : Transfers all proceed using the settings in DEVCFG
                                                     register (everything in the same data rate)                               */
  MSPI0_CTRL1_PIOMIXED_D2              = 1,     /*!< D2 : Data operations proceed in dual data rate                            */
  MSPI0_CTRL1_PIOMIXED_AD2             = 3,     /*!< AD2 : Address and Data operations proceed in dual data rate               */
  MSPI0_CTRL1_PIOMIXED_D4              = 5,     /*!< D4 : Data operations proceed in quad data rate                            */
  MSPI0_CTRL1_PIOMIXED_AD4             = 7,     /*!< AD4 : Address and Data operations proceed in quad data rate               */
  MSPI0_CTRL1_PIOMIXED_D8              = 9,     /*!< D8 : Data operations proceed in octal data rate                           */
  MSPI0_CTRL1_PIOMIXED_AD8             = 11,    /*!< AD8 : Address and Data operations proceed in octal data rate              */
} MSPI0_CTRL1_PIOMIXED_Enum;

/* =========================================================  ADDR  ========================================================== */
/* =========================================================  INSTR  ========================================================= */
/* ========================================================  TXFIFO  ========================================================= */
/* ========================================================  RXFIFO  ========================================================= */
/* =======================================================  TXENTRIES  ======================================================= */
/* =======================================================  RXENTRIES  ======================================================= */
/* =======================================================  THRESHOLD  ======================================================= */
/* ========================================================  MSPICFG  ======================================================== */
/* ==============================================  MSPI0 MSPICFG IOMSEL [4..7]  ============================================== */
typedef enum {                                  /*!< MSPI0_MSPICFG_IOMSEL                                                      */
  MSPI0_MSPICFG_IOMSEL_IOM0            = 0,     /*!< IOM0 : ERROR: desc VALUE MISSING                                          */
  MSPI0_MSPICFG_IOMSEL_IOM1            = 1,     /*!< IOM1 : ERROR: desc VALUE MISSING                                          */
  MSPI0_MSPICFG_IOMSEL_IOM2            = 2,     /*!< IOM2 : ERROR: desc VALUE MISSING                                          */
  MSPI0_MSPICFG_IOMSEL_IOM3            = 3,     /*!< IOM3 : ERROR: desc VALUE MISSING                                          */
  MSPI0_MSPICFG_IOMSEL_IOM4            = 4,     /*!< IOM4 : ERROR: desc VALUE MISSING                                          */
  MSPI0_MSPICFG_IOMSEL_IOM5            = 5,     /*!< IOM5 : ERROR: desc VALUE MISSING                                          */
  MSPI0_MSPICFG_IOMSEL_IOM6            = 6,     /*!< IOM6 : ERROR: desc VALUE MISSING                                          */
  MSPI0_MSPICFG_IOMSEL_IOM7            = 7,     /*!< IOM7 : ERROR: desc VALUE MISSING                                          */
  MSPI0_MSPICFG_IOMSEL_MSPI0           = 8,     /*!< MSPI0 : ERROR: desc VALUE MISSING                                         */
  MSPI0_MSPICFG_IOMSEL_MSPI1           = 9,     /*!< MSPI1 : ERROR: desc VALUE MISSING                                         */
  MSPI0_MSPICFG_IOMSEL_MSPI2           = 10,    /*!< MSPI2 : ERROR: desc VALUE MISSING                                         */
} MSPI0_MSPICFG_IOMSEL_Enum;

/* ==============================================  MSPI0 MSPICFG APBCLK [0..0]  ============================================== */
typedef enum {                                  /*!< MSPI0_MSPICFG_APBCLK                                                      */
  MSPI0_MSPICFG_APBCLK_DIS             = 0,     /*!< DIS : Disable continuous clock.                                           */
  MSPI0_MSPICFG_APBCLK_EN              = 1,     /*!< EN : Enable continuous clock.                                             */
} MSPI0_MSPICFG_APBCLK_Enum;

/* =======================================================  PADOUTEN  ======================================================== */
/* =============================================  MSPI0 PADOUTEN OUTEN [0..19]  ============================================== */
typedef enum {                                  /*!< MSPI0_PADOUTEN_OUTEN                                                      */
  MSPI0_PADOUTEN_OUTEN_QUAD0           = 271,   /*!< QUAD0 : Quad0 (4 data + 1 clock)                                          */
  MSPI0_PADOUTEN_OUTEN_QUAD1           = 496,   /*!< QUAD1 : Quad1 (4 data + 1 clock)                                          */
  MSPI0_PADOUTEN_OUTEN_OCTAL           = 1023,  /*!< OCTAL : Octal (8 data + 1 clock)                                          */
  MSPI0_PADOUTEN_OUTEN_SERIAL0         = 259,   /*!< SERIAL0 : Serial (2 data + 1 clock)                                       */
  MSPI0_PADOUTEN_OUTEN_SERIAL1         = 304,   /*!< SERIAL1 : Serial (2 data + 1 clock)                                       */
  MSPI0_PADOUTEN_OUTEN_HEX             = 524287,/*!< HEX : Octal (16 data + 1 clock + 2 bytemask)                              */
} MSPI0_PADOUTEN_OUTEN_Enum;

/* =======================================================  PADOVEREN  ======================================================= */
/* ========================================================  PADOVER  ======================================================== */
/* ========================================================  DEV0AXI  ======================================================== */
/* ============================================  MSPI0 DEV0AXI READONLY0 [4..4]  ============================================= */
typedef enum {                                  /*!< MSPI0_DEV0AXI_READONLY0                                                   */
  MSPI0_DEV0AXI_READONLY0_READONLY     = 1,     /*!< READONLY : Indicates AXI aperture only supports read operations           */
  MSPI0_DEV0AXI_READONLY0_READWRITE    = 0,     /*!< READWRITE : Indicates AXI aperture supports read and write operations     */
} MSPI0_DEV0AXI_READONLY0_Enum;

/* ==============================================  MSPI0 DEV0AXI SIZE0 [0..3]  =============================================== */
typedef enum {                                  /*!< MSPI0_DEV0AXI_SIZE0                                                       */
  MSPI0_DEV0AXI_SIZE0_SIZE64K          = 0,     /*!< SIZE64K : 64KB Aperture                                                   */
  MSPI0_DEV0AXI_SIZE0_SIZE128K         = 1,     /*!< SIZE128K : 128KB Aperture                                                 */
  MSPI0_DEV0AXI_SIZE0_SIZE256K         = 2,     /*!< SIZE256K : 256KB Aperture                                                 */
  MSPI0_DEV0AXI_SIZE0_SIZE512K         = 3,     /*!< SIZE512K : 512KB Aperture                                                 */
  MSPI0_DEV0AXI_SIZE0_SIZE1M           = 4,     /*!< SIZE1M : 1MB Aperture                                                     */
  MSPI0_DEV0AXI_SIZE0_SIZE2M           = 5,     /*!< SIZE2M : 2MB Aperture                                                     */
  MSPI0_DEV0AXI_SIZE0_SIZE4M           = 6,     /*!< SIZE4M : 4MB Aperture                                                     */
  MSPI0_DEV0AXI_SIZE0_SIZE8M           = 7,     /*!< SIZE8M : 8MB Aperture                                                     */
  MSPI0_DEV0AXI_SIZE0_SIZE16M          = 8,     /*!< SIZE16M : 16MB Aperture                                                   */
  MSPI0_DEV0AXI_SIZE0_SIZE32M          = 9,     /*!< SIZE32M : 32MB Aperture                                                   */
  MSPI0_DEV0AXI_SIZE0_SIZE64M          = 10,    /*!< SIZE64M : 64MB Aperture                                                   */
} MSPI0_DEV0AXI_SIZE0_Enum;

/* ========================================================  DEV0CFG  ======================================================== */
/* =============================================  MSPI0 DEV0CFG TXNEG0 [24..24]  ============================================= */
typedef enum {                                  /*!< MSPI0_DEV0CFG_TXNEG0                                                      */
  MSPI0_DEV0CFG_TXNEG0_NORMAL          = 0,     /*!< NORMAL : TX launched from posedge internal clock                          */
  MSPI0_DEV0CFG_TXNEG0_NEGEDGE         = 1,     /*!< NEGEDGE : TX data launched from negedge of internal clock                 */
} MSPI0_DEV0CFG_TXNEG0_Enum;

/* =============================================  MSPI0 DEV0CFG RXNEG0 [23..23]  ============================================= */
typedef enum {                                  /*!< MSPI0_DEV0CFG_RXNEG0                                                      */
  MSPI0_DEV0CFG_RXNEG0_NORMAL          = 0,     /*!< NORMAL : RX data sampled on posedge of internal clock                     */
  MSPI0_DEV0CFG_RXNEG0_NEGEDGE         = 1,     /*!< NEGEDGE : RX data sampled on negedge of internal clock                    */
} MSPI0_DEV0CFG_RXNEG0_Enum;

/* =============================================  MSPI0 DEV0CFG RXCAP0 [22..22]  ============================================= */
typedef enum {                                  /*!< MSPI0_DEV0CFG_RXCAP0                                                      */
  MSPI0_DEV0CFG_RXCAP0_NORMAL          = 0,     /*!< NORMAL : RX Capture phase aligns with CPHA setting                        */
  MSPI0_DEV0CFG_RXCAP0_DELAY           = 1,     /*!< DELAY : RX Capture phase is delayed from CPHA setting by one
                                                     clock edge                                                                */
} MSPI0_DEV0CFG_RXCAP0_Enum;

/* ============================================  MSPI0 DEV0CFG CLKDIV0 [16..21]  ============================================= */
typedef enum {                                  /*!< MSPI0_DEV0CFG_CLKDIV0                                                     */
  MSPI0_DEV0CFG_CLKDIV0_CLK96          = 1,     /*!< CLK96 : 96 MHz MSPI clock                                                 */
  MSPI0_DEV0CFG_CLKDIV0_CLK48          = 2,     /*!< CLK48 : 48 MHz MSPI clock                                                 */
  MSPI0_DEV0CFG_CLKDIV0_CLK32          = 3,     /*!< CLK32 : 32 MHz MSPI clock                                                 */
  MSPI0_DEV0CFG_CLKDIV0_CLK24          = 4,     /*!< CLK24 : 24 MHz MSPI clock                                                 */
  MSPI0_DEV0CFG_CLKDIV0_CLK16          = 6,     /*!< CLK16 : 16 MHz MSPI clock                                                 */
  MSPI0_DEV0CFG_CLKDIV0_CLK12          = 8,     /*!< CLK12 : 12 MHz MSPI clock                                                 */
  MSPI0_DEV0CFG_CLKDIV0_CLK8           = 12,    /*!< CLK8 : 8 MHz MSPI clock                                                   */
  MSPI0_DEV0CFG_CLKDIV0_CLK6           = 16,    /*!< CLK6 : 6 MHz MSPI clock                                                   */
  MSPI0_DEV0CFG_CLKDIV0_CLK4           = 24,    /*!< CLK4 : 4 MHz MSPI clock                                                   */
  MSPI0_DEV0CFG_CLKDIV0_CLK3           = 32,    /*!< CLK3 : 3 MHz MSPI clock                                                   */
} MSPI0_DEV0CFG_CLKDIV0_Enum;

/* =============================================  MSPI0 DEV0CFG CPOL0 [15..15]  ============================================== */
typedef enum {                                  /*!< MSPI0_DEV0CFG_CPOL0                                                       */
  MSPI0_DEV0CFG_CPOL0_LOW              = 0,     /*!< LOW : Clock inactive state is low.                                        */
  MSPI0_DEV0CFG_CPOL0_HIGH             = 1,     /*!< HIGH : Clock inactive state is high.                                      */
} MSPI0_DEV0CFG_CPOL0_Enum;

/* =============================================  MSPI0 DEV0CFG CPHA0 [14..14]  ============================================== */
typedef enum {                                  /*!< MSPI0_DEV0CFG_CPHA0                                                       */
  MSPI0_DEV0CFG_CPHA0_MIDDLE           = 0,     /*!< MIDDLE : Clock toggles in middle of data bit.                             */
  MSPI0_DEV0CFG_CPHA0_START            = 1,     /*!< START : Clock toggles at start of data bit.                               */
} MSPI0_DEV0CFG_CPHA0_Enum;

/* ==============================================  MSPI0 DEV0CFG ISIZE0 [7..7]  ============================================== */
typedef enum {                                  /*!< MSPI0_DEV0CFG_ISIZE0                                                      */
  MSPI0_DEV0CFG_ISIZE0_I8              = 0,     /*!< I8 : Instruction is 1 byte                                                */
  MSPI0_DEV0CFG_ISIZE0_I16             = 1,     /*!< I16 : Instruction is 2 bytes                                              */
} MSPI0_DEV0CFG_ISIZE0_Enum;

/* ==============================================  MSPI0 DEV0CFG ASIZE0 [5..6]  ============================================== */
typedef enum {                                  /*!< MSPI0_DEV0CFG_ASIZE0                                                      */
  MSPI0_DEV0CFG_ASIZE0_A1              = 0,     /*!< A1 : Send one address byte                                                */
  MSPI0_DEV0CFG_ASIZE0_A2              = 1,     /*!< A2 : Send two address bytes                                               */
  MSPI0_DEV0CFG_ASIZE0_A3              = 2,     /*!< A3 : Send three address bytes                                             */
  MSPI0_DEV0CFG_ASIZE0_A4              = 3,     /*!< A4 : Send four address bytes                                              */
} MSPI0_DEV0CFG_ASIZE0_Enum;

/* =============================================  MSPI0 DEV0CFG DEVCFG0 [0..4]  ============================================== */
typedef enum {                                  /*!< MSPI0_DEV0CFG_DEVCFG0                                                     */
  MSPI0_DEV0CFG_DEVCFG0_SERIAL0        = 1,     /*!< SERIAL0 : Single bit SPI flash on chip select 0                           */
  MSPI0_DEV0CFG_DEVCFG0_SERIAL1        = 2,     /*!< SERIAL1 : Single bit SPI flash on chip select 1                           */
  MSPI0_DEV0CFG_DEVCFG0_DUAL0          = 5,     /*!< DUAL0 : Dual SPI flash on chip select 0                                   */
  MSPI0_DEV0CFG_DEVCFG0_DUAL1          = 6,     /*!< DUAL1 : Dual bit SPI flash on chip select 1                               */
  MSPI0_DEV0CFG_DEVCFG0_QUAD0          = 9,     /*!< QUAD0 : Quad SPI flash on chip select 0                                   */
  MSPI0_DEV0CFG_DEVCFG0_QUAD1          = 10,    /*!< QUAD1 : Quad SPI flash on chip select 1                                   */
  MSPI0_DEV0CFG_DEVCFG0_OCTAL0         = 13,    /*!< OCTAL0 : Octal SPI flash on chip select 0                                 */
  MSPI0_DEV0CFG_DEVCFG0_OCTAL1         = 14,    /*!< OCTAL1 : Octal SPI flash on chip select 1                                 */
  MSPI0_DEV0CFG_DEVCFG0_QUADPAIRED     = 15,    /*!< QUADPAIRED : Dual Quad SPI flash on chip selects 0/1.                     */
  MSPI0_DEV0CFG_DEVCFG0_QUADPAIRED_SERIAL = 3,  /*!< QUADPAIRED_SERIAL : Dual Quad SPI flash on chip selects 0/1,
                                                     but transmit in serial mode for initialization operations                 */
  MSPI0_DEV0CFG_DEVCFG0_HEX0           = 17,    /*!< HEX0 : Hex SPI flash on chip selects 0.                                   */
  MSPI0_DEV0CFG_DEVCFG0_HEX1           = 18,    /*!< HEX1 : Hex SPI flash on chip selects 1.                                   */
} MSPI0_DEV0CFG_DEVCFG0_Enum;

/* ========================================================  DEV0DDR  ======================================================== */
/* =======================================================  DEV0CFG1  ======================================================== */
/* ========================================================  DEV0XIP  ======================================================== */
/* ======================================  MSPI0 DEV0XIP XIPHALFWORDREVERSE0 [26..26]  ======================================= */
typedef enum {                                  /*!< MSPI0_DEV0XIP_XIPHALFWORDREVERSE0                                         */
  MSPI0_DEV0XIP_XIPHALFWORDREVERSE0_DIS = 0,    /*!< DIS : No change                                                           */
  MSPI0_DEV0XIP_XIPHALFWORDREVERSE0_EN = 1,     /*!< EN : Indicates XIP/AUTO DMA data transfers are in Reverse bytes           */
} MSPI0_DEV0XIP_XIPHALFWORDREVERSE0_Enum;

/* ============================================  MSPI0 DEV0XIP XIPMIXED0 [8..11]  ============================================ */
typedef enum {                                  /*!< MSPI0_DEV0XIP_XIPMIXED0                                                   */
  MSPI0_DEV0XIP_XIPMIXED0_NORMAL       = 0,     /*!< NORMAL : Transfers all proceed using the settings in DEVCFG
                                                     register (everything in the same data rate)                               */
  MSPI0_DEV0XIP_XIPMIXED0_D2           = 1,     /*!< D2 : Data operations proceed in dual data rate                            */
  MSPI0_DEV0XIP_XIPMIXED0_AD2          = 3,     /*!< AD2 : Address and Data operations proceed in dual data rate               */
  MSPI0_DEV0XIP_XIPMIXED0_D4           = 5,     /*!< D4 : Data operations proceed in quad data rate                            */
  MSPI0_DEV0XIP_XIPMIXED0_AD4          = 7,     /*!< AD4 : Address and Data operations proceed in quad data rate               */
  MSPI0_DEV0XIP_XIPMIXED0_D8           = 9,     /*!< D8 : Data operations proceed in octal data rate                           */
  MSPI0_DEV0XIP_XIPMIXED0_AD8          = 11,    /*!< AD8 : Address and Data operations proceed in octal data rate              */
} MSPI0_DEV0XIP_XIPMIXED0_Enum;

/* =============================================  MSPI0 DEV0XIP XIPACK0 [2..3]  ============================================== */
typedef enum {                                  /*!< MSPI0_DEV0XIP_XIPACK0                                                     */
  MSPI0_DEV0XIP_XIPACK0_NOACK          = 0,     /*!< NOACK : No acknowledege sent. Data IOs are tristated the first
                                                     turnaround cycle                                                          */
  MSPI0_DEV0XIP_XIPACK0_ACK            = 2,     /*!< ACK : Positive acknowledege sent. Data IOs are driven to 0 the
                                                     first turnaround cycle to acknowledge XIP mode                            */
  MSPI0_DEV0XIP_XIPACK0_TERMINATE      = 3,     /*!< TERMINATE : Negative acknowledege sent. Data IOs are driven
                                                     to 1 the first turnaround cycle to terminate XIP mode.
                                                     XIPSENDI should be reenabled for the next transfer                        */
} MSPI0_DEV0XIP_XIPACK0_Enum;

/* =======================================================  DEV0INSTR  ======================================================= */
/* =====================================================  DEV0BOUNDARY  ====================================================== */
/* =========================================  MSPI0 DEV0BOUNDARY DMABOUND0 [12..15]  ========================================= */
typedef enum {                                  /*!< MSPI0_DEV0BOUNDARY_DMABOUND0                                              */
  MSPI0_DEV0BOUNDARY_DMABOUND0_NONE    = 0,     /*!< NONE : Disable DMA address boundary breaks                                */
  MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK32 = 1,     /*!< BREAK32 : Break at 32 byte boundary (0x20 increments)                     */
  MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK64 = 2,     /*!< BREAK64 : Break at 64 byte boundary (0x40 increments)                     */
  MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK128 = 3,    /*!< BREAK128 : Break at 128 byte boundary (0x80 increments)                   */
  MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK256 = 4,    /*!< BREAK256 : Break at 256 byte boundary (0x100 increments)                  */
  MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK512 = 5,    /*!< BREAK512 : Break at 512 byte boundary (0x200 increments)                  */
  MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK1K = 6,     /*!< BREAK1K : Break at 1KB boundary (0x400 increments)                        */
  MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK2K = 7,     /*!< BREAK2K : Break at 2KB boundary (0x800 increments)                        */
  MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK4K = 8,     /*!< BREAK4K : Break at 4KB boundary (0x1000 increments)                       */
  MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK8K = 9,     /*!< BREAK8K : Break at 8KB boundary (0x2000 increments)                       */
  MSPI0_DEV0BOUNDARY_DMABOUND0_BREAK16K = 10,   /*!< BREAK16K : Break at 16KB boundary (0x4000 increments)                     */
} MSPI0_DEV0BOUNDARY_DMABOUND0_Enum;

/* ====================================================  DEV0SCRAMBLING  ===================================================== */
/* ======================================================  DEV0XIPMISC  ====================================================== */
/* ==========================================  MSPI0 DEV0XIPMISC APNDODD0 [21..21]  ========================================== */
typedef enum {                                  /*!< MSPI0_DEV0XIPMISC_APNDODD0                                                */
  MSPI0_DEV0XIPMISC_APNDODD0_DIS       = 0,     /*!< DIS : No appending byte                                                   */
  MSPI0_DEV0XIPMISC_APNDODD0_EN        = 1,     /*!< EN : Append one dummy byte                                                */
} MSPI0_DEV0XIPMISC_APNDODD0_Enum;

/* ========================================  MSPI0 DEV0XIPMISC XIPBOUNDARY0 [15..15]  ======================================== */
typedef enum {                                  /*!< MSPI0_DEV0XIPMISC_XIPBOUNDARY0                                            */
  MSPI0_DEV0XIPMISC_XIPBOUNDARY0_DIS   = 0,     /*!< DIS : ERROR: desc VALUE MISSING                                           */
  MSPI0_DEV0XIPMISC_XIPBOUNDARY0_EN    = 1,     /*!< EN : ERROR: desc VALUE MISSING                                            */
} MSPI0_DEV0XIPMISC_XIPBOUNDARY0_Enum;

/* ===========================================  MSPI0 DEV0XIPMISC BEON0 [14..14]  ============================================ */
typedef enum {                                  /*!< MSPI0_DEV0XIPMISC_BEON0                                                   */
  MSPI0_DEV0XIPMISC_BEON0_DIS          = 0,     /*!< DIS : Byte enable is calculated on the fly                                */
  MSPI0_DEV0XIPMISC_BEON0_EN           = 1,     /*!< EN : Byte enable of all bytes are always on                               */
} MSPI0_DEV0XIPMISC_BEON0_Enum;

/* ==========================================  MSPI0 DEV0XIPMISC XIPODD0 [12..12]  =========================================== */
typedef enum {                                  /*!< MSPI0_DEV0XIPMISC_XIPODD0                                                 */
  MSPI0_DEV0XIPMISC_XIPODD0_DIS        = 0,     /*!< DIS : No conversion                                                       */
  MSPI0_DEV0XIPMISC_XIPODD0_EN         = 1,     /*!< EN : Enable the conversion                                                */
} MSPI0_DEV0XIPMISC_XIPODD0_Enum;

/* ========================================================  DMACFG  ========================================================= */
/* ==============================================  MSPI0 DMACFG DMAPRI [4..5]  =============================================== */
typedef enum {                                  /*!< MSPI0_DMACFG_DMAPRI                                                       */
  MSPI0_DMACFG_DMAPRI_LOW              = 0,     /*!< LOW : Low Priority (service as best effort)                               */
  MSPI0_DMACFG_DMAPRI_HIGH             = 1,     /*!< HIGH : High Priority (service immediately)                                */
  MSPI0_DMACFG_DMAPRI_AUTO             = 2,     /*!< AUTO : Auto Priority (priority raised once TX FIFO empties or
                                                     RX FIFO fills)                                                            */
} MSPI0_DMACFG_DMAPRI_Enum;

/* ==============================================  MSPI0 DMACFG DMADEV [3..3]  =============================================== */
typedef enum {                                  /*!< MSPI0_DMACFG_DMADEV                                                       */
  MSPI0_DMACFG_DMADEV_DEV0             = 0,     /*!< DEV0 : Select Device 0 for DMA                                            */
} MSPI0_DMACFG_DMADEV_Enum;

/* ==============================================  MSPI0 DMACFG DMADIR [2..2]  =============================================== */
typedef enum {                                  /*!< MSPI0_DMACFG_DMADIR                                                       */
  MSPI0_DMACFG_DMADIR_P2M              = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction                             */
  MSPI0_DMACFG_DMADIR_M2P              = 1,     /*!< M2P : Memory to Peripheral transaction                                    */
} MSPI0_DMACFG_DMADIR_Enum;

/* ===============================================  MSPI0 DMACFG DMAEN [0..1]  =============================================== */
typedef enum {                                  /*!< MSPI0_DMACFG_DMAEN                                                        */
  MSPI0_DMACFG_DMAEN_DIS               = 0,     /*!< DIS : Disable DMA Function                                                */
  MSPI0_DMACFG_DMAEN_EN                = 3,     /*!< EN : Enable HW controlled DMA Function to manage DMA to flash
                                                     devices. HW will automatically handle issuance of instruction/address
                                                     bytes based on settings in the FLASH register.                            */
} MSPI0_DMACFG_DMAEN_Enum;

/* ========================================================  DMASTAT  ======================================================== */
/* ======================================================  DMATARGADDR  ====================================================== */
/* ======================================================  DMADEVADDR  ======================================================= */
/* ======================================================  DMATOTCOUNT  ====================================================== */
/* =======================================================  DMABCOUNT  ======================================================= */
/* =======================================================  DMATHRESH  ======================================================= */
/* =========================================================  INTEN  ========================================================= */
/* ========================================================  INTSTAT  ======================================================== */
/* ========================================================  INTCLR  ========================================================= */
/* ========================================================  INTSET  ========================================================= */
/* =========================================================  CQCFG  ========================================================= */
/* ===============================================  MSPI0 CQCFG CQPRI [1..1]  ================================================ */
typedef enum {                                  /*!< MSPI0_CQCFG_CQPRI                                                         */
  MSPI0_CQCFG_CQPRI_LOW                = 0,     /*!< LOW : Low Priority (service as best effort)                               */
  MSPI0_CQCFG_CQPRI_HIGH               = 1,     /*!< HIGH : High Priority (service immediately)                                */
} MSPI0_CQCFG_CQPRI_Enum;

/* ================================================  MSPI0 CQCFG CQEN [0..0]  ================================================ */
typedef enum {                                  /*!< MSPI0_CQCFG_CQEN                                                          */
  MSPI0_CQCFG_CQEN_DIS                 = 0,     /*!< DIS : Disable CQ Function                                                 */
  MSPI0_CQCFG_CQEN_EN                  = 1,     /*!< EN : Enable CQ Function                                                   */
} MSPI0_CQCFG_CQEN_Enum;

/* ========================================================  CQADDR  ========================================================= */
/* ========================================================  CQSTAT  ========================================================= */
/* ========================================================  CQFLAGS  ======================================================== */
/* =============================================  MSPI0 CQFLAGS CQFLAGS [0..15]  ============================================= */
typedef enum {                                  /*!< MSPI0_CQFLAGS_CQFLAGS                                                     */
  MSPI0_CQFLAGS_CQFLAGS_STOP           = 32768, /*!< STOP : CQ Stop Flag. When set, CQ processing will complete.               */
  MSPI0_CQFLAGS_CQFLAGS_CQIDX          = 16384, /*!< CQIDX : CQ Index Pointers (CURIDX/ENDIDX) match.                          */
  MSPI0_CQFLAGS_CQFLAGS_BUF1XOREN      = 8192,  /*!< BUF1XOREN : Buffer 1 Ready Status (from selected IOM/MSPI).
                                                     This status is the result of XOR'ing the IOM1START with
                                                     the incoming status from the IOM. When high, MSPI can transfer
                                                     the buffer.                                                               */
  MSPI0_CQFLAGS_CQFLAGS_BUF0XOREN      = 4096,  /*!< BUF0XOREN : Buffer 0 Ready Status (from selected IOM/MSPI).
                                                     This status is the result of XOR'ing the IOM0START with
                                                     the incoming status from the IOM. When high, MSPI can transfer
                                                     the buffer.                                                               */
  MSPI0_CQFLAGS_CQFLAGS_DMACPL         = 2048,  /*!< DMACPL : DMA Complete Status (hardwired DMACPL bit in DMASTAT)            */
  MSPI0_CQFLAGS_CQFLAGS_CMDCPL         = 1024,  /*!< CMDCPL : PIO Operation completed (STATUS bit in CTRL register)            */
  MSPI0_CQFLAGS_CQFLAGS_IOM1READY      = 512,   /*!< IOM1READY : (BUF1XNOREN) IOM Buffer 1 Ready Status (from selected
                                                     IOM). This status is the result of XNOR'ing the IOM0START
                                                     with the incoming status from the IOM. When high, MSPI
                                                     can send to the buffer.                                                   */
  MSPI0_CQFLAGS_CQFLAGS_IOM0READY      = 256,   /*!< IOM0READY : (BUF0XNOREN) IOM Buffer 0 Ready Status (from selected
                                                     IOM). This status is the result of XNOR'ing the IOM0START
                                                     with the incoming status from the IOM. When high, MSPI
                                                     can send to the buffer.                                                   */
  MSPI0_CQFLAGS_CQFLAGS_SWFLAG7        = 128,   /*!< SWFLAG7 : Software flag 7. Can be used by software to start/pause
                                                     operations.                                                               */
  MSPI0_CQFLAGS_CQFLAGS_SWFLAG6        = 64,    /*!< SWFLAG6 : Software flag 6. Can be used by software to start/pause
                                                     operations.                                                               */
  MSPI0_CQFLAGS_CQFLAGS_SWFLAG5        = 32,    /*!< SWFLAG5 : Software flag 5. Can be used by software to start/pause
                                                     operations.                                                               */
  MSPI0_CQFLAGS_CQFLAGS_SWFLAG4        = 16,    /*!< SWFLAG4 : Software flag 4. Can be used by software to start/pause
                                                     operations.                                                               */
  MSPI0_CQFLAGS_CQFLAGS_SWFLAG3        = 8,     /*!< SWFLAG3 : Software flag 3. Can be used by software to start/pause
                                                     operations.                                                               */
  MSPI0_CQFLAGS_CQFLAGS_SWFLAG2        = 4,     /*!< SWFLAG2 : Software flag 2. Can be used by software to start/pause
                                                     operations.                                                               */
  MSPI0_CQFLAGS_CQFLAGS_SWFLAG1        = 2,     /*!< SWFLAG1 : Software flag 1. Can be used by software to start/pause
                                                     operations. Also, IOM Buffer 1 status. When linked to IOM,
                                                     indicates to IOM that buffer 1 is ready.                                  */
  MSPI0_CQFLAGS_CQFLAGS_SWFLAG0        = 1,     /*!< SWFLAG0 : Software flag 0. Can be used by software to start/pause
                                                     operations. Also, IOM Buffer 0 status. When linked to IOM,
                                                     indicates to IOM that buffer 0 is ready.                                  */
} MSPI0_CQFLAGS_CQFLAGS_Enum;

/* ======================================================  CQSETCLEAR  ======================================================= */
/* ========================================================  CQPAUSE  ======================================================== */
/* =============================================  MSPI0 CQPAUSE CQMASK [0..15]  ============================================== */
typedef enum {                                  /*!< MSPI0_CQPAUSE_CQMASK                                                      */
  MSPI0_CQPAUSE_CQMASK_STOP            = 32768, /*!< STOP : CQ Stop Flag. When set, CQ processing will complete.               */
  MSPI0_CQPAUSE_CQMASK_CQIDX           = 16384, /*!< CQIDX : CQ Index Pointers (CURIDX/ENDIDX) match.                          */
  MSPI0_CQPAUSE_CQMASK_BUF1XOREN       = 8192,  /*!< BUF1XOREN : Buffer 1 Ready Status (from selected IOM/MSPI).
                                                     This status is the result of XOR'ing the IOM1START with
                                                     the incoming status from the IOM. When high, MSPI can transfer
                                                     the buffer.                                                               */
  MSPI0_CQPAUSE_CQMASK_BUF0XOREN       = 4096,  /*!< BUF0XOREN : Buffer 0 Ready Status (from selected IOM/MSPI).
                                                     This status is the result of XOR'ing the IOM0START with
                                                     the incoming status from the IOM. When high, MSPI can transfer
                                                     the buffer.                                                               */
  MSPI0_CQPAUSE_CQMASK_DMACPL          = 2048,  /*!< DMACPL : DMA Complete Status (hardwired DMACPL bit in DMASTAT)            */
  MSPI0_CQPAUSE_CQMASK_CMDCPL          = 1024,  /*!< CMDCPL : PIO Operation completed (STATUS bit in CTRL register)            */
  MSPI0_CQPAUSE_CQMASK_IOM1READY       = 512,   /*!< IOM1READY : (BUF1XNOREN) IOM Buffer 1 Ready Status (from selected
                                                     IOM). This status is the result of XNOR'ing the IOM0START
                                                     with the incoming status from the IOM. When high, MSPI
                                                     can send to the buffer.                                                   */
  MSPI0_CQPAUSE_CQMASK_IOM0READY       = 256,   /*!< IOM0READY : (BUF0XNOREN) IOM Buffer 0 Ready Status (from selected
                                                     IOM). This status is the result of XNOR'ing the IOM0START
                                                     with the incoming status from the IOM. When high, MSPI
                                                     can send to the buffer.                                                   */
  MSPI0_CQPAUSE_CQMASK_SWFLAG7         = 128,   /*!< SWFLAG7 : Software flag 7. Can be used by software to start/pause
                                                     operations.                                                               */
  MSPI0_CQPAUSE_CQMASK_SWFLAG6         = 64,    /*!< SWFLAG6 : Software flag 6. Can be used by software to start/pause
                                                     operations.                                                               */
  MSPI0_CQPAUSE_CQMASK_SWFLAG5         = 32,    /*!< SWFLAG5 : Software flag 5. Can be used by software to start/pause
                                                     operations.                                                               */
  MSPI0_CQPAUSE_CQMASK_SWFLAG4         = 16,    /*!< SWFLAG4 : Software flag 4. Can be used by software to start/pause
                                                     operations.                                                               */
  MSPI0_CQPAUSE_CQMASK_SWFLAG3         = 8,     /*!< SWFLAG3 : Software flag 3. Can be used by software to start/pause
                                                     operations.                                                               */
  MSPI0_CQPAUSE_CQMASK_SWFLAG2         = 4,     /*!< SWFLAG2 : Software flag 2. Can be used by software to start/pause
                                                     operations.                                                               */
  MSPI0_CQPAUSE_CQMASK_SWFLAG1         = 2,     /*!< SWFLAG1 : Software flag 1. Can be used by software to start/pause
                                                     operations. Also, IOM Buffer 1 status (same as SWFLAG1).
                                                     When linked to IOM, indicates to IOM that buffer 1 is ready.              */
  MSPI0_CQPAUSE_CQMASK_SWFLAG0         = 1,     /*!< SWFLAG0 : Software flag 0. Can be used by software to start/pause
                                                     operations. Also, IOM Buffer 0 status (same as SWFLAG0).
                                                     When linked to IOM, indicates to IOM that buffer 0 is ready.              */
} MSPI0_CQPAUSE_CQMASK_Enum;

/* =======================================================  CQCURIDX  ======================================================== */
/* =======================================================  CQENDIDX  ======================================================== */
/* ======================================================  STATXIPDMA  ======================================================= */
/* ============================================  MSPI0 STATXIPDMA FLD32 [0..31]  ============================================= */
typedef enum {                                  /*!< MSPI0_STATXIPDMA_FLD32                                                    */
  MSPI0_STATXIPDMA_FLD32_XIPDMAIDLE    = 2048,  /*!< XIPDMAIDLE : This bit indicates the idle status of XIPDMA.                */
} MSPI0_STATXIPDMA_FLD32_Enum;



/* =========================================================================================================================== */
/* ================                                           PDM0                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
/* ==================================================  PDM0 CTRL EN [6..6]  ================================================== */
typedef enum {                                  /*!< PDM0_CTRL_EN                                                              */
  PDM0_CTRL_EN_DIS                     = 0,     /*!< DIS : Disable PDM.                                                        */
  PDM0_CTRL_EN_EN                      = 1,     /*!< EN : Enable PDM.                                                          */
} PDM0_CTRL_EN_Enum;

/* ===============================================  PDM0 CTRL PCMPACK [5..5]  ================================================ */
typedef enum {                                  /*!< PDM0_CTRL_PCMPACK                                                         */
  PDM0_CTRL_PCMPACK_DIS                = 0,     /*!< DIS : Disable PCM packing.                                                */
  PDM0_CTRL_PCMPACK_EN                 = 1,     /*!< EN : Enable PCM packing.                                                  */
} PDM0_CTRL_PCMPACK_Enum;

/* =================================================  PDM0 CTRL RSTB [4..4]  ================================================= */
typedef enum {                                  /*!< PDM0_CTRL_RSTB                                                            */
  PDM0_CTRL_RSTB_RESET                 = 0,     /*!< RESET : Put the core in reset.                                            */
  PDM0_CTRL_RSTB_NORMAL                = 1,     /*!< NORMAL : Core not in reset.                                               */
} PDM0_CTRL_RSTB_Enum;

/* ================================================  PDM0 CTRL CLKEN [0..0]  ================================================= */
typedef enum {                                  /*!< PDM0_CTRL_CLKEN                                                           */
  PDM0_CTRL_CLKEN_DIS                  = 0,     /*!< DIS : Disable serial clock                                                */
  PDM0_CTRL_CLKEN_EN                   = 1,     /*!< EN : Enable serial clock                                                  */
} PDM0_CTRL_CLKEN_Enum;

/* =======================================================  CORECFG0  ======================================================== */
/* ==============================================  PDM0 CORECFG0 PGAR [26..30]  ============================================== */
typedef enum {                                  /*!< PDM0_CORECFG0_PGAR                                                        */
  PDM0_CORECFG0_PGAR_M12_0DB           = 0,     /*!< M12_0DB : Right channel PGA gain = -12.0 dB                               */
  PDM0_CORECFG0_PGAR_M10_5DB           = 1,     /*!< M10_5DB : Right channel PGA gain = -10.5 dB                               */
  PDM0_CORECFG0_PGAR_M9_0DB            = 2,     /*!< M9_0DB : Right channel PGA gain = -9.0 dB                                 */
  PDM0_CORECFG0_PGAR_M7_5DB            = 3,     /*!< M7_5DB : Right channel PGA gain = -7.5 dB                                 */
  PDM0_CORECFG0_PGAR_M6_0DB            = 4,     /*!< M6_0DB : Right channel PGA gain = -6.0 dB                                 */
  PDM0_CORECFG0_PGAR_M4_5DB            = 5,     /*!< M4_5DB : Right channel PGA gain = -4.5 dB                                 */
  PDM0_CORECFG0_PGAR_M3_0DB            = 6,     /*!< M3_0DB : Right channel PGA gain = -3.0 dB                                 */
  PDM0_CORECFG0_PGAR_M1_5DB            = 7,     /*!< M1_5DB : Right channel PGA gain = -1.5 dB                                 */
  PDM0_CORECFG0_PGAR_0DB               = 8,     /*!< 0DB : Right channel PGA gain = 0 DB                                       */
  PDM0_CORECFG0_PGAR_P1_5DB            = 9,     /*!< P1_5DB : Right channel PGA gain = 1.5 dB                                  */
  PDM0_CORECFG0_PGAR_P3_0DB            = 10,    /*!< P3_0DB : Right channel PGA gain = 3.0 dB                                  */
  PDM0_CORECFG0_PGAR_P4_5DB            = 11,    /*!< P4_5DB : Right channel PGA gain = 4.5 dB                                  */
  PDM0_CORECFG0_PGAR_P6_0DB            = 12,    /*!< P6_0DB : Right channel PGA gain = 6.0 DB                                  */
  PDM0_CORECFG0_PGAR_P7_5DB            = 13,    /*!< P7_5DB : Right channel PGA gain = 7.5 dB                                  */
  PDM0_CORECFG0_PGAR_P9_0DB            = 14,    /*!< P9_0DB : Right channel PGA gain = 9.0 dB                                  */
  PDM0_CORECFG0_PGAR_P10_5DB           = 15,    /*!< P10_5DB : Right channel PGA gain = 10.5 dB                                */
  PDM0_CORECFG0_PGAR_P12_0DB           = 16,    /*!< P12_0DB : Right channel PGA gain = 12.0 DB                                */
  PDM0_CORECFG0_PGAR_P13_5DB           = 17,    /*!< P13_5DB : Right channel PGA gain = 13.5 dB                                */
  PDM0_CORECFG0_PGAR_P15_0DB           = 18,    /*!< P15_0DB : Right channel PGA gain = 15.0 dB                                */
  PDM0_CORECFG0_PGAR_P16_5DB           = 19,    /*!< P16_5DB : Right channel PGA gain = 16.5 dB                                */
  PDM0_CORECFG0_PGAR_P18_0DB           = 20,    /*!< P18_0DB : Right channel PGA gain = 18.0 DB                                */
  PDM0_CORECFG0_PGAR_P19_5DB           = 21,    /*!< P19_5DB : Right channel PGA gain = 19.5 dB                                */
  PDM0_CORECFG0_PGAR_P21_0DB           = 22,    /*!< P21_0DB : Right channel PGA gain = 21.0 dB                                */
  PDM0_CORECFG0_PGAR_P22_5DB           = 23,    /*!< P22_5DB : Right channel PGA gain = 22.5 dB                                */
  PDM0_CORECFG0_PGAR_P24_0DB           = 24,    /*!< P24_0DB : Right channel PGA gain = 24.0 DB                                */
  PDM0_CORECFG0_PGAR_P25_5DB           = 25,    /*!< P25_5DB : Right channel PGA gain = 25.5 dB                                */
  PDM0_CORECFG0_PGAR_P27_0DB           = 26,    /*!< P27_0DB : Right channel PGA gain = 27.0 dB                                */
  PDM0_CORECFG0_PGAR_P28_5DB           = 27,    /*!< P28_5DB : Right channel PGA gain = 28.5 dB                                */
  PDM0_CORECFG0_PGAR_P30_0DB           = 28,    /*!< P30_0DB : Right channel PGA gain = 30.0 DB                                */
  PDM0_CORECFG0_PGAR_P31_5DB           = 29,    /*!< P31_5DB : Right channel PGA gain = 31.5 dB                                */
  PDM0_CORECFG0_PGAR_P33_0DB           = 30,    /*!< P33_0DB : Right channel PGA gain = 33.0 dB                                */
  PDM0_CORECFG0_PGAR_P34_5DB           = 31,    /*!< P34_5DB : Right channel PGA gain = 34.5 dB                                */
} PDM0_CORECFG0_PGAR_Enum;

/* ==============================================  PDM0 CORECFG0 PGAL [21..25]  ============================================== */
typedef enum {                                  /*!< PDM0_CORECFG0_PGAL                                                        */
  PDM0_CORECFG0_PGAL_M10_5DB           = 1,     /*!< M10_5DB : Left channel PGA gain = -10.5 dB                                */
  PDM0_CORECFG0_PGAL_M9_0DB            = 2,     /*!< M9_0DB : Left channel PGA gain = -9.0 dB                                  */
  PDM0_CORECFG0_PGAL_M7_5DB            = 3,     /*!< M7_5DB : Left channel PGA gain = -7.5 dB                                  */
  PDM0_CORECFG0_PGAL_M6_0DB            = 4,     /*!< M6_0DB : Left channel PGA gain = -6.0 dB                                  */
  PDM0_CORECFG0_PGAL_M4_5DB            = 5,     /*!< M4_5DB : Left channel PGA gain = -4.5 dB                                  */
  PDM0_CORECFG0_PGAL_M3_0DB            = 6,     /*!< M3_0DB : Left channel PGA gain = -3.0 dB                                  */
  PDM0_CORECFG0_PGAL_M1_5DB            = 7,     /*!< M1_5DB : Left channel PGA gain = -1.5 dB                                  */
  PDM0_CORECFG0_PGAL_0DB               = 8,     /*!< 0DB : Left channel PGA gain = 0 DB                                        */
  PDM0_CORECFG0_PGAL_P1_5DB            = 9,     /*!< P1_5DB : Left channel PGA gain = 1.5 dB                                   */
  PDM0_CORECFG0_PGAL_P3_0DB            = 10,    /*!< P3_0DB : Left channel PGA gain = 3.0 dB                                   */
  PDM0_CORECFG0_PGAL_P4_5DB            = 11,    /*!< P4_5DB : Left channel PGA gain = 4.5 dB                                   */
  PDM0_CORECFG0_PGAL_P6_0DB            = 12,    /*!< P6_0DB : Left channel PGA gain = 6.0 DB                                   */
  PDM0_CORECFG0_PGAL_P7_5DB            = 13,    /*!< P7_5DB : Left channel PGA gain = 7.5 dB                                   */
  PDM0_CORECFG0_PGAL_P9_0DB            = 14,    /*!< P9_0DB : Left channel PGA gain = 9.0 dB                                   */
  PDM0_CORECFG0_PGAL_P10_5DB           = 15,    /*!< P10_5DB : Left channel PGA gain = 10.5 dB                                 */
  PDM0_CORECFG0_PGAL_P12_0DB           = 16,    /*!< P12_0DB : Left channel PGA gain = 12.0 DB                                 */
  PDM0_CORECFG0_PGAL_P13_5DB           = 17,    /*!< P13_5DB : Left channel PGA gain = 13.5 dB                                 */
  PDM0_CORECFG0_PGAL_P15_0DB           = 18,    /*!< P15_0DB : Left channel PGA gain = 15.0 dB                                 */
  PDM0_CORECFG0_PGAL_P16_5DB           = 19,    /*!< P16_5DB : Left channel PGA gain = 16.5 dB                                 */
  PDM0_CORECFG0_PGAL_P18_0DB           = 20,    /*!< P18_0DB : Left channel PGA gain = 18.0 DB                                 */
  PDM0_CORECFG0_PGAL_P19_5DB           = 21,    /*!< P19_5DB : Left channel PGA gain = 19.5 dB                                 */
  PDM0_CORECFG0_PGAL_P21_0DB           = 22,    /*!< P21_0DB : Left channel PGA gain = 21.0 dB                                 */
  PDM0_CORECFG0_PGAL_P22_5DB           = 23,    /*!< P22_5DB : Left channel PGA gain = 22.5 dB                                 */
  PDM0_CORECFG0_PGAL_P24_0DB           = 24,    /*!< P24_0DB : Left channel PGA gain = 24.0 DB                                 */
  PDM0_CORECFG0_PGAL_P25_5DB           = 25,    /*!< P25_5DB : Left channel PGA gain = 25.5 dB                                 */
  PDM0_CORECFG0_PGAL_P27_0DB           = 26,    /*!< P27_0DB : Left channel PGA gain = 27.0 dB                                 */
  PDM0_CORECFG0_PGAL_P28_5DB           = 27,    /*!< P28_5DB : Left channel PGA gain = 28.5 dB                                 */
  PDM0_CORECFG0_PGAL_P30_0DB           = 28,    /*!< P30_0DB : Left channel PGA gain = 30.0 DB                                 */
  PDM0_CORECFG0_PGAL_P31_5DB           = 29,    /*!< P31_5DB : Left channel PGA gain = 31.5 dB                                 */
  PDM0_CORECFG0_PGAL_P33_0DB           = 30,    /*!< P33_0DB : Left channel PGA gain = 33.0 dB                                 */
  PDM0_CORECFG0_PGAL_P34_5DB           = 31,    /*!< P34_5DB : Left channel PGA gain = 34.5 dB                                 */
} PDM0_CORECFG0_PGAL_Enum;

/* ==============================================  PDM0 CORECFG0 ADCHPD [9..9]  ============================================== */
typedef enum {                                  /*!< PDM0_CORECFG0_ADCHPD                                                      */
  PDM0_CORECFG0_ADCHPD_DIS             = 0,     /*!< DIS : Disable high pass filter.                                           */
  PDM0_CORECFG0_ADCHPD_EN              = 1,     /*!< EN : Enable high pass filter.                                             */
} PDM0_CORECFG0_ADCHPD_Enum;

/* =============================================  PDM0 CORECFG0 SCYCLES [2..4]  ============================================== */
typedef enum {                                  /*!< PDM0_CORECFG0_SCYCLES                                                     */
  PDM0_CORECFG0_SCYCLES_0CYCLES        = 0,     /*!< 0CYCLES : Zero PDMA_CK0 clock cycles during gain setting changes
                                                     or soft mute.                                                             */
  PDM0_CORECFG0_SCYCLES_1CYCLES        = 1,     /*!< 1CYCLES : One PDMA_CK0 clock cycle during gain setting changes
                                                     or soft mute.                                                             */
  PDM0_CORECFG0_SCYCLES_2CYCLES        = 2,     /*!< 2CYCLES : Two PDMA_CK0 clock cycles during gain setting changes
                                                     or soft mute.                                                             */
  PDM0_CORECFG0_SCYCLES_3CYCLES        = 3,     /*!< 3CYCLES : Three PDMA_CK0 clock cycles during gain setting changes
                                                     or soft mute.                                                             */
  PDM0_CORECFG0_SCYCLES_4CYCLES        = 4,     /*!< 4CYCLES : Four PDMA_CK0 clock cycles during gain setting changes
                                                     or soft mute.                                                             */
  PDM0_CORECFG0_SCYCLES_5CYCLES        = 5,     /*!< 5CYCLES : Five PDMA_CK0 clock cycles during gain setting changes
                                                     or soft mute.                                                             */
  PDM0_CORECFG0_SCYCLES_6CYCLES        = 6,     /*!< 6CYCLES : Six PDMA_CK0 clock cycles during gain setting changes
                                                     or soft mute.                                                             */
  PDM0_CORECFG0_SCYCLES_7CYCLES        = 7,     /*!< 7CYCLES : Seven PDMA_CK0 clock cycles during gain setting changes
                                                     or soft mute.                                                             */
} PDM0_CORECFG0_SCYCLES_Enum;

/* ==============================================  PDM0 CORECFG0 LRSWAP [0..0]  ============================================== */
typedef enum {                                  /*!< PDM0_CORECFG0_LRSWAP                                                      */
  PDM0_CORECFG0_LRSWAP_DIS             = 0,     /*!< DIS : Disable left/right channel swapping.                                */
  PDM0_CORECFG0_LRSWAP_EN              = 1,     /*!< EN : Enable left/right channel swapping.                                  */
} PDM0_CORECFG0_LRSWAP_Enum;

/* =======================================================  CORECFG1  ======================================================== */
/* =============================================  PDM0 CORECFG1 SELSTEP [7..7]  ============================================== */
typedef enum {                                  /*!< PDM0_CORECFG1_SELSTEP                                                     */
  PDM0_CORECFG1_SELSTEP_0_13DB         = 0,     /*!< 0_13DB : 0.13dB fine grain step size.                                     */
  PDM0_CORECFG1_SELSTEP_0_26DB         = 1,     /*!< 0_26DB : 0.26dB fine grain step size.                                     */
} PDM0_CORECFG1_SELSTEP_Enum;

/* ==============================================  PDM0 CORECFG1 CKODLY [4..6]  ============================================== */
typedef enum {                                  /*!< PDM0_CORECFG1_CKODLY                                                      */
  PDM0_CORECFG1_CKODLY_0CYCLES         = 0,     /*!< 0CYCLES : No extra PDMCLK cycle delays.                                   */
  PDM0_CORECFG1_CKODLY_1CYCLES         = 1,     /*!< 1CYCLES : One xtra PDMCLK cycle delay.                                    */
  PDM0_CORECFG1_CKODLY_2CYCLES         = 2,     /*!< 2CYCLES : Two extra PDMCLK cycle delays.                                  */
  PDM0_CORECFG1_CKODLY_3CYCLES         = 3,     /*!< 3CYCLES : Three extra PDMCLK cycle delays.                                */
  PDM0_CORECFG1_CKODLY_4CYCLES         = 4,     /*!< 4CYCLES : Four extra PDMCLK cycle delays.                                 */
  PDM0_CORECFG1_CKODLY_5CYCLES         = 5,     /*!< 5CYCLES : Five extra PDMCLK cycle delays.                                 */
  PDM0_CORECFG1_CKODLY_6CYCLES         = 6,     /*!< 6CYCLES : Six extra PDMCLK cycle delays.                                  */
  PDM0_CORECFG1_CKODLY_7CYCLES         = 7,     /*!< 7CYCLES : Seven extra PDMCLK cycle delays.                                */
} PDM0_CORECFG1_CKODLY_Enum;

/* =============================================  PDM0 CORECFG1 PCMCHSET [0..1]  ============================================= */
typedef enum {                                  /*!< PDM0_CORECFG1_PCMCHSET                                                    */
  PDM0_CORECFG1_PCMCHSET_CHANDIS       = 0,     /*!< CHANDIS : Channel Disabled                                                */
  PDM0_CORECFG1_PCMCHSET_MONOL         = 1,     /*!< MONOL : MONO Left                                                         */
  PDM0_CORECFG1_PCMCHSET_MONOR         = 2,     /*!< MONOR : MONO right                                                        */
  PDM0_CORECFG1_PCMCHSET_STEREO        = 3,     /*!< STEREO : Stereo                                                           */
} PDM0_CORECFG1_PCMCHSET_Enum;

/* =======================================================  CORECTRL  ======================================================== */
/* ========================================================  FIFOCNT  ======================================================== */
/* =======================================================  FIFOREAD  ======================================================== */
/* =======================================================  FIFOFLUSH  ======================================================= */
/* ========================================================  FIFOTHR  ======================================================== */
/* =========================================================  INTEN  ========================================================= */
/* ========================================================  INTSTAT  ======================================================== */
/* ========================================================  INTCLR  ========================================================= */
/* ========================================================  INTSET  ========================================================= */
/* =======================================================  DMATRIGEN  ======================================================= */
/* ======================================================  DMATRIGSTAT  ====================================================== */
/* ========================================================  DMACFG  ========================================================= */
/* ===============================================  PDM0 DMACFG DMAPRI [8..8]  =============================================== */
typedef enum {                                  /*!< PDM0_DMACFG_DMAPRI                                                        */
  PDM0_DMACFG_DMAPRI_LOW               = 0,     /*!< LOW : Low Priority (service as best effort)                               */
  PDM0_DMACFG_DMAPRI_HIGH              = 1,     /*!< HIGH : High Priority (service immediately)                                */
} PDM0_DMACFG_DMAPRI_Enum;

/* ===============================================  PDM0 DMACFG DMADIR [2..2]  =============================================== */
typedef enum {                                  /*!< PDM0_DMACFG_DMADIR                                                        */
  PDM0_DMACFG_DMADIR_P2M               = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction. THe PDM module
                                                     will only DMA to memory.                                                  */
  PDM0_DMACFG_DMADIR_M2P               = 1,     /*!< M2P : Memory to Peripheral transaction. Not available for PDM
                                                     module                                                                    */
} PDM0_DMACFG_DMADIR_Enum;

/* ===============================================  PDM0 DMACFG DMAEN [0..0]  ================================================ */
typedef enum {                                  /*!< PDM0_DMACFG_DMAEN                                                         */
  PDM0_DMACFG_DMAEN_DIS                = 0,     /*!< DIS : Disable DMA Function                                                */
  PDM0_DMACFG_DMAEN_EN                 = 1,     /*!< EN : Enable DMA Function                                                  */
} PDM0_DMACFG_DMAEN_Enum;

/* ======================================================  DMATARGADDR  ====================================================== */
/* ========================================================  DMASTAT  ======================================================== */
/* ======================================================  DMATOTCOUNT  ====================================================== */


/* =========================================================================================================================== */
/* ================                                          PWRCTRL                                          ================ */
/* =========================================================================================================================== */

/* ======================================================  MCUPERFREQ  ======================================================= */
/* ========================================  PWRCTRL MCUPERFREQ MCUPERFSTATUS [3..4]  ======================================== */
typedef enum {                                  /*!< PWRCTRL_MCUPERFREQ_MCUPERFSTATUS                                          */
  PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_ULP = 0,     /*!< ULP : MCU is in ULP mode (freq=24MHz)                                     */
  PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_LP  = 1,     /*!< LP : MCU is in LP mode (freq=96MHz)                                       */
  PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_HP  = 2,     /*!< HP : MCU is in HP mode (freq=192MHz)                                      */
} PWRCTRL_MCUPERFREQ_MCUPERFSTATUS_Enum;

/* =========================================  PWRCTRL MCUPERFREQ MCUPERFREQ [0..1]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_MCUPERFREQ_MCUPERFREQ                                             */
  PWRCTRL_MCUPERFREQ_MCUPERFREQ_ULP    = 0,     /*!< ULP : MCU to be run in ULP mode (freq=24MHz)                              */
  PWRCTRL_MCUPERFREQ_MCUPERFREQ_LP     = 1,     /*!< LP : MCU to be run in LP mode (freq=96MHz)                                */
  PWRCTRL_MCUPERFREQ_MCUPERFREQ_HP     = 2,     /*!< HP : MCU to be run in HP mode (freq=192MHz)                               */
} PWRCTRL_MCUPERFREQ_MCUPERFREQ_Enum;

/* =======================================================  DEVPWREN  ======================================================== */
/* ==========================================  PWRCTRL DEVPWREN PWRENDBG [24..24]  =========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENDBG                                                 */
  PWRCTRL_DEVPWREN_PWRENDBG_EN         = 1,     /*!< EN : Enable                                                               */
  PWRCTRL_DEVPWREN_PWRENDBG_DIS        = 0,     /*!< DIS : Disable                                                             */
} PWRCTRL_DEVPWREN_PWRENDBG_Enum;

/* ==========================================  PWRCTRL DEVPWREN PWRENSDIO [21..21]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENSDIO                                                */
  PWRCTRL_DEVPWREN_PWRENSDIO_EN        = 1,     /*!< EN : Power up SDIO                                                        */
  PWRCTRL_DEVPWREN_PWRENSDIO_DIS       = 0,     /*!< DIS : Power down SDIO                                                     */
} PWRCTRL_DEVPWREN_PWRENSDIO_Enum;

/* =========================================  PWRCTRL DEVPWREN PWRENCRYPTO [20..20]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENCRYPTO                                              */
  PWRCTRL_DEVPWREN_PWRENCRYPTO_EN      = 1,     /*!< EN : Power up CRYPTO                                                      */
  PWRCTRL_DEVPWREN_PWRENCRYPTO_DIS     = 0,     /*!< DIS : Power down CRYPTO                                                   */
} PWRCTRL_DEVPWREN_PWRENCRYPTO_Enum;

/* ==========================================  PWRCTRL DEVPWREN PWRENGFX [17..17]  =========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENGFX                                                 */
  PWRCTRL_DEVPWREN_PWRENGFX_EN         = 1,     /*!< EN : Power up GFX                                                         */
  PWRCTRL_DEVPWREN_PWRENGFX_DIS        = 0,     /*!< DIS : Power down GFX                                                      */
} PWRCTRL_DEVPWREN_PWRENGFX_Enum;

/* =========================================  PWRCTRL DEVPWREN PWRENMSPI2 [16..16]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENMSPI2                                               */
  PWRCTRL_DEVPWREN_PWRENMSPI2_EN       = 1,     /*!< EN : Power up MSPI2                                                       */
  PWRCTRL_DEVPWREN_PWRENMSPI2_DIS      = 0,     /*!< DIS : Power down MSPI2                                                    */
} PWRCTRL_DEVPWREN_PWRENMSPI2_Enum;

/* =========================================  PWRCTRL DEVPWREN PWRENMSPI1 [15..15]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENMSPI1                                               */
  PWRCTRL_DEVPWREN_PWRENMSPI1_EN       = 1,     /*!< EN : Power up MSPI1                                                       */
  PWRCTRL_DEVPWREN_PWRENMSPI1_DIS      = 0,     /*!< DIS : Power down MSPI1                                                    */
} PWRCTRL_DEVPWREN_PWRENMSPI1_Enum;

/* =========================================  PWRCTRL DEVPWREN PWRENMSPI0 [14..14]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENMSPI0                                               */
  PWRCTRL_DEVPWREN_PWRENMSPI0_EN       = 1,     /*!< EN : Power up MSPI0                                                       */
  PWRCTRL_DEVPWREN_PWRENMSPI0_DIS      = 0,     /*!< DIS : Power down MSPI0                                                    */
} PWRCTRL_DEVPWREN_PWRENMSPI0_Enum;

/* ==========================================  PWRCTRL DEVPWREN PWRENADC [13..13]  =========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENADC                                                 */
  PWRCTRL_DEVPWREN_PWRENADC_EN         = 1,     /*!< EN : Power up ADC                                                         */
  PWRCTRL_DEVPWREN_PWRENADC_DIS        = 0,     /*!< DIS : Power Down ADC                                                      */
} PWRCTRL_DEVPWREN_PWRENADC_Enum;

/* =========================================  PWRCTRL DEVPWREN PWRENUART3 [12..12]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENUART3                                               */
  PWRCTRL_DEVPWREN_PWRENUART3_EN       = 1,     /*!< EN : Power up UART 3                                                      */
  PWRCTRL_DEVPWREN_PWRENUART3_DIS      = 0,     /*!< DIS : Power down UART 3                                                   */
} PWRCTRL_DEVPWREN_PWRENUART3_Enum;

/* =========================================  PWRCTRL DEVPWREN PWRENUART2 [11..11]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENUART2                                               */
  PWRCTRL_DEVPWREN_PWRENUART2_EN       = 1,     /*!< EN : Power up UART 2                                                      */
  PWRCTRL_DEVPWREN_PWRENUART2_DIS      = 0,     /*!< DIS : Power down UART 2                                                   */
} PWRCTRL_DEVPWREN_PWRENUART2_Enum;

/* =========================================  PWRCTRL DEVPWREN PWRENUART1 [10..10]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENUART1                                               */
  PWRCTRL_DEVPWREN_PWRENUART1_EN       = 1,     /*!< EN : Power up UART 1                                                      */
  PWRCTRL_DEVPWREN_PWRENUART1_DIS      = 0,     /*!< DIS : Power down UART 1                                                   */
} PWRCTRL_DEVPWREN_PWRENUART1_Enum;

/* ==========================================  PWRCTRL DEVPWREN PWRENUART0 [9..9]  =========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENUART0                                               */
  PWRCTRL_DEVPWREN_PWRENUART0_EN       = 1,     /*!< EN : Power up UART 0                                                      */
  PWRCTRL_DEVPWREN_PWRENUART0_DIS      = 0,     /*!< DIS : Power down UART 0                                                   */
} PWRCTRL_DEVPWREN_PWRENUART0_Enum;

/* ===========================================  PWRCTRL DEVPWREN PWRENIOM7 [8..8]  =========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM7                                                */
  PWRCTRL_DEVPWREN_PWRENIOM7_EN        = 1,     /*!< EN : Power up IO Master 7                                                 */
  PWRCTRL_DEVPWREN_PWRENIOM7_DIS       = 0,     /*!< DIS : Power down IO Master 7                                              */
} PWRCTRL_DEVPWREN_PWRENIOM7_Enum;

/* ===========================================  PWRCTRL DEVPWREN PWRENIOM6 [7..7]  =========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM6                                                */
  PWRCTRL_DEVPWREN_PWRENIOM6_EN        = 1,     /*!< EN : Power up IO Master 6                                                 */
  PWRCTRL_DEVPWREN_PWRENIOM6_DIS       = 0,     /*!< DIS : Power down IO Master 6                                              */
} PWRCTRL_DEVPWREN_PWRENIOM6_Enum;

/* ===========================================  PWRCTRL DEVPWREN PWRENIOM5 [6..6]  =========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM5                                                */
  PWRCTRL_DEVPWREN_PWRENIOM5_EN        = 1,     /*!< EN : Power up IO Master 5                                                 */
  PWRCTRL_DEVPWREN_PWRENIOM5_DIS       = 0,     /*!< DIS : Power down IO Master 5                                              */
} PWRCTRL_DEVPWREN_PWRENIOM5_Enum;

/* ===========================================  PWRCTRL DEVPWREN PWRENIOM4 [5..5]  =========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM4                                                */
  PWRCTRL_DEVPWREN_PWRENIOM4_EN        = 1,     /*!< EN : Power up IO Master 4                                                 */
  PWRCTRL_DEVPWREN_PWRENIOM4_DIS       = 0,     /*!< DIS : Power down IO Master 4                                              */
} PWRCTRL_DEVPWREN_PWRENIOM4_Enum;

/* ===========================================  PWRCTRL DEVPWREN PWRENIOM3 [4..4]  =========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM3                                                */
  PWRCTRL_DEVPWREN_PWRENIOM3_EN        = 1,     /*!< EN : Power up IO Master 3                                                 */
  PWRCTRL_DEVPWREN_PWRENIOM3_DIS       = 0,     /*!< DIS : Power down IO Master 3                                              */
} PWRCTRL_DEVPWREN_PWRENIOM3_Enum;

/* ===========================================  PWRCTRL DEVPWREN PWRENIOM2 [3..3]  =========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM2                                                */
  PWRCTRL_DEVPWREN_PWRENIOM2_EN        = 1,     /*!< EN : Power up IO Master 2                                                 */
  PWRCTRL_DEVPWREN_PWRENIOM2_DIS       = 0,     /*!< DIS : Power down IO Master 2                                              */
} PWRCTRL_DEVPWREN_PWRENIOM2_Enum;

/* ===========================================  PWRCTRL DEVPWREN PWRENIOM1 [2..2]  =========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM1                                                */
  PWRCTRL_DEVPWREN_PWRENIOM1_EN        = 1,     /*!< EN : Power up IO Master 1                                                 */
  PWRCTRL_DEVPWREN_PWRENIOM1_DIS       = 0,     /*!< DIS : Power down IO Master 1                                              */
} PWRCTRL_DEVPWREN_PWRENIOM1_Enum;

/* ===========================================  PWRCTRL DEVPWREN PWRENIOM0 [1..1]  =========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOM0                                                */
  PWRCTRL_DEVPWREN_PWRENIOM0_EN        = 1,     /*!< EN : Power up IO Master 0                                                 */
  PWRCTRL_DEVPWREN_PWRENIOM0_DIS       = 0,     /*!< DIS : Power down IO Master 0                                              */
} PWRCTRL_DEVPWREN_PWRENIOM0_Enum;

/* ===========================================  PWRCTRL DEVPWREN PWRENIOS [0..0]  ============================================ */
typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRENIOS                                                 */
  PWRCTRL_DEVPWREN_PWRENIOS_EN         = 1,     /*!< EN : Power up IO slave                                                    */
  PWRCTRL_DEVPWREN_PWRENIOS_DIS        = 0,     /*!< DIS : Power down IO slave                                                 */
} PWRCTRL_DEVPWREN_PWRENIOS_Enum;

/* =====================================================  DEVPWRSTATUS  ====================================================== */
/* ========================================  PWRCTRL DEVPWRSTATUS PWRSTDBG [24..24]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTDBG                                             */
  PWRCTRL_DEVPWRSTATUS_PWRSTDBG_ON     = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTDBG_OFF    = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTDBG_Enum;

/* ========================================  PWRCTRL DEVPWRSTATUS PWRSTSDIO [21..21]  ======================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTSDIO                                            */
  PWRCTRL_DEVPWRSTATUS_PWRSTSDIO_ON    = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTSDIO_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTSDIO_Enum;

/* =======================================  PWRCTRL DEVPWRSTATUS PWRSTCRYPTO [20..20]  ======================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO                                          */
  PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO_ON  = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO_OFF = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTCRYPTO_Enum;

/* ========================================  PWRCTRL DEVPWRSTATUS PWRSTGFX [17..17]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTGFX                                             */
  PWRCTRL_DEVPWRSTATUS_PWRSTGFX_ON     = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTGFX_OFF    = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTGFX_Enum;

/* =======================================  PWRCTRL DEVPWRSTATUS PWRSTMSPI2 [16..16]  ======================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2                                           */
  PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2_ON   = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTMSPI2_Enum;

/* =======================================  PWRCTRL DEVPWRSTATUS PWRSTMSPI1 [15..15]  ======================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1                                           */
  PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1_ON   = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTMSPI1_Enum;

/* =======================================  PWRCTRL DEVPWRSTATUS PWRSTMSPI0 [14..14]  ======================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0                                           */
  PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0_ON   = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTMSPI0_Enum;

/* ========================================  PWRCTRL DEVPWRSTATUS PWRSTADC [13..13]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTADC                                             */
  PWRCTRL_DEVPWRSTATUS_PWRSTADC_ON     = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTADC_OFF    = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTADC_Enum;

/* =======================================  PWRCTRL DEVPWRSTATUS PWRSTUART3 [12..12]  ======================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTUART3                                           */
  PWRCTRL_DEVPWRSTATUS_PWRSTUART3_ON   = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTUART3_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTUART3_Enum;

/* =======================================  PWRCTRL DEVPWRSTATUS PWRSTUART2 [11..11]  ======================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTUART2                                           */
  PWRCTRL_DEVPWRSTATUS_PWRSTUART2_ON   = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTUART2_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTUART2_Enum;

/* =======================================  PWRCTRL DEVPWRSTATUS PWRSTUART1 [10..10]  ======================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTUART1                                           */
  PWRCTRL_DEVPWRSTATUS_PWRSTUART1_ON   = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTUART1_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTUART1_Enum;

/* ========================================  PWRCTRL DEVPWRSTATUS PWRSTUART0 [9..9]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTUART0                                           */
  PWRCTRL_DEVPWRSTATUS_PWRSTUART0_ON   = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTUART0_OFF  = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTUART0_Enum;

/* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM7 [8..8]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM7                                            */
  PWRCTRL_DEVPWRSTATUS_PWRSTIOM7_ON    = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTIOM7_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTIOM7_Enum;

/* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM6 [7..7]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM6                                            */
  PWRCTRL_DEVPWRSTATUS_PWRSTIOM6_ON    = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTIOM6_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTIOM6_Enum;

/* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM5 [6..6]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM5                                            */
  PWRCTRL_DEVPWRSTATUS_PWRSTIOM5_ON    = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTIOM5_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTIOM5_Enum;

/* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM4 [5..5]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM4                                            */
  PWRCTRL_DEVPWRSTATUS_PWRSTIOM4_ON    = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTIOM4_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTIOM4_Enum;

/* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM3 [4..4]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM3                                            */
  PWRCTRL_DEVPWRSTATUS_PWRSTIOM3_ON    = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTIOM3_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTIOM3_Enum;

/* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM2 [3..3]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM2                                            */
  PWRCTRL_DEVPWRSTATUS_PWRSTIOM2_ON    = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTIOM2_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTIOM2_Enum;

/* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM1 [2..2]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM1                                            */
  PWRCTRL_DEVPWRSTATUS_PWRSTIOM1_ON    = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTIOM1_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTIOM1_Enum;

/* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOM0 [1..1]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOM0                                            */
  PWRCTRL_DEVPWRSTATUS_PWRSTIOM0_ON    = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTIOM0_OFF   = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTIOM0_Enum;

/* =========================================  PWRCTRL DEVPWRSTATUS PWRSTIOS [0..0]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWRSTATUS_PWRSTIOS                                             */
  PWRCTRL_DEVPWRSTATUS_PWRSTIOS_ON     = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_DEVPWRSTATUS_PWRSTIOS_OFF    = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_DEVPWRSTATUS_PWRSTIOS_Enum;

/* ======================================================  AUDSSPWREN  ======================================================= */
/* ==========================================  PWRCTRL AUDSSPWREN PWRENI2S1 [7..7]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENI2S1                                              */
  PWRCTRL_AUDSSPWREN_PWRENI2S1_EN      = 1,     /*!< EN : Power up I2S1                                                        */
  PWRCTRL_AUDSSPWREN_PWRENI2S1_DIS     = 0,     /*!< DIS : Power down I2S1                                                     */
} PWRCTRL_AUDSSPWREN_PWRENI2S1_Enum;

/* ==========================================  PWRCTRL AUDSSPWREN PWRENI2S0 [6..6]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENI2S0                                              */
  PWRCTRL_AUDSSPWREN_PWRENI2S0_EN      = 1,     /*!< EN : Power up I2S0                                                        */
  PWRCTRL_AUDSSPWREN_PWRENI2S0_DIS     = 0,     /*!< DIS : Power down I2S0                                                     */
} PWRCTRL_AUDSSPWREN_PWRENI2S0_Enum;

/* ==========================================  PWRCTRL AUDSSPWREN PWRENPDM0 [2..2]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENPDM0                                              */
  PWRCTRL_AUDSSPWREN_PWRENPDM0_EN      = 1,     /*!< EN : Power up PDM0                                                        */
  PWRCTRL_AUDSSPWREN_PWRENPDM0_DIS     = 0,     /*!< DIS : Power down PDM0                                                     */
} PWRCTRL_AUDSSPWREN_PWRENPDM0_Enum;

/* =========================================  PWRCTRL AUDSSPWREN PWRENAUDPB [1..1]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENAUDPB                                             */
  PWRCTRL_AUDSSPWREN_PWRENAUDPB_EN     = 1,     /*!< EN : Power up AUDPB                                                       */
  PWRCTRL_AUDSSPWREN_PWRENAUDPB_DIS    = 0,     /*!< DIS : Power down AUDPB                                                    */
} PWRCTRL_AUDSSPWREN_PWRENAUDPB_Enum;

/* =========================================  PWRCTRL AUDSSPWREN PWRENAUDREC [0..0]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_AUDSSPWREN_PWRENAUDREC                                            */
  PWRCTRL_AUDSSPWREN_PWRENAUDREC_EN    = 1,     /*!< EN : Power up AUDREC                                                      */
  PWRCTRL_AUDSSPWREN_PWRENAUDREC_DIS   = 0,     /*!< DIS : Power down AUDREC                                                   */
} PWRCTRL_AUDSSPWREN_PWRENAUDREC_Enum;

/* ====================================================  AUDSSPWRSTATUS  ===================================================== */
/* ========================================  PWRCTRL AUDSSPWRSTATUS PWRSTI2S1 [7..7]  ======================================== */
typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1                                          */
  PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1_ON  = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1_OFF = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S1_Enum;

/* ========================================  PWRCTRL AUDSSPWRSTATUS PWRSTI2S0 [6..6]  ======================================== */
typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0                                          */
  PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0_ON  = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0_OFF = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_AUDSSPWRSTATUS_PWRSTI2S0_Enum;

/* ========================================  PWRCTRL AUDSSPWRSTATUS PWRSTPDM0 [2..2]  ======================================== */
typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0                                          */
  PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0_ON  = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0_OFF = 0,     /*!< OFF : Domain powered off                                                  */
} PWRCTRL_AUDSSPWRSTATUS_PWRSTPDM0_Enum;

/* =======================================  PWRCTRL AUDSSPWRSTATUS PWRSTAUDPB [1..1]  ======================================== */
typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB                                         */
  PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB_ON = 1,     /*!< ON : Domain powered on                                                    */
  PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB_OFF = 0,    /*!< OFF : Domain powered off                                                  */
} PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDPB_Enum;

/* =======================================  PWRCTRL AUDSSPWRSTATUS PWRSTAUDREC [0..0]  ======================================= */
typedef enum {                                  /*!< PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC                                        */
  PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC_ON = 1,    /*!< ON : Domain powered on                                                    */
  PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC_OFF = 0,   /*!< OFF : Domain powered off                                                  */
} PWRCTRL_AUDSSPWRSTATUS_PWRSTAUDREC_Enum;

/* =======================================================  MEMPWREN  ======================================================== */
/* =========================================  PWRCTRL MEMPWREN PWRENCACHEB2 [5..5]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_MEMPWREN_PWRENCACHEB2                                             */
  PWRCTRL_MEMPWREN_PWRENCACHEB2_EN     = 1,     /*!< EN : Power up Cache Bank 2                                                */
  PWRCTRL_MEMPWREN_PWRENCACHEB2_DIS    = 0,     /*!< DIS : Power down Cache Bank 2                                             */
} PWRCTRL_MEMPWREN_PWRENCACHEB2_Enum;

/* =========================================  PWRCTRL MEMPWREN PWRENCACHEB0 [4..4]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_MEMPWREN_PWRENCACHEB0                                             */
  PWRCTRL_MEMPWREN_PWRENCACHEB0_EN     = 1,     /*!< EN : Power up Cache Bank 0                                                */
  PWRCTRL_MEMPWREN_PWRENCACHEB0_DIS    = 0,     /*!< DIS : Power down Cache Bank 0                                             */
} PWRCTRL_MEMPWREN_PWRENCACHEB0_Enum;

/* ===========================================  PWRCTRL MEMPWREN PWRENNVM0 [3..3]  =========================================== */
typedef enum {                                  /*!< PWRCTRL_MEMPWREN_PWRENNVM0                                                */
  PWRCTRL_MEMPWREN_PWRENNVM0_EN        = 1,     /*!< EN : Power up NVM0                                                        */
  PWRCTRL_MEMPWREN_PWRENNVM0_DIS       = 0,     /*!< DIS : Power down NVM0                                                     */
} PWRCTRL_MEMPWREN_PWRENNVM0_Enum;

/* ===========================================  PWRCTRL MEMPWREN PWRENDTCM [0..2]  =========================================== */
typedef enum {                                  /*!< PWRCTRL_MEMPWREN_PWRENDTCM                                                */
  PWRCTRL_MEMPWREN_PWRENDTCM_NONE      = 0,     /*!< NONE : Do not enable power to any DTCMs                                   */
  PWRCTRL_MEMPWREN_PWRENDTCM_TCM32K    = 1,     /*!< TCM32K : Power ON only lower 32k                                          */
  PWRCTRL_MEMPWREN_PWRENDTCM_TCM128K   = 3,     /*!< TCM128K : Power ON only lower 128k                                        */
  PWRCTRL_MEMPWREN_PWRENDTCM_TCM384K   = 7,     /*!< TCM384K : Power ON 384k                                                   */
} PWRCTRL_MEMPWREN_PWRENDTCM_Enum;

/* =====================================================  MEMPWRSTATUS  ====================================================== */
/* =========================================  PWRCTRL MEMPWRSTATUS PWRSTDTCM [0..2]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_MEMPWRSTATUS_PWRSTDTCM                                            */
  PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_NONE  = 0,     /*!< NONE : Do not enable power to any DTCMs                                   */
  PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_TCM32K = 1,    /*!< TCM32K : Only lower 32k is powered up                                     */
  PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_TCM128K = 3,   /*!< TCM128K : Only lower 128k is powered up                                   */
  PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_TCM384K = 7,   /*!< TCM384K : All 384k is powered up                                          */
} PWRCTRL_MEMPWRSTATUS_PWRSTDTCM_Enum;

/* =======================================================  MEMRETCFG  ======================================================= */
/* =========================================  PWRCTRL MEMRETCFG CACHEPWDSLP [4..4]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_MEMRETCFG_CACHEPWDSLP                                             */
  PWRCTRL_MEMRETCFG_CACHEPWDSLP_EN     = 1,     /*!< EN : Power down cache in deep sleep                                       */
  PWRCTRL_MEMRETCFG_CACHEPWDSLP_DIS    = 0,     /*!< DIS : Retain cache in deep sleep                                          */
} PWRCTRL_MEMRETCFG_CACHEPWDSLP_Enum;

/* ==========================================  PWRCTRL MEMRETCFG NVM0PWDSLP [3..3]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_MEMRETCFG_NVM0PWDSLP                                              */
  PWRCTRL_MEMRETCFG_NVM0PWDSLP_EN      = 1,     /*!< EN : NVM0 is powered down during deepsleep                                */
  PWRCTRL_MEMRETCFG_NVM0PWDSLP_DIS     = 0,     /*!< DIS : NVM0 is kept powered on during deepsleep                            */
} PWRCTRL_MEMRETCFG_NVM0PWDSLP_Enum;

/* ==========================================  PWRCTRL MEMRETCFG DTCMPWDSLP [0..2]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_MEMRETCFG_DTCMPWDSLP                                              */
  PWRCTRL_MEMRETCFG_DTCMPWDSLP_NONE    = 0,     /*!< NONE : All DTCM retained                                                  */
  PWRCTRL_MEMRETCFG_DTCMPWDSLP_GROUP0DTCM0 = 1, /*!< GROUP0DTCM0 : Group0_DTCM0 powered down in deep sleep (0KB-32KB)          */
  PWRCTRL_MEMRETCFG_DTCMPWDSLP_GROUP0DTCM1 = 2, /*!< GROUP0DTCM1 : Group0_DTCM1 powered down in deep sleep (32KB-128KB)        */
  PWRCTRL_MEMRETCFG_DTCMPWDSLP_GROUP0  = 3,     /*!< GROUP0 : Both DTCMs in group0 are powered down in deep sleep
                                                     (0KB-128KB)                                                               */
  PWRCTRL_MEMRETCFG_DTCMPWDSLP_ALLBUTGROUP0DTCM0 = 6,/*!< ALLBUTGROUP0DTCM0 : Group1 and Group0_DTCM1 are powered down
                                                     in deep sleep (32KB-384KB)                                                */
  PWRCTRL_MEMRETCFG_DTCMPWDSLP_GROUP1  = 4,     /*!< GROUP1 : Group1 DTCM powered down in deep sleep (128KB-384KB)             */
  PWRCTRL_MEMRETCFG_DTCMPWDSLP_ALL     = 7,     /*!< ALL : All DTCMs powered down in deep sleep (0KB-384KB)                    */
} PWRCTRL_MEMRETCFG_DTCMPWDSLP_Enum;

/* =====================================================  SYSPWRSTATUS  ====================================================== */
/* ======================================================  SSRAMPWREN  ======================================================= */
/* =========================================  PWRCTRL SSRAMPWREN PWRENSSRAM [0..1]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_SSRAMPWREN_PWRENSSRAM                                             */
  PWRCTRL_SSRAMPWREN_PWRENSSRAM_NONE   = 0,     /*!< NONE : Do not power ON any of the SRAM banks                              */
  PWRCTRL_SSRAMPWREN_PWRENSSRAM_GROUP0 = 1,     /*!< GROUP0 : Power ON only SRAM0 group (lower 1M)                             */
  PWRCTRL_SSRAMPWREN_PWRENSSRAM_GROUP1 = 2,     /*!< GROUP1 : Power ON only SRAM1 group (upper 1M)                             */
  PWRCTRL_SSRAMPWREN_PWRENSSRAM_ALL    = 3,     /*!< ALL : All shared SRAM banks (SSRAM0 1M + SSRAM1 1M) powered
                                                     ON                                                                        */
} PWRCTRL_SSRAMPWREN_PWRENSSRAM_Enum;

/* ======================================================  SSRAMPWRST  ======================================================= */
/* ======================================================  SSRAMRETCFG  ====================================================== */
/* ========================================  PWRCTRL SSRAMRETCFG SSRAMPWDSLP [0..1]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP                                           */
  PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_NONE = 0,     /*!< NONE : All banks retained                                                 */
  PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_GROUP0 = 1,   /*!< GROUP0 : Power down only SRAM group0                                      */
  PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_GROUP1 = 2,   /*!< GROUP1 : Power down only SRAM group1                                      */
  PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_ALL  = 3,     /*!< ALL : All shared SRAM banks powered down                                  */
} PWRCTRL_SSRAMRETCFG_SSRAMPWDSLP_Enum;

/* =====================================================  DEVPWREVENTEN  ===================================================== */
/* =========================================  PWRCTRL DEVPWREVENTEN AUDEVEN [7..7]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_AUDEVEN                                             */
  PWRCTRL_DEVPWREVENTEN_AUDEVEN_EN     = 1,     /*!< EN : Enable AUD power-on status event                                     */
  PWRCTRL_DEVPWREVENTEN_AUDEVEN_DIS    = 0,     /*!< DIS : Disable AUD power-on status event                                   */
} PWRCTRL_DEVPWREVENTEN_AUDEVEN_Enum;

/* =========================================  PWRCTRL DEVPWREVENTEN MSPIEVEN [6..6]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_MSPIEVEN                                            */
  PWRCTRL_DEVPWREVENTEN_MSPIEVEN_EN    = 1,     /*!< EN : Enable MSPI power-on status event                                    */
  PWRCTRL_DEVPWREVENTEN_MSPIEVEN_DIS   = 0,     /*!< DIS : Disable MSPI power-on status event                                  */
} PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Enum;

/* =========================================  PWRCTRL DEVPWREVENTEN ADCEVEN [5..5]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_ADCEVEN                                             */
  PWRCTRL_DEVPWREVENTEN_ADCEVEN_EN     = 1,     /*!< EN : Enable ADC power-on status event                                     */
  PWRCTRL_DEVPWREVENTEN_ADCEVEN_DIS    = 0,     /*!< DIS : Disable ADC power-on status event                                   */
} PWRCTRL_DEVPWREVENTEN_ADCEVEN_Enum;

/* =========================================  PWRCTRL DEVPWREVENTEN HCPCEVEN [4..4]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_HCPCEVEN                                            */
  PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN    = 1,     /*!< EN : Enable HCPC power-on status event                                    */
  PWRCTRL_DEVPWREVENTEN_HCPCEVEN_DIS   = 0,     /*!< DIS : Disable HCPC power-on status event                                  */
} PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Enum;

/* =========================================  PWRCTRL DEVPWREVENTEN HCPBEVEN [3..3]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_HCPBEVEN                                            */
  PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN    = 1,     /*!< EN : Enable HCPB power-on status event                                    */
  PWRCTRL_DEVPWREVENTEN_HCPBEVEN_DIS   = 0,     /*!< DIS : Disable HCPB power-on status event                                  */
} PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Enum;

/* =========================================  PWRCTRL DEVPWREVENTEN HCPAEVEN [2..2]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_HCPAEVEN                                            */
  PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN    = 1,     /*!< EN : Enable HCPA power-on status event                                    */
  PWRCTRL_DEVPWREVENTEN_HCPAEVEN_DIS   = 0,     /*!< DIS : Disable HCPA power-on status event                                  */
} PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Enum;

/* =========================================  PWRCTRL DEVPWREVENTEN MCUHEVEN [1..1]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_MCUHEVEN                                            */
  PWRCTRL_DEVPWREVENTEN_MCUHEVEN_EN    = 1,     /*!< EN : Enable MCHU power-on status event                                    */
  PWRCTRL_DEVPWREVENTEN_MCUHEVEN_DIS   = 0,     /*!< DIS : Disable MCUH power-on status event                                  */
} PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Enum;

/* =========================================  PWRCTRL DEVPWREVENTEN MCULEVEN [0..0]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_MCULEVEN                                            */
  PWRCTRL_DEVPWREVENTEN_MCULEVEN_EN    = 1,     /*!< EN : Enable MCUL power-on status event                                    */
  PWRCTRL_DEVPWREVENTEN_MCULEVEN_DIS   = 0,     /*!< DIS : Disable MCUL power-on status event                                  */
} PWRCTRL_DEVPWREVENTEN_MCULEVEN_Enum;

/* =====================================================  MEMPWREVENTEN  ===================================================== */
/* ========================================  PWRCTRL MEMPWREVENTEN CACHEB2EN [5..5]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_CACHEB2EN                                           */
  PWRCTRL_MEMPWREVENTEN_CACHEB2EN_EN   = 1,     /*!< EN : Enable CACHE BANK 2 status event                                     */
  PWRCTRL_MEMPWREVENTEN_CACHEB2EN_DIS  = 0,     /*!< DIS : Disable CACHE BANK 2 status event                                   */
} PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Enum;

/* ========================================  PWRCTRL MEMPWREVENTEN CACHEB0EN [4..4]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_CACHEB0EN                                           */
  PWRCTRL_MEMPWREVENTEN_CACHEB0EN_EN   = 1,     /*!< EN : Enable CACHE BANK 0 status event                                     */
  PWRCTRL_MEMPWREVENTEN_CACHEB0EN_DIS  = 0,     /*!< DIS : Disable CACHE BANK 0 status event                                   */
} PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Enum;

/* ==========================================  PWRCTRL MEMPWREVENTEN NVM0EN [3..3]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_NVM0EN                                              */
  PWRCTRL_MEMPWREVENTEN_NVM0EN_EN      = 1,     /*!< EN : Enable NVM status event                                              */
  PWRCTRL_MEMPWREVENTEN_NVM0EN_DIS     = 0,     /*!< DIS : Disables NVM status event                                           */
} PWRCTRL_MEMPWREVENTEN_NVM0EN_Enum;

/* ==========================================  PWRCTRL MEMPWREVENTEN DTCMEN [0..2]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_DTCMEN                                              */
  PWRCTRL_MEMPWREVENTEN_DTCMEN_NONE    = 0,     /*!< NONE : Do not enable DTCM power-on status event                           */
  PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM0EN = 1,/*!< GROUP0DTCM0EN : Enable GROUP0_DTCM0 power on status event                */
  PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM1EN = 2,/*!< GROUP0DTCM1EN : Enable GROUP0_DTCM1 power on status event                */
  PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0EN = 3,    /*!< GROUP0EN : Enable DTCMs in group0 power on status event                   */
  PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP1EN = 4,    /*!< GROUP1EN : Enable DTCMs in group1 power on status event                   */
  PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL     = 7,     /*!< ALL : Enable all DTCM power on status event                               */
} PWRCTRL_MEMPWREVENTEN_DTCMEN_Enum;

/* ======================================================  MMSOVERRIDE  ====================================================== */
/* ====================================  PWRCTRL MMSOVERRIDE MMSOVRSSRAMRETGFX [10..11]  ===================================== */
typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX                                     */
  PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX_ALWAYSON = 1,/*!< ALWAYSON : When PD_GFX is off, retention is always okay for
                                                     PD_GFX domain.                                                            */
  PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX_PGSTATE = 0,/*!< PGSTATE : When PD_GFX is off, retention is okay based on the
                                                     state of PD_GFX domain and SSRAMRETCFG.                                   */
} PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETGFX_Enum;

/* =====================================  PWRCTRL MMSOVERRIDE MMSOVRSSRAMRETDISP [8..9]  ===================================== */
typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP                                    */
  PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP_ALWAYSON = 1,/*!< ALWAYSON : When PD_DISP is off, retention is always okay for
                                                     PD_DISP domain.                                                           */
  PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP_PGSTATE = 0,/*!< PGSTATE : When PD_DISP is off, retention is okay based on the
                                                     state of PD_DISP domain and SSRAMRETCFG.                                  */
} PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMRETDISP_Enum;

/* =====================================  PWRCTRL MMSOVERRIDE MMSOVRDSPRAMRETGFX [6..7]  ===================================== */
typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX                                    */
  PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX_ALWAYSON = 1,/*!< ALWAYSON : When PD_GFX is off, retention is always okay for
                                                     PD_GFX domain.                                                            */
  PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX_PGSTATE = 0,/*!< PGSTATE : When PD_GFX is off, retention is okay based on the
                                                     state of PD_GFX domain and DSP[1|0]MEMRETCFG.                             */
} PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETGFX_Enum;

/* ====================================  PWRCTRL MMSOVERRIDE MMSOVRDSPRAMRETDISP [4..5]  ===================================== */
typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP                                   */
  PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP_ALWAYSON = 1,/*!< ALWAYSON : When PD_DISP is off, retention is always okay for
                                                     PD_DISP domain.                                                           */
  PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP_PGSTATE = 0,/*!< PGSTATE : When PD_DISP is off, retention is okay based on the
                                                     state of PD_DISP domain and DSP[1|0]MEMRETCFG.                            */
} PWRCTRL_MMSOVERRIDE_MMSOVRDSPRAMRETDISP_Enum;

/* =======================================  PWRCTRL MMSOVERRIDE MMSOVRSSRAMGFX [3..3]  ======================================= */
typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX                                        */
  PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX_NOGFX = 1, /*!< NOGFX : SSRAM power state is not affected by PD_GFX setting.              */
  PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX_PD_GFX = 0,/*!< PD_GFX : SSRAM power state set by SSRAMPWREN_PWRENSSRAM is overridden
                                                     by PD_GFX setting.                                                        */
} PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMGFX_Enum;

/* ======================================  PWRCTRL MMSOVERRIDE MMSOVRSSRAMDISP [2..2]  ======================================= */
typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP                                       */
  PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP_NODISP = 1,/*!< NODISP : SSRAM power state is not affected by PD_DISP setting.           */
  PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP_PD_DISP = 0,/*!< PD_DISP : SSRAM power state set by SSRAMPWREN_PWRENSSRAM is
                                                     overridden by PD_DISP setting.                                            */
} PWRCTRL_MMSOVERRIDE_MMSOVRSSRAMDISP_Enum;

/* =======================================  PWRCTRL MMSOVERRIDE MMSOVRMCULGFX [1..1]  ======================================== */
typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX                                         */
  PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX_MCULON = 0, /*!< MCULON : When PD_GFX is on, MCUL is on.                                   */
  PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX_MCULOFF = 1,/*!< MCULOFF : When PD_GFX is on, MCUL is still off.                           */
} PWRCTRL_MMSOVERRIDE_MMSOVRMCULGFX_Enum;

/* =======================================  PWRCTRL MMSOVERRIDE MMSOVRMCULDISP [0..0]  ======================================= */
typedef enum {                                  /*!< PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP                                        */
  PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP_MCULON = 0,/*!< MCULON : When PD_DISP is on, MCUL is on.                                  */
  PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP_MCULOFF = 1,/*!< MCULOFF : When PD_DISP is on, MCUL is still off.                         */
} PWRCTRL_MMSOVERRIDE_MMSOVRMCULDISP_Enum;

/* ======================================================  DSP0PWRCTRL  ====================================================== */
/* ========================================  PWRCTRL DSP0PWRCTRL DSP0PCMRSTOR [4..4]  ======================================== */
typedef enum {                                  /*!< PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR                                          */
  PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR_EN  = 1,     /*!< EN : Keep DSP0 PCM in Reset                                               */
  PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR_DIS = 0,     /*!< DIS : Remove DSP0 PCM Reset override                                      */
} PWRCTRL_DSP0PWRCTRL_DSP0PCMRSTOR_Enum;

/* ======================================================  DSP0PERFREQ  ====================================================== */
/* =======================================  PWRCTRL DSP0PERFREQ DSP0PERFSTATUS [3..4]  ======================================= */
typedef enum {                                  /*!< PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS                                        */
  PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_ULP = 0,   /*!< ULP : DSP0 is in ULP mode (freq=48MHz)                                    */
  PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_LP = 1,    /*!< LP : DSP0 is in LP mode (freq=192MHz)                                     */
  PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_HP = 2,    /*!< HP : DSP0 is in HP mode (freq=384MHz)                                     */
} PWRCTRL_DSP0PERFREQ_DSP0PERFSTATUS_Enum;

/* ========================================  PWRCTRL DSP0PERFREQ DSP0PERFREQ [0..1]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DSP0PERFREQ_DSP0PERFREQ                                           */
  PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_ULP  = 0,     /*!< ULP : DSP0 to be run in ULP mode (freq=48MHz)                             */
  PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_LP   = 1,     /*!< LP : DSP0 to be run in LP mode (freq=192MHz)                              */
  PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_HP   = 2,     /*!< HP : DSP0 to be run in HP mode (freq=384MHz)                              */
} PWRCTRL_DSP0PERFREQ_DSP0PERFREQ_Enum;

/* =====================================================  DSP0MEMPWREN  ====================================================== */
/* ======================================  PWRCTRL DSP0MEMPWREN PWRENDSP0ICACHE [1..1]  ====================================== */
typedef enum {                                  /*!< PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE                                      */
  PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE_OFF = 0, /*!< OFF : Do not power up ICACHE                                              */
  PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE_ON = 1,  /*!< ON : Power up ICACHE                                                      */
} PWRCTRL_DSP0MEMPWREN_PWRENDSP0ICACHE_Enum;

/* =======================================  PWRCTRL DSP0MEMPWREN PWRENDSP0RAM [0..0]  ======================================== */
typedef enum {                                  /*!< PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM                                         */
  PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM_OFF = 0,    /*!< OFF : Do not power ON any of the IRAM/DRAM                                */
  PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM_ON = 1,     /*!< ON : Power up all IRAM (128K) and DRAM (256K)                             */
} PWRCTRL_DSP0MEMPWREN_PWRENDSP0RAM_Enum;

/* =====================================================  DSP0MEMPWRST  ====================================================== */
/* =====================================================  DSP0MEMRETCFG  ===================================================== */
/* ======================================  PWRCTRL DSP0MEMRETCFG DSP0RAMACTGFX [4..4]  ======================================= */
typedef enum {                                  /*!< PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX                                       */
  PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX_WAKEONDEMAND = 0,/*!< WAKEONDEMAND : Wakeup on demand                                    */
  PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX_ACT = 1,  /*!< ACT : Keep RAMs active irrespective of GFX state                          */
} PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTGFX_Enum;

/* ======================================  PWRCTRL DSP0MEMRETCFG DSP0RAMACTDISP [3..3]  ====================================== */
typedef enum {                                  /*!< PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP                                      */
  PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP_WAKEONDEMAND = 0,/*!< WAKEONDEMAND : Wakeup on demand                                   */
  PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP_ACT = 1, /*!< ACT : Keep RAMs active irrespective of DISP state                         */
} PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTDISP_Enum;

/* =====================================  PWRCTRL DSP0MEMRETCFG ICACHEPWDDSP0OFF [2..2]  ===================================== */
typedef enum {                                  /*!< PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF                                    */
  PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF_RET = 0,/*!< RET : ICACHE retained                                                    */
  PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF_PWD = 1,/*!< PWD : Power down ICACHE                                                  */
} PWRCTRL_DSP0MEMRETCFG_ICACHEPWDDSP0OFF_Enum;

/* ======================================  PWRCTRL DSP0MEMRETCFG DSP0RAMACTMCU [1..1]  ======================================= */
typedef enum {                                  /*!< PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU                                       */
  PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU_WAKEONDEMAND = 0,/*!< WAKEONDEMAND : Wakeup on demand                                    */
  PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU_ACT = 1,  /*!< ACT : Keep RAMs active irrespective of MCU state                          */
} PWRCTRL_DSP0MEMRETCFG_DSP0RAMACTMCU_Enum;

/* ======================================  PWRCTRL DSP0MEMRETCFG RAMPWDDSP0OFF [0..0]  ======================================= */
typedef enum {                                  /*!< PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF                                       */
  PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF_RET = 0,  /*!< RET : IRAM and DRAM retained                                              */
  PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF_PWD = 1,  /*!< PWD : Power down all IRAM and DRAM                                        */
} PWRCTRL_DSP0MEMRETCFG_RAMPWDDSP0OFF_Enum;

/* ======================================================  DSP1PWRCTRL  ====================================================== */
/* ========================================  PWRCTRL DSP1PWRCTRL DSP1PCMRSTOR [4..4]  ======================================== */
typedef enum {                                  /*!< PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR                                          */
  PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR_EN  = 1,     /*!< EN : Keep DSP1 PCM in Reset                                               */
  PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR_DIS = 0,     /*!< DIS : Remove DSP1 PCM Reset override                                      */
} PWRCTRL_DSP1PWRCTRL_DSP1PCMRSTOR_Enum;

/* ======================================================  DSP1PERFREQ  ====================================================== */
/* =======================================  PWRCTRL DSP1PERFREQ DSP1PERFSTATUS [3..4]  ======================================= */
typedef enum {                                  /*!< PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS                                        */
  PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_ULP = 0,   /*!< ULP : DSP1 is in ULP mode (freq=48MHz)                                    */
  PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_LP = 1,    /*!< LP : DSP1 is in LP mode (freq=192MHz)                                     */
  PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_HP = 2,    /*!< HP : DSP1 is in HP mode (freq=384MHz)                                     */
} PWRCTRL_DSP1PERFREQ_DSP1PERFSTATUS_Enum;

/* ========================================  PWRCTRL DSP1PERFREQ DSP1PERFREQ [0..1]  ========================================= */
typedef enum {                                  /*!< PWRCTRL_DSP1PERFREQ_DSP1PERFREQ                                           */
  PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_ULP  = 0,     /*!< ULP : DSP1 to be run in ULP mode (freq=48MHz)                             */
  PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_LP   = 1,     /*!< LP : DSP1 to be run in LP mode (freq=192MHz)                              */
  PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_HP   = 2,     /*!< HP : DSP1 to be run in HP mode (freq=384MHz)                              */
} PWRCTRL_DSP1PERFREQ_DSP1PERFREQ_Enum;

/* =====================================================  DSP1MEMPWREN  ====================================================== */
/* ======================================  PWRCTRL DSP1MEMPWREN PWRENDSP1ICACHE [1..1]  ====================================== */
typedef enum {                                  /*!< PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE                                      */
  PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE_OFF = 0, /*!< OFF : Do not power up ICACHE                                              */
  PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE_ON = 1,  /*!< ON : Power up ICACHE                                                      */
} PWRCTRL_DSP1MEMPWREN_PWRENDSP1ICACHE_Enum;

/* =======================================  PWRCTRL DSP1MEMPWREN PWRENDSP1RAM [0..0]  ======================================== */
typedef enum {                                  /*!< PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM                                         */
  PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM_OFF = 0,    /*!< OFF : Do not power ON any of the IRAM/DRAM                                */
  PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM_ON = 1,     /*!< ON : Power up all IRAM (32K) and DRAM (64K)                               */
} PWRCTRL_DSP1MEMPWREN_PWRENDSP1RAM_Enum;

/* =====================================================  DSP1MEMPWRST  ====================================================== */
/* =====================================================  DSP1MEMRETCFG  ===================================================== */
/* ======================================  PWRCTRL DSP1MEMRETCFG DSP1RAMACTGFX [4..4]  ======================================= */
typedef enum {                                  /*!< PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX                                       */
  PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX_WAKEONDEMAND = 0,/*!< WAKEONDEMAND : Wakeup on demand                                    */
  PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX_ACT = 1,  /*!< ACT : Keep RAMs active irrespective of GFX state                          */
} PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTGFX_Enum;

/* ======================================  PWRCTRL DSP1MEMRETCFG DSP1RAMACTDISP [3..3]  ====================================== */
typedef enum {                                  /*!< PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP                                      */
  PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP_WAKEONDEMAND = 0,/*!< WAKEONDEMAND : Wakeup on demand                                   */
  PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP_ACT = 1, /*!< ACT : Keep RAMs active irrespective of DISP state                         */
} PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTDISP_Enum;

/* =====================================  PWRCTRL DSP1MEMRETCFG ICACHEPWDDSP1OFF [2..2]  ===================================== */
typedef enum {                                  /*!< PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF                                    */
  PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF_RET = 0,/*!< RET : ICACHE retained                                                    */
  PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF_PWD = 1,/*!< PWD : Power down ICACHE                                                  */
} PWRCTRL_DSP1MEMRETCFG_ICACHEPWDDSP1OFF_Enum;

/* ======================================  PWRCTRL DSP1MEMRETCFG DSP1RAMACTMCU [1..1]  ======================================= */
typedef enum {                                  /*!< PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU                                       */
  PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU_WAKEONDEMAND = 0,/*!< WAKEONDEMAND : Wakeup on demand                                    */
  PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU_ACT = 1,  /*!< ACT : Keep RAMs active irrespective of MCU state                          */
} PWRCTRL_DSP1MEMRETCFG_DSP1RAMACTMCU_Enum;

/* ======================================  PWRCTRL DSP1MEMRETCFG RAMPWDDSP1OFF [0..0]  ======================================= */
typedef enum {                                  /*!< PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF                                       */
  PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF_RET = 0,  /*!< RET : IRAM and DRAM retained                                              */
  PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF_PWD = 1,  /*!< PWD : Power down all IRAM and DRAM                                        */
} PWRCTRL_DSP1MEMRETCFG_RAMPWDDSP1OFF_Enum;

/* =======================================================  PWRACKOVR  ======================================================= */
/* =====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEDSPA [17..17]  ===================================== */
typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDSPA                                      */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDSPA_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                          */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDSPA_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
                                                     HW generated power ack                                                    */
} PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDSPA_Enum;

/* ====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEUSBPHY [16..16]  ==================================== */
typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSBPHY                                    */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSBPHY_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                        */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSBPHY_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
                                                     HW generated power ack                                                    */
} PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSBPHY_Enum;

/* =====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEUSB [15..15]  ====================================== */
typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSB                                       */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSB_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                           */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSB_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
                                                     HW generated power ack                                                    */
} PWRCTRL_PWRACKOVR_PWRACKOVERRIDEUSB_Enum;

/* =====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDESDIO [14..14]  ===================================== */
typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDESDIO                                      */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDESDIO_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                          */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDESDIO_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
                                                     HW generated power ack                                                    */
} PWRCTRL_PWRACKOVR_PWRACKOVERRIDESDIO_Enum;

/* =====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEMSPI [13..13]  ===================================== */
typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMSPI                                      */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMSPI_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                          */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMSPI_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
                                                     HW generated power ack                                                    */
} PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMSPI_Enum;

/* =====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEMCUL [12..12]  ===================================== */
typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMCUL                                      */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMCUL_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                          */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMCUL_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
                                                     HW generated power ack                                                    */
} PWRCTRL_PWRACKOVR_PWRACKOVERRIDEMCUL_Enum;

/* =====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEIOS [11..11]  ====================================== */
typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEIOS                                       */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEIOS_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                           */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEIOS_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
                                                     HW generated power ack                                                    */
} PWRCTRL_PWRACKOVR_PWRACKOVERRIDEIOS_Enum;

/* =====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEHCPC [10..10]  ===================================== */
typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPC                                      */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPC_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                          */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPC_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
                                                     HW generated power ack                                                    */
} PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPC_Enum;

/* ======================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEHCPB [9..9]  ====================================== */
typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPB                                      */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPB_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                          */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPB_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
                                                     HW generated power ack                                                    */
} PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPB_Enum;

/* ======================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEHCPA [8..8]  ====================================== */
typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPA                                      */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPA_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                          */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPA_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
                                                     HW generated power ack                                                    */
} PWRCTRL_PWRACKOVR_PWRACKOVERRIDEHCPA_Enum;

/* ======================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEGFX [7..7]  ======================================= */
typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEGFX                                       */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEGFX_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                           */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEGFX_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
                                                     HW generated power ack                                                    */
} PWRCTRL_PWRACKOVR_PWRACKOVERRIDEGFX_Enum;

/* ====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEDISPPHY [6..6]  ===================================== */
typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISPPHY                                   */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISPPHY_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                       */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISPPHY_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
                                                     HW generated power ack                                                    */
} PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISPPHY_Enum;

/* ======================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEDISP [5..5]  ====================================== */
typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISP                                      */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISP_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                          */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISP_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
                                                     HW generated power ack                                                    */
} PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDISP_Enum;

/* ======================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEDBG [4..4]  ======================================= */
typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDBG                                       */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDBG_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                           */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDBG_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
                                                     HW generated power ack                                                    */
} PWRCTRL_PWRACKOVR_PWRACKOVERRIDEDBG_Enum;

/* =====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDECRYPTO [3..3]  ===================================== */
typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDECRYPTO                                    */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDECRYPTO_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                        */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDECRYPTO_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
                                                     HW generated power ack                                                    */
} PWRCTRL_PWRACKOVR_PWRACKOVERRIDECRYPTO_Enum;

/* =====================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEAUDADC [2..2]  ===================================== */
typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUDADC                                    */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUDADC_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                        */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUDADC_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
                                                     HW generated power ack                                                    */
} PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUDADC_Enum;

/* ======================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEAUD [1..1]  ======================================= */
typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUD                                       */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUD_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                           */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUD_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
                                                     HW generated power ack                                                    */
} PWRCTRL_PWRACKOVR_PWRACKOVERRIDEAUD_Enum;

/* ======================================  PWRCTRL PWRACKOVR PWRACKOVERRIDEADC [0..0]  ======================================= */
typedef enum {                                  /*!< PWRCTRL_PWRACKOVR_PWRACKOVERRIDEADC                                       */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEADC_DEFAULT = 0,/*!< DEFAULT : Hardware generates Power switch ack                           */
  PWRCTRL_PWRACKOVR_PWRACKOVERRIDEADC_SWOVRRIDE = 1,/*!< SWOVRRIDE : Software override or defeaure mode. Will bypass
                                                     HW generated power ack                                                    */
} PWRCTRL_PWRACKOVR_PWRACKOVERRIDEADC_Enum;

/* =====================================================  PWRCNTDEFVAL  ====================================================== */
/* ========================================================  VRCTRL  ========================================================= */
/* ===========================================  PWRCTRL VRCTRL SIMOBUCKEN [0..0]  ============================================ */
typedef enum {                                  /*!< PWRCTRL_VRCTRL_SIMOBUCKEN                                                 */
  PWRCTRL_VRCTRL_SIMOBUCKEN_EN         = 1,     /*!< EN : Enable the SIMO Buck                                                 */
  PWRCTRL_VRCTRL_SIMOBUCKEN_DIS        = 0,     /*!< DIS : Disable the SIMO Buck                                               */
} PWRCTRL_VRCTRL_SIMOBUCKEN_Enum;

/* =====================================================  LEGACYVRLPOVR  ===================================================== */
/* =======================================================  VRSTATUS  ======================================================== */
/* ==========================================  PWRCTRL VRSTATUS SIMOBUCKST [4..5]  =========================================== */
typedef enum {                                  /*!< PWRCTRL_VRSTATUS_SIMOBUCKST                                               */
  PWRCTRL_VRSTATUS_SIMOBUCKST_OFF      = 0,     /*!< OFF : Indicates the the SIMO BUCK is OFF.                                 */
  PWRCTRL_VRSTATUS_SIMOBUCKST_LP       = 2,     /*!< LP : Indicates the the SIMO BUCK is ON and in LP mode.                    */
  PWRCTRL_VRSTATUS_SIMOBUCKST_ACT      = 3,     /*!< ACT : Indicates the the SIMO BUCK is ON and in ACT mode.                  */
} PWRCTRL_VRSTATUS_SIMOBUCKST_Enum;

/* ===========================================  PWRCTRL VRSTATUS MEMLDOST [2..3]  ============================================ */
typedef enum {                                  /*!< PWRCTRL_VRSTATUS_MEMLDOST                                                 */
  PWRCTRL_VRSTATUS_MEMLDOST_OFF        = 0,     /*!< OFF : Indicates the the MEMLDO is OFF.                                    */
  PWRCTRL_VRSTATUS_MEMLDOST_LP         = 2,     /*!< LP : Indicates the the MEMLDO is ON and in LP mode.                       */
  PWRCTRL_VRSTATUS_MEMLDOST_ACT        = 3,     /*!< ACT : Indicates the the MEMLDO is ON and in ACT mode.                     */
} PWRCTRL_VRSTATUS_MEMLDOST_Enum;

/* ===========================================  PWRCTRL VRSTATUS CORELDOST [0..1]  =========================================== */
typedef enum {                                  /*!< PWRCTRL_VRSTATUS_CORELDOST                                                */
  PWRCTRL_VRSTATUS_CORELDOST_OFF       = 0,     /*!< OFF : Indicates the the CORELDO is OFF.                                   */
  PWRCTRL_VRSTATUS_CORELDOST_LP        = 2,     /*!< LP : Indicates the the CORELDO is ON and in LP mode.                      */
  PWRCTRL_VRSTATUS_CORELDOST_ACT       = 3,     /*!< ACT : Indicates the the CORELDO is ON and in ACT mode.                    */
} PWRCTRL_VRSTATUS_CORELDOST_Enum;

/* =======================================================  SRAMCTRL  ======================================================== */
/* ========================================  PWRCTRL SRAMCTRL SRAMLIGHTSLEEP [8..19]  ======================================== */
typedef enum {                                  /*!< PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP                                           */
  PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_ALL  = 4095,  /*!< ALL : Enable LIGHT SLEEP for ALL SRAMs                                    */
  PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_DIS  = 0,     /*!< DIS : Disables LIGHT SLEEP for ALL SRAMs                                  */
} PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Enum;

/* =======================================  PWRCTRL SRAMCTRL SRAMMASTERCLKGATE [2..2]  ======================================= */
typedef enum {                                  /*!< PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE                                        */
  PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_EN = 1,    /*!< EN : Enable Master SRAM Clock Gate                                        */
  PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_DIS = 0,   /*!< DIS : Disables Master SRAM Clock Gating                                   */
} PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Enum;

/* ==========================================  PWRCTRL SRAMCTRL SRAMCLKGATE [1..1]  ========================================== */
typedef enum {                                  /*!< PWRCTRL_SRAMCTRL_SRAMCLKGATE                                              */
  PWRCTRL_SRAMCTRL_SRAMCLKGATE_EN      = 1,     /*!< EN : Enable Individual SRAM Clock Gating                                  */
  PWRCTRL_SRAMCTRL_SRAMCLKGATE_DIS     = 0,     /*!< DIS : Disables Individual SRAM Clock Gating                               */
} PWRCTRL_SRAMCTRL_SRAMCLKGATE_Enum;

/* =======================================================  ADCSTATUS  ======================================================= */
/* =====================================================  AUDADCSTATUS  ====================================================== */
/* =======================================================  EMONCTRL  ======================================================== */
/* =======================================================  EMONCFG0  ======================================================== */
/* ===========================================  PWRCTRL EMONCFG0 EMONSEL0 [0..7]  ============================================ */
typedef enum {                                  /*!< PWRCTRL_EMONCFG0_EMONSEL0                                                 */
  PWRCTRL_EMONCFG0_EMONSEL0_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
  PWRCTRL_EMONCFG0_EMONSEL0_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
  PWRCTRL_EMONCFG0_EMONSEL0_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
  PWRCTRL_EMONCFG0_EMONSEL0_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
  PWRCTRL_EMONCFG0_EMONSEL0_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
  PWRCTRL_EMONCFG0_EMONSEL0_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
  PWRCTRL_EMONCFG0_EMONSEL0_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
  PWRCTRL_EMONCFG0_EMONSEL0_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
  PWRCTRL_EMONCFG0_EMONSEL0_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
  PWRCTRL_EMONCFG0_EMONSEL0_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
  PWRCTRL_EMONCFG0_EMONSEL0_PDM0ON     = 10,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
  PWRCTRL_EMONCFG0_EMONSEL0_CRYPTOON   = 11,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
  PWRCTRL_EMONCFG0_EMONSEL0_DBGON      = 12,    /*!< DBGON : Increment the counter when DBG is powered on                      */
  PWRCTRL_EMONCFG0_EMONSEL0_DSPAON     = 13,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
  PWRCTRL_EMONCFG0_EMONSEL0_GFXON      = 14,    /*!< GFXON : Increment the counter when GFX is powered on                      */
  PWRCTRL_EMONCFG0_EMONSEL0_UART0ON    = 15,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
  PWRCTRL_EMONCFG0_EMONSEL0_UART1ON    = 16,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
  PWRCTRL_EMONCFG0_EMONSEL0_UART2ON    = 17,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
  PWRCTRL_EMONCFG0_EMONSEL0_UART3ON    = 18,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
  PWRCTRL_EMONCFG0_EMONSEL0_IOM0ON     = 19,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
  PWRCTRL_EMONCFG0_EMONSEL0_IOM1ON     = 20,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
  PWRCTRL_EMONCFG0_EMONSEL0_IOM2ON     = 21,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
  PWRCTRL_EMONCFG0_EMONSEL0_IOM3ON     = 22,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
  PWRCTRL_EMONCFG0_EMONSEL0_RESERVED23 = 23,    /*!< RESERVED23 : Reserved selection. Operation unknown if selected.           */
  PWRCTRL_EMONCFG0_EMONSEL0_RESERVED24 = 24,    /*!< RESERVED24 : Reserved selection. Operation unknown if selected.           */
  PWRCTRL_EMONCFG0_EMONSEL0_IOM4ON     = 25,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
  PWRCTRL_EMONCFG0_EMONSEL0_IOM5ON     = 26,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
  PWRCTRL_EMONCFG0_EMONSEL0_IOM6ON     = 27,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
  PWRCTRL_EMONCFG0_EMONSEL0_IOM7ON     = 28,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
  PWRCTRL_EMONCFG0_EMONSEL0_IOSON      = 29,    /*!< IOSON : Increment the counter when IOS is powered on                      */
  PWRCTRL_EMONCFG0_EMONSEL0_MSPI0ON    = 30,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
  PWRCTRL_EMONCFG0_EMONSEL0_MSPI1ON    = 31,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
  PWRCTRL_EMONCFG0_EMONSEL0_MSPI2ON    = 32,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
  PWRCTRL_EMONCFG0_EMONSEL0_SDIOON     = 33,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
} PWRCTRL_EMONCFG0_EMONSEL0_Enum;

/* =======================================================  EMONCFG1  ======================================================== */
/* ===========================================  PWRCTRL EMONCFG1 EMONSEL1 [0..7]  ============================================ */
typedef enum {                                  /*!< PWRCTRL_EMONCFG1_EMONSEL1                                                 */
  PWRCTRL_EMONCFG1_EMONSEL1_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
  PWRCTRL_EMONCFG1_EMONSEL1_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
  PWRCTRL_EMONCFG1_EMONSEL1_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
  PWRCTRL_EMONCFG1_EMONSEL1_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
  PWRCTRL_EMONCFG1_EMONSEL1_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
  PWRCTRL_EMONCFG1_EMONSEL1_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
  PWRCTRL_EMONCFG1_EMONSEL1_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
  PWRCTRL_EMONCFG1_EMONSEL1_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
  PWRCTRL_EMONCFG1_EMONSEL1_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
  PWRCTRL_EMONCFG1_EMONSEL1_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
  PWRCTRL_EMONCFG1_EMONSEL1_PDM0ON     = 10,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
  PWRCTRL_EMONCFG1_EMONSEL1_CRYPTOON   = 11,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
  PWRCTRL_EMONCFG1_EMONSEL1_DBGON      = 12,    /*!< DBGON : Increment the counter when DBG is powered on                      */
  PWRCTRL_EMONCFG1_EMONSEL1_DSPAON     = 13,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
  PWRCTRL_EMONCFG1_EMONSEL1_GFXON      = 14,    /*!< GFXON : Increment the counter when GFX is powered on                      */
  PWRCTRL_EMONCFG1_EMONSEL1_UART0ON    = 15,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
  PWRCTRL_EMONCFG1_EMONSEL1_UART1ON    = 16,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
  PWRCTRL_EMONCFG1_EMONSEL1_UART2ON    = 17,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
  PWRCTRL_EMONCFG1_EMONSEL1_UART3ON    = 18,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
  PWRCTRL_EMONCFG1_EMONSEL1_IOM0ON     = 19,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
  PWRCTRL_EMONCFG1_EMONSEL1_IOM1ON     = 20,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
  PWRCTRL_EMONCFG1_EMONSEL1_IOM2ON     = 21,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
  PWRCTRL_EMONCFG1_EMONSEL1_IOM3ON     = 22,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
  PWRCTRL_EMONCFG1_EMONSEL1_RESERVED23 = 23,    /*!< RESERVED23 : Reserved selection. Operation unknown if selected.           */
  PWRCTRL_EMONCFG1_EMONSEL1_RESERVED24 = 24,    /*!< RESERVED24 : Reserved selection. Operation unknown if selected.           */
  PWRCTRL_EMONCFG1_EMONSEL1_IOM4ON     = 25,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
  PWRCTRL_EMONCFG1_EMONSEL1_IOM5ON     = 26,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
  PWRCTRL_EMONCFG1_EMONSEL1_IOM6ON     = 27,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
  PWRCTRL_EMONCFG1_EMONSEL1_IOM7ON     = 28,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
  PWRCTRL_EMONCFG1_EMONSEL1_IOSON      = 29,    /*!< IOSON : Increment the counter when IOS is powered on                      */
  PWRCTRL_EMONCFG1_EMONSEL1_MSPI0ON    = 30,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
  PWRCTRL_EMONCFG1_EMONSEL1_MSPI1ON    = 31,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
  PWRCTRL_EMONCFG1_EMONSEL1_MSPI2ON    = 32,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
  PWRCTRL_EMONCFG1_EMONSEL1_SDIOON     = 33,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
} PWRCTRL_EMONCFG1_EMONSEL1_Enum;

/* =======================================================  EMONCFG2  ======================================================== */
/* ===========================================  PWRCTRL EMONCFG2 EMONSEL2 [0..7]  ============================================ */
typedef enum {                                  /*!< PWRCTRL_EMONCFG2_EMONSEL2                                                 */
  PWRCTRL_EMONCFG2_EMONSEL2_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
  PWRCTRL_EMONCFG2_EMONSEL2_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
  PWRCTRL_EMONCFG2_EMONSEL2_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
  PWRCTRL_EMONCFG2_EMONSEL2_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
  PWRCTRL_EMONCFG2_EMONSEL2_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
  PWRCTRL_EMONCFG2_EMONSEL2_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
  PWRCTRL_EMONCFG2_EMONSEL2_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
  PWRCTRL_EMONCFG2_EMONSEL2_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
  PWRCTRL_EMONCFG2_EMONSEL2_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
  PWRCTRL_EMONCFG2_EMONSEL2_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
  PWRCTRL_EMONCFG2_EMONSEL2_PDM0ON     = 10,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
  PWRCTRL_EMONCFG2_EMONSEL2_CRYPTOON   = 11,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
  PWRCTRL_EMONCFG2_EMONSEL2_DBGON      = 12,    /*!< DBGON : Increment the counter when DBG is powered on                      */
  PWRCTRL_EMONCFG2_EMONSEL2_DSPAON     = 13,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
  PWRCTRL_EMONCFG2_EMONSEL2_GFXON      = 14,    /*!< GFXON : Increment the counter when GFX is powered on                      */
  PWRCTRL_EMONCFG2_EMONSEL2_UART0ON    = 15,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
  PWRCTRL_EMONCFG2_EMONSEL2_UART1ON    = 16,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
  PWRCTRL_EMONCFG2_EMONSEL2_UART2ON    = 17,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
  PWRCTRL_EMONCFG2_EMONSEL2_UART3ON    = 18,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
  PWRCTRL_EMONCFG2_EMONSEL2_IOM0ON     = 19,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
  PWRCTRL_EMONCFG2_EMONSEL2_IOM1ON     = 20,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
  PWRCTRL_EMONCFG2_EMONSEL2_IOM2ON     = 21,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
  PWRCTRL_EMONCFG2_EMONSEL2_IOM3ON     = 22,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
  PWRCTRL_EMONCFG2_EMONSEL2_RESERVED23 = 23,    /*!< RESERVED23 : Reserved selection. Operation unknown if selected.           */
  PWRCTRL_EMONCFG2_EMONSEL2_RESERVED24 = 24,    /*!< RESERVED24 : Reserved selection. Operation unknown if selected.           */
  PWRCTRL_EMONCFG2_EMONSEL2_IOM4ON     = 25,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
  PWRCTRL_EMONCFG2_EMONSEL2_IOM5ON     = 26,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
  PWRCTRL_EMONCFG2_EMONSEL2_IOM6ON     = 27,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
  PWRCTRL_EMONCFG2_EMONSEL2_IOM7ON     = 28,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
  PWRCTRL_EMONCFG2_EMONSEL2_IOSON      = 29,    /*!< IOSON : Increment the counter when IOS is powered on                      */
  PWRCTRL_EMONCFG2_EMONSEL2_MSPI0ON    = 30,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
  PWRCTRL_EMONCFG2_EMONSEL2_MSPI1ON    = 31,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
  PWRCTRL_EMONCFG2_EMONSEL2_MSPI2ON    = 32,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
  PWRCTRL_EMONCFG2_EMONSEL2_SDIOON     = 33,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
} PWRCTRL_EMONCFG2_EMONSEL2_Enum;

/* =======================================================  EMONCFG3  ======================================================== */
/* ===========================================  PWRCTRL EMONCFG3 EMONSEL3 [0..7]  ============================================ */
typedef enum {                                  /*!< PWRCTRL_EMONCFG3_EMONSEL3                                                 */
  PWRCTRL_EMONCFG3_EMONSEL3_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
  PWRCTRL_EMONCFG3_EMONSEL3_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
  PWRCTRL_EMONCFG3_EMONSEL3_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
  PWRCTRL_EMONCFG3_EMONSEL3_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
  PWRCTRL_EMONCFG3_EMONSEL3_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
  PWRCTRL_EMONCFG3_EMONSEL3_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
  PWRCTRL_EMONCFG3_EMONSEL3_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
  PWRCTRL_EMONCFG3_EMONSEL3_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
  PWRCTRL_EMONCFG3_EMONSEL3_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
  PWRCTRL_EMONCFG3_EMONSEL3_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
  PWRCTRL_EMONCFG3_EMONSEL3_PDM0ON     = 10,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
  PWRCTRL_EMONCFG3_EMONSEL3_CRYPTOON   = 11,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
  PWRCTRL_EMONCFG3_EMONSEL3_DBGON      = 12,    /*!< DBGON : Increment the counter when DBG is powered on                      */
  PWRCTRL_EMONCFG3_EMONSEL3_DSPAON     = 13,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
  PWRCTRL_EMONCFG3_EMONSEL3_GFXON      = 14,    /*!< GFXON : Increment the counter when GFX is powered on                      */
  PWRCTRL_EMONCFG3_EMONSEL3_UART0ON    = 15,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
  PWRCTRL_EMONCFG3_EMONSEL3_UART1ON    = 16,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
  PWRCTRL_EMONCFG3_EMONSEL3_UART2ON    = 17,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
  PWRCTRL_EMONCFG3_EMONSEL3_UART3ON    = 18,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
  PWRCTRL_EMONCFG3_EMONSEL3_IOM0ON     = 19,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
  PWRCTRL_EMONCFG3_EMONSEL3_IOM1ON     = 20,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
  PWRCTRL_EMONCFG3_EMONSEL3_IOM2ON     = 21,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
  PWRCTRL_EMONCFG3_EMONSEL3_IOM3ON     = 22,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
  PWRCTRL_EMONCFG3_EMONSEL3_RESERVED23 = 23,    /*!< RESERVED23 : Reserved selection. Operation unknown if selected.           */
  PWRCTRL_EMONCFG3_EMONSEL3_RESERVED24 = 24,    /*!< RESERVED24 : Reserved selection. Operation unknown if selected.           */
  PWRCTRL_EMONCFG3_EMONSEL3_IOM4ON     = 25,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
  PWRCTRL_EMONCFG3_EMONSEL3_IOM5ON     = 26,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
  PWRCTRL_EMONCFG3_EMONSEL3_IOM6ON     = 27,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
  PWRCTRL_EMONCFG3_EMONSEL3_IOM7ON     = 28,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
  PWRCTRL_EMONCFG3_EMONSEL3_IOSON      = 29,    /*!< IOSON : Increment the counter when IOS is powered on                      */
  PWRCTRL_EMONCFG3_EMONSEL3_MSPI0ON    = 30,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
  PWRCTRL_EMONCFG3_EMONSEL3_MSPI1ON    = 31,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
  PWRCTRL_EMONCFG3_EMONSEL3_MSPI2ON    = 32,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
  PWRCTRL_EMONCFG3_EMONSEL3_SDIOON     = 33,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
} PWRCTRL_EMONCFG3_EMONSEL3_Enum;

/* =======================================================  EMONCFG4  ======================================================== */
/* ===========================================  PWRCTRL EMONCFG4 EMONSEL4 [0..7]  ============================================ */
typedef enum {                                  /*!< PWRCTRL_EMONCFG4_EMONSEL4                                                 */
  PWRCTRL_EMONCFG4_EMONSEL4_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
  PWRCTRL_EMONCFG4_EMONSEL4_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
  PWRCTRL_EMONCFG4_EMONSEL4_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
  PWRCTRL_EMONCFG4_EMONSEL4_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
  PWRCTRL_EMONCFG4_EMONSEL4_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
  PWRCTRL_EMONCFG4_EMONSEL4_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
  PWRCTRL_EMONCFG4_EMONSEL4_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
  PWRCTRL_EMONCFG4_EMONSEL4_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
  PWRCTRL_EMONCFG4_EMONSEL4_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
  PWRCTRL_EMONCFG4_EMONSEL4_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
  PWRCTRL_EMONCFG4_EMONSEL4_PDM0ON     = 10,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
  PWRCTRL_EMONCFG4_EMONSEL4_CRYPTOON   = 11,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
  PWRCTRL_EMONCFG4_EMONSEL4_DBGON      = 12,    /*!< DBGON : Increment the counter when DBG is powered on                      */
  PWRCTRL_EMONCFG4_EMONSEL4_DSPAON     = 13,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
  PWRCTRL_EMONCFG4_EMONSEL4_GFXON      = 14,    /*!< GFXON : Increment the counter when GFX is powered on                      */
  PWRCTRL_EMONCFG4_EMONSEL4_UART0ON    = 15,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
  PWRCTRL_EMONCFG4_EMONSEL4_UART1ON    = 16,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
  PWRCTRL_EMONCFG4_EMONSEL4_UART2ON    = 17,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
  PWRCTRL_EMONCFG4_EMONSEL4_UART3ON    = 18,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
  PWRCTRL_EMONCFG4_EMONSEL4_IOM0ON     = 19,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
  PWRCTRL_EMONCFG4_EMONSEL4_IOM1ON     = 20,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
  PWRCTRL_EMONCFG4_EMONSEL4_IOM2ON     = 21,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
  PWRCTRL_EMONCFG4_EMONSEL4_IOM3ON     = 22,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
  PWRCTRL_EMONCFG4_EMONSEL4_RESERVED23 = 23,    /*!< RESERVED23 : Reserved selection. Operation unknown if selected.           */
  PWRCTRL_EMONCFG4_EMONSEL4_RESERVED24 = 24,    /*!< RESERVED24 : Reserved selection. Operation unknown if selected.           */
  PWRCTRL_EMONCFG4_EMONSEL4_IOM4ON     = 25,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
  PWRCTRL_EMONCFG4_EMONSEL4_IOM5ON     = 26,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
  PWRCTRL_EMONCFG4_EMONSEL4_IOM6ON     = 27,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
  PWRCTRL_EMONCFG4_EMONSEL4_IOM7ON     = 28,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
  PWRCTRL_EMONCFG4_EMONSEL4_IOSON      = 29,    /*!< IOSON : Increment the counter when IOS is powered on                      */
  PWRCTRL_EMONCFG4_EMONSEL4_MSPI0ON    = 30,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
  PWRCTRL_EMONCFG4_EMONSEL4_MSPI1ON    = 31,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
  PWRCTRL_EMONCFG4_EMONSEL4_MSPI2ON    = 32,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
  PWRCTRL_EMONCFG4_EMONSEL4_SDIOON     = 33,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
} PWRCTRL_EMONCFG4_EMONSEL4_Enum;

/* =======================================================  EMONCFG5  ======================================================== */
/* ===========================================  PWRCTRL EMONCFG5 EMONSEL5 [0..7]  ============================================ */
typedef enum {                                  /*!< PWRCTRL_EMONCFG5_EMONSEL5                                                 */
  PWRCTRL_EMONCFG5_EMONSEL5_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
  PWRCTRL_EMONCFG5_EMONSEL5_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
  PWRCTRL_EMONCFG5_EMONSEL5_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
  PWRCTRL_EMONCFG5_EMONSEL5_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
  PWRCTRL_EMONCFG5_EMONSEL5_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
  PWRCTRL_EMONCFG5_EMONSEL5_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
  PWRCTRL_EMONCFG5_EMONSEL5_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
  PWRCTRL_EMONCFG5_EMONSEL5_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
  PWRCTRL_EMONCFG5_EMONSEL5_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
  PWRCTRL_EMONCFG5_EMONSEL5_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
  PWRCTRL_EMONCFG5_EMONSEL5_PDM0ON     = 10,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
  PWRCTRL_EMONCFG5_EMONSEL5_CRYPTOON   = 11,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
  PWRCTRL_EMONCFG5_EMONSEL5_DBGON      = 12,    /*!< DBGON : Increment the counter when DBG is powered on                      */
  PWRCTRL_EMONCFG5_EMONSEL5_DSPAON     = 13,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
  PWRCTRL_EMONCFG5_EMONSEL5_GFXON      = 14,    /*!< GFXON : Increment the counter when GFX is powered on                      */
  PWRCTRL_EMONCFG5_EMONSEL5_UART0ON    = 15,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
  PWRCTRL_EMONCFG5_EMONSEL5_UART1ON    = 16,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
  PWRCTRL_EMONCFG5_EMONSEL5_UART2ON    = 17,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
  PWRCTRL_EMONCFG5_EMONSEL5_UART3ON    = 18,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
  PWRCTRL_EMONCFG5_EMONSEL5_IOM0ON     = 19,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
  PWRCTRL_EMONCFG5_EMONSEL5_IOM1ON     = 20,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
  PWRCTRL_EMONCFG5_EMONSEL5_IOM2ON     = 21,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
  PWRCTRL_EMONCFG5_EMONSEL5_IOM3ON     = 22,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
  PWRCTRL_EMONCFG5_EMONSEL5_RESERVED23 = 23,    /*!< RESERVED23 : Reserved selection. Operation unknown if selected.           */
  PWRCTRL_EMONCFG5_EMONSEL5_RESERVED24 = 24,    /*!< RESERVED24 : Reserved selection. Operation unknown if selected.           */
  PWRCTRL_EMONCFG5_EMONSEL5_IOM4ON     = 25,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
  PWRCTRL_EMONCFG5_EMONSEL5_IOM5ON     = 26,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
  PWRCTRL_EMONCFG5_EMONSEL5_IOM6ON     = 27,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
  PWRCTRL_EMONCFG5_EMONSEL5_IOM7ON     = 28,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
  PWRCTRL_EMONCFG5_EMONSEL5_IOSON      = 29,    /*!< IOSON : Increment the counter when IOS is powered on                      */
  PWRCTRL_EMONCFG5_EMONSEL5_MSPI0ON    = 30,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
  PWRCTRL_EMONCFG5_EMONSEL5_MSPI1ON    = 31,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
  PWRCTRL_EMONCFG5_EMONSEL5_MSPI2ON    = 32,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
  PWRCTRL_EMONCFG5_EMONSEL5_SDIOON     = 33,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
} PWRCTRL_EMONCFG5_EMONSEL5_Enum;

/* =======================================================  EMONCFG6  ======================================================== */
/* ===========================================  PWRCTRL EMONCFG6 EMONSEL6 [0..7]  ============================================ */
typedef enum {                                  /*!< PWRCTRL_EMONCFG6_EMONSEL6                                                 */
  PWRCTRL_EMONCFG6_EMONSEL6_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
  PWRCTRL_EMONCFG6_EMONSEL6_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
  PWRCTRL_EMONCFG6_EMONSEL6_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
  PWRCTRL_EMONCFG6_EMONSEL6_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
  PWRCTRL_EMONCFG6_EMONSEL6_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
  PWRCTRL_EMONCFG6_EMONSEL6_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
  PWRCTRL_EMONCFG6_EMONSEL6_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
  PWRCTRL_EMONCFG6_EMONSEL6_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
  PWRCTRL_EMONCFG6_EMONSEL6_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
  PWRCTRL_EMONCFG6_EMONSEL6_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
  PWRCTRL_EMONCFG6_EMONSEL6_PDM0ON     = 10,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
  PWRCTRL_EMONCFG6_EMONSEL6_CRYPTOON   = 11,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
  PWRCTRL_EMONCFG6_EMONSEL6_DBGON      = 12,    /*!< DBGON : Increment the counter when DBG is powered on                      */
  PWRCTRL_EMONCFG6_EMONSEL6_DSPAON     = 13,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
  PWRCTRL_EMONCFG6_EMONSEL6_GFXON      = 14,    /*!< GFXON : Increment the counter when GFX is powered on                      */
  PWRCTRL_EMONCFG6_EMONSEL6_UART0ON    = 15,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
  PWRCTRL_EMONCFG6_EMONSEL6_UART1ON    = 16,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
  PWRCTRL_EMONCFG6_EMONSEL6_UART2ON    = 17,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
  PWRCTRL_EMONCFG6_EMONSEL6_UART3ON    = 18,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
  PWRCTRL_EMONCFG6_EMONSEL6_IOM0ON     = 19,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
  PWRCTRL_EMONCFG6_EMONSEL6_IOM1ON     = 20,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
  PWRCTRL_EMONCFG6_EMONSEL6_IOM2ON     = 21,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
  PWRCTRL_EMONCFG6_EMONSEL6_IOM3ON     = 22,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
  PWRCTRL_EMONCFG6_EMONSEL6_RESERVED23 = 23,    /*!< RESERVED23 : Reserved selection. Operation unknown if selected.           */
  PWRCTRL_EMONCFG6_EMONSEL6_RESERVED24 = 24,    /*!< RESERVED24 : Reserved selection. Operation unknown if selected.           */
  PWRCTRL_EMONCFG6_EMONSEL6_IOM4ON     = 25,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
  PWRCTRL_EMONCFG6_EMONSEL6_IOM5ON     = 26,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
  PWRCTRL_EMONCFG6_EMONSEL6_IOM6ON     = 27,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
  PWRCTRL_EMONCFG6_EMONSEL6_IOM7ON     = 28,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
  PWRCTRL_EMONCFG6_EMONSEL6_IOSON      = 29,    /*!< IOSON : Increment the counter when IOS is powered on                      */
  PWRCTRL_EMONCFG6_EMONSEL6_MSPI0ON    = 30,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
  PWRCTRL_EMONCFG6_EMONSEL6_MSPI1ON    = 31,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
  PWRCTRL_EMONCFG6_EMONSEL6_MSPI2ON    = 32,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
  PWRCTRL_EMONCFG6_EMONSEL6_SDIOON     = 33,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
} PWRCTRL_EMONCFG6_EMONSEL6_Enum;

/* =======================================================  EMONCFG7  ======================================================== */
/* ===========================================  PWRCTRL EMONCFG7 EMONSEL7 [0..7]  ============================================ */
typedef enum {                                  /*!< PWRCTRL_EMONCFG7_EMONSEL7                                                 */
  PWRCTRL_EMONCFG7_EMONSEL7_NEVER      = 0,     /*!< NEVER : Never increment the counter                                       */
  PWRCTRL_EMONCFG7_EMONSEL7_ALWAYS     = 1,     /*!< ALWAYS : Always increment the counter                                     */
  PWRCTRL_EMONCFG7_EMONSEL7_MCUSLEEP   = 2,     /*!< MCUSLEEP : Increment the counter for MCU sleep mode                       */
  PWRCTRL_EMONCFG7_EMONSEL7_MCUDEEPSLEEP = 3,   /*!< MCUDEEPSLEEP : Increment the counter for MCU deepsleep mode               */
  PWRCTRL_EMONCFG7_EMONSEL7_DSP0ON     = 4,     /*!< DSP0ON : Increment the counter for DSP0 active mode                       */
  PWRCTRL_EMONCFG7_EMONSEL7_DSP1ON     = 5,     /*!< DSP1ON : Increment the counter for DSP1 active mode                       */
  PWRCTRL_EMONCFG7_EMONSEL7_ADCON      = 6,     /*!< ADCON : Increment the counter when ADC is powered on                      */
  PWRCTRL_EMONCFG7_EMONSEL7_AUDPBON    = 7,     /*!< AUDPBON : Increment the counter when AUDPB is powered on                  */
  PWRCTRL_EMONCFG7_EMONSEL7_AUDRECON   = 8,     /*!< AUDRECON : Increment the counter when AUDREC is powered on                */
  PWRCTRL_EMONCFG7_EMONSEL7_I2S0ON     = 9,     /*!< I2S0ON : Increment the counter when I2S0 is powered on                    */
  PWRCTRL_EMONCFG7_EMONSEL7_PDM0ON     = 10,    /*!< PDM0ON : Increment the counter when PDM0 is powered on                    */
  PWRCTRL_EMONCFG7_EMONSEL7_CRYPTOON   = 11,    /*!< CRYPTOON : Increment the counter when CRYPTO is powered on                */
  PWRCTRL_EMONCFG7_EMONSEL7_DBGON      = 12,    /*!< DBGON : Increment the counter when DBG is powered on                      */
  PWRCTRL_EMONCFG7_EMONSEL7_DSPAON     = 13,    /*!< DSPAON : Increment the counter when DSPA is powered on                    */
  PWRCTRL_EMONCFG7_EMONSEL7_GFXON      = 14,    /*!< GFXON : Increment the counter when GFX is powered on                      */
  PWRCTRL_EMONCFG7_EMONSEL7_UART0ON    = 15,    /*!< UART0ON : Increment the counter when UART0 is powered on                  */
  PWRCTRL_EMONCFG7_EMONSEL7_UART1ON    = 16,    /*!< UART1ON : Increment the counter when UART1 is powered on                  */
  PWRCTRL_EMONCFG7_EMONSEL7_UART2ON    = 17,    /*!< UART2ON : Increment the counter when UART2 is powered on                  */
  PWRCTRL_EMONCFG7_EMONSEL7_UART3ON    = 18,    /*!< UART3ON : Increment the counter when UART3 is powered on                  */
  PWRCTRL_EMONCFG7_EMONSEL7_IOM0ON     = 19,    /*!< IOM0ON : Increment the counter when IOM0 is powered on                    */
  PWRCTRL_EMONCFG7_EMONSEL7_IOM1ON     = 20,    /*!< IOM1ON : Increment the counter when IOM1 is powered on                    */
  PWRCTRL_EMONCFG7_EMONSEL7_IOM2ON     = 21,    /*!< IOM2ON : Increment the counter when IOM2 is powered on                    */
  PWRCTRL_EMONCFG7_EMONSEL7_IOM3ON     = 22,    /*!< IOM3ON : Increment the counter when IOM3 is powered on                    */
  PWRCTRL_EMONCFG7_EMONSEL7_RESERVED23 = 23,    /*!< RESERVED23 : Reserved selection. Operation unknown if selected.           */
  PWRCTRL_EMONCFG7_EMONSEL7_RESERVED24 = 24,    /*!< RESERVED24 : Reserved selection. Operation unknown if selected.           */
  PWRCTRL_EMONCFG7_EMONSEL7_IOM4ON     = 25,    /*!< IOM4ON : Increment the counter when IOM4 is powered on                    */
  PWRCTRL_EMONCFG7_EMONSEL7_IOM5ON     = 26,    /*!< IOM5ON : Increment the counter when IOM5 is powered on                    */
  PWRCTRL_EMONCFG7_EMONSEL7_IOM6ON     = 27,    /*!< IOM6ON : Increment the counter when IOM6 is powered on                    */
  PWRCTRL_EMONCFG7_EMONSEL7_IOM7ON     = 28,    /*!< IOM7ON : Increment the counter when IOM7 is powered on                    */
  PWRCTRL_EMONCFG7_EMONSEL7_IOSON      = 29,    /*!< IOSON : Increment the counter when IOS is powered on                      */
  PWRCTRL_EMONCFG7_EMONSEL7_MSPI0ON    = 30,    /*!< MSPI0ON : Increment the counter when MSPI0 is powered on                  */
  PWRCTRL_EMONCFG7_EMONSEL7_MSPI1ON    = 31,    /*!< MSPI1ON : Increment the counter when MSPI1 is powered on                  */
  PWRCTRL_EMONCFG7_EMONSEL7_MSPI2ON    = 32,    /*!< MSPI2ON : Increment the counter when MSPI2 is powered on                  */
  PWRCTRL_EMONCFG7_EMONSEL7_SDIOON     = 33,    /*!< SDIOON : Increment the counter when SDIO is powered on                    */
} PWRCTRL_EMONCFG7_EMONSEL7_Enum;

/* ======================================================  EMONCOUNT0  ======================================================= */
/* ======================================================  EMONCOUNT1  ======================================================= */
/* ======================================================  EMONCOUNT2  ======================================================= */
/* ======================================================  EMONCOUNT3  ======================================================= */
/* ======================================================  EMONCOUNT4  ======================================================= */
/* ======================================================  EMONCOUNT5  ======================================================= */
/* ======================================================  EMONCOUNT6  ======================================================= */
/* ======================================================  EMONCOUNT7  ======================================================= */
/* ======================================================  EMONSTATUS  ======================================================= */


/* =========================================================================================================================== */
/* ================                                          RSTGEN                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  CFG  ========================================================== */
/* =========================================================  SWPOI  ========================================================= */
/* =============================================  RSTGEN SWPOI SWPOIKEY [0..7]  ============================================== */
typedef enum {                                  /*!< RSTGEN_SWPOI_SWPOIKEY                                                     */
  RSTGEN_SWPOI_SWPOIKEY_KEYVALUE       = 27,    /*!< KEYVALUE : Writing 0x1B key value generates a software POI reset.         */
  RSTGEN_SWPOI_SWPOIKEY_DEFAULT        = 0,     /*!< DEFAULT : Default value.                                                  */
} RSTGEN_SWPOI_SWPOIKEY_Enum;

/* =========================================================  SWPOR  ========================================================= */
/* =============================================  RSTGEN SWPOR SWPORKEY [0..7]  ============================================== */
typedef enum {                                  /*!< RSTGEN_SWPOR_SWPORKEY                                                     */
  RSTGEN_SWPOR_SWPORKEY_KEYVALUE       = 212,   /*!< KEYVALUE : Writing 0xD4 key value generates a software POR reset.         */
  RSTGEN_SWPOR_SWPORKEY_DEFAULT        = 0,     /*!< DEFAULT : Default value.                                                  */
} RSTGEN_SWPOR_SWPORKEY_Enum;

/* =======================================================  SIMOBODM  ======================================================== */
/* ===========================================  RSTGEN SIMOBODM DIGBOECLV [3..3]  ============================================ */
typedef enum {                                  /*!< RSTGEN_SIMOBODM_DIGBOECLV                                                 */
  RSTGEN_SIMOBODM_DIGBOECLV_BOM        = 0,     /*!< BOM : Mask the VDDC_LV digital brownout detection into the interrupt
                                                     block.                                                                    */
  RSTGEN_SIMOBODM_DIGBOECLV_BOE        = 1,     /*!< BOE : Enable brown VDDC_LV digital brownout detection into the
                                                     interrupt block.                                                          */
} RSTGEN_SIMOBODM_DIGBOECLV_Enum;

/* ============================================  RSTGEN SIMOBODM DIGBOES [2..2]  ============================================= */
typedef enum {                                  /*!< RSTGEN_SIMOBODM_DIGBOES                                                   */
  RSTGEN_SIMOBODM_DIGBOES_BOM          = 0,     /*!< BOM : Mask the VDDS digital brownout detection into the interrupt
                                                     block.                                                                    */
  RSTGEN_SIMOBODM_DIGBOES_BOE          = 1,     /*!< BOE : Enable the VDDS digital brownout detection into the interrupt
                                                     block.                                                                    */
} RSTGEN_SIMOBODM_DIGBOES_Enum;

/* ============================================  RSTGEN SIMOBODM DIGBOEF [1..1]  ============================================= */
typedef enum {                                  /*!< RSTGEN_SIMOBODM_DIGBOEF                                                   */
  RSTGEN_SIMOBODM_DIGBOEF_BOM          = 0,     /*!< BOM : Mask the VDDF digital brownout detection into the interrupt
                                                     block.                                                                    */
  RSTGEN_SIMOBODM_DIGBOEF_BOE          = 1,     /*!< BOE : Enable the VDDF digital brownout detection into the interrupt
                                                     block.                                                                    */
} RSTGEN_SIMOBODM_DIGBOEF_Enum;

/* ============================================  RSTGEN SIMOBODM DIGBOEC [0..0]  ============================================= */
typedef enum {                                  /*!< RSTGEN_SIMOBODM_DIGBOEC                                                   */
  RSTGEN_SIMOBODM_DIGBOEC_BOA          = 0,     /*!< BOA : Enable brown out detection for VDDF using the analog method.        */
  RSTGEN_SIMOBODM_DIGBOEC_BOD          = 1,     /*!< BOD : Enable brown out detection for VDDF using the digital
                                                     method.                                                                   */
} RSTGEN_SIMOBODM_DIGBOEC_Enum;

/* =========================================================  INTEN  ========================================================= */
/* ========================================================  INTSTAT  ======================================================== */
/* ========================================================  INTCLR  ========================================================= */
/* ========================================================  INTSET  ========================================================= */
/* =========================================================  STAT  ========================================================== */


/* =========================================================================================================================== */
/* ================                                            RTC                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  RTCCTL  ========================================================= */
/* ===============================================  RTC RTCCTL HR1224 [5..5]  ================================================ */
typedef enum {                                  /*!< RTC_RTCCTL_HR1224                                                         */
  RTC_RTCCTL_HR1224_24HR               = 0,     /*!< 24HR : Hours in 24 hour mode                                              */
  RTC_RTCCTL_HR1224_DISABLED           = 1,     /*!< DISABLED : Disable the 24 hour mode                                       */
} RTC_RTCCTL_HR1224_Enum;

/* ================================================  RTC RTCCTL RSTOP [4..4]  ================================================ */
typedef enum {                                  /*!< RTC_RTCCTL_RSTOP                                                          */
  RTC_RTCCTL_RSTOP_RUN                 = 0,     /*!< RUN : Allow the RTC input clock to run                                    */
  RTC_RTCCTL_RSTOP_STOP                = 1,     /*!< STOP : Stop the RTC input clock                                           */
} RTC_RTCCTL_RSTOP_Enum;

/* =================================================  RTC RTCCTL RPT [1..3]  ================================================= */
typedef enum {                                  /*!< RTC_RTCCTL_RPT                                                            */
  RTC_RTCCTL_RPT_DIS                   = 0,     /*!< DIS : Alarm interrupt disabled                                            */
  RTC_RTCCTL_RPT_YEAR                  = 1,     /*!< YEAR : Interrupt every year                                               */
  RTC_RTCCTL_RPT_MONTH                 = 2,     /*!< MONTH : Interrupt every month                                             */
  RTC_RTCCTL_RPT_WEEK                  = 3,     /*!< WEEK : Interrupt every week                                               */
  RTC_RTCCTL_RPT_DAY                   = 4,     /*!< DAY : Interrupt every day                                                 */
  RTC_RTCCTL_RPT_HR                    = 5,     /*!< HR : Interrupt every hour                                                 */
  RTC_RTCCTL_RPT_MIN                   = 6,     /*!< MIN : Interrupt every minute                                              */
  RTC_RTCCTL_RPT_SEC                   = 7,     /*!< SEC : Interrupt every second/10th/100th                                   */
} RTC_RTCCTL_RPT_Enum;

/* ================================================  RTC RTCCTL WRTC [0..0]  ================================================= */
typedef enum {                                  /*!< RTC_RTCCTL_WRTC                                                           */
  RTC_RTCCTL_WRTC_DIS                  = 0,     /*!< DIS : Counter writes are disabled                                         */
  RTC_RTCCTL_WRTC_EN                   = 1,     /*!< EN : Counter writes are enabled                                           */
} RTC_RTCCTL_WRTC_Enum;

/* ========================================================  RTCSTAT  ======================================================== */
/* ========================================================  CTRLOW  ========================================================= */
/* =========================================================  CTRUP  ========================================================= */
/* ===============================================  RTC CTRUP CTERR [31..31]  ================================================ */
typedef enum {                                  /*!< RTC_CTRUP_CTERR                                                           */
  RTC_CTRUP_CTERR_NOERR                = 0,     /*!< NOERR : No read error occurred                                            */
  RTC_CTRUP_CTERR_RDERR                = 1,     /*!< RDERR : Read error occurred                                               */
} RTC_CTRUP_CTERR_Enum;

/* =================================================  RTC CTRUP CB [28..28]  ================================================= */
typedef enum {                                  /*!< RTC_CTRUP_CB                                                              */
  RTC_CTRUP_CB_2100                    = 0,     /*!< 2100 : Century is 2100s                                                   */
  RTC_CTRUP_CB_2000                    = 1,     /*!< 2000 : Century is 2000s                                                   */
} RTC_CTRUP_CB_Enum;

/* ========================================================  ALMLOW  ========================================================= */
/* =========================================================  ALMUP  ========================================================= */
/* =========================================================  INTEN  ========================================================= */
/* ========================================================  INTSTAT  ======================================================== */
/* ========================================================  INTCLR  ========================================================= */
/* ========================================================  INTSET  ========================================================= */


/* =========================================================================================================================== */
/* ================                                           SDIO                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  SDMA  ========================================================== */
/* =========================================================  BLOCK  ========================================================= */
/* ==============================================  SDIO BLOCK BLKCNT [16..31]  =============================================== */
typedef enum {                                  /*!< SDIO_BLOCK_BLKCNT                                                         */
  SDIO_BLOCK_BLKCNT_STOPCNT            = 0,     /*!< STOPCNT : Stop Count                                                      */
  SDIO_BLOCK_BLKCNT_1BLOCK             = 1,     /*!< 1BLOCK : 1 block                                                          */
  SDIO_BLOCK_BLKCNT_2BLOCKS            = 2,     /*!< 2BLOCKS : 2 blocks (and so on from 1-65535)                               */
  SDIO_BLOCK_BLKCNT_65535BLOCKS        = 65535, /*!< 65535BLOCKS : 65535 blocks                                                */
} SDIO_BLOCK_BLKCNT_Enum;

/* ===========================================  SDIO BLOCK HOSTSDMABUFSZ [12..14]  =========================================== */
typedef enum {                                  /*!< SDIO_BLOCK_HOSTSDMABUFSZ                                                  */
  SDIO_BLOCK_HOSTSDMABUFSZ_4KB         = 0,     /*!< 4KB : 4KB(Detects A11 Carry out)                                          */
  SDIO_BLOCK_HOSTSDMABUFSZ_8KB         = 1,     /*!< 8KB : 8KB(Detects A12 Carry out)                                          */
  SDIO_BLOCK_HOSTSDMABUFSZ_16KB        = 2,     /*!< 16KB : 16KB(Detects A13 Carry out)                                        */
  SDIO_BLOCK_HOSTSDMABUFSZ_32KB        = 3,     /*!< 32KB : 32KB(Detects A14 Carry out)                                        */
  SDIO_BLOCK_HOSTSDMABUFSZ_64KB        = 4,     /*!< 64KB : 64KB(Detects A15 Carry out)                                        */
  SDIO_BLOCK_HOSTSDMABUFSZ_128KB       = 5,     /*!< 128KB : 128KB(Detects A16 Carry out)                                      */
  SDIO_BLOCK_HOSTSDMABUFSZ_256KB       = 6,     /*!< 256KB : 256KB(Detects A17 Carry out)                                      */
  SDIO_BLOCK_HOSTSDMABUFSZ_512KB       = 7,     /*!< 512KB : 512KB(Detects A18 Carry out)                                      */
} SDIO_BLOCK_HOSTSDMABUFSZ_Enum;

/* =========================================  SDIO BLOCK TRANSFERBLOCKSIZE [0..11]  ========================================== */
typedef enum {                                  /*!< SDIO_BLOCK_TRANSFERBLOCKSIZE                                              */
  SDIO_BLOCK_TRANSFERBLOCKSIZE_NODATAXFER = 0,  /*!< NODATAXFER : No Data Transfer                                             */
  SDIO_BLOCK_TRANSFERBLOCKSIZE_1BYTE   = 1,     /*!< 1BYTE : 1 Byte                                                            */
  SDIO_BLOCK_TRANSFERBLOCKSIZE_2BYTES  = 2,     /*!< 2BYTES : 2 Bytes                                                          */
  SDIO_BLOCK_TRANSFERBLOCKSIZE_3BYTES  = 3,     /*!< 3BYTES : 3 Bytes                                                          */
  SDIO_BLOCK_TRANSFERBLOCKSIZE_4BYTES  = 4,     /*!< 4BYTES : 4 Bytes (and so on from 1-2048)                                  */
  SDIO_BLOCK_TRANSFERBLOCKSIZE_511BYTES = 511,  /*!< 511BYTES : 511 Bytes                                                      */
  SDIO_BLOCK_TRANSFERBLOCKSIZE_512BYTES = 512,  /*!< 512BYTES : 512 Bytes                                                      */
  SDIO_BLOCK_TRANSFERBLOCKSIZE_2048BYTES = 2048,/*!< 2048BYTES : 2048 Bytes                                                    */
} SDIO_BLOCK_TRANSFERBLOCKSIZE_Enum;

/* =======================================================  ARGUMENT1  ======================================================= */
/* =======================================================  TRANSFER  ======================================================== */
/* ============================================  SDIO TRANSFER CMDTYPE [22..23]  ============================================= */
typedef enum {                                  /*!< SDIO_TRANSFER_CMDTYPE                                                     */
  SDIO_TRANSFER_CMDTYPE_NORMAL         = 0,     /*!< NORMAL : Normal                                                           */
  SDIO_TRANSFER_CMDTYPE_SUSPEND        = 1,     /*!< SUSPEND : Suspend                                                         */
  SDIO_TRANSFER_CMDTYPE_RESUME         = 2,     /*!< RESUME : Resume                                                           */
  SDIO_TRANSFER_CMDTYPE_ABORT          = 3,     /*!< ABORT : Abort                                                             */
} SDIO_TRANSFER_CMDTYPE_Enum;

/* ==========================================  SDIO TRANSFER DATAPRSNTSEL [21..21]  ========================================== */
typedef enum {                                  /*!< SDIO_TRANSFER_DATAPRSNTSEL                                                */
  SDIO_TRANSFER_DATAPRSNTSEL_NODATAPRESENT = 0, /*!< NODATAPRESENT : No Data Present                                           */
  SDIO_TRANSFER_DATAPRSNTSEL_DATAPRESENT = 1,   /*!< DATAPRESENT : Data Present                                                */
} SDIO_TRANSFER_DATAPRSNTSEL_Enum;

/* ==========================================  SDIO TRANSFER CMDIDXCHKEN [20..20]  =========================================== */
typedef enum {                                  /*!< SDIO_TRANSFER_CMDIDXCHKEN                                                 */
  SDIO_TRANSFER_CMDIDXCHKEN_DISABLE    = 0,     /*!< DISABLE : Disable                                                         */
  SDIO_TRANSFER_CMDIDXCHKEN_ENABLE     = 1,     /*!< ENABLE : Enable                                                           */
} SDIO_TRANSFER_CMDIDXCHKEN_Enum;

/* ==========================================  SDIO TRANSFER CMDCRCCHKEN [19..19]  =========================================== */
typedef enum {                                  /*!< SDIO_TRANSFER_CMDCRCCHKEN                                                 */
  SDIO_TRANSFER_CMDCRCCHKEN_DISABLE    = 0,     /*!< DISABLE : Disable                                                         */
  SDIO_TRANSFER_CMDCRCCHKEN_ENABLE     = 1,     /*!< ENABLE : Enable                                                           */
} SDIO_TRANSFER_CMDCRCCHKEN_Enum;

/* ==========================================  SDIO TRANSFER RESPTYPESEL [16..17]  =========================================== */
typedef enum {                                  /*!< SDIO_TRANSFER_RESPTYPESEL                                                 */
  SDIO_TRANSFER_RESPTYPESEL_NORESPONSE = 0,     /*!< NORESPONSE : No Response                                                  */
  SDIO_TRANSFER_RESPTYPESEL_LEN136     = 1,     /*!< LEN136 : Response length 136                                              */
  SDIO_TRANSFER_RESPTYPESEL_LEN48      = 2,     /*!< LEN48 : Response length 48                                                */
  SDIO_TRANSFER_RESPTYPESEL_LEN48CHKBUSY = 3,   /*!< LEN48CHKBUSY : Response length 48 check Busy after response               */
} SDIO_TRANSFER_RESPTYPESEL_Enum;

/* ==============================================  SDIO TRANSFER BLKSEL [5..5]  ============================================== */
typedef enum {                                  /*!< SDIO_TRANSFER_BLKSEL                                                      */
  SDIO_TRANSFER_BLKSEL_SINGLEBLOCK     = 0,     /*!< SINGLEBLOCK : Single Block                                                */
  SDIO_TRANSFER_BLKSEL_MULTIPLEBLOCK   = 1,     /*!< MULTIPLEBLOCK : Multiple Block                                            */
} SDIO_TRANSFER_BLKSEL_Enum;

/* ===========================================  SDIO TRANSFER DXFERDIRSEL [4..4]  ============================================ */
typedef enum {                                  /*!< SDIO_TRANSFER_DXFERDIRSEL                                                 */
  SDIO_TRANSFER_DXFERDIRSEL_WRITE      = 0,     /*!< WRITE : Write (Host to Card)                                              */
  SDIO_TRANSFER_DXFERDIRSEL_READ       = 1,     /*!< READ : Read (Card to Host)                                                */
} SDIO_TRANSFER_DXFERDIRSEL_Enum;

/* ==============================================  SDIO TRANSFER ACMDEN [2..3]  ============================================== */
typedef enum {                                  /*!< SDIO_TRANSFER_ACMDEN                                                      */
  SDIO_TRANSFER_ACMDEN_DISABLED        = 0,     /*!< DISABLED : Auto Command Disabled                                          */
  SDIO_TRANSFER_ACMDEN_CMD12ENABLE     = 1,     /*!< CMD12ENABLE : Auto CMD12 Enable                                           */
  SDIO_TRANSFER_ACMDEN_CMD23ENABLE     = 2,     /*!< CMD23ENABLE : Auto CMD23 Enable                                           */
} SDIO_TRANSFER_ACMDEN_Enum;

/* =============================================  SDIO TRANSFER BLKCNTEN [1..1]  ============================================= */
typedef enum {                                  /*!< SDIO_TRANSFER_BLKCNTEN                                                    */
  SDIO_TRANSFER_BLKCNTEN_DISABLE       = 0,     /*!< DISABLE : Disable                                                         */
  SDIO_TRANSFER_BLKCNTEN_ENABLE        = 1,     /*!< ENABLE : Enable                                                           */
} SDIO_TRANSFER_BLKCNTEN_Enum;

/* ==============================================  SDIO TRANSFER DMAEN [0..0]  =============================================== */
typedef enum {                                  /*!< SDIO_TRANSFER_DMAEN                                                       */
  SDIO_TRANSFER_DMAEN_DISABLE          = 0,     /*!< DISABLE : Disable                                                         */
  SDIO_TRANSFER_DMAEN_ENABLE           = 1,     /*!< ENABLE : Enable                                                           */
} SDIO_TRANSFER_DMAEN_Enum;

/* =======================================================  RESPONSE0  ======================================================= */
/* =======================================================  RESPONSE1  ======================================================= */
/* =======================================================  RESPONSE2  ======================================================= */
/* =======================================================  RESPONSE3  ======================================================= */
/* ========================================================  BUFFER  ========================================================= */
/* ========================================================  PRESENT  ======================================================== */
/* ============================================  SDIO PRESENT DAT74LINE [25..28]  ============================================ */
typedef enum {                                  /*!< SDIO_PRESENT_DAT74LINE                                                    */
  SDIO_PRESENT_DAT74LINE_DAT7          = 8,     /*!< DAT7 : DAT[7]                                                             */
  SDIO_PRESENT_DAT74LINE_DAT6          = 4,     /*!< DAT6 : DAT[6]                                                             */
  SDIO_PRESENT_DAT74LINE_DAT5          = 2,     /*!< DAT5 : DAT[5]                                                             */
  SDIO_PRESENT_DAT74LINE_DAT4          = 1,     /*!< DAT4 : DAT[4]                                                             */
} SDIO_PRESENT_DAT74LINE_Enum;

/* ============================================  SDIO PRESENT DAT30LINE [20..23]  ============================================ */
typedef enum {                                  /*!< SDIO_PRESENT_DAT30LINE                                                    */
  SDIO_PRESENT_DAT30LINE_DAT3          = 8,     /*!< DAT3 : DAT[3]                                                             */
  SDIO_PRESENT_DAT30LINE_DAT2          = 4,     /*!< DAT2 : DAT[2]                                                             */
  SDIO_PRESENT_DAT30LINE_DAT1          = 2,     /*!< DAT1 : DAT[1]                                                             */
  SDIO_PRESENT_DAT30LINE_DAT0          = 1,     /*!< DAT0 : DAT[0]                                                             */
} SDIO_PRESENT_DAT30LINE_Enum;

/* ============================================  SDIO PRESENT WRPROTSW [19..19]  ============================================= */
typedef enum {                                  /*!< SDIO_PRESENT_WRPROTSW                                                     */
  SDIO_PRESENT_WRPROTSW_WRITEPROTECTED = 0,     /*!< WRITEPROTECTED : Write protected (SDWP# = 0)                              */
  SDIO_PRESENT_WRPROTSW_WRITEENABLED   = 1,     /*!< WRITEENABLED : Write enabled (SDWP# = 1)                                  */
} SDIO_PRESENT_WRPROTSW_Enum;

/* =============================================  SDIO PRESENT CARDDET [18..18]  ============================================= */
typedef enum {                                  /*!< SDIO_PRESENT_CARDDET                                                      */
  SDIO_PRESENT_CARDDET_NOCARDPRESENT   = 0,     /*!< NOCARDPRESENT : No Card present (SDCD# = 1)                               */
  SDIO_PRESENT_CARDDET_CARDPRESENT     = 1,     /*!< CARDPRESENT : Card present (SDCD# = 0)                                    */
} SDIO_PRESENT_CARDDET_Enum;

/* ===========================================  SDIO PRESENT CARDSTABLE [17..17]  ============================================ */
typedef enum {                                  /*!< SDIO_PRESENT_CARDSTABLE                                                   */
  SDIO_PRESENT_CARDSTABLE_RESET_DEBOUNCING_NOCARD = 0,/*!< RESET_DEBOUNCING_NOCARD : Reset or Debouncing or No Card            */
  SDIO_PRESENT_CARDSTABLE_CARDINSERTED = 1,     /*!< CARDINSERTED : Card Inserted                                              */
} SDIO_PRESENT_CARDSTABLE_Enum;

/* ==========================================  SDIO PRESENT CARDINSERTED [16..16]  =========================================== */
typedef enum {                                  /*!< SDIO_PRESENT_CARDINSERTED                                                 */
  SDIO_PRESENT_CARDINSERTED_RESET_DEBOUNCING_NOCARD = 0,/*!< RESET_DEBOUNCING_NOCARD : Reset or Debouncing or No Card          */
  SDIO_PRESENT_CARDINSERTED_CARDINSERTED = 1,   /*!< CARDINSERTED : Card Inserted                                              */
} SDIO_PRESENT_CARDINSERTED_Enum;

/* =============================================  SDIO PRESENT BUFRDEN [11..11]  ============================================= */
typedef enum {                                  /*!< SDIO_PRESENT_BUFRDEN                                                      */
  SDIO_PRESENT_BUFRDEN_DISABLE         = 0,     /*!< DISABLE : Read Disable                                                    */
  SDIO_PRESENT_BUFRDEN_ENABLE          = 1,     /*!< ENABLE : Read Enable.                                                     */
} SDIO_PRESENT_BUFRDEN_Enum;

/* =============================================  SDIO PRESENT BUFWREN [10..10]  ============================================= */
typedef enum {                                  /*!< SDIO_PRESENT_BUFWREN                                                      */
  SDIO_PRESENT_BUFWREN_DISABLE         = 0,     /*!< DISABLE : Write Disable                                                   */
  SDIO_PRESENT_BUFWREN_ENABLE          = 1,     /*!< ENABLE : Write Enable.                                                    */
} SDIO_PRESENT_BUFWREN_Enum;

/* =============================================  SDIO PRESENT RDXFERACT [9..9]  ============================================= */
typedef enum {                                  /*!< SDIO_PRESENT_RDXFERACT                                                    */
  SDIO_PRESENT_RDXFERACT_TRANSFERRING  = 1,     /*!< TRANSFERRING : Transferring data                                          */
  SDIO_PRESENT_RDXFERACT_NOVALIDATA    = 0,     /*!< NOVALIDATA : No valid data                                                */
} SDIO_PRESENT_RDXFERACT_Enum;

/* =============================================  SDIO PRESENT WRXFERACT [8..8]  ============================================= */
typedef enum {                                  /*!< SDIO_PRESENT_WRXFERACT                                                    */
  SDIO_PRESENT_WRXFERACT_TRANSFERRING  = 1,     /*!< TRANSFERRING : transferring data                                          */
  SDIO_PRESENT_WRXFERACT_NOVALIDDATA   = 0,     /*!< NOVALIDDATA : No valid data                                               */
} SDIO_PRESENT_WRXFERACT_Enum;

/* ==========================================  SDIO PRESENT RETUNINGREQUEST [3..3]  ========================================== */
typedef enum {                                  /*!< SDIO_PRESENT_RETUNINGREQUEST                                              */
  SDIO_PRESENT_RETUNINGREQUEST_RETUNENEEDED = 1,/*!< RETUNENEEDED : Sampling clock needs re-tuning                             */
  SDIO_PRESENT_RETUNINGREQUEST_WELLTUNED = 0,   /*!< WELLTUNED : Fixed or well tuned sampling clock                            */
} SDIO_PRESENT_RETUNINGREQUEST_Enum;

/* =============================================  SDIO PRESENT DLINEACT [2..2]  ============================================== */
typedef enum {                                  /*!< SDIO_PRESENT_DLINEACT                                                     */
  SDIO_PRESENT_DLINEACT_ACTIVE         = 1,     /*!< ACTIVE : DAT line active                                                  */
  SDIO_PRESENT_DLINEACT_INACTIVE       = 0,     /*!< INACTIVE : DAT line inactive                                              */
} SDIO_PRESENT_DLINEACT_Enum;

/* =============================================  SDIO PRESENT CMDINHDAT [1..1]  ============================================= */
typedef enum {                                  /*!< SDIO_PRESENT_CMDINHDAT                                                    */
  SDIO_PRESENT_CMDINHDAT_DONTISSUE     = 1,     /*!< DONTISSUE : cannot issue command which uses the DAT line                  */
  SDIO_PRESENT_CMDINHDAT_ISSUE         = 0,     /*!< ISSUE : Can issue command which uses the DAT line                         */
} SDIO_PRESENT_CMDINHDAT_Enum;

/* =============================================  SDIO PRESENT CMDINHCMD [0..0]  ============================================= */
typedef enum {                                  /*!< SDIO_PRESENT_CMDINHCMD                                                    */
  SDIO_PRESENT_CMDINHCMD_DONTISSUE     = 1,     /*!< DONTISSUE : CMD line is in use                                            */
  SDIO_PRESENT_CMDINHCMD_ISSUE         = 0,     /*!< ISSUE : Indicates that the CMD line is not in use and the HC
                                                     can issue a SD command using the CMD line.                                */
} SDIO_PRESENT_CMDINHCMD_Enum;

/* =======================================================  HOSTCTRL1  ======================================================= */
/* ========================================  SDIO HOSTCTRL1 WUENCARDREMOVL [26..26]  ========================================= */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_WUENCARDREMOVL                                             */
  SDIO_HOSTCTRL1_WUENCARDREMOVL_ENABLE = 1,     /*!< ENABLE : Enable                                                           */
  SDIO_HOSTCTRL1_WUENCARDREMOVL_DISABLE = 0,    /*!< DISABLE : Disable                                                         */
} SDIO_HOSTCTRL1_WUENCARDREMOVL_Enum;

/* ========================================  SDIO HOSTCTRL1 WUENCARDINSERT [25..25]  ========================================= */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_WUENCARDINSERT                                             */
  SDIO_HOSTCTRL1_WUENCARDINSERT_ENABLE = 1,     /*!< ENABLE : Enable                                                           */
  SDIO_HOSTCTRL1_WUENCARDINSERT_DISABLE = 0,    /*!< DISABLE : Disable                                                         */
} SDIO_HOSTCTRL1_WUENCARDINSERT_Enum;

/* ==========================================  SDIO HOSTCTRL1 WUENCARDINT [24..24]  ========================================== */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_WUENCARDINT                                                */
  SDIO_HOSTCTRL1_WUENCARDINT_ENABLE    = 1,     /*!< ENABLE : Enable                                                           */
  SDIO_HOSTCTRL1_WUENCARDINT_DISABLE   = 0,     /*!< DISABLE : Disable                                                         */
} SDIO_HOSTCTRL1_WUENCARDINT_Enum;

/* ==========================================  SDIO HOSTCTRL1 BOOTACKCHK [23..23]  =========================================== */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_BOOTACKCHK                                                 */
  SDIO_HOSTCTRL1_BOOTACKCHK_WAIT       = 1,     /*!< WAIT : wait for boot ack from eMMC card                                   */
  SDIO_HOSTCTRL1_BOOTACKCHK_NOWAIT     = 0,     /*!< NOWAIT : Will not wait for boot ack from eMMC card                        */
} SDIO_HOSTCTRL1_BOOTACKCHK_Enum;

/* ===========================================  SDIO HOSTCTRL1 ALTBOOTEN [22..22]  =========================================== */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_ALTBOOTEN                                                  */
  SDIO_HOSTCTRL1_ALTBOOTEN_START       = 1,     /*!< START : To start alternate boot mode access                               */
  SDIO_HOSTCTRL1_ALTBOOTEN_STOP        = 0,     /*!< STOP : To stop alternate boot mode access                                 */
} SDIO_HOSTCTRL1_ALTBOOTEN_Enum;

/* ============================================  SDIO HOSTCTRL1 BOOTEN [21..21]  ============================================= */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_BOOTEN                                                     */
  SDIO_HOSTCTRL1_BOOTEN_START          = 1,     /*!< START : To start boot code access                                         */
  SDIO_HOSTCTRL1_BOOTEN_STOP           = 0,     /*!< STOP : To stop boot code access                                           */
} SDIO_HOSTCTRL1_BOOTEN_Enum;

/* ============================================  SDIO HOSTCTRL1 SPIMODE [20..20]  ============================================ */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_SPIMODE                                                    */
  SDIO_HOSTCTRL1_SPIMODE_SPI           = 1,     /*!< SPI : SPI mode                                                            */
  SDIO_HOSTCTRL1_SPIMODE_SD            = 0,     /*!< SD : SD mode                                                              */
} SDIO_HOSTCTRL1_SPIMODE_Enum;

/* =========================================  SDIO HOSTCTRL1 READWAITCTRL [18..18]  ========================================== */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_READWAITCTRL                                               */
  SDIO_HOSTCTRL1_READWAITCTRL_ENABLE   = 1,     /*!< ENABLE : Enable Read Wait Control                                         */
  SDIO_HOSTCTRL1_READWAITCTRL_DISABLE  = 0,     /*!< DISABLE : Disable Read Wait Control                                       */
} SDIO_HOSTCTRL1_READWAITCTRL_Enum;

/* ============================================  SDIO HOSTCTRL1 CONTREQ [17..17]  ============================================ */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_CONTREQ                                                    */
  SDIO_HOSTCTRL1_CONTREQ_RESTART       = 1,     /*!< RESTART : Restart                                                         */
  SDIO_HOSTCTRL1_CONTREQ_IGNORED       = 0,     /*!< IGNORED : Ignored                                                         */
} SDIO_HOSTCTRL1_CONTREQ_Enum;

/* =====================================  SDIO HOSTCTRL1 STOPATBLOCKGAPREQUEST [16..16]  ===================================== */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST                                      */
  SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST_STOP = 1,/*!< STOP : Stop                                                               */
  SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST_TRANSFER = 0,/*!< TRANSFER : Transfer                                                   */
} SDIO_HOSTCTRL1_STOPATBLOCKGAPREQUEST_Enum;

/* ============================================  SDIO HOSTCTRL1 HWRESET [12..12]  ============================================ */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_HWRESET                                                    */
  SDIO_HOSTCTRL1_HWRESET_ASSERT        = 1,     /*!< ASSERT : Drives the hardware reset pin as ZERO (Active LOW to
                                                     eMMC card)                                                                */
  SDIO_HOSTCTRL1_HWRESET_DEASSERT      = 0,     /*!< DEASSERT : Deassert the hardware reset pin                                */
} SDIO_HOSTCTRL1_HWRESET_Enum;

/* ===========================================  SDIO HOSTCTRL1 VOLTSELECT [9..11]  =========================================== */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_VOLTSELECT                                                 */
  SDIO_HOSTCTRL1_VOLTSELECT_3_3V       = 7,     /*!< 3_3V : 3.3 V(Typ.)                                                        */
  SDIO_HOSTCTRL1_VOLTSELECT_3_0V       = 6,     /*!< 3_0V : 3.0 V(Typ.)                                                        */
  SDIO_HOSTCTRL1_VOLTSELECT_1_8V       = 5,     /*!< 1_8V : 1.8 V(Typ.)                                                        */
} SDIO_HOSTCTRL1_VOLTSELECT_Enum;

/* ===========================================  SDIO HOSTCTRL1 SDBUSPOWER [8..8]  ============================================ */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_SDBUSPOWER                                                 */
  SDIO_HOSTCTRL1_SDBUSPOWER_POWERON    = 1,     /*!< POWERON : Power on                                                        */
  SDIO_HOSTCTRL1_SDBUSPOWER_POWEROFF   = 0,     /*!< POWEROFF : Power off                                                      */
} SDIO_HOSTCTRL1_SDBUSPOWER_Enum;

/* =============================================  SDIO HOSTCTRL1 CARDSRC [7..7]  ============================================= */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_CARDSRC                                                    */
  SDIO_HOSTCTRL1_CARDSRC_TEST          = 1,     /*!< TEST : The card detect test level is selected                             */
  SDIO_HOSTCTRL1_CARDSRC_SDCD          = 0,     /*!< SDCD : SDCD is selected (for normal use)                                  */
} SDIO_HOSTCTRL1_CARDSRC_Enum;

/* ============================================  SDIO HOSTCTRL1 TESTLEVEL [6..6]  ============================================ */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_TESTLEVEL                                                  */
  SDIO_HOSTCTRL1_TESTLEVEL_CARDINSERTED = 1,    /*!< CARDINSERTED : Card Inserted                                              */
  SDIO_HOSTCTRL1_TESTLEVEL_NOCARD      = 0,     /*!< NOCARD : No Card                                                          */
} SDIO_HOSTCTRL1_TESTLEVEL_Enum;

/* ============================================  SDIO HOSTCTRL1 XFERWIDTH [5..5]  ============================================ */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_XFERWIDTH                                                  */
  SDIO_HOSTCTRL1_XFERWIDTH_8BIT        = 1,     /*!< 8BIT : 8-bit Bus Width                                                    */
  SDIO_HOSTCTRL1_XFERWIDTH_XFER        = 0,     /*!< XFER : Bus Width is selected by Data Transfer Width                       */
} SDIO_HOSTCTRL1_XFERWIDTH_Enum;

/* ============================================  SDIO HOSTCTRL1 DMASELECT [3..4]  ============================================ */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_DMASELECT                                                  */
  SDIO_HOSTCTRL1_DMASELECT_SDMA        = 0,     /*!< SDMA : SDMA is selected                                                   */
  SDIO_HOSTCTRL1_DMASELECT_ADMA132     = 1,     /*!< ADMA132 : 32-bit Address ADMA1 is selected                                */
  SDIO_HOSTCTRL1_DMASELECT_ADMA232     = 2,     /*!< ADMA232 : 32-bit Address ADMA2 is selected                                */
  SDIO_HOSTCTRL1_DMASELECT_ADMA264     = 3,     /*!< ADMA264 : 64-bit Address ADMA2 is selected                                */
} SDIO_HOSTCTRL1_DMASELECT_Enum;

/* ============================================  SDIO HOSTCTRL1 HISPEEDEN [2..2]  ============================================ */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_HISPEEDEN                                                  */
  SDIO_HOSTCTRL1_HISPEEDEN_HIGH        = 1,     /*!< HIGH : High Speed Mode                                                    */
  SDIO_HOSTCTRL1_HISPEEDEN_NORMAL      = 0,     /*!< NORMAL : Normal Speed Mode                                                */
} SDIO_HOSTCTRL1_HISPEEDEN_Enum;

/* ========================================  SDIO HOSTCTRL1 DATATRANSFERWIDTH [1..1]  ======================================== */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_DATATRANSFERWIDTH                                          */
  SDIO_HOSTCTRL1_DATATRANSFERWIDTH_SD4 = 1,     /*!< SD4 : 4 bit mode                                                          */
  SDIO_HOSTCTRL1_DATATRANSFERWIDTH_SD1 = 0,     /*!< SD1 : 1 bit mode                                                          */
} SDIO_HOSTCTRL1_DATATRANSFERWIDTH_Enum;

/* ===========================================  SDIO HOSTCTRL1 LEDCONTROL [0..0]  ============================================ */
typedef enum {                                  /*!< SDIO_HOSTCTRL1_LEDCONTROL                                                 */
  SDIO_HOSTCTRL1_LEDCONTROL_ON         = 1,     /*!< ON : LED on                                                               */
  SDIO_HOSTCTRL1_LEDCONTROL_OFF        = 0,     /*!< OFF : LED off                                                             */
} SDIO_HOSTCTRL1_LEDCONTROL_Enum;

/* =======================================================  CLOCKCTRL  ======================================================= */
/* ===========================================  SDIO CLOCKCTRL SWRSTDAT [26..26]  ============================================ */
typedef enum {                                  /*!< SDIO_CLOCKCTRL_SWRSTDAT                                                   */
  SDIO_CLOCKCTRL_SWRSTDAT_RESET        = 1,     /*!< RESET : Reset                                                             */
  SDIO_CLOCKCTRL_SWRSTDAT_WORK         = 0,     /*!< WORK : Work                                                               */
} SDIO_CLOCKCTRL_SWRSTDAT_Enum;

/* ===========================================  SDIO CLOCKCTRL SWRSTCMD [25..25]  ============================================ */
typedef enum {                                  /*!< SDIO_CLOCKCTRL_SWRSTCMD                                                   */
  SDIO_CLOCKCTRL_SWRSTCMD_RESET        = 1,     /*!< RESET : Reset                                                             */
  SDIO_CLOCKCTRL_SWRSTCMD_WORK         = 0,     /*!< WORK : Work                                                               */
} SDIO_CLOCKCTRL_SWRSTCMD_Enum;

/* ===========================================  SDIO CLOCKCTRL SWRSTALL [24..24]  ============================================ */
typedef enum {                                  /*!< SDIO_CLOCKCTRL_SWRSTALL                                                   */
  SDIO_CLOCKCTRL_SWRSTALL_RESET        = 1,     /*!< RESET : Reset                                                             */
  SDIO_CLOCKCTRL_SWRSTALL_WORK         = 0,     /*!< WORK : Work                                                               */
} SDIO_CLOCKCTRL_SWRSTALL_Enum;

/* ==========================================  SDIO CLOCKCTRL TIMEOUTCNT [16..19]  =========================================== */
typedef enum {                                  /*!< SDIO_CLOCKCTRL_TIMEOUTCNT                                                 */
  SDIO_CLOCKCTRL_TIMEOUTCNT_27         = 14,    /*!< 27 : TMCLK * 2^27                                                         */
  SDIO_CLOCKCTRL_TIMEOUTCNT_26         = 0,     /*!< 26 : TMCLK * 2^26                                                         */
} SDIO_CLOCKCTRL_TIMEOUTCNT_Enum;

/* ============================================  SDIO CLOCKCTRL FREQSEL [8..15]  ============================================= */
typedef enum {                                  /*!< SDIO_CLOCKCTRL_FREQSEL                                                    */
  SDIO_CLOCKCTRL_FREQSEL_DIV256        = 128,   /*!< DIV256 : base clock divided by 256                                        */
  SDIO_CLOCKCTRL_FREQSEL_DIV128        = 64,    /*!< DIV128 : base clock divided by 128                                        */
  SDIO_CLOCKCTRL_FREQSEL_DIV64         = 32,    /*!< DIV64 : base clock divided by 64                                          */
  SDIO_CLOCKCTRL_FREQSEL_DIV32         = 16,    /*!< DIV32 : base clock divided by 32                                          */
  SDIO_CLOCKCTRL_FREQSEL_DIV16         = 8,     /*!< DIV16 : base clock divided by 16                                          */
  SDIO_CLOCKCTRL_FREQSEL_DIV8          = 4,     /*!< DIV8 : base clock divided by 8                                            */
  SDIO_CLOCKCTRL_FREQSEL_DIV4          = 2,     /*!< DIV4 : base clock divided by 4                                            */
  SDIO_CLOCKCTRL_FREQSEL_DIV2          = 1,     /*!< DIV2 : base clock divided by 2                                            */
  SDIO_CLOCKCTRL_FREQSEL_BASECLK       = 0,     /*!< BASECLK : Base clock (10MHz - 63MHz)                                      */
} SDIO_CLOCKCTRL_FREQSEL_Enum;

/* ============================================  SDIO CLOCKCTRL CLKGENSEL [5..5]  ============================================ */
typedef enum {                                  /*!< SDIO_CLOCKCTRL_CLKGENSEL                                                  */
  SDIO_CLOCKCTRL_CLKGENSEL_PROGCLK     = 1,     /*!< PROGCLK : Programmable Clock Mode                                         */
  SDIO_CLOCKCTRL_CLKGENSEL_DIVCLK      = 0,     /*!< DIVCLK : Divided Clock Mode                                               */
} SDIO_CLOCKCTRL_CLKGENSEL_Enum;

/* =============================================  SDIO CLOCKCTRL SDCLKEN [2..2]  ============================================= */
typedef enum {                                  /*!< SDIO_CLOCKCTRL_SDCLKEN                                                    */
  SDIO_CLOCKCTRL_SDCLKEN_ENABLE        = 1,     /*!< ENABLE : Enable                                                           */
  SDIO_CLOCKCTRL_SDCLKEN_DISABLE       = 0,     /*!< DISABLE : Disable                                                         */
} SDIO_CLOCKCTRL_SDCLKEN_Enum;

/* ============================================  SDIO CLOCKCTRL CLKSTABLE [1..1]  ============================================ */
typedef enum {                                  /*!< SDIO_CLOCKCTRL_CLKSTABLE                                                  */
  SDIO_CLOCKCTRL_CLKSTABLE_READY       = 1,     /*!< READY : Ready                                                             */
  SDIO_CLOCKCTRL_CLKSTABLE_NOTREADY    = 0,     /*!< NOTREADY : Not Ready                                                      */
} SDIO_CLOCKCTRL_CLKSTABLE_Enum;

/* ==============================================  SDIO CLOCKCTRL CLKEN [0..0]  ============================================== */
typedef enum {                                  /*!< SDIO_CLOCKCTRL_CLKEN                                                      */
  SDIO_CLOCKCTRL_CLKEN_OSC             = 1,     /*!< OSC : Oscillate                                                           */
  SDIO_CLOCKCTRL_CLKEN_STOP            = 0,     /*!< STOP : Stop                                                               */
} SDIO_CLOCKCTRL_CLKEN_Enum;

/* ========================================================  INTSTAT  ======================================================== */
/* ===========================================  SDIO INTSTAT VNDERRSTAT [29..31]  ============================================ */
typedef enum {                                  /*!< SDIO_INTSTAT_VNDERRSTAT                                                   */
  SDIO_INTSTAT_VNDERRSTAT_READY        = 1,     /*!< READY : Ready                                                             */
  SDIO_INTSTAT_VNDERRSTAT_NOTREADY     = 0,     /*!< NOTREADY : Not Ready                                                      */
} SDIO_INTSTAT_VNDERRSTAT_Enum;

/* ===========================================  SDIO INTSTAT TGTRESPERR [28..28]  ============================================ */
typedef enum {                                  /*!< SDIO_INTSTAT_TGTRESPERR                                                   */
  SDIO_INTSTAT_TGTRESPERR_NOERROR      = 0,     /*!< NOERROR : no error                                                        */
  SDIO_INTSTAT_TGTRESPERR_ERROR        = 1,     /*!< ERROR : error                                                             */
} SDIO_INTSTAT_TGTRESPERR_Enum;

/* ============================================  SDIO INTSTAT ADMAERROR [25..25]  ============================================ */
typedef enum {                                  /*!< SDIO_INTSTAT_ADMAERROR                                                    */
  SDIO_INTSTAT_ADMAERROR_ERROR         = 1,     /*!< ERROR : Error                                                             */
  SDIO_INTSTAT_ADMAERROR_NOERROR       = 0,     /*!< NOERROR : No error                                                        */
} SDIO_INTSTAT_ADMAERROR_Enum;

/* ==========================================  SDIO INTSTAT AUTOCMDERROR [24..24]  =========================================== */
typedef enum {                                  /*!< SDIO_INTSTAT_AUTOCMDERROR                                                 */
  SDIO_INTSTAT_AUTOCMDERROR_NOERROR    = 0,     /*!< NOERROR : No Error                                                        */
  SDIO_INTSTAT_AUTOCMDERROR_ERROR      = 1,     /*!< ERROR : Error                                                             */
} SDIO_INTSTAT_AUTOCMDERROR_Enum;

/* ========================================  SDIO INTSTAT CURRENTLIMITERROR [23..23]  ======================================== */
typedef enum {                                  /*!< SDIO_INTSTAT_CURRENTLIMITERROR                                            */
  SDIO_INTSTAT_CURRENTLIMITERROR_NOERROR = 0,   /*!< NOERROR : No Error                                                        */
  SDIO_INTSTAT_CURRENTLIMITERROR_ERROR = 1,     /*!< ERROR : Power Fail                                                        */
} SDIO_INTSTAT_CURRENTLIMITERROR_Enum;

/* =========================================  SDIO INTSTAT DATAENDBITERROR [22..22]  ========================================= */
typedef enum {                                  /*!< SDIO_INTSTAT_DATAENDBITERROR                                              */
  SDIO_INTSTAT_DATAENDBITERROR_NOERROR = 0,     /*!< NOERROR : No Error                                                        */
  SDIO_INTSTAT_DATAENDBITERROR_ERROR   = 1,     /*!< ERROR : Error                                                             */
} SDIO_INTSTAT_DATAENDBITERROR_Enum;

/* ==========================================  SDIO INTSTAT DATACRCERROR [21..21]  =========================================== */
typedef enum {                                  /*!< SDIO_INTSTAT_DATACRCERROR                                                 */
  SDIO_INTSTAT_DATACRCERROR_NOERROR    = 0,     /*!< NOERROR : No Error                                                        */
  SDIO_INTSTAT_DATACRCERROR_ERROR      = 1,     /*!< ERROR : Error                                                             */
} SDIO_INTSTAT_DATACRCERROR_Enum;

/* ========================================  SDIO INTSTAT DATATIMEOUTERROR [20..20]  ========================================= */
typedef enum {                                  /*!< SDIO_INTSTAT_DATATIMEOUTERROR                                             */
  SDIO_INTSTAT_DATATIMEOUTERROR_NOERROR = 0,    /*!< NOERROR : No Error                                                        */
  SDIO_INTSTAT_DATATIMEOUTERROR_ERROR  = 1,     /*!< ERROR : Timeout                                                           */
} SDIO_INTSTAT_DATATIMEOUTERROR_Enum;

/* ========================================  SDIO INTSTAT COMMANDINDEXERROR [19..19]  ======================================== */
typedef enum {                                  /*!< SDIO_INTSTAT_COMMANDINDEXERROR                                            */
  SDIO_INTSTAT_COMMANDINDEXERROR_NOERROR = 0,   /*!< NOERROR : No Error                                                        */
  SDIO_INTSTAT_COMMANDINDEXERROR_ERROR = 1,     /*!< ERROR : Error                                                             */
} SDIO_INTSTAT_COMMANDINDEXERROR_Enum;

/* =======================================  SDIO INTSTAT COMMANDENDBITERROR [18..18]  ======================================== */
typedef enum {                                  /*!< SDIO_INTSTAT_COMMANDENDBITERROR                                           */
  SDIO_INTSTAT_COMMANDENDBITERROR_NOERROR = 0,  /*!< NOERROR : No Error                                                        */
  SDIO_INTSTAT_COMMANDENDBITERROR_ERROR = 1,    /*!< ERROR : Timeout                                                           */
} SDIO_INTSTAT_COMMANDENDBITERROR_Enum;

/* =========================================  SDIO INTSTAT COMMANDCRCERROR [17..17]  ========================================= */
typedef enum {                                  /*!< SDIO_INTSTAT_COMMANDCRCERROR                                              */
  SDIO_INTSTAT_COMMANDCRCERROR_NOERROR = 0,     /*!< NOERROR : No Error                                                        */
  SDIO_INTSTAT_COMMANDCRCERROR_ERROR   = 1,     /*!< ERROR : End Bit Error Generated                                           */
} SDIO_INTSTAT_COMMANDCRCERROR_Enum;

/* =======================================  SDIO INTSTAT COMMANDTIMEOUTERROR [16..16]  ======================================= */
typedef enum {                                  /*!< SDIO_INTSTAT_COMMANDTIMEOUTERROR                                          */
  SDIO_INTSTAT_COMMANDTIMEOUTERROR_NOERROR = 0, /*!< NOERROR : No Error                                                        */
  SDIO_INTSTAT_COMMANDTIMEOUTERROR_ERROR = 1,   /*!< ERROR : CRC Error Generated                                               */
} SDIO_INTSTAT_COMMANDTIMEOUTERROR_Enum;

/* =========================================  SDIO INTSTAT ERRORINTERRUPT [15..15]  ========================================== */
typedef enum {                                  /*!< SDIO_INTSTAT_ERRORINTERRUPT                                               */
  SDIO_INTSTAT_ERRORINTERRUPT_NOERROR  = 0,     /*!< NOERROR : No Error.                                                       */
  SDIO_INTSTAT_ERRORINTERRUPT_ERROR    = 1,     /*!< ERROR : Error.                                                            */
} SDIO_INTSTAT_ERRORINTERRUPT_Enum;

/* ==========================================  SDIO INTSTAT BOOTTERMINATE [14..14]  ========================================== */
typedef enum {                                  /*!< SDIO_INTSTAT_BOOTTERMINATE                                                */
  SDIO_INTSTAT_BOOTTERMINATE_OK        = 0,     /*!< OK : Boot operation is not terminated.                                    */
  SDIO_INTSTAT_BOOTTERMINATE_BOOTTERM  = 1,     /*!< BOOTTERM : Boot operation is terminated                                   */
} SDIO_INTSTAT_BOOTTERMINATE_Enum;

/* ===========================================  SDIO INTSTAT BOOTACKRCV [13..13]  ============================================ */
typedef enum {                                  /*!< SDIO_INTSTAT_BOOTACKRCV                                                   */
  SDIO_INTSTAT_BOOTACKRCV_NOACK        = 0,     /*!< NOACK : Boot ack is not received.                                         */
  SDIO_INTSTAT_BOOTACKRCV_ACK          = 1,     /*!< ACK : Boot ack is received.                                               */
} SDIO_INTSTAT_BOOTACKRCV_Enum;

/* ==========================================  SDIO INTSTAT RETUNINGEVENT [12..12]  ========================================== */
typedef enum {                                  /*!< SDIO_INTSTAT_RETUNINGEVENT                                                */
  SDIO_INTSTAT_RETUNINGEVENT_RETUNE    = 1,     /*!< RETUNE : ReTuning should be performed                                     */
  SDIO_INTSTAT_RETUNINGEVENT_NORETUNE  = 0,     /*!< NORETUNE : ReTuning is not required                                       */
} SDIO_INTSTAT_RETUNINGEVENT_Enum;

/* ===========================================  SDIO INTSTAT CARDINTERRUPT [8..8]  =========================================== */
typedef enum {                                  /*!< SDIO_INTSTAT_CARDINTERRUPT                                                */
  SDIO_INTSTAT_CARDINTERRUPT_NOINT     = 0,     /*!< NOINT : No Card Interrupt                                                 */
  SDIO_INTSTAT_CARDINTERRUPT_INT       = 1,     /*!< INT : Generate Card Interrupt                                             */
} SDIO_INTSTAT_CARDINTERRUPT_Enum;

/* ============================================  SDIO INTSTAT CARDREMOVAL [7..7]  ============================================ */
typedef enum {                                  /*!< SDIO_INTSTAT_CARDREMOVAL                                                  */
  SDIO_INTSTAT_CARDREMOVAL_STABLE      = 0,     /*!< STABLE : Card State Stable or Debouncing                                  */
  SDIO_INTSTAT_CARDREMOVAL_REMOVED     = 1,     /*!< REMOVED : Card Removed                                                    */
} SDIO_INTSTAT_CARDREMOVAL_Enum;

/* ===========================================  SDIO INTSTAT CARDINSERTION [6..6]  =========================================== */
typedef enum {                                  /*!< SDIO_INTSTAT_CARDINSERTION                                                */
  SDIO_INTSTAT_CARDINSERTION_STABLE    = 0,     /*!< STABLE : Card State Stable or Debouncing                                  */
  SDIO_INTSTAT_CARDINSERTION_INSERTED  = 1,     /*!< INSERTED : Card Inserted                                                  */
} SDIO_INTSTAT_CARDINSERTION_Enum;

/* ==========================================  SDIO INTSTAT BUFFERREADREADY [5..5]  ========================================== */
typedef enum {                                  /*!< SDIO_INTSTAT_BUFFERREADREADY                                              */
  SDIO_INTSTAT_BUFFERREADREADY_NOREADY = 0,     /*!< NOREADY : Not Ready to read Buffer.                                       */
  SDIO_INTSTAT_BUFFERREADREADY_READY   = 1,     /*!< READY : Ready to read Buffer.                                             */
} SDIO_INTSTAT_BUFFERREADREADY_Enum;

/* =========================================  SDIO INTSTAT BUFFERWRITEREADY [4..4]  ========================================== */
typedef enum {                                  /*!< SDIO_INTSTAT_BUFFERWRITEREADY                                             */
  SDIO_INTSTAT_BUFFERWRITEREADY_NOTREADY = 0,   /*!< NOTREADY : Not Ready to Write Buffer.                                     */
  SDIO_INTSTAT_BUFFERWRITEREADY_READY  = 1,     /*!< READY : Ready to Write Buffer.                                            */
} SDIO_INTSTAT_BUFFERWRITEREADY_Enum;

/* ===========================================  SDIO INTSTAT DMAINTERRUPT [3..3]  ============================================ */
typedef enum {                                  /*!< SDIO_INTSTAT_DMAINTERRUPT                                                 */
  SDIO_INTSTAT_DMAINTERRUPT_NOINT      = 0,     /*!< NOINT : No DMA Interrupt                                                  */
  SDIO_INTSTAT_DMAINTERRUPT_INT        = 1,     /*!< INT : DMA Interrupt is Generated                                          */
} SDIO_INTSTAT_DMAINTERRUPT_Enum;

/* ===========================================  SDIO INTSTAT BLOCKGAPEVENT [2..2]  =========================================== */
typedef enum {                                  /*!< SDIO_INTSTAT_BLOCKGAPEVENT                                                */
  SDIO_INTSTAT_BLOCKGAPEVENT_NOEVENT   = 0,     /*!< NOEVENT : No Block Gap Event                                              */
  SDIO_INTSTAT_BLOCKGAPEVENT_STOPPED   = 1,     /*!< STOPPED : Transaction stopped at Block Gap                                */
} SDIO_INTSTAT_BLOCKGAPEVENT_Enum;

/* =========================================  SDIO INTSTAT TRANSFERCOMPLETE [1..1]  ========================================== */
typedef enum {                                  /*!< SDIO_INTSTAT_TRANSFERCOMPLETE                                             */
  SDIO_INTSTAT_TRANSFERCOMPLETE_NODATA = 0,     /*!< NODATA : No Data Transfer Complete                                        */
  SDIO_INTSTAT_TRANSFERCOMPLETE_COMPLETE = 1,   /*!< COMPLETE : Data Transfer Complete                                         */
} SDIO_INTSTAT_TRANSFERCOMPLETE_Enum;

/* ==========================================  SDIO INTSTAT COMMANDCOMPLETE [0..0]  ========================================== */
typedef enum {                                  /*!< SDIO_INTSTAT_COMMANDCOMPLETE                                              */
  SDIO_INTSTAT_COMMANDCOMPLETE_NOCMP   = 0,     /*!< NOCMP : No Command Complete                                               */
  SDIO_INTSTAT_COMMANDCOMPLETE_CMDCMP  = 1,     /*!< CMDCMP : Command Complete                                                 */
} SDIO_INTSTAT_COMMANDCOMPLETE_Enum;

/* =======================================================  INTENABLE  ======================================================= */
/* ========================================================  INTSIG  ========================================================= */
/* ============================================  SDIO INTSIG TGTRESPEN [28..28]  ============================================= */
typedef enum {                                  /*!< SDIO_INTSIG_TGTRESPEN                                                     */
  SDIO_INTSIG_TGTRESPEN_MASKED         = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_TGTRESPEN_ENABLED        = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_TGTRESPEN_Enum;

/* ===========================================  SDIO INTSIG TUNINGERREN [26..26]  ============================================ */
typedef enum {                                  /*!< SDIO_INTSIG_TUNINGERREN                                                   */
  SDIO_INTSIG_TUNINGERREN_MASKED       = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_TUNINGERREN_ENABLED      = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_TUNINGERREN_Enum;

/* ============================================  SDIO INTSIG ADMAERREN [25..25]  ============================================= */
typedef enum {                                  /*!< SDIO_INTSIG_ADMAERREN                                                     */
  SDIO_INTSIG_ADMAERREN_MASKED         = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_ADMAERREN_ENABLED        = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_ADMAERREN_Enum;

/* ==========================================  SDIO INTSIG AUTOCMD12ERREN [24..24]  ========================================== */
typedef enum {                                  /*!< SDIO_INTSIG_AUTOCMD12ERREN                                                */
  SDIO_INTSIG_AUTOCMD12ERREN_MASKED    = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_AUTOCMD12ERREN_ENABLED   = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_AUTOCMD12ERREN_Enum;

/* ===========================================  SDIO INTSIG CURRLMTERREN [23..23]  =========================================== */
typedef enum {                                  /*!< SDIO_INTSIG_CURRLMTERREN                                                  */
  SDIO_INTSIG_CURRLMTERREN_MASKED      = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_CURRLMTERREN_ENABLED     = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_CURRLMTERREN_Enum;

/* ===========================================  SDIO INTSIG DATAENDERREN [22..22]  =========================================== */
typedef enum {                                  /*!< SDIO_INTSIG_DATAENDERREN                                                  */
  SDIO_INTSIG_DATAENDERREN_MASKED      = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_DATAENDERREN_ENABLED     = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_DATAENDERREN_Enum;

/* ===========================================  SDIO INTSIG DATACRCERREN [21..21]  =========================================== */
typedef enum {                                  /*!< SDIO_INTSIG_DATACRCERREN                                                  */
  SDIO_INTSIG_DATACRCERREN_MASKED      = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_DATACRCERREN_ENABLED     = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_DATACRCERREN_Enum;

/* ==========================================  SDIO INTSIG DATATOERROREN [20..20]  =========================================== */
typedef enum {                                  /*!< SDIO_INTSIG_DATATOERROREN                                                 */
  SDIO_INTSIG_DATATOERROREN_MASKED     = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_DATATOERROREN_ENABLED    = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_DATATOERROREN_Enum;

/* ===========================================  SDIO INTSIG CMDIDXERREN [19..19]  ============================================ */
typedef enum {                                  /*!< SDIO_INTSIG_CMDIDXERREN                                                   */
  SDIO_INTSIG_CMDIDXERREN_MASKED       = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_CMDIDXERREN_ENABLED      = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_CMDIDXERREN_Enum;

/* ==========================================  SDIO INTSIG CMDENDBITERREN [18..18]  ========================================== */
typedef enum {                                  /*!< SDIO_INTSIG_CMDENDBITERREN                                                */
  SDIO_INTSIG_CMDENDBITERREN_MASKED    = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_CMDENDBITERREN_ENABLED   = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_CMDENDBITERREN_Enum;

/* ===========================================  SDIO INTSIG CMDCRCERREN [17..17]  ============================================ */
typedef enum {                                  /*!< SDIO_INTSIG_CMDCRCERREN                                                   */
  SDIO_INTSIG_CMDCRCERREN_MASKED       = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_CMDCRCERREN_ENABLED      = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_CMDCRCERREN_Enum;

/* ============================================  SDIO INTSIG CMDTOERREN [16..16]  ============================================ */
typedef enum {                                  /*!< SDIO_INTSIG_CMDTOERREN                                                    */
  SDIO_INTSIG_CMDTOERREN_MASKED        = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_CMDTOERREN_ENABLED       = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_CMDTOERREN_Enum;

/* ==============================================  SDIO INTSIG FIXED0 [15..15]  ============================================== */
typedef enum {                                  /*!< SDIO_INTSIG_FIXED0                                                        */
  SDIO_INTSIG_FIXED0_MASKED            = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_FIXED0_ENABLED           = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_FIXED0_Enum;

/* =============================================  SDIO INTSIG BOOTTERM [14..14]  ============================================= */
typedef enum {                                  /*!< SDIO_INTSIG_BOOTTERM                                                      */
  SDIO_INTSIG_BOOTTERM_MASKED          = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_BOOTTERM_ENABLED         = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_BOOTTERM_Enum;

/* ============================================  SDIO INTSIG BOOTACKEN [13..13]  ============================================= */
typedef enum {                                  /*!< SDIO_INTSIG_BOOTACKEN                                                     */
  SDIO_INTSIG_BOOTACKEN_MASKED         = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_BOOTACKEN_ENABLED        = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_BOOTACKEN_Enum;

/* ==========================================  SDIO INTSIG RETUNEEVENTEN [12..12]  =========================================== */
typedef enum {                                  /*!< SDIO_INTSIG_RETUNEEVENTEN                                                 */
  SDIO_INTSIG_RETUNEEVENTEN_MASKED     = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_RETUNEEVENTEN_ENABLED    = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_RETUNEEVENTEN_Enum;

/* ==============================================  SDIO INTSIG INTCEN [11..11]  ============================================== */
typedef enum {                                  /*!< SDIO_INTSIG_INTCEN                                                        */
  SDIO_INTSIG_INTCEN_MASKED            = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_INTCEN_ENABLED           = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_INTCEN_Enum;

/* ==============================================  SDIO INTSIG INTBEN [10..10]  ============================================== */
typedef enum {                                  /*!< SDIO_INTSIG_INTBEN                                                        */
  SDIO_INTSIG_INTBEN_MASKED            = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_INTBEN_ENABLED           = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_INTBEN_Enum;

/* ===============================================  SDIO INTSIG INTAEN [9..9]  =============================================== */
typedef enum {                                  /*!< SDIO_INTSIG_INTAEN                                                        */
  SDIO_INTSIG_INTAEN_MASKED            = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_INTAEN_ENABLED           = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_INTAEN_Enum;

/* =============================================  SDIO INTSIG CARDINTEN [8..8]  ============================================== */
typedef enum {                                  /*!< SDIO_INTSIG_CARDINTEN                                                     */
  SDIO_INTSIG_CARDINTEN_MASKED         = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_CARDINTEN_ENABLED        = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_CARDINTEN_Enum;

/* ===========================================  SDIO INTSIG CARDREMOVALEN [7..7]  ============================================ */
typedef enum {                                  /*!< SDIO_INTSIG_CARDREMOVALEN                                                 */
  SDIO_INTSIG_CARDREMOVALEN_MASKED     = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_CARDREMOVALEN_ENABLED    = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_CARDREMOVALEN_Enum;

/* ============================================  SDIO INTSIG CARDINSERTEN [6..6]  ============================================ */
typedef enum {                                  /*!< SDIO_INTSIG_CARDINSERTEN                                                  */
  SDIO_INTSIG_CARDINSERTEN_MASKED      = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_CARDINSERTEN_ENABLED     = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_CARDINSERTEN_Enum;

/* =============================================  SDIO INTSIG BUFFERRDEN [5..5]  ============================================= */
typedef enum {                                  /*!< SDIO_INTSIG_BUFFERRDEN                                                    */
  SDIO_INTSIG_BUFFERRDEN_MASKED        = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_BUFFERRDEN_ENABLED       = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_BUFFERRDEN_Enum;

/* =============================================  SDIO INTSIG BUFFERWREN [4..4]  ============================================= */
typedef enum {                                  /*!< SDIO_INTSIG_BUFFERWREN                                                    */
  SDIO_INTSIG_BUFFERWREN_MASKED        = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_BUFFERWREN_ENABLED       = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_BUFFERWREN_Enum;

/* ==============================================  SDIO INTSIG DMAINTEN [3..3]  ============================================== */
typedef enum {                                  /*!< SDIO_INTSIG_DMAINTEN                                                      */
  SDIO_INTSIG_DMAINTEN_MASKED          = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_DMAINTEN_ENABLED         = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_DMAINTEN_Enum;

/* =============================================  SDIO INTSIG BLOCKGAPEN [2..2]  ============================================= */
typedef enum {                                  /*!< SDIO_INTSIG_BLOCKGAPEN                                                    */
  SDIO_INTSIG_BLOCKGAPEN_MASKED        = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_BLOCKGAPEN_ENABLED       = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_BLOCKGAPEN_Enum;

/* =============================================  SDIO INTSIG XFERCMPEN [1..1]  ============================================== */
typedef enum {                                  /*!< SDIO_INTSIG_XFERCMPEN                                                     */
  SDIO_INTSIG_XFERCMPEN_MASKED         = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_XFERCMPEN_ENABLED        = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_XFERCMPEN_Enum;

/* ==============================================  SDIO INTSIG CMDCMPEN [0..0]  ============================================== */
typedef enum {                                  /*!< SDIO_INTSIG_CMDCMPEN                                                      */
  SDIO_INTSIG_CMDCMPEN_MASKED          = 0,     /*!< MASKED : Masked                                                           */
  SDIO_INTSIG_CMDCMPEN_ENABLED         = 1,     /*!< ENABLED : Enabled                                                         */
} SDIO_INTSIG_CMDCMPEN_Enum;

/* =========================================================  AUTO  ========================================================== */
/* ==============================================  SDIO AUTO PRESETEN [31..31]  ============================================== */
typedef enum {                                  /*!< SDIO_AUTO_PRESETEN                                                        */
  SDIO_AUTO_PRESETEN_AUTOEN            = 1,     /*!< AUTOEN : Automatic Selection by Preset Value are Enabled                  */
  SDIO_AUTO_PRESETEN_HOSTCTRL          = 0,     /*!< HOSTCTRL : SDCLK and Driver Strength are controlled by Host
                                                     Driver                                                                    */
} SDIO_AUTO_PRESETEN_Enum;

/* =============================================  SDIO AUTO ASYNCINTEN [30..30]  ============================================= */
typedef enum {                                  /*!< SDIO_AUTO_ASYNCINTEN                                                      */
  SDIO_AUTO_ASYNCINTEN_ENABLED         = 1,     /*!< ENABLED : Enabled,                                                        */
  SDIO_AUTO_ASYNCINTEN_DISABLED        = 0,     /*!< DISABLED : Disabled                                                       */
} SDIO_AUTO_ASYNCINTEN_Enum;

/* ============================================  SDIO AUTO SAMPLCLKSEL [23..23]  ============================================= */
typedef enum {                                  /*!< SDIO_AUTO_SAMPLCLKSEL                                                     */
  SDIO_AUTO_SAMPLCLKSEL_TUNEDCLK       = 1,     /*!< TUNEDCLK : Tuned clock is used to sample data                             */
  SDIO_AUTO_SAMPLCLKSEL_FIXEDCLK       = 0,     /*!< FIXEDCLK : Fixed clock is used to sample data                             */
} SDIO_AUTO_SAMPLCLKSEL_Enum;

/* ============================================  SDIO AUTO STARTTUNING [22..22]  ============================================= */
typedef enum {                                  /*!< SDIO_AUTO_STARTTUNING                                                     */
  SDIO_AUTO_STARTTUNING_TUNESTART      = 1,     /*!< TUNESTART : Execute Tuning,                                               */
  SDIO_AUTO_STARTTUNING_TUNECMP        = 0,     /*!< TUNECMP : Not Tuned or Tuning Completed                                   */
} SDIO_AUTO_STARTTUNING_Enum;

/* =============================================  SDIO AUTO DRVRSTRSEL [20..21]  ============================================= */
typedef enum {                                  /*!< SDIO_AUTO_DRVRSTRSEL                                                      */
  SDIO_AUTO_DRVRSTRSEL_DRVRB           = 0,     /*!< DRVRB : Driver Type B is Selected (Default)                               */
  SDIO_AUTO_DRVRSTRSEL_DRVRA           = 1,     /*!< DRVRA : Driver Type A is Selected                                         */
  SDIO_AUTO_DRVRSTRSEL_DRVRC           = 2,     /*!< DRVRC : Driver Type C is Selected                                         */
  SDIO_AUTO_DRVRSTRSEL_DRVRD           = 3,     /*!< DRVRD : Driver Type D is Selected                                         */
} SDIO_AUTO_DRVRSTRSEL_Enum;

/* =============================================  SDIO AUTO SIGNALVOLT [19..19]  ============================================= */
typedef enum {                                  /*!< SDIO_AUTO_SIGNALVOLT                                                      */
  SDIO_AUTO_SIGNALVOLT_1_8V            = 1,     /*!< 1_8V : 1.8V Signaling                                                     */
  SDIO_AUTO_SIGNALVOLT_3_3V            = 0,     /*!< 3_3V : 3.3V Signaling                                                     */
} SDIO_AUTO_SIGNALVOLT_Enum;

/* =============================================  SDIO AUTO UHSMODESEL [16..18]  ============================================= */
typedef enum {                                  /*!< SDIO_AUTO_UHSMODESEL                                                      */
  SDIO_AUTO_UHSMODESEL_SDR12           = 0,     /*!< SDR12 : UHS-I mode SDR12                                                  */
  SDIO_AUTO_UHSMODESEL_SDR25           = 1,     /*!< SDR25 : UHS-I mode SDR25                                                  */
  SDIO_AUTO_UHSMODESEL_SDR50           = 2,     /*!< SDR50 : UHS-I mode SDR50                                                  */
  SDIO_AUTO_UHSMODESEL_SDR104          = 3,     /*!< SDR104 : UHS-I mode SDR104                                                */
  SDIO_AUTO_UHSMODESEL_DDR50           = 4,     /*!< DDR50 : UHS-I mode DDR50                                                  */
} SDIO_AUTO_UHSMODESEL_Enum;

/* ===========================================  SDIO AUTO NOTAUTOCMD12ERR [7..7]  ============================================ */
typedef enum {                                  /*!< SDIO_AUTO_NOTAUTOCMD12ERR                                                 */
  SDIO_AUTO_NOTAUTOCMD12ERR_NOERROR    = 0,     /*!< NOERROR : No Error                                                        */
  SDIO_AUTO_NOTAUTOCMD12ERR_ERROR      = 1,     /*!< ERROR : Not Issued                                                        */
} SDIO_AUTO_NOTAUTOCMD12ERR_Enum;

/* ==============================================  SDIO AUTO CMDIDXERR [4..4]  =============================================== */
typedef enum {                                  /*!< SDIO_AUTO_CMDIDXERR                                                       */
  SDIO_AUTO_CMDIDXERR_NOERROR          = 0,     /*!< NOERROR : No Error                                                        */
  SDIO_AUTO_CMDIDXERR_ERROR            = 1,     /*!< ERROR : Error                                                             */
} SDIO_AUTO_CMDIDXERR_Enum;

/* ==============================================  SDIO AUTO CMDENDERR [3..3]  =============================================== */
typedef enum {                                  /*!< SDIO_AUTO_CMDENDERR                                                       */
  SDIO_AUTO_CMDENDERR_NOERROR          = 0,     /*!< NOERROR : No Error                                                        */
  SDIO_AUTO_CMDENDERR_ERROR            = 1,     /*!< ERROR : End Bit Error Generated                                           */
} SDIO_AUTO_CMDENDERR_Enum;

/* ==============================================  SDIO AUTO CMDCRCERR [2..2]  =============================================== */
typedef enum {                                  /*!< SDIO_AUTO_CMDCRCERR                                                       */
  SDIO_AUTO_CMDCRCERR_NOERROR          = 0,     /*!< NOERROR : No Error                                                        */
  SDIO_AUTO_CMDCRCERR_ERROR            = 1,     /*!< ERROR : CRC Error Generated                                               */
} SDIO_AUTO_CMDCRCERR_Enum;

/* ===============================================  SDIO AUTO CMDTOERR [1..1]  =============================================== */
typedef enum {                                  /*!< SDIO_AUTO_CMDTOERR                                                        */
  SDIO_AUTO_CMDTOERR_NOERROR           = 0,     /*!< NOERROR : No Error                                                        */
  SDIO_AUTO_CMDTOERR_ERROR             = 1,     /*!< ERROR : Timeout                                                           */
} SDIO_AUTO_CMDTOERR_Enum;

/* =============================================  SDIO AUTO CMD12NOTEXEC [0..0]  ============================================= */
typedef enum {                                  /*!< SDIO_AUTO_CMD12NOTEXEC                                                    */
  SDIO_AUTO_CMD12NOTEXEC_EXECUTED      = 0,     /*!< EXECUTED : Executed                                                       */
  SDIO_AUTO_CMD12NOTEXEC_NOTEXECUTED   = 1,     /*!< NOTEXECUTED : Not Executed                                                */
} SDIO_AUTO_CMD12NOTEXEC_Enum;

/* =====================================================  CAPABILITIES0  ===================================================== */
/* =========================================  SDIO CAPABILITIES0 SLOTTYPE [30..31]  ========================================== */
typedef enum {                                  /*!< SDIO_CAPABILITIES0_SLOTTYPE                                               */
  SDIO_CAPABILITIES0_SLOTTYPE_REMOVABLE = 0,    /*!< REMOVABLE : Removable card slot                                           */
  SDIO_CAPABILITIES0_SLOTTYPE_EMBEDDED = 1,     /*!< EMBEDDED : Embedded Slot for One Device                                   */
  SDIO_CAPABILITIES0_SLOTTYPE_SHARED   = 2,     /*!< SHARED : Shared Bus Slot                                                  */
} SDIO_CAPABILITIES0_SLOTTYPE_Enum;

/* =========================================  SDIO CAPABILITIES0 ASYNCINT [29..29]  ========================================== */
typedef enum {                                  /*!< SDIO_CAPABILITIES0_ASYNCINT                                               */
  SDIO_CAPABILITIES0_ASYNCINT_SUPPORTED = 1,    /*!< SUPPORTED : Asynchronous Interrupt Supported                              */
  SDIO_CAPABILITIES0_ASYNCINT_NOTSUPPORTED = 0, /*!< NOTSUPPORTED : Asynchronous Interrupt Not Supported                       */
} SDIO_CAPABILITIES0_ASYNCINT_Enum;

/* =========================================  SDIO CAPABILITIES0 SYSBUS64 [28..28]  ========================================== */
typedef enum {                                  /*!< SDIO_CAPABILITIES0_SYSBUS64                                               */
  SDIO_CAPABILITIES0_SYSBUS64_SUPPORTED = 1,    /*!< SUPPORTED : Supports 64 bit system address                                */
  SDIO_CAPABILITIES0_SYSBUS64_NOTSUPPORTED = 0, /*!< NOTSUPPORTED : Does not support 64 bit system address                     */
} SDIO_CAPABILITIES0_SYSBUS64_Enum;

/* ==========================================  SDIO CAPABILITIES0 VOLT18V [26..26]  ========================================== */
typedef enum {                                  /*!< SDIO_CAPABILITIES0_VOLT18V                                                */
  SDIO_CAPABILITIES0_VOLT18V_NOTSUPPORTED = 0,  /*!< NOTSUPPORTED : 1.8 V Not Supported                                        */
  SDIO_CAPABILITIES0_VOLT18V_SUPPORTED = 1,     /*!< SUPPORTED : 1.8 V Supported                                               */
} SDIO_CAPABILITIES0_VOLT18V_Enum;

/* ==========================================  SDIO CAPABILITIES0 VOLT30V [25..25]  ========================================== */
typedef enum {                                  /*!< SDIO_CAPABILITIES0_VOLT30V                                                */
  SDIO_CAPABILITIES0_VOLT30V_NOTSUPPORTED = 0,  /*!< NOTSUPPORTED : 3.0 V Not Supported                                        */
  SDIO_CAPABILITIES0_VOLT30V_SUPPORTED = 1,     /*!< SUPPORTED : 3.0 V Supported                                               */
} SDIO_CAPABILITIES0_VOLT30V_Enum;

/* ==========================================  SDIO CAPABILITIES0 VOLT33V [24..24]  ========================================== */
typedef enum {                                  /*!< SDIO_CAPABILITIES0_VOLT33V                                                */
  SDIO_CAPABILITIES0_VOLT33V_NOTSUPPORTED = 0,  /*!< NOTSUPPORTED : 3.3 V Not Supported                                        */
  SDIO_CAPABILITIES0_VOLT33V_SUPPORTED = 1,     /*!< SUPPORTED : 3.3 V Supported                                               */
} SDIO_CAPABILITIES0_VOLT33V_Enum;

/* ==========================================  SDIO CAPABILITIES0 SUSPRES [23..23]  ========================================== */
typedef enum {                                  /*!< SDIO_CAPABILITIES0_SUSPRES                                                */
  SDIO_CAPABILITIES0_SUSPRES_NOTSUPPORTED = 0,  /*!< NOTSUPPORTED : Suspend / Resume Not Supported                             */
  SDIO_CAPABILITIES0_SUSPRES_SUPPORTED = 1,     /*!< SUPPORTED : Suspend / Resume Supported                                    */
} SDIO_CAPABILITIES0_SUSPRES_Enum;

/* ===========================================  SDIO CAPABILITIES0 SDMA [22..22]  ============================================ */
typedef enum {                                  /*!< SDIO_CAPABILITIES0_SDMA                                                   */
  SDIO_CAPABILITIES0_SDMA_NOTSUPPORTED = 0,     /*!< NOTSUPPORTED : SDMA Not Supported                                         */
  SDIO_CAPABILITIES0_SDMA_SUPPORTED    = 1,     /*!< SUPPORTED : SDMA Supported.                                               */
} SDIO_CAPABILITIES0_SDMA_Enum;

/* =========================================  SDIO CAPABILITIES0 HIGHSPEED [21..21]  ========================================= */
typedef enum {                                  /*!< SDIO_CAPABILITIES0_HIGHSPEED                                              */
  SDIO_CAPABILITIES0_HIGHSPEED_NOTSUPPORTED = 0,/*!< NOTSUPPORTED : High Speed Not Supported                                   */
  SDIO_CAPABILITIES0_HIGHSPEED_SUPPORTED = 1,   /*!< SUPPORTED : High Speed Supported                                          */
} SDIO_CAPABILITIES0_HIGHSPEED_Enum;

/* ===========================================  SDIO CAPABILITIES0 ADMA2 [19..19]  =========================================== */
typedef enum {                                  /*!< SDIO_CAPABILITIES0_ADMA2                                                  */
  SDIO_CAPABILITIES0_ADMA2_SUPPORTED   = 1,     /*!< SUPPORTED : ADMA2 support.                                                */
  SDIO_CAPABILITIES0_ADMA2_NOTSUPPORTED = 0,    /*!< NOTSUPPORTED : ADMA2 not support                                          */
} SDIO_CAPABILITIES0_ADMA2_Enum;

/* =========================================  SDIO CAPABILITIES0 EXTMEDIA [18..18]  ========================================== */
typedef enum {                                  /*!< SDIO_CAPABILITIES0_EXTMEDIA                                               */
  SDIO_CAPABILITIES0_EXTMEDIA_SUPPORTED = 1,    /*!< SUPPORTED : Extended Media Bus Supported                                  */
  SDIO_CAPABILITIES0_EXTMEDIA_NOTSUPPORTED = 0, /*!< NOTSUPPORTED : Extended Media Bus not supported                           */
} SDIO_CAPABILITIES0_EXTMEDIA_Enum;

/* =========================================  SDIO CAPABILITIES0 MAXBLKLEN [16..17]  ========================================= */
typedef enum {                                  /*!< SDIO_CAPABILITIES0_MAXBLKLEN                                              */
  SDIO_CAPABILITIES0_MAXBLKLEN_512     = 0,     /*!< 512 : 512 byte                                                            */
  SDIO_CAPABILITIES0_MAXBLKLEN_1024    = 1,     /*!< 1024 : 1024 byte                                                          */
  SDIO_CAPABILITIES0_MAXBLKLEN_2048    = 2,     /*!< 2048 : 2048 byte                                                          */
  SDIO_CAPABILITIES0_MAXBLKLEN_4096    = 3,     /*!< 4096 : 4096 byte                                                          */
} SDIO_CAPABILITIES0_MAXBLKLEN_Enum;

/* =========================================  SDIO CAPABILITIES0 SDCLKFREQ [8..15]  ========================================== */
typedef enum {                                  /*!< SDIO_CAPABILITIES0_SDCLKFREQ                                              */
  SDIO_CAPABILITIES0_SDCLKFREQ_255MHZ  = 255,   /*!< 255MHZ : 2) 8-bit base clock frequency supports frequencies
                                                     10MHz-255MHz.                                                             */
  SDIO_CAPABILITIES0_SDCLKFREQ_63MHZ   = 63,    /*!< 63MHZ : 1) 6-bit base clock frequency supports frequencies 10MHz-63MHz.
                                                     2) 8-bit base clock frequency supports frequencies 10MHz-255MHz.          */
  SDIO_CAPABILITIES0_SDCLKFREQ_2MHZ    = 2,     /*!< 2MHZ : 1) 6-bit base clock frequency supports frequencies 10MHz-63MHz.
                                                     2) 8-bit base clock frequency supports frequencies 10MHz-255MHz.          */
  SDIO_CAPABILITIES0_SDCLKFREQ_1MHZ    = 1,     /*!< 1MHZ : 1) 6-bit base clock frequency supports frequencies 10MHz-63MHz.
                                                     2) 8-bit base clock frequency supports frequencies 10MHz-255MHz.          */
  SDIO_CAPABILITIES0_SDCLKFREQ_OTHER   = 0,     /*!< OTHER : Get information via another method                                */
} SDIO_CAPABILITIES0_SDCLKFREQ_Enum;

/* ==========================================  SDIO CAPABILITIES0 TOCLKUNIT [7..7]  ========================================== */
typedef enum {                                  /*!< SDIO_CAPABILITIES0_TOCLKUNIT                                              */
  SDIO_CAPABILITIES0_TOCLKUNIT_KHZ     = 0,     /*!< KHZ : Khz                                                                 */
  SDIO_CAPABILITIES0_TOCLKUNIT_MHZ     = 1,     /*!< MHZ : Mhz                                                                 */
} SDIO_CAPABILITIES0_TOCLKUNIT_Enum;

/* ==========================================  SDIO CAPABILITIES0 TOCLKFREQ [0..5]  ========================================== */
typedef enum {                                  /*!< SDIO_CAPABILITIES0_TOCLKFREQ                                              */
  SDIO_CAPABILITIES0_TOCLKFREQ_1       = 1,     /*!< 1 : 1KHZ or 1MHZ                                                          */
  SDIO_CAPABILITIES0_TOCLKFREQ_2       = 2,     /*!< 2 : 2KHZ or 2MHZ                                                          */
  SDIO_CAPABILITIES0_TOCLKFREQ_63      = 63,    /*!< 63 : 63KHZ or 63MHZ                                                       */
  SDIO_CAPABILITIES0_TOCLKFREQ_OTHER   = 0,     /*!< OTHER : Get Information via another method.                               */
} SDIO_CAPABILITIES0_TOCLKFREQ_Enum;

/* =====================================================  CAPABILITIES1  ===================================================== */
/* =======================================  SDIO CAPABILITIES1 SPIBLOCKMODE [25..25]  ======================================== */
typedef enum {                                  /*!< SDIO_CAPABILITIES1_SPIBLOCKMODE                                           */
  SDIO_CAPABILITIES1_SPIBLOCKMODE_NOTSUPPORTED = 0,/*!< NOTSUPPORTED : Not Supported                                           */
  SDIO_CAPABILITIES1_SPIBLOCKMODE_SUPPORTED = 1,/*!< SUPPORTED : Supported                                                     */
} SDIO_CAPABILITIES1_SPIBLOCKMODE_Enum;

/* ==========================================  SDIO CAPABILITIES1 SPIMODE [24..24]  ========================================== */
typedef enum {                                  /*!< SDIO_CAPABILITIES1_SPIMODE                                                */
  SDIO_CAPABILITIES1_SPIMODE_NOTSUPPORTED = 0,  /*!< NOTSUPPORTED : Not Supported                                              */
  SDIO_CAPABILITIES1_SPIMODE_SUPPORTED = 1,     /*!< SUPPORTED : Supported                                                     */
} SDIO_CAPABILITIES1_SPIMODE_Enum;

/* ==========================================  SDIO CAPABILITIES1 CLKMULT [16..23]  ========================================== */
typedef enum {                                  /*!< SDIO_CAPABILITIES1_CLKMULT                                                */
  SDIO_CAPABILITIES1_CLKMULT_MULTX256  = 255,   /*!< MULTX256 : Clock Multiplier M = 256                                       */
  SDIO_CAPABILITIES1_CLKMULT_MULTX3    = 2,     /*!< MULTX3 : Clock Multiplier M = 3                                           */
  SDIO_CAPABILITIES1_CLKMULT_MULTX2    = 1,     /*!< MULTX2 : Clock Multiplier M = 2                                           */
  SDIO_CAPABILITIES1_CLKMULT_NOTSUPPORTED = 0,  /*!< NOTSUPPORTED : Clock Multiplier is Not Supported                          */
} SDIO_CAPABILITIES1_CLKMULT_Enum;

/* =======================================  SDIO CAPABILITIES1 RETUNINGMODES [14..15]  ======================================= */
typedef enum {                                  /*!< SDIO_CAPABILITIES1_RETUNINGMODES                                          */
  SDIO_CAPABILITIES1_RETUNINGMODES_MODE1 = 0,   /*!< MODE1 : Mode1                                                             */
  SDIO_CAPABILITIES1_RETUNINGMODES_MODE2 = 1,   /*!< MODE2 : Mode2                                                             */
  SDIO_CAPABILITIES1_RETUNINGMODES_MODE3 = 2,   /*!< MODE3 : Mode3                                                             */
  SDIO_CAPABILITIES1_RETUNINGMODES_NOTSUPPORTED = 3,/*!< NOTSUPPORTED : Clock Multiplier is not supported.                     */
} SDIO_CAPABILITIES1_RETUNINGMODES_Enum;

/* ========================================  SDIO CAPABILITIES1 TUNINGSDR50 [13..13]  ======================================== */
typedef enum {                                  /*!< SDIO_CAPABILITIES1_TUNINGSDR50                                            */
  SDIO_CAPABILITIES1_TUNINGSDR50_TUNINGREQD = 1,/*!< TUNINGREQD : SDR50 requires tuning                                        */
  SDIO_CAPABILITIES1_TUNINGSDR50_NOTUNINGREQD = 0,/*!< NOTUNINGREQD : SDR50 does not require tuning                            */
} SDIO_CAPABILITIES1_TUNINGSDR50_Enum;

/* =======================================  SDIO CAPABILITIES1 RETUNINGTMRCNT [8..11]  ======================================= */
typedef enum {                                  /*!< SDIO_CAPABILITIES1_RETUNINGTMRCNT                                         */
  SDIO_CAPABILITIES1_RETUNINGTMRCNT_OTHER = 0,  /*!< OTHER : 0h Get information via other source.                              */
  SDIO_CAPABILITIES1_RETUNINGTMRCNT_1SEC = 1,   /*!< 1SEC : 1 seconds                                                          */
  SDIO_CAPABILITIES1_RETUNINGTMRCNT_2SEC = 2,   /*!< 2SEC : 2 seconds                                                          */
  SDIO_CAPABILITIES1_RETUNINGTMRCNT_4SEC = 3,   /*!< 4SEC : 4 seconds                                                          */
  SDIO_CAPABILITIES1_RETUNINGTMRCNT_8S = 4,     /*!< 8S : 8 seconds                                                            */
  SDIO_CAPABILITIES1_RETUNINGTMRCNT_16S = 5,    /*!< 16S : 16 seconds                                                          */
  SDIO_CAPABILITIES1_RETUNINGTMRCNT_32S = 6,    /*!< 32S : 32 seconds                                                          */
  SDIO_CAPABILITIES1_RETUNINGTMRCNT_64S = 7,    /*!< 64S : 64 seconds                                                          */
  SDIO_CAPABILITIES1_RETUNINGTMRCNT_128S = 8,   /*!< 128S : 128 seconds                                                        */
  SDIO_CAPABILITIES1_RETUNINGTMRCNT_256S = 9,   /*!< 256S : 256 seconds                                                        */
  SDIO_CAPABILITIES1_RETUNINGTMRCNT_512S = 10,  /*!< 512S : 512 seconds                                                        */
  SDIO_CAPABILITIES1_RETUNINGTMRCNT_1024S = 11, /*!< 1024S : 1024 seconds                                                      */
} SDIO_CAPABILITIES1_RETUNINGTMRCNT_Enum;

/* ============================================  SDIO CAPABILITIES1 TYPED [6..6]  ============================================ */
typedef enum {                                  /*!< SDIO_CAPABILITIES1_TYPED                                                  */
  SDIO_CAPABILITIES1_TYPED_SUPPORTED   = 1,     /*!< SUPPORTED : Driver Type D is Supported                                    */
  SDIO_CAPABILITIES1_TYPED_NOTSUPPORTED = 0,    /*!< NOTSUPPORTED : Driver Type D is Not Supported                             */
} SDIO_CAPABILITIES1_TYPED_Enum;

/* ============================================  SDIO CAPABILITIES1 TYPEC [5..5]  ============================================ */
typedef enum {                                  /*!< SDIO_CAPABILITIES1_TYPEC                                                  */
  SDIO_CAPABILITIES1_TYPEC_SUPPORTED   = 1,     /*!< SUPPORTED : Driver Type C is Supported                                    */
  SDIO_CAPABILITIES1_TYPEC_NOTSUPPORTED = 0,    /*!< NOTSUPPORTED : Driver Type C is Not Supported                             */
} SDIO_CAPABILITIES1_TYPEC_Enum;

/* ============================================  SDIO CAPABILITIES1 TYPEA [4..4]  ============================================ */
typedef enum {                                  /*!< SDIO_CAPABILITIES1_TYPEA                                                  */
  SDIO_CAPABILITIES1_TYPEA_SUPPORTED   = 1,     /*!< SUPPORTED : Driver Type A is Supported                                    */
  SDIO_CAPABILITIES1_TYPEA_NOTSUPPORTED = 0,    /*!< NOTSUPPORTED : Driver Type A is Not Supported                             */
} SDIO_CAPABILITIES1_TYPEA_Enum;

/* ============================================  SDIO CAPABILITIES1 DDR50 [2..2]  ============================================ */
typedef enum {                                  /*!< SDIO_CAPABILITIES1_DDR50                                                  */
  SDIO_CAPABILITIES1_DDR50_SUPPORTED   = 1,     /*!< SUPPORTED : DDR50 is Supported                                            */
  SDIO_CAPABILITIES1_DDR50_NOTSUPPORTED = 0,    /*!< NOTSUPPORTED : DDR50 is Not Supported                                     */
} SDIO_CAPABILITIES1_DDR50_Enum;

/* ===========================================  SDIO CAPABILITIES1 SDR104 [1..1]  ============================================ */
typedef enum {                                  /*!< SDIO_CAPABILITIES1_SDR104                                                 */
  SDIO_CAPABILITIES1_SDR104_SUPPORTED  = 1,     /*!< SUPPORTED : SDR104 is Not Supported                                       */
  SDIO_CAPABILITIES1_SDR104_NOTSUPPORTED = 0,   /*!< NOTSUPPORTED : SDR104 is Not Supported                                    */
} SDIO_CAPABILITIES1_SDR104_Enum;

/* ============================================  SDIO CAPABILITIES1 SDR50 [0..0]  ============================================ */
typedef enum {                                  /*!< SDIO_CAPABILITIES1_SDR50                                                  */
  SDIO_CAPABILITIES1_SDR50_SUPPORTED   = 1,     /*!< SUPPORTED : SDR50 is Not Supported                                        */
  SDIO_CAPABILITIES1_SDR50_NOTSUPPORTED = 0,    /*!< NOTSUPPORTED : SDR50 is Not Supported                                     */
} SDIO_CAPABILITIES1_SDR50_Enum;

/* =======================================================  MAXIMUM0  ======================================================== */
/* =======================================================  MAXIMUM1  ======================================================== */
/* ===========================================  SDIO MAXIMUM1 MAXCURR18V [16..23]  =========================================== */
typedef enum {                                  /*!< SDIO_MAXIMUM1_MAXCURR18V                                                  */
  SDIO_MAXIMUM1_MAXCURR18V_1020mA      = 255,   /*!< 1020mA : 1020mA = 255 * 4mA                                               */
  SDIO_MAXIMUM1_MAXCURR18V_4mA         = 1,     /*!< 4mA : 1020mA, 255 * 4mA                                                   */
} SDIO_MAXIMUM1_MAXCURR18V_Enum;

/* ===========================================  SDIO MAXIMUM1 MAXCURR30V [8..15]  ============================================ */
typedef enum {                                  /*!< SDIO_MAXIMUM1_MAXCURR30V                                                  */
  SDIO_MAXIMUM1_MAXCURR30V_1020mA      = 255,   /*!< 1020mA : 1020mA = 255 * 4mA                                               */
  SDIO_MAXIMUM1_MAXCURR30V_4mA         = 1,     /*!< 4mA : 1020mA, 255 * 4mA                                                   */
} SDIO_MAXIMUM1_MAXCURR30V_Enum;

/* ============================================  SDIO MAXIMUM1 MAXCURR33V [0..7]  ============================================ */
typedef enum {                                  /*!< SDIO_MAXIMUM1_MAXCURR33V                                                  */
  SDIO_MAXIMUM1_MAXCURR33V_1020mA      = 255,   /*!< 1020mA : 1020mA = 255 * 4mA                                               */
  SDIO_MAXIMUM1_MAXCURR33V_4mA         = 1,     /*!< 4mA : 1020mA, 255 * 4mA                                                   */
} SDIO_MAXIMUM1_MAXCURR33V_Enum;

/* =========================================================  FORCE  ========================================================= */
/* ===========================================  SDIO FORCE FORCEADMAERR [25..25]  ============================================ */
typedef enum {                                  /*!< SDIO_FORCE_FORCEADMAERR                                                   */
  SDIO_FORCE_FORCEADMAERR_INT          = 1,     /*!< INT : Interrupt is generated                                              */
  SDIO_FORCE_FORCEADMAERR_NOINT        = 0,     /*!< NOINT : No interrupt                                                      */
} SDIO_FORCE_FORCEADMAERR_Enum;

/* ===========================================  SDIO FORCE FORCEACMDERR [24..24]  ============================================ */
typedef enum {                                  /*!< SDIO_FORCE_FORCEACMDERR                                                   */
  SDIO_FORCE_FORCEACMDERR_INT          = 1,     /*!< INT : Interrupt is generated                                              */
  SDIO_FORCE_FORCEACMDERR_NOINT        = 0,     /*!< NOINT : No interrupt                                                      */
} SDIO_FORCE_FORCEACMDERR_Enum;

/* =========================================  SDIO FORCE FORCECURRLIMITERR [23..23]  ========================================= */
typedef enum {                                  /*!< SDIO_FORCE_FORCECURRLIMITERR                                              */
  SDIO_FORCE_FORCECURRLIMITERR_INT     = 1,     /*!< INT : Interrupt is generated                                              */
  SDIO_FORCE_FORCECURRLIMITERR_NOINT   = 0,     /*!< NOINT : No interrupt                                                      */
} SDIO_FORCE_FORCECURRLIMITERR_Enum;

/* ==========================================  SDIO FORCE FORCEDATAENDERR [22..22]  ========================================== */
typedef enum {                                  /*!< SDIO_FORCE_FORCEDATAENDERR                                                */
  SDIO_FORCE_FORCEDATAENDERR_INT       = 1,     /*!< INT : Interrupt is generated                                              */
  SDIO_FORCE_FORCEDATAENDERR_NOINT     = 0,     /*!< NOINT : No interrupt                                                      */
} SDIO_FORCE_FORCEDATAENDERR_Enum;

/* ==========================================  SDIO FORCE FORCEDATACRCERR [21..21]  ========================================== */
typedef enum {                                  /*!< SDIO_FORCE_FORCEDATACRCERR                                                */
  SDIO_FORCE_FORCEDATACRCERR_INT       = 1,     /*!< INT : Interrupt is generated                                              */
  SDIO_FORCE_FORCEDATACRCERR_NOINT     = 0,     /*!< NOINT : No interrupt                                                      */
} SDIO_FORCE_FORCEDATACRCERR_Enum;

/* ==========================================  SDIO FORCE FORCEDATATOERR [20..20]  =========================================== */
typedef enum {                                  /*!< SDIO_FORCE_FORCEDATATOERR                                                 */
  SDIO_FORCE_FORCEDATATOERR_INT        = 1,     /*!< INT : Interrupt is generated                                              */
  SDIO_FORCE_FORCEDATATOERR_NOINT      = 0,     /*!< NOINT : No interrupt                                                      */
} SDIO_FORCE_FORCEDATATOERR_Enum;

/* ==========================================  SDIO FORCE FORCECMDIDXERR [19..19]  =========================================== */
typedef enum {                                  /*!< SDIO_FORCE_FORCECMDIDXERR                                                 */
  SDIO_FORCE_FORCECMDIDXERR_INT        = 1,     /*!< INT : Interrupt is generated                                              */
  SDIO_FORCE_FORCECMDIDXERR_NOINT      = 0,     /*!< NOINT : No interrupt                                                      */
} SDIO_FORCE_FORCECMDIDXERR_Enum;

/* ==========================================  SDIO FORCE FORCECMDENDERR [18..18]  =========================================== */
typedef enum {                                  /*!< SDIO_FORCE_FORCECMDENDERR                                                 */
  SDIO_FORCE_FORCECMDENDERR_INT        = 1,     /*!< INT : Interrupt is generated                                              */
  SDIO_FORCE_FORCECMDENDERR_NOINT      = 0,     /*!< NOINT : No interrupt                                                      */
} SDIO_FORCE_FORCECMDENDERR_Enum;

/* ==========================================  SDIO FORCE FORCECMDCRCERR [17..17]  =========================================== */
typedef enum {                                  /*!< SDIO_FORCE_FORCECMDCRCERR                                                 */
  SDIO_FORCE_FORCECMDCRCERR_INT        = 1,     /*!< INT : Interrupt is generated                                              */
  SDIO_FORCE_FORCECMDCRCERR_NOINT      = 0,     /*!< NOINT : No interrupt                                                      */
} SDIO_FORCE_FORCECMDCRCERR_Enum;

/* ===========================================  SDIO FORCE FORCECMDTOERR [16..16]  =========================================== */
typedef enum {                                  /*!< SDIO_FORCE_FORCECMDTOERR                                                  */
  SDIO_FORCE_FORCECMDTOERR_INT         = 1,     /*!< INT : Interrupt is generated                                              */
  SDIO_FORCE_FORCECMDTOERR_NOINT       = 0,     /*!< NOINT : No interrupt                                                      */
} SDIO_FORCE_FORCECMDTOERR_Enum;

/* =========================================  SDIO FORCE FORCEACMDISSUEDERR [7..7]  ========================================== */
typedef enum {                                  /*!< SDIO_FORCE_FORCEACMDISSUEDERR                                             */
  SDIO_FORCE_FORCEACMDISSUEDERR_INT    = 1,     /*!< INT : Interrupt is generated                                              */
  SDIO_FORCE_FORCEACMDISSUEDERR_NOINT  = 0,     /*!< NOINT : no interrupt                                                      */
} SDIO_FORCE_FORCEACMDISSUEDERR_Enum;

/* ===========================================  SDIO FORCE FORCEACMDIDXERR [4..4]  =========================================== */
typedef enum {                                  /*!< SDIO_FORCE_FORCEACMDIDXERR                                                */
  SDIO_FORCE_FORCEACMDIDXERR_INT       = 1,     /*!< INT : Interrupt is generated                                              */
  SDIO_FORCE_FORCEACMDIDXERR_NOINT     = 0,     /*!< NOINT : no interrupt                                                      */
} SDIO_FORCE_FORCEACMDIDXERR_Enum;

/* ===========================================  SDIO FORCE FORCEACMDENDERR [3..3]  =========================================== */
typedef enum {                                  /*!< SDIO_FORCE_FORCEACMDENDERR                                                */
  SDIO_FORCE_FORCEACMDENDERR_INT       = 1,     /*!< INT : Interrupt is generated                                              */
  SDIO_FORCE_FORCEACMDENDERR_NOINT     = 0,     /*!< NOINT : no interrupt                                                      */
} SDIO_FORCE_FORCEACMDENDERR_Enum;

/* ===========================================  SDIO FORCE FORCEACMDCRCERR [2..2]  =========================================== */
typedef enum {                                  /*!< SDIO_FORCE_FORCEACMDCRCERR                                                */
  SDIO_FORCE_FORCEACMDCRCERR_INT       = 1,     /*!< INT : Interrupt is generated                                              */
  SDIO_FORCE_FORCEACMDCRCERR_NOINT     = 0,     /*!< NOINT : no interrupt                                                      */
} SDIO_FORCE_FORCEACMDCRCERR_Enum;

/* ===========================================  SDIO FORCE FORCEACMDTOERR [1..1]  ============================================ */
typedef enum {                                  /*!< SDIO_FORCE_FORCEACMDTOERR                                                 */
  SDIO_FORCE_FORCEACMDTOERR_INT        = 1,     /*!< INT : Interrupt is generated                                              */
  SDIO_FORCE_FORCEACMDTOERR_NOINT      = 0,     /*!< NOINT : no interrupt                                                      */
} SDIO_FORCE_FORCEACMDTOERR_Enum;

/* ===========================================  SDIO FORCE FORCEACMD12NOT [0..0]  ============================================ */
typedef enum {                                  /*!< SDIO_FORCE_FORCEACMD12NOT                                                 */
  SDIO_FORCE_FORCEACMD12NOT_INT        = 1,     /*!< INT : Interrupt is generated                                              */
  SDIO_FORCE_FORCEACMD12NOT_NOINT      = 0,     /*!< NOINT : no interrupt                                                      */
} SDIO_FORCE_FORCEACMD12NOT_Enum;

/* =========================================================  ADMA  ========================================================== */
/* ==========================================  SDIO ADMA ADMALENMISMATCHERR [2..2]  ========================================== */
typedef enum {                                  /*!< SDIO_ADMA_ADMALENMISMATCHERR                                              */
  SDIO_ADMA_ADMALENMISMATCHERR_ERROR   = 1,     /*!< ERROR : Error                                                             */
  SDIO_ADMA_ADMALENMISMATCHERR_NOERROR = 0,     /*!< NOERROR : No error                                                        */
} SDIO_ADMA_ADMALENMISMATCHERR_Enum;

/* ============================================  SDIO ADMA ADMAERRORSTATE [0..1]  ============================================ */
typedef enum {                                  /*!< SDIO_ADMA_ADMAERRORSTATE                                                  */
  SDIO_ADMA_ADMAERRORSTATE_STDMA       = 0,     /*!< STDMA : ST_STOP (Stop DMA) Points to next of the error descriptor         */
  SDIO_ADMA_ADMAERRORSTATE_FETCHDESC   = 1,     /*!< FETCHDESC : ST_FDS (Fetch Descriptor) Points to the error descriptor      */
  SDIO_ADMA_ADMAERRORSTATE_INVALID     = 2,     /*!< INVALID : Never set this state (Not used)                                 */
  SDIO_ADMA_ADMAERRORSTATE_XFERDATA    = 3,     /*!< XFERDATA : ST_TFR (Transfer Data) Points to the next of the
                                                     error descriptor                                                          */
} SDIO_ADMA_ADMAERRORSTATE_Enum;

/* =======================================================  ADMALOWD  ======================================================== */
/* =======================================================  ADMAHIWD  ======================================================== */
/* ========================================================  PRESET0  ======================================================== */
/* =========================================  SDIO PRESET0 DEFSPDRVRSTRSEL [30..31]  ========================================= */
typedef enum {                                  /*!< SDIO_PRESET0_DEFSPDRVRSTRSEL                                              */
  SDIO_PRESET0_DEFSPDRVRSTRSEL_TYPED   = 3,     /*!< TYPED : Driver Type D is Selected                                         */
  SDIO_PRESET0_DEFSPDRVRSTRSEL_TYPEC   = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
  SDIO_PRESET0_DEFSPDRVRSTRSEL_TYPEA   = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
  SDIO_PRESET0_DEFSPDRVRSTRSEL_TYPEB   = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
} SDIO_PRESET0_DEFSPDRVRSTRSEL_Enum;

/* =========================================  SDIO PRESET0 DEFSPCLKGENSEL [26..26]  ========================================== */
typedef enum {                                  /*!< SDIO_PRESET0_DEFSPCLKGENSEL                                               */
  SDIO_PRESET0_DEFSPCLKGENSEL_PROGCLK  = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
  SDIO_PRESET0_DEFSPCLKGENSEL_HOSTCTLR = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
} SDIO_PRESET0_DEFSPCLKGENSEL_Enum;

/* =========================================  SDIO PRESET0 HISPDRVRSTRSEL [14..15]  ========================================== */
typedef enum {                                  /*!< SDIO_PRESET0_HISPDRVRSTRSEL                                               */
  SDIO_PRESET0_HISPDRVRSTRSEL_TYPED    = 3,     /*!< TYPED : Driver Type D is Selected                                         */
  SDIO_PRESET0_HISPDRVRSTRSEL_TYPEC    = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
  SDIO_PRESET0_HISPDRVRSTRSEL_TYPEA    = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
  SDIO_PRESET0_HISPDRVRSTRSEL_TYPEB    = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
} SDIO_PRESET0_HISPDRVRSTRSEL_Enum;

/* ==========================================  SDIO PRESET0 HISPCLKGENSEL [10..10]  ========================================== */
typedef enum {                                  /*!< SDIO_PRESET0_HISPCLKGENSEL                                                */
  SDIO_PRESET0_HISPCLKGENSEL_PROGCLK   = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
  SDIO_PRESET0_HISPCLKGENSEL_HOSTCTLR  = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
} SDIO_PRESET0_HISPCLKGENSEL_Enum;

/* ========================================================  PRESET1  ======================================================== */
/* =========================================  SDIO PRESET1 SDR12DRVRSTRSEL [30..31]  ========================================= */
typedef enum {                                  /*!< SDIO_PRESET1_SDR12DRVRSTRSEL                                              */
  SDIO_PRESET1_SDR12DRVRSTRSEL_TYPED   = 3,     /*!< TYPED : Driver Type D is Selected                                         */
  SDIO_PRESET1_SDR12DRVRSTRSEL_TYPEC   = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
  SDIO_PRESET1_SDR12DRVRSTRSEL_TYPEA   = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
  SDIO_PRESET1_SDR12DRVRSTRSEL_TYPEB   = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
} SDIO_PRESET1_SDR12DRVRSTRSEL_Enum;

/* =========================================  SDIO PRESET1 SDR12CLKGENSEL [26..26]  ========================================== */
typedef enum {                                  /*!< SDIO_PRESET1_SDR12CLKGENSEL                                               */
  SDIO_PRESET1_SDR12CLKGENSEL_PROGCLK  = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
  SDIO_PRESET1_SDR12CLKGENSEL_HOSTCTLR = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
} SDIO_PRESET1_SDR12CLKGENSEL_Enum;

/* ==========================================  SDIO PRESET1 HSDRVRSTRSEL [14..15]  =========================================== */
typedef enum {                                  /*!< SDIO_PRESET1_HSDRVRSTRSEL                                                 */
  SDIO_PRESET1_HSDRVRSTRSEL_TYPED      = 3,     /*!< TYPED : Driver Type D is Selected                                         */
  SDIO_PRESET1_HSDRVRSTRSEL_TYPEC      = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
  SDIO_PRESET1_HSDRVRSTRSEL_TYPEA      = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
  SDIO_PRESET1_HSDRVRSTRSEL_TYPEB      = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
} SDIO_PRESET1_HSDRVRSTRSEL_Enum;

/* ===========================================  SDIO PRESET1 HSCLKGENSEL [10..10]  =========================================== */
typedef enum {                                  /*!< SDIO_PRESET1_HSCLKGENSEL                                                  */
  SDIO_PRESET1_HSCLKGENSEL_PROGCLK     = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
  SDIO_PRESET1_HSCLKGENSEL_HOSTCTLR    = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
} SDIO_PRESET1_HSCLKGENSEL_Enum;

/* ========================================================  PRESET2  ======================================================== */
/* =========================================  SDIO PRESET2 SDR50DRVRSTRSEL [30..31]  ========================================= */
typedef enum {                                  /*!< SDIO_PRESET2_SDR50DRVRSTRSEL                                              */
  SDIO_PRESET2_SDR50DRVRSTRSEL_TYPED   = 3,     /*!< TYPED : Driver Type D is Selected                                         */
  SDIO_PRESET2_SDR50DRVRSTRSEL_TYPEC   = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
  SDIO_PRESET2_SDR50DRVRSTRSEL_TYPEA   = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
  SDIO_PRESET2_SDR50DRVRSTRSEL_TYPEB   = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
} SDIO_PRESET2_SDR50DRVRSTRSEL_Enum;

/* =========================================  SDIO PRESET2 SDR50CLKGENSEL [26..26]  ========================================== */
typedef enum {                                  /*!< SDIO_PRESET2_SDR50CLKGENSEL                                               */
  SDIO_PRESET2_SDR50CLKGENSEL_PROGCLK  = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
  SDIO_PRESET2_SDR50CLKGENSEL_HOSTCTLR = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
} SDIO_PRESET2_SDR50CLKGENSEL_Enum;

/* =========================================  SDIO PRESET2 SDR25DRVRSTRSEL [14..15]  ========================================= */
typedef enum {                                  /*!< SDIO_PRESET2_SDR25DRVRSTRSEL                                              */
  SDIO_PRESET2_SDR25DRVRSTRSEL_TYPED   = 3,     /*!< TYPED : Driver Type D is Selected                                         */
  SDIO_PRESET2_SDR25DRVRSTRSEL_TYPEC   = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
  SDIO_PRESET2_SDR25DRVRSTRSEL_TYPEA   = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
  SDIO_PRESET2_SDR25DRVRSTRSEL_TYPEB   = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
} SDIO_PRESET2_SDR25DRVRSTRSEL_Enum;

/* =========================================  SDIO PRESET2 SDR25CLKGENSEL [10..10]  ========================================== */
typedef enum {                                  /*!< SDIO_PRESET2_SDR25CLKGENSEL                                               */
  SDIO_PRESET2_SDR25CLKGENSEL_PROGCLK  = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
  SDIO_PRESET2_SDR25CLKGENSEL_HOSTCTLR = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
} SDIO_PRESET2_SDR25CLKGENSEL_Enum;

/* ========================================================  PRESET3  ======================================================== */
/* =========================================  SDIO PRESET3 DDR50DRVRSTRSEL [30..31]  ========================================= */
typedef enum {                                  /*!< SDIO_PRESET3_DDR50DRVRSTRSEL                                              */
  SDIO_PRESET3_DDR50DRVRSTRSEL_TYPED   = 3,     /*!< TYPED : Driver Type D is Selected                                         */
  SDIO_PRESET3_DDR50DRVRSTRSEL_TYPEC   = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
  SDIO_PRESET3_DDR50DRVRSTRSEL_TYPEA   = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
  SDIO_PRESET3_DDR50DRVRSTRSEL_TYPEB   = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
} SDIO_PRESET3_DDR50DRVRSTRSEL_Enum;

/* =========================================  SDIO PRESET3 DDR50CLKGENSEL [26..26]  ========================================== */
typedef enum {                                  /*!< SDIO_PRESET3_DDR50CLKGENSEL                                               */
  SDIO_PRESET3_DDR50CLKGENSEL_PROGCLK  = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
  SDIO_PRESET3_DDR50CLKGENSEL_HOSTCTLR = 0,     /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
} SDIO_PRESET3_DDR50CLKGENSEL_Enum;

/* ========================================  SDIO PRESET3 SDR104DRVRSTRSEL [14..15]  ========================================= */
typedef enum {                                  /*!< SDIO_PRESET3_SDR104DRVRSTRSEL                                             */
  SDIO_PRESET3_SDR104DRVRSTRSEL_TYPED  = 3,     /*!< TYPED : Driver Type D is Selected                                         */
  SDIO_PRESET3_SDR104DRVRSTRSEL_TYPEC  = 2,     /*!< TYPEC : Driver Type C is Selected                                         */
  SDIO_PRESET3_SDR104DRVRSTRSEL_TYPEA  = 1,     /*!< TYPEA : Driver Type A is Selected                                         */
  SDIO_PRESET3_SDR104DRVRSTRSEL_TYPEB  = 0,     /*!< TYPEB : Driver Type B is Selected                                         */
} SDIO_PRESET3_SDR104DRVRSTRSEL_Enum;

/* =========================================  SDIO PRESET3 SDR104CLKGENSEL [10..10]  ========================================= */
typedef enum {                                  /*!< SDIO_PRESET3_SDR104CLKGENSEL                                              */
  SDIO_PRESET3_SDR104CLKGENSEL_PROGCLK = 1,     /*!< PROGCLK : Programmable Clock Generator                                    */
  SDIO_PRESET3_SDR104CLKGENSEL_HOSTCTLR = 0,    /*!< HOSTCTLR : Host Controller Ver2.00 Compatible Clock Generator             */
} SDIO_PRESET3_SDR104CLKGENSEL_Enum;

/* ======================================================  BOOTTOCTRL  ======================================================= */
/* ========================================================  VENDOR  ========================================================= */
/* ===============================================  SDIO VENDOR DLYDIS [1..1]  =============================================== */
typedef enum {                                  /*!< SDIO_VENDOR_DLYDIS                                                        */
  SDIO_VENDOR_DLYDIS_DISABLE           = 1,     /*!< DISABLE : Disable the rtl fix made to delay the sampling of
                                                     cmd_in and data_in                                                        */
  SDIO_VENDOR_DLYDIS_ENABLE            = 0,     /*!< ENABLE : Enable the rtl fix made to delay the sampling of cmd_in
                                                     and data_in                                                               */
} SDIO_VENDOR_DLYDIS_Enum;

/* ============================================  SDIO VENDOR GATESDCLKEN [0..0]  ============================================= */
typedef enum {                                  /*!< SDIO_VENDOR_GATESDCLKEN                                                   */
  SDIO_VENDOR_GATESDCLKEN_GATE         = 1,     /*!< GATE : SD_CLK to card will be gated automatically when there
                                                     is no transfer.                                                           */
  SDIO_VENDOR_GATESDCLKEN_NOGATE       = 0,     /*!< NOGATE : SD_CLK to card will NOT be gated automatically when
                                                     there is no transfer.                                                     */
} SDIO_VENDOR_GATESDCLKEN_Enum;

/* =======================================================  SLOTSTAT  ======================================================== */


/* =========================================================================================================================== */
/* ================                                         SECURITY                                          ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
/* =============================================  SECURITY CTRL FUNCTION [4..7]  ============================================= */
typedef enum {                                  /*!< SECURITY_CTRL_FUNCTION                                                    */
  SECURITY_CTRL_FUNCTION_CRC32         = 0,     /*!< CRC32 : Perform CRC32 operation                                           */
  SECURITY_CTRL_FUNCTION_RAND          = 1,     /*!< RAND : DMA pseudo-random number stream based on CRC value                 */
  SECURITY_CTRL_FUNCTION_GENADDR       = 2,     /*!< GENADDR : Generate DMA stream based on address                            */
} SECURITY_CTRL_FUNCTION_Enum;

/* ========================================================  SRCADDR  ======================================================== */
/* ==========================================================  LEN  ========================================================== */
/* ========================================================  RESULT  ========================================================= */
/* =======================================================  LOCKCTRL  ======================================================== */
/* ============================================  SECURITY LOCKCTRL SELECT [0..7]  ============================================ */
typedef enum {                                  /*!< SECURITY_LOCKCTRL_SELECT                                                  */
  SECURITY_LOCKCTRL_SELECT_LOCK01      = 1,     /*!< LOCK01 : Enable customer OTP program.                                     */
  SECURITY_LOCKCTRL_SELECT_LOCK02      = 2,     /*!< LOCK02 : Enable customer OTP read.                                        */
  SECURITY_LOCKCTRL_SELECT_LOCK11      = 17,    /*!< LOCK11 : Enable Ambiq OTP program.                                        */
  SECURITY_LOCKCTRL_SELECT_LOCK12      = 18,    /*!< LOCK12 : Enable Ambiq OTP read.                                           */
  SECURITY_LOCKCTRL_SELECT_LOCK9D      = 157,   /*!< LOCK9D : Enable Bootloader Recovery.                                      */
  SECURITY_LOCKCTRL_SELECT_LOCK9E      = 158,   /*!< LOCK9E : Enable Bootloader info1.                                         */
  SECURITY_LOCKCTRL_SELECT_RESET       = 0,     /*!< RESET : Reset all.                                                        */
} SECURITY_LOCKCTRL_SELECT_Enum;

/* =======================================================  LOCKSTAT  ======================================================== */
/* ===========================================  SECURITY LOCKSTAT STATUS [0..31]  ============================================ */
typedef enum {                                  /*!< SECURITY_LOCKSTAT_STATUS                                                  */
  SECURITY_LOCKSTAT_STATUS_LOCK01      = 1,     /*!< LOCK01 : Enabled customer OTP program.                                    */
  SECURITY_LOCKSTAT_STATUS_LOCK02      = 2,     /*!< LOCK02 : Enabled customer OTP read.                                       */
  SECURITY_LOCKSTAT_STATUS_LOCK11      = 16,    /*!< LOCK11 : Enabled Ambiq OTP program.                                       */
  SECURITY_LOCKSTAT_STATUS_LOCK12      = 32,    /*!< LOCK12 : Enabled Ambiq OTP read.                                          */
  SECURITY_LOCKSTAT_STATUS_LOCK9D      = 1073741824,/*!< LOCK9D : Enabled Bootloader Recovery.                                 */
  SECURITY_LOCKSTAT_STATUS_LOCK9E      = -2147483648,/*!< LOCK9E : Enabled Bootloader info1.                                   */
  SECURITY_LOCKSTAT_STATUS_RESET       = 0,     /*!< RESET : All Reset.                                                        */
} SECURITY_LOCKSTAT_STATUS_Enum;

/* =========================================================  KEY0  ========================================================== */
/* =========================================================  KEY1  ========================================================== */
/* =========================================================  KEY2  ========================================================== */
/* =========================================================  KEY3  ========================================================== */


/* =========================================================================================================================== */
/* ================                                          STIMER                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  STCFG  ========================================================= */
/* =============================================  STIMER STCFG FREEZE [31..31]  ============================================== */
typedef enum {                                  /*!< STIMER_STCFG_FREEZE                                                       */
  STIMER_STCFG_FREEZE_THAW             = 0,     /*!< THAW : Let the COUNTER register run on its input clock.                   */
  STIMER_STCFG_FREEZE_FREEZE           = 1,     /*!< FREEZE : Stop the COUNTER register for loading.                           */
} STIMER_STCFG_FREEZE_Enum;

/* ==============================================  STIMER STCFG CLEAR [30..30]  ============================================== */
typedef enum {                                  /*!< STIMER_STCFG_CLEAR                                                        */
  STIMER_STCFG_CLEAR_RUN               = 0,     /*!< RUN : Let the COUNTER register run on its input clock.                    */
  STIMER_STCFG_CLEAR_CLEAR             = 1,     /*!< CLEAR : Stop the COUNTER register for loading.                            */
} STIMER_STCFG_CLEAR_Enum;

/* ===========================================  STIMER STCFG COMPAREHEN [15..15]  ============================================ */
typedef enum {                                  /*!< STIMER_STCFG_COMPAREHEN                                                   */
  STIMER_STCFG_COMPAREHEN_DISABLE      = 0,     /*!< DISABLE : Compare H disabled.                                             */
  STIMER_STCFG_COMPAREHEN_ENABLE       = 1,     /*!< ENABLE : Compare H enabled.                                               */
} STIMER_STCFG_COMPAREHEN_Enum;

/* ===========================================  STIMER STCFG COMPAREGEN [14..14]  ============================================ */
typedef enum {                                  /*!< STIMER_STCFG_COMPAREGEN                                                   */
  STIMER_STCFG_COMPAREGEN_DISABLE      = 0,     /*!< DISABLE : Compare G disabled.                                             */
  STIMER_STCFG_COMPAREGEN_ENABLE       = 1,     /*!< ENABLE : Compare G enabled.                                               */
} STIMER_STCFG_COMPAREGEN_Enum;

/* ===========================================  STIMER STCFG COMPAREFEN [13..13]  ============================================ */
typedef enum {                                  /*!< STIMER_STCFG_COMPAREFEN                                                   */
  STIMER_STCFG_COMPAREFEN_DISABLE      = 0,     /*!< DISABLE : Compare F disabled.                                             */
  STIMER_STCFG_COMPAREFEN_ENABLE       = 1,     /*!< ENABLE : Compare F enabled.                                               */
} STIMER_STCFG_COMPAREFEN_Enum;

/* ===========================================  STIMER STCFG COMPAREEEN [12..12]  ============================================ */
typedef enum {                                  /*!< STIMER_STCFG_COMPAREEEN                                                   */
  STIMER_STCFG_COMPAREEEN_DISABLE      = 0,     /*!< DISABLE : Compare E disabled.                                             */
  STIMER_STCFG_COMPAREEEN_ENABLE       = 1,     /*!< ENABLE : Compare E enabled.                                               */
} STIMER_STCFG_COMPAREEEN_Enum;

/* ===========================================  STIMER STCFG COMPAREDEN [11..11]  ============================================ */
typedef enum {                                  /*!< STIMER_STCFG_COMPAREDEN                                                   */
  STIMER_STCFG_COMPAREDEN_DISABLE      = 0,     /*!< DISABLE : Compare D disabled.                                             */
  STIMER_STCFG_COMPAREDEN_ENABLE       = 1,     /*!< ENABLE : Compare D enabled.                                               */
} STIMER_STCFG_COMPAREDEN_Enum;

/* ===========================================  STIMER STCFG COMPARECEN [10..10]  ============================================ */
typedef enum {                                  /*!< STIMER_STCFG_COMPARECEN                                                   */
  STIMER_STCFG_COMPARECEN_DISABLE      = 0,     /*!< DISABLE : Compare C disabled.                                             */
  STIMER_STCFG_COMPARECEN_ENABLE       = 1,     /*!< ENABLE : Compare C enabled.                                               */
} STIMER_STCFG_COMPARECEN_Enum;

/* ============================================  STIMER STCFG COMPAREBEN [9..9]  ============================================= */
typedef enum {                                  /*!< STIMER_STCFG_COMPAREBEN                                                   */
  STIMER_STCFG_COMPAREBEN_DISABLE      = 0,     /*!< DISABLE : Compare B disabled.                                             */
  STIMER_STCFG_COMPAREBEN_ENABLE       = 1,     /*!< ENABLE : Compare B enabled.                                               */
} STIMER_STCFG_COMPAREBEN_Enum;

/* ============================================  STIMER STCFG COMPAREAEN [8..8]  ============================================= */
typedef enum {                                  /*!< STIMER_STCFG_COMPAREAEN                                                   */
  STIMER_STCFG_COMPAREAEN_DISABLE      = 0,     /*!< DISABLE : Compare A disabled.                                             */
  STIMER_STCFG_COMPAREAEN_ENABLE       = 1,     /*!< ENABLE : Compare A enabled.                                               */
} STIMER_STCFG_COMPAREAEN_Enum;

/* ==============================================  STIMER STCFG CLKSEL [0..3]  =============================================== */
typedef enum {                                  /*!< STIMER_STCFG_CLKSEL                                                       */
  STIMER_STCFG_CLKSEL_NOCLK            = 0,     /*!< NOCLK : No clock enabled.                                                 */
  STIMER_STCFG_CLKSEL_HFRC_6MHZ        = 1,     /*!< HFRC_6MHZ : 6MHz from the HFRC clock divider.                             */
  STIMER_STCFG_CLKSEL_HFRC_375KHZ      = 2,     /*!< HFRC_375KHZ : 375KHz from the HFRC clock divider.                         */
  STIMER_STCFG_CLKSEL_XTAL_32KHZ       = 3,     /*!< XTAL_32KHZ : 32768Hz from the crystal oscillator.                         */
  STIMER_STCFG_CLKSEL_XTAL_16KHZ       = 4,     /*!< XTAL_16KHZ : 16384Hz from the crystal oscillator.                         */
  STIMER_STCFG_CLKSEL_XTAL_1KHZ        = 5,     /*!< XTAL_1KHZ : 1024Hz from the crystal oscillator.                           */
  STIMER_STCFG_CLKSEL_LFRC_1KHZ        = 6,     /*!< LFRC_1KHZ : Approximately 1KHz from the LFRC oscillator (uncalibrated).   */
  STIMER_STCFG_CLKSEL_CTIMER0          = 7,     /*!< CTIMER0 : Use CTIMER 0 for the clock source (allows prescaling
                                                     from other system clocks).                                                */
  STIMER_STCFG_CLKSEL_CTIMER1          = 8,     /*!< CTIMER1 : Use CTIMER 1 for the clock source (allows prescaling
                                                     from other system clocks).                                                */
} STIMER_STCFG_CLKSEL_Enum;

/* =========================================================  STTMR  ========================================================= */
/* =======================================================  SCAPCTRL0  ======================================================= */
/* ===========================================  STIMER SCAPCTRL0 CAPTURE0 [9..9]  ============================================ */
typedef enum {                                  /*!< STIMER_SCAPCTRL0_CAPTURE0                                                 */
  STIMER_SCAPCTRL0_CAPTURE0_DISABLE    = 0,     /*!< DISABLE : Capture function disabled.                                      */
  STIMER_SCAPCTRL0_CAPTURE0_ENABLE     = 1,     /*!< ENABLE : Capture function enabled.                                        */
} STIMER_SCAPCTRL0_CAPTURE0_Enum;

/* ============================================  STIMER SCAPCTRL0 STPOL0 [8..8]  ============================================= */
typedef enum {                                  /*!< STIMER_SCAPCTRL0_STPOL0                                                   */
  STIMER_SCAPCTRL0_STPOL0_CAPLH        = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
  STIMER_SCAPCTRL0_STPOL0_CAPHL        = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
} STIMER_SCAPCTRL0_STPOL0_Enum;

/* =======================================================  SCAPCTRL1  ======================================================= */
/* ===========================================  STIMER SCAPCTRL1 CAPTURE1 [9..9]  ============================================ */
typedef enum {                                  /*!< STIMER_SCAPCTRL1_CAPTURE1                                                 */
  STIMER_SCAPCTRL1_CAPTURE1_DISABLE    = 0,     /*!< DISABLE : Capture function disabled.                                      */
  STIMER_SCAPCTRL1_CAPTURE1_ENABLE     = 1,     /*!< ENABLE : Capture function enabled.                                        */
} STIMER_SCAPCTRL1_CAPTURE1_Enum;

/* ============================================  STIMER SCAPCTRL1 STPOL1 [8..8]  ============================================= */
typedef enum {                                  /*!< STIMER_SCAPCTRL1_STPOL1                                                   */
  STIMER_SCAPCTRL1_STPOL1_CAPLH        = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
  STIMER_SCAPCTRL1_STPOL1_CAPHL        = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
} STIMER_SCAPCTRL1_STPOL1_Enum;

/* =======================================================  SCAPCTRL2  ======================================================= */
/* ===========================================  STIMER SCAPCTRL2 CAPTURE2 [9..9]  ============================================ */
typedef enum {                                  /*!< STIMER_SCAPCTRL2_CAPTURE2                                                 */
  STIMER_SCAPCTRL2_CAPTURE2_DISABLE    = 0,     /*!< DISABLE : Capture function disabled.                                      */
  STIMER_SCAPCTRL2_CAPTURE2_ENABLE     = 1,     /*!< ENABLE : Capture function enabled.                                        */
} STIMER_SCAPCTRL2_CAPTURE2_Enum;

/* ============================================  STIMER SCAPCTRL2 STPOL2 [8..8]  ============================================= */
typedef enum {                                  /*!< STIMER_SCAPCTRL2_STPOL2                                                   */
  STIMER_SCAPCTRL2_STPOL2_CAPLH        = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
  STIMER_SCAPCTRL2_STPOL2_CAPHL        = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
} STIMER_SCAPCTRL2_STPOL2_Enum;

/* =======================================================  SCAPCTRL3  ======================================================= */
/* ===========================================  STIMER SCAPCTRL3 CAPTURE3 [9..9]  ============================================ */
typedef enum {                                  /*!< STIMER_SCAPCTRL3_CAPTURE3                                                 */
  STIMER_SCAPCTRL3_CAPTURE3_DISABLE    = 0,     /*!< DISABLE : Capture function disabled.                                      */
  STIMER_SCAPCTRL3_CAPTURE3_ENABLE     = 1,     /*!< ENABLE : Capture function enabled.                                        */
} STIMER_SCAPCTRL3_CAPTURE3_Enum;

/* ============================================  STIMER SCAPCTRL3 STPOL3 [8..8]  ============================================= */
typedef enum {                                  /*!< STIMER_SCAPCTRL3_STPOL3                                                   */
  STIMER_SCAPCTRL3_STPOL3_CAPLH        = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
  STIMER_SCAPCTRL3_STPOL3_CAPHL        = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
} STIMER_SCAPCTRL3_STPOL3_Enum;

/* ========================================================  SCMPR0  ========================================================= */
/* ========================================================  SCMPR1  ========================================================= */
/* ========================================================  SCMPR2  ========================================================= */
/* ========================================================  SCMPR3  ========================================================= */
/* ========================================================  SCMPR4  ========================================================= */
/* ========================================================  SCMPR5  ========================================================= */
/* ========================================================  SCMPR6  ========================================================= */
/* ========================================================  SCMPR7  ========================================================= */
/* ========================================================  SCAPT0  ========================================================= */
/* ========================================================  SCAPT1  ========================================================= */
/* ========================================================  SCAPT2  ========================================================= */
/* ========================================================  SCAPT3  ========================================================= */
/* =========================================================  SNVR0  ========================================================= */
/* =========================================================  SNVR1  ========================================================= */
/* =========================================================  SNVR2  ========================================================= */
/* =======================================================  STMINTEN  ======================================================== */
/* ===========================================  STIMER STMINTEN CAPTURED [12..12]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTEN_CAPTURED                                                  */
  STIMER_STMINTEN_CAPTURED_CAPD_INT    = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
  STIMER_STMINTEN_CAPTURED_CAPD_DEFAULT = 0,    /*!< CAPD_DEFAULT : Capture D interrupt status default/not set.                */
} STIMER_STMINTEN_CAPTURED_Enum;

/* ===========================================  STIMER STMINTEN CAPTUREC [11..11]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTEN_CAPTUREC                                                  */
  STIMER_STMINTEN_CAPTUREC_CAPC_INT    = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
  STIMER_STMINTEN_CAPTUREC_CAPC_DEFAULT = 0,    /*!< CAPC_DEFAULT : CAPTURE C interrupt status default/not set.                */
} STIMER_STMINTEN_CAPTUREC_Enum;

/* ===========================================  STIMER STMINTEN CAPTUREB [10..10]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTEN_CAPTUREB                                                  */
  STIMER_STMINTEN_CAPTUREB_CAPB_INT    = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
  STIMER_STMINTEN_CAPTUREB_CAPB_DEFAULT = 0,    /*!< CAPB_DEFAULT : CAPTURE B interrupt status default/not set.                */
} STIMER_STMINTEN_CAPTUREB_Enum;

/* ============================================  STIMER STMINTEN CAPTUREA [9..9]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTEN_CAPTUREA                                                  */
  STIMER_STMINTEN_CAPTUREA_CAPA_INT    = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
  STIMER_STMINTEN_CAPTUREA_CAPA_DEFAULT = 0,    /*!< CAPA_DEFAULT : CAPTURE A interrupt status default/not set.                */
} STIMER_STMINTEN_CAPTUREA_Enum;

/* ============================================  STIMER STMINTEN OVERFLOW [8..8]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTEN_OVERFLOW                                                  */
  STIMER_STMINTEN_OVERFLOW_OFLOW_INT   = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
  STIMER_STMINTEN_OVERFLOW_OFLOW_DEFAULT = 0,   /*!< OFLOW_DEFAULT : Overflow interrupt status bit default/not set.            */
} STIMER_STMINTEN_OVERFLOW_Enum;

/* ============================================  STIMER STMINTEN COMPAREH [7..7]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREH                                                  */
  STIMER_STMINTEN_COMPAREH_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTEN_COMPAREH_DEFAULT     = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTEN_COMPAREH_Enum;

/* ============================================  STIMER STMINTEN COMPAREG [6..6]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREG                                                  */
  STIMER_STMINTEN_COMPAREG_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTEN_COMPAREG_DEFAULT     = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTEN_COMPAREG_Enum;

/* ============================================  STIMER STMINTEN COMPAREF [5..5]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREF                                                  */
  STIMER_STMINTEN_COMPAREF_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTEN_COMPAREF_DEFAULT     = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTEN_COMPAREF_Enum;

/* ============================================  STIMER STMINTEN COMPAREE [4..4]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREE                                                  */
  STIMER_STMINTEN_COMPAREE_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTEN_COMPAREE_DEFAULT     = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTEN_COMPAREE_Enum;

/* ============================================  STIMER STMINTEN COMPARED [3..3]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTEN_COMPARED                                                  */
  STIMER_STMINTEN_COMPARED_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTEN_COMPARED_DEFAULT     = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTEN_COMPARED_Enum;

/* ============================================  STIMER STMINTEN COMPAREC [2..2]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREC                                                  */
  STIMER_STMINTEN_COMPAREC_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTEN_COMPAREC_DEFAULT     = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTEN_COMPAREC_Enum;

/* ============================================  STIMER STMINTEN COMPAREB [1..1]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREB                                                  */
  STIMER_STMINTEN_COMPAREB_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTEN_COMPAREB_DEFAULT     = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTEN_COMPAREB_Enum;

/* ============================================  STIMER STMINTEN COMPAREA [0..0]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTEN_COMPAREA                                                  */
  STIMER_STMINTEN_COMPAREA_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTEN_COMPAREA_DEFAULT     = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTEN_COMPAREA_Enum;

/* ======================================================  STMINTSTAT  ======================================================= */
/* ==========================================  STIMER STMINTSTAT CAPTURED [12..12]  ========================================== */
typedef enum {                                  /*!< STIMER_STMINTSTAT_CAPTURED                                                */
  STIMER_STMINTSTAT_CAPTURED_CAPD_INT  = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
  STIMER_STMINTSTAT_CAPTURED_CAPD_DEFAULT = 0,  /*!< CAPD_DEFAULT : Capture D interrupt status default/not set.                */
} STIMER_STMINTSTAT_CAPTURED_Enum;

/* ==========================================  STIMER STMINTSTAT CAPTUREC [11..11]  ========================================== */
typedef enum {                                  /*!< STIMER_STMINTSTAT_CAPTUREC                                                */
  STIMER_STMINTSTAT_CAPTUREC_CAPC_INT  = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
  STIMER_STMINTSTAT_CAPTUREC_CAPC_DEFAULT = 0,  /*!< CAPC_DEFAULT : CAPTURE C interrupt status default/not set.                */
} STIMER_STMINTSTAT_CAPTUREC_Enum;

/* ==========================================  STIMER STMINTSTAT CAPTUREB [10..10]  ========================================== */
typedef enum {                                  /*!< STIMER_STMINTSTAT_CAPTUREB                                                */
  STIMER_STMINTSTAT_CAPTUREB_CAPB_INT  = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
  STIMER_STMINTSTAT_CAPTUREB_CAPB_DEFAULT = 0,  /*!< CAPB_DEFAULT : CAPTURE B interrupt status default/not set.                */
} STIMER_STMINTSTAT_CAPTUREB_Enum;

/* ===========================================  STIMER STMINTSTAT CAPTUREA [9..9]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTSTAT_CAPTUREA                                                */
  STIMER_STMINTSTAT_CAPTUREA_CAPA_INT  = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
  STIMER_STMINTSTAT_CAPTUREA_CAPA_DEFAULT = 0,  /*!< CAPA_DEFAULT : CAPTURE A interrupt status default/not set.                */
} STIMER_STMINTSTAT_CAPTUREA_Enum;

/* ===========================================  STIMER STMINTSTAT OVERFLOW [8..8]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTSTAT_OVERFLOW                                                */
  STIMER_STMINTSTAT_OVERFLOW_OFLOW_INT = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
  STIMER_STMINTSTAT_OVERFLOW_OFLOW_DEFAULT = 0, /*!< OFLOW_DEFAULT : Overflow interrupt status bit default/not set.            */
} STIMER_STMINTSTAT_OVERFLOW_Enum;

/* ===========================================  STIMER STMINTSTAT COMPAREH [7..7]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREH                                                */
  STIMER_STMINTSTAT_COMPAREH_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTSTAT_COMPAREH_DEFAULT   = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTSTAT_COMPAREH_Enum;

/* ===========================================  STIMER STMINTSTAT COMPAREG [6..6]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREG                                                */
  STIMER_STMINTSTAT_COMPAREG_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTSTAT_COMPAREG_DEFAULT   = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTSTAT_COMPAREG_Enum;

/* ===========================================  STIMER STMINTSTAT COMPAREF [5..5]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREF                                                */
  STIMER_STMINTSTAT_COMPAREF_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTSTAT_COMPAREF_DEFAULT   = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTSTAT_COMPAREF_Enum;

/* ===========================================  STIMER STMINTSTAT COMPAREE [4..4]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREE                                                */
  STIMER_STMINTSTAT_COMPAREE_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTSTAT_COMPAREE_DEFAULT   = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTSTAT_COMPAREE_Enum;

/* ===========================================  STIMER STMINTSTAT COMPARED [3..3]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPARED                                                */
  STIMER_STMINTSTAT_COMPARED_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTSTAT_COMPARED_DEFAULT   = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTSTAT_COMPARED_Enum;

/* ===========================================  STIMER STMINTSTAT COMPAREC [2..2]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREC                                                */
  STIMER_STMINTSTAT_COMPAREC_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTSTAT_COMPAREC_DEFAULT   = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTSTAT_COMPAREC_Enum;

/* ===========================================  STIMER STMINTSTAT COMPAREB [1..1]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREB                                                */
  STIMER_STMINTSTAT_COMPAREB_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTSTAT_COMPAREB_DEFAULT   = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTSTAT_COMPAREB_Enum;

/* ===========================================  STIMER STMINTSTAT COMPAREA [0..0]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTSTAT_COMPAREA                                                */
  STIMER_STMINTSTAT_COMPAREA_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTSTAT_COMPAREA_DEFAULT   = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTSTAT_COMPAREA_Enum;

/* =======================================================  STMINTCLR  ======================================================= */
/* ==========================================  STIMER STMINTCLR CAPTURED [12..12]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTCLR_CAPTURED                                                 */
  STIMER_STMINTCLR_CAPTURED_CAPD_INT   = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
  STIMER_STMINTCLR_CAPTURED_CAPD_DEFAULT = 0,   /*!< CAPD_DEFAULT : Capture D interrupt status default/not set.                */
} STIMER_STMINTCLR_CAPTURED_Enum;

/* ==========================================  STIMER STMINTCLR CAPTUREC [11..11]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTCLR_CAPTUREC                                                 */
  STIMER_STMINTCLR_CAPTUREC_CAPC_INT   = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
  STIMER_STMINTCLR_CAPTUREC_CAPC_DEFAULT = 0,   /*!< CAPC_DEFAULT : CAPTURE C interrupt status default/not set.                */
} STIMER_STMINTCLR_CAPTUREC_Enum;

/* ==========================================  STIMER STMINTCLR CAPTUREB [10..10]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTCLR_CAPTUREB                                                 */
  STIMER_STMINTCLR_CAPTUREB_CAPB_INT   = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
  STIMER_STMINTCLR_CAPTUREB_CAPB_DEFAULT = 0,   /*!< CAPB_DEFAULT : CAPTURE B interrupt status default/not set.                */
} STIMER_STMINTCLR_CAPTUREB_Enum;

/* ===========================================  STIMER STMINTCLR CAPTUREA [9..9]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTCLR_CAPTUREA                                                 */
  STIMER_STMINTCLR_CAPTUREA_CAPA_INT   = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
  STIMER_STMINTCLR_CAPTUREA_CAPA_DEFAULT = 0,   /*!< CAPA_DEFAULT : CAPTURE A interrupt status default/not set.                */
} STIMER_STMINTCLR_CAPTUREA_Enum;

/* ===========================================  STIMER STMINTCLR OVERFLOW [8..8]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTCLR_OVERFLOW                                                 */
  STIMER_STMINTCLR_OVERFLOW_OFLOW_INT  = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
  STIMER_STMINTCLR_OVERFLOW_OFLOW_DEFAULT = 0,  /*!< OFLOW_DEFAULT : Overflow interrupt status bit default/not set.            */
} STIMER_STMINTCLR_OVERFLOW_Enum;

/* ===========================================  STIMER STMINTCLR COMPAREH [7..7]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREH                                                 */
  STIMER_STMINTCLR_COMPAREH_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTCLR_COMPAREH_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTCLR_COMPAREH_Enum;

/* ===========================================  STIMER STMINTCLR COMPAREG [6..6]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREG                                                 */
  STIMER_STMINTCLR_COMPAREG_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTCLR_COMPAREG_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTCLR_COMPAREG_Enum;

/* ===========================================  STIMER STMINTCLR COMPAREF [5..5]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREF                                                 */
  STIMER_STMINTCLR_COMPAREF_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTCLR_COMPAREF_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTCLR_COMPAREF_Enum;

/* ===========================================  STIMER STMINTCLR COMPAREE [4..4]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREE                                                 */
  STIMER_STMINTCLR_COMPAREE_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTCLR_COMPAREE_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTCLR_COMPAREE_Enum;

/* ===========================================  STIMER STMINTCLR COMPARED [3..3]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTCLR_COMPARED                                                 */
  STIMER_STMINTCLR_COMPARED_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTCLR_COMPARED_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTCLR_COMPARED_Enum;

/* ===========================================  STIMER STMINTCLR COMPAREC [2..2]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREC                                                 */
  STIMER_STMINTCLR_COMPAREC_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTCLR_COMPAREC_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTCLR_COMPAREC_Enum;

/* ===========================================  STIMER STMINTCLR COMPAREB [1..1]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREB                                                 */
  STIMER_STMINTCLR_COMPAREB_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTCLR_COMPAREB_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTCLR_COMPAREB_Enum;

/* ===========================================  STIMER STMINTCLR COMPAREA [0..0]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTCLR_COMPAREA                                                 */
  STIMER_STMINTCLR_COMPAREA_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTCLR_COMPAREA_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTCLR_COMPAREA_Enum;

/* =======================================================  STMINTSET  ======================================================= */
/* ==========================================  STIMER STMINTSET CAPTURED [12..12]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTSET_CAPTURED                                                 */
  STIMER_STMINTSET_CAPTURED_CAPD_INT   = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
  STIMER_STMINTSET_CAPTURED_CAPD_DEFAULT = 0,   /*!< CAPD_DEFAULT : Capture D interrupt status default/not set.                */
} STIMER_STMINTSET_CAPTURED_Enum;

/* ==========================================  STIMER STMINTSET CAPTUREC [11..11]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTSET_CAPTUREC                                                 */
  STIMER_STMINTSET_CAPTUREC_CAPC_INT   = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
  STIMER_STMINTSET_CAPTUREC_CAPC_DEFAULT = 0,   /*!< CAPC_DEFAULT : CAPTURE C interrupt status default/not set.                */
} STIMER_STMINTSET_CAPTUREC_Enum;

/* ==========================================  STIMER STMINTSET CAPTUREB [10..10]  =========================================== */
typedef enum {                                  /*!< STIMER_STMINTSET_CAPTUREB                                                 */
  STIMER_STMINTSET_CAPTUREB_CAPB_INT   = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
  STIMER_STMINTSET_CAPTUREB_CAPB_DEFAULT = 0,   /*!< CAPB_DEFAULT : CAPTURE B interrupt status default/not set.                */
} STIMER_STMINTSET_CAPTUREB_Enum;

/* ===========================================  STIMER STMINTSET CAPTUREA [9..9]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTSET_CAPTUREA                                                 */
  STIMER_STMINTSET_CAPTUREA_CAPA_INT   = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
  STIMER_STMINTSET_CAPTUREA_CAPA_DEFAULT = 0,   /*!< CAPA_DEFAULT : CAPTURE A interrupt status default/not set.                */
} STIMER_STMINTSET_CAPTUREA_Enum;

/* ===========================================  STIMER STMINTSET OVERFLOW [8..8]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTSET_OVERFLOW                                                 */
  STIMER_STMINTSET_OVERFLOW_OFLOW_INT  = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
  STIMER_STMINTSET_OVERFLOW_OFLOW_DEFAULT = 0,  /*!< OFLOW_DEFAULT : Overflow interrupt status bit default/not set.            */
} STIMER_STMINTSET_OVERFLOW_Enum;

/* ===========================================  STIMER STMINTSET COMPAREH [7..7]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREH                                                 */
  STIMER_STMINTSET_COMPAREH_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTSET_COMPAREH_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTSET_COMPAREH_Enum;

/* ===========================================  STIMER STMINTSET COMPAREG [6..6]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREG                                                 */
  STIMER_STMINTSET_COMPAREG_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTSET_COMPAREG_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTSET_COMPAREG_Enum;

/* ===========================================  STIMER STMINTSET COMPAREF [5..5]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREF                                                 */
  STIMER_STMINTSET_COMPAREF_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTSET_COMPAREF_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTSET_COMPAREF_Enum;

/* ===========================================  STIMER STMINTSET COMPAREE [4..4]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREE                                                 */
  STIMER_STMINTSET_COMPAREE_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTSET_COMPAREE_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTSET_COMPAREE_Enum;

/* ===========================================  STIMER STMINTSET COMPARED [3..3]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTSET_COMPARED                                                 */
  STIMER_STMINTSET_COMPARED_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTSET_COMPARED_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTSET_COMPARED_Enum;

/* ===========================================  STIMER STMINTSET COMPAREC [2..2]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREC                                                 */
  STIMER_STMINTSET_COMPAREC_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTSET_COMPAREC_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTSET_COMPAREC_Enum;

/* ===========================================  STIMER STMINTSET COMPAREB [1..1]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREB                                                 */
  STIMER_STMINTSET_COMPAREB_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTSET_COMPAREB_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTSET_COMPAREB_Enum;

/* ===========================================  STIMER STMINTSET COMPAREA [0..0]  ============================================ */
typedef enum {                                  /*!< STIMER_STMINTSET_COMPAREA                                                 */
  STIMER_STMINTSET_COMPAREA_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
  STIMER_STMINTSET_COMPAREA_DEFAULT    = 0,     /*!< DEFAULT : COUNTER less than COMPARE register.                             */
} STIMER_STMINTSET_COMPAREA_Enum;



/* =========================================================================================================================== */
/* ================                                           TIMER                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
/* ========================================================  STATUS  ========================================================= */
/* ========================================================  GLOBEN  ========================================================= */
/* ==============================================  TIMER GLOBEN ADCEN [31..31]  ============================================== */
typedef enum {                                  /*!< TIMER_GLOBEN_ADCEN                                                        */
  TIMER_GLOBEN_ADCEN_EN                = 1,     /*!< EN : Timer Enabled. TMREN enable is used.                                 */
  TIMER_GLOBEN_ADCEN_DIS               = 0,     /*!< DIS : Disable TIMER .                                                     */
} TIMER_GLOBEN_ADCEN_Enum;

/* ============================================  TIMER GLOBEN AUDADCEN [30..30]  ============================================= */
typedef enum {                                  /*!< TIMER_GLOBEN_AUDADCEN                                                     */
  TIMER_GLOBEN_AUDADCEN_EN             = 1,     /*!< EN : Timer Enabled. TMREN enable is used.                                 */
  TIMER_GLOBEN_AUDADCEN_DIS            = 0,     /*!< DIS : Disable TIMER .                                                     */
} TIMER_GLOBEN_AUDADCEN_Enum;

/* =========================================  TIMER GLOBEN ENABLEALLINPUTS [29..29]  ========================================= */
typedef enum {                                  /*!< TIMER_GLOBEN_ENABLEALLINPUTS                                              */
  TIMER_GLOBEN_ENABLEALLINPUTS_EN      = 1,     /*!< EN : Override to enable all inputs from GPIO                              */
  TIMER_GLOBEN_ENABLEALLINPUTS_DIS     = 0,     /*!< DIS : Normal mode where inputs from GPIO are enabled based on
                                                     enabled clock and triggers.                                               */
} TIMER_GLOBEN_ENABLEALLINPUTS_Enum;

/* ==============================================  TIMER GLOBEN ENB15 [15..15]  ============================================== */
typedef enum {                                  /*!< TIMER_GLOBEN_ENB15                                                        */
  TIMER_GLOBEN_ENB15_EN                = 1,     /*!< EN : Timer Enabled. TMR15EN enable is used.                               */
  TIMER_GLOBEN_ENB15_DIS               = 0,     /*!< DIS : Disable TIMER 15.                                                   */
} TIMER_GLOBEN_ENB15_Enum;

/* ==============================================  TIMER GLOBEN ENB14 [14..14]  ============================================== */
typedef enum {                                  /*!< TIMER_GLOBEN_ENB14                                                        */
  TIMER_GLOBEN_ENB14_EN                = 1,     /*!< EN : Timer Enabled. TMR14EN enable is used.                               */
  TIMER_GLOBEN_ENB14_DIS               = 0,     /*!< DIS : Disable TIMER 14.                                                   */
} TIMER_GLOBEN_ENB14_Enum;

/* ==============================================  TIMER GLOBEN ENB13 [13..13]  ============================================== */
typedef enum {                                  /*!< TIMER_GLOBEN_ENB13                                                        */
  TIMER_GLOBEN_ENB13_EN                = 1,     /*!< EN : Timer Enabled. TMR13EN enable is used.                               */
  TIMER_GLOBEN_ENB13_DIS               = 0,     /*!< DIS : Disable TIMER 13.                                                   */
} TIMER_GLOBEN_ENB13_Enum;

/* ==============================================  TIMER GLOBEN ENB12 [12..12]  ============================================== */
typedef enum {                                  /*!< TIMER_GLOBEN_ENB12                                                        */
  TIMER_GLOBEN_ENB12_EN                = 1,     /*!< EN : Timer Enabled. TMR12EN enable is used.                               */
  TIMER_GLOBEN_ENB12_DIS               = 0,     /*!< DIS : Disable TIMER 12.                                                   */
} TIMER_GLOBEN_ENB12_Enum;

/* ==============================================  TIMER GLOBEN ENB11 [11..11]  ============================================== */
typedef enum {                                  /*!< TIMER_GLOBEN_ENB11                                                        */
  TIMER_GLOBEN_ENB11_EN                = 1,     /*!< EN : Timer Enabled. TMR11EN enable is used.                               */
  TIMER_GLOBEN_ENB11_DIS               = 0,     /*!< DIS : Disable TIMER 11.                                                   */
} TIMER_GLOBEN_ENB11_Enum;

/* ==============================================  TIMER GLOBEN ENB10 [10..10]  ============================================== */
typedef enum {                                  /*!< TIMER_GLOBEN_ENB10                                                        */
  TIMER_GLOBEN_ENB10_EN                = 1,     /*!< EN : Timer Enabled. TMR10EN enable is used.                               */
  TIMER_GLOBEN_ENB10_DIS               = 0,     /*!< DIS : Disable TIMER 10.                                                   */
} TIMER_GLOBEN_ENB10_Enum;

/* ===============================================  TIMER GLOBEN ENB9 [9..9]  ================================================ */
typedef enum {                                  /*!< TIMER_GLOBEN_ENB9                                                         */
  TIMER_GLOBEN_ENB9_EN                 = 1,     /*!< EN : Timer Enabled. TMR9EN enable is used.                                */
  TIMER_GLOBEN_ENB9_DIS                = 0,     /*!< DIS : Disable TIMER 9.                                                    */
} TIMER_GLOBEN_ENB9_Enum;

/* ===============================================  TIMER GLOBEN ENB8 [8..8]  ================================================ */
typedef enum {                                  /*!< TIMER_GLOBEN_ENB8                                                         */
  TIMER_GLOBEN_ENB8_EN                 = 1,     /*!< EN : Timer Enabled. TMR8EN enable is used.                                */
  TIMER_GLOBEN_ENB8_DIS                = 0,     /*!< DIS : Disable TIMER 8.                                                    */
} TIMER_GLOBEN_ENB8_Enum;

/* ===============================================  TIMER GLOBEN ENB7 [7..7]  ================================================ */
typedef enum {                                  /*!< TIMER_GLOBEN_ENB7                                                         */
  TIMER_GLOBEN_ENB7_EN                 = 1,     /*!< EN : Timer Enabled. TMR7EN enable is used.                                */
  TIMER_GLOBEN_ENB7_DIS                = 0,     /*!< DIS : Disable TIMER 7.                                                    */
} TIMER_GLOBEN_ENB7_Enum;

/* ===============================================  TIMER GLOBEN ENB6 [6..6]  ================================================ */
typedef enum {                                  /*!< TIMER_GLOBEN_ENB6                                                         */
  TIMER_GLOBEN_ENB6_EN                 = 1,     /*!< EN : Timer Enabled. TMR6EN enable is used.                                */
  TIMER_GLOBEN_ENB6_DIS                = 0,     /*!< DIS : Disable TIMER 6.                                                    */
} TIMER_GLOBEN_ENB6_Enum;

/* ===============================================  TIMER GLOBEN ENB5 [5..5]  ================================================ */
typedef enum {                                  /*!< TIMER_GLOBEN_ENB5                                                         */
  TIMER_GLOBEN_ENB5_EN                 = 1,     /*!< EN : Timer Enabled. TMR5EN enable is used.                                */
  TIMER_GLOBEN_ENB5_DIS                = 0,     /*!< DIS : Disable TIMER 5.                                                    */
} TIMER_GLOBEN_ENB5_Enum;

/* ===============================================  TIMER GLOBEN ENB4 [4..4]  ================================================ */
typedef enum {                                  /*!< TIMER_GLOBEN_ENB4                                                         */
  TIMER_GLOBEN_ENB4_EN                 = 1,     /*!< EN : Timer Enabled. TMR4EN enable is used.                                */
  TIMER_GLOBEN_ENB4_DIS                = 0,     /*!< DIS : Disable TIMER 4.                                                    */
} TIMER_GLOBEN_ENB4_Enum;

/* ===============================================  TIMER GLOBEN ENB3 [3..3]  ================================================ */
typedef enum {                                  /*!< TIMER_GLOBEN_ENB3                                                         */
  TIMER_GLOBEN_ENB3_EN                 = 1,     /*!< EN : Timer Enabled. TMR3EN enable is used.                                */
  TIMER_GLOBEN_ENB3_DIS                = 0,     /*!< DIS : Disable TIMER 3.                                                    */
} TIMER_GLOBEN_ENB3_Enum;

/* ===============================================  TIMER GLOBEN ENB2 [2..2]  ================================================ */
typedef enum {                                  /*!< TIMER_GLOBEN_ENB2                                                         */
  TIMER_GLOBEN_ENB2_EN                 = 1,     /*!< EN : Timer Enabled. TMR2EN enable is used.                                */
  TIMER_GLOBEN_ENB2_DIS                = 0,     /*!< DIS : Disable TIMER 2.                                                    */
} TIMER_GLOBEN_ENB2_Enum;

/* ===============================================  TIMER GLOBEN ENB1 [1..1]  ================================================ */
typedef enum {                                  /*!< TIMER_GLOBEN_ENB1                                                         */
  TIMER_GLOBEN_ENB1_EN                 = 1,     /*!< EN : Timer Enabled. TMR1EN enable is used.                                */
  TIMER_GLOBEN_ENB1_DIS                = 0,     /*!< DIS : Disable TIMER 1.                                                    */
} TIMER_GLOBEN_ENB1_Enum;

/* ===============================================  TIMER GLOBEN ENB0 [0..0]  ================================================ */
typedef enum {                                  /*!< TIMER_GLOBEN_ENB0                                                         */
  TIMER_GLOBEN_ENB0_EN                 = 1,     /*!< EN : Timer Enabled. TMR0EN enable is used.                                */
  TIMER_GLOBEN_ENB0_DIS                = 0,     /*!< DIS : Disable TIMER 0.                                                    */
} TIMER_GLOBEN_ENB0_Enum;

/* =========================================================  INTEN  ========================================================= */
/* ========================================================  INTSTAT  ======================================================== */
/* ========================================================  INTCLR  ========================================================= */
/* ========================================================  INTSET  ========================================================= */
/* ========================================================  OUTCFG0  ======================================================== */
/* ============================================  TIMER OUTCFG0 OUTCFG3 [24..29]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG0_OUTCFG3                                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG0_OUTCFG3_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG0_OUTCFG3_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG0_OUTCFG3_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG0_OUTCFG3_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG0_OUTCFG3_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG0_OUTCFG3_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG0_OUTCFG3_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG0_OUTCFG3_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG0_OUTCFG3_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG0_OUTCFG3_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG0_OUTCFG3_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG0_OUTCFG3_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG0_OUTCFG3_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG0_OUTCFG3_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG0_OUTCFG3_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG0_OUTCFG3_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG0_OUTCFG3_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG0_OUTCFG3_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG0_OUTCFG3_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG0_OUTCFG3_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG0_OUTCFG3_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG0_OUTCFG3_Enum;

/* ============================================  TIMER OUTCFG0 OUTCFG2 [16..21]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG0_OUTCFG2                                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG0_OUTCFG2_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG0_OUTCFG2_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG0_OUTCFG2_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG0_OUTCFG2_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG0_OUTCFG2_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG0_OUTCFG2_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG0_OUTCFG2_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG0_OUTCFG2_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG0_OUTCFG2_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG0_OUTCFG2_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG0_OUTCFG2_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG0_OUTCFG2_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG0_OUTCFG2_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG0_OUTCFG2_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG0_OUTCFG2_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG0_OUTCFG2_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG0_OUTCFG2_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG0_OUTCFG2_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG0_OUTCFG2_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG0_OUTCFG2_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG0_OUTCFG2_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG0_OUTCFG2_Enum;

/* =============================================  TIMER OUTCFG0 OUTCFG1 [8..13]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG0_OUTCFG1                                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG0_OUTCFG1_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG0_OUTCFG1_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG0_OUTCFG1_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG0_OUTCFG1_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG0_OUTCFG1_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG0_OUTCFG1_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG0_OUTCFG1_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG0_OUTCFG1_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG0_OUTCFG1_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG0_OUTCFG1_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG0_OUTCFG1_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG0_OUTCFG1_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG0_OUTCFG1_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG0_OUTCFG1_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG0_OUTCFG1_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG0_OUTCFG1_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG0_OUTCFG1_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG0_OUTCFG1_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG0_OUTCFG1_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG0_OUTCFG1_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG0_OUTCFG1_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG0_OUTCFG1_Enum;

/* =============================================  TIMER OUTCFG0 OUTCFG0 [0..5]  ============================================== */
typedef enum {                                  /*!< TIMER_OUTCFG0_OUTCFG0                                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG0_OUTCFG0_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG0_OUTCFG0_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG0_OUTCFG0_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG0_OUTCFG0_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG0_OUTCFG0_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG0_OUTCFG0_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG0_OUTCFG0_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG0_OUTCFG0_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG0_OUTCFG0_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG0_OUTCFG0_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG0_OUTCFG0_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG0_OUTCFG0_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG0_OUTCFG0_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG0_OUTCFG0_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG0_OUTCFG0_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG0_OUTCFG0_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG0_OUTCFG0_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG0_OUTCFG0_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG0_OUTCFG0_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG0_OUTCFG0_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG0_OUTCFG0_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG0_OUTCFG0_Enum;

/* ========================================================  OUTCFG1  ======================================================== */
/* ============================================  TIMER OUTCFG1 OUTCFG7 [24..29]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG1_OUTCFG7                                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG1_OUTCFG7_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG1_OUTCFG7_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG1_OUTCFG7_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG1_OUTCFG7_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG1_OUTCFG7_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG1_OUTCFG7_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG1_OUTCFG7_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG1_OUTCFG7_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG1_OUTCFG7_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG1_OUTCFG7_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG1_OUTCFG7_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG1_OUTCFG7_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG1_OUTCFG7_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG1_OUTCFG7_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG1_OUTCFG7_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG1_OUTCFG7_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG1_OUTCFG7_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG1_OUTCFG7_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG1_OUTCFG7_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG1_OUTCFG7_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG1_OUTCFG7_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG1_OUTCFG7_Enum;

/* ============================================  TIMER OUTCFG1 OUTCFG6 [16..21]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG1_OUTCFG6                                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG1_OUTCFG6_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG1_OUTCFG6_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG1_OUTCFG6_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG1_OUTCFG6_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG1_OUTCFG6_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG1_OUTCFG6_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG1_OUTCFG6_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG1_OUTCFG6_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG1_OUTCFG6_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG1_OUTCFG6_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG1_OUTCFG6_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG1_OUTCFG6_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG1_OUTCFG6_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG1_OUTCFG6_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG1_OUTCFG6_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG1_OUTCFG6_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG1_OUTCFG6_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG1_OUTCFG6_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG1_OUTCFG6_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG1_OUTCFG6_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG1_OUTCFG6_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG1_OUTCFG6_Enum;

/* =============================================  TIMER OUTCFG1 OUTCFG5 [8..13]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG1_OUTCFG5                                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG1_OUTCFG5_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG1_OUTCFG5_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG1_OUTCFG5_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG1_OUTCFG5_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG1_OUTCFG5_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG1_OUTCFG5_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG1_OUTCFG5_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG1_OUTCFG5_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG1_OUTCFG5_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG1_OUTCFG5_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG1_OUTCFG5_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG1_OUTCFG5_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG1_OUTCFG5_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG1_OUTCFG5_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG1_OUTCFG5_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG1_OUTCFG5_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG1_OUTCFG5_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG1_OUTCFG5_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG1_OUTCFG5_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG1_OUTCFG5_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG1_OUTCFG5_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG1_OUTCFG5_Enum;

/* =============================================  TIMER OUTCFG1 OUTCFG4 [0..5]  ============================================== */
typedef enum {                                  /*!< TIMER_OUTCFG1_OUTCFG4                                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG1_OUTCFG4_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG1_OUTCFG4_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG1_OUTCFG4_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG1_OUTCFG4_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG1_OUTCFG4_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG1_OUTCFG4_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG1_OUTCFG4_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG1_OUTCFG4_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG1_OUTCFG4_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG1_OUTCFG4_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG1_OUTCFG4_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG1_OUTCFG4_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG1_OUTCFG4_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG1_OUTCFG4_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG1_OUTCFG4_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG1_OUTCFG4_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG1_OUTCFG4_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG1_OUTCFG4_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG1_OUTCFG4_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG1_OUTCFG4_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG1_OUTCFG4_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG1_OUTCFG4_Enum;

/* ========================================================  OUTCFG2  ======================================================== */
/* ============================================  TIMER OUTCFG2 OUTCFG11 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG2_OUTCFG11                                                    */
  TIMER_OUTCFG2_OUTCFG11_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG2_OUTCFG11_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG2_OUTCFG11_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG2_OUTCFG11_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG2_OUTCFG11_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG2_OUTCFG11_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG2_OUTCFG11_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG2_OUTCFG11_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG2_OUTCFG11_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG2_OUTCFG11_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG2_OUTCFG11_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG2_OUTCFG11_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG2_OUTCFG11_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG2_OUTCFG11_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG2_OUTCFG11_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG2_OUTCFG11_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG2_OUTCFG11_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG2_OUTCFG11_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG2_OUTCFG11_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG2_OUTCFG11_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG2_OUTCFG11_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG2_OUTCFG11_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG2_OUTCFG11_Enum;

/* ============================================  TIMER OUTCFG2 OUTCFG10 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG2_OUTCFG10                                                    */
  TIMER_OUTCFG2_OUTCFG10_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG2_OUTCFG10_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG2_OUTCFG10_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG2_OUTCFG10_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG2_OUTCFG10_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG2_OUTCFG10_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG2_OUTCFG10_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG2_OUTCFG10_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG2_OUTCFG10_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG2_OUTCFG10_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG2_OUTCFG10_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG2_OUTCFG10_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG2_OUTCFG10_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG2_OUTCFG10_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG2_OUTCFG10_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG2_OUTCFG10_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG2_OUTCFG10_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG2_OUTCFG10_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG2_OUTCFG10_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG2_OUTCFG10_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG2_OUTCFG10_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG2_OUTCFG10_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG2_OUTCFG10_Enum;

/* =============================================  TIMER OUTCFG2 OUTCFG9 [8..13]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG2_OUTCFG9                                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG2_OUTCFG9_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG2_OUTCFG9_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG2_OUTCFG9_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG2_OUTCFG9_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG2_OUTCFG9_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG2_OUTCFG9_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG2_OUTCFG9_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG2_OUTCFG9_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG2_OUTCFG9_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG2_OUTCFG9_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG2_OUTCFG9_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG2_OUTCFG9_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG2_OUTCFG9_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG2_OUTCFG9_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG2_OUTCFG9_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG2_OUTCFG9_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG2_OUTCFG9_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG2_OUTCFG9_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG2_OUTCFG9_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG2_OUTCFG9_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG2_OUTCFG9_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG2_OUTCFG9_Enum;

/* =============================================  TIMER OUTCFG2 OUTCFG8 [0..5]  ============================================== */
typedef enum {                                  /*!< TIMER_OUTCFG2_OUTCFG8                                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER00        = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER01        = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER10        = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER11        = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER20        = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER21        = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER30        = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER31        = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER40        = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER41        = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER50        = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER51        = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER60        = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER61        = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER70        = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER71        = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER80        = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER81        = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER90        = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER91        = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG2_OUTCFG8_TIMER100       = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG2_OUTCFG8_TIMER101       = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG2_OUTCFG8_TIMER110       = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG2_OUTCFG8_TIMER111       = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG2_OUTCFG8_TIMER120       = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG2_OUTCFG8_TIMER121       = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG2_OUTCFG8_TIMER130       = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG2_OUTCFG8_TIMER131       = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG2_OUTCFG8_TIMER140       = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG2_OUTCFG8_TIMER141       = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG2_OUTCFG8_TIMER150       = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG2_OUTCFG8_TIMER151       = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG2_OUTCFG8_STIMER0        = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG2_OUTCFG8_STIMER1        = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG2_OUTCFG8_STIMER2        = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG2_OUTCFG8_STIMER3        = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG2_OUTCFG8_STIMER4        = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG2_OUTCFG8_STIMER5        = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG2_OUTCFG8_STIMER6        = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG2_OUTCFG8_STIMER7        = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG2_OUTCFG8_DISABLED       = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG2_OUTCFG8_Enum;

/* ========================================================  OUTCFG3  ======================================================== */
/* ============================================  TIMER OUTCFG3 OUTCFG15 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG3_OUTCFG15                                                    */
  TIMER_OUTCFG3_OUTCFG15_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG3_OUTCFG15_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG3_OUTCFG15_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG3_OUTCFG15_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG3_OUTCFG15_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG3_OUTCFG15_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG3_OUTCFG15_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG3_OUTCFG15_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG3_OUTCFG15_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG3_OUTCFG15_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG3_OUTCFG15_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG3_OUTCFG15_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG3_OUTCFG15_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG3_OUTCFG15_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG3_OUTCFG15_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG3_OUTCFG15_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG3_OUTCFG15_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG3_OUTCFG15_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG3_OUTCFG15_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG3_OUTCFG15_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG3_OUTCFG15_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG3_OUTCFG15_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG3_OUTCFG15_Enum;

/* ============================================  TIMER OUTCFG3 OUTCFG14 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG3_OUTCFG14                                                    */
  TIMER_OUTCFG3_OUTCFG14_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG3_OUTCFG14_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG3_OUTCFG14_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG3_OUTCFG14_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG3_OUTCFG14_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG3_OUTCFG14_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG3_OUTCFG14_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG3_OUTCFG14_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG3_OUTCFG14_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG3_OUTCFG14_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG3_OUTCFG14_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG3_OUTCFG14_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG3_OUTCFG14_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG3_OUTCFG14_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG3_OUTCFG14_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG3_OUTCFG14_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG3_OUTCFG14_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG3_OUTCFG14_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG3_OUTCFG14_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG3_OUTCFG14_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG3_OUTCFG14_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG3_OUTCFG14_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG3_OUTCFG14_Enum;

/* ============================================  TIMER OUTCFG3 OUTCFG13 [8..13]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG3_OUTCFG13                                                    */
  TIMER_OUTCFG3_OUTCFG13_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG3_OUTCFG13_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG3_OUTCFG13_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG3_OUTCFG13_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG3_OUTCFG13_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG3_OUTCFG13_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG3_OUTCFG13_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG3_OUTCFG13_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG3_OUTCFG13_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG3_OUTCFG13_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG3_OUTCFG13_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG3_OUTCFG13_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG3_OUTCFG13_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG3_OUTCFG13_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG3_OUTCFG13_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG3_OUTCFG13_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG3_OUTCFG13_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG3_OUTCFG13_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG3_OUTCFG13_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG3_OUTCFG13_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG3_OUTCFG13_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG3_OUTCFG13_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG3_OUTCFG13_Enum;

/* =============================================  TIMER OUTCFG3 OUTCFG12 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG3_OUTCFG12                                                    */
  TIMER_OUTCFG3_OUTCFG12_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG3_OUTCFG12_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG3_OUTCFG12_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG3_OUTCFG12_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG3_OUTCFG12_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG3_OUTCFG12_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG3_OUTCFG12_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG3_OUTCFG12_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG3_OUTCFG12_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG3_OUTCFG12_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG3_OUTCFG12_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG3_OUTCFG12_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG3_OUTCFG12_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG3_OUTCFG12_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG3_OUTCFG12_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG3_OUTCFG12_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG3_OUTCFG12_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG3_OUTCFG12_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG3_OUTCFG12_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG3_OUTCFG12_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG3_OUTCFG12_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG3_OUTCFG12_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG3_OUTCFG12_Enum;

/* ========================================================  OUTCFG4  ======================================================== */
/* ============================================  TIMER OUTCFG4 OUTCFG19 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG4_OUTCFG19                                                    */
  TIMER_OUTCFG4_OUTCFG19_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG4_OUTCFG19_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG4_OUTCFG19_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG4_OUTCFG19_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG4_OUTCFG19_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG4_OUTCFG19_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG4_OUTCFG19_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG4_OUTCFG19_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG4_OUTCFG19_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG4_OUTCFG19_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG4_OUTCFG19_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG4_OUTCFG19_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG4_OUTCFG19_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG4_OUTCFG19_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG4_OUTCFG19_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG4_OUTCFG19_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG4_OUTCFG19_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG4_OUTCFG19_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG4_OUTCFG19_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG4_OUTCFG19_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG4_OUTCFG19_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG4_OUTCFG19_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG4_OUTCFG19_Enum;

/* ============================================  TIMER OUTCFG4 OUTCFG18 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG4_OUTCFG18                                                    */
  TIMER_OUTCFG4_OUTCFG18_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG4_OUTCFG18_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG4_OUTCFG18_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG4_OUTCFG18_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG4_OUTCFG18_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG4_OUTCFG18_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG4_OUTCFG18_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG4_OUTCFG18_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG4_OUTCFG18_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG4_OUTCFG18_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG4_OUTCFG18_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG4_OUTCFG18_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG4_OUTCFG18_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG4_OUTCFG18_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG4_OUTCFG18_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG4_OUTCFG18_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG4_OUTCFG18_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG4_OUTCFG18_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG4_OUTCFG18_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG4_OUTCFG18_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG4_OUTCFG18_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG4_OUTCFG18_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG4_OUTCFG18_Enum;

/* ============================================  TIMER OUTCFG4 OUTCFG17 [8..13]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG4_OUTCFG17                                                    */
  TIMER_OUTCFG4_OUTCFG17_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG4_OUTCFG17_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG4_OUTCFG17_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG4_OUTCFG17_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG4_OUTCFG17_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG4_OUTCFG17_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG4_OUTCFG17_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG4_OUTCFG17_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG4_OUTCFG17_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG4_OUTCFG17_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG4_OUTCFG17_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG4_OUTCFG17_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG4_OUTCFG17_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG4_OUTCFG17_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG4_OUTCFG17_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG4_OUTCFG17_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG4_OUTCFG17_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG4_OUTCFG17_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG4_OUTCFG17_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG4_OUTCFG17_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG4_OUTCFG17_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG4_OUTCFG17_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG4_OUTCFG17_Enum;

/* =============================================  TIMER OUTCFG4 OUTCFG16 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG4_OUTCFG16                                                    */
  TIMER_OUTCFG4_OUTCFG16_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG4_OUTCFG16_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG4_OUTCFG16_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG4_OUTCFG16_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG4_OUTCFG16_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG4_OUTCFG16_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG4_OUTCFG16_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG4_OUTCFG16_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG4_OUTCFG16_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG4_OUTCFG16_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG4_OUTCFG16_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG4_OUTCFG16_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG4_OUTCFG16_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG4_OUTCFG16_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG4_OUTCFG16_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG4_OUTCFG16_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG4_OUTCFG16_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG4_OUTCFG16_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG4_OUTCFG16_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG4_OUTCFG16_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG4_OUTCFG16_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG4_OUTCFG16_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG4_OUTCFG16_Enum;

/* ========================================================  OUTCFG5  ======================================================== */
/* ============================================  TIMER OUTCFG5 OUTCFG23 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG5_OUTCFG23                                                    */
  TIMER_OUTCFG5_OUTCFG23_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG5_OUTCFG23_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG5_OUTCFG23_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG5_OUTCFG23_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG5_OUTCFG23_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG5_OUTCFG23_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG5_OUTCFG23_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG5_OUTCFG23_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG5_OUTCFG23_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG5_OUTCFG23_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG5_OUTCFG23_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG5_OUTCFG23_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG5_OUTCFG23_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG5_OUTCFG23_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG5_OUTCFG23_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG5_OUTCFG23_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG5_OUTCFG23_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG5_OUTCFG23_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG5_OUTCFG23_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG5_OUTCFG23_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG5_OUTCFG23_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG5_OUTCFG23_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG5_OUTCFG23_Enum;

/* ============================================  TIMER OUTCFG5 OUTCFG22 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG5_OUTCFG22                                                    */
  TIMER_OUTCFG5_OUTCFG22_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG5_OUTCFG22_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG5_OUTCFG22_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG5_OUTCFG22_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG5_OUTCFG22_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG5_OUTCFG22_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG5_OUTCFG22_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG5_OUTCFG22_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG5_OUTCFG22_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG5_OUTCFG22_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG5_OUTCFG22_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG5_OUTCFG22_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG5_OUTCFG22_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG5_OUTCFG22_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG5_OUTCFG22_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG5_OUTCFG22_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG5_OUTCFG22_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG5_OUTCFG22_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG5_OUTCFG22_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG5_OUTCFG22_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG5_OUTCFG22_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG5_OUTCFG22_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG5_OUTCFG22_Enum;

/* ============================================  TIMER OUTCFG5 OUTCFG21 [8..13]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG5_OUTCFG21                                                    */
  TIMER_OUTCFG5_OUTCFG21_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG5_OUTCFG21_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG5_OUTCFG21_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG5_OUTCFG21_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG5_OUTCFG21_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG5_OUTCFG21_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG5_OUTCFG21_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG5_OUTCFG21_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG5_OUTCFG21_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG5_OUTCFG21_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG5_OUTCFG21_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG5_OUTCFG21_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG5_OUTCFG21_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG5_OUTCFG21_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG5_OUTCFG21_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG5_OUTCFG21_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG5_OUTCFG21_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG5_OUTCFG21_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG5_OUTCFG21_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG5_OUTCFG21_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG5_OUTCFG21_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG5_OUTCFG21_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG5_OUTCFG21_Enum;

/* =============================================  TIMER OUTCFG5 OUTCFG20 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG5_OUTCFG20                                                    */
  TIMER_OUTCFG5_OUTCFG20_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG5_OUTCFG20_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG5_OUTCFG20_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG5_OUTCFG20_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG5_OUTCFG20_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG5_OUTCFG20_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG5_OUTCFG20_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG5_OUTCFG20_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG5_OUTCFG20_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG5_OUTCFG20_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG5_OUTCFG20_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG5_OUTCFG20_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG5_OUTCFG20_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG5_OUTCFG20_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG5_OUTCFG20_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG5_OUTCFG20_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG5_OUTCFG20_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG5_OUTCFG20_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG5_OUTCFG20_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG5_OUTCFG20_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG5_OUTCFG20_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG5_OUTCFG20_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG5_OUTCFG20_Enum;

/* ========================================================  OUTCFG6  ======================================================== */
/* ============================================  TIMER OUTCFG6 OUTCFG27 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG6_OUTCFG27                                                    */
  TIMER_OUTCFG6_OUTCFG27_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG6_OUTCFG27_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG6_OUTCFG27_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG6_OUTCFG27_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG6_OUTCFG27_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG6_OUTCFG27_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG6_OUTCFG27_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG6_OUTCFG27_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG6_OUTCFG27_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG6_OUTCFG27_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG6_OUTCFG27_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG6_OUTCFG27_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG6_OUTCFG27_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG6_OUTCFG27_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG6_OUTCFG27_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG6_OUTCFG27_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG6_OUTCFG27_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG6_OUTCFG27_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG6_OUTCFG27_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG6_OUTCFG27_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG6_OUTCFG27_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG6_OUTCFG27_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG6_OUTCFG27_Enum;

/* ============================================  TIMER OUTCFG6 OUTCFG26 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG6_OUTCFG26                                                    */
  TIMER_OUTCFG6_OUTCFG26_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG6_OUTCFG26_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG6_OUTCFG26_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG6_OUTCFG26_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG6_OUTCFG26_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG6_OUTCFG26_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG6_OUTCFG26_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG6_OUTCFG26_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG6_OUTCFG26_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG6_OUTCFG26_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG6_OUTCFG26_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG6_OUTCFG26_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG6_OUTCFG26_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG6_OUTCFG26_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG6_OUTCFG26_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG6_OUTCFG26_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG6_OUTCFG26_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG6_OUTCFG26_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG6_OUTCFG26_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG6_OUTCFG26_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG6_OUTCFG26_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG6_OUTCFG26_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG6_OUTCFG26_Enum;

/* ============================================  TIMER OUTCFG6 OUTCFG25 [8..13]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG6_OUTCFG25                                                    */
  TIMER_OUTCFG6_OUTCFG25_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG6_OUTCFG25_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG6_OUTCFG25_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG6_OUTCFG25_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG6_OUTCFG25_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG6_OUTCFG25_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG6_OUTCFG25_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG6_OUTCFG25_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG6_OUTCFG25_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG6_OUTCFG25_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG6_OUTCFG25_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG6_OUTCFG25_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG6_OUTCFG25_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG6_OUTCFG25_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG6_OUTCFG25_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG6_OUTCFG25_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG6_OUTCFG25_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG6_OUTCFG25_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG6_OUTCFG25_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG6_OUTCFG25_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG6_OUTCFG25_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG6_OUTCFG25_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG6_OUTCFG25_Enum;

/* =============================================  TIMER OUTCFG6 OUTCFG24 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG6_OUTCFG24                                                    */
  TIMER_OUTCFG6_OUTCFG24_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG6_OUTCFG24_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG6_OUTCFG24_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG6_OUTCFG24_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG6_OUTCFG24_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG6_OUTCFG24_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG6_OUTCFG24_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG6_OUTCFG24_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG6_OUTCFG24_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG6_OUTCFG24_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG6_OUTCFG24_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG6_OUTCFG24_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG6_OUTCFG24_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG6_OUTCFG24_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG6_OUTCFG24_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG6_OUTCFG24_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG6_OUTCFG24_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG6_OUTCFG24_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG6_OUTCFG24_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG6_OUTCFG24_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG6_OUTCFG24_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG6_OUTCFG24_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG6_OUTCFG24_Enum;

/* ========================================================  OUTCFG7  ======================================================== */
/* ============================================  TIMER OUTCFG7 OUTCFG31 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG7_OUTCFG31                                                    */
  TIMER_OUTCFG7_OUTCFG31_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG7_OUTCFG31_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG7_OUTCFG31_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG7_OUTCFG31_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG7_OUTCFG31_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG7_OUTCFG31_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG7_OUTCFG31_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG7_OUTCFG31_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG7_OUTCFG31_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG7_OUTCFG31_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG7_OUTCFG31_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG7_OUTCFG31_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG7_OUTCFG31_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG7_OUTCFG31_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG7_OUTCFG31_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG7_OUTCFG31_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG7_OUTCFG31_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG7_OUTCFG31_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG7_OUTCFG31_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG7_OUTCFG31_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG7_OUTCFG31_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG7_OUTCFG31_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG7_OUTCFG31_Enum;

/* ============================================  TIMER OUTCFG7 OUTCFG30 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG7_OUTCFG30                                                    */
  TIMER_OUTCFG7_OUTCFG30_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG7_OUTCFG30_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG7_OUTCFG30_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG7_OUTCFG30_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG7_OUTCFG30_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG7_OUTCFG30_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG7_OUTCFG30_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG7_OUTCFG30_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG7_OUTCFG30_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG7_OUTCFG30_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG7_OUTCFG30_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG7_OUTCFG30_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG7_OUTCFG30_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG7_OUTCFG30_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG7_OUTCFG30_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG7_OUTCFG30_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG7_OUTCFG30_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG7_OUTCFG30_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG7_OUTCFG30_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG7_OUTCFG30_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG7_OUTCFG30_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG7_OUTCFG30_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG7_OUTCFG30_Enum;

/* ============================================  TIMER OUTCFG7 OUTCFG29 [8..13]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG7_OUTCFG29                                                    */
  TIMER_OUTCFG7_OUTCFG29_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG7_OUTCFG29_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG7_OUTCFG29_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG7_OUTCFG29_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG7_OUTCFG29_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG7_OUTCFG29_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG7_OUTCFG29_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG7_OUTCFG29_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG7_OUTCFG29_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG7_OUTCFG29_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG7_OUTCFG29_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG7_OUTCFG29_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG7_OUTCFG29_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG7_OUTCFG29_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG7_OUTCFG29_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG7_OUTCFG29_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG7_OUTCFG29_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG7_OUTCFG29_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG7_OUTCFG29_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG7_OUTCFG29_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG7_OUTCFG29_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG7_OUTCFG29_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG7_OUTCFG29_Enum;

/* =============================================  TIMER OUTCFG7 OUTCFG28 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG7_OUTCFG28                                                    */
  TIMER_OUTCFG7_OUTCFG28_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG7_OUTCFG28_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG7_OUTCFG28_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG7_OUTCFG28_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG7_OUTCFG28_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG7_OUTCFG28_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG7_OUTCFG28_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG7_OUTCFG28_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG7_OUTCFG28_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG7_OUTCFG28_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG7_OUTCFG28_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG7_OUTCFG28_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG7_OUTCFG28_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG7_OUTCFG28_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG7_OUTCFG28_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG7_OUTCFG28_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG7_OUTCFG28_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG7_OUTCFG28_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG7_OUTCFG28_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG7_OUTCFG28_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG7_OUTCFG28_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG7_OUTCFG28_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG7_OUTCFG28_Enum;

/* ========================================================  OUTCFG8  ======================================================== */
/* ============================================  TIMER OUTCFG8 OUTCFG35 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG8_OUTCFG35                                                    */
  TIMER_OUTCFG8_OUTCFG35_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG8_OUTCFG35_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG8_OUTCFG35_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG8_OUTCFG35_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG8_OUTCFG35_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG8_OUTCFG35_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG8_OUTCFG35_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG8_OUTCFG35_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG8_OUTCFG35_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG8_OUTCFG35_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG8_OUTCFG35_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG8_OUTCFG35_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG8_OUTCFG35_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG8_OUTCFG35_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG8_OUTCFG35_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG8_OUTCFG35_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG8_OUTCFG35_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG8_OUTCFG35_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG8_OUTCFG35_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG8_OUTCFG35_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG8_OUTCFG35_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG8_OUTCFG35_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG8_OUTCFG35_Enum;

/* ============================================  TIMER OUTCFG8 OUTCFG34 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG8_OUTCFG34                                                    */
  TIMER_OUTCFG8_OUTCFG34_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG8_OUTCFG34_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG8_OUTCFG34_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG8_OUTCFG34_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG8_OUTCFG34_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG8_OUTCFG34_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG8_OUTCFG34_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG8_OUTCFG34_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG8_OUTCFG34_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG8_OUTCFG34_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG8_OUTCFG34_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG8_OUTCFG34_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG8_OUTCFG34_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG8_OUTCFG34_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG8_OUTCFG34_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG8_OUTCFG34_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG8_OUTCFG34_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG8_OUTCFG34_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG8_OUTCFG34_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG8_OUTCFG34_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG8_OUTCFG34_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG8_OUTCFG34_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG8_OUTCFG34_Enum;

/* ============================================  TIMER OUTCFG8 OUTCFG33 [8..13]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG8_OUTCFG33                                                    */
  TIMER_OUTCFG8_OUTCFG33_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG8_OUTCFG33_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG8_OUTCFG33_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG8_OUTCFG33_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG8_OUTCFG33_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG8_OUTCFG33_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG8_OUTCFG33_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG8_OUTCFG33_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG8_OUTCFG33_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG8_OUTCFG33_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG8_OUTCFG33_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG8_OUTCFG33_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG8_OUTCFG33_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG8_OUTCFG33_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG8_OUTCFG33_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG8_OUTCFG33_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG8_OUTCFG33_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG8_OUTCFG33_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG8_OUTCFG33_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG8_OUTCFG33_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG8_OUTCFG33_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG8_OUTCFG33_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG8_OUTCFG33_Enum;

/* =============================================  TIMER OUTCFG8 OUTCFG32 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG8_OUTCFG32                                                    */
  TIMER_OUTCFG8_OUTCFG32_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG8_OUTCFG32_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG8_OUTCFG32_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG8_OUTCFG32_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG8_OUTCFG32_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG8_OUTCFG32_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG8_OUTCFG32_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG8_OUTCFG32_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG8_OUTCFG32_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG8_OUTCFG32_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG8_OUTCFG32_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG8_OUTCFG32_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG8_OUTCFG32_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG8_OUTCFG32_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG8_OUTCFG32_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG8_OUTCFG32_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG8_OUTCFG32_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG8_OUTCFG32_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG8_OUTCFG32_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG8_OUTCFG32_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG8_OUTCFG32_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG8_OUTCFG32_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG8_OUTCFG32_Enum;

/* ========================================================  OUTCFG9  ======================================================== */
/* ============================================  TIMER OUTCFG9 OUTCFG39 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG9_OUTCFG39                                                    */
  TIMER_OUTCFG9_OUTCFG39_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG9_OUTCFG39_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG9_OUTCFG39_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG9_OUTCFG39_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG9_OUTCFG39_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG9_OUTCFG39_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG9_OUTCFG39_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG9_OUTCFG39_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG9_OUTCFG39_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG9_OUTCFG39_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG9_OUTCFG39_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG9_OUTCFG39_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG9_OUTCFG39_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG9_OUTCFG39_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG9_OUTCFG39_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG9_OUTCFG39_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG9_OUTCFG39_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG9_OUTCFG39_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG9_OUTCFG39_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG9_OUTCFG39_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG9_OUTCFG39_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG9_OUTCFG39_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG9_OUTCFG39_Enum;

/* ============================================  TIMER OUTCFG9 OUTCFG38 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG9_OUTCFG38                                                    */
  TIMER_OUTCFG9_OUTCFG38_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG9_OUTCFG38_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG9_OUTCFG38_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG9_OUTCFG38_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG9_OUTCFG38_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG9_OUTCFG38_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG9_OUTCFG38_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG9_OUTCFG38_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG9_OUTCFG38_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG9_OUTCFG38_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG9_OUTCFG38_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG9_OUTCFG38_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG9_OUTCFG38_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG9_OUTCFG38_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG9_OUTCFG38_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG9_OUTCFG38_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG9_OUTCFG38_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG9_OUTCFG38_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG9_OUTCFG38_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG9_OUTCFG38_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG9_OUTCFG38_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG9_OUTCFG38_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG9_OUTCFG38_Enum;

/* ============================================  TIMER OUTCFG9 OUTCFG37 [8..13]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG9_OUTCFG37                                                    */
  TIMER_OUTCFG9_OUTCFG37_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG9_OUTCFG37_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG9_OUTCFG37_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG9_OUTCFG37_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG9_OUTCFG37_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG9_OUTCFG37_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG9_OUTCFG37_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG9_OUTCFG37_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG9_OUTCFG37_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG9_OUTCFG37_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG9_OUTCFG37_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG9_OUTCFG37_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG9_OUTCFG37_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG9_OUTCFG37_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG9_OUTCFG37_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG9_OUTCFG37_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG9_OUTCFG37_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG9_OUTCFG37_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG9_OUTCFG37_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG9_OUTCFG37_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG9_OUTCFG37_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG9_OUTCFG37_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG9_OUTCFG37_Enum;

/* =============================================  TIMER OUTCFG9 OUTCFG36 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG9_OUTCFG36                                                    */
  TIMER_OUTCFG9_OUTCFG36_TIMER00       = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER01       = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER10       = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER11       = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER20       = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER21       = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER30       = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER31       = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER40       = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER41       = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER50       = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER51       = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER60       = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER61       = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER70       = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER71       = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER80       = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER81       = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER90       = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER91       = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG9_OUTCFG36_TIMER100      = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG9_OUTCFG36_TIMER101      = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG9_OUTCFG36_TIMER110      = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG9_OUTCFG36_TIMER111      = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG9_OUTCFG36_TIMER120      = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG9_OUTCFG36_TIMER121      = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG9_OUTCFG36_TIMER130      = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG9_OUTCFG36_TIMER131      = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG9_OUTCFG36_TIMER140      = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG9_OUTCFG36_TIMER141      = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG9_OUTCFG36_TIMER150      = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG9_OUTCFG36_TIMER151      = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG9_OUTCFG36_STIMER0       = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG9_OUTCFG36_STIMER1       = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG9_OUTCFG36_STIMER2       = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG9_OUTCFG36_STIMER3       = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG9_OUTCFG36_STIMER4       = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG9_OUTCFG36_STIMER5       = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG9_OUTCFG36_STIMER6       = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG9_OUTCFG36_STIMER7       = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG9_OUTCFG36_DISABLED      = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG9_OUTCFG36_Enum;

/* =======================================================  OUTCFG10  ======================================================== */
/* ===========================================  TIMER OUTCFG10 OUTCFG43 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG10_OUTCFG43                                                   */
  TIMER_OUTCFG10_OUTCFG43_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG10_OUTCFG43_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG10_OUTCFG43_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG10_OUTCFG43_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG10_OUTCFG43_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG10_OUTCFG43_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG10_OUTCFG43_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG10_OUTCFG43_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG10_OUTCFG43_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG10_OUTCFG43_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG10_OUTCFG43_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG10_OUTCFG43_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG10_OUTCFG43_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG10_OUTCFG43_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG10_OUTCFG43_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG10_OUTCFG43_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG10_OUTCFG43_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG10_OUTCFG43_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG10_OUTCFG43_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG10_OUTCFG43_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG10_OUTCFG43_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG10_OUTCFG43_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG10_OUTCFG43_Enum;

/* ===========================================  TIMER OUTCFG10 OUTCFG42 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG10_OUTCFG42                                                   */
  TIMER_OUTCFG10_OUTCFG42_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG10_OUTCFG42_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG10_OUTCFG42_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG10_OUTCFG42_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG10_OUTCFG42_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG10_OUTCFG42_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG10_OUTCFG42_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG10_OUTCFG42_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG10_OUTCFG42_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG10_OUTCFG42_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG10_OUTCFG42_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG10_OUTCFG42_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG10_OUTCFG42_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG10_OUTCFG42_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG10_OUTCFG42_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG10_OUTCFG42_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG10_OUTCFG42_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG10_OUTCFG42_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG10_OUTCFG42_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG10_OUTCFG42_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG10_OUTCFG42_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG10_OUTCFG42_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG10_OUTCFG42_Enum;

/* ============================================  TIMER OUTCFG10 OUTCFG41 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG10_OUTCFG41                                                   */
  TIMER_OUTCFG10_OUTCFG41_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG10_OUTCFG41_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG10_OUTCFG41_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG10_OUTCFG41_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG10_OUTCFG41_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG10_OUTCFG41_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG10_OUTCFG41_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG10_OUTCFG41_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG10_OUTCFG41_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG10_OUTCFG41_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG10_OUTCFG41_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG10_OUTCFG41_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG10_OUTCFG41_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG10_OUTCFG41_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG10_OUTCFG41_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG10_OUTCFG41_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG10_OUTCFG41_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG10_OUTCFG41_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG10_OUTCFG41_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG10_OUTCFG41_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG10_OUTCFG41_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG10_OUTCFG41_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG10_OUTCFG41_Enum;

/* ============================================  TIMER OUTCFG10 OUTCFG40 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG10_OUTCFG40                                                   */
  TIMER_OUTCFG10_OUTCFG40_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG10_OUTCFG40_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG10_OUTCFG40_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG10_OUTCFG40_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG10_OUTCFG40_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG10_OUTCFG40_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG10_OUTCFG40_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG10_OUTCFG40_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG10_OUTCFG40_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG10_OUTCFG40_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG10_OUTCFG40_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG10_OUTCFG40_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG10_OUTCFG40_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG10_OUTCFG40_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG10_OUTCFG40_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG10_OUTCFG40_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG10_OUTCFG40_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG10_OUTCFG40_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG10_OUTCFG40_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG10_OUTCFG40_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG10_OUTCFG40_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG10_OUTCFG40_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG10_OUTCFG40_Enum;

/* =======================================================  OUTCFG11  ======================================================== */
/* ===========================================  TIMER OUTCFG11 OUTCFG47 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG11_OUTCFG47                                                   */
  TIMER_OUTCFG11_OUTCFG47_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG11_OUTCFG47_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG11_OUTCFG47_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG11_OUTCFG47_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG11_OUTCFG47_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG11_OUTCFG47_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG11_OUTCFG47_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG11_OUTCFG47_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG11_OUTCFG47_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG11_OUTCFG47_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG11_OUTCFG47_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG11_OUTCFG47_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG11_OUTCFG47_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG11_OUTCFG47_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG11_OUTCFG47_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG11_OUTCFG47_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG11_OUTCFG47_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG11_OUTCFG47_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG11_OUTCFG47_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG11_OUTCFG47_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG11_OUTCFG47_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG11_OUTCFG47_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG11_OUTCFG47_Enum;

/* ===========================================  TIMER OUTCFG11 OUTCFG46 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG11_OUTCFG46                                                   */
  TIMER_OUTCFG11_OUTCFG46_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG11_OUTCFG46_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG11_OUTCFG46_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG11_OUTCFG46_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG11_OUTCFG46_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG11_OUTCFG46_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG11_OUTCFG46_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG11_OUTCFG46_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG11_OUTCFG46_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG11_OUTCFG46_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG11_OUTCFG46_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG11_OUTCFG46_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG11_OUTCFG46_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG11_OUTCFG46_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG11_OUTCFG46_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG11_OUTCFG46_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG11_OUTCFG46_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG11_OUTCFG46_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG11_OUTCFG46_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG11_OUTCFG46_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG11_OUTCFG46_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG11_OUTCFG46_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG11_OUTCFG46_Enum;

/* ============================================  TIMER OUTCFG11 OUTCFG45 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG11_OUTCFG45                                                   */
  TIMER_OUTCFG11_OUTCFG45_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG11_OUTCFG45_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG11_OUTCFG45_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG11_OUTCFG45_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG11_OUTCFG45_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG11_OUTCFG45_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG11_OUTCFG45_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG11_OUTCFG45_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG11_OUTCFG45_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG11_OUTCFG45_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG11_OUTCFG45_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG11_OUTCFG45_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG11_OUTCFG45_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG11_OUTCFG45_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG11_OUTCFG45_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG11_OUTCFG45_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG11_OUTCFG45_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG11_OUTCFG45_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG11_OUTCFG45_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG11_OUTCFG45_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG11_OUTCFG45_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG11_OUTCFG45_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG11_OUTCFG45_Enum;

/* ============================================  TIMER OUTCFG11 OUTCFG44 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG11_OUTCFG44                                                   */
  TIMER_OUTCFG11_OUTCFG44_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG11_OUTCFG44_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG11_OUTCFG44_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG11_OUTCFG44_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG11_OUTCFG44_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG11_OUTCFG44_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG11_OUTCFG44_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG11_OUTCFG44_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG11_OUTCFG44_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG11_OUTCFG44_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG11_OUTCFG44_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG11_OUTCFG44_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG11_OUTCFG44_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG11_OUTCFG44_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG11_OUTCFG44_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG11_OUTCFG44_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG11_OUTCFG44_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG11_OUTCFG44_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG11_OUTCFG44_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG11_OUTCFG44_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG11_OUTCFG44_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG11_OUTCFG44_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG11_OUTCFG44_Enum;

/* =======================================================  OUTCFG12  ======================================================== */
/* ===========================================  TIMER OUTCFG12 OUTCFG51 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG12_OUTCFG51                                                   */
  TIMER_OUTCFG12_OUTCFG51_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG12_OUTCFG51_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG12_OUTCFG51_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG12_OUTCFG51_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG12_OUTCFG51_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG12_OUTCFG51_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG12_OUTCFG51_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG12_OUTCFG51_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG12_OUTCFG51_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG12_OUTCFG51_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG12_OUTCFG51_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG12_OUTCFG51_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG12_OUTCFG51_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG12_OUTCFG51_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG12_OUTCFG51_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG12_OUTCFG51_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG12_OUTCFG51_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG12_OUTCFG51_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG12_OUTCFG51_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG12_OUTCFG51_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG12_OUTCFG51_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG12_OUTCFG51_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG12_OUTCFG51_Enum;

/* ===========================================  TIMER OUTCFG12 OUTCFG50 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG12_OUTCFG50                                                   */
  TIMER_OUTCFG12_OUTCFG50_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG12_OUTCFG50_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG12_OUTCFG50_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG12_OUTCFG50_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG12_OUTCFG50_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG12_OUTCFG50_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG12_OUTCFG50_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG12_OUTCFG50_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG12_OUTCFG50_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG12_OUTCFG50_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG12_OUTCFG50_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG12_OUTCFG50_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG12_OUTCFG50_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG12_OUTCFG50_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG12_OUTCFG50_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG12_OUTCFG50_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG12_OUTCFG50_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG12_OUTCFG50_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG12_OUTCFG50_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG12_OUTCFG50_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG12_OUTCFG50_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG12_OUTCFG50_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG12_OUTCFG50_Enum;

/* ============================================  TIMER OUTCFG12 OUTCFG49 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG12_OUTCFG49                                                   */
  TIMER_OUTCFG12_OUTCFG49_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG12_OUTCFG49_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG12_OUTCFG49_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG12_OUTCFG49_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG12_OUTCFG49_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG12_OUTCFG49_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG12_OUTCFG49_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG12_OUTCFG49_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG12_OUTCFG49_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG12_OUTCFG49_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG12_OUTCFG49_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG12_OUTCFG49_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG12_OUTCFG49_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG12_OUTCFG49_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG12_OUTCFG49_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG12_OUTCFG49_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG12_OUTCFG49_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG12_OUTCFG49_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG12_OUTCFG49_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG12_OUTCFG49_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG12_OUTCFG49_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG12_OUTCFG49_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG12_OUTCFG49_Enum;

/* ============================================  TIMER OUTCFG12 OUTCFG48 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG12_OUTCFG48                                                   */
  TIMER_OUTCFG12_OUTCFG48_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG12_OUTCFG48_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG12_OUTCFG48_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG12_OUTCFG48_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG12_OUTCFG48_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG12_OUTCFG48_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG12_OUTCFG48_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG12_OUTCFG48_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG12_OUTCFG48_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG12_OUTCFG48_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG12_OUTCFG48_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG12_OUTCFG48_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG12_OUTCFG48_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG12_OUTCFG48_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG12_OUTCFG48_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG12_OUTCFG48_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG12_OUTCFG48_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG12_OUTCFG48_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG12_OUTCFG48_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG12_OUTCFG48_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG12_OUTCFG48_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG12_OUTCFG48_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG12_OUTCFG48_Enum;

/* =======================================================  OUTCFG13  ======================================================== */
/* ===========================================  TIMER OUTCFG13 OUTCFG55 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG13_OUTCFG55                                                   */
  TIMER_OUTCFG13_OUTCFG55_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG13_OUTCFG55_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG13_OUTCFG55_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG13_OUTCFG55_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG13_OUTCFG55_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG13_OUTCFG55_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG13_OUTCFG55_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG13_OUTCFG55_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG13_OUTCFG55_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG13_OUTCFG55_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG13_OUTCFG55_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG13_OUTCFG55_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG13_OUTCFG55_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG13_OUTCFG55_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG13_OUTCFG55_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG13_OUTCFG55_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG13_OUTCFG55_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG13_OUTCFG55_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG13_OUTCFG55_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG13_OUTCFG55_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG13_OUTCFG55_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG13_OUTCFG55_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG13_OUTCFG55_Enum;

/* ===========================================  TIMER OUTCFG13 OUTCFG54 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG13_OUTCFG54                                                   */
  TIMER_OUTCFG13_OUTCFG54_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG13_OUTCFG54_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG13_OUTCFG54_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG13_OUTCFG54_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG13_OUTCFG54_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG13_OUTCFG54_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG13_OUTCFG54_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG13_OUTCFG54_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG13_OUTCFG54_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG13_OUTCFG54_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG13_OUTCFG54_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG13_OUTCFG54_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG13_OUTCFG54_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG13_OUTCFG54_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG13_OUTCFG54_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG13_OUTCFG54_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG13_OUTCFG54_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG13_OUTCFG54_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG13_OUTCFG54_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG13_OUTCFG54_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG13_OUTCFG54_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG13_OUTCFG54_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG13_OUTCFG54_Enum;

/* ============================================  TIMER OUTCFG13 OUTCFG53 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG13_OUTCFG53                                                   */
  TIMER_OUTCFG13_OUTCFG53_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG13_OUTCFG53_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG13_OUTCFG53_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG13_OUTCFG53_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG13_OUTCFG53_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG13_OUTCFG53_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG13_OUTCFG53_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG13_OUTCFG53_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG13_OUTCFG53_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG13_OUTCFG53_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG13_OUTCFG53_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG13_OUTCFG53_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG13_OUTCFG53_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG13_OUTCFG53_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG13_OUTCFG53_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG13_OUTCFG53_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG13_OUTCFG53_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG13_OUTCFG53_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG13_OUTCFG53_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG13_OUTCFG53_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG13_OUTCFG53_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG13_OUTCFG53_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG13_OUTCFG53_Enum;

/* ============================================  TIMER OUTCFG13 OUTCFG52 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG13_OUTCFG52                                                   */
  TIMER_OUTCFG13_OUTCFG52_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG13_OUTCFG52_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG13_OUTCFG52_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG13_OUTCFG52_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG13_OUTCFG52_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG13_OUTCFG52_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG13_OUTCFG52_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG13_OUTCFG52_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG13_OUTCFG52_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG13_OUTCFG52_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG13_OUTCFG52_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG13_OUTCFG52_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG13_OUTCFG52_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG13_OUTCFG52_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG13_OUTCFG52_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG13_OUTCFG52_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG13_OUTCFG52_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG13_OUTCFG52_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG13_OUTCFG52_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG13_OUTCFG52_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG13_OUTCFG52_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG13_OUTCFG52_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG13_OUTCFG52_Enum;

/* =======================================================  OUTCFG14  ======================================================== */
/* ===========================================  TIMER OUTCFG14 OUTCFG59 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG14_OUTCFG59                                                   */
  TIMER_OUTCFG14_OUTCFG59_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG14_OUTCFG59_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG14_OUTCFG59_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG14_OUTCFG59_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG14_OUTCFG59_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG14_OUTCFG59_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG14_OUTCFG59_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG14_OUTCFG59_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG14_OUTCFG59_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG14_OUTCFG59_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG14_OUTCFG59_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG14_OUTCFG59_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG14_OUTCFG59_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG14_OUTCFG59_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG14_OUTCFG59_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG14_OUTCFG59_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG14_OUTCFG59_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG14_OUTCFG59_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG14_OUTCFG59_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG14_OUTCFG59_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG14_OUTCFG59_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG14_OUTCFG59_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG14_OUTCFG59_Enum;

/* ===========================================  TIMER OUTCFG14 OUTCFG58 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG14_OUTCFG58                                                   */
  TIMER_OUTCFG14_OUTCFG58_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG14_OUTCFG58_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG14_OUTCFG58_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG14_OUTCFG58_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG14_OUTCFG58_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG14_OUTCFG58_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG14_OUTCFG58_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG14_OUTCFG58_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG14_OUTCFG58_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG14_OUTCFG58_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG14_OUTCFG58_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG14_OUTCFG58_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG14_OUTCFG58_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG14_OUTCFG58_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG14_OUTCFG58_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG14_OUTCFG58_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG14_OUTCFG58_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG14_OUTCFG58_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG14_OUTCFG58_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG14_OUTCFG58_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG14_OUTCFG58_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG14_OUTCFG58_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG14_OUTCFG58_Enum;

/* ============================================  TIMER OUTCFG14 OUTCFG57 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG14_OUTCFG57                                                   */
  TIMER_OUTCFG14_OUTCFG57_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG14_OUTCFG57_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG14_OUTCFG57_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG14_OUTCFG57_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG14_OUTCFG57_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG14_OUTCFG57_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG14_OUTCFG57_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG14_OUTCFG57_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG14_OUTCFG57_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG14_OUTCFG57_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG14_OUTCFG57_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG14_OUTCFG57_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG14_OUTCFG57_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG14_OUTCFG57_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG14_OUTCFG57_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG14_OUTCFG57_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG14_OUTCFG57_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG14_OUTCFG57_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG14_OUTCFG57_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG14_OUTCFG57_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG14_OUTCFG57_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG14_OUTCFG57_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG14_OUTCFG57_Enum;

/* ============================================  TIMER OUTCFG14 OUTCFG56 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG14_OUTCFG56                                                   */
  TIMER_OUTCFG14_OUTCFG56_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG14_OUTCFG56_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG14_OUTCFG56_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG14_OUTCFG56_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG14_OUTCFG56_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG14_OUTCFG56_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG14_OUTCFG56_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG14_OUTCFG56_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG14_OUTCFG56_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG14_OUTCFG56_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG14_OUTCFG56_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG14_OUTCFG56_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG14_OUTCFG56_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG14_OUTCFG56_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG14_OUTCFG56_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG14_OUTCFG56_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG14_OUTCFG56_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG14_OUTCFG56_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG14_OUTCFG56_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG14_OUTCFG56_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG14_OUTCFG56_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG14_OUTCFG56_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG14_OUTCFG56_Enum;

/* =======================================================  OUTCFG15  ======================================================== */
/* ===========================================  TIMER OUTCFG15 OUTCFG63 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG15_OUTCFG63                                                   */
  TIMER_OUTCFG15_OUTCFG63_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG15_OUTCFG63_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG15_OUTCFG63_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG15_OUTCFG63_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG15_OUTCFG63_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG15_OUTCFG63_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG15_OUTCFG63_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG15_OUTCFG63_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG15_OUTCFG63_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG15_OUTCFG63_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG15_OUTCFG63_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG15_OUTCFG63_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG15_OUTCFG63_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG15_OUTCFG63_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG15_OUTCFG63_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG15_OUTCFG63_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG15_OUTCFG63_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG15_OUTCFG63_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG15_OUTCFG63_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG15_OUTCFG63_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG15_OUTCFG63_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG15_OUTCFG63_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG15_OUTCFG63_Enum;

/* ===========================================  TIMER OUTCFG15 OUTCFG62 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG15_OUTCFG62                                                   */
  TIMER_OUTCFG15_OUTCFG62_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG15_OUTCFG62_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG15_OUTCFG62_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG15_OUTCFG62_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG15_OUTCFG62_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG15_OUTCFG62_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG15_OUTCFG62_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG15_OUTCFG62_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG15_OUTCFG62_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG15_OUTCFG62_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG15_OUTCFG62_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG15_OUTCFG62_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG15_OUTCFG62_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG15_OUTCFG62_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG15_OUTCFG62_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG15_OUTCFG62_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG15_OUTCFG62_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG15_OUTCFG62_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG15_OUTCFG62_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG15_OUTCFG62_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG15_OUTCFG62_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG15_OUTCFG62_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG15_OUTCFG62_Enum;

/* ============================================  TIMER OUTCFG15 OUTCFG61 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG15_OUTCFG61                                                   */
  TIMER_OUTCFG15_OUTCFG61_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG15_OUTCFG61_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG15_OUTCFG61_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG15_OUTCFG61_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG15_OUTCFG61_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG15_OUTCFG61_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG15_OUTCFG61_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG15_OUTCFG61_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG15_OUTCFG61_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG15_OUTCFG61_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG15_OUTCFG61_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG15_OUTCFG61_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG15_OUTCFG61_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG15_OUTCFG61_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG15_OUTCFG61_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG15_OUTCFG61_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG15_OUTCFG61_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG15_OUTCFG61_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG15_OUTCFG61_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG15_OUTCFG61_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG15_OUTCFG61_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG15_OUTCFG61_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG15_OUTCFG61_Enum;

/* ============================================  TIMER OUTCFG15 OUTCFG60 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG15_OUTCFG60                                                   */
  TIMER_OUTCFG15_OUTCFG60_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG15_OUTCFG60_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG15_OUTCFG60_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG15_OUTCFG60_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG15_OUTCFG60_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG15_OUTCFG60_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG15_OUTCFG60_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG15_OUTCFG60_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG15_OUTCFG60_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG15_OUTCFG60_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG15_OUTCFG60_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG15_OUTCFG60_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG15_OUTCFG60_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG15_OUTCFG60_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG15_OUTCFG60_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG15_OUTCFG60_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG15_OUTCFG60_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG15_OUTCFG60_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG15_OUTCFG60_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG15_OUTCFG60_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG15_OUTCFG60_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG15_OUTCFG60_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG15_OUTCFG60_Enum;

/* =======================================================  OUTCFG16  ======================================================== */
/* ===========================================  TIMER OUTCFG16 OUTCFG67 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG16_OUTCFG67                                                   */
  TIMER_OUTCFG16_OUTCFG67_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG16_OUTCFG67_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG16_OUTCFG67_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG16_OUTCFG67_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG16_OUTCFG67_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG16_OUTCFG67_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG16_OUTCFG67_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG16_OUTCFG67_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG16_OUTCFG67_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG16_OUTCFG67_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG16_OUTCFG67_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG16_OUTCFG67_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG16_OUTCFG67_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG16_OUTCFG67_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG16_OUTCFG67_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG16_OUTCFG67_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG16_OUTCFG67_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG16_OUTCFG67_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG16_OUTCFG67_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG16_OUTCFG67_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG16_OUTCFG67_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG16_OUTCFG67_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG16_OUTCFG67_Enum;

/* ===========================================  TIMER OUTCFG16 OUTCFG66 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG16_OUTCFG66                                                   */
  TIMER_OUTCFG16_OUTCFG66_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG16_OUTCFG66_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG16_OUTCFG66_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG16_OUTCFG66_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG16_OUTCFG66_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG16_OUTCFG66_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG16_OUTCFG66_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG16_OUTCFG66_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG16_OUTCFG66_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG16_OUTCFG66_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG16_OUTCFG66_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG16_OUTCFG66_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG16_OUTCFG66_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG16_OUTCFG66_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG16_OUTCFG66_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG16_OUTCFG66_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG16_OUTCFG66_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG16_OUTCFG66_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG16_OUTCFG66_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG16_OUTCFG66_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG16_OUTCFG66_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG16_OUTCFG66_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG16_OUTCFG66_Enum;

/* ============================================  TIMER OUTCFG16 OUTCFG65 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG16_OUTCFG65                                                   */
  TIMER_OUTCFG16_OUTCFG65_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG16_OUTCFG65_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG16_OUTCFG65_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG16_OUTCFG65_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG16_OUTCFG65_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG16_OUTCFG65_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG16_OUTCFG65_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG16_OUTCFG65_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG16_OUTCFG65_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG16_OUTCFG65_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG16_OUTCFG65_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG16_OUTCFG65_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG16_OUTCFG65_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG16_OUTCFG65_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG16_OUTCFG65_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG16_OUTCFG65_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG16_OUTCFG65_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG16_OUTCFG65_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG16_OUTCFG65_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG16_OUTCFG65_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG16_OUTCFG65_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG16_OUTCFG65_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG16_OUTCFG65_Enum;

/* ============================================  TIMER OUTCFG16 OUTCFG64 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG16_OUTCFG64                                                   */
  TIMER_OUTCFG16_OUTCFG64_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG16_OUTCFG64_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG16_OUTCFG64_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG16_OUTCFG64_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG16_OUTCFG64_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG16_OUTCFG64_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG16_OUTCFG64_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG16_OUTCFG64_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG16_OUTCFG64_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG16_OUTCFG64_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG16_OUTCFG64_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG16_OUTCFG64_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG16_OUTCFG64_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG16_OUTCFG64_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG16_OUTCFG64_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG16_OUTCFG64_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG16_OUTCFG64_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG16_OUTCFG64_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG16_OUTCFG64_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG16_OUTCFG64_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG16_OUTCFG64_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG16_OUTCFG64_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG16_OUTCFG64_Enum;

/* =======================================================  OUTCFG17  ======================================================== */
/* ===========================================  TIMER OUTCFG17 OUTCFG71 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG17_OUTCFG71                                                   */
  TIMER_OUTCFG17_OUTCFG71_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG17_OUTCFG71_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG17_OUTCFG71_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG17_OUTCFG71_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG17_OUTCFG71_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG17_OUTCFG71_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG17_OUTCFG71_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG17_OUTCFG71_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG17_OUTCFG71_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG17_OUTCFG71_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG17_OUTCFG71_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG17_OUTCFG71_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG17_OUTCFG71_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG17_OUTCFG71_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG17_OUTCFG71_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG17_OUTCFG71_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG17_OUTCFG71_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG17_OUTCFG71_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG17_OUTCFG71_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG17_OUTCFG71_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG17_OUTCFG71_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG17_OUTCFG71_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG17_OUTCFG71_Enum;

/* ===========================================  TIMER OUTCFG17 OUTCFG70 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG17_OUTCFG70                                                   */
  TIMER_OUTCFG17_OUTCFG70_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG17_OUTCFG70_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG17_OUTCFG70_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG17_OUTCFG70_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG17_OUTCFG70_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG17_OUTCFG70_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG17_OUTCFG70_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG17_OUTCFG70_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG17_OUTCFG70_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG17_OUTCFG70_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG17_OUTCFG70_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG17_OUTCFG70_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG17_OUTCFG70_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG17_OUTCFG70_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG17_OUTCFG70_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG17_OUTCFG70_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG17_OUTCFG70_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG17_OUTCFG70_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG17_OUTCFG70_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG17_OUTCFG70_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG17_OUTCFG70_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG17_OUTCFG70_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG17_OUTCFG70_Enum;

/* ============================================  TIMER OUTCFG17 OUTCFG69 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG17_OUTCFG69                                                   */
  TIMER_OUTCFG17_OUTCFG69_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG17_OUTCFG69_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG17_OUTCFG69_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG17_OUTCFG69_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG17_OUTCFG69_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG17_OUTCFG69_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG17_OUTCFG69_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG17_OUTCFG69_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG17_OUTCFG69_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG17_OUTCFG69_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG17_OUTCFG69_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG17_OUTCFG69_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG17_OUTCFG69_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG17_OUTCFG69_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG17_OUTCFG69_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG17_OUTCFG69_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG17_OUTCFG69_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG17_OUTCFG69_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG17_OUTCFG69_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG17_OUTCFG69_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG17_OUTCFG69_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG17_OUTCFG69_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG17_OUTCFG69_Enum;

/* ============================================  TIMER OUTCFG17 OUTCFG68 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG17_OUTCFG68                                                   */
  TIMER_OUTCFG17_OUTCFG68_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG17_OUTCFG68_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG17_OUTCFG68_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG17_OUTCFG68_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG17_OUTCFG68_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG17_OUTCFG68_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG17_OUTCFG68_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG17_OUTCFG68_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG17_OUTCFG68_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG17_OUTCFG68_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG17_OUTCFG68_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG17_OUTCFG68_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG17_OUTCFG68_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG17_OUTCFG68_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG17_OUTCFG68_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG17_OUTCFG68_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG17_OUTCFG68_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG17_OUTCFG68_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG17_OUTCFG68_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG17_OUTCFG68_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG17_OUTCFG68_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG17_OUTCFG68_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG17_OUTCFG68_Enum;

/* =======================================================  OUTCFG18  ======================================================== */
/* ===========================================  TIMER OUTCFG18 OUTCFG75 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG18_OUTCFG75                                                   */
  TIMER_OUTCFG18_OUTCFG75_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG18_OUTCFG75_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG18_OUTCFG75_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG18_OUTCFG75_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG18_OUTCFG75_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG18_OUTCFG75_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG18_OUTCFG75_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG18_OUTCFG75_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG18_OUTCFG75_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG18_OUTCFG75_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG18_OUTCFG75_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG18_OUTCFG75_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG18_OUTCFG75_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG18_OUTCFG75_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG18_OUTCFG75_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG18_OUTCFG75_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG18_OUTCFG75_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG18_OUTCFG75_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG18_OUTCFG75_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG18_OUTCFG75_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG18_OUTCFG75_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG18_OUTCFG75_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG18_OUTCFG75_Enum;

/* ===========================================  TIMER OUTCFG18 OUTCFG74 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG18_OUTCFG74                                                   */
  TIMER_OUTCFG18_OUTCFG74_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG18_OUTCFG74_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG18_OUTCFG74_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG18_OUTCFG74_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG18_OUTCFG74_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG18_OUTCFG74_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG18_OUTCFG74_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG18_OUTCFG74_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG18_OUTCFG74_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG18_OUTCFG74_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG18_OUTCFG74_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG18_OUTCFG74_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG18_OUTCFG74_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG18_OUTCFG74_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG18_OUTCFG74_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG18_OUTCFG74_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG18_OUTCFG74_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG18_OUTCFG74_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG18_OUTCFG74_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG18_OUTCFG74_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG18_OUTCFG74_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG18_OUTCFG74_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG18_OUTCFG74_Enum;

/* ============================================  TIMER OUTCFG18 OUTCFG73 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG18_OUTCFG73                                                   */
  TIMER_OUTCFG18_OUTCFG73_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG18_OUTCFG73_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG18_OUTCFG73_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG18_OUTCFG73_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG18_OUTCFG73_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG18_OUTCFG73_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG18_OUTCFG73_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG18_OUTCFG73_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG18_OUTCFG73_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG18_OUTCFG73_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG18_OUTCFG73_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG18_OUTCFG73_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG18_OUTCFG73_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG18_OUTCFG73_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG18_OUTCFG73_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG18_OUTCFG73_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG18_OUTCFG73_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG18_OUTCFG73_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG18_OUTCFG73_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG18_OUTCFG73_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG18_OUTCFG73_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG18_OUTCFG73_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG18_OUTCFG73_Enum;

/* ============================================  TIMER OUTCFG18 OUTCFG72 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG18_OUTCFG72                                                   */
  TIMER_OUTCFG18_OUTCFG72_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG18_OUTCFG72_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG18_OUTCFG72_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG18_OUTCFG72_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG18_OUTCFG72_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG18_OUTCFG72_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG18_OUTCFG72_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG18_OUTCFG72_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG18_OUTCFG72_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG18_OUTCFG72_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG18_OUTCFG72_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG18_OUTCFG72_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG18_OUTCFG72_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG18_OUTCFG72_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG18_OUTCFG72_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG18_OUTCFG72_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG18_OUTCFG72_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG18_OUTCFG72_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG18_OUTCFG72_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG18_OUTCFG72_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG18_OUTCFG72_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG18_OUTCFG72_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG18_OUTCFG72_Enum;

/* =======================================================  OUTCFG19  ======================================================== */
/* ===========================================  TIMER OUTCFG19 OUTCFG79 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG19_OUTCFG79                                                   */
  TIMER_OUTCFG19_OUTCFG79_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG19_OUTCFG79_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG19_OUTCFG79_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG19_OUTCFG79_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG19_OUTCFG79_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG19_OUTCFG79_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG19_OUTCFG79_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG19_OUTCFG79_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG19_OUTCFG79_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG19_OUTCFG79_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG19_OUTCFG79_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG19_OUTCFG79_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG19_OUTCFG79_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG19_OUTCFG79_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG19_OUTCFG79_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG19_OUTCFG79_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG19_OUTCFG79_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG19_OUTCFG79_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG19_OUTCFG79_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG19_OUTCFG79_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG19_OUTCFG79_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG19_OUTCFG79_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG19_OUTCFG79_Enum;

/* ===========================================  TIMER OUTCFG19 OUTCFG78 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG19_OUTCFG78                                                   */
  TIMER_OUTCFG19_OUTCFG78_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG19_OUTCFG78_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG19_OUTCFG78_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG19_OUTCFG78_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG19_OUTCFG78_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG19_OUTCFG78_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG19_OUTCFG78_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG19_OUTCFG78_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG19_OUTCFG78_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG19_OUTCFG78_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG19_OUTCFG78_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG19_OUTCFG78_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG19_OUTCFG78_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG19_OUTCFG78_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG19_OUTCFG78_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG19_OUTCFG78_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG19_OUTCFG78_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG19_OUTCFG78_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG19_OUTCFG78_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG19_OUTCFG78_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG19_OUTCFG78_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG19_OUTCFG78_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG19_OUTCFG78_Enum;

/* ============================================  TIMER OUTCFG19 OUTCFG77 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG19_OUTCFG77                                                   */
  TIMER_OUTCFG19_OUTCFG77_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG19_OUTCFG77_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG19_OUTCFG77_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG19_OUTCFG77_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG19_OUTCFG77_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG19_OUTCFG77_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG19_OUTCFG77_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG19_OUTCFG77_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG19_OUTCFG77_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG19_OUTCFG77_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG19_OUTCFG77_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG19_OUTCFG77_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG19_OUTCFG77_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG19_OUTCFG77_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG19_OUTCFG77_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG19_OUTCFG77_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG19_OUTCFG77_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG19_OUTCFG77_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG19_OUTCFG77_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG19_OUTCFG77_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG19_OUTCFG77_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG19_OUTCFG77_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG19_OUTCFG77_Enum;

/* ============================================  TIMER OUTCFG19 OUTCFG76 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG19_OUTCFG76                                                   */
  TIMER_OUTCFG19_OUTCFG76_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG19_OUTCFG76_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG19_OUTCFG76_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG19_OUTCFG76_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG19_OUTCFG76_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG19_OUTCFG76_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG19_OUTCFG76_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG19_OUTCFG76_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG19_OUTCFG76_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG19_OUTCFG76_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG19_OUTCFG76_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG19_OUTCFG76_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG19_OUTCFG76_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG19_OUTCFG76_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG19_OUTCFG76_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG19_OUTCFG76_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG19_OUTCFG76_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG19_OUTCFG76_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG19_OUTCFG76_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG19_OUTCFG76_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG19_OUTCFG76_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG19_OUTCFG76_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG19_OUTCFG76_Enum;

/* =======================================================  OUTCFG20  ======================================================== */
/* ===========================================  TIMER OUTCFG20 OUTCFG83 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG20_OUTCFG83                                                   */
  TIMER_OUTCFG20_OUTCFG83_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG20_OUTCFG83_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG20_OUTCFG83_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG20_OUTCFG83_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG20_OUTCFG83_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG20_OUTCFG83_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG20_OUTCFG83_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG20_OUTCFG83_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG20_OUTCFG83_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG20_OUTCFG83_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG20_OUTCFG83_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG20_OUTCFG83_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG20_OUTCFG83_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG20_OUTCFG83_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG20_OUTCFG83_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG20_OUTCFG83_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG20_OUTCFG83_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG20_OUTCFG83_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG20_OUTCFG83_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG20_OUTCFG83_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG20_OUTCFG83_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG20_OUTCFG83_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG20_OUTCFG83_Enum;

/* ===========================================  TIMER OUTCFG20 OUTCFG82 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG20_OUTCFG82                                                   */
  TIMER_OUTCFG20_OUTCFG82_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG20_OUTCFG82_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG20_OUTCFG82_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG20_OUTCFG82_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG20_OUTCFG82_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG20_OUTCFG82_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG20_OUTCFG82_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG20_OUTCFG82_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG20_OUTCFG82_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG20_OUTCFG82_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG20_OUTCFG82_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG20_OUTCFG82_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG20_OUTCFG82_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG20_OUTCFG82_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG20_OUTCFG82_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG20_OUTCFG82_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG20_OUTCFG82_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG20_OUTCFG82_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG20_OUTCFG82_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG20_OUTCFG82_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG20_OUTCFG82_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG20_OUTCFG82_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG20_OUTCFG82_Enum;

/* ============================================  TIMER OUTCFG20 OUTCFG81 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG20_OUTCFG81                                                   */
  TIMER_OUTCFG20_OUTCFG81_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG20_OUTCFG81_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG20_OUTCFG81_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG20_OUTCFG81_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG20_OUTCFG81_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG20_OUTCFG81_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG20_OUTCFG81_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG20_OUTCFG81_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG20_OUTCFG81_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG20_OUTCFG81_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG20_OUTCFG81_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG20_OUTCFG81_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG20_OUTCFG81_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG20_OUTCFG81_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG20_OUTCFG81_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG20_OUTCFG81_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG20_OUTCFG81_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG20_OUTCFG81_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG20_OUTCFG81_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG20_OUTCFG81_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG20_OUTCFG81_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG20_OUTCFG81_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG20_OUTCFG81_Enum;

/* ============================================  TIMER OUTCFG20 OUTCFG80 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG20_OUTCFG80                                                   */
  TIMER_OUTCFG20_OUTCFG80_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG20_OUTCFG80_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG20_OUTCFG80_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG20_OUTCFG80_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG20_OUTCFG80_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG20_OUTCFG80_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG20_OUTCFG80_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG20_OUTCFG80_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG20_OUTCFG80_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG20_OUTCFG80_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG20_OUTCFG80_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG20_OUTCFG80_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG20_OUTCFG80_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG20_OUTCFG80_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG20_OUTCFG80_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG20_OUTCFG80_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG20_OUTCFG80_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG20_OUTCFG80_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG20_OUTCFG80_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG20_OUTCFG80_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG20_OUTCFG80_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG20_OUTCFG80_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG20_OUTCFG80_Enum;

/* =======================================================  OUTCFG21  ======================================================== */
/* ===========================================  TIMER OUTCFG21 OUTCFG87 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG21_OUTCFG87                                                   */
  TIMER_OUTCFG21_OUTCFG87_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG21_OUTCFG87_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG21_OUTCFG87_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG21_OUTCFG87_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG21_OUTCFG87_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG21_OUTCFG87_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG21_OUTCFG87_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG21_OUTCFG87_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG21_OUTCFG87_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG21_OUTCFG87_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG21_OUTCFG87_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG21_OUTCFG87_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG21_OUTCFG87_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG21_OUTCFG87_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG21_OUTCFG87_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG21_OUTCFG87_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG21_OUTCFG87_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG21_OUTCFG87_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG21_OUTCFG87_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG21_OUTCFG87_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG21_OUTCFG87_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG21_OUTCFG87_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG21_OUTCFG87_Enum;

/* ===========================================  TIMER OUTCFG21 OUTCFG86 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG21_OUTCFG86                                                   */
  TIMER_OUTCFG21_OUTCFG86_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG21_OUTCFG86_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG21_OUTCFG86_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG21_OUTCFG86_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG21_OUTCFG86_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG21_OUTCFG86_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG21_OUTCFG86_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG21_OUTCFG86_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG21_OUTCFG86_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG21_OUTCFG86_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG21_OUTCFG86_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG21_OUTCFG86_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG21_OUTCFG86_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG21_OUTCFG86_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG21_OUTCFG86_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG21_OUTCFG86_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG21_OUTCFG86_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG21_OUTCFG86_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG21_OUTCFG86_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG21_OUTCFG86_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG21_OUTCFG86_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG21_OUTCFG86_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG21_OUTCFG86_Enum;

/* ============================================  TIMER OUTCFG21 OUTCFG85 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG21_OUTCFG85                                                   */
  TIMER_OUTCFG21_OUTCFG85_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG21_OUTCFG85_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG21_OUTCFG85_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG21_OUTCFG85_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG21_OUTCFG85_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG21_OUTCFG85_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG21_OUTCFG85_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG21_OUTCFG85_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG21_OUTCFG85_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG21_OUTCFG85_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG21_OUTCFG85_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG21_OUTCFG85_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG21_OUTCFG85_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG21_OUTCFG85_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG21_OUTCFG85_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG21_OUTCFG85_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG21_OUTCFG85_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG21_OUTCFG85_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG21_OUTCFG85_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG21_OUTCFG85_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG21_OUTCFG85_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG21_OUTCFG85_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG21_OUTCFG85_Enum;

/* ============================================  TIMER OUTCFG21 OUTCFG84 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG21_OUTCFG84                                                   */
  TIMER_OUTCFG21_OUTCFG84_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG21_OUTCFG84_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG21_OUTCFG84_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG21_OUTCFG84_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG21_OUTCFG84_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG21_OUTCFG84_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG21_OUTCFG84_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG21_OUTCFG84_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG21_OUTCFG84_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG21_OUTCFG84_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG21_OUTCFG84_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG21_OUTCFG84_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG21_OUTCFG84_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG21_OUTCFG84_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG21_OUTCFG84_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG21_OUTCFG84_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG21_OUTCFG84_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG21_OUTCFG84_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG21_OUTCFG84_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG21_OUTCFG84_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG21_OUTCFG84_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG21_OUTCFG84_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG21_OUTCFG84_Enum;

/* =======================================================  OUTCFG22  ======================================================== */
/* ===========================================  TIMER OUTCFG22 OUTCFG91 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG22_OUTCFG91                                                   */
  TIMER_OUTCFG22_OUTCFG91_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG22_OUTCFG91_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG22_OUTCFG91_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG22_OUTCFG91_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG22_OUTCFG91_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG22_OUTCFG91_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG22_OUTCFG91_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG22_OUTCFG91_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG22_OUTCFG91_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG22_OUTCFG91_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG22_OUTCFG91_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG22_OUTCFG91_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG22_OUTCFG91_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG22_OUTCFG91_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG22_OUTCFG91_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG22_OUTCFG91_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG22_OUTCFG91_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG22_OUTCFG91_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG22_OUTCFG91_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG22_OUTCFG91_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG22_OUTCFG91_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG22_OUTCFG91_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG22_OUTCFG91_Enum;

/* ===========================================  TIMER OUTCFG22 OUTCFG90 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG22_OUTCFG90                                                   */
  TIMER_OUTCFG22_OUTCFG90_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG22_OUTCFG90_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG22_OUTCFG90_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG22_OUTCFG90_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG22_OUTCFG90_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG22_OUTCFG90_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG22_OUTCFG90_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG22_OUTCFG90_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG22_OUTCFG90_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG22_OUTCFG90_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG22_OUTCFG90_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG22_OUTCFG90_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG22_OUTCFG90_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG22_OUTCFG90_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG22_OUTCFG90_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG22_OUTCFG90_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG22_OUTCFG90_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG22_OUTCFG90_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG22_OUTCFG90_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG22_OUTCFG90_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG22_OUTCFG90_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG22_OUTCFG90_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG22_OUTCFG90_Enum;

/* ============================================  TIMER OUTCFG22 OUTCFG89 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG22_OUTCFG89                                                   */
  TIMER_OUTCFG22_OUTCFG89_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG22_OUTCFG89_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG22_OUTCFG89_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG22_OUTCFG89_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG22_OUTCFG89_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG22_OUTCFG89_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG22_OUTCFG89_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG22_OUTCFG89_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG22_OUTCFG89_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG22_OUTCFG89_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG22_OUTCFG89_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG22_OUTCFG89_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG22_OUTCFG89_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG22_OUTCFG89_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG22_OUTCFG89_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG22_OUTCFG89_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG22_OUTCFG89_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG22_OUTCFG89_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG22_OUTCFG89_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG22_OUTCFG89_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG22_OUTCFG89_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG22_OUTCFG89_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG22_OUTCFG89_Enum;

/* ============================================  TIMER OUTCFG22 OUTCFG88 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG22_OUTCFG88                                                   */
  TIMER_OUTCFG22_OUTCFG88_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG22_OUTCFG88_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG22_OUTCFG88_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG22_OUTCFG88_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG22_OUTCFG88_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG22_OUTCFG88_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG22_OUTCFG88_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG22_OUTCFG88_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG22_OUTCFG88_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG22_OUTCFG88_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG22_OUTCFG88_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG22_OUTCFG88_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG22_OUTCFG88_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG22_OUTCFG88_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG22_OUTCFG88_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG22_OUTCFG88_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG22_OUTCFG88_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG22_OUTCFG88_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG22_OUTCFG88_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG22_OUTCFG88_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG22_OUTCFG88_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG22_OUTCFG88_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG22_OUTCFG88_Enum;

/* =======================================================  OUTCFG23  ======================================================== */
/* ===========================================  TIMER OUTCFG23 OUTCFG95 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG23_OUTCFG95                                                   */
  TIMER_OUTCFG23_OUTCFG95_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG23_OUTCFG95_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG23_OUTCFG95_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG23_OUTCFG95_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG23_OUTCFG95_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG23_OUTCFG95_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG23_OUTCFG95_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG23_OUTCFG95_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG23_OUTCFG95_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG23_OUTCFG95_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG23_OUTCFG95_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG23_OUTCFG95_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG23_OUTCFG95_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG23_OUTCFG95_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG23_OUTCFG95_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG23_OUTCFG95_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG23_OUTCFG95_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG23_OUTCFG95_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG23_OUTCFG95_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG23_OUTCFG95_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG23_OUTCFG95_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG23_OUTCFG95_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG23_OUTCFG95_Enum;

/* ===========================================  TIMER OUTCFG23 OUTCFG94 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG23_OUTCFG94                                                   */
  TIMER_OUTCFG23_OUTCFG94_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG23_OUTCFG94_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG23_OUTCFG94_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG23_OUTCFG94_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG23_OUTCFG94_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG23_OUTCFG94_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG23_OUTCFG94_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG23_OUTCFG94_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG23_OUTCFG94_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG23_OUTCFG94_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG23_OUTCFG94_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG23_OUTCFG94_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG23_OUTCFG94_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG23_OUTCFG94_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG23_OUTCFG94_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG23_OUTCFG94_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG23_OUTCFG94_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG23_OUTCFG94_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG23_OUTCFG94_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG23_OUTCFG94_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG23_OUTCFG94_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG23_OUTCFG94_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG23_OUTCFG94_Enum;

/* ============================================  TIMER OUTCFG23 OUTCFG93 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG23_OUTCFG93                                                   */
  TIMER_OUTCFG23_OUTCFG93_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG23_OUTCFG93_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG23_OUTCFG93_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG23_OUTCFG93_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG23_OUTCFG93_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG23_OUTCFG93_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG23_OUTCFG93_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG23_OUTCFG93_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG23_OUTCFG93_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG23_OUTCFG93_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG23_OUTCFG93_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG23_OUTCFG93_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG23_OUTCFG93_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG23_OUTCFG93_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG23_OUTCFG93_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG23_OUTCFG93_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG23_OUTCFG93_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG23_OUTCFG93_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG23_OUTCFG93_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG23_OUTCFG93_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG23_OUTCFG93_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG23_OUTCFG93_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG23_OUTCFG93_Enum;

/* ============================================  TIMER OUTCFG23 OUTCFG92 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG23_OUTCFG92                                                   */
  TIMER_OUTCFG23_OUTCFG92_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG23_OUTCFG92_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG23_OUTCFG92_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG23_OUTCFG92_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG23_OUTCFG92_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG23_OUTCFG92_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG23_OUTCFG92_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG23_OUTCFG92_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG23_OUTCFG92_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG23_OUTCFG92_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG23_OUTCFG92_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG23_OUTCFG92_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG23_OUTCFG92_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG23_OUTCFG92_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG23_OUTCFG92_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG23_OUTCFG92_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG23_OUTCFG92_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG23_OUTCFG92_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG23_OUTCFG92_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG23_OUTCFG92_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG23_OUTCFG92_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG23_OUTCFG92_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG23_OUTCFG92_Enum;

/* =======================================================  OUTCFG24  ======================================================== */
/* ===========================================  TIMER OUTCFG24 OUTCFG99 [24..29]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG24_OUTCFG99                                                   */
  TIMER_OUTCFG24_OUTCFG99_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG24_OUTCFG99_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG24_OUTCFG99_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG24_OUTCFG99_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG24_OUTCFG99_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG24_OUTCFG99_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG24_OUTCFG99_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG24_OUTCFG99_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG24_OUTCFG99_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG24_OUTCFG99_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG24_OUTCFG99_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG24_OUTCFG99_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG24_OUTCFG99_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG24_OUTCFG99_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG24_OUTCFG99_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG24_OUTCFG99_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG24_OUTCFG99_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG24_OUTCFG99_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG24_OUTCFG99_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG24_OUTCFG99_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG24_OUTCFG99_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG24_OUTCFG99_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG24_OUTCFG99_Enum;

/* ===========================================  TIMER OUTCFG24 OUTCFG98 [16..21]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG24_OUTCFG98                                                   */
  TIMER_OUTCFG24_OUTCFG98_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG24_OUTCFG98_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG24_OUTCFG98_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG24_OUTCFG98_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG24_OUTCFG98_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG24_OUTCFG98_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG24_OUTCFG98_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG24_OUTCFG98_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG24_OUTCFG98_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG24_OUTCFG98_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG24_OUTCFG98_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG24_OUTCFG98_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG24_OUTCFG98_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG24_OUTCFG98_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG24_OUTCFG98_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG24_OUTCFG98_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG24_OUTCFG98_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG24_OUTCFG98_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG24_OUTCFG98_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG24_OUTCFG98_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG24_OUTCFG98_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG24_OUTCFG98_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG24_OUTCFG98_Enum;

/* ============================================  TIMER OUTCFG24 OUTCFG97 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG24_OUTCFG97                                                   */
  TIMER_OUTCFG24_OUTCFG97_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG24_OUTCFG97_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG24_OUTCFG97_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG24_OUTCFG97_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG24_OUTCFG97_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG24_OUTCFG97_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG24_OUTCFG97_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG24_OUTCFG97_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG24_OUTCFG97_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG24_OUTCFG97_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG24_OUTCFG97_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG24_OUTCFG97_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG24_OUTCFG97_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG24_OUTCFG97_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG24_OUTCFG97_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG24_OUTCFG97_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG24_OUTCFG97_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG24_OUTCFG97_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG24_OUTCFG97_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG24_OUTCFG97_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG24_OUTCFG97_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG24_OUTCFG97_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG24_OUTCFG97_Enum;

/* ============================================  TIMER OUTCFG24 OUTCFG96 [0..5]  ============================================= */
typedef enum {                                  /*!< TIMER_OUTCFG24_OUTCFG96                                                   */
  TIMER_OUTCFG24_OUTCFG96_TIMER00      = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER01      = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER10      = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER11      = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER20      = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER21      = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER30      = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER31      = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER40      = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER41      = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER50      = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER51      = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER60      = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER61      = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER70      = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER71      = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER80      = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER81      = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER90      = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER91      = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG24_OUTCFG96_TIMER100     = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG24_OUTCFG96_TIMER101     = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG24_OUTCFG96_TIMER110     = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG24_OUTCFG96_TIMER111     = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG24_OUTCFG96_TIMER120     = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG24_OUTCFG96_TIMER121     = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG24_OUTCFG96_TIMER130     = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG24_OUTCFG96_TIMER131     = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG24_OUTCFG96_TIMER140     = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG24_OUTCFG96_TIMER141     = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG24_OUTCFG96_TIMER150     = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG24_OUTCFG96_TIMER151     = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG24_OUTCFG96_STIMER0      = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG24_OUTCFG96_STIMER1      = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG24_OUTCFG96_STIMER2      = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG24_OUTCFG96_STIMER3      = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG24_OUTCFG96_STIMER4      = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG24_OUTCFG96_STIMER5      = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG24_OUTCFG96_STIMER6      = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG24_OUTCFG96_STIMER7      = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG24_OUTCFG96_DISABLED     = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG24_OUTCFG96_Enum;

/* =======================================================  OUTCFG25  ======================================================== */
/* ===========================================  TIMER OUTCFG25 OUTCFG103 [24..29]  =========================================== */
typedef enum {                                  /*!< TIMER_OUTCFG25_OUTCFG103                                                  */
  TIMER_OUTCFG25_OUTCFG103_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG25_OUTCFG103_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG25_OUTCFG103_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG25_OUTCFG103_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG25_OUTCFG103_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG25_OUTCFG103_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG25_OUTCFG103_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG25_OUTCFG103_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG25_OUTCFG103_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG25_OUTCFG103_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG25_OUTCFG103_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG25_OUTCFG103_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG25_OUTCFG103_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG25_OUTCFG103_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG25_OUTCFG103_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG25_OUTCFG103_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG25_OUTCFG103_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG25_OUTCFG103_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG25_OUTCFG103_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG25_OUTCFG103_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG25_OUTCFG103_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG25_OUTCFG103_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG25_OUTCFG103_Enum;

/* ===========================================  TIMER OUTCFG25 OUTCFG102 [16..21]  =========================================== */
typedef enum {                                  /*!< TIMER_OUTCFG25_OUTCFG102                                                  */
  TIMER_OUTCFG25_OUTCFG102_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG25_OUTCFG102_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG25_OUTCFG102_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG25_OUTCFG102_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG25_OUTCFG102_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG25_OUTCFG102_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG25_OUTCFG102_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG25_OUTCFG102_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG25_OUTCFG102_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG25_OUTCFG102_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG25_OUTCFG102_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG25_OUTCFG102_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG25_OUTCFG102_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG25_OUTCFG102_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG25_OUTCFG102_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG25_OUTCFG102_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG25_OUTCFG102_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG25_OUTCFG102_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG25_OUTCFG102_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG25_OUTCFG102_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG25_OUTCFG102_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG25_OUTCFG102_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG25_OUTCFG102_Enum;

/* ===========================================  TIMER OUTCFG25 OUTCFG101 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG25_OUTCFG101                                                  */
  TIMER_OUTCFG25_OUTCFG101_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG25_OUTCFG101_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG25_OUTCFG101_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG25_OUTCFG101_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG25_OUTCFG101_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG25_OUTCFG101_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG25_OUTCFG101_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG25_OUTCFG101_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG25_OUTCFG101_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG25_OUTCFG101_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG25_OUTCFG101_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG25_OUTCFG101_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG25_OUTCFG101_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG25_OUTCFG101_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG25_OUTCFG101_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG25_OUTCFG101_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG25_OUTCFG101_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG25_OUTCFG101_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG25_OUTCFG101_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG25_OUTCFG101_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG25_OUTCFG101_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG25_OUTCFG101_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG25_OUTCFG101_Enum;

/* ============================================  TIMER OUTCFG25 OUTCFG100 [0..5]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG25_OUTCFG100                                                  */
  TIMER_OUTCFG25_OUTCFG100_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG25_OUTCFG100_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG25_OUTCFG100_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG25_OUTCFG100_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG25_OUTCFG100_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG25_OUTCFG100_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG25_OUTCFG100_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG25_OUTCFG100_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG25_OUTCFG100_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG25_OUTCFG100_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG25_OUTCFG100_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG25_OUTCFG100_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG25_OUTCFG100_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG25_OUTCFG100_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG25_OUTCFG100_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG25_OUTCFG100_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG25_OUTCFG100_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG25_OUTCFG100_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG25_OUTCFG100_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG25_OUTCFG100_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG25_OUTCFG100_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG25_OUTCFG100_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG25_OUTCFG100_Enum;

/* =======================================================  OUTCFG26  ======================================================== */
/* ===========================================  TIMER OUTCFG26 OUTCFG107 [24..29]  =========================================== */
typedef enum {                                  /*!< TIMER_OUTCFG26_OUTCFG107                                                  */
  TIMER_OUTCFG26_OUTCFG107_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG26_OUTCFG107_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG26_OUTCFG107_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG26_OUTCFG107_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG26_OUTCFG107_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG26_OUTCFG107_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG26_OUTCFG107_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG26_OUTCFG107_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG26_OUTCFG107_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG26_OUTCFG107_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG26_OUTCFG107_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG26_OUTCFG107_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG26_OUTCFG107_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG26_OUTCFG107_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG26_OUTCFG107_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG26_OUTCFG107_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG26_OUTCFG107_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG26_OUTCFG107_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG26_OUTCFG107_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG26_OUTCFG107_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG26_OUTCFG107_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG26_OUTCFG107_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG26_OUTCFG107_Enum;

/* ===========================================  TIMER OUTCFG26 OUTCFG106 [16..21]  =========================================== */
typedef enum {                                  /*!< TIMER_OUTCFG26_OUTCFG106                                                  */
  TIMER_OUTCFG26_OUTCFG106_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG26_OUTCFG106_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG26_OUTCFG106_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG26_OUTCFG106_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG26_OUTCFG106_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG26_OUTCFG106_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG26_OUTCFG106_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG26_OUTCFG106_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG26_OUTCFG106_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG26_OUTCFG106_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG26_OUTCFG106_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG26_OUTCFG106_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG26_OUTCFG106_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG26_OUTCFG106_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG26_OUTCFG106_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG26_OUTCFG106_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG26_OUTCFG106_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG26_OUTCFG106_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG26_OUTCFG106_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG26_OUTCFG106_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG26_OUTCFG106_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG26_OUTCFG106_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG26_OUTCFG106_Enum;

/* ===========================================  TIMER OUTCFG26 OUTCFG105 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG26_OUTCFG105                                                  */
  TIMER_OUTCFG26_OUTCFG105_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG26_OUTCFG105_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG26_OUTCFG105_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG26_OUTCFG105_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG26_OUTCFG105_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG26_OUTCFG105_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG26_OUTCFG105_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG26_OUTCFG105_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG26_OUTCFG105_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG26_OUTCFG105_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG26_OUTCFG105_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG26_OUTCFG105_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG26_OUTCFG105_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG26_OUTCFG105_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG26_OUTCFG105_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG26_OUTCFG105_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG26_OUTCFG105_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG26_OUTCFG105_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG26_OUTCFG105_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG26_OUTCFG105_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG26_OUTCFG105_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG26_OUTCFG105_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG26_OUTCFG105_Enum;

/* ============================================  TIMER OUTCFG26 OUTCFG104 [0..5]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG26_OUTCFG104                                                  */
  TIMER_OUTCFG26_OUTCFG104_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG26_OUTCFG104_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG26_OUTCFG104_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG26_OUTCFG104_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG26_OUTCFG104_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG26_OUTCFG104_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG26_OUTCFG104_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG26_OUTCFG104_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG26_OUTCFG104_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG26_OUTCFG104_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG26_OUTCFG104_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG26_OUTCFG104_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG26_OUTCFG104_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG26_OUTCFG104_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG26_OUTCFG104_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG26_OUTCFG104_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG26_OUTCFG104_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG26_OUTCFG104_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG26_OUTCFG104_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG26_OUTCFG104_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG26_OUTCFG104_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG26_OUTCFG104_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG26_OUTCFG104_Enum;

/* =======================================================  OUTCFG27  ======================================================== */
/* ===========================================  TIMER OUTCFG27 OUTCFG111 [24..29]  =========================================== */
typedef enum {                                  /*!< TIMER_OUTCFG27_OUTCFG111                                                  */
  TIMER_OUTCFG27_OUTCFG111_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG27_OUTCFG111_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG27_OUTCFG111_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG27_OUTCFG111_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG27_OUTCFG111_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG27_OUTCFG111_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG27_OUTCFG111_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG27_OUTCFG111_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG27_OUTCFG111_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG27_OUTCFG111_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG27_OUTCFG111_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG27_OUTCFG111_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG27_OUTCFG111_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG27_OUTCFG111_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG27_OUTCFG111_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG27_OUTCFG111_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG27_OUTCFG111_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG27_OUTCFG111_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG27_OUTCFG111_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG27_OUTCFG111_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG27_OUTCFG111_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG27_OUTCFG111_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG27_OUTCFG111_Enum;

/* ===========================================  TIMER OUTCFG27 OUTCFG110 [16..21]  =========================================== */
typedef enum {                                  /*!< TIMER_OUTCFG27_OUTCFG110                                                  */
  TIMER_OUTCFG27_OUTCFG110_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG27_OUTCFG110_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG27_OUTCFG110_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG27_OUTCFG110_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG27_OUTCFG110_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG27_OUTCFG110_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG27_OUTCFG110_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG27_OUTCFG110_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG27_OUTCFG110_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG27_OUTCFG110_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG27_OUTCFG110_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG27_OUTCFG110_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG27_OUTCFG110_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG27_OUTCFG110_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG27_OUTCFG110_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG27_OUTCFG110_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG27_OUTCFG110_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG27_OUTCFG110_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG27_OUTCFG110_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG27_OUTCFG110_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG27_OUTCFG110_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG27_OUTCFG110_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG27_OUTCFG110_Enum;

/* ===========================================  TIMER OUTCFG27 OUTCFG109 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG27_OUTCFG109                                                  */
  TIMER_OUTCFG27_OUTCFG109_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG27_OUTCFG109_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG27_OUTCFG109_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG27_OUTCFG109_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG27_OUTCFG109_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG27_OUTCFG109_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG27_OUTCFG109_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG27_OUTCFG109_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG27_OUTCFG109_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG27_OUTCFG109_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG27_OUTCFG109_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG27_OUTCFG109_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG27_OUTCFG109_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG27_OUTCFG109_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG27_OUTCFG109_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG27_OUTCFG109_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG27_OUTCFG109_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG27_OUTCFG109_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG27_OUTCFG109_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG27_OUTCFG109_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG27_OUTCFG109_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG27_OUTCFG109_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG27_OUTCFG109_Enum;

/* ============================================  TIMER OUTCFG27 OUTCFG108 [0..5]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG27_OUTCFG108                                                  */
  TIMER_OUTCFG27_OUTCFG108_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG27_OUTCFG108_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG27_OUTCFG108_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG27_OUTCFG108_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG27_OUTCFG108_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG27_OUTCFG108_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG27_OUTCFG108_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG27_OUTCFG108_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG27_OUTCFG108_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG27_OUTCFG108_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG27_OUTCFG108_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG27_OUTCFG108_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG27_OUTCFG108_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG27_OUTCFG108_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG27_OUTCFG108_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG27_OUTCFG108_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG27_OUTCFG108_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG27_OUTCFG108_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG27_OUTCFG108_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG27_OUTCFG108_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG27_OUTCFG108_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG27_OUTCFG108_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG27_OUTCFG108_Enum;

/* =======================================================  OUTCFG28  ======================================================== */
/* ===========================================  TIMER OUTCFG28 OUTCFG115 [24..29]  =========================================== */
typedef enum {                                  /*!< TIMER_OUTCFG28_OUTCFG115                                                  */
  TIMER_OUTCFG28_OUTCFG115_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG28_OUTCFG115_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG28_OUTCFG115_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG28_OUTCFG115_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG28_OUTCFG115_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG28_OUTCFG115_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG28_OUTCFG115_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG28_OUTCFG115_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG28_OUTCFG115_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG28_OUTCFG115_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG28_OUTCFG115_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG28_OUTCFG115_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG28_OUTCFG115_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG28_OUTCFG115_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG28_OUTCFG115_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG28_OUTCFG115_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG28_OUTCFG115_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG28_OUTCFG115_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG28_OUTCFG115_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG28_OUTCFG115_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG28_OUTCFG115_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG28_OUTCFG115_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG28_OUTCFG115_Enum;

/* ===========================================  TIMER OUTCFG28 OUTCFG114 [16..21]  =========================================== */
typedef enum {                                  /*!< TIMER_OUTCFG28_OUTCFG114                                                  */
  TIMER_OUTCFG28_OUTCFG114_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG28_OUTCFG114_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG28_OUTCFG114_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG28_OUTCFG114_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG28_OUTCFG114_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG28_OUTCFG114_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG28_OUTCFG114_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG28_OUTCFG114_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG28_OUTCFG114_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG28_OUTCFG114_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG28_OUTCFG114_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG28_OUTCFG114_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG28_OUTCFG114_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG28_OUTCFG114_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG28_OUTCFG114_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG28_OUTCFG114_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG28_OUTCFG114_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG28_OUTCFG114_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG28_OUTCFG114_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG28_OUTCFG114_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG28_OUTCFG114_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG28_OUTCFG114_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG28_OUTCFG114_Enum;

/* ===========================================  TIMER OUTCFG28 OUTCFG113 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG28_OUTCFG113                                                  */
  TIMER_OUTCFG28_OUTCFG113_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG28_OUTCFG113_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG28_OUTCFG113_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG28_OUTCFG113_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG28_OUTCFG113_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG28_OUTCFG113_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG28_OUTCFG113_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG28_OUTCFG113_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG28_OUTCFG113_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG28_OUTCFG113_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG28_OUTCFG113_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG28_OUTCFG113_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG28_OUTCFG113_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG28_OUTCFG113_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG28_OUTCFG113_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG28_OUTCFG113_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG28_OUTCFG113_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG28_OUTCFG113_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG28_OUTCFG113_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG28_OUTCFG113_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG28_OUTCFG113_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG28_OUTCFG113_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG28_OUTCFG113_Enum;

/* ============================================  TIMER OUTCFG28 OUTCFG112 [0..5]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG28_OUTCFG112                                                  */
  TIMER_OUTCFG28_OUTCFG112_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG28_OUTCFG112_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG28_OUTCFG112_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG28_OUTCFG112_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG28_OUTCFG112_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG28_OUTCFG112_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG28_OUTCFG112_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG28_OUTCFG112_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG28_OUTCFG112_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG28_OUTCFG112_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG28_OUTCFG112_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG28_OUTCFG112_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG28_OUTCFG112_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG28_OUTCFG112_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG28_OUTCFG112_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG28_OUTCFG112_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG28_OUTCFG112_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG28_OUTCFG112_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG28_OUTCFG112_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG28_OUTCFG112_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG28_OUTCFG112_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG28_OUTCFG112_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG28_OUTCFG112_Enum;

/* =======================================================  OUTCFG29  ======================================================== */
/* ===========================================  TIMER OUTCFG29 OUTCFG119 [24..29]  =========================================== */
typedef enum {                                  /*!< TIMER_OUTCFG29_OUTCFG119                                                  */
  TIMER_OUTCFG29_OUTCFG119_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG29_OUTCFG119_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG29_OUTCFG119_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG29_OUTCFG119_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG29_OUTCFG119_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG29_OUTCFG119_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG29_OUTCFG119_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG29_OUTCFG119_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG29_OUTCFG119_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG29_OUTCFG119_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG29_OUTCFG119_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG29_OUTCFG119_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG29_OUTCFG119_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG29_OUTCFG119_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG29_OUTCFG119_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG29_OUTCFG119_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG29_OUTCFG119_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG29_OUTCFG119_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG29_OUTCFG119_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG29_OUTCFG119_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG29_OUTCFG119_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG29_OUTCFG119_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG29_OUTCFG119_Enum;

/* ===========================================  TIMER OUTCFG29 OUTCFG118 [16..21]  =========================================== */
typedef enum {                                  /*!< TIMER_OUTCFG29_OUTCFG118                                                  */
  TIMER_OUTCFG29_OUTCFG118_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG29_OUTCFG118_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG29_OUTCFG118_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG29_OUTCFG118_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG29_OUTCFG118_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG29_OUTCFG118_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG29_OUTCFG118_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG29_OUTCFG118_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG29_OUTCFG118_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG29_OUTCFG118_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG29_OUTCFG118_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG29_OUTCFG118_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG29_OUTCFG118_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG29_OUTCFG118_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG29_OUTCFG118_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG29_OUTCFG118_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG29_OUTCFG118_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG29_OUTCFG118_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG29_OUTCFG118_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG29_OUTCFG118_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG29_OUTCFG118_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG29_OUTCFG118_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG29_OUTCFG118_Enum;

/* ===========================================  TIMER OUTCFG29 OUTCFG117 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG29_OUTCFG117                                                  */
  TIMER_OUTCFG29_OUTCFG117_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG29_OUTCFG117_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG29_OUTCFG117_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG29_OUTCFG117_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG29_OUTCFG117_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG29_OUTCFG117_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG29_OUTCFG117_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG29_OUTCFG117_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG29_OUTCFG117_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG29_OUTCFG117_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG29_OUTCFG117_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG29_OUTCFG117_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG29_OUTCFG117_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG29_OUTCFG117_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG29_OUTCFG117_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG29_OUTCFG117_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG29_OUTCFG117_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG29_OUTCFG117_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG29_OUTCFG117_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG29_OUTCFG117_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG29_OUTCFG117_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG29_OUTCFG117_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG29_OUTCFG117_Enum;

/* ============================================  TIMER OUTCFG29 OUTCFG116 [0..5]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG29_OUTCFG116                                                  */
  TIMER_OUTCFG29_OUTCFG116_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG29_OUTCFG116_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG29_OUTCFG116_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG29_OUTCFG116_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG29_OUTCFG116_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG29_OUTCFG116_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG29_OUTCFG116_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG29_OUTCFG116_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG29_OUTCFG116_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG29_OUTCFG116_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG29_OUTCFG116_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG29_OUTCFG116_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG29_OUTCFG116_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG29_OUTCFG116_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG29_OUTCFG116_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG29_OUTCFG116_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG29_OUTCFG116_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG29_OUTCFG116_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG29_OUTCFG116_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG29_OUTCFG116_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG29_OUTCFG116_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG29_OUTCFG116_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG29_OUTCFG116_Enum;

/* =======================================================  OUTCFG30  ======================================================== */
/* ===========================================  TIMER OUTCFG30 OUTCFG123 [24..29]  =========================================== */
typedef enum {                                  /*!< TIMER_OUTCFG30_OUTCFG123                                                  */
  TIMER_OUTCFG30_OUTCFG123_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG30_OUTCFG123_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG30_OUTCFG123_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG30_OUTCFG123_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG30_OUTCFG123_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG30_OUTCFG123_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG30_OUTCFG123_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG30_OUTCFG123_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG30_OUTCFG123_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG30_OUTCFG123_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG30_OUTCFG123_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG30_OUTCFG123_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG30_OUTCFG123_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG30_OUTCFG123_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG30_OUTCFG123_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG30_OUTCFG123_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG30_OUTCFG123_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG30_OUTCFG123_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG30_OUTCFG123_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG30_OUTCFG123_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG30_OUTCFG123_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG30_OUTCFG123_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG30_OUTCFG123_Enum;

/* ===========================================  TIMER OUTCFG30 OUTCFG122 [16..21]  =========================================== */
typedef enum {                                  /*!< TIMER_OUTCFG30_OUTCFG122                                                  */
  TIMER_OUTCFG30_OUTCFG122_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG30_OUTCFG122_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG30_OUTCFG122_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG30_OUTCFG122_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG30_OUTCFG122_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG30_OUTCFG122_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG30_OUTCFG122_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG30_OUTCFG122_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG30_OUTCFG122_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG30_OUTCFG122_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG30_OUTCFG122_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG30_OUTCFG122_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG30_OUTCFG122_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG30_OUTCFG122_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG30_OUTCFG122_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG30_OUTCFG122_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG30_OUTCFG122_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG30_OUTCFG122_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG30_OUTCFG122_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG30_OUTCFG122_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG30_OUTCFG122_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG30_OUTCFG122_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG30_OUTCFG122_Enum;

/* ===========================================  TIMER OUTCFG30 OUTCFG121 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG30_OUTCFG121                                                  */
  TIMER_OUTCFG30_OUTCFG121_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG30_OUTCFG121_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG30_OUTCFG121_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG30_OUTCFG121_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG30_OUTCFG121_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG30_OUTCFG121_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG30_OUTCFG121_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG30_OUTCFG121_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG30_OUTCFG121_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG30_OUTCFG121_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG30_OUTCFG121_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG30_OUTCFG121_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG30_OUTCFG121_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG30_OUTCFG121_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG30_OUTCFG121_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG30_OUTCFG121_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG30_OUTCFG121_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG30_OUTCFG121_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG30_OUTCFG121_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG30_OUTCFG121_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG30_OUTCFG121_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG30_OUTCFG121_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG30_OUTCFG121_Enum;

/* ============================================  TIMER OUTCFG30 OUTCFG120 [0..5]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG30_OUTCFG120                                                  */
  TIMER_OUTCFG30_OUTCFG120_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG30_OUTCFG120_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG30_OUTCFG120_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG30_OUTCFG120_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG30_OUTCFG120_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG30_OUTCFG120_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG30_OUTCFG120_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG30_OUTCFG120_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG30_OUTCFG120_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG30_OUTCFG120_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG30_OUTCFG120_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG30_OUTCFG120_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG30_OUTCFG120_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG30_OUTCFG120_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG30_OUTCFG120_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG30_OUTCFG120_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG30_OUTCFG120_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG30_OUTCFG120_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG30_OUTCFG120_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG30_OUTCFG120_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG30_OUTCFG120_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG30_OUTCFG120_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG30_OUTCFG120_Enum;

/* =======================================================  OUTCFG31  ======================================================== */
/* ===========================================  TIMER OUTCFG31 OUTCFG127 [24..29]  =========================================== */
typedef enum {                                  /*!< TIMER_OUTCFG31_OUTCFG127                                                  */
  TIMER_OUTCFG31_OUTCFG127_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG31_OUTCFG127_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG31_OUTCFG127_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG31_OUTCFG127_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG31_OUTCFG127_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG31_OUTCFG127_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG31_OUTCFG127_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG31_OUTCFG127_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG31_OUTCFG127_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG31_OUTCFG127_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG31_OUTCFG127_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG31_OUTCFG127_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG31_OUTCFG127_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG31_OUTCFG127_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG31_OUTCFG127_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG31_OUTCFG127_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG31_OUTCFG127_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG31_OUTCFG127_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG31_OUTCFG127_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG31_OUTCFG127_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG31_OUTCFG127_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG31_OUTCFG127_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG31_OUTCFG127_Enum;

/* ===========================================  TIMER OUTCFG31 OUTCFG126 [16..21]  =========================================== */
typedef enum {                                  /*!< TIMER_OUTCFG31_OUTCFG126                                                  */
  TIMER_OUTCFG31_OUTCFG126_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG31_OUTCFG126_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG31_OUTCFG126_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG31_OUTCFG126_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG31_OUTCFG126_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG31_OUTCFG126_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG31_OUTCFG126_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG31_OUTCFG126_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG31_OUTCFG126_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG31_OUTCFG126_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG31_OUTCFG126_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG31_OUTCFG126_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG31_OUTCFG126_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG31_OUTCFG126_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG31_OUTCFG126_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG31_OUTCFG126_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG31_OUTCFG126_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG31_OUTCFG126_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG31_OUTCFG126_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG31_OUTCFG126_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG31_OUTCFG126_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG31_OUTCFG126_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG31_OUTCFG126_Enum;

/* ===========================================  TIMER OUTCFG31 OUTCFG125 [8..13]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG31_OUTCFG125                                                  */
  TIMER_OUTCFG31_OUTCFG125_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG31_OUTCFG125_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG31_OUTCFG125_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG31_OUTCFG125_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG31_OUTCFG125_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG31_OUTCFG125_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG31_OUTCFG125_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG31_OUTCFG125_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG31_OUTCFG125_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG31_OUTCFG125_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG31_OUTCFG125_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG31_OUTCFG125_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG31_OUTCFG125_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG31_OUTCFG125_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG31_OUTCFG125_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG31_OUTCFG125_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG31_OUTCFG125_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG31_OUTCFG125_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG31_OUTCFG125_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG31_OUTCFG125_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG31_OUTCFG125_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG31_OUTCFG125_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG31_OUTCFG125_Enum;

/* ============================================  TIMER OUTCFG31 OUTCFG124 [0..5]  ============================================ */
typedef enum {                                  /*!< TIMER_OUTCFG31_OUTCFG124                                                  */
  TIMER_OUTCFG31_OUTCFG124_TIMER00     = 0,     /*!< TIMER00 : Output is Timer 0, output 0                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER01     = 1,     /*!< TIMER01 : Output is Timer 0, output 1                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER10     = 2,     /*!< TIMER10 : Output is Timer 1, output 0                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER11     = 3,     /*!< TIMER11 : Output is Timer 1, output 1                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER20     = 4,     /*!< TIMER20 : Output is Timer 2, output 0                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER21     = 5,     /*!< TIMER21 : Output is Timer 2, output 1                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER30     = 6,     /*!< TIMER30 : Output is Timer 3, output 0                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER31     = 7,     /*!< TIMER31 : Output is Timer 3, output 1                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER40     = 8,     /*!< TIMER40 : Output is Timer 4, output 0                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER41     = 9,     /*!< TIMER41 : Output is Timer 4, output 1                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER50     = 10,    /*!< TIMER50 : Output is Timer 5, output 0                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER51     = 11,    /*!< TIMER51 : Output is Timer 5, output 1                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER60     = 12,    /*!< TIMER60 : Output is Timer 6, output 0                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER61     = 13,    /*!< TIMER61 : Output is Timer 6, output 1                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER70     = 14,    /*!< TIMER70 : Output is Timer 7, output 0                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER71     = 15,    /*!< TIMER71 : Output is Timer 7, output 1                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER80     = 16,    /*!< TIMER80 : Output is Timer 8, output 0                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER81     = 17,    /*!< TIMER81 : Output is Timer 8, output 1                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER90     = 18,    /*!< TIMER90 : Output is Timer 9, output 0                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER91     = 19,    /*!< TIMER91 : Output is Timer 9, output 1                                     */
  TIMER_OUTCFG31_OUTCFG124_TIMER100    = 20,    /*!< TIMER100 : Output is Timer 10, output 0                                   */
  TIMER_OUTCFG31_OUTCFG124_TIMER101    = 21,    /*!< TIMER101 : Output is Timer 10, output 1                                   */
  TIMER_OUTCFG31_OUTCFG124_TIMER110    = 22,    /*!< TIMER110 : Output is Timer 11, output 0                                   */
  TIMER_OUTCFG31_OUTCFG124_TIMER111    = 23,    /*!< TIMER111 : Output is Timer 11, output 1                                   */
  TIMER_OUTCFG31_OUTCFG124_TIMER120    = 24,    /*!< TIMER120 : Output is Timer 12, output 0                                   */
  TIMER_OUTCFG31_OUTCFG124_TIMER121    = 25,    /*!< TIMER121 : Output is Timer 12, output 1                                   */
  TIMER_OUTCFG31_OUTCFG124_TIMER130    = 26,    /*!< TIMER130 : Output is Timer 13, output 0                                   */
  TIMER_OUTCFG31_OUTCFG124_TIMER131    = 27,    /*!< TIMER131 : Output is Timer 13, output 1                                   */
  TIMER_OUTCFG31_OUTCFG124_TIMER140    = 28,    /*!< TIMER140 : Output is Timer 14, output 0                                   */
  TIMER_OUTCFG31_OUTCFG124_TIMER141    = 29,    /*!< TIMER141 : Output is Timer 14, output 1                                   */
  TIMER_OUTCFG31_OUTCFG124_TIMER150    = 30,    /*!< TIMER150 : Output is Timer 15, output 0                                   */
  TIMER_OUTCFG31_OUTCFG124_TIMER151    = 31,    /*!< TIMER151 : Output is Timer 15, output 1                                   */
  TIMER_OUTCFG31_OUTCFG124_STIMER0     = 32,    /*!< STIMER0 : Output is STimer 0                                              */
  TIMER_OUTCFG31_OUTCFG124_STIMER1     = 33,    /*!< STIMER1 : Output is STimer 1                                              */
  TIMER_OUTCFG31_OUTCFG124_STIMER2     = 34,    /*!< STIMER2 : Output is STimer 2                                              */
  TIMER_OUTCFG31_OUTCFG124_STIMER3     = 35,    /*!< STIMER3 : Output is STimer 3                                              */
  TIMER_OUTCFG31_OUTCFG124_STIMER4     = 36,    /*!< STIMER4 : Output is STimer 4                                              */
  TIMER_OUTCFG31_OUTCFG124_STIMER5     = 37,    /*!< STIMER5 : Output is STimer 5                                              */
  TIMER_OUTCFG31_OUTCFG124_STIMER6     = 38,    /*!< STIMER6 : Output is STimer 6                                              */
  TIMER_OUTCFG31_OUTCFG124_STIMER7     = 39,    /*!< STIMER7 : Output is STimer 7                                              */
  TIMER_OUTCFG31_OUTCFG124_DISABLED    = 63,    /*!< DISABLED : Output is disabled                                             */
} TIMER_OUTCFG31_OUTCFG124_Enum;

/* =========================================================  CTRL0  ========================================================= */
/* ============================================  TIMER CTRL0 TMR0TMODE [16..17]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL0_TMR0TMODE                                                     */
  TIMER_CTRL0_TMR0TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
  TIMER_CTRL0_TMR0TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
  TIMER_CTRL0_TMR0TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
  TIMER_CTRL0_TMR0TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
} TIMER_CTRL0_TMR0TMODE_Enum;

/* ==============================================  TIMER CTRL0 TMR0CLK [8..15]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL0_TMR0CLK                                                       */
  TIMER_CTRL0_TMR0CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
  TIMER_CTRL0_TMR0CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
  TIMER_CTRL0_TMR0CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
  TIMER_CTRL0_TMR0CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
  TIMER_CTRL0_TMR0CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
  TIMER_CTRL0_TMR0CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
  TIMER_CTRL0_TMR0CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
  TIMER_CTRL0_TMR0CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
  TIMER_CTRL0_TMR0CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
  TIMER_CTRL0_TMR0CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
  TIMER_CTRL0_TMR0CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
  TIMER_CTRL0_TMR0CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
  TIMER_CTRL0_TMR0CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
  TIMER_CTRL0_TMR0CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
  TIMER_CTRL0_TMR0CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
  TIMER_CTRL0_TMR0CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
  TIMER_CTRL0_TMR0CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
  TIMER_CTRL0_TMR0CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
  TIMER_CTRL0_TMR0CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
  TIMER_CTRL0_TMR0CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
  TIMER_CTRL0_TMR0CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
  TIMER_CTRL0_TMR0CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
  TIMER_CTRL0_TMR0CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
  TIMER_CTRL0_TMR0CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
  TIMER_CTRL0_TMR0CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
  TIMER_CTRL0_TMR0CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
  TIMER_CTRL0_TMR0CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
  TIMER_CTRL0_TMR0CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
  TIMER_CTRL0_TMR0CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
  TIMER_CTRL0_TMR0CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
  TIMER_CTRL0_TMR0CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
  TIMER_CTRL0_TMR0CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
  TIMER_CTRL0_TMR0CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
  TIMER_CTRL0_TMR0CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
  TIMER_CTRL0_TMR0CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
  TIMER_CTRL0_TMR0CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
  TIMER_CTRL0_TMR0CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
  TIMER_CTRL0_TMR0CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
  TIMER_CTRL0_TMR0CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
  TIMER_CTRL0_TMR0CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
  TIMER_CTRL0_TMR0CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
  TIMER_CTRL0_TMR0CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
  TIMER_CTRL0_TMR0CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
  TIMER_CTRL0_TMR0CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
  TIMER_CTRL0_TMR0CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
  TIMER_CTRL0_TMR0CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
  TIMER_CTRL0_TMR0CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
  TIMER_CTRL0_TMR0CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
  TIMER_CTRL0_TMR0CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
  TIMER_CTRL0_TMR0CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
  TIMER_CTRL0_TMR0CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
  TIMER_CTRL0_TMR0CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
  TIMER_CTRL0_TMR0CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
  TIMER_CTRL0_TMR0CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
  TIMER_CTRL0_TMR0CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
  TIMER_CTRL0_TMR0CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
  TIMER_CTRL0_TMR0CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
  TIMER_CTRL0_TMR0CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
} TIMER_CTRL0_TMR0CLK_Enum;

/* ===============================================  TIMER CTRL0 TMR0FN [4..7]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL0_TMR0FN                                                        */
  TIMER_CTRL0_TMR0FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
                                                     value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
                                                     to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
  TIMER_CTRL0_TMR0FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
                                                     CMP. OUT[0]/OUT[1] is pulsed for one source clock period
                                                     when TIMER matches CMP0/CMP1 respectively. Timer repeats
                                                     for TMR_LMT iterations.                                                   */
  TIMER_CTRL0_TMR0FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
                                                     clock pulse. CMP1 dictates the low phase of the output
                                                     and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
  TIMER_CTRL0_TMR0FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
                                                     LMT field specifies length of pattern. When LMT GT 32 OUT0
                                                     and OUT1 is the same 64-bit pattern consisting of concatenated
                                                     CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
                                                     Both OUT0 and OUT1 can be inverted individually applications
                                                     with POL0/POL1 = 0x1.                                                     */
  TIMER_CTRL0_TMR0FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
                                                     pattern repeats after reaching LMT.                                       */
} TIMER_CTRL0_TMR0FN_Enum;

/* ==============================================  TIMER CTRL0 TMR0POL1 [3..3]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL0_TMR0POL1                                                      */
  TIMER_CTRL0_TMR0POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR0OUT1 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL0_TMR0POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR0OUT1 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL0_TMR0POL1_Enum;

/* ==============================================  TIMER CTRL0 TMR0POL0 [2..2]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL0_TMR0POL0                                                      */
  TIMER_CTRL0_TMR0POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR0OUT0 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL0_TMR0POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR0OUT0 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL0_TMR0POL0_Enum;

/* ==============================================  TIMER CTRL0 TMR0CLR [1..1]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL0_TMR0CLR                                                       */
  TIMER_CTRL0_TMR0CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
                                                     cleared to its reset state # (0 for count up counter, CMP0
                                                     for down counter)                                                         */
  TIMER_CTRL0_TMR0CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
} TIMER_CTRL0_TMR0CLR_Enum;

/* ===============================================  TIMER CTRL0 TMR0EN [0..0]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL0_TMR0EN                                                        */
  TIMER_CTRL0_TMR0EN_DIS               = 0,     /*!< DIS : Counter/Timer 0 Disable.                                            */
  TIMER_CTRL0_TMR0EN_EN                = 1,     /*!< EN : Counter/Timer 0 Enable.                                              */
} TIMER_CTRL0_TMR0EN_Enum;

/* ========================================================  TIMER0  ========================================================= */
/* =======================================================  TMR0CMP0  ======================================================== */
/* =======================================================  TMR0CMP1  ======================================================== */
/* =========================================================  MODE0  ========================================================= */
/* ============================================  TIMER MODE0 TMR0TRIGSEL [8..15]  ============================================ */
typedef enum {                                  /*!< TIMER_MODE0_TMR0TRIGSEL                                                   */
  TIMER_MODE0_TMR0TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
  TIMER_MODE0_TMR0TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
  TIMER_MODE0_TMR0TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
  TIMER_MODE0_TMR0TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
  TIMER_MODE0_TMR0TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
  TIMER_MODE0_TMR0TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
  TIMER_MODE0_TMR0TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
  TIMER_MODE0_TMR0TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
  TIMER_MODE0_TMR0TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
  TIMER_MODE0_TMR0TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
  TIMER_MODE0_TMR0TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
  TIMER_MODE0_TMR0TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
  TIMER_MODE0_TMR0TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
  TIMER_MODE0_TMR0TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
  TIMER_MODE0_TMR0TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
} TIMER_MODE0_TMR0TRIGSEL_Enum;

/* ======================================================  TMR0LMTVAL  ======================================================= */
/* =========================================================  CTRL1  ========================================================= */
/* ============================================  TIMER CTRL1 TMR1TMODE [16..17]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL1_TMR1TMODE                                                     */
  TIMER_CTRL1_TMR1TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
  TIMER_CTRL1_TMR1TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
  TIMER_CTRL1_TMR1TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
  TIMER_CTRL1_TMR1TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
} TIMER_CTRL1_TMR1TMODE_Enum;

/* ==============================================  TIMER CTRL1 TMR1CLK [8..15]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL1_TMR1CLK                                                       */
  TIMER_CTRL1_TMR1CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
  TIMER_CTRL1_TMR1CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
  TIMER_CTRL1_TMR1CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
  TIMER_CTRL1_TMR1CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
  TIMER_CTRL1_TMR1CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
  TIMER_CTRL1_TMR1CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
  TIMER_CTRL1_TMR1CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
  TIMER_CTRL1_TMR1CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
  TIMER_CTRL1_TMR1CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
  TIMER_CTRL1_TMR1CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
  TIMER_CTRL1_TMR1CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
  TIMER_CTRL1_TMR1CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
  TIMER_CTRL1_TMR1CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
  TIMER_CTRL1_TMR1CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
  TIMER_CTRL1_TMR1CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
  TIMER_CTRL1_TMR1CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
  TIMER_CTRL1_TMR1CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
  TIMER_CTRL1_TMR1CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
  TIMER_CTRL1_TMR1CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
  TIMER_CTRL1_TMR1CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
  TIMER_CTRL1_TMR1CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
  TIMER_CTRL1_TMR1CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
  TIMER_CTRL1_TMR1CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
  TIMER_CTRL1_TMR1CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
  TIMER_CTRL1_TMR1CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
  TIMER_CTRL1_TMR1CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
  TIMER_CTRL1_TMR1CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
  TIMER_CTRL1_TMR1CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
  TIMER_CTRL1_TMR1CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
  TIMER_CTRL1_TMR1CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
  TIMER_CTRL1_TMR1CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
  TIMER_CTRL1_TMR1CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
  TIMER_CTRL1_TMR1CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
  TIMER_CTRL1_TMR1CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
  TIMER_CTRL1_TMR1CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
  TIMER_CTRL1_TMR1CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
  TIMER_CTRL1_TMR1CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
  TIMER_CTRL1_TMR1CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
  TIMER_CTRL1_TMR1CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
  TIMER_CTRL1_TMR1CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
  TIMER_CTRL1_TMR1CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
  TIMER_CTRL1_TMR1CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
  TIMER_CTRL1_TMR1CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
  TIMER_CTRL1_TMR1CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
  TIMER_CTRL1_TMR1CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
  TIMER_CTRL1_TMR1CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
  TIMER_CTRL1_TMR1CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
  TIMER_CTRL1_TMR1CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
  TIMER_CTRL1_TMR1CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
  TIMER_CTRL1_TMR1CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
  TIMER_CTRL1_TMR1CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
  TIMER_CTRL1_TMR1CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
  TIMER_CTRL1_TMR1CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
  TIMER_CTRL1_TMR1CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
  TIMER_CTRL1_TMR1CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
  TIMER_CTRL1_TMR1CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
  TIMER_CTRL1_TMR1CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
  TIMER_CTRL1_TMR1CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
} TIMER_CTRL1_TMR1CLK_Enum;

/* ===============================================  TIMER CTRL1 TMR1FN [4..7]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL1_TMR1FN                                                        */
  TIMER_CTRL1_TMR1FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
                                                     value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
                                                     to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
  TIMER_CTRL1_TMR1FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
                                                     CMP. OUT[0]/OUT[1] is pulsed for one source clock period
                                                     when TIMER matches CMP0/CMP1 respectively. Timer repeats
                                                     for TMR_LMT iterations.                                                   */
  TIMER_CTRL1_TMR1FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
                                                     clock pulse. CMP1 dictates the low phase of the output
                                                     and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
  TIMER_CTRL1_TMR1FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
                                                     LMT field specifies length of pattern. When LMT GT 32 OUT0
                                                     and OUT1 is the same 64-bit pattern consisting of concatenated
                                                     CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
                                                     Both OUT0 and OUT1 can be inverted individually applications
                                                     with POL0/POL1 = 0x1.                                                     */
  TIMER_CTRL1_TMR1FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
                                                     pattern repeats after reaching LMT.                                       */
} TIMER_CTRL1_TMR1FN_Enum;

/* ==============================================  TIMER CTRL1 TMR1POL1 [3..3]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL1_TMR1POL1                                                      */
  TIMER_CTRL1_TMR1POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR1OUT1 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL1_TMR1POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR1OUT1 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL1_TMR1POL1_Enum;

/* ==============================================  TIMER CTRL1 TMR1POL0 [2..2]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL1_TMR1POL0                                                      */
  TIMER_CTRL1_TMR1POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR1OUT0 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL1_TMR1POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR1OUT0 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL1_TMR1POL0_Enum;

/* ==============================================  TIMER CTRL1 TMR1CLR [1..1]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL1_TMR1CLR                                                       */
  TIMER_CTRL1_TMR1CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
                                                     cleared to its reset state # (0 for count up counter, CMP0
                                                     for down counter)                                                         */
  TIMER_CTRL1_TMR1CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
} TIMER_CTRL1_TMR1CLR_Enum;

/* ===============================================  TIMER CTRL1 TMR1EN [0..0]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL1_TMR1EN                                                        */
  TIMER_CTRL1_TMR1EN_DIS               = 0,     /*!< DIS : Counter/Timer 1 Disable.                                            */
  TIMER_CTRL1_TMR1EN_EN                = 1,     /*!< EN : Counter/Timer 1 Enable.                                              */
} TIMER_CTRL1_TMR1EN_Enum;

/* ========================================================  TIMER1  ========================================================= */
/* =======================================================  TMR1CMP0  ======================================================== */
/* =======================================================  TMR1CMP1  ======================================================== */
/* =========================================================  MODE1  ========================================================= */
/* ============================================  TIMER MODE1 TMR1TRIGSEL [8..15]  ============================================ */
typedef enum {                                  /*!< TIMER_MODE1_TMR1TRIGSEL                                                   */
  TIMER_MODE1_TMR1TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
  TIMER_MODE1_TMR1TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
  TIMER_MODE1_TMR1TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
  TIMER_MODE1_TMR1TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
  TIMER_MODE1_TMR1TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
  TIMER_MODE1_TMR1TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
  TIMER_MODE1_TMR1TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
  TIMER_MODE1_TMR1TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
  TIMER_MODE1_TMR1TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
  TIMER_MODE1_TMR1TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
  TIMER_MODE1_TMR1TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
  TIMER_MODE1_TMR1TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
  TIMER_MODE1_TMR1TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
  TIMER_MODE1_TMR1TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
  TIMER_MODE1_TMR1TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
} TIMER_MODE1_TMR1TRIGSEL_Enum;

/* ======================================================  TMR1LMTVAL  ======================================================= */
/* =========================================================  CTRL2  ========================================================= */
/* ============================================  TIMER CTRL2 TMR2TMODE [16..17]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL2_TMR2TMODE                                                     */
  TIMER_CTRL2_TMR2TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
  TIMER_CTRL2_TMR2TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
  TIMER_CTRL2_TMR2TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
  TIMER_CTRL2_TMR2TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
} TIMER_CTRL2_TMR2TMODE_Enum;

/* ==============================================  TIMER CTRL2 TMR2CLK [8..15]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL2_TMR2CLK                                                       */
  TIMER_CTRL2_TMR2CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
  TIMER_CTRL2_TMR2CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
  TIMER_CTRL2_TMR2CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
  TIMER_CTRL2_TMR2CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
  TIMER_CTRL2_TMR2CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
  TIMER_CTRL2_TMR2CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
  TIMER_CTRL2_TMR2CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
  TIMER_CTRL2_TMR2CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
  TIMER_CTRL2_TMR2CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
  TIMER_CTRL2_TMR2CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
  TIMER_CTRL2_TMR2CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
  TIMER_CTRL2_TMR2CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
  TIMER_CTRL2_TMR2CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
  TIMER_CTRL2_TMR2CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
  TIMER_CTRL2_TMR2CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
  TIMER_CTRL2_TMR2CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
  TIMER_CTRL2_TMR2CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
  TIMER_CTRL2_TMR2CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
  TIMER_CTRL2_TMR2CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
  TIMER_CTRL2_TMR2CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
  TIMER_CTRL2_TMR2CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
  TIMER_CTRL2_TMR2CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
  TIMER_CTRL2_TMR2CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
  TIMER_CTRL2_TMR2CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
  TIMER_CTRL2_TMR2CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
  TIMER_CTRL2_TMR2CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
  TIMER_CTRL2_TMR2CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
  TIMER_CTRL2_TMR2CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
  TIMER_CTRL2_TMR2CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
  TIMER_CTRL2_TMR2CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
  TIMER_CTRL2_TMR2CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
  TIMER_CTRL2_TMR2CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
  TIMER_CTRL2_TMR2CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
  TIMER_CTRL2_TMR2CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
  TIMER_CTRL2_TMR2CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
  TIMER_CTRL2_TMR2CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
  TIMER_CTRL2_TMR2CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
  TIMER_CTRL2_TMR2CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
  TIMER_CTRL2_TMR2CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
  TIMER_CTRL2_TMR2CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
  TIMER_CTRL2_TMR2CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
  TIMER_CTRL2_TMR2CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
  TIMER_CTRL2_TMR2CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
  TIMER_CTRL2_TMR2CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
  TIMER_CTRL2_TMR2CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
  TIMER_CTRL2_TMR2CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
  TIMER_CTRL2_TMR2CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
  TIMER_CTRL2_TMR2CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
  TIMER_CTRL2_TMR2CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
  TIMER_CTRL2_TMR2CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
  TIMER_CTRL2_TMR2CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
  TIMER_CTRL2_TMR2CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
  TIMER_CTRL2_TMR2CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
  TIMER_CTRL2_TMR2CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
  TIMER_CTRL2_TMR2CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
  TIMER_CTRL2_TMR2CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
  TIMER_CTRL2_TMR2CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
  TIMER_CTRL2_TMR2CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
} TIMER_CTRL2_TMR2CLK_Enum;

/* ===============================================  TIMER CTRL2 TMR2FN [4..7]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL2_TMR2FN                                                        */
  TIMER_CTRL2_TMR2FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
                                                     value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
                                                     to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
  TIMER_CTRL2_TMR2FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
                                                     CMP. OUT[0]/OUT[1] is pulsed for one source clock period
                                                     when TIMER matches CMP0/CMP1 respectively. Timer repeats
                                                     for TMR_LMT iterations.                                                   */
  TIMER_CTRL2_TMR2FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
                                                     clock pulse. CMP1 dictates the low phase of the output
                                                     and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
  TIMER_CTRL2_TMR2FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
                                                     LMT field specifies length of pattern. When LMT GT 32 OUT0
                                                     and OUT1 is the same 64-bit pattern consisting of concatenated
                                                     CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
                                                     Both OUT0 and OUT1 can be inverted individually applications
                                                     with POL0/POL1 = 0x1.                                                     */
  TIMER_CTRL2_TMR2FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
                                                     pattern repeats after reaching LMT.                                       */
} TIMER_CTRL2_TMR2FN_Enum;

/* ==============================================  TIMER CTRL2 TMR2POL1 [3..3]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL2_TMR2POL1                                                      */
  TIMER_CTRL2_TMR2POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR2OUT1 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL2_TMR2POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR2OUT1 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL2_TMR2POL1_Enum;

/* ==============================================  TIMER CTRL2 TMR2POL0 [2..2]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL2_TMR2POL0                                                      */
  TIMER_CTRL2_TMR2POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR2OUT0 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL2_TMR2POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR2OUT0 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL2_TMR2POL0_Enum;

/* ==============================================  TIMER CTRL2 TMR2CLR [1..1]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL2_TMR2CLR                                                       */
  TIMER_CTRL2_TMR2CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
                                                     cleared to its reset state # (0 for count up counter, CMP0
                                                     for down counter)                                                         */
  TIMER_CTRL2_TMR2CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
} TIMER_CTRL2_TMR2CLR_Enum;

/* ===============================================  TIMER CTRL2 TMR2EN [0..0]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL2_TMR2EN                                                        */
  TIMER_CTRL2_TMR2EN_DIS               = 0,     /*!< DIS : Counter/Timer 2 Disable.                                            */
  TIMER_CTRL2_TMR2EN_EN                = 1,     /*!< EN : Counter/Timer 2 Enable.                                              */
} TIMER_CTRL2_TMR2EN_Enum;

/* ========================================================  TIMER2  ========================================================= */
/* =======================================================  TMR2CMP0  ======================================================== */
/* =======================================================  TMR2CMP1  ======================================================== */
/* =========================================================  MODE2  ========================================================= */
/* ============================================  TIMER MODE2 TMR2TRIGSEL [8..15]  ============================================ */
typedef enum {                                  /*!< TIMER_MODE2_TMR2TRIGSEL                                                   */
  TIMER_MODE2_TMR2TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
  TIMER_MODE2_TMR2TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
  TIMER_MODE2_TMR2TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
  TIMER_MODE2_TMR2TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
  TIMER_MODE2_TMR2TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
  TIMER_MODE2_TMR2TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
  TIMER_MODE2_TMR2TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
  TIMER_MODE2_TMR2TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
  TIMER_MODE2_TMR2TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
  TIMER_MODE2_TMR2TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
  TIMER_MODE2_TMR2TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
  TIMER_MODE2_TMR2TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
  TIMER_MODE2_TMR2TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
  TIMER_MODE2_TMR2TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
  TIMER_MODE2_TMR2TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
} TIMER_MODE2_TMR2TRIGSEL_Enum;

/* ======================================================  TMR2LMTVAL  ======================================================= */
/* =========================================================  CTRL3  ========================================================= */
/* ============================================  TIMER CTRL3 TMR3TMODE [16..17]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL3_TMR3TMODE                                                     */
  TIMER_CTRL3_TMR3TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
  TIMER_CTRL3_TMR3TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
  TIMER_CTRL3_TMR3TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
  TIMER_CTRL3_TMR3TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
} TIMER_CTRL3_TMR3TMODE_Enum;

/* ==============================================  TIMER CTRL3 TMR3CLK [8..15]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL3_TMR3CLK                                                       */
  TIMER_CTRL3_TMR3CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
  TIMER_CTRL3_TMR3CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
  TIMER_CTRL3_TMR3CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
  TIMER_CTRL3_TMR3CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
  TIMER_CTRL3_TMR3CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
  TIMER_CTRL3_TMR3CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
  TIMER_CTRL3_TMR3CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
  TIMER_CTRL3_TMR3CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
  TIMER_CTRL3_TMR3CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
  TIMER_CTRL3_TMR3CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
  TIMER_CTRL3_TMR3CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
  TIMER_CTRL3_TMR3CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
  TIMER_CTRL3_TMR3CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
  TIMER_CTRL3_TMR3CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
  TIMER_CTRL3_TMR3CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
  TIMER_CTRL3_TMR3CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
  TIMER_CTRL3_TMR3CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
  TIMER_CTRL3_TMR3CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
  TIMER_CTRL3_TMR3CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
  TIMER_CTRL3_TMR3CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
  TIMER_CTRL3_TMR3CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
  TIMER_CTRL3_TMR3CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
  TIMER_CTRL3_TMR3CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
  TIMER_CTRL3_TMR3CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
  TIMER_CTRL3_TMR3CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
  TIMER_CTRL3_TMR3CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
  TIMER_CTRL3_TMR3CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
  TIMER_CTRL3_TMR3CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
  TIMER_CTRL3_TMR3CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
  TIMER_CTRL3_TMR3CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
  TIMER_CTRL3_TMR3CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
  TIMER_CTRL3_TMR3CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
  TIMER_CTRL3_TMR3CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
  TIMER_CTRL3_TMR3CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
  TIMER_CTRL3_TMR3CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
  TIMER_CTRL3_TMR3CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
  TIMER_CTRL3_TMR3CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
  TIMER_CTRL3_TMR3CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
  TIMER_CTRL3_TMR3CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
  TIMER_CTRL3_TMR3CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
  TIMER_CTRL3_TMR3CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
  TIMER_CTRL3_TMR3CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
  TIMER_CTRL3_TMR3CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
  TIMER_CTRL3_TMR3CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
  TIMER_CTRL3_TMR3CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
  TIMER_CTRL3_TMR3CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
  TIMER_CTRL3_TMR3CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
  TIMER_CTRL3_TMR3CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
  TIMER_CTRL3_TMR3CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
  TIMER_CTRL3_TMR3CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
  TIMER_CTRL3_TMR3CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
  TIMER_CTRL3_TMR3CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
  TIMER_CTRL3_TMR3CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
  TIMER_CTRL3_TMR3CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
  TIMER_CTRL3_TMR3CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
  TIMER_CTRL3_TMR3CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
  TIMER_CTRL3_TMR3CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
  TIMER_CTRL3_TMR3CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
} TIMER_CTRL3_TMR3CLK_Enum;

/* ===============================================  TIMER CTRL3 TMR3FN [4..7]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL3_TMR3FN                                                        */
  TIMER_CTRL3_TMR3FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
                                                     value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
                                                     to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
  TIMER_CTRL3_TMR3FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
                                                     CMP. OUT[0]/OUT[1] is pulsed for one source clock period
                                                     when TIMER matches CMP0/CMP1 respectively. Timer repeats
                                                     for TMR_LMT iterations.                                                   */
  TIMER_CTRL3_TMR3FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
                                                     clock pulse. CMP1 dictates the low phase of the output
                                                     and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
  TIMER_CTRL3_TMR3FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
                                                     LMT field specifies length of pattern. When LMT GT 32 OUT0
                                                     and OUT1 is the same 64-bit pattern consisting of concatenated
                                                     CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
                                                     Both OUT0 and OUT1 can be inverted individually applications
                                                     with POL0/POL1 = 0x1.                                                     */
  TIMER_CTRL3_TMR3FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
                                                     pattern repeats after reaching LMT.                                       */
} TIMER_CTRL3_TMR3FN_Enum;

/* ==============================================  TIMER CTRL3 TMR3POL1 [3..3]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL3_TMR3POL1                                                      */
  TIMER_CTRL3_TMR3POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR3OUT1 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL3_TMR3POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR3OUT1 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL3_TMR3POL1_Enum;

/* ==============================================  TIMER CTRL3 TMR3POL0 [2..2]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL3_TMR3POL0                                                      */
  TIMER_CTRL3_TMR3POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR3OUT0 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL3_TMR3POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR3OUT0 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL3_TMR3POL0_Enum;

/* ==============================================  TIMER CTRL3 TMR3CLR [1..1]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL3_TMR3CLR                                                       */
  TIMER_CTRL3_TMR3CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
                                                     cleared to its reset state # (0 for count up counter, CMP0
                                                     for down counter)                                                         */
  TIMER_CTRL3_TMR3CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
} TIMER_CTRL3_TMR3CLR_Enum;

/* ===============================================  TIMER CTRL3 TMR3EN [0..0]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL3_TMR3EN                                                        */
  TIMER_CTRL3_TMR3EN_DIS               = 0,     /*!< DIS : Counter/Timer 3 Disable.                                            */
  TIMER_CTRL3_TMR3EN_EN                = 1,     /*!< EN : Counter/Timer 3 Enable.                                              */
} TIMER_CTRL3_TMR3EN_Enum;

/* ========================================================  TIMER3  ========================================================= */
/* =======================================================  TMR3CMP0  ======================================================== */
/* =======================================================  TMR3CMP1  ======================================================== */
/* =========================================================  MODE3  ========================================================= */
/* ============================================  TIMER MODE3 TMR3TRIGSEL [8..15]  ============================================ */
typedef enum {                                  /*!< TIMER_MODE3_TMR3TRIGSEL                                                   */
  TIMER_MODE3_TMR3TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
  TIMER_MODE3_TMR3TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
  TIMER_MODE3_TMR3TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
  TIMER_MODE3_TMR3TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
  TIMER_MODE3_TMR3TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
  TIMER_MODE3_TMR3TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
  TIMER_MODE3_TMR3TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
  TIMER_MODE3_TMR3TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
  TIMER_MODE3_TMR3TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
  TIMER_MODE3_TMR3TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
  TIMER_MODE3_TMR3TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
  TIMER_MODE3_TMR3TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
  TIMER_MODE3_TMR3TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
  TIMER_MODE3_TMR3TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
  TIMER_MODE3_TMR3TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
} TIMER_MODE3_TMR3TRIGSEL_Enum;

/* ======================================================  TMR3LMTVAL  ======================================================= */
/* =========================================================  CTRL4  ========================================================= */
/* ============================================  TIMER CTRL4 TMR4TMODE [16..17]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL4_TMR4TMODE                                                     */
  TIMER_CTRL4_TMR4TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
  TIMER_CTRL4_TMR4TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
  TIMER_CTRL4_TMR4TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
  TIMER_CTRL4_TMR4TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
} TIMER_CTRL4_TMR4TMODE_Enum;

/* ==============================================  TIMER CTRL4 TMR4CLK [8..15]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL4_TMR4CLK                                                       */
  TIMER_CTRL4_TMR4CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
  TIMER_CTRL4_TMR4CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
  TIMER_CTRL4_TMR4CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
  TIMER_CTRL4_TMR4CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
  TIMER_CTRL4_TMR4CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
  TIMER_CTRL4_TMR4CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
  TIMER_CTRL4_TMR4CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
  TIMER_CTRL4_TMR4CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
  TIMER_CTRL4_TMR4CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
  TIMER_CTRL4_TMR4CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
  TIMER_CTRL4_TMR4CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
  TIMER_CTRL4_TMR4CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
  TIMER_CTRL4_TMR4CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
  TIMER_CTRL4_TMR4CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
  TIMER_CTRL4_TMR4CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
  TIMER_CTRL4_TMR4CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
  TIMER_CTRL4_TMR4CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
  TIMER_CTRL4_TMR4CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
  TIMER_CTRL4_TMR4CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
  TIMER_CTRL4_TMR4CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
  TIMER_CTRL4_TMR4CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
  TIMER_CTRL4_TMR4CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
  TIMER_CTRL4_TMR4CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
  TIMER_CTRL4_TMR4CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
  TIMER_CTRL4_TMR4CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
  TIMER_CTRL4_TMR4CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
  TIMER_CTRL4_TMR4CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
  TIMER_CTRL4_TMR4CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
  TIMER_CTRL4_TMR4CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
  TIMER_CTRL4_TMR4CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
  TIMER_CTRL4_TMR4CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
  TIMER_CTRL4_TMR4CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
  TIMER_CTRL4_TMR4CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
  TIMER_CTRL4_TMR4CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
  TIMER_CTRL4_TMR4CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
  TIMER_CTRL4_TMR4CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
  TIMER_CTRL4_TMR4CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
  TIMER_CTRL4_TMR4CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
  TIMER_CTRL4_TMR4CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
  TIMER_CTRL4_TMR4CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
  TIMER_CTRL4_TMR4CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
  TIMER_CTRL4_TMR4CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
  TIMER_CTRL4_TMR4CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
  TIMER_CTRL4_TMR4CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
  TIMER_CTRL4_TMR4CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
  TIMER_CTRL4_TMR4CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
  TIMER_CTRL4_TMR4CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
  TIMER_CTRL4_TMR4CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
  TIMER_CTRL4_TMR4CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
  TIMER_CTRL4_TMR4CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
  TIMER_CTRL4_TMR4CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
  TIMER_CTRL4_TMR4CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
  TIMER_CTRL4_TMR4CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
  TIMER_CTRL4_TMR4CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
  TIMER_CTRL4_TMR4CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
  TIMER_CTRL4_TMR4CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
  TIMER_CTRL4_TMR4CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
  TIMER_CTRL4_TMR4CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
} TIMER_CTRL4_TMR4CLK_Enum;

/* ===============================================  TIMER CTRL4 TMR4FN [4..7]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL4_TMR4FN                                                        */
  TIMER_CTRL4_TMR4FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
                                                     value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
                                                     to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
  TIMER_CTRL4_TMR4FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
                                                     CMP. OUT[0]/OUT[1] is pulsed for one source clock period
                                                     when TIMER matches CMP0/CMP1 respectively. Timer repeats
                                                     for TMR_LMT iterations.                                                   */
  TIMER_CTRL4_TMR4FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
                                                     clock pulse. CMP1 dictates the low phase of the output
                                                     and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
  TIMER_CTRL4_TMR4FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
                                                     LMT field specifies length of pattern. When LMT GT 32 OUT0
                                                     and OUT1 is the same 64-bit pattern consisting of concatenated
                                                     CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
                                                     Both OUT0 and OUT1 can be inverted individually applications
                                                     with POL0/POL1 = 0x1.                                                     */
  TIMER_CTRL4_TMR4FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
                                                     pattern repeats after reaching LMT.                                       */
} TIMER_CTRL4_TMR4FN_Enum;

/* ==============================================  TIMER CTRL4 TMR4POL1 [3..3]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL4_TMR4POL1                                                      */
  TIMER_CTRL4_TMR4POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR4OUT1 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL4_TMR4POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR4OUT1 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL4_TMR4POL1_Enum;

/* ==============================================  TIMER CTRL4 TMR4POL0 [2..2]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL4_TMR4POL0                                                      */
  TIMER_CTRL4_TMR4POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR4OUT0 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL4_TMR4POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR4OUT0 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL4_TMR4POL0_Enum;

/* ==============================================  TIMER CTRL4 TMR4CLR [1..1]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL4_TMR4CLR                                                       */
  TIMER_CTRL4_TMR4CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
                                                     cleared to its reset state # (0 for count up counter, CMP0
                                                     for down counter)                                                         */
  TIMER_CTRL4_TMR4CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
} TIMER_CTRL4_TMR4CLR_Enum;

/* ===============================================  TIMER CTRL4 TMR4EN [0..0]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL4_TMR4EN                                                        */
  TIMER_CTRL4_TMR4EN_DIS               = 0,     /*!< DIS : Counter/Timer 4 Disable.                                            */
  TIMER_CTRL4_TMR4EN_EN                = 1,     /*!< EN : Counter/Timer 4 Enable.                                              */
} TIMER_CTRL4_TMR4EN_Enum;

/* ========================================================  TIMER4  ========================================================= */
/* =======================================================  TMR4CMP0  ======================================================== */
/* =======================================================  TMR4CMP1  ======================================================== */
/* =========================================================  MODE4  ========================================================= */
/* ============================================  TIMER MODE4 TMR4TRIGSEL [8..15]  ============================================ */
typedef enum {                                  /*!< TIMER_MODE4_TMR4TRIGSEL                                                   */
  TIMER_MODE4_TMR4TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
  TIMER_MODE4_TMR4TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
  TIMER_MODE4_TMR4TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
  TIMER_MODE4_TMR4TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
  TIMER_MODE4_TMR4TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
  TIMER_MODE4_TMR4TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
  TIMER_MODE4_TMR4TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
  TIMER_MODE4_TMR4TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
  TIMER_MODE4_TMR4TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
  TIMER_MODE4_TMR4TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
  TIMER_MODE4_TMR4TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
  TIMER_MODE4_TMR4TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
  TIMER_MODE4_TMR4TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
  TIMER_MODE4_TMR4TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
  TIMER_MODE4_TMR4TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
} TIMER_MODE4_TMR4TRIGSEL_Enum;

/* ======================================================  TMR4LMTVAL  ======================================================= */
/* =========================================================  CTRL5  ========================================================= */
/* ============================================  TIMER CTRL5 TMR5TMODE [16..17]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL5_TMR5TMODE                                                     */
  TIMER_CTRL5_TMR5TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
  TIMER_CTRL5_TMR5TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
  TIMER_CTRL5_TMR5TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
  TIMER_CTRL5_TMR5TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
} TIMER_CTRL5_TMR5TMODE_Enum;

/* ==============================================  TIMER CTRL5 TMR5CLK [8..15]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL5_TMR5CLK                                                       */
  TIMER_CTRL5_TMR5CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
  TIMER_CTRL5_TMR5CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
  TIMER_CTRL5_TMR5CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
  TIMER_CTRL5_TMR5CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
  TIMER_CTRL5_TMR5CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
  TIMER_CTRL5_TMR5CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
  TIMER_CTRL5_TMR5CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
  TIMER_CTRL5_TMR5CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
  TIMER_CTRL5_TMR5CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
  TIMER_CTRL5_TMR5CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
  TIMER_CTRL5_TMR5CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
  TIMER_CTRL5_TMR5CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
  TIMER_CTRL5_TMR5CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
  TIMER_CTRL5_TMR5CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
  TIMER_CTRL5_TMR5CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
  TIMER_CTRL5_TMR5CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
  TIMER_CTRL5_TMR5CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
  TIMER_CTRL5_TMR5CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
  TIMER_CTRL5_TMR5CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
  TIMER_CTRL5_TMR5CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
  TIMER_CTRL5_TMR5CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
  TIMER_CTRL5_TMR5CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
  TIMER_CTRL5_TMR5CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
  TIMER_CTRL5_TMR5CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
  TIMER_CTRL5_TMR5CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
  TIMER_CTRL5_TMR5CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
  TIMER_CTRL5_TMR5CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
  TIMER_CTRL5_TMR5CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
  TIMER_CTRL5_TMR5CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
  TIMER_CTRL5_TMR5CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
  TIMER_CTRL5_TMR5CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
  TIMER_CTRL5_TMR5CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
  TIMER_CTRL5_TMR5CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
  TIMER_CTRL5_TMR5CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
  TIMER_CTRL5_TMR5CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
  TIMER_CTRL5_TMR5CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
  TIMER_CTRL5_TMR5CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
  TIMER_CTRL5_TMR5CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
  TIMER_CTRL5_TMR5CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
  TIMER_CTRL5_TMR5CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
  TIMER_CTRL5_TMR5CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
  TIMER_CTRL5_TMR5CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
  TIMER_CTRL5_TMR5CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
  TIMER_CTRL5_TMR5CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
  TIMER_CTRL5_TMR5CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
  TIMER_CTRL5_TMR5CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
  TIMER_CTRL5_TMR5CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
  TIMER_CTRL5_TMR5CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
  TIMER_CTRL5_TMR5CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
  TIMER_CTRL5_TMR5CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
  TIMER_CTRL5_TMR5CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
  TIMER_CTRL5_TMR5CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
  TIMER_CTRL5_TMR5CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
  TIMER_CTRL5_TMR5CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
  TIMER_CTRL5_TMR5CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
  TIMER_CTRL5_TMR5CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
  TIMER_CTRL5_TMR5CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
  TIMER_CTRL5_TMR5CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
} TIMER_CTRL5_TMR5CLK_Enum;

/* ===============================================  TIMER CTRL5 TMR5FN [4..7]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL5_TMR5FN                                                        */
  TIMER_CTRL5_TMR5FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
                                                     value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
                                                     to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
  TIMER_CTRL5_TMR5FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
                                                     CMP. OUT[0]/OUT[1] is pulsed for one source clock period
                                                     when TIMER matches CMP0/CMP1 respectively. Timer repeats
                                                     for TMR_LMT iterations.                                                   */
  TIMER_CTRL5_TMR5FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
                                                     clock pulse. CMP1 dictates the low phase of the output
                                                     and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
  TIMER_CTRL5_TMR5FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
                                                     LMT field specifies length of pattern. When LMT GT 32 OUT0
                                                     and OUT1 is the same 64-bit pattern consisting of concatenated
                                                     CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
                                                     Both OUT0 and OUT1 can be inverted individually applications
                                                     with POL0/POL1 = 0x1.                                                     */
  TIMER_CTRL5_TMR5FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
                                                     pattern repeats after reaching LMT.                                       */
} TIMER_CTRL5_TMR5FN_Enum;

/* ==============================================  TIMER CTRL5 TMR5POL1 [3..3]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL5_TMR5POL1                                                      */
  TIMER_CTRL5_TMR5POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR5OUT1 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL5_TMR5POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR5OUT1 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL5_TMR5POL1_Enum;

/* ==============================================  TIMER CTRL5 TMR5POL0 [2..2]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL5_TMR5POL0                                                      */
  TIMER_CTRL5_TMR5POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR5OUT0 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL5_TMR5POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR5OUT0 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL5_TMR5POL0_Enum;

/* ==============================================  TIMER CTRL5 TMR5CLR [1..1]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL5_TMR5CLR                                                       */
  TIMER_CTRL5_TMR5CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
                                                     cleared to its reset state # (0 for count up counter, CMP0
                                                     for down counter)                                                         */
  TIMER_CTRL5_TMR5CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
} TIMER_CTRL5_TMR5CLR_Enum;

/* ===============================================  TIMER CTRL5 TMR5EN [0..0]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL5_TMR5EN                                                        */
  TIMER_CTRL5_TMR5EN_DIS               = 0,     /*!< DIS : Counter/Timer 5 Disable.                                            */
  TIMER_CTRL5_TMR5EN_EN                = 1,     /*!< EN : Counter/Timer 5 Enable.                                              */
} TIMER_CTRL5_TMR5EN_Enum;

/* ========================================================  TIMER5  ========================================================= */
/* =======================================================  TMR5CMP0  ======================================================== */
/* =======================================================  TMR5CMP1  ======================================================== */
/* =========================================================  MODE5  ========================================================= */
/* ============================================  TIMER MODE5 TMR5TRIGSEL [8..15]  ============================================ */
typedef enum {                                  /*!< TIMER_MODE5_TMR5TRIGSEL                                                   */
  TIMER_MODE5_TMR5TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
  TIMER_MODE5_TMR5TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
  TIMER_MODE5_TMR5TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
  TIMER_MODE5_TMR5TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
  TIMER_MODE5_TMR5TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
  TIMER_MODE5_TMR5TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
  TIMER_MODE5_TMR5TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
  TIMER_MODE5_TMR5TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
  TIMER_MODE5_TMR5TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
  TIMER_MODE5_TMR5TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
  TIMER_MODE5_TMR5TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
  TIMER_MODE5_TMR5TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
  TIMER_MODE5_TMR5TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
  TIMER_MODE5_TMR5TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
  TIMER_MODE5_TMR5TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
} TIMER_MODE5_TMR5TRIGSEL_Enum;

/* ======================================================  TMR5LMTVAL  ======================================================= */
/* =========================================================  CTRL6  ========================================================= */
/* ============================================  TIMER CTRL6 TMR6TMODE [16..17]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL6_TMR6TMODE                                                     */
  TIMER_CTRL6_TMR6TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
  TIMER_CTRL6_TMR6TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
  TIMER_CTRL6_TMR6TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
  TIMER_CTRL6_TMR6TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
} TIMER_CTRL6_TMR6TMODE_Enum;

/* ==============================================  TIMER CTRL6 TMR6CLK [8..15]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL6_TMR6CLK                                                       */
  TIMER_CTRL6_TMR6CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
  TIMER_CTRL6_TMR6CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
  TIMER_CTRL6_TMR6CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
  TIMER_CTRL6_TMR6CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
  TIMER_CTRL6_TMR6CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
  TIMER_CTRL6_TMR6CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
  TIMER_CTRL6_TMR6CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
  TIMER_CTRL6_TMR6CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
  TIMER_CTRL6_TMR6CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
  TIMER_CTRL6_TMR6CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
  TIMER_CTRL6_TMR6CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
  TIMER_CTRL6_TMR6CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
  TIMER_CTRL6_TMR6CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
  TIMER_CTRL6_TMR6CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
  TIMER_CTRL6_TMR6CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
  TIMER_CTRL6_TMR6CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
  TIMER_CTRL6_TMR6CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
  TIMER_CTRL6_TMR6CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
  TIMER_CTRL6_TMR6CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
  TIMER_CTRL6_TMR6CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
  TIMER_CTRL6_TMR6CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
  TIMER_CTRL6_TMR6CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
  TIMER_CTRL6_TMR6CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
  TIMER_CTRL6_TMR6CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
  TIMER_CTRL6_TMR6CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
  TIMER_CTRL6_TMR6CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
  TIMER_CTRL6_TMR6CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
  TIMER_CTRL6_TMR6CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
  TIMER_CTRL6_TMR6CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
  TIMER_CTRL6_TMR6CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
  TIMER_CTRL6_TMR6CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
  TIMER_CTRL6_TMR6CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
  TIMER_CTRL6_TMR6CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
  TIMER_CTRL6_TMR6CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
  TIMER_CTRL6_TMR6CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
  TIMER_CTRL6_TMR6CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
  TIMER_CTRL6_TMR6CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
  TIMER_CTRL6_TMR6CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
  TIMER_CTRL6_TMR6CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
  TIMER_CTRL6_TMR6CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
  TIMER_CTRL6_TMR6CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
  TIMER_CTRL6_TMR6CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
  TIMER_CTRL6_TMR6CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
  TIMER_CTRL6_TMR6CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
  TIMER_CTRL6_TMR6CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
  TIMER_CTRL6_TMR6CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
  TIMER_CTRL6_TMR6CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
  TIMER_CTRL6_TMR6CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
  TIMER_CTRL6_TMR6CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
  TIMER_CTRL6_TMR6CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
  TIMER_CTRL6_TMR6CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
  TIMER_CTRL6_TMR6CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
  TIMER_CTRL6_TMR6CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
  TIMER_CTRL6_TMR6CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
  TIMER_CTRL6_TMR6CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
  TIMER_CTRL6_TMR6CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
  TIMER_CTRL6_TMR6CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
  TIMER_CTRL6_TMR6CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
} TIMER_CTRL6_TMR6CLK_Enum;

/* ===============================================  TIMER CTRL6 TMR6FN [4..7]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL6_TMR6FN                                                        */
  TIMER_CTRL6_TMR6FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
                                                     value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
                                                     to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
  TIMER_CTRL6_TMR6FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
                                                     CMP. OUT[0]/OUT[1] is pulsed for one source clock period
                                                     when TIMER matches CMP0/CMP1 respectively. Timer repeats
                                                     for TMR_LMT iterations.                                                   */
  TIMER_CTRL6_TMR6FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
                                                     clock pulse. CMP1 dictates the low phase of the output
                                                     and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
  TIMER_CTRL6_TMR6FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
                                                     LMT field specifies length of pattern. When LMT GT 32 OUT0
                                                     and OUT1 is the same 64-bit pattern consisting of concatenated
                                                     CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
                                                     Both OUT0 and OUT1 can be inverted individually applications
                                                     with POL0/POL1 = 0x1.                                                     */
  TIMER_CTRL6_TMR6FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
                                                     pattern repeats after reaching LMT.                                       */
} TIMER_CTRL6_TMR6FN_Enum;

/* ==============================================  TIMER CTRL6 TMR6POL1 [3..3]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL6_TMR6POL1                                                      */
  TIMER_CTRL6_TMR6POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR6OUT1 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL6_TMR6POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR6OUT1 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL6_TMR6POL1_Enum;

/* ==============================================  TIMER CTRL6 TMR6POL0 [2..2]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL6_TMR6POL0                                                      */
  TIMER_CTRL6_TMR6POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR6OUT0 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL6_TMR6POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR6OUT0 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL6_TMR6POL0_Enum;

/* ==============================================  TIMER CTRL6 TMR6CLR [1..1]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL6_TMR6CLR                                                       */
  TIMER_CTRL6_TMR6CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
                                                     cleared to its reset state # (0 for count up counter, CMP0
                                                     for down counter)                                                         */
  TIMER_CTRL6_TMR6CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
} TIMER_CTRL6_TMR6CLR_Enum;

/* ===============================================  TIMER CTRL6 TMR6EN [0..0]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL6_TMR6EN                                                        */
  TIMER_CTRL6_TMR6EN_DIS               = 0,     /*!< DIS : Counter/Timer 6 Disable.                                            */
  TIMER_CTRL6_TMR6EN_EN                = 1,     /*!< EN : Counter/Timer 6 Enable.                                              */
} TIMER_CTRL6_TMR6EN_Enum;

/* ========================================================  TIMER6  ========================================================= */
/* =======================================================  TMR6CMP0  ======================================================== */
/* =======================================================  TMR6CMP1  ======================================================== */
/* =========================================================  MODE6  ========================================================= */
/* ============================================  TIMER MODE6 TMR6TRIGSEL [8..15]  ============================================ */
typedef enum {                                  /*!< TIMER_MODE6_TMR6TRIGSEL                                                   */
  TIMER_MODE6_TMR6TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
  TIMER_MODE6_TMR6TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
  TIMER_MODE6_TMR6TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
  TIMER_MODE6_TMR6TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
  TIMER_MODE6_TMR6TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
  TIMER_MODE6_TMR6TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
  TIMER_MODE6_TMR6TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
  TIMER_MODE6_TMR6TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
  TIMER_MODE6_TMR6TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
  TIMER_MODE6_TMR6TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
  TIMER_MODE6_TMR6TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
  TIMER_MODE6_TMR6TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
  TIMER_MODE6_TMR6TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
  TIMER_MODE6_TMR6TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
  TIMER_MODE6_TMR6TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
} TIMER_MODE6_TMR6TRIGSEL_Enum;

/* ======================================================  TMR6LMTVAL  ======================================================= */
/* =========================================================  CTRL7  ========================================================= */
/* ============================================  TIMER CTRL7 TMR7TMODE [16..17]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL7_TMR7TMODE                                                     */
  TIMER_CTRL7_TMR7TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
  TIMER_CTRL7_TMR7TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
  TIMER_CTRL7_TMR7TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
  TIMER_CTRL7_TMR7TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
} TIMER_CTRL7_TMR7TMODE_Enum;

/* ==============================================  TIMER CTRL7 TMR7CLK [8..15]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL7_TMR7CLK                                                       */
  TIMER_CTRL7_TMR7CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
  TIMER_CTRL7_TMR7CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
  TIMER_CTRL7_TMR7CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
  TIMER_CTRL7_TMR7CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
  TIMER_CTRL7_TMR7CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
  TIMER_CTRL7_TMR7CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
  TIMER_CTRL7_TMR7CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
  TIMER_CTRL7_TMR7CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
  TIMER_CTRL7_TMR7CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
  TIMER_CTRL7_TMR7CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
  TIMER_CTRL7_TMR7CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
  TIMER_CTRL7_TMR7CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
  TIMER_CTRL7_TMR7CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
  TIMER_CTRL7_TMR7CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
  TIMER_CTRL7_TMR7CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
  TIMER_CTRL7_TMR7CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
  TIMER_CTRL7_TMR7CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
  TIMER_CTRL7_TMR7CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
  TIMER_CTRL7_TMR7CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
  TIMER_CTRL7_TMR7CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
  TIMER_CTRL7_TMR7CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
  TIMER_CTRL7_TMR7CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
  TIMER_CTRL7_TMR7CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
  TIMER_CTRL7_TMR7CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
  TIMER_CTRL7_TMR7CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
  TIMER_CTRL7_TMR7CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
  TIMER_CTRL7_TMR7CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
  TIMER_CTRL7_TMR7CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
  TIMER_CTRL7_TMR7CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
  TIMER_CTRL7_TMR7CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
  TIMER_CTRL7_TMR7CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
  TIMER_CTRL7_TMR7CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
  TIMER_CTRL7_TMR7CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
  TIMER_CTRL7_TMR7CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
  TIMER_CTRL7_TMR7CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
  TIMER_CTRL7_TMR7CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
  TIMER_CTRL7_TMR7CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
  TIMER_CTRL7_TMR7CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
  TIMER_CTRL7_TMR7CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
  TIMER_CTRL7_TMR7CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
  TIMER_CTRL7_TMR7CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
  TIMER_CTRL7_TMR7CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
  TIMER_CTRL7_TMR7CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
  TIMER_CTRL7_TMR7CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
  TIMER_CTRL7_TMR7CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
  TIMER_CTRL7_TMR7CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
  TIMER_CTRL7_TMR7CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
  TIMER_CTRL7_TMR7CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
  TIMER_CTRL7_TMR7CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
  TIMER_CTRL7_TMR7CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
  TIMER_CTRL7_TMR7CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
  TIMER_CTRL7_TMR7CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
  TIMER_CTRL7_TMR7CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
  TIMER_CTRL7_TMR7CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
  TIMER_CTRL7_TMR7CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
  TIMER_CTRL7_TMR7CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
  TIMER_CTRL7_TMR7CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
  TIMER_CTRL7_TMR7CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
} TIMER_CTRL7_TMR7CLK_Enum;

/* ===============================================  TIMER CTRL7 TMR7FN [4..7]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL7_TMR7FN                                                        */
  TIMER_CTRL7_TMR7FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
                                                     value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
                                                     to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
  TIMER_CTRL7_TMR7FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
                                                     CMP. OUT[0]/OUT[1] is pulsed for one source clock period
                                                     when TIMER matches CMP0/CMP1 respectively. Timer repeats
                                                     for TMR_LMT iterations.                                                   */
  TIMER_CTRL7_TMR7FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
                                                     clock pulse. CMP1 dictates the low phase of the output
                                                     and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
  TIMER_CTRL7_TMR7FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
                                                     LMT field specifies length of pattern. When LMT GT 32 OUT0
                                                     and OUT1 is the same 64-bit pattern consisting of concatenated
                                                     CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
                                                     Both OUT0 and OUT1 can be inverted individually applications
                                                     with POL0/POL1 = 0x1.                                                     */
  TIMER_CTRL7_TMR7FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
                                                     pattern repeats after reaching LMT.                                       */
} TIMER_CTRL7_TMR7FN_Enum;

/* ==============================================  TIMER CTRL7 TMR7POL1 [3..3]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL7_TMR7POL1                                                      */
  TIMER_CTRL7_TMR7POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR7OUT1 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL7_TMR7POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR7OUT1 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL7_TMR7POL1_Enum;

/* ==============================================  TIMER CTRL7 TMR7POL0 [2..2]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL7_TMR7POL0                                                      */
  TIMER_CTRL7_TMR7POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR7OUT0 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL7_TMR7POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR7OUT0 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL7_TMR7POL0_Enum;

/* ==============================================  TIMER CTRL7 TMR7CLR [1..1]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL7_TMR7CLR                                                       */
  TIMER_CTRL7_TMR7CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
                                                     cleared to its reset state # (0 for count up counter, CMP0
                                                     for down counter)                                                         */
  TIMER_CTRL7_TMR7CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
} TIMER_CTRL7_TMR7CLR_Enum;

/* ===============================================  TIMER CTRL7 TMR7EN [0..0]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL7_TMR7EN                                                        */
  TIMER_CTRL7_TMR7EN_DIS               = 0,     /*!< DIS : Counter/Timer 7 Disable.                                            */
  TIMER_CTRL7_TMR7EN_EN                = 1,     /*!< EN : Counter/Timer 7 Enable.                                              */
} TIMER_CTRL7_TMR7EN_Enum;

/* ========================================================  TIMER7  ========================================================= */
/* =======================================================  TMR7CMP0  ======================================================== */
/* =======================================================  TMR7CMP1  ======================================================== */
/* =========================================================  MODE7  ========================================================= */
/* ============================================  TIMER MODE7 TMR7TRIGSEL [8..15]  ============================================ */
typedef enum {                                  /*!< TIMER_MODE7_TMR7TRIGSEL                                                   */
  TIMER_MODE7_TMR7TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
  TIMER_MODE7_TMR7TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
  TIMER_MODE7_TMR7TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
  TIMER_MODE7_TMR7TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
  TIMER_MODE7_TMR7TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
  TIMER_MODE7_TMR7TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
  TIMER_MODE7_TMR7TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
  TIMER_MODE7_TMR7TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
  TIMER_MODE7_TMR7TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
  TIMER_MODE7_TMR7TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
  TIMER_MODE7_TMR7TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
  TIMER_MODE7_TMR7TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
  TIMER_MODE7_TMR7TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
  TIMER_MODE7_TMR7TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
  TIMER_MODE7_TMR7TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
} TIMER_MODE7_TMR7TRIGSEL_Enum;

/* ======================================================  TMR7LMTVAL  ======================================================= */
/* =========================================================  CTRL8  ========================================================= */
/* ============================================  TIMER CTRL8 TMR8TMODE [16..17]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL8_TMR8TMODE                                                     */
  TIMER_CTRL8_TMR8TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
  TIMER_CTRL8_TMR8TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
  TIMER_CTRL8_TMR8TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
  TIMER_CTRL8_TMR8TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
} TIMER_CTRL8_TMR8TMODE_Enum;

/* ==============================================  TIMER CTRL8 TMR8CLK [8..15]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL8_TMR8CLK                                                       */
  TIMER_CTRL8_TMR8CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
  TIMER_CTRL8_TMR8CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
  TIMER_CTRL8_TMR8CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
  TIMER_CTRL8_TMR8CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
  TIMER_CTRL8_TMR8CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
  TIMER_CTRL8_TMR8CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
  TIMER_CTRL8_TMR8CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
  TIMER_CTRL8_TMR8CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
  TIMER_CTRL8_TMR8CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
  TIMER_CTRL8_TMR8CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
  TIMER_CTRL8_TMR8CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
  TIMER_CTRL8_TMR8CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
  TIMER_CTRL8_TMR8CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
  TIMER_CTRL8_TMR8CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
  TIMER_CTRL8_TMR8CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
  TIMER_CTRL8_TMR8CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
  TIMER_CTRL8_TMR8CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
  TIMER_CTRL8_TMR8CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
  TIMER_CTRL8_TMR8CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
  TIMER_CTRL8_TMR8CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
  TIMER_CTRL8_TMR8CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
  TIMER_CTRL8_TMR8CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
  TIMER_CTRL8_TMR8CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
  TIMER_CTRL8_TMR8CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
  TIMER_CTRL8_TMR8CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
  TIMER_CTRL8_TMR8CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
  TIMER_CTRL8_TMR8CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
  TIMER_CTRL8_TMR8CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
  TIMER_CTRL8_TMR8CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
  TIMER_CTRL8_TMR8CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
  TIMER_CTRL8_TMR8CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
  TIMER_CTRL8_TMR8CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
  TIMER_CTRL8_TMR8CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
  TIMER_CTRL8_TMR8CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
  TIMER_CTRL8_TMR8CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
  TIMER_CTRL8_TMR8CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
  TIMER_CTRL8_TMR8CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
  TIMER_CTRL8_TMR8CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
  TIMER_CTRL8_TMR8CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
  TIMER_CTRL8_TMR8CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
  TIMER_CTRL8_TMR8CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
  TIMER_CTRL8_TMR8CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
  TIMER_CTRL8_TMR8CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
  TIMER_CTRL8_TMR8CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
  TIMER_CTRL8_TMR8CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
  TIMER_CTRL8_TMR8CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
  TIMER_CTRL8_TMR8CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
  TIMER_CTRL8_TMR8CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
  TIMER_CTRL8_TMR8CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
  TIMER_CTRL8_TMR8CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
  TIMER_CTRL8_TMR8CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
  TIMER_CTRL8_TMR8CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
  TIMER_CTRL8_TMR8CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
  TIMER_CTRL8_TMR8CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
  TIMER_CTRL8_TMR8CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
  TIMER_CTRL8_TMR8CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
  TIMER_CTRL8_TMR8CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
  TIMER_CTRL8_TMR8CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
} TIMER_CTRL8_TMR8CLK_Enum;

/* ===============================================  TIMER CTRL8 TMR8FN [4..7]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL8_TMR8FN                                                        */
  TIMER_CTRL8_TMR8FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
                                                     value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
                                                     to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
  TIMER_CTRL8_TMR8FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
                                                     CMP. OUT[0]/OUT[1] is pulsed for one source clock period
                                                     when TIMER matches CMP0/CMP1 respectively. Timer repeats
                                                     for TMR_LMT iterations.                                                   */
  TIMER_CTRL8_TMR8FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
                                                     clock pulse. CMP1 dictates the low phase of the output
                                                     and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
  TIMER_CTRL8_TMR8FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
                                                     LMT field specifies length of pattern. When LMT GT 32 OUT0
                                                     and OUT1 is the same 64-bit pattern consisting of concatenated
                                                     CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
                                                     Both OUT0 and OUT1 can be inverted individually applications
                                                     with POL0/POL1 = 0x1.                                                     */
  TIMER_CTRL8_TMR8FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
                                                     pattern repeats after reaching LMT.                                       */
} TIMER_CTRL8_TMR8FN_Enum;

/* ==============================================  TIMER CTRL8 TMR8POL1 [3..3]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL8_TMR8POL1                                                      */
  TIMER_CTRL8_TMR8POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR8OUT1 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL8_TMR8POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR8OUT1 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL8_TMR8POL1_Enum;

/* ==============================================  TIMER CTRL8 TMR8POL0 [2..2]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL8_TMR8POL0                                                      */
  TIMER_CTRL8_TMR8POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR8OUT0 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL8_TMR8POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR8OUT0 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL8_TMR8POL0_Enum;

/* ==============================================  TIMER CTRL8 TMR8CLR [1..1]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL8_TMR8CLR                                                       */
  TIMER_CTRL8_TMR8CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
                                                     cleared to its reset state # (0 for count up counter, CMP0
                                                     for down counter)                                                         */
  TIMER_CTRL8_TMR8CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
} TIMER_CTRL8_TMR8CLR_Enum;

/* ===============================================  TIMER CTRL8 TMR8EN [0..0]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL8_TMR8EN                                                        */
  TIMER_CTRL8_TMR8EN_DIS               = 0,     /*!< DIS : Counter/Timer 8 Disable.                                            */
  TIMER_CTRL8_TMR8EN_EN                = 1,     /*!< EN : Counter/Timer 8 Enable.                                              */
} TIMER_CTRL8_TMR8EN_Enum;

/* ========================================================  TIMER8  ========================================================= */
/* =======================================================  TMR8CMP0  ======================================================== */
/* =======================================================  TMR8CMP1  ======================================================== */
/* =========================================================  MODE8  ========================================================= */
/* ============================================  TIMER MODE8 TMR8TRIGSEL [8..15]  ============================================ */
typedef enum {                                  /*!< TIMER_MODE8_TMR8TRIGSEL                                                   */
  TIMER_MODE8_TMR8TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
  TIMER_MODE8_TMR8TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
  TIMER_MODE8_TMR8TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
  TIMER_MODE8_TMR8TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
  TIMER_MODE8_TMR8TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
  TIMER_MODE8_TMR8TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
  TIMER_MODE8_TMR8TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
  TIMER_MODE8_TMR8TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
  TIMER_MODE8_TMR8TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
  TIMER_MODE8_TMR8TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
  TIMER_MODE8_TMR8TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
  TIMER_MODE8_TMR8TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
  TIMER_MODE8_TMR8TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
  TIMER_MODE8_TMR8TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
  TIMER_MODE8_TMR8TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
} TIMER_MODE8_TMR8TRIGSEL_Enum;

/* ======================================================  TMR8LMTVAL  ======================================================= */
/* =========================================================  CTRL9  ========================================================= */
/* ============================================  TIMER CTRL9 TMR9TMODE [16..17]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL9_TMR9TMODE                                                     */
  TIMER_CTRL9_TMR9TMODE_DIS            = 0,     /*!< DIS : Trigger not enabled                                                 */
  TIMER_CTRL9_TMR9TMODE_RISE           = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
  TIMER_CTRL9_TMR9TMODE_FALL           = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
  TIMER_CTRL9_TMR9TMODE_BOTH           = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
} TIMER_CTRL9_TMR9TMODE_Enum;

/* ==============================================  TIMER CTRL9 TMR9CLK [8..15]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL9_TMR9CLK                                                       */
  TIMER_CTRL9_TMR9CLK_HFRC_DIV4        = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
  TIMER_CTRL9_TMR9CLK_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
  TIMER_CTRL9_TMR9CLK_HFRC_DIV64       = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
  TIMER_CTRL9_TMR9CLK_HFRC_DIV256      = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
  TIMER_CTRL9_TMR9CLK_HFRC_DIV1024     = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
  TIMER_CTRL9_TMR9CLK_HFRC_DIV4K       = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
  TIMER_CTRL9_TMR9CLK_LFRC             = 6,     /*!< LFRC : Clock source is LFRC                                               */
  TIMER_CTRL9_TMR9CLK_LFRC_DIV2        = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
  TIMER_CTRL9_TMR9CLK_LFRC_DIV32       = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
  TIMER_CTRL9_TMR9CLK_LFRC_DIV1K       = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
  TIMER_CTRL9_TMR9CLK_XT               = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
  TIMER_CTRL9_TMR9CLK_XT_DIV2          = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
  TIMER_CTRL9_TMR9CLK_XT_DIV4          = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
  TIMER_CTRL9_TMR9CLK_XT_DIV8          = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
  TIMER_CTRL9_TMR9CLK_XT_DIV16         = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
  TIMER_CTRL9_TMR9CLK_XT_DIV32         = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
  TIMER_CTRL9_TMR9CLK_XT_DIV128        = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
  TIMER_CTRL9_TMR9CLK_RTC_100HZ        = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
  TIMER_CTRL9_TMR9CLK_BUCKC            = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
  TIMER_CTRL9_TMR9CLK_BUCKF            = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
  TIMER_CTRL9_TMR9CLK_BUCKS            = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
  TIMER_CTRL9_TMR9CLK_BUCKC_LV         = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
  TIMER_CTRL9_TMR9CLK_TMR00            = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
  TIMER_CTRL9_TMR9CLK_TMR01            = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
  TIMER_CTRL9_TMR9CLK_TMR10            = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
  TIMER_CTRL9_TMR9CLK_TMR11            = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
  TIMER_CTRL9_TMR9CLK_TMR20            = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
  TIMER_CTRL9_TMR9CLK_TMR21            = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
  TIMER_CTRL9_TMR9CLK_TMR30            = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
  TIMER_CTRL9_TMR9CLK_TMR31            = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
  TIMER_CTRL9_TMR9CLK_TMR40            = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
  TIMER_CTRL9_TMR9CLK_TMR41            = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
  TIMER_CTRL9_TMR9CLK_TMR50            = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
  TIMER_CTRL9_TMR9CLK_TMR51            = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
  TIMER_CTRL9_TMR9CLK_TMR60            = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
  TIMER_CTRL9_TMR9CLK_TMR61            = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
  TIMER_CTRL9_TMR9CLK_TMR70            = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
  TIMER_CTRL9_TMR9CLK_TMR71            = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
  TIMER_CTRL9_TMR9CLK_TMR80            = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
  TIMER_CTRL9_TMR9CLK_TMR81            = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
  TIMER_CTRL9_TMR9CLK_TMR90            = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
  TIMER_CTRL9_TMR9CLK_TMR91            = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
  TIMER_CTRL9_TMR9CLK_TMR100           = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
  TIMER_CTRL9_TMR9CLK_TMR101           = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
  TIMER_CTRL9_TMR9CLK_TMR110           = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
  TIMER_CTRL9_TMR9CLK_TMR111           = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
  TIMER_CTRL9_TMR9CLK_TMR120           = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
  TIMER_CTRL9_TMR9CLK_TMR121           = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
  TIMER_CTRL9_TMR9CLK_TMR130           = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
  TIMER_CTRL9_TMR9CLK_TMR131           = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
  TIMER_CTRL9_TMR9CLK_TMR140           = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
  TIMER_CTRL9_TMR9CLK_TMR141           = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
  TIMER_CTRL9_TMR9CLK_TMR150           = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
  TIMER_CTRL9_TMR9CLK_TMR151           = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
  TIMER_CTRL9_TMR9CLK_GPIO0            = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
  TIMER_CTRL9_TMR9CLK_GPIO63           = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
  TIMER_CTRL9_TMR9CLK_GPIO95           = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
  TIMER_CTRL9_TMR9CLK_GPIO127          = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
} TIMER_CTRL9_TMR9CLK_Enum;

/* ===============================================  TIMER CTRL9 TMR9FN [4..7]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL9_TMR9FN                                                        */
  TIMER_CTRL9_TMR9FN_EDGE              = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
                                                     value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
                                                     to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
  TIMER_CTRL9_TMR9FN_UPCOUNT           = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
                                                     CMP. OUT[0]/OUT[1] is pulsed for one source clock period
                                                     when TIMER matches CMP0/CMP1 respectively. Timer repeats
                                                     for TMR_LMT iterations.                                                   */
  TIMER_CTRL9_TMR9FN_PWM               = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
                                                     clock pulse. CMP1 dictates the low phase of the output
                                                     and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
  TIMER_CTRL9_TMR9FN_SINGLEPATTERN     = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
                                                     LMT field specifies length of pattern. When LMT GT 32 OUT0
                                                     and OUT1 is the same 64-bit pattern consisting of concatenated
                                                     CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
                                                     Both OUT0 and OUT1 can be inverted individually applications
                                                     with POL0/POL1 = 0x1.                                                     */
  TIMER_CTRL9_TMR9FN_REPEATPATTERN     = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
                                                     pattern repeats after reaching LMT.                                       */
} TIMER_CTRL9_TMR9FN_Enum;

/* ==============================================  TIMER CTRL9 TMR9POL1 [3..3]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL9_TMR9POL1                                                      */
  TIMER_CTRL9_TMR9POL1_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR9OUT1 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL9_TMR9POL1_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR9OUT1 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL9_TMR9POL1_Enum;

/* ==============================================  TIMER CTRL9 TMR9POL0 [2..2]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL9_TMR9POL0                                                      */
  TIMER_CTRL9_TMR9POL0_NORMAL          = 0,     /*!< NORMAL : The polarity of the TMR9OUT0 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL9_TMR9POL0_INVERTED        = 1,     /*!< INVERTED : The polarity of the TMR9OUT0 pin is the inverse of
                                                     the timer output.                                                         */
} TIMER_CTRL9_TMR9POL0_Enum;

/* ==============================================  TIMER CTRL9 TMR9CLR [1..1]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL9_TMR9CLR                                                       */
  TIMER_CTRL9_TMR9CLR_CLEAR            = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
                                                     cleared to its reset state # (0 for count up counter, CMP0
                                                     for down counter)                                                         */
  TIMER_CTRL9_TMR9CLR_DEFAULT          = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
} TIMER_CTRL9_TMR9CLR_Enum;

/* ===============================================  TIMER CTRL9 TMR9EN [0..0]  =============================================== */
typedef enum {                                  /*!< TIMER_CTRL9_TMR9EN                                                        */
  TIMER_CTRL9_TMR9EN_DIS               = 0,     /*!< DIS : Counter/Timer 9 Disable.                                            */
  TIMER_CTRL9_TMR9EN_EN                = 1,     /*!< EN : Counter/Timer 9 Enable.                                              */
} TIMER_CTRL9_TMR9EN_Enum;

/* ========================================================  TIMER9  ========================================================= */
/* =======================================================  TMR9CMP0  ======================================================== */
/* =======================================================  TMR9CMP1  ======================================================== */
/* =========================================================  MODE9  ========================================================= */
/* ============================================  TIMER MODE9 TMR9TRIGSEL [8..15]  ============================================ */
typedef enum {                                  /*!< TIMER_MODE9_TMR9TRIGSEL                                                   */
  TIMER_MODE9_TMR9TRIGSEL_TMR00        = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR01        = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR10        = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR11        = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR20        = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR21        = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR30        = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR31        = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR40        = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR41        = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR50        = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR51        = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR60        = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR61        = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR70        = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR71        = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR80        = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR81        = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR90        = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR91        = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
  TIMER_MODE9_TMR9TRIGSEL_TMR100       = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
  TIMER_MODE9_TMR9TRIGSEL_TMR101       = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
  TIMER_MODE9_TMR9TRIGSEL_TMR110       = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
  TIMER_MODE9_TMR9TRIGSEL_TMR111       = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
  TIMER_MODE9_TMR9TRIGSEL_TMR120       = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
  TIMER_MODE9_TMR9TRIGSEL_TMR121       = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
  TIMER_MODE9_TMR9TRIGSEL_TMR130       = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
  TIMER_MODE9_TMR9TRIGSEL_TMR131       = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
  TIMER_MODE9_TMR9TRIGSEL_TMR140       = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
  TIMER_MODE9_TMR9TRIGSEL_TMR141       = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
  TIMER_MODE9_TMR9TRIGSEL_TMR150       = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
  TIMER_MODE9_TMR9TRIGSEL_TMR151       = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
  TIMER_MODE9_TMR9TRIGSEL_GPIO0        = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
  TIMER_MODE9_TMR9TRIGSEL_GPIO127      = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
} TIMER_MODE9_TMR9TRIGSEL_Enum;

/* ======================================================  TMR9LMTVAL  ======================================================= */
/* ========================================================  CTRL10  ========================================================= */
/* ===========================================  TIMER CTRL10 TMR10TMODE [16..17]  ============================================ */
typedef enum {                                  /*!< TIMER_CTRL10_TMR10TMODE                                                   */
  TIMER_CTRL10_TMR10TMODE_DIS          = 0,     /*!< DIS : Trigger not enabled                                                 */
  TIMER_CTRL10_TMR10TMODE_RISE         = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
  TIMER_CTRL10_TMR10TMODE_FALL         = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
  TIMER_CTRL10_TMR10TMODE_BOTH         = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
} TIMER_CTRL10_TMR10TMODE_Enum;

/* =============================================  TIMER CTRL10 TMR10CLK [8..15]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL10_TMR10CLK                                                     */
  TIMER_CTRL10_TMR10CLK_HFRC_DIV4      = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
  TIMER_CTRL10_TMR10CLK_HFRC_DIV16     = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
  TIMER_CTRL10_TMR10CLK_HFRC_DIV64     = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
  TIMER_CTRL10_TMR10CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
  TIMER_CTRL10_TMR10CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
  TIMER_CTRL10_TMR10CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
  TIMER_CTRL10_TMR10CLK_LFRC           = 6,     /*!< LFRC : Clock source is LFRC                                               */
  TIMER_CTRL10_TMR10CLK_LFRC_DIV2      = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
  TIMER_CTRL10_TMR10CLK_LFRC_DIV32     = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
  TIMER_CTRL10_TMR10CLK_LFRC_DIV1K     = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
  TIMER_CTRL10_TMR10CLK_XT             = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
  TIMER_CTRL10_TMR10CLK_XT_DIV2        = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
  TIMER_CTRL10_TMR10CLK_XT_DIV4        = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
  TIMER_CTRL10_TMR10CLK_XT_DIV8        = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
  TIMER_CTRL10_TMR10CLK_XT_DIV16       = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
  TIMER_CTRL10_TMR10CLK_XT_DIV32       = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
  TIMER_CTRL10_TMR10CLK_XT_DIV128      = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
  TIMER_CTRL10_TMR10CLK_RTC_100HZ      = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
  TIMER_CTRL10_TMR10CLK_BUCKC          = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
  TIMER_CTRL10_TMR10CLK_BUCKF          = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
  TIMER_CTRL10_TMR10CLK_BUCKS          = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
  TIMER_CTRL10_TMR10CLK_BUCKC_LV       = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
  TIMER_CTRL10_TMR10CLK_TMR00          = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
  TIMER_CTRL10_TMR10CLK_TMR01          = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
  TIMER_CTRL10_TMR10CLK_TMR10          = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
  TIMER_CTRL10_TMR10CLK_TMR11          = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
  TIMER_CTRL10_TMR10CLK_TMR20          = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
  TIMER_CTRL10_TMR10CLK_TMR21          = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
  TIMER_CTRL10_TMR10CLK_TMR30          = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
  TIMER_CTRL10_TMR10CLK_TMR31          = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
  TIMER_CTRL10_TMR10CLK_TMR40          = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
  TIMER_CTRL10_TMR10CLK_TMR41          = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
  TIMER_CTRL10_TMR10CLK_TMR50          = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
  TIMER_CTRL10_TMR10CLK_TMR51          = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
  TIMER_CTRL10_TMR10CLK_TMR60          = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
  TIMER_CTRL10_TMR10CLK_TMR61          = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
  TIMER_CTRL10_TMR10CLK_TMR70          = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
  TIMER_CTRL10_TMR10CLK_TMR71          = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
  TIMER_CTRL10_TMR10CLK_TMR80          = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
  TIMER_CTRL10_TMR10CLK_TMR81          = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
  TIMER_CTRL10_TMR10CLK_TMR90          = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
  TIMER_CTRL10_TMR10CLK_TMR91          = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
  TIMER_CTRL10_TMR10CLK_TMR100         = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
  TIMER_CTRL10_TMR10CLK_TMR101         = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
  TIMER_CTRL10_TMR10CLK_TMR110         = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
  TIMER_CTRL10_TMR10CLK_TMR111         = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
  TIMER_CTRL10_TMR10CLK_TMR120         = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
  TIMER_CTRL10_TMR10CLK_TMR121         = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
  TIMER_CTRL10_TMR10CLK_TMR130         = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
  TIMER_CTRL10_TMR10CLK_TMR131         = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
  TIMER_CTRL10_TMR10CLK_TMR140         = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
  TIMER_CTRL10_TMR10CLK_TMR141         = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
  TIMER_CTRL10_TMR10CLK_TMR150         = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
  TIMER_CTRL10_TMR10CLK_TMR151         = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
  TIMER_CTRL10_TMR10CLK_GPIO0          = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
  TIMER_CTRL10_TMR10CLK_GPIO63         = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
  TIMER_CTRL10_TMR10CLK_GPIO95         = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
  TIMER_CTRL10_TMR10CLK_GPIO127        = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
} TIMER_CTRL10_TMR10CLK_Enum;

/* ==============================================  TIMER CTRL10 TMR10FN [4..7]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL10_TMR10FN                                                      */
  TIMER_CTRL10_TMR10FN_EDGE            = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
                                                     value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
                                                     to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
  TIMER_CTRL10_TMR10FN_UPCOUNT         = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
                                                     CMP. OUT[0]/OUT[1] is pulsed for one source clock period
                                                     when TIMER matches CMP0/CMP1 respectively. Timer repeats
                                                     for TMR_LMT iterations.                                                   */
  TIMER_CTRL10_TMR10FN_PWM             = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
                                                     clock pulse. CMP1 dictates the low phase of the output
                                                     and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
  TIMER_CTRL10_TMR10FN_SINGLEPATTERN   = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
                                                     LMT field specifies length of pattern. When LMT GT 32 OUT0
                                                     and OUT1 is the same 64-bit pattern consisting of concatenated
                                                     CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
                                                     Both OUT0 and OUT1 can be inverted individually applications
                                                     with POL0/POL1 = 0x1.                                                     */
  TIMER_CTRL10_TMR10FN_REPEATPATTERN   = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
                                                     pattern repeats after reaching LMT.                                       */
} TIMER_CTRL10_TMR10FN_Enum;

/* =============================================  TIMER CTRL10 TMR10POL1 [3..3]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL10_TMR10POL1                                                    */
  TIMER_CTRL10_TMR10POL1_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR10OUT1 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL10_TMR10POL1_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR10OUT1 pin is the inverse
                                                     of the timer output.                                                      */
} TIMER_CTRL10_TMR10POL1_Enum;

/* =============================================  TIMER CTRL10 TMR10POL0 [2..2]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL10_TMR10POL0                                                    */
  TIMER_CTRL10_TMR10POL0_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR10OUT0 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL10_TMR10POL0_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR10OUT0 pin is the inverse
                                                     of the timer output.                                                      */
} TIMER_CTRL10_TMR10POL0_Enum;

/* =============================================  TIMER CTRL10 TMR10CLR [1..1]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL10_TMR10CLR                                                     */
  TIMER_CTRL10_TMR10CLR_CLEAR          = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
                                                     cleared to its reset state # (0 for count up counter, CMP0
                                                     for down counter)                                                         */
  TIMER_CTRL10_TMR10CLR_DEFAULT        = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
} TIMER_CTRL10_TMR10CLR_Enum;

/* ==============================================  TIMER CTRL10 TMR10EN [0..0]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL10_TMR10EN                                                      */
  TIMER_CTRL10_TMR10EN_DIS             = 0,     /*!< DIS : Counter/Timer 10 Disable.                                           */
  TIMER_CTRL10_TMR10EN_EN              = 1,     /*!< EN : Counter/Timer 10 Enable.                                             */
} TIMER_CTRL10_TMR10EN_Enum;

/* ========================================================  TIMER10  ======================================================== */
/* =======================================================  TMR10CMP0  ======================================================= */
/* =======================================================  TMR10CMP1  ======================================================= */
/* ========================================================  MODE10  ========================================================= */
/* ===========================================  TIMER MODE10 TMR10TRIGSEL [8..15]  =========================================== */
typedef enum {                                  /*!< TIMER_MODE10_TMR10TRIGSEL                                                 */
  TIMER_MODE10_TMR10TRIGSEL_TMR00      = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR01      = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR10      = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR11      = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR20      = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR21      = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR30      = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR31      = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR40      = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR41      = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR50      = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR51      = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR60      = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR61      = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR70      = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR71      = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR80      = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR81      = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR90      = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR91      = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
  TIMER_MODE10_TMR10TRIGSEL_TMR100     = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
  TIMER_MODE10_TMR10TRIGSEL_TMR101     = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
  TIMER_MODE10_TMR10TRIGSEL_TMR110     = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
  TIMER_MODE10_TMR10TRIGSEL_TMR111     = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
  TIMER_MODE10_TMR10TRIGSEL_TMR120     = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
  TIMER_MODE10_TMR10TRIGSEL_TMR121     = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
  TIMER_MODE10_TMR10TRIGSEL_TMR130     = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
  TIMER_MODE10_TMR10TRIGSEL_TMR131     = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
  TIMER_MODE10_TMR10TRIGSEL_TMR140     = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
  TIMER_MODE10_TMR10TRIGSEL_TMR141     = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
  TIMER_MODE10_TMR10TRIGSEL_TMR150     = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
  TIMER_MODE10_TMR10TRIGSEL_TMR151     = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
  TIMER_MODE10_TMR10TRIGSEL_GPIO0      = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
  TIMER_MODE10_TMR10TRIGSEL_GPIO127    = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
} TIMER_MODE10_TMR10TRIGSEL_Enum;

/* ======================================================  TMR10LMTVAL  ====================================================== */
/* ========================================================  CTRL11  ========================================================= */
/* ===========================================  TIMER CTRL11 TMR11TMODE [16..17]  ============================================ */
typedef enum {                                  /*!< TIMER_CTRL11_TMR11TMODE                                                   */
  TIMER_CTRL11_TMR11TMODE_DIS          = 0,     /*!< DIS : Trigger not enabled                                                 */
  TIMER_CTRL11_TMR11TMODE_RISE         = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
  TIMER_CTRL11_TMR11TMODE_FALL         = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
  TIMER_CTRL11_TMR11TMODE_BOTH         = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
} TIMER_CTRL11_TMR11TMODE_Enum;

/* =============================================  TIMER CTRL11 TMR11CLK [8..15]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL11_TMR11CLK                                                     */
  TIMER_CTRL11_TMR11CLK_HFRC_DIV4      = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
  TIMER_CTRL11_TMR11CLK_HFRC_DIV16     = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
  TIMER_CTRL11_TMR11CLK_HFRC_DIV64     = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
  TIMER_CTRL11_TMR11CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
  TIMER_CTRL11_TMR11CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
  TIMER_CTRL11_TMR11CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
  TIMER_CTRL11_TMR11CLK_LFRC           = 6,     /*!< LFRC : Clock source is LFRC                                               */
  TIMER_CTRL11_TMR11CLK_LFRC_DIV2      = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
  TIMER_CTRL11_TMR11CLK_LFRC_DIV32     = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
  TIMER_CTRL11_TMR11CLK_LFRC_DIV1K     = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
  TIMER_CTRL11_TMR11CLK_XT             = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
  TIMER_CTRL11_TMR11CLK_XT_DIV2        = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
  TIMER_CTRL11_TMR11CLK_XT_DIV4        = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
  TIMER_CTRL11_TMR11CLK_XT_DIV8        = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
  TIMER_CTRL11_TMR11CLK_XT_DIV16       = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
  TIMER_CTRL11_TMR11CLK_XT_DIV32       = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
  TIMER_CTRL11_TMR11CLK_XT_DIV128      = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
  TIMER_CTRL11_TMR11CLK_RTC_100HZ      = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
  TIMER_CTRL11_TMR11CLK_BUCKC          = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
  TIMER_CTRL11_TMR11CLK_BUCKF          = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
  TIMER_CTRL11_TMR11CLK_BUCKS          = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
  TIMER_CTRL11_TMR11CLK_BUCKC_LV       = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
  TIMER_CTRL11_TMR11CLK_TMR00          = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
  TIMER_CTRL11_TMR11CLK_TMR01          = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
  TIMER_CTRL11_TMR11CLK_TMR10          = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
  TIMER_CTRL11_TMR11CLK_TMR11          = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
  TIMER_CTRL11_TMR11CLK_TMR20          = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
  TIMER_CTRL11_TMR11CLK_TMR21          = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
  TIMER_CTRL11_TMR11CLK_TMR30          = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
  TIMER_CTRL11_TMR11CLK_TMR31          = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
  TIMER_CTRL11_TMR11CLK_TMR40          = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
  TIMER_CTRL11_TMR11CLK_TMR41          = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
  TIMER_CTRL11_TMR11CLK_TMR50          = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
  TIMER_CTRL11_TMR11CLK_TMR51          = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
  TIMER_CTRL11_TMR11CLK_TMR60          = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
  TIMER_CTRL11_TMR11CLK_TMR61          = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
  TIMER_CTRL11_TMR11CLK_TMR70          = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
  TIMER_CTRL11_TMR11CLK_TMR71          = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
  TIMER_CTRL11_TMR11CLK_TMR80          = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
  TIMER_CTRL11_TMR11CLK_TMR81          = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
  TIMER_CTRL11_TMR11CLK_TMR90          = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
  TIMER_CTRL11_TMR11CLK_TMR91          = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
  TIMER_CTRL11_TMR11CLK_TMR100         = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
  TIMER_CTRL11_TMR11CLK_TMR101         = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
  TIMER_CTRL11_TMR11CLK_TMR110         = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
  TIMER_CTRL11_TMR11CLK_TMR111         = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
  TIMER_CTRL11_TMR11CLK_TMR120         = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
  TIMER_CTRL11_TMR11CLK_TMR121         = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
  TIMER_CTRL11_TMR11CLK_TMR130         = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
  TIMER_CTRL11_TMR11CLK_TMR131         = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
  TIMER_CTRL11_TMR11CLK_TMR140         = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
  TIMER_CTRL11_TMR11CLK_TMR141         = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
  TIMER_CTRL11_TMR11CLK_TMR150         = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
  TIMER_CTRL11_TMR11CLK_TMR151         = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
  TIMER_CTRL11_TMR11CLK_GPIO0          = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
  TIMER_CTRL11_TMR11CLK_GPIO63         = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
  TIMER_CTRL11_TMR11CLK_GPIO95         = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
  TIMER_CTRL11_TMR11CLK_GPIO127        = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
} TIMER_CTRL11_TMR11CLK_Enum;

/* ==============================================  TIMER CTRL11 TMR11FN [4..7]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL11_TMR11FN                                                      */
  TIMER_CTRL11_TMR11FN_EDGE            = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
                                                     value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
                                                     to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
  TIMER_CTRL11_TMR11FN_UPCOUNT         = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
                                                     CMP. OUT[0]/OUT[1] is pulsed for one source clock period
                                                     when TIMER matches CMP0/CMP1 respectively. Timer repeats
                                                     for TMR_LMT iterations.                                                   */
  TIMER_CTRL11_TMR11FN_PWM             = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
                                                     clock pulse. CMP1 dictates the low phase of the output
                                                     and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
  TIMER_CTRL11_TMR11FN_SINGLEPATTERN   = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
                                                     LMT field specifies length of pattern. When LMT GT 32 OUT0
                                                     and OUT1 is the same 64-bit pattern consisting of concatenated
                                                     CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
                                                     Both OUT0 and OUT1 can be inverted individually applications
                                                     with POL0/POL1 = 0x1.                                                     */
  TIMER_CTRL11_TMR11FN_REPEATPATTERN   = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
                                                     pattern repeats after reaching LMT.                                       */
} TIMER_CTRL11_TMR11FN_Enum;

/* =============================================  TIMER CTRL11 TMR11POL1 [3..3]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL11_TMR11POL1                                                    */
  TIMER_CTRL11_TMR11POL1_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR11OUT1 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL11_TMR11POL1_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR11OUT1 pin is the inverse
                                                     of the timer output.                                                      */
} TIMER_CTRL11_TMR11POL1_Enum;

/* =============================================  TIMER CTRL11 TMR11POL0 [2..2]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL11_TMR11POL0                                                    */
  TIMER_CTRL11_TMR11POL0_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR11OUT0 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL11_TMR11POL0_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR11OUT0 pin is the inverse
                                                     of the timer output.                                                      */
} TIMER_CTRL11_TMR11POL0_Enum;

/* =============================================  TIMER CTRL11 TMR11CLR [1..1]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL11_TMR11CLR                                                     */
  TIMER_CTRL11_TMR11CLR_CLEAR          = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
                                                     cleared to its reset state # (0 for count up counter, CMP0
                                                     for down counter)                                                         */
  TIMER_CTRL11_TMR11CLR_DEFAULT        = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
} TIMER_CTRL11_TMR11CLR_Enum;

/* ==============================================  TIMER CTRL11 TMR11EN [0..0]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL11_TMR11EN                                                      */
  TIMER_CTRL11_TMR11EN_DIS             = 0,     /*!< DIS : Counter/Timer 11 Disable.                                           */
  TIMER_CTRL11_TMR11EN_EN              = 1,     /*!< EN : Counter/Timer 11 Enable.                                             */
} TIMER_CTRL11_TMR11EN_Enum;

/* ========================================================  TIMER11  ======================================================== */
/* =======================================================  TMR11CMP0  ======================================================= */
/* =======================================================  TMR11CMP1  ======================================================= */
/* ========================================================  MODE11  ========================================================= */
/* ===========================================  TIMER MODE11 TMR11TRIGSEL [8..15]  =========================================== */
typedef enum {                                  /*!< TIMER_MODE11_TMR11TRIGSEL                                                 */
  TIMER_MODE11_TMR11TRIGSEL_TMR00      = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR01      = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR10      = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR11      = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR20      = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR21      = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR30      = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR31      = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR40      = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR41      = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR50      = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR51      = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR60      = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR61      = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR70      = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR71      = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR80      = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR81      = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR90      = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR91      = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
  TIMER_MODE11_TMR11TRIGSEL_TMR100     = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
  TIMER_MODE11_TMR11TRIGSEL_TMR101     = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
  TIMER_MODE11_TMR11TRIGSEL_TMR110     = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
  TIMER_MODE11_TMR11TRIGSEL_TMR111     = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
  TIMER_MODE11_TMR11TRIGSEL_TMR120     = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
  TIMER_MODE11_TMR11TRIGSEL_TMR121     = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
  TIMER_MODE11_TMR11TRIGSEL_TMR130     = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
  TIMER_MODE11_TMR11TRIGSEL_TMR131     = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
  TIMER_MODE11_TMR11TRIGSEL_TMR140     = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
  TIMER_MODE11_TMR11TRIGSEL_TMR141     = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
  TIMER_MODE11_TMR11TRIGSEL_TMR150     = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
  TIMER_MODE11_TMR11TRIGSEL_TMR151     = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
  TIMER_MODE11_TMR11TRIGSEL_GPIO0      = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
  TIMER_MODE11_TMR11TRIGSEL_GPIO127    = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
} TIMER_MODE11_TMR11TRIGSEL_Enum;

/* ======================================================  TMR11LMTVAL  ====================================================== */
/* ========================================================  CTRL12  ========================================================= */
/* ===========================================  TIMER CTRL12 TMR12TMODE [16..17]  ============================================ */
typedef enum {                                  /*!< TIMER_CTRL12_TMR12TMODE                                                   */
  TIMER_CTRL12_TMR12TMODE_DIS          = 0,     /*!< DIS : Trigger not enabled                                                 */
  TIMER_CTRL12_TMR12TMODE_RISE         = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
  TIMER_CTRL12_TMR12TMODE_FALL         = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
  TIMER_CTRL12_TMR12TMODE_BOTH         = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
} TIMER_CTRL12_TMR12TMODE_Enum;

/* =============================================  TIMER CTRL12 TMR12CLK [8..15]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL12_TMR12CLK                                                     */
  TIMER_CTRL12_TMR12CLK_HFRC_DIV4      = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
  TIMER_CTRL12_TMR12CLK_HFRC_DIV16     = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
  TIMER_CTRL12_TMR12CLK_HFRC_DIV64     = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
  TIMER_CTRL12_TMR12CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
  TIMER_CTRL12_TMR12CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
  TIMER_CTRL12_TMR12CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
  TIMER_CTRL12_TMR12CLK_LFRC           = 6,     /*!< LFRC : Clock source is LFRC                                               */
  TIMER_CTRL12_TMR12CLK_LFRC_DIV2      = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
  TIMER_CTRL12_TMR12CLK_LFRC_DIV32     = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
  TIMER_CTRL12_TMR12CLK_LFRC_DIV1K     = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
  TIMER_CTRL12_TMR12CLK_XT             = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
  TIMER_CTRL12_TMR12CLK_XT_DIV2        = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
  TIMER_CTRL12_TMR12CLK_XT_DIV4        = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
  TIMER_CTRL12_TMR12CLK_XT_DIV8        = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
  TIMER_CTRL12_TMR12CLK_XT_DIV16       = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
  TIMER_CTRL12_TMR12CLK_XT_DIV32       = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
  TIMER_CTRL12_TMR12CLK_XT_DIV128      = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
  TIMER_CTRL12_TMR12CLK_RTC_100HZ      = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
  TIMER_CTRL12_TMR12CLK_BUCKC          = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
  TIMER_CTRL12_TMR12CLK_BUCKF          = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
  TIMER_CTRL12_TMR12CLK_BUCKS          = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
  TIMER_CTRL12_TMR12CLK_BUCKC_LV       = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
  TIMER_CTRL12_TMR12CLK_TMR00          = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
  TIMER_CTRL12_TMR12CLK_TMR01          = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
  TIMER_CTRL12_TMR12CLK_TMR10          = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
  TIMER_CTRL12_TMR12CLK_TMR11          = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
  TIMER_CTRL12_TMR12CLK_TMR20          = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
  TIMER_CTRL12_TMR12CLK_TMR21          = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
  TIMER_CTRL12_TMR12CLK_TMR30          = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
  TIMER_CTRL12_TMR12CLK_TMR31          = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
  TIMER_CTRL12_TMR12CLK_TMR40          = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
  TIMER_CTRL12_TMR12CLK_TMR41          = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
  TIMER_CTRL12_TMR12CLK_TMR50          = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
  TIMER_CTRL12_TMR12CLK_TMR51          = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
  TIMER_CTRL12_TMR12CLK_TMR60          = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
  TIMER_CTRL12_TMR12CLK_TMR61          = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
  TIMER_CTRL12_TMR12CLK_TMR70          = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
  TIMER_CTRL12_TMR12CLK_TMR71          = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
  TIMER_CTRL12_TMR12CLK_TMR80          = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
  TIMER_CTRL12_TMR12CLK_TMR81          = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
  TIMER_CTRL12_TMR12CLK_TMR90          = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
  TIMER_CTRL12_TMR12CLK_TMR91          = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
  TIMER_CTRL12_TMR12CLK_TMR100         = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
  TIMER_CTRL12_TMR12CLK_TMR101         = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
  TIMER_CTRL12_TMR12CLK_TMR110         = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
  TIMER_CTRL12_TMR12CLK_TMR111         = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
  TIMER_CTRL12_TMR12CLK_TMR120         = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
  TIMER_CTRL12_TMR12CLK_TMR121         = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
  TIMER_CTRL12_TMR12CLK_TMR130         = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
  TIMER_CTRL12_TMR12CLK_TMR131         = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
  TIMER_CTRL12_TMR12CLK_TMR140         = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
  TIMER_CTRL12_TMR12CLK_TMR141         = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
  TIMER_CTRL12_TMR12CLK_TMR150         = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
  TIMER_CTRL12_TMR12CLK_TMR151         = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
  TIMER_CTRL12_TMR12CLK_GPIO0          = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
  TIMER_CTRL12_TMR12CLK_GPIO63         = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
  TIMER_CTRL12_TMR12CLK_GPIO95         = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
  TIMER_CTRL12_TMR12CLK_GPIO127        = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
} TIMER_CTRL12_TMR12CLK_Enum;

/* ==============================================  TIMER CTRL12 TMR12FN [4..7]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL12_TMR12FN                                                      */
  TIMER_CTRL12_TMR12FN_EDGE            = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
                                                     value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
                                                     to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
  TIMER_CTRL12_TMR12FN_UPCOUNT         = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
                                                     CMP. OUT[0]/OUT[1] is pulsed for one source clock period
                                                     when TIMER matches CMP0/CMP1 respectively. Timer repeats
                                                     for TMR_LMT iterations.                                                   */
  TIMER_CTRL12_TMR12FN_PWM             = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
                                                     clock pulse. CMP1 dictates the low phase of the output
                                                     and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
  TIMER_CTRL12_TMR12FN_SINGLEPATTERN   = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
                                                     LMT field specifies length of pattern. When LMT GT 32 OUT0
                                                     and OUT1 is the same 64-bit pattern consisting of concatenated
                                                     CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
                                                     Both OUT0 and OUT1 can be inverted individually applications
                                                     with POL0/POL1 = 0x1.                                                     */
  TIMER_CTRL12_TMR12FN_REPEATPATTERN   = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
                                                     pattern repeats after reaching LMT.                                       */
} TIMER_CTRL12_TMR12FN_Enum;

/* =============================================  TIMER CTRL12 TMR12POL1 [3..3]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL12_TMR12POL1                                                    */
  TIMER_CTRL12_TMR12POL1_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR12OUT1 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL12_TMR12POL1_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR12OUT1 pin is the inverse
                                                     of the timer output.                                                      */
} TIMER_CTRL12_TMR12POL1_Enum;

/* =============================================  TIMER CTRL12 TMR12POL0 [2..2]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL12_TMR12POL0                                                    */
  TIMER_CTRL12_TMR12POL0_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR12OUT0 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL12_TMR12POL0_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR12OUT0 pin is the inverse
                                                     of the timer output.                                                      */
} TIMER_CTRL12_TMR12POL0_Enum;

/* =============================================  TIMER CTRL12 TMR12CLR [1..1]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL12_TMR12CLR                                                     */
  TIMER_CTRL12_TMR12CLR_CLEAR          = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
                                                     cleared to its reset state # (0 for count up counter, CMP0
                                                     for down counter)                                                         */
  TIMER_CTRL12_TMR12CLR_DEFAULT        = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
} TIMER_CTRL12_TMR12CLR_Enum;

/* ==============================================  TIMER CTRL12 TMR12EN [0..0]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL12_TMR12EN                                                      */
  TIMER_CTRL12_TMR12EN_DIS             = 0,     /*!< DIS : Counter/Timer 12 Disable.                                           */
  TIMER_CTRL12_TMR12EN_EN              = 1,     /*!< EN : Counter/Timer 12 Enable.                                             */
} TIMER_CTRL12_TMR12EN_Enum;

/* ========================================================  TIMER12  ======================================================== */
/* =======================================================  TMR12CMP0  ======================================================= */
/* =======================================================  TMR12CMP1  ======================================================= */
/* ========================================================  MODE12  ========================================================= */
/* ===========================================  TIMER MODE12 TMR12TRIGSEL [8..15]  =========================================== */
typedef enum {                                  /*!< TIMER_MODE12_TMR12TRIGSEL                                                 */
  TIMER_MODE12_TMR12TRIGSEL_TMR00      = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR01      = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR10      = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR11      = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR20      = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR21      = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR30      = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR31      = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR40      = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR41      = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR50      = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR51      = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR60      = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR61      = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR70      = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR71      = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR80      = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR81      = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR90      = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR91      = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
  TIMER_MODE12_TMR12TRIGSEL_TMR100     = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
  TIMER_MODE12_TMR12TRIGSEL_TMR101     = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
  TIMER_MODE12_TMR12TRIGSEL_TMR110     = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
  TIMER_MODE12_TMR12TRIGSEL_TMR111     = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
  TIMER_MODE12_TMR12TRIGSEL_TMR120     = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
  TIMER_MODE12_TMR12TRIGSEL_TMR121     = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
  TIMER_MODE12_TMR12TRIGSEL_TMR130     = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
  TIMER_MODE12_TMR12TRIGSEL_TMR131     = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
  TIMER_MODE12_TMR12TRIGSEL_TMR140     = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
  TIMER_MODE12_TMR12TRIGSEL_TMR141     = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
  TIMER_MODE12_TMR12TRIGSEL_TMR150     = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
  TIMER_MODE12_TMR12TRIGSEL_TMR151     = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
  TIMER_MODE12_TMR12TRIGSEL_GPIO0      = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
  TIMER_MODE12_TMR12TRIGSEL_GPIO127    = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
} TIMER_MODE12_TMR12TRIGSEL_Enum;

/* ======================================================  TMR12LMTVAL  ====================================================== */
/* ========================================================  CTRL13  ========================================================= */
/* ===========================================  TIMER CTRL13 TMR13TMODE [16..17]  ============================================ */
typedef enum {                                  /*!< TIMER_CTRL13_TMR13TMODE                                                   */
  TIMER_CTRL13_TMR13TMODE_DIS          = 0,     /*!< DIS : Trigger not enabled                                                 */
  TIMER_CTRL13_TMR13TMODE_RISE         = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
  TIMER_CTRL13_TMR13TMODE_FALL         = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
  TIMER_CTRL13_TMR13TMODE_BOTH         = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
} TIMER_CTRL13_TMR13TMODE_Enum;

/* =============================================  TIMER CTRL13 TMR13CLK [8..15]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL13_TMR13CLK                                                     */
  TIMER_CTRL13_TMR13CLK_HFRC_DIV4      = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
  TIMER_CTRL13_TMR13CLK_HFRC_DIV16     = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
  TIMER_CTRL13_TMR13CLK_HFRC_DIV64     = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
  TIMER_CTRL13_TMR13CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
  TIMER_CTRL13_TMR13CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
  TIMER_CTRL13_TMR13CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
  TIMER_CTRL13_TMR13CLK_LFRC           = 6,     /*!< LFRC : Clock source is LFRC                                               */
  TIMER_CTRL13_TMR13CLK_LFRC_DIV2      = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
  TIMER_CTRL13_TMR13CLK_LFRC_DIV32     = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
  TIMER_CTRL13_TMR13CLK_LFRC_DIV1K     = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
  TIMER_CTRL13_TMR13CLK_XT             = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
  TIMER_CTRL13_TMR13CLK_XT_DIV2        = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
  TIMER_CTRL13_TMR13CLK_XT_DIV4        = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
  TIMER_CTRL13_TMR13CLK_XT_DIV8        = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
  TIMER_CTRL13_TMR13CLK_XT_DIV16       = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
  TIMER_CTRL13_TMR13CLK_XT_DIV32       = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
  TIMER_CTRL13_TMR13CLK_XT_DIV128      = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
  TIMER_CTRL13_TMR13CLK_RTC_100HZ      = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
  TIMER_CTRL13_TMR13CLK_BUCKC          = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
  TIMER_CTRL13_TMR13CLK_BUCKF          = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
  TIMER_CTRL13_TMR13CLK_BUCKS          = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
  TIMER_CTRL13_TMR13CLK_BUCKC_LV       = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
  TIMER_CTRL13_TMR13CLK_TMR00          = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
  TIMER_CTRL13_TMR13CLK_TMR01          = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
  TIMER_CTRL13_TMR13CLK_TMR10          = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
  TIMER_CTRL13_TMR13CLK_TMR11          = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
  TIMER_CTRL13_TMR13CLK_TMR20          = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
  TIMER_CTRL13_TMR13CLK_TMR21          = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
  TIMER_CTRL13_TMR13CLK_TMR30          = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
  TIMER_CTRL13_TMR13CLK_TMR31          = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
  TIMER_CTRL13_TMR13CLK_TMR40          = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
  TIMER_CTRL13_TMR13CLK_TMR41          = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
  TIMER_CTRL13_TMR13CLK_TMR50          = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
  TIMER_CTRL13_TMR13CLK_TMR51          = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
  TIMER_CTRL13_TMR13CLK_TMR60          = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
  TIMER_CTRL13_TMR13CLK_TMR61          = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
  TIMER_CTRL13_TMR13CLK_TMR70          = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
  TIMER_CTRL13_TMR13CLK_TMR71          = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
  TIMER_CTRL13_TMR13CLK_TMR80          = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
  TIMER_CTRL13_TMR13CLK_TMR81          = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
  TIMER_CTRL13_TMR13CLK_TMR90          = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
  TIMER_CTRL13_TMR13CLK_TMR91          = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
  TIMER_CTRL13_TMR13CLK_TMR100         = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
  TIMER_CTRL13_TMR13CLK_TMR101         = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
  TIMER_CTRL13_TMR13CLK_TMR110         = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
  TIMER_CTRL13_TMR13CLK_TMR111         = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
  TIMER_CTRL13_TMR13CLK_TMR120         = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
  TIMER_CTRL13_TMR13CLK_TMR121         = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
  TIMER_CTRL13_TMR13CLK_TMR130         = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
  TIMER_CTRL13_TMR13CLK_TMR131         = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
  TIMER_CTRL13_TMR13CLK_TMR140         = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
  TIMER_CTRL13_TMR13CLK_TMR141         = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
  TIMER_CTRL13_TMR13CLK_TMR150         = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
  TIMER_CTRL13_TMR13CLK_TMR151         = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
  TIMER_CTRL13_TMR13CLK_GPIO0          = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
  TIMER_CTRL13_TMR13CLK_GPIO63         = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
  TIMER_CTRL13_TMR13CLK_GPIO95         = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
  TIMER_CTRL13_TMR13CLK_GPIO127        = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
} TIMER_CTRL13_TMR13CLK_Enum;

/* ==============================================  TIMER CTRL13 TMR13FN [4..7]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL13_TMR13FN                                                      */
  TIMER_CTRL13_TMR13FN_EDGE            = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
                                                     value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
                                                     to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
  TIMER_CTRL13_TMR13FN_UPCOUNT         = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
                                                     CMP. OUT[0]/OUT[1] is pulsed for one source clock period
                                                     when TIMER matches CMP0/CMP1 respectively. Timer repeats
                                                     for TMR_LMT iterations.                                                   */
  TIMER_CTRL13_TMR13FN_PWM             = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
                                                     clock pulse. CMP1 dictates the low phase of the output
                                                     and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
  TIMER_CTRL13_TMR13FN_SINGLEPATTERN   = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
                                                     LMT field specifies length of pattern. When LMT GT 32 OUT0
                                                     and OUT1 is the same 64-bit pattern consisting of concatenated
                                                     CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
                                                     Both OUT0 and OUT1 can be inverted individually applications
                                                     with POL0/POL1 = 0x1.                                                     */
  TIMER_CTRL13_TMR13FN_REPEATPATTERN   = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
                                                     pattern repeats after reaching LMT.                                       */
} TIMER_CTRL13_TMR13FN_Enum;

/* =============================================  TIMER CTRL13 TMR13POL1 [3..3]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL13_TMR13POL1                                                    */
  TIMER_CTRL13_TMR13POL1_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR13OUT1 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL13_TMR13POL1_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR13OUT1 pin is the inverse
                                                     of the timer output.                                                      */
} TIMER_CTRL13_TMR13POL1_Enum;

/* =============================================  TIMER CTRL13 TMR13POL0 [2..2]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL13_TMR13POL0                                                    */
  TIMER_CTRL13_TMR13POL0_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR13OUT0 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL13_TMR13POL0_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR13OUT0 pin is the inverse
                                                     of the timer output.                                                      */
} TIMER_CTRL13_TMR13POL0_Enum;

/* =============================================  TIMER CTRL13 TMR13CLR [1..1]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL13_TMR13CLR                                                     */
  TIMER_CTRL13_TMR13CLR_CLEAR          = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
                                                     cleared to its reset state # (0 for count up counter, CMP0
                                                     for down counter)                                                         */
  TIMER_CTRL13_TMR13CLR_DEFAULT        = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
} TIMER_CTRL13_TMR13CLR_Enum;

/* ==============================================  TIMER CTRL13 TMR13EN [0..0]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL13_TMR13EN                                                      */
  TIMER_CTRL13_TMR13EN_DIS             = 0,     /*!< DIS : Counter/Timer 13 Disable.                                           */
  TIMER_CTRL13_TMR13EN_EN              = 1,     /*!< EN : Counter/Timer 13 Enable.                                             */
} TIMER_CTRL13_TMR13EN_Enum;

/* ========================================================  TIMER13  ======================================================== */
/* =======================================================  TMR13CMP0  ======================================================= */
/* =======================================================  TMR13CMP1  ======================================================= */
/* ========================================================  MODE13  ========================================================= */
/* ===========================================  TIMER MODE13 TMR13TRIGSEL [8..15]  =========================================== */
typedef enum {                                  /*!< TIMER_MODE13_TMR13TRIGSEL                                                 */
  TIMER_MODE13_TMR13TRIGSEL_TMR00      = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR01      = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR10      = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR11      = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR20      = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR21      = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR30      = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR31      = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR40      = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR41      = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR50      = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR51      = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR60      = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR61      = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR70      = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR71      = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR80      = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR81      = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR90      = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR91      = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
  TIMER_MODE13_TMR13TRIGSEL_TMR100     = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
  TIMER_MODE13_TMR13TRIGSEL_TMR101     = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
  TIMER_MODE13_TMR13TRIGSEL_TMR110     = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
  TIMER_MODE13_TMR13TRIGSEL_TMR111     = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
  TIMER_MODE13_TMR13TRIGSEL_TMR120     = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
  TIMER_MODE13_TMR13TRIGSEL_TMR121     = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
  TIMER_MODE13_TMR13TRIGSEL_TMR130     = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
  TIMER_MODE13_TMR13TRIGSEL_TMR131     = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
  TIMER_MODE13_TMR13TRIGSEL_TMR140     = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
  TIMER_MODE13_TMR13TRIGSEL_TMR141     = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
  TIMER_MODE13_TMR13TRIGSEL_TMR150     = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
  TIMER_MODE13_TMR13TRIGSEL_TMR151     = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
  TIMER_MODE13_TMR13TRIGSEL_GPIO0      = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
  TIMER_MODE13_TMR13TRIGSEL_GPIO127    = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
} TIMER_MODE13_TMR13TRIGSEL_Enum;

/* ======================================================  TMR13LMTVAL  ====================================================== */
/* ========================================================  CTRL14  ========================================================= */
/* ===========================================  TIMER CTRL14 TMR14TMODE [16..17]  ============================================ */
typedef enum {                                  /*!< TIMER_CTRL14_TMR14TMODE                                                   */
  TIMER_CTRL14_TMR14TMODE_DIS          = 0,     /*!< DIS : Trigger not enabled                                                 */
  TIMER_CTRL14_TMR14TMODE_RISE         = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
  TIMER_CTRL14_TMR14TMODE_FALL         = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
  TIMER_CTRL14_TMR14TMODE_BOTH         = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
} TIMER_CTRL14_TMR14TMODE_Enum;

/* =============================================  TIMER CTRL14 TMR14CLK [8..15]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL14_TMR14CLK                                                     */
  TIMER_CTRL14_TMR14CLK_HFRC_DIV4      = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
  TIMER_CTRL14_TMR14CLK_HFRC_DIV16     = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
  TIMER_CTRL14_TMR14CLK_HFRC_DIV64     = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
  TIMER_CTRL14_TMR14CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
  TIMER_CTRL14_TMR14CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
  TIMER_CTRL14_TMR14CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
  TIMER_CTRL14_TMR14CLK_LFRC           = 6,     /*!< LFRC : Clock source is LFRC                                               */
  TIMER_CTRL14_TMR14CLK_LFRC_DIV2      = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
  TIMER_CTRL14_TMR14CLK_LFRC_DIV32     = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
  TIMER_CTRL14_TMR14CLK_LFRC_DIV1K     = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
  TIMER_CTRL14_TMR14CLK_XT             = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
  TIMER_CTRL14_TMR14CLK_XT_DIV2        = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
  TIMER_CTRL14_TMR14CLK_XT_DIV4        = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
  TIMER_CTRL14_TMR14CLK_XT_DIV8        = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
  TIMER_CTRL14_TMR14CLK_XT_DIV16       = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
  TIMER_CTRL14_TMR14CLK_XT_DIV32       = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
  TIMER_CTRL14_TMR14CLK_XT_DIV128      = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
  TIMER_CTRL14_TMR14CLK_RTC_100HZ      = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
  TIMER_CTRL14_TMR14CLK_BUCKC          = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
  TIMER_CTRL14_TMR14CLK_BUCKF          = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
  TIMER_CTRL14_TMR14CLK_BUCKS          = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
  TIMER_CTRL14_TMR14CLK_BUCKC_LV       = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
  TIMER_CTRL14_TMR14CLK_TMR00          = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
  TIMER_CTRL14_TMR14CLK_TMR01          = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
  TIMER_CTRL14_TMR14CLK_TMR10          = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
  TIMER_CTRL14_TMR14CLK_TMR11          = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
  TIMER_CTRL14_TMR14CLK_TMR20          = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
  TIMER_CTRL14_TMR14CLK_TMR21          = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
  TIMER_CTRL14_TMR14CLK_TMR30          = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
  TIMER_CTRL14_TMR14CLK_TMR31          = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
  TIMER_CTRL14_TMR14CLK_TMR40          = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
  TIMER_CTRL14_TMR14CLK_TMR41          = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
  TIMER_CTRL14_TMR14CLK_TMR50          = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
  TIMER_CTRL14_TMR14CLK_TMR51          = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
  TIMER_CTRL14_TMR14CLK_TMR60          = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
  TIMER_CTRL14_TMR14CLK_TMR61          = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
  TIMER_CTRL14_TMR14CLK_TMR70          = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
  TIMER_CTRL14_TMR14CLK_TMR71          = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
  TIMER_CTRL14_TMR14CLK_TMR80          = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
  TIMER_CTRL14_TMR14CLK_TMR81          = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
  TIMER_CTRL14_TMR14CLK_TMR90          = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
  TIMER_CTRL14_TMR14CLK_TMR91          = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
  TIMER_CTRL14_TMR14CLK_TMR100         = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
  TIMER_CTRL14_TMR14CLK_TMR101         = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
  TIMER_CTRL14_TMR14CLK_TMR110         = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
  TIMER_CTRL14_TMR14CLK_TMR111         = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
  TIMER_CTRL14_TMR14CLK_TMR120         = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
  TIMER_CTRL14_TMR14CLK_TMR121         = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
  TIMER_CTRL14_TMR14CLK_TMR130         = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
  TIMER_CTRL14_TMR14CLK_TMR131         = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
  TIMER_CTRL14_TMR14CLK_TMR140         = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
  TIMER_CTRL14_TMR14CLK_TMR141         = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
  TIMER_CTRL14_TMR14CLK_TMR150         = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
  TIMER_CTRL14_TMR14CLK_TMR151         = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
  TIMER_CTRL14_TMR14CLK_GPIO0          = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
  TIMER_CTRL14_TMR14CLK_GPIO63         = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
  TIMER_CTRL14_TMR14CLK_GPIO95         = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
  TIMER_CTRL14_TMR14CLK_GPIO127        = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
} TIMER_CTRL14_TMR14CLK_Enum;

/* ==============================================  TIMER CTRL14 TMR14FN [4..7]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL14_TMR14FN                                                      */
  TIMER_CTRL14_TMR14FN_EDGE            = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
                                                     value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
                                                     to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
  TIMER_CTRL14_TMR14FN_UPCOUNT         = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
                                                     CMP. OUT[0]/OUT[1] is pulsed for one source clock period
                                                     when TIMER matches CMP0/CMP1 respectively. Timer repeats
                                                     for TMR_LMT iterations.                                                   */
  TIMER_CTRL14_TMR14FN_PWM             = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
                                                     clock pulse. CMP1 dictates the low phase of the output
                                                     and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
  TIMER_CTRL14_TMR14FN_SINGLEPATTERN   = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
                                                     LMT field specifies length of pattern. When LMT GT 32 OUT0
                                                     and OUT1 is the same 64-bit pattern consisting of concatenated
                                                     CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
                                                     Both OUT0 and OUT1 can be inverted individually applications
                                                     with POL0/POL1 = 0x1.                                                     */
  TIMER_CTRL14_TMR14FN_REPEATPATTERN   = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
                                                     pattern repeats after reaching LMT.                                       */
} TIMER_CTRL14_TMR14FN_Enum;

/* =============================================  TIMER CTRL14 TMR14POL1 [3..3]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL14_TMR14POL1                                                    */
  TIMER_CTRL14_TMR14POL1_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR14OUT1 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL14_TMR14POL1_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR14OUT1 pin is the inverse
                                                     of the timer output.                                                      */
} TIMER_CTRL14_TMR14POL1_Enum;

/* =============================================  TIMER CTRL14 TMR14POL0 [2..2]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL14_TMR14POL0                                                    */
  TIMER_CTRL14_TMR14POL0_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR14OUT0 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL14_TMR14POL0_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR14OUT0 pin is the inverse
                                                     of the timer output.                                                      */
} TIMER_CTRL14_TMR14POL0_Enum;

/* =============================================  TIMER CTRL14 TMR14CLR [1..1]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL14_TMR14CLR                                                     */
  TIMER_CTRL14_TMR14CLR_CLEAR          = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
                                                     cleared to its reset state # (0 for count up counter, CMP0
                                                     for down counter)                                                         */
  TIMER_CTRL14_TMR14CLR_DEFAULT        = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
} TIMER_CTRL14_TMR14CLR_Enum;

/* ==============================================  TIMER CTRL14 TMR14EN [0..0]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL14_TMR14EN                                                      */
  TIMER_CTRL14_TMR14EN_DIS             = 0,     /*!< DIS : Counter/Timer 14 Disable.                                           */
  TIMER_CTRL14_TMR14EN_EN              = 1,     /*!< EN : Counter/Timer 14 Enable.                                             */
} TIMER_CTRL14_TMR14EN_Enum;

/* ========================================================  TIMER14  ======================================================== */
/* =======================================================  TMR14CMP0  ======================================================= */
/* =======================================================  TMR14CMP1  ======================================================= */
/* ========================================================  MODE14  ========================================================= */
/* ===========================================  TIMER MODE14 TMR14TRIGSEL [8..15]  =========================================== */
typedef enum {                                  /*!< TIMER_MODE14_TMR14TRIGSEL                                                 */
  TIMER_MODE14_TMR14TRIGSEL_TMR00      = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR01      = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR10      = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR11      = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR20      = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR21      = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR30      = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR31      = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR40      = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR41      = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR50      = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR51      = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR60      = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR61      = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR70      = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR71      = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR80      = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR81      = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR90      = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR91      = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
  TIMER_MODE14_TMR14TRIGSEL_TMR100     = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
  TIMER_MODE14_TMR14TRIGSEL_TMR101     = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
  TIMER_MODE14_TMR14TRIGSEL_TMR110     = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
  TIMER_MODE14_TMR14TRIGSEL_TMR111     = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
  TIMER_MODE14_TMR14TRIGSEL_TMR120     = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
  TIMER_MODE14_TMR14TRIGSEL_TMR121     = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
  TIMER_MODE14_TMR14TRIGSEL_TMR130     = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
  TIMER_MODE14_TMR14TRIGSEL_TMR131     = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
  TIMER_MODE14_TMR14TRIGSEL_TMR140     = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
  TIMER_MODE14_TMR14TRIGSEL_TMR141     = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
  TIMER_MODE14_TMR14TRIGSEL_TMR150     = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
  TIMER_MODE14_TMR14TRIGSEL_TMR151     = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
  TIMER_MODE14_TMR14TRIGSEL_GPIO0      = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
  TIMER_MODE14_TMR14TRIGSEL_GPIO127    = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
} TIMER_MODE14_TMR14TRIGSEL_Enum;

/* ======================================================  TMR14LMTVAL  ====================================================== */
/* ========================================================  CTRL15  ========================================================= */
/* ===========================================  TIMER CTRL15 TMR15TMODE [16..17]  ============================================ */
typedef enum {                                  /*!< TIMER_CTRL15_TMR15TMODE                                                   */
  TIMER_CTRL15_TMR15TMODE_DIS          = 0,     /*!< DIS : Trigger not enabled                                                 */
  TIMER_CTRL15_TMR15TMODE_RISE         = 1,     /*!< RISE : Trigger on rising edge of TRIGSEL source                           */
  TIMER_CTRL15_TMR15TMODE_FALL         = 2,     /*!< FALL : Trigger on falling edge of TRIGSEL source                          */
  TIMER_CTRL15_TMR15TMODE_BOTH         = 3,     /*!< BOTH : Trigger on either edge of TRIGSEL source                           */
} TIMER_CTRL15_TMR15TMODE_Enum;

/* =============================================  TIMER CTRL15 TMR15CLK [8..15]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL15_TMR15CLK                                                     */
  TIMER_CTRL15_TMR15CLK_HFRC_DIV4      = 0,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
  TIMER_CTRL15_TMR15CLK_HFRC_DIV16     = 1,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
  TIMER_CTRL15_TMR15CLK_HFRC_DIV64     = 2,     /*!< HFRC_DIV64 : Clock source is HFRC / 64                                    */
  TIMER_CTRL15_TMR15CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
  TIMER_CTRL15_TMR15CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
  TIMER_CTRL15_TMR15CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
  TIMER_CTRL15_TMR15CLK_LFRC           = 6,     /*!< LFRC : Clock source is LFRC                                               */
  TIMER_CTRL15_TMR15CLK_LFRC_DIV2      = 7,     /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
  TIMER_CTRL15_TMR15CLK_LFRC_DIV32     = 8,     /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
  TIMER_CTRL15_TMR15CLK_LFRC_DIV1K     = 9,     /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
  TIMER_CTRL15_TMR15CLK_XT             = 10,    /*!< XT : Clock source is the XT (uncalibrated).                               */
  TIMER_CTRL15_TMR15CLK_XT_DIV2        = 11,    /*!< XT_DIV2 : Clock source is XT / 2                                          */
  TIMER_CTRL15_TMR15CLK_XT_DIV4        = 12,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
  TIMER_CTRL15_TMR15CLK_XT_DIV8        = 13,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
  TIMER_CTRL15_TMR15CLK_XT_DIV16       = 14,    /*!< XT_DIV16 : Clock source is XT / 16                                        */
  TIMER_CTRL15_TMR15CLK_XT_DIV32       = 15,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
  TIMER_CTRL15_TMR15CLK_XT_DIV128      = 16,    /*!< XT_DIV128 : Clock source is XT / 128                                      */
  TIMER_CTRL15_TMR15CLK_RTC_100HZ      = 17,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
  TIMER_CTRL15_TMR15CLK_BUCKC          = 28,    /*!< BUCKC : Clock source is Buck VDDC TON pulses.                             */
  TIMER_CTRL15_TMR15CLK_BUCKF          = 29,    /*!< BUCKF : Clock source is Buck VDDF TON pulses.                             */
  TIMER_CTRL15_TMR15CLK_BUCKS          = 30,    /*!< BUCKS : Clock source is Buck VDDS TON pulses.                             */
  TIMER_CTRL15_TMR15CLK_BUCKC_LV       = 31,    /*!< BUCKC_LV : Clock source is Buck VDDC_LV TON pulses.                       */
  TIMER_CTRL15_TMR15CLK_TMR00          = 32,    /*!< TMR00 : Clock source is TIMER 0 Output 0                                  */
  TIMER_CTRL15_TMR15CLK_TMR01          = 33,    /*!< TMR01 : Clock source is TIMER 0 Output 1                                  */
  TIMER_CTRL15_TMR15CLK_TMR10          = 34,    /*!< TMR10 : Clock source is TIMER 1 Output 0                                  */
  TIMER_CTRL15_TMR15CLK_TMR11          = 35,    /*!< TMR11 : Clock source is TIMER 1 Output 1                                  */
  TIMER_CTRL15_TMR15CLK_TMR20          = 36,    /*!< TMR20 : Clock source is TIMER 2 Output 0                                  */
  TIMER_CTRL15_TMR15CLK_TMR21          = 37,    /*!< TMR21 : Clock source is TIMER 2 Output 1                                  */
  TIMER_CTRL15_TMR15CLK_TMR30          = 38,    /*!< TMR30 : Clock source is TIMER 3 Output 0                                  */
  TIMER_CTRL15_TMR15CLK_TMR31          = 39,    /*!< TMR31 : Clock source is TIMER 3 Output 1                                  */
  TIMER_CTRL15_TMR15CLK_TMR40          = 40,    /*!< TMR40 : Clock source is TIMER 4 Output 0                                  */
  TIMER_CTRL15_TMR15CLK_TMR41          = 41,    /*!< TMR41 : Clock source is TIMER 4 Output 1                                  */
  TIMER_CTRL15_TMR15CLK_TMR50          = 42,    /*!< TMR50 : Clock source is TIMER 5 Output 0                                  */
  TIMER_CTRL15_TMR15CLK_TMR51          = 43,    /*!< TMR51 : Clock source is TIMER 5 Output 1                                  */
  TIMER_CTRL15_TMR15CLK_TMR60          = 44,    /*!< TMR60 : Clock source is TIMER 6 Output 0                                  */
  TIMER_CTRL15_TMR15CLK_TMR61          = 45,    /*!< TMR61 : Clock source is TIMER 6 Output 1                                  */
  TIMER_CTRL15_TMR15CLK_TMR70          = 46,    /*!< TMR70 : Clock source is TIMER 7 Output 0                                  */
  TIMER_CTRL15_TMR15CLK_TMR71          = 47,    /*!< TMR71 : Clock source is TIMER 7 Output 1                                  */
  TIMER_CTRL15_TMR15CLK_TMR80          = 48,    /*!< TMR80 : Clock source is TIMER 8 Output 0                                  */
  TIMER_CTRL15_TMR15CLK_TMR81          = 49,    /*!< TMR81 : Clock source is TIMER 8 Output 1                                  */
  TIMER_CTRL15_TMR15CLK_TMR90          = 50,    /*!< TMR90 : Clock source is TIMER 9 Output 0                                  */
  TIMER_CTRL15_TMR15CLK_TMR91          = 51,    /*!< TMR91 : Clock source is TIMER 9 Output 1                                  */
  TIMER_CTRL15_TMR15CLK_TMR100         = 52,    /*!< TMR100 : Clock source is TIMER 10 Output 0                                */
  TIMER_CTRL15_TMR15CLK_TMR101         = 53,    /*!< TMR101 : Clock source is TIMER 10 Output 1                                */
  TIMER_CTRL15_TMR15CLK_TMR110         = 54,    /*!< TMR110 : Clock source is TIMER 11 Output 0                                */
  TIMER_CTRL15_TMR15CLK_TMR111         = 55,    /*!< TMR111 : Clock source is TIMER 11 Output 1                                */
  TIMER_CTRL15_TMR15CLK_TMR120         = 56,    /*!< TMR120 : Clock source is TIMER 12 Output 0                                */
  TIMER_CTRL15_TMR15CLK_TMR121         = 57,    /*!< TMR121 : Clock source is TIMER 12 Output 1                                */
  TIMER_CTRL15_TMR15CLK_TMR130         = 58,    /*!< TMR130 : Clock source is TIMER 13 Output 0                                */
  TIMER_CTRL15_TMR15CLK_TMR131         = 59,    /*!< TMR131 : Clock source is TIMER 13 Output 1                                */
  TIMER_CTRL15_TMR15CLK_TMR140         = 60,    /*!< TMR140 : Clock source is TIMER 14 Output 0                                */
  TIMER_CTRL15_TMR15CLK_TMR141         = 61,    /*!< TMR141 : Clock source is TIMER 14 Output 1                                */
  TIMER_CTRL15_TMR15CLK_TMR150         = 62,    /*!< TMR150 : Clock source is TIMER 15 Output 0                                */
  TIMER_CTRL15_TMR15CLK_TMR151         = 63,    /*!< TMR151 : Clock source is TIMER 15 Output 1                                */
  TIMER_CTRL15_TMR15CLK_GPIO0          = 128,   /*!< GPIO0 : GPIO #0 is clock source                                           */
  TIMER_CTRL15_TMR15CLK_GPIO63         = 191,   /*!< GPIO63 : GPIO #63 is clock source                                         */
  TIMER_CTRL15_TMR15CLK_GPIO95         = 223,   /*!< GPIO95 : GPIO #95 is clock source                                         */
  TIMER_CTRL15_TMR15CLK_GPIO127        = 255,   /*!< GPIO127 : GPIO #127 is clock source                                       */
} TIMER_CTRL15_TMR15CLK_Enum;

/* ==============================================  TIMER CTRL15 TMR15FN [4..7]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL15_TMR15FN                                                      */
  TIMER_CTRL15_TMR15FN_EDGE            = 1,     /*!< EDGE : This Mode generates a single edge on OUT0/OUT1 when TIMER
                                                     value hits CMP0/CMP1 respectively. OUT[0]=0, counter increments
                                                     to CMP0, OUT[0]=1, counter stops. OUT[1] follows CMP1.                    */
  TIMER_CTRL15_TMR15FN_UPCOUNT         = 2,     /*!< UPCOUNT : This mode is run up counter generating a pulse on
                                                     CMP. OUT[0]/OUT[1] is pulsed for one source clock period
                                                     when TIMER matches CMP0/CMP1 respectively. Timer repeats
                                                     for TMR_LMT iterations.                                                   */
  TIMER_CTRL15_TMR15FN_PWM             = 4,     /*!< PWM : PWM mode. OUT0 and OUT1 are waveforms, and not just one
                                                     clock pulse. CMP1 dictates the low phase of the output
                                                     and CMP0 dictates the period. OUT[1]=~OUT[0].                             */
  TIMER_CTRL15_TMR15FN_SINGLEPATTERN   = 12,    /*!< SINGLEPATTERN : Single pattern. OUT0=CMP0[TIMER], OUT1=CMP1[TIMER].
                                                     LMT field specifies length of pattern. When LMT GT 32 OUT0
                                                     and OUT1 is the same 64-bit pattern consisting of concatenated
                                                     CMP1,CMP0. When LMT LT 32 OUT0 and OUT1 are independent.
                                                     Both OUT0 and OUT1 can be inverted individually applications
                                                     with POL0/POL1 = 0x1.                                                     */
  TIMER_CTRL15_TMR15FN_REPEATPATTERN   = 13,    /*!< REPEATPATTERN : Repeated pattern. Like SINGLEPATTERN mode, but
                                                     pattern repeats after reaching LMT.                                       */
} TIMER_CTRL15_TMR15FN_Enum;

/* =============================================  TIMER CTRL15 TMR15POL1 [3..3]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL15_TMR15POL1                                                    */
  TIMER_CTRL15_TMR15POL1_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR15OUT1 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL15_TMR15POL1_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR15OUT1 pin is the inverse
                                                     of the timer output.                                                      */
} TIMER_CTRL15_TMR15POL1_Enum;

/* =============================================  TIMER CTRL15 TMR15POL0 [2..2]  ============================================= */
typedef enum {                                  /*!< TIMER_CTRL15_TMR15POL0                                                    */
  TIMER_CTRL15_TMR15POL0_NORMAL        = 0,     /*!< NORMAL : The polarity of the TMR15OUT0 pin is the same as the
                                                     timer output.                                                             */
  TIMER_CTRL15_TMR15POL0_INVERTED      = 1,     /*!< INVERTED : The polarity of the TMR15OUT0 pin is the inverse
                                                     of the timer output.                                                      */
} TIMER_CTRL15_TMR15POL0_Enum;

/* =============================================  TIMER CTRL15 TMR15CLR [1..1]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL15_TMR15CLR                                                     */
  TIMER_CTRL15_TMR15CLR_CLEAR          = 1,     /*!< CLEAR : When written to a 1, the timer will automatically be
                                                     cleared to its reset state # (0 for count up counter, CMP0
                                                     for down counter)                                                         */
  TIMER_CTRL15_TMR15CLR_DEFAULT        = 0,     /*!< DEFAULT : Default value set to 0. Timer works normally.                   */
} TIMER_CTRL15_TMR15CLR_Enum;

/* ==============================================  TIMER CTRL15 TMR15EN [0..0]  ============================================== */
typedef enum {                                  /*!< TIMER_CTRL15_TMR15EN                                                      */
  TIMER_CTRL15_TMR15EN_DIS             = 0,     /*!< DIS : Counter/Timer 15 Disable.                                           */
  TIMER_CTRL15_TMR15EN_EN              = 1,     /*!< EN : Counter/Timer 15 Enable.                                             */
} TIMER_CTRL15_TMR15EN_Enum;

/* ========================================================  TIMER15  ======================================================== */
/* =======================================================  TMR15CMP0  ======================================================= */
/* =======================================================  TMR15CMP1  ======================================================= */
/* ========================================================  MODE15  ========================================================= */
/* ===========================================  TIMER MODE15 TMR15TRIGSEL [8..15]  =========================================== */
typedef enum {                                  /*!< TIMER_MODE15_TMR15TRIGSEL                                                 */
  TIMER_MODE15_TMR15TRIGSEL_TMR00      = 0,     /*!< TMR00 : Trigger source is TIMER 0 Output 0                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR01      = 1,     /*!< TMR01 : Trigger source is TIMER 0 Output 1                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR10      = 2,     /*!< TMR10 : Trigger source is TIMER 1 Output 0                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR11      = 3,     /*!< TMR11 : Trigger source is TIMER 1 Output 1                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR20      = 4,     /*!< TMR20 : Trigger source is TIMER 2 Output 0                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR21      = 5,     /*!< TMR21 : Trigger source is TIMER 2 Output 1                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR30      = 6,     /*!< TMR30 : Trigger source is TIMER 3 Output 0                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR31      = 7,     /*!< TMR31 : Trigger source is TIMER 3 Output 1                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR40      = 8,     /*!< TMR40 : Trigger source is TIMER 4 Output 0                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR41      = 9,     /*!< TMR41 : Trigger source is TIMER 4 Output 1                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR50      = 10,    /*!< TMR50 : Trigger source is TIMER 5 Output 0                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR51      = 11,    /*!< TMR51 : Trigger source is TIMER 5 Output 1                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR60      = 12,    /*!< TMR60 : Trigger source is TIMER 6 Output 0                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR61      = 13,    /*!< TMR61 : Trigger source is TIMER 6 Output 1                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR70      = 14,    /*!< TMR70 : Trigger source is TIMER 7 Output 0                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR71      = 15,    /*!< TMR71 : Trigger source is TIMER 7 Output 1                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR80      = 16,    /*!< TMR80 : Trigger source is TIMER 8 Output 0                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR81      = 17,    /*!< TMR81 : Trigger source is TIMER 8 Output 1                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR90      = 18,    /*!< TMR90 : Trigger source is TIMER 9 Output 0                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR91      = 19,    /*!< TMR91 : Trigger source is TIMER 9 Output 1                                */
  TIMER_MODE15_TMR15TRIGSEL_TMR100     = 20,    /*!< TMR100 : Trigger source is TIMER 10 Output 0                              */
  TIMER_MODE15_TMR15TRIGSEL_TMR101     = 21,    /*!< TMR101 : Trigger source is TIMER 10 Output 1                              */
  TIMER_MODE15_TMR15TRIGSEL_TMR110     = 22,    /*!< TMR110 : Trigger source is TIMER 11 Output 0                              */
  TIMER_MODE15_TMR15TRIGSEL_TMR111     = 23,    /*!< TMR111 : Trigger source is TIMER 11 Output 1                              */
  TIMER_MODE15_TMR15TRIGSEL_TMR120     = 24,    /*!< TMR120 : Trigger source is TIMER 12 Output 0                              */
  TIMER_MODE15_TMR15TRIGSEL_TMR121     = 25,    /*!< TMR121 : Trigger source is TIMER 12 Output 1                              */
  TIMER_MODE15_TMR15TRIGSEL_TMR130     = 26,    /*!< TMR130 : Trigger source is TIMER 13 Output 0                              */
  TIMER_MODE15_TMR15TRIGSEL_TMR131     = 27,    /*!< TMR131 : Trigger source is TIMER 13 Output 1                              */
  TIMER_MODE15_TMR15TRIGSEL_TMR140     = 28,    /*!< TMR140 : Trigger source is TIMER 14 Output 0                              */
  TIMER_MODE15_TMR15TRIGSEL_TMR141     = 29,    /*!< TMR141 : Trigger source is TIMER 14 Output 1                              */
  TIMER_MODE15_TMR15TRIGSEL_TMR150     = 30,    /*!< TMR150 : Trigger source is TIMER 15 Output 0                              */
  TIMER_MODE15_TMR15TRIGSEL_TMR151     = 31,    /*!< TMR151 : Trigger source is TIMER 15 Output 1                              */
  TIMER_MODE15_TMR15TRIGSEL_GPIO0      = 128,   /*!< GPIO0 : Trigger source is GPIO #0                                         */
  TIMER_MODE15_TMR15TRIGSEL_GPIO127    = 255,   /*!< GPIO127 : Trigger source is GPIO #127                                     */
} TIMER_MODE15_TMR15TRIGSEL_Enum;

/* ======================================================  TMR15LMTVAL  ====================================================== */
/* ======================================================  TIMERSPARES  ====================================================== */


/* =========================================================================================================================== */
/* ================                                           UART0                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  DR  =========================================================== */
/* ===============================================  UART0 DR OEDATA [11..11]  ================================================ */
typedef enum {                                  /*!< UART0_DR_OEDATA                                                           */
  UART0_DR_OEDATA_NOERR                = 0,     /*!< NOERR : No error on UART OEDATA, overrun error indicator.                 */
  UART0_DR_OEDATA_ERR                  = 1,     /*!< ERR : Error on UART OEDATA, overrun error indicator.                      */
} UART0_DR_OEDATA_Enum;

/* ===============================================  UART0 DR BEDATA [10..10]  ================================================ */
typedef enum {                                  /*!< UART0_DR_BEDATA                                                           */
  UART0_DR_BEDATA_NOERR                = 0,     /*!< NOERR : No error on UART BEDATA, break error indicator.                   */
  UART0_DR_BEDATA_ERR                  = 1,     /*!< ERR : Error on UART BEDATA, break error indicator.                        */
} UART0_DR_BEDATA_Enum;

/* ================================================  UART0 DR PEDATA [9..9]  ================================================= */
typedef enum {                                  /*!< UART0_DR_PEDATA                                                           */
  UART0_DR_PEDATA_NOERR                = 0,     /*!< NOERR : No error on UART PEDATA, parity error indicator.                  */
  UART0_DR_PEDATA_ERR                  = 1,     /*!< ERR : Error on UART PEDATA, parity error indicator.                       */
} UART0_DR_PEDATA_Enum;

/* ================================================  UART0 DR FEDATA [8..8]  ================================================= */
typedef enum {                                  /*!< UART0_DR_FEDATA                                                           */
  UART0_DR_FEDATA_NOERR                = 0,     /*!< NOERR : No error on UART FEDATA, framing error indicator.                 */
  UART0_DR_FEDATA_ERR                  = 1,     /*!< ERR : Error on UART FEDATA, framing error indicator.                      */
} UART0_DR_FEDATA_Enum;

/* ==========================================================  RSR  ========================================================== */
/* ================================================  UART0 RSR OESTAT [3..3]  ================================================ */
typedef enum {                                  /*!< UART0_RSR_OESTAT                                                          */
  UART0_RSR_OESTAT_NOERR               = 0,     /*!< NOERR : No error on UART OESTAT, overrun error indicator.                 */
  UART0_RSR_OESTAT_ERR                 = 1,     /*!< ERR : Error on UART OESTAT, overrun error indicator.                      */
} UART0_RSR_OESTAT_Enum;

/* ================================================  UART0 RSR BESTAT [2..2]  ================================================ */
typedef enum {                                  /*!< UART0_RSR_BESTAT                                                          */
  UART0_RSR_BESTAT_NOERR               = 0,     /*!< NOERR : No error on UART BESTAT, break error indicator.                   */
  UART0_RSR_BESTAT_ERR                 = 1,     /*!< ERR : Error on UART BESTAT, break error indicator.                        */
} UART0_RSR_BESTAT_Enum;

/* ================================================  UART0 RSR PESTAT [1..1]  ================================================ */
typedef enum {                                  /*!< UART0_RSR_PESTAT                                                          */
  UART0_RSR_PESTAT_NOERR               = 0,     /*!< NOERR : No error on UART PESTAT, parity error indicator.                  */
  UART0_RSR_PESTAT_ERR                 = 1,     /*!< ERR : Error on UART PESTAT, parity error indicator.                       */
} UART0_RSR_PESTAT_Enum;

/* ================================================  UART0 RSR FESTAT [0..0]  ================================================ */
typedef enum {                                  /*!< UART0_RSR_FESTAT                                                          */
  UART0_RSR_FESTAT_NOERR               = 0,     /*!< NOERR : No error on UART FESTAT, framing error indicator.                 */
  UART0_RSR_FESTAT_ERR                 = 1,     /*!< ERR : Error on UART FESTAT, framing error indicator.                      */
} UART0_RSR_FESTAT_Enum;

/* ==========================================================  FR  =========================================================== */
/* =================================================  UART0 FR TXFE [7..7]  ================================================== */
typedef enum {                                  /*!< UART0_FR_TXFE                                                             */
  UART0_FR_TXFE_XMTFIFO_EMPTY          = 1,     /*!< XMTFIFO_EMPTY : Transmit fifo is empty.                                   */
  UART0_FR_TXFE_XMTFIFO_NOTEMPTY       = 0,     /*!< XMTFIFO_NOTEMPTY : Transmit fifo is not empty.                            */
} UART0_FR_TXFE_Enum;

/* =================================================  UART0 FR RXFF [6..6]  ================================================== */
typedef enum {                                  /*!< UART0_FR_RXFF                                                             */
  UART0_FR_RXFF_RCVFIFO_FULL           = 1,     /*!< RCVFIFO_FULL : Receive fifo is full.                                      */
  UART0_FR_RXFF_RCVFIFO_NOTFULL        = 0,     /*!< RCVFIFO_NOTFULL : Receive fifo is not full.                               */
} UART0_FR_RXFF_Enum;

/* =================================================  UART0 FR TXFF [5..5]  ================================================== */
typedef enum {                                  /*!< UART0_FR_TXFF                                                             */
  UART0_FR_TXFF_XMTFIFO_FULL           = 1,     /*!< XMTFIFO_FULL : Transmit fifo is full.                                     */
  UART0_FR_TXFF_XMTFIFO_NOTFULL        = 0,     /*!< XMTFIFO_NOTFULL : Transmit fifo is not full.                              */
} UART0_FR_TXFF_Enum;

/* =================================================  UART0 FR RXFE [4..4]  ================================================== */
typedef enum {                                  /*!< UART0_FR_RXFE                                                             */
  UART0_FR_RXFE_RCVFIFO_EMPTY          = 1,     /*!< RCVFIFO_EMPTY : Receive fifo is empty.                                    */
  UART0_FR_RXFE_RCVFIFO_NOTEMPTY       = 0,     /*!< RCVFIFO_NOTEMPTY : Receive fifo is not empty.                             */
} UART0_FR_RXFE_Enum;

/* =================================================  UART0 FR BUSY [3..3]  ================================================== */
typedef enum {                                  /*!< UART0_FR_BUSY                                                             */
  UART0_FR_BUSY_BUSY                   = 1,     /*!< BUSY : UART busy indicator.                                               */
  UART0_FR_BUSY_NOTBUSY                = 0,     /*!< NOTBUSY : UART not busy.                                                  */
} UART0_FR_BUSY_Enum;

/* ==================================================  UART0 FR DCD [2..2]  ================================================== */
typedef enum {                                  /*!< UART0_FR_DCD                                                              */
  UART0_FR_DCD_DETECTED                = 1,     /*!< DETECTED : Data carrier detect detected.                                  */
  UART0_FR_DCD_DEFAULT                 = 0,     /*!< DEFAULT : Data carrier detect not detected/default.                       */
} UART0_FR_DCD_Enum;

/* ==================================================  UART0 FR DSR [1..1]  ================================================== */
typedef enum {                                  /*!< UART0_FR_DSR                                                              */
  UART0_FR_DSR_READY                   = 1,     /*!< READY : Data set ready.                                                   */
  UART0_FR_DSR_NOTREADY                = 0,     /*!< NOTREADY : Data set not ready/default.                                    */
} UART0_FR_DSR_Enum;

/* ==================================================  UART0 FR CTS [0..0]  ================================================== */
typedef enum {                                  /*!< UART0_FR_CTS                                                              */
  UART0_FR_CTS_CLEARTOSEND             = 1,     /*!< CLEARTOSEND : Clear to send is indicated.                                 */
  UART0_FR_CTS_DEFAULT                 = 0,     /*!< DEFAULT : Clear to send default value.                                    */
} UART0_FR_CTS_Enum;

/* =========================================================  ILPR  ========================================================== */
/* =========================================================  IBRD  ========================================================== */
/* =========================================================  FBRD  ========================================================== */
/* =========================================================  LCRH  ========================================================== */
/* ==========================================================  CR  =========================================================== */
/* ================================================  UART0 CR CLKSEL [4..6]  ================================================= */
typedef enum {                                  /*!< UART0_CR_CLKSEL                                                           */
  UART0_CR_CLKSEL_NOCLK                = 0,     /*!< NOCLK : No UART clock. This is the low power default.                     */
  UART0_CR_CLKSEL_24MHZ                = 1,     /*!< 24MHZ : 24 MHz clock.                                                     */
  UART0_CR_CLKSEL_12MHZ                = 2,     /*!< 12MHZ : 12 MHz clock.                                                     */
  UART0_CR_CLKSEL_6MHZ                 = 3,     /*!< 6MHZ : 6 MHz clock.                                                       */
  UART0_CR_CLKSEL_3MHZ                 = 4,     /*!< 3MHZ : 3 MHz clock.                                                       */
  UART0_CR_CLKSEL_48MHZ                = 5,     /*!< 48MHZ : Reserved.                                                         */
} UART0_CR_CLKSEL_Enum;

/* =========================================================  IFLS  ========================================================== */
/* ==========================================================  IER  ========================================================== */
/* ==========================================================  IES  ========================================================== */
/* ==========================================================  MIS  ========================================================== */
/* ==========================================================  IEC  ========================================================== */


/* =========================================================================================================================== */
/* ================                                           VCOMP                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  CFG  ========================================================== */
/* ===============================================  VCOMP CFG LVLSEL [16..19]  =============================================== */
typedef enum {                                  /*!< VCOMP_CFG_LVLSEL                                                          */
  VCOMP_CFG_LVLSEL_0P58V               = 0,     /*!< 0P58V : Set Reference input to 0.58 Volts.                                */
  VCOMP_CFG_LVLSEL_0P77V               = 1,     /*!< 0P77V : Set Reference input to 0.77 Volts.                                */
  VCOMP_CFG_LVLSEL_0P97V               = 2,     /*!< 0P97V : Set Reference input to 0.97 Volts.                                */
  VCOMP_CFG_LVLSEL_1P16V               = 3,     /*!< 1P16V : Set Reference input to 1.16 Volts.                                */
  VCOMP_CFG_LVLSEL_1P35V               = 4,     /*!< 1P35V : Set Reference input to 1.35 Volts.                                */
  VCOMP_CFG_LVLSEL_1P55V               = 5,     /*!< 1P55V : Set Reference input to 1.55 Volts.                                */
  VCOMP_CFG_LVLSEL_1P74V               = 6,     /*!< 1P74V : Set Reference input to 1.74 Volts.                                */
  VCOMP_CFG_LVLSEL_1P93V               = 7,     /*!< 1P93V : Set Reference input to 1.93 Volts.                                */
  VCOMP_CFG_LVLSEL_2P13V               = 8,     /*!< 2P13V : Set Reference input to 2.13 Volts.                                */
} VCOMP_CFG_LVLSEL_Enum;

/* =================================================  VCOMP CFG NSEL [8..9]  ================================================= */
typedef enum {                                  /*!< VCOMP_CFG_NSEL                                                            */
  VCOMP_CFG_NSEL_VREFEXT1              = 0,     /*!< VREFEXT1 : Use external reference 1 for reference input.                  */
  VCOMP_CFG_NSEL_VREFEXT2              = 1,     /*!< VREFEXT2 : Use external reference 2 for reference input.                  */
  VCOMP_CFG_NSEL_VREFEXT3              = 2,     /*!< VREFEXT3 : Use external reference 3 for reference input.                  */
  VCOMP_CFG_NSEL_DAC                   = 3,     /*!< DAC : Use DAC output selected by LVLSEL for reference input.              */
} VCOMP_CFG_NSEL_Enum;

/* =================================================  VCOMP CFG PSEL [0..1]  ================================================= */
typedef enum {                                  /*!< VCOMP_CFG_PSEL                                                            */
  VCOMP_CFG_PSEL_VDDADJ                = 0,     /*!< VDDADJ : Use VDDADJ for the positive input.                               */
  VCOMP_CFG_PSEL_VTEMP                 = 1,     /*!< VTEMP : Use the temperature sensor output for the positive input.
                                                     Note: If this channel is selected for PSEL, the bandap
                                                     circuit required for temperature comparisons will automatically
                                                     turn on. The bandgap circuit requires 11us to stabalize.                  */
  VCOMP_CFG_PSEL_VEXT1                 = 2,     /*!< VEXT1 : Use external voltage 0 for positive input.                        */
  VCOMP_CFG_PSEL_VEXT2                 = 3,     /*!< VEXT2 : Use external voltage 1 for positive input.                        */
} VCOMP_CFG_PSEL_Enum;

/* =========================================================  STAT  ========================================================== */
/* ===============================================  VCOMP STAT PWDSTAT [1..1]  =============================================== */
typedef enum {                                  /*!< VCOMP_STAT_PWDSTAT                                                        */
  VCOMP_STAT_PWDSTAT_POWERED_DOWN      = 1,     /*!< POWERED_DOWN : The voltage comparator is powered down.                    */
  VCOMP_STAT_PWDSTAT_POWERED_UP        = 0,     /*!< POWERED_UP : The voltage comparator is powered up.                        */
} VCOMP_STAT_PWDSTAT_Enum;

/* ===============================================  VCOMP STAT CMPOUT [0..0]  ================================================ */
typedef enum {                                  /*!< VCOMP_STAT_CMPOUT                                                         */
  VCOMP_STAT_CMPOUT_VOUT_LOW           = 0,     /*!< VOUT_LOW : The negative input of the comparator is greater than
                                                     the positive input.                                                       */
  VCOMP_STAT_CMPOUT_VOUT_HIGH          = 1,     /*!< VOUT_HIGH : The positive input of the comparator is greater
                                                     than the negative input.                                                  */
} VCOMP_STAT_CMPOUT_Enum;

/* ========================================================  PWDKEY  ========================================================= */
/* ==============================================  VCOMP PWDKEY PWDKEY [0..31]  ============================================== */
typedef enum {                                  /*!< VCOMP_PWDKEY_PWDKEY                                                       */
  VCOMP_PWDKEY_PWDKEY_Key              = 55,    /*!< Key : Key value to unlock the register.                                   */
} VCOMP_PWDKEY_PWDKEY_Enum;

/* =========================================================  INTEN  ========================================================= */
/* ========================================================  INTSTAT  ======================================================== */
/* ========================================================  INTCLR  ========================================================= */
/* ========================================================  INTSET  ========================================================= */


/* =========================================================================================================================== */
/* ================                                            WDT                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CFG  ========================================================== */
/* ================================================  WDT CFG CLKSEL [24..26]  ================================================ */
typedef enum {                                  /*!< WDT_CFG_CLKSEL                                                            */
  WDT_CFG_CLKSEL_OFF                   = 0,     /*!< OFF : Low Power Mode. This setting disables the watch dog timer.          */
  WDT_CFG_CLKSEL_128HZ                 = 1,     /*!< 128HZ : 128 Hz LFRC clock.                                                */
  WDT_CFG_CLKSEL_16HZ                  = 2,     /*!< 16HZ : 16 Hz LFRC clock.                                                  */
  WDT_CFG_CLKSEL_1HZ                   = 3,     /*!< 1HZ : 1 Hz LFRC clock.                                                    */
  WDT_CFG_CLKSEL_1_16HZ                = 4,     /*!< 1_16HZ : 1/16th Hz LFRC clock.                                            */
} WDT_CFG_CLKSEL_Enum;

/* =========================================================  RSTRT  ========================================================= */
/* ================================================  WDT RSTRT RSTRT [0..7]  ================================================= */
typedef enum {                                  /*!< WDT_RSTRT_RSTRT                                                           */
  WDT_RSTRT_RSTRT_KEYVALUE             = 178,   /*!< KEYVALUE : This is the key value to write to WDTRSTRT to restart
                                                     the WDT. This is a write only register.                                   */
  WDT_RSTRT_RSTRT_DEFAULT              = 0,     /*!< DEFAULT : Default/Reset value. This is a write only register.             */
} WDT_RSTRT_RSTRT_Enum;

/* =========================================================  LOCK  ========================================================== */
/* =================================================  WDT LOCK LOCK [0..7]  ================================================== */
typedef enum {                                  /*!< WDT_LOCK_LOCK                                                             */
  WDT_LOCK_LOCK_KEYVALUE               = 58,    /*!< KEYVALUE : This is the key value to write to WDTLOCK to lock
                                                     the WDT.                                                                  */
  WDT_LOCK_LOCK_DEFAULT                = 0,     /*!< DEFAULT : Default/Reset value.                                            */
} WDT_LOCK_LOCK_Enum;

/* =========================================================  COUNT  ========================================================= */
/* =======================================================  WDTIEREN  ======================================================== */
/* ======================================================  WDTIERSTAT  ======================================================= */
/* =======================================================  WDTIERCLR  ======================================================= */
/* =======================================================  WDTIERSET  ======================================================= */

/** @} */ /* End of group EnumValue_peripherals */


#ifdef __cplusplus
}
#endif

#endif /* APOLLO4L_H */


/** @} */ /* End of group apollo4l */

/** @} */ /* End of group Ambiq Micro */
