Apollo Register Documentation  v${version}
RTC - Real Time Clock

RTC Register Index

  0x00000040:   CTRLOW - RTC Counters Lower
  0x00000044:   CTRUP - RTC Counters Upper
  0x00000048:   ALMLOW - RTC Alarms Lower
  0x0000004C:   ALMUP - RTC Alarms Upper
  0x00000050:   RTCCTL - RTC Control
  0x00000100:   INTEN - RTC Interrupt: Enable
  0x00000104:   INTSTAT - RTC Interrupt: Status
  0x00000108:   INTCLR - RTC Interrupt: Clear
  0x0000010C:   INTSET - RTC Interrupt: Set

CTRLOW - RTC Counters Lower

Address:

  Instance 0 Address:   0x40004240

Description:

This counter contains the values for hour, minutes, seconds and 100ths of a second Counter.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CTRHR
0x1
RSVD
0x0
CTRMIN
0x0
RSVD
0x0
CTRSEC
0x0
CTR100
0x0

Bits Name RW Description
31:30 RSVD RO RESERVED

29:24 CTRHR RW Hours Counter

23 RSVD RO RESERVED

22:16 CTRMIN RW Minutes Counter

15 RSVD RO RESERVED

14:8 CTRSEC RW Seconds Counter

7:0 CTR100 RW 100ths of a second Counter


CTRUP - RTC Counters Upper

Address:

  Instance 0 Address:   0x40004244

Description:

This register contains the day, month and year information. It contains which day in the week, and the century as well. The information of the century can also be derived from the year information. The 31st bit contains the error bit. See description in the register bit for condition when error is triggered.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTERR
0x0
RSVD
0x0
CEB
0x0
CB
0x0
CTRWKDY
0x0
CTRYR
0x0
RSVD
0x0
CTRMO
0x0
RSVD
0x0
CTRDATE
0x0

Bits Name RW Description
31 CTERR RO Counter read error status. Error is triggered when software reads the lower word of the counters, and fails to read the upper counter within 1/100 second. This is because when the lower counter is read, the upper counter is held off from incrementing until it is read so that the full time stamp can be read.

NOERR = 0x0 - No read error occurred
RDERR = 0x1 - Read error occurred
30:29 RSVD RO RESERVED

28 CEB RW Century enable

DIS = 0x0 - Disable the Century bit from changing
EN = 0x1 - Enable the Century bit to change
27 CB RW Century

2000 = 0x0 - Century is 2000s
1900_2100 = 0x1 - Century is 1900s/2100s
26:24 CTRWKDY RW Weekdays Counter

23:16 CTRYR RW Years Counter

15:13 RSVD RO RESERVED

12:8 CTRMO RW Months Counter

7:6 RSVD RO RESERVED

5:0 CTRDATE RW Date Counter


ALMLOW - RTC Alarms Lower

Address:

  Instance 0 Address:   0x40004248

Description:

This register is the Alarm settings for hours, minutes, second and 1/100th seconds settings.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ALMHR
0x0
RSVD
0x0
ALMMIN
0x0
RSVD
0x0
ALMSEC
0x0
ALM100
0x0

Bits Name RW Description
31:30 RSVD RO RESERVED

29:24 ALMHR RW Hours Alarm

23 RSVD RO RESERVED

22:16 ALMMIN RW Minutes Alarm

15 RSVD RO RESERVED

14:8 ALMSEC RW Seconds Alarm

7:0 ALM100 RW 100ths of a second Alarm


ALMUP - RTC Alarms Upper

Address:

  Instance 0 Address:   0x4000424C

Description:

This register is the alarm settings for week, month and day.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ALMWKDY
0x0
RSVD
0x0
ALMMO
0x0
RSVD
0x0
ALMDATE
0x0

Bits Name RW Description
31:19 RSVD RO RESERVED

18:16 ALMWKDY RW Weekdays Alarm

15:13 RSVD RO RESERVED

12:8 ALMMO RW Months Alarm

7:6 RSVD RO RESERVED

5:0 ALMDATE RW Date Alarm


RTCCTL - RTC Control

Address:

  Instance 0 Address:   0x40004250

Description:

This is the register control for the RTC module. It sets the 12 or 24 hours mode, enables counter writes and sets the alarm repeat interval.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
HR1224
0x0
RSTOP
0x0
RPT
0x0
WRTC
0x0

Bits Name RW Description
31:6 RSVD RO RESERVED

5 HR1224 RW Hours Counter mode

24HR = 0x0 - Hours in 24 hour mode
12HR = 0x1 - Hours in 12 hour mode
4 RSTOP RW RTC input clock control

RUN = 0x0 - Allow the RTC input clock to run
STOP = 0x1 - Stop the RTC input clock
3:1 RPT RW Alarm repeat interval

DIS = 0x0 - Alarm interrupt disabled
YEAR = 0x1 - Interrupt every year
MONTH = 0x2 - Interrupt every month
WEEK = 0x3 - Interrupt every week
DAY = 0x4 - Interrupt every day
HR = 0x5 - Interrupt every hour
MIN = 0x6 - Interrupt every minute
SEC = 0x7 - Interrupt every second/10th/100th
0 WRTC RW Counter write control

DIS = 0x0 - Counter writes are disabled
EN = 0x1 - Counter writes are enabled

INTEN - RTC Interrupt: Enable

Address:

  Instance 0 Address:   0x40004300

Description:

Set bits in this register to allow this module to generate the corresponding interrupt.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ALM
0x0

Bits Name RW Description
31:1 RSVD RO RESERVED

0 ALM RW RTC Alarm interrupt


INTSTAT - RTC Interrupt: Status

Address:

  Instance 0 Address:   0x40004304

Description:

Read bits from this register to discover the cause of a recent interrupt.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ALM
0x0

Bits Name RW Description
31:1 RSVD RO RESERVED

0 ALM RW RTC Alarm interrupt


INTCLR - RTC Interrupt: Clear

Address:

  Instance 0 Address:   0x40004308

Description:

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ALM
0x0

Bits Name RW Description
31:1 RSVD RO RESERVED

0 ALM RW RTC Alarm interrupt


INTSET - RTC Interrupt: Set

Address:

  Instance 0 Address:   0x4000430C

Description:

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ALM
0x0

Bits Name RW Description
31:1 RSVD RO RESERVED

0 ALM RW RTC Alarm interrupt