Apollo Register Documentation  v${version}
NVIC - Nested Vectored Interrupt Controller

NVIC Register Index

  0xE000E100:   ISER0 - Interrupt Set-Enable Register 0
  0xE000E180:   ICER0 - Interrupt Clear-Enable Register 0
  0xE000E200:   ISPR0 - Interrupt Set-Pending Register 0
  0xE000E280:   ICPR0 - Interrupt Clear-Pending Register 0
  0xE000E300:   IABR0 - Interrupt Active Bit Register 0
  0xE000E400:   IPR0 - Interrupt Priority Register 0
  0xE000E404:   IPR1 - Interrupt Priority Register 1
  0xE000E408:   IPR2 - Interrupt Priority Register 2
  0xE000E40C:   IPR3 - Interrupt Priority Register 3
  0xE000E410:   IPR4 - Interrupt Priority Register 4
  0xE000E414:   IPR5 - Interrupt Priority Register 5
  0xE000E418:   IPR6 - Interrupt Priority Register 6
  0xE000E41C:   IPR7 - Interrupt Priority Register 7

ISER0 - Interrupt Set-Enable Register 0

Address:

  Instance 0 Address:   0xE000E100

Description:

Interrupt Set-Enable Register 0

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
0x0

Bits Name RW Description
31:0 BITS RW NVIC_ISERn[31:0] are the set-enable bits for interrupts 31 through 0.


ICER0 - Interrupt Clear-Enable Register 0

Address:

  Instance 0 Address:   0xE000E180

Description:

Interrupt Clear-Enable Register 0

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
0x0

Bits Name RW Description
31:0 BITS RW NVIC_ISERn[31:0] are the clear-enable bits for interrupts 31 through 0.


ISPR0 - Interrupt Set-Pending Register 0

Address:

  Instance 0 Address:   0xE000E200

Description:

Interrupt Set-Pending Register 0

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
0x0

Bits Name RW Description
31:0 BITS RW NVIC_ISERn[31:0] are the set-pending bits for interrupts 31 through 0.


ICPR0 - Interrupt Clear-Pending Register 0

Address:

  Instance 0 Address:   0xE000E280

Description:

Interrupt Clear-Pending Register 0

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
0x0

Bits Name RW Description
31:0 BITS RW NVIC_ISERn[31:0] are the clear-pending bits for interrupts 31 through 0.


IABR0 - Interrupt Active Bit Register 0

Address:

  Instance 0 Address:   0xE000E300

Description:

Interrupt Active Bit Register 0

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
0x0

Bits Name RW Description
31:0 BITS RO NVIC_ISERn[31:0] are the interrupt active bits for interrupts 31 through 0.


IPR0 - Interrupt Priority Register 0

Address:

  Instance 0 Address:   0xE000E400

Description:

Interrupt Priority Register 0

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_N3
0x0
PRI_N2
0x0
PRI_N1
0x0
PRI_N0
0x0

Bits Name RW Description
31:24 PRI_N3 RW Priority assignment for interrupt vector 3.

23:16 PRI_N2 RW Priority assignment for interrupt vector 2.

15:8 PRI_N1 RW Priority assignment for interrupt vector 1.

7:0 PRI_N0 RW Priority assignment for interrupt vector 0.


IPR1 - Interrupt Priority Register 1

Address:

  Instance 0 Address:   0xE000E404

Description:

Interrupt Priority Register 1

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_N3
0x0
PRI_N2
0x0
PRI_N1
0x0
PRI_N0
0x0

Bits Name RW Description
31:24 PRI_N3 RW Priority assignment for interrupt vector 7.

23:16 PRI_N2 RW Priority assignment for interrupt vector 6.

15:8 PRI_N1 RW Priority assignment for interrupt vector 5.

7:0 PRI_N0 RW Priority assignment for interrupt vector 4.


IPR2 - Interrupt Priority Register 2

Address:

  Instance 0 Address:   0xE000E408

Description:

Interrupt Priority Register 2

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_N3
0x0
PRI_N2
0x0
PRI_N1
0x0
PRI_N0
0x0

Bits Name RW Description
31:24 PRI_N3 RW Priority assignment for interrupt vector 11.

23:16 PRI_N2 RW Priority assignment for interrupt vector 10.

15:8 PRI_N1 RW Priority assignment for interrupt vector 9.

7:0 PRI_N0 RW Priority assignment for interrupt vector 8.


IPR3 - Interrupt Priority Register 3

Address:

  Instance 0 Address:   0xE000E40C

Description:

Interrupt Priority Register 3

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_N3
0x0
PRI_N2
0x0
PRI_N1
0x0
PRI_N0
0x0

Bits Name RW Description
31:24 PRI_N3 RW Priority assignment for interrupt vector 15.

23:16 PRI_N2 RW Priority assignment for interrupt vector 14.

15:8 PRI_N1 RW Priority assignment for interrupt vector 13.

7:0 PRI_N0 RW Priority assignment for interrupt vector 12.


IPR4 - Interrupt Priority Register 4

Address:

  Instance 0 Address:   0xE000E410

Description:

Interrupt Priority Register 4

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_N3
0x0
PRI_N2
0x0
PRI_N1
0x0
PRI_N0
0x0

Bits Name RW Description
31:24 PRI_N3 RW Priority assignment for interrupt vector 19.

23:16 PRI_N2 RW Priority assignment for interrupt vector 18.

15:8 PRI_N1 RW Priority assignment for interrupt vector 17.

7:0 PRI_N0 RW Priority assignment for interrupt vector 16.


IPR5 - Interrupt Priority Register 5

Address:

  Instance 0 Address:   0xE000E414

Description:

Interrupt Priority Register 5

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_N3
0x0
PRI_N2
0x0
PRI_N1
0x0
PRI_N0
0x0

Bits Name RW Description
31:24 PRI_N3 RW Priority assignment for interrupt vector 23.

23:16 PRI_N2 RW Priority assignment for interrupt vector 22.

15:8 PRI_N1 RW Priority assignment for interrupt vector 21.

7:0 PRI_N0 RW Priority assignment for interrupt vector 20.


IPR6 - Interrupt Priority Register 6

Address:

  Instance 0 Address:   0xE000E418

Description:

Interrupt Priority Register 6

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_N3
0x0
PRI_N2
0x0
PRI_N1
0x0
PRI_N0
0x0

Bits Name RW Description
31:24 PRI_N3 RW Priority assignment for interrupt vector 27.

23:16 PRI_N2 RW Priority assignment for interrupt vector 26.

15:8 PRI_N1 RW Priority assignment for interrupt vector 25.

7:0 PRI_N0 RW Priority assignment for interrupt vector 24.


IPR7 - Interrupt Priority Register 7

Address:

  Instance 0 Address:   0xE000E41C

Description:

Interrupt Priority Register 7

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRI_N3
0x0
PRI_N2
0x0
PRI_N1
0x0
PRI_N0
0x0

Bits Name RW Description
31:24 PRI_N3 RW Priority assignment for interrupt vector 31.

23:16 PRI_N2 RW Priority assignment for interrupt vector 30.

15:8 PRI_N1 RW Priority assignment for interrupt vector 29.

7:0 PRI_N0 RW Priority assignment for interrupt vector 28.