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Apollo Register Documentation v${version}
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0x00000000: | SR - ISO7816 interrupt status |
0x00000004: | IER - ISO7816 interrupt enable |
0x00000008: | TCR - ISO7816 transmit control |
0x0000000C: | UCR - ISO7816 user control |
0x00000010: | DR - ISO7816 data |
0x00000014: | BPRL - ISO7816 baud rate low |
0x00000018: | BPRH - ISO7816 baud rate high |
0x0000001C: | UCR1 - ISO7816 user control 1 |
0x00000020: | SR1 - ISO7816 interrupt status 1 |
0x00000024: | IER1 - ISO7816 interrupt enable 1 |
0x00000028: | ECNTL - ETU counter low |
0x0000002C: | ECNTH - ETU counter high |
0x00000030: | GTR - ISO7816 guard time configuration |
0x00000034: | RETXCNT - ISO7816 resend count |
0x00000038: | RETXCNTRMI - ISO7816 resent count inquiry |
0x00000100: | CLKCTRL - Clock Control |
Instance 0 Address: | 0x40080000 |
ISO7816 interrupt status
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
FHF
0x0 |
FT2REND
0x0 |
PE
0x0 |
OVR
0x0 |
FER
0x0 |
TBERBF
0x0 |
FNE
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:7 | RSVD | RO | This bit field is reserved for future use. |
6 | FHF | RW | FIFO Half Full. HALFFULL = 0x1 - FIFO is half full. |
5 | FT2REND | RW | TX to RX finished. CMPL = 0x1 - TX to RX completed. NOTCMPL = 0x0 - TX to RX not completed. |
4 | PE | RW | Parity Error. PEERR = 0x1 - Parity error. PENONE = 0x0 - No parity error. |
3 | OVR | RW | RX FIFO overflow. RXOVR = 0x1 - RX FIFO overflow. RXOVRNONE = 0x0 - RX FIFO no overflow. |
2 | FER | RW | Framing error. FRAMINGERR = 0x1 - Framing error. NOFRAMINGERR = 0x0 - No framing error detected. |
1 | TBERBF | RO | FIFO empty (transmit) or full (receive). TXFIFOEMPTY = 0x1 - Transmit: FIFO empty. RXFIFOFULL = 0x1 - Receive: FIFO full. TXFIFONOTEMPTY = 0x0 - Transmit: FIFO not empty. RXFIFONOTFULL = 0x0 - Receive: FIFO not full. |
0 | FNE | RO | RX FIFO not empty. NOTEMPTY = 0x1 - RX FIFO not empty. EMPTY = 0x0 - RX FIFO empty. |
Instance 0 Address: | 0x40080004 |
ISO7816 interrupt enable
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
FHFEN
0x0 |
FT2RENDEN
0x0 |
PEEN
0x0 |
OVREN
0x0 |
FEREN
0x0 |
TBERBFEN
0x0 |
FNEEN
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:7 | RSVD | RO | This bit field is reserved for future use. |
6 | FHFEN | RW | FIFO Half Full interrupt enable. |
5 | FT2RENDEN | RW | TX to RX finished interrupt enable. |
4 | PEEN | RW | Parity Error interrupt enable. |
3 | OVREN | RW | RX FIFOI overflow interrupt enable. |
2 | FEREN | RW | Framing error interrupt enable. |
1 | TBERBFEN | RW | FIFO empty (transmit) or full (receive) interrupt enable. |
0 | FNEEN | RW | RX FIFO not empty interrupt enable. |
Instance 0 Address: | 0x40080008 |
ISO7816 transmit control
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
DMAMD
0x0 |
FIP
0x0 |
AUTOCONV
0x0 |
PROT
0x0 |
TR
0x0 |
LCT
0x0 |
SS
0x1 |
CONV
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:8 | RSVD | RO | This bit field is reserved for future use. |
7 | DMAMD | RW | DMA direction. |
6 | FIP | RW | Parity select. |
5 | AUTOCONV | RW | Automatic conversion. |
4 | PROT | RW | PROT control. |
3 | TR | RW | Transmit/receive mode. |
2 | LCT | RW | Fast TX to RX. |
1 | SS | RW | Use first byte to configure conversion. |
0 | CONV | RW | Conversion inversion control. |
Instance 0 Address: | 0x4008000C |
ISO7816 user control
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
RETXEN
0x1 |
RSTIN
0x0 |
RIU
0x0 |
CST
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:4 | RSVD | RO | This bit field is reserved for future use. |
3 | RETXEN | RW | Enable TX/RX time configuration. |
2 | RSTIN | RW | Reset polarity. |
1 | RIU | WO | ISO7816 reset. This bit is write-only. |
0 | CST | RW | Clock control. |
Instance 0 Address: | 0x40080010 |
ISO7816 data
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
DR
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:8 | RSVD | RO | This bit field is reserved for future use. |
7:0 | DR | RW | Data register. |
Instance 0 Address: | 0x40080014 |
ISO7816 baud rate low
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
BPRL
0x74 |
Bits | Name | RW | Description |
---|---|---|---|
31:8 | RSVD | RO | This bit field is reserved for future use. |
7:0 | BPRL | RW | Baud rate low |
Instance 0 Address: | 0x40080018 |
ISO7816 baud rate high
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
BPRH
0x1 |
Bits | Name | RW | Description |
---|---|---|---|
31:4 | RSVD | RO | This bit field is reserved for future use. |
3:0 | BPRH | RW | Baud rate high |
Instance 0 Address: | 0x4008001C |
ISO7816 user control 1
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
ENLASTB
0x1 |
CLKIOV
0x1 |
T1PAREN
0x0 |
STSP
0x0 |
RSVD
0x0 |
PR
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:6 | RSVD | RO | This bit field is reserved for future use. |
5 | ENLASTB | RW | Enable last byte function. |
4 | CLKIOV | RW | Output clock level. |
3 | T1PAREN | RW | Parity check control. |
2 | STSP | WO | ETU counter control. This bit is write-only. |
1 | RSVD | RO | This bit field is reserved for future use. |
0 | PR | RW | Query Card Detect. |
Instance 0 Address: | 0x40080020 |
ISO7816 interrupt status 1
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
IDLE
0x1 |
SYNCEND
0x0 |
PRL
0x0 |
ECNTOVER
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:4 | RSVD | RO | This bit field is reserved for future use. |
3 | IDLE | RO | ISO7816 idle. IDLE = 0x1 - ISO7816 idle. ACTIVE = 0x0 - ISO7816 active. |
2 | SYNCEND | RW | Write complete synchronization. CMPL = 0x1 - Synchronization complete. INCMPL = 0x0 - Incomplete. |
1 | PRL | RW | Card insert/remove. INSREM = 0x1 - Card inserted/removed. |
0 | ECNTOVER | RW | ETU counter overflow. OVR = 0x1 - ETU overflow. |
Instance 0 Address: | 0x40080024 |
ISO7816 interrupt enable 1
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
SYNCENDEN
0x0 |
PRLEN
0x0 |
ECNTOVEREN
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:3 | RSVD | RO | This bit field is reserved for future use. |
2 | SYNCENDEN | RW | Write complete synchronization interrupt enable. |
1 | PRLEN | RW | Card insert/remove interrupt enable. |
0 | ECNTOVEREN | RW | ETU counter overflow interrupt enable. |
Instance 0 Address: | 0x40080028 |
ETU counter low
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
ECNTL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:8 | RSVD | RO | This bit field is reserved for future use. |
7:0 | ECNTL | RW | ETU counter low register. |
Instance 0 Address: | 0x4008002C |
ETU counter high
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
ECNTH
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:8 | RSVD | RO | This bit field is reserved for future use. |
7:0 | ECNTH | RW | ETU counter high register. |
Instance 0 Address: | 0x40080030 |
ISO7816 guard time configuration
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
GTR
0xff |
Bits | Name | RW | Description |
---|---|---|---|
31:8 | RSVD | RO | This bit field is reserved for future use. |
7:0 | GTR | RW | Guard time configuration register. |
Instance 0 Address: | 0x40080034 |
ISO7816 resend count
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
RETXCNT
0x4 |
Bits | Name | RW | Description |
---|---|---|---|
31:4 | RSVD | RO | This bit field is reserved for future use. |
3:0 | RETXCNT | RW | Resend count register. |
Instance 0 Address: | 0x40080038 |
ISO7816 resent count inquiry
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
RETXCNTRMI
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:4 | RSVD | RO | This bit field is reserved for future use. |
3:0 | RETXCNTRMI | RW | Resent count inquiry register. |
Instance 0 Address: | 0x40080100 |
SCARD external clock control
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
APBCLKEN
0x0 |
CLKEN
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:2 | RSVD | RO | This bit field is reserved for future use. |
1 | APBCLKEN | RW | Enable the SCARD APB clock to run continuously. |
0 | CLKEN | RW | Enable the serial source clock for SCARD. |