![]() |
Apollo Register Documentation v${version}
|
Instance 0 Address: | 0x40021000 |
This register controls the enable for BLE BUCK.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
BLEBUCKEN
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:1 | RSVD | RO | RESERVED. |
0 | BLEBUCKEN | RW | Enables and Selects the BLE Buck as the supply for the BLE power domain or for Burst LDO. It takes the initial value from Customer INFO space. Buck will be powered up only if there is an active request for BLEH domain or Burst mode and appropriate feature is allowed. EN = 0x1 - Enable the BLE Buck. DIS = 0x0 - Disable the BLE Buck. |
Instance 0 Address: | 0x40021004 |
Provides an indicator for the BLE BUCK and SIMO BUCK status. Once the SIMO BUCK is powered up MEM and CORE LDOs are disabled.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
BLEBUCKON
0x0 |
SIMOBUCKON
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:2 | RSVD | RO | RESERVED. |
1 | BLEBUCKON | RO | Indicates whether the BLE (if supported) domain and burst (if supported) domain is supplied from the LDO or the Buck. Buck will be powered up only if there is an active request for BLEH domain or Burst mode and appropriate feature is allowed. LDO = 0x0 - Indicates the the LDO is supplying the BLE/Burst power domain BUCK = 0x1 - Indicates the the Buck is supplying the BLE/Burst power domain |
0 | SIMOBUCKON | RO | Indicates whether the Core/Mem low-voltage domains are supplied from the LDO or the Buck. OFF = 0x0 - Indicates the the SIMO Buck is OFF. ON = 0x1 - Indicates the the SIMO Buck is ON. |
Instance 0 Address: | 0x40021008 |
This enables various peripherals power domains.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
PWRBLEL
0x0 |
PWRPDM
0x0 |
PWRMSPI2
0x0 |
PWRMSPI1
0x0 |
PWRMSPI0
0x0 |
PWRSCARD
0x0 |
PWRADC
0x0 |
PWRUART1
0x0 |
PWRUART0
0x0 |
PWRIOM5
0x0 |
PWRIOM4
0x0 |
PWRIOM3
0x0 |
PWRIOM2
0x0 |
PWRIOM1
0x0 |
PWRIOM0
0x0 |
PWRIOS
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:16 | RSVD | RO | RESERVED. |
15 | PWRBLEL | RW | Power up BLE controller EN = 0x1 - Power up BLE controller DIS = 0x0 - Power down BLE controller |
14 | PWRPDM | RW | Power up PDM block EN = 0x1 - Power up PDM DIS = 0x0 - Power down PDM |
13 | PWRMSPI2 | RW | Power up MSPI2 Controller EN = 0x1 - Power up MSPI2 DIS = 0x0 - Power down MSPI2 |
12 | PWRMSPI1 | RW | Power up MSPI1 Controller EN = 0x1 - Power up MSPI1 DIS = 0x0 - Power down MSPI1 |
11 | PWRMSPI0 | RW | Power up MSPI0 Controller EN = 0x1 - Power up MSPI0 DIS = 0x0 - Power down MSPI0 |
10 | PWRSCARD | RW | Power up SCARD Controller EN = 0x1 - Power up SCARD DIS = 0x0 - Power down SCARD |
9 | PWRADC | RW | Power up ADC Digital Controller EN = 0x1 - Power up ADC DIS = 0x0 - Power Down ADC |
8 | PWRUART1 | RW | Power up UART Controller 1 EN = 0x1 - Power up UART 1 DIS = 0x0 - Power down UART 1 |
7 | PWRUART0 | RW | Power up UART Controller 0 EN = 0x1 - Power up UART 0 DIS = 0x0 - Power down UART 0 |
6 | PWRIOM5 | RW | Power up IO Master 5 EN = 0x1 - Power up IO Master 5 DIS = 0x0 - Power down IO Master 5 |
5 | PWRIOM4 | RW | Power up IO Master 4 EN = 0x1 - Power up IO Master 4 DIS = 0x0 - Power down IO Master 4 |
4 | PWRIOM3 | RW | Power up IO Master 3 EN = 0x1 - Power up IO Master 3 DIS = 0x0 - Power down IO Master 3 |
3 | PWRIOM2 | RW | Power up IO Master 2 EN = 0x1 - Power up IO Master 2 DIS = 0x0 - Power down IO Master 2 |
2 | PWRIOM1 | RW | Power up IO Master 1 EN = 0x1 - Power up IO Master 1 DIS = 0x0 - Power down IO Master 1 |
1 | PWRIOM0 | RW | Power up IO Master 0 EN = 0x1 - Power up IO Master 0 DIS = 0x0 - Power down IO Master 0 |
0 | PWRIOS | RW | Power up IO Slave EN = 0x1 - Power up IO slave DIS = 0x0 - Power down IO slave |
Instance 0 Address: | 0x4002100C |
This controls the power down of the SRAM banks in deep sleep mode. If this is set, then the power for that SRAM bank will be gated when the core goes into deep sleep. Upon wake, the data within the SRAMs will be erased. If this is not set, retention voltage will be applied to the SRAM bank when the core goes into deep sleep. Upon wake, the data within the SRAMs are retained. Do not set this if the SRAM bank is used as the target for DMA transfer while CPU in deep sleep.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CACHEPWDSLP
0x0 |
RSVD
0x0 |
FLASH1PWDSLP
0x1 |
FLASH0PWDSLP
0x1 |
SRAMPWDSLP
0x0 |
DTCMPWDSLP
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | CACHEPWDSLP | RW | power down cache in deep sleep EN = 0x1 - Power down cache in deep sleep DIS = 0x0 - Retain cache in deep sleep |
30:15 | RSVD | RO | RESERVED. |
14 | FLASH1PWDSLP | RW | Power-down FLASH1 in deep sleep EN = 0x1 - FLASH1 is powered down during deep sleep DIS = 0x0 - FLASH1 is kept powered on during deep sleep |
13 | FLASH0PWDSLP | RW | Power-down FLASH0 in deep sleep EN = 0x1 - FLASH0 is powered down during deep sleep DIS = 0x0 - FLASH0 is kept powered on during deep sleep |
12:3 | SRAMPWDSLP | RW | Selects which SRAM banks are powered down in deep sleep mode, causing the contents of the bank to be lost. NONE = 0x0 - All banks retained GROUP0 = 0x1 - SRAM GROUP0 powered down (64KB-128KB) GROUP1 = 0x2 - SRAM GROUP1 powered down (128KB-192KB) GROUP2 = 0x4 - SRAM GROUP2 powered down (192KB-256KB) GROUP3 = 0x8 - SRAM GROUP3 powered down (256KB-320KB) GROUP4 = 0x10 - SRAM GROUP4 powered down (320KB-384KB) GROUP5 = 0x20 - SRAM GROUP5 powered down (384KB-448KB) GROUP6 = 0x40 - SRAM GROUP6 powered down (448KB-512KB) GROUP7 = 0x80 - SRAM GROUP7 powered down (512KB-576KB) GROUP8 = 0x100 - SRAM GROUP8 powered down (576KB-672KB) GROUP9 = 0x200 - SRAM GROUP9 powered down (672KB-768KB) SRAM64K = 0x1 - Power-down lower 64k SRAM (64KB-128KB) SRAM128K = 0x3 - Power-down lower 128k SRAM (64KB-192KB) SRAM256K = 0xF - Power-down lower 256k SRAM (64KB-320KB) ALLBUTLOWER64K = 0x3FE - All SRAM banks but lower 64k powered down. ALLBUTLOWER128K = 0x3FC - All banks but lower 128k powered down. ALLBUTLOWER256K = 0x3F0 - All banks but lower 256k powered down. ALL = 0x3FF - All banks powered down. |
2:0 | DTCMPWDSLP | RW | power down DTCM in deep sleep NONE = 0x0 - All DTCM retained GROUP0DTCM0 = 0x1 - Group0_DTCM0 powered down in deep sleep (0KB-8KB) GROUP0DTCM1 = 0x2 - Group0_DTCM1 powered down in deep sleep (8KB-32KB) GROUP0 = 0x3 - Both DTCMs in group0 are powered down in deep sleep (0KB-32KB) ALLBUTGROUP0DTCM0 = 0x6 - Group1 and Group0_DTCM1 are powered down in deep sleep (8KB-64KB) GROUP1 = 0x4 - Group1 DTCM powered down in deep sleep (32KB-64KB) ALL = 0x7 - All DTCMs powered down in deep sleep (0KB-64KB) |
Instance 0 Address: | 0x40021010 |
This register enables the individual banks for the memories. When set, power will be enabled to the banks. This register works in conjunction with the MEMPWDINSLEEP register. When this register is set, then the MEMPWRINSLEEP register will determine whether power is enabled to the SRAMs in deep sleep. If this register is not set, then power will always be disabled to the memory bank.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CACHEB2
0x1 |
CACHEB0
0x1 |
RSVD
0x0 |
FLASH1
0x1 |
FLASH0
0x1 |
SRAM
0x3ff |
DTCM
0x7 |
Bits | Name | RW | Description |
---|---|---|---|
31 | CACHEB2 | RW | Power up Cache Bank 2. This works in conjunction with Cache enable from flash_cache module. To power up cache bank 2, cache has to be enabled and this bit has to be set. EN = 0x1 - Power up Cache Bank 2 DIS = 0x0 - Power down Cache Bank 2 |
30 | CACHEB0 | RW | Power up Cache Bank 0. This works in conjunction with Cache enable from flash_cache module. To power up cache bank 0, cache has to be enabled and this bit has to be set. EN = 0x1 - Power up Cache Bank 0 DIS = 0x0 - Power down Cache Bank 0 |
29:15 | RSVD | RO | RESERVED. |
14 | FLASH1 | RW | Power up FLASH group 1 (1MB-2MB) EN = 0x1 - Power up FLASH group 1 (1MB-2MB) DIS = 0x0 - Power down FLASH group 1 (1MB-2MB) |
13 | FLASH0 | RW | Power up FLASH group 0 (0MB-1MB) EN = 0x1 - Power up FLASH group 0 (0MB-1MB) DIS = 0x0 - Power down FLASH group 0 (0MB-1MB) |
12:3 | SRAM | RW | Power up SRAM groups NONE = 0x0 - Do not power ON any of the SRAM banks GROUP0 = 0x1 - Power ON only SRAM 64KB group0 (addr: 0x10010000 - 0x1001FFFF) GROUP1 = 0x2 - Power ON only SRAM 64KB group1 (addr: 0x10020000 - 0x1002FFFF) GROUP2 = 0x4 - Power ON only SRAM 64KB group2 (addr: 0x10030000 - 0x1003FFFF) GROUP3 = 0x8 - Power ON only SRAM 64KB group3 (addr: 0x10040000 - 0x1004FFFF) GROUP4 = 0x10 - Power ON only SRAM 64KB group4 (addr: 0x10050000 - 0x1005FFFF) GROUP5 = 0x20 - Power ON only SRAM 64KB group5 (addr: 0x10060000 - 0x1006FFFF) GROUP6 = 0x40 - Power ON only SRAM 64KB group6 (addr: 0x10070000 - 0x1007FFFF) GROUP7 = 0x80 - Power ON only SRAM 64KB group7 (addr: 0x10080000 - 0x1008FFFF) GROUP8 = 0x100 - Power ON only SRAM 96KB group8 (addr: 0x10090000 - 0x100A7FFF) GROUP9 = 0x200 - Power ON only SRAM 96KB group9 (addr: 0x100A8000 - 0x100BFFFF) SRAM64K = 0x1 - Power ON only lower 64k (addr: 0x10010000 - 0x1001FFFF) SRAM128K = 0x3 - Power ON only lower 128k (addr: 0x10010000 - 0x1002FFFF) SRAM256K = 0xF - Power ON only lower 256k (addr: 0x10010000 - 0x1004FFFF) SRAM512K = 0xFF - Power ON only lower 512k (addr: 0x10010000 - 0x1008FFFF) ALL = 0x3FF - All SRAM banks (704K) powered ON (addr: 0x10010000 - 0x100BFFFF) |
2:0 | DTCM | RW | Power up DTCM NONE = 0x0 - Do not enable power to any DTCMs GROUP0DTCM0 = 0x1 - Power ON only 8KB GROUP0_DTCM0 (0 - 8KB, addr: 0x10000000 - 0x10001FFF) GROUP0DTCM1 = 0x2 - Power ON only 24KB GROUP0_DTCM1 (8KB - 32KB, addr: 0x10002000 - 0x10007FFF) GROUP0 = 0x3 - Power ON only DTCMs in 32KB group0 (0 - 32KB, addr: 0x10000000 - 0x10007FFF) GROUP1 = 0x4 - Power ON only DTCMs in 32KB group1 (32KB - 64KB, addr: 0x10008000 - 0x1000FFFF) ALL = 0x7 - Power ON all DTCMs (0 - 64KB, addr: 0x10000000 - 0x1000FFFF) |
Instance 0 Address: | 0x40021014 |
It provides the power status for all the memory banks including- caches, FLASH (0 and 1) and all the SRAM groups. The status here should reflect the enable provided by the MEMPWREN register. There may be a lag time between setting the bits in MEMPWREN register and MEMPWRSTATUS register, due to the need to cycle the power gate and isolation sequences to the memory banks.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
CACHEB2
0x0 |
CACHEB0
0x0 |
FLASH1
0x1 |
FLASH0
0x1 |
SRAM9
0x1 |
SRAM8
0x1 |
SRAM7
0x1 |
SRAM6
0x1 |
SRAM5
0x1 |
SRAM4
0x1 |
SRAM3
0x1 |
SRAM2
0x1 |
SRAM1
0x1 |
SRAM0
0x1 |
DTCM1
0x1 |
DTCM01
0x1 |
DTCM00
0x1 |
Bits | Name | RW | Description |
---|---|---|---|
31:17 | RSVD | RO | This bit field is reserved for future use. |
16 | CACHEB2 | RO | This bit is 1 if power is supplied to Cache Bank 2 |
15 | CACHEB0 | RO | This bit is 1 if power is supplied to Cache Bank 0 |
14 | FLASH1 | RO | This bit is 1 if power is supplied to FLASH group 1 |
13 | FLASH0 | RO | This bit is 1 if power is supplied to FLASH group 0 |
12 | SRAM9 | RO | This bit is 1 if power is supplied to SRAM GROUP9 |
11 | SRAM8 | RO | This bit is 1 if power is supplied to SRAM GROUP8 |
10 | SRAM7 | RO | This bit is 1 if power is supplied to SRAM GROUP7 |
9 | SRAM6 | RO | This bit is 1 if power is supplied to SRAM GROUP6 |
8 | SRAM5 | RO | This bit is 1 if power is supplied to SRAM GROUP5 |
7 | SRAM4 | RO | This bit is 1 if power is supplied to SRAM GROUP4 |
6 | SRAM3 | RO | This bit is 1 if power is supplied to SRAM GROUP3 |
5 | SRAM2 | RO | This bit is 1 if power is supplied to SRAM GROUP2 |
4 | SRAM1 | RO | This bit is 1 if power is supplied to SRAM GROUP1 |
3 | SRAM0 | RO | This bit is 1 if power is supplied to SRAM GROUP0 |
2 | DTCM1 | RO | This bit is 1 if power is supplied to DTCM GROUP1 |
1 | DTCM01 | RO | This bit is 1 if power is supplied to DTCM GROUP0_1 |
0 | DTCM00 | RO | This bit is 1 if power is supplied to DTCM GROUP0_0 |
Instance 0 Address: | 0x40021018 |
This provides the power status for the peripheral devices- BLEL, PDM, PDM, MSPI2-0, SCARD, ADC, UART0 and 1, IOM5 to 0, IOSLAVE and MCUL (DMA and Fabrics) and MCUH (ARM core). The status here should reflect the enable provided by the DEVPWREN register. There may be a lag time between setting the bits in DEVPWREN register and DEVPWRSTATUS register, due to the need to cycle the power gate, isolation and reset sequences to the device power domains.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
RSVD
0x0 |
RSVD
0x0 |
RSVD
0x0 |
BLEH
0x0 |
BLEL
0x0 |
PWRPDM
0x0 |
PWRMSPI
0x0 |
PWRADC
0x0 |
HCPC
0x0 |
HCPB
0x0 |
HCPA
0x0 |
MCUH
0x1 |
MCUL
0x1 |
Bits | Name | RW | Description |
---|---|---|---|
31 | RSVD | RO | RESERVED |
30 | RSVD | RO | RESERVED |
29 | RSVD | RO | RESERVED |
28:10 | RSVD | RO | This bit field is reserved for future use. |
9 | BLEH | RO | This bit is 1 if power is supplied to BLEH |
8 | BLEL | RO | This bit is 1 if power is supplied to BLEL |
7 | PWRPDM | RO | This bit is 1 if power is supplied to PDM |
6 | PWRMSPI | RO | This bit is 1 if power is supplied to MSPI |
5 | PWRADC | RO | This bit is 1 if power is supplied to ADC |
4 | HCPC | RO | This bit is 1 if power is supplied to HCPC domain (IO MASTER4, 5, 6) |
3 | HCPB | RO | This bit is 1 if power is supplied to HCPB domain (IO MASTER 0, 1, 2) |
2 | HCPA | RO | This bit is 1 if power is supplied to HCPA domain (IO SLAVE, UART0, UART1, SCARD) |
1 | MCUH | RO | This bit is 1 if power is supplied to MCUH |
0 | MCUL | RO | This bit is 1 if power is supplied to MCUL |
Instance 0 Address: | 0x4002101C |
This register provides additional fine-tune power management controls for the SRAMs and the SRAM controller. This includes enabling light sleep for the SRAM and TCM banks, and clock gating for reduced dynamic power.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
SRAMLIGHTSLEEP
0x0 |
RSVD
0x0 |
SRAMMASTERCLKGATE
0x0 |
SRAMCLKGATE
0x0 |
RSVD
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:20 | RSVD | RO | This bit field is reserved for future use. |
19:8 | SRAMLIGHTSLEEP | RW | Light Sleep enable for each TCM/SRAM bank. When 1, corresponding bank will be put into light sleep. For optimal power, banks should be put into light sleep while the system is active but the bank has minimal or no accesses. ALL = 0xFF - Enable LIGHT SLEEP for ALL SRAMs DIS = 0x0 - Disables LIGHT SLEEP for ALL SRAMs |
7:3 | RSVD | RO | This bit field is reserved for future use. |
2 | SRAMMASTERCLKGATE | RW | This bit is 1 when the master clock gate is enabled (top-level clock gate for entire SRAM block) EN = 0x1 - Enable Master SRAM Clock Gate DIS = 0x0 - Disables Master SRAM Clock Gating |
1 | SRAMCLKGATE | RW | This bit is 1 if clock gating is allowed for individual system SRAMs EN = 0x1 - Enable Individual SRAM Clock Gating DIS = 0x0 - Disables Individual SRAM Clock Gating |
0 | RSVD | RO | This bit field is reserved for future use. |
Instance 0 Address: | 0x40021020 |
This provides the power status for various blocks within the ADC. These status comes directly from the ADC module and is captured through this interface.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
REFBUFPWD
0x1 |
REFKEEPPWD
0x1 |
VBATPWD
0x1 |
VPTATPWD
0x1 |
BGTPWD
0x1 |
ADCPWD
0x1 |
Bits | Name | RW | Description |
---|---|---|---|
31:6 | RSVD | RO | RESERVED. |
5 | REFBUFPWD | RO | This bit indicates that the ADC REFBUF is powered down |
4 | REFKEEPPWD | RO | This bit indicates that the ADC REFKEEP is powered down |
3 | VBATPWD | RO | This bit indicates that the ADC VBAT resistor divider is powered down |
2 | VPTATPWD | RO | This bit indicates that the ADC temperature sensor input buffer is powered down |
1 | BGTPWD | RO | This bit indicates that the ADC Band Gap is powered down |
0 | ADCPWD | RO | This bit indicates that the ADC is powered down |
Instance 0 Address: | 0x40021024 |
This register includes additional debug control bits. This is an internal Ambiq-only register. Customers should not attempt to change this or else functionality cannot be guaranteed.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
RSVD08
0x0 |
RSVD07
0x0 |
MEMVRLPBLE
0x0 |
RSVD04
0x0 |
FORCEMEMVRLPTIMERS
0x0 |
RSVD02
0x0 |
RSVD01
0x0 |
RSVD00
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:9 | RSVD | RO | RESERVED. |
8 | RSVD08 | RW | RESERVED - this field should not be modified |
7 | RSVD07 | RW | RESERVED - this field should not be modified |
6 | MEMVRLPBLE | RW | Control Bit to let Mem VR go to lp mode in deep sleep even when BLEL or BLEH is powered on given none of the other domains require it. EN = 0x1 - Mem VR can go to lp mode even when BLE is powered on. DIS = 0x0 - Mem VR will stay in active mode when BLE is powered on. |
5:4 | RSVD04 | RW | RESERVED - this field should not be modified |
3 | FORCEMEMVRLPTIMERS | RW | Control Bit to force Mem VR to LP mode in deep sleep even when hfrc based ctimer or stimer is running. |
2 | RSVD02 | RW | RESERVED - this field should not be modified |
1 | RSVD01 | RW | RESERVED - this field should not be modified |
0 | RSVD00 | RW | RESERVED - this field should not be modified |
Instance 0 Address: | 0x40021028 |
This register controls which feature trigger will result in an event to the CPU. It includes all the power on status for the core domains, as well as the Burst event. If any bits are set, then if the domain is turned on, it will result in an event to the ARM core.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
BURSTEVEN
0x0 |
BURSTFEATUREEVEN
0x0 |
BLEFEATUREEVEN
0x0 |
RSVD
0x0 |
BLELEVEN
0x0 |
PDMEVEN
0x0 |
MSPIEVEN
0x0 |
ADCEVEN
0x0 |
HCPCEVEN
0x0 |
HCPBEVEN
0x0 |
HCPAEVEN
0x0 |
MCUHEVEN
0x0 |
MCULEVEN
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | BURSTEVEN | RW | Control BURST status event EN = 0x1 - Enable BURST status event DIS = 0x0 - Disable BURST status event |
30 | BURSTFEATUREEVEN | RW | Control BURSTFEATURE status event EN = 0x1 - Enable BURSTFEATURE status event DIS = 0x0 - Disable BURSTFEATURE status event |
29 | BLEFEATUREEVEN | RW | Control BLEFEATURE status event EN = 0x1 - Enable BLEFEATURE status event DIS = 0x0 - Disable BLEFEATURE status event |
28:9 | RSVD | RO | RESERVED. |
8 | BLELEVEN | RW | Control BLE power-on status event EN = 0x1 - Enable BLE power-on status event DIS = 0x0 - Disable BLE power-on status event |
7 | PDMEVEN | RW | Control PDM power-on status event EN = 0x1 - Enable PDM power-on status event DIS = 0x0 - Disable PDM power-on status event |
6 | MSPIEVEN | RW | Control MSPI power-on status event EN = 0x1 - Enable MSPI power-on status event DIS = 0x0 - Disable MSPI power-on status event |
5 | ADCEVEN | RW | Control ADC power-on status event EN = 0x1 - Enable ADC power-on status event DIS = 0x0 - Disable ADC power-on status event |
4 | HCPCEVEN | RW | Control HCPC power-on status event EN = 0x1 - Enable HCPC power-on status event DIS = 0x0 - Disable HCPC power-on status event |
3 | HCPBEVEN | RW | Control HCPB power-on status event EN = 0x1 - Enable HCPB power-on status event DIS = 0x0 - Disable HCPB power-on status event |
2 | HCPAEVEN | RW | Control HCPA power-on status event EN = 0x1 - Enable HCPA power-on status event DIS = 0x0 - Disable HCPA power-on status event |
1 | MCUHEVEN | RW | Control MCUH power-on status event EN = 0x1 - Enable MCHU power-on status event DIS = 0x0 - Disable MCUH power-on status event |
0 | MCULEVEN | RW | Control MCUL power-on status event EN = 0x1 - Enable MCUL power-on status event DIS = 0x0 - Disable MCUL power-on status event |
Instance 0 Address: | 0x4002102C |
This register controls which power enable for the memories will result in an event to the CPU. It includes all the power on status for the memory domains. If any bits are set, then if the domain is turned on, it will result in an event to the ARM core.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CACHEB2EN
0x0 |
CACHEB0EN
0x0 |
RSVD
0x0 |
FLASH1EN
0x0 |
FLASH0EN
0x0 |
SRAMEN
0x0 |
DTCMEN
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | CACHEB2EN | RW | Control CACHEB2 power-on status event EN = 0x1 - Enable CACHE BANK 2 status event DIS = 0x0 - Disable CACHE BANK 2 status event |
30 | CACHEB0EN | RW | Control CACHE BANK 0 power-on status event EN = 0x1 - Enable CACHE BANK 0 status event DIS = 0x0 - Disable CACHE BANK 0 status event |
29:15 | RSVD | RO | RESERVED. |
14 | FLASH1EN | RW | Control FLASH power-on status event EN = 0x1 - Enable FLASH status event DIS = 0x0 - Disables FLASH status event |
13 | FLASH0EN | RW | Control FLASH power-on status event EN = 0x1 - Enable FLASH status event DIS = 0x0 - Disables FLASH status event |
12:3 | SRAMEN | RW | Control SRAM power-on status event NONE = 0x0 - Disable SRAM power-on status event GROUP0EN = 0x1 - Enable SRAM group0 (0KB-32KB) power on status event GROUP1EN = 0x2 - Enable SRAM group1 (32KB-64KB) power on status event GROUP2EN = 0x4 - Enable SRAM group2 (64KB-96KB) power on status event GROUP3EN = 0x8 - Enable SRAM group3 (96KB-128KB) power on status event GROUP4EN = 0x10 - Enable SRAM group4 (128KB-160KB) power on status event GROUP5EN = 0x20 - Enable SRAM group5 (160KB-192KB) power on status event GROUP6EN = 0x40 - Enable SRAM group6 (192KB-224KB) power on status event GROUP7EN = 0x80 - Enable SRAM group7 (224KB-256KB) power on status event GROUP8EN = 0x100 - Enable SRAM group8 (256KB-288KB) power on status event GROUP9EN = 0x200 - Enable SRAM group9 (288KB-320KB) power on status event |
2:0 | DTCMEN | RW | Enable DTCM power-on status event NONE = 0x0 - Do not enable DTCM power-on status event GROUP0DTCM0EN = 0x1 - Enable GROUP0_DTCM0 power on status event GROUP0DTCM1EN = 0x2 - Enable GROUP0_DTCM1 power on status event GROUP0EN = 0x3 - Enable DTCMs in group0 power on status event GROUP1EN = 0x4 - Enable DTCMs in group1 power on status event ALL = 0x7 - Enable all DTCM power on status event |