Apollo Register Documentation  v${version}
ADC - Analog Digital Converter Control

ADC Register Index

  0x00000000:   CFG - Configuration Register
  0x00000004:   STAT - ADC Power Status
  0x00000008:   SWT - Software trigger
  0x0000000C:   SL0CFG - Slot 0 Configuration Register
  0x00000010:   SL1CFG - Slot 1 Configuration Register
  0x00000014:   SL2CFG - Slot 2 Configuration Register
  0x00000018:   SL3CFG - Slot 3 Configuration Register
  0x0000001C:   SL4CFG - Slot 4 Configuration Register
  0x00000020:   SL5CFG - Slot 5 Configuration Register
  0x00000024:   SL6CFG - Slot 6 Configuration Register
  0x00000028:   SL7CFG - Slot 7 Configuration Register
  0x0000002C:   WULIM - Window Comparator Upper Limits Register
  0x00000030:   WLLIM - Window Comparator Lower Limits Register
  0x00000034:   SCWLIM - Scale Window Comparator Limits
  0x00000038:   FIFO - FIFO Data and Valid Count Register
  0x0000003C:   FIFOPR - FIFO Data and Valid Count Register
  0x00000200:   INTEN - ADC Interrupt registers: Enable
  0x00000204:   INTSTAT - ADC Interrupt registers: Status
  0x00000208:   INTCLR - ADC Interrupt registers: Clear
  0x0000020C:   INTSET - ADC Interrupt registers: Set
  0x00000240:   DMATRIGEN - DMA Trigger Enable Register
  0x00000244:   DMATRIGSTAT - DMA Trigger Status Register
  0x00000280:   DMACFG - DMA Configuration Register
  0x00000288:   DMATOTCOUNT - DMA Total Transfer Count
  0x0000028C:   DMATARGADDR - DMA Target Address Register
  0x00000290:   DMASTAT - DMA Status Register

CFG - Configuration Register

Address:

  Instance 0 Address:   0x50010000

Description:

The ADC Configuration Register contains the software control for selecting the clock frequency used for the SAR conversions, the trigger polarity, the trigger select, the reference voltage select, the low power mode, the operating mode (single scan per trigger vs. repeating mode) and ADC enable.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CLKSEL
0x0
RSVD
0x0
TRIGPOL
0x0
TRIGSEL
0x0
RSVD
0x0
DFIFORDEN
0x0
RSVD
0x0
REFSEL
0x0
RSVD
0x0
CKMODE
0x0
LPMODE
0x0
RPTEN
0x0
RSVD
0x0
ADCEN
0x0

Bits Name RW Description
31:26 RSVD RO RESERVED.

25:24 CLKSEL RW Select the source and frequency for the ADC clock. All values not enumerated below are undefined.

OFF = 0x0 - Off mode. The HFRC or HFRC_DIV2 clock must be selected for the ADC to function. The ADC controller automatically shuts off the clock in it's low power modes. When setting ADCEN to '0', the CLKSEL should remain set to one of the two clock selects for proper power down sequencing.
HFRC = 0x1 - HFRC Core Clock divided by (CORESEL+1)
HFRC_DIV2 = 0x2 - HFRC Core Clock / 2 further divided by (CORESEL+1)
23:20 RSVD RO RESERVED.

19 TRIGPOL RW This bit selects the ADC trigger polarity for external off chip triggers.

RISING_EDGE = 0x0 - Trigger on rising edge.
FALLING_EDGE = 0x1 - Trigger on falling edge.
18:16 TRIGSEL RW Select the ADC trigger source.

EXT0 = 0x0 - Off chip External Trigger0 (ADC_ET0)
EXT1 = 0x1 - Off chip External Trigger1 (ADC_ET1)
EXT2 = 0x2 - Off chip External Trigger2 (ADC_ET2)
EXT3 = 0x3 - Off chip External Trigger3 (ADC_ET3)
VCOMP = 0x4 - Voltage Comparator Output
SWT = 0x7 - Software Trigger
15:13 RSVD RO RESERVED.

12 DFIFORDEN RW Destructive FIFO Read Enable. Setting this will enable FIFO pop upon reading the FIFOPR register.

DIS = 0x0 - Destructive Reads are prevented. Reads to the FIFOPR register will not POP an entry off the FIFO.
EN = 0x1 - Reads to the FIFOPR register will automatically pop an entry off the FIFO.
11:10 RSVD RO RESERVED.

9:8 REFSEL RW Select the ADC reference voltage.

INT2P0 = 0x0 - Internal 2.0V Bandgap Reference Voltage
INT1P5 = 0x1 - Internal 1.5V Bandgap Reference Voltage
EXT2P0 = 0x2 - Off Chip 2.0V Reference
EXT1P5 = 0x3 - Off Chip 1.5V Reference
7:5 RSVD RO RESERVED.

4 CKMODE RW Clock mode register

LPCKMODE = 0x0 - Disable the clock between scans for LPMODE0. Set LPCKMODE to 0x1 while configuring the ADC.
LLCKMODE = 0x1 - Low Latency Clock Mode. When set, HFRC and the adc_clk will remain on while in functioning in LPMODE0.
3 LPMODE RW Select power mode to enter between active scans.

MODE0 = 0x0 - Low Power Mode 0. Leaves the ADC fully powered between scans with minimum latency between a trigger event and sample data collection.
MODE1 = 0x1 - Low Power Mode 1. Powers down all circuity and clocks associated with the ADC until the next trigger event. Between scans, the reference buffer requires up to 50us of delay from a scan trigger event before the conversion will commence while operating in this mode.
2 RPTEN RW This bit enables Repeating Scan Mode.

SINGLE_SCAN = 0x0 - In Single Scan Mode, the ADC will complete a single scan upon each trigger event.
REPEATING_SCAN = 0x1 - In Repeating Scan Mode, the ADC will complete it's first scan upon the initial trigger event and all subsequent scans will occur at regular intervals defined by the configuration programmed for the CTTMRA3 internal timer until the timer is disabled or the ADC is disabled. When disabling the ADC (setting ADCEN to '0'), the RPTEN bit should be cleared.
1 RSVD RO RESERVED.

0 ADCEN RW This bit enables the ADC module. While the ADC is enabled, the ADCCFG and SLOT Configuration register settings must remain stable and unchanged. All configuration register settings, slot configuration settings and window comparison settings should be written prior to setting the ADCEN bit to '1'.

DIS = 0x0 - Disable the ADC module.
EN = 0x1 - Enable the ADC module.

STAT - ADC Power Status

Address:

  Instance 0 Address:   0x50010004

Description:

This register indicates the basic power status for the ADC. For detailed power status, see the power control power status register. ADC power mode 0 indicates the ADC is in it's full power state and is ready to process scans. ADC Power mode 1 indicates the ADC enabled and in a low power state.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
PWDSTAT
0x0

Bits Name RW Description
31:1 RSVD RO RESERVED.

0 PWDSTAT RO Indicates the power-status of the ADC.

ON = 0x0 - Powered on.
POWERED_DOWN = 0x1 - ADC Low Power Mode 1.

SWT - Software trigger

Address:

  Instance 0 Address:   0x50010008

Description:

This register enables initiating an ADC scan through software.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
SWT
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED.

7:0 SWT RW Writing 0x37 to this register generates a software trigger.

GEN_SW_TRIGGER = 0x37 - Writing this value generates a software trigger.

SL0CFG - Slot 0 Configuration Register

Address:

  Instance 0 Address:   0x5001000C

Description:

Slot 0 Configuration Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADSEL0
0x0
RSVD
0x0
PRMODE0
0x0
RSVD
0x0
CHSEL0
0x0
RSVD
0x0
WCEN0
0x0
SLEN0
0x0

Bits Name RW Description
31:27 RSVD RO RESERVED.

26:24 ADSEL0 RW Select the number of measurements to average in the accumulate divide module for this slot.

AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:18 RSVD RO RESERVED.

17:16 PRMODE0 RW Set the Precision Mode For Slot.

P14B = 0x0 - 14-bit precision mode
P12B = 0x1 - 12-bit precision mode
P10B = 0x2 - 10-bit precision mode
P8B = 0x3 - 8-bit precision mode
15:12 RSVD RO RESERVED.

11:8 CHSEL0 RW Select one of the 14 channel inputs for this slot.

SE0 = 0x0 - single ended external GPIO connection to pad16.
SE1 = 0x1 - single ended external GPIO connection to pad29.
SE2 = 0x2 - single ended external GPIO connection to pad11.
SE3 = 0x3 - single ended external GPIO connection to pad31.
SE4 = 0x4 - single ended external GPIO connection to pad32.
SE5 = 0x5 - single ended external GPIO connection to pad33.
SE6 = 0x6 - single ended external GPIO connection to pad34.
SE7 = 0x7 - single ended external GPIO connection to pad35.
SE8 = 0x8 - single ended external GPIO connection to pad13.
SE9 = 0x9 - single ended external GPIO connection to pad12.
DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).
DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).
TEMP = 0xC - internal temperature sensor.
BATT = 0xD - internal voltage divide-by-3 connection.
VSS = 0xE - Input VSS
7:2 RSVD RO RESERVED.

1 WCEN0 RW This bit enables the window compare function for slot 0.

WCEN = 0x1 - Enable the window compare for slot 0.
0 SLEN0 RW This bit enables slot 0 for ADC conversions.

SLEN = 0x1 - Enable slot 0 for ADC conversions.

SL1CFG - Slot 1 Configuration Register

Address:

  Instance 0 Address:   0x50010010

Description:

Slot 1 Configuration Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADSEL1
0x0
RSVD
0x0
PRMODE1
0x0
RSVD
0x0
CHSEL1
0x0
RSVD
0x0
WCEN1
0x0
SLEN1
0x0

Bits Name RW Description
31:27 RSVD RO RESERVED.

26:24 ADSEL1 RW Select the number of measurements to average in the accumulate divide module for this slot.

AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:18 RSVD RO RESERVED.

17:16 PRMODE1 RW Set the Precision Mode For Slot.

P14B = 0x0 - 14-bit precision mode
P12B = 0x1 - 12-bit precision mode
P10B = 0x2 - 10-bit precision mode
P8B = 0x3 - 8-bit precision mode
15:12 RSVD RO RESERVED.

11:8 CHSEL1 RW Select one of the 14 channel inputs for this slot.

SE0 = 0x0 - single ended external GPIO connection to pad16.
SE1 = 0x1 - single ended external GPIO connection to pad29.
SE2 = 0x2 - single ended external GPIO connection to pad11.
SE3 = 0x3 - single ended external GPIO connection to pad31.
SE4 = 0x4 - single ended external GPIO connection to pad32.
SE5 = 0x5 - single ended external GPIO connection to pad33.
SE6 = 0x6 - single ended external GPIO connection to pad34.
SE7 = 0x7 - single ended external GPIO connection to pad35.
SE8 = 0x8 - single ended external GPIO connection to pad13.
SE9 = 0x9 - single ended external GPIO connection to pad12.
DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).
DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).
TEMP = 0xC - internal temperature sensor.
BATT = 0xD - internal voltage divide-by-3 connection.
VSS = 0xE - Input VSS
7:2 RSVD RO RESERVED.

1 WCEN1 RW This bit enables the window compare function for slot 1.

WCEN = 0x1 - Enable the window compare for slot 1.
0 SLEN1 RW This bit enables slot 1 for ADC conversions.

SLEN = 0x1 - Enable slot 1 for ADC conversions.

SL2CFG - Slot 2 Configuration Register

Address:

  Instance 0 Address:   0x50010014

Description:

Slot 2 Configuration Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADSEL2
0x0
RSVD
0x0
PRMODE2
0x0
RSVD
0x0
CHSEL2
0x0
RSVD
0x0
WCEN2
0x0
SLEN2
0x0

Bits Name RW Description
31:27 RSVD RO RESERVED.

26:24 ADSEL2 RW Select the number of measurements to average in the accumulate divide module for this slot.

AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:18 RSVD RO RESERVED.

17:16 PRMODE2 RW Set the Precision Mode For Slot.

P14B = 0x0 - 14-bit precision mode
P12B = 0x1 - 12-bit precision mode
P10B = 0x2 - 10-bit precision mode
P8B = 0x3 - 8-bit precision mode
15:12 RSVD RO RESERVED.

11:8 CHSEL2 RW Select one of the 14 channel inputs for this slot.

SE0 = 0x0 - single ended external GPIO connection to pad16.
SE1 = 0x1 - single ended external GPIO connection to pad29.
SE2 = 0x2 - single ended external GPIO connection to pad11.
SE3 = 0x3 - single ended external GPIO connection to pad31.
SE4 = 0x4 - single ended external GPIO connection to pad32.
SE5 = 0x5 - single ended external GPIO connection to pad33.
SE6 = 0x6 - single ended external GPIO connection to pad34.
SE7 = 0x7 - single ended external GPIO connection to pad35.
SE8 = 0x8 - single ended external GPIO connection to pad13.
SE9 = 0x9 - single ended external GPIO connection to pad12.
DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).
DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).
TEMP = 0xC - internal temperature sensor.
BATT = 0xD - internal voltage divide-by-3 connection.
VSS = 0xE - Input VSS
7:2 RSVD RO RESERVED.

1 WCEN2 RW This bit enables the window compare function for slot 2.

WCEN = 0x1 - Enable the window compare for slot 2.
0 SLEN2 RW This bit enables slot 2 for ADC conversions.

SLEN = 0x1 - Enable slot 2 for ADC conversions.

SL3CFG - Slot 3 Configuration Register

Address:

  Instance 0 Address:   0x50010018

Description:

Slot 3 Configuration Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADSEL3
0x0
RSVD
0x0
PRMODE3
0x0
RSVD
0x0
CHSEL3
0x0
RSVD
0x0
WCEN3
0x0
SLEN3
0x0

Bits Name RW Description
31:27 RSVD RO RESERVED.

26:24 ADSEL3 RW Select the number of measurements to average in the accumulate divide module for this slot.

AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:18 RSVD RO RESERVED.

17:16 PRMODE3 RW Set the Precision Mode For Slot.

P14B = 0x0 - 14-bit precision mode
P12B = 0x1 - 12-bit precision mode
P10B = 0x2 - 10-bit precision mode
P8B = 0x3 - 8-bit precision mode
15:12 RSVD RO RESERVED.

11:8 CHSEL3 RW Select one of the 14 channel inputs for this slot.

SE0 = 0x0 - single ended external GPIO connection to pad16.
SE1 = 0x1 - single ended external GPIO connection to pad29.
SE2 = 0x2 - single ended external GPIO connection to pad11.
SE3 = 0x3 - single ended external GPIO connection to pad31.
SE4 = 0x4 - single ended external GPIO connection to pad32.
SE5 = 0x5 - single ended external GPIO connection to pad33.
SE6 = 0x6 - single ended external GPIO connection to pad34.
SE7 = 0x7 - single ended external GPIO connection to pad35.
SE8 = 0x8 - single ended external GPIO connection to pad13.
SE9 = 0x9 - single ended external GPIO connection to pad12.
DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).
DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).
TEMP = 0xC - internal temperature sensor.
BATT = 0xD - internal voltage divide-by-3 connection.
VSS = 0xE - Input VSS
7:2 RSVD RO RESERVED.

1 WCEN3 RW This bit enables the window compare function for slot 3.

WCEN = 0x1 - Enable the window compare for slot 3.
0 SLEN3 RW This bit enables slot 3 for ADC conversions.

SLEN = 0x1 - Enable slot 3 for ADC conversions.

SL4CFG - Slot 4 Configuration Register

Address:

  Instance 0 Address:   0x5001001C

Description:

Slot 4 Configuration Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADSEL4
0x0
RSVD
0x0
PRMODE4
0x0
RSVD
0x0
CHSEL4
0x0
RSVD
0x0
WCEN4
0x0
SLEN4
0x0

Bits Name RW Description
31:27 RSVD RO RESERVED.

26:24 ADSEL4 RW Select the number of measurements to average in the accumulate divide module for this slot.

AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:18 RSVD RO RESERVED.

17:16 PRMODE4 RW Set the Precision Mode For Slot.

P14B = 0x0 - 14-bit precision mode
P12B = 0x1 - 12-bit precision mode
P10B = 0x2 - 10-bit precision mode
P8B = 0x3 - 8-bit precision mode
15:12 RSVD RO RESERVED.

11:8 CHSEL4 RW Select one of the 14 channel inputs for this slot.

SE0 = 0x0 - single ended external GPIO connection to pad16.
SE1 = 0x1 - single ended external GPIO connection to pad29.
SE2 = 0x2 - single ended external GPIO connection to pad11.
SE3 = 0x3 - single ended external GPIO connection to pad31.
SE4 = 0x4 - single ended external GPIO connection to pad32.
SE5 = 0x5 - single ended external GPIO connection to pad33.
SE6 = 0x6 - single ended external GPIO connection to pad34.
SE7 = 0x7 - single ended external GPIO connection to pad35.
SE8 = 0x8 - single ended external GPIO connection to pad13.
SE9 = 0x9 - single ended external GPIO connection to pad12.
DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).
DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).
TEMP = 0xC - internal temperature sensor.
BATT = 0xD - internal voltage divide-by-3 connection.
VSS = 0xE - Input VSS
7:2 RSVD RO RESERVED.

1 WCEN4 RW This bit enables the window compare function for slot 4.

WCEN = 0x1 - Enable the window compare for slot 4.
0 SLEN4 RW This bit enables slot 4 for ADC conversions.

SLEN = 0x1 - Enable slot 4 for ADC conversions.

SL5CFG - Slot 5 Configuration Register

Address:

  Instance 0 Address:   0x50010020

Description:

Slot 5 Configuration Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADSEL5
0x0
RSVD
0x0
PRMODE5
0x0
RSVD
0x0
CHSEL5
0x0
RSVD
0x0
WCEN5
0x0
SLEN5
0x0

Bits Name RW Description
31:27 RSVD RO RESERVED.

26:24 ADSEL5 RW Select number of measurements to average in the accumulate divide module for this slot.

AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:18 RSVD RO RESERVED.

17:16 PRMODE5 RW Set the Precision Mode For Slot.

P14B = 0x0 - 14-bit precision mode
P12B = 0x1 - 12-bit precision mode
P10B = 0x2 - 10-bit precision mode
P8B = 0x3 - 8-bit precision mode
15:12 RSVD RO RESERVED.

11:8 CHSEL5 RW Select one of the 14 channel inputs for this slot.

SE0 = 0x0 - single ended external GPIO connection to pad16.
SE1 = 0x1 - single ended external GPIO connection to pad29.
SE2 = 0x2 - single ended external GPIO connection to pad11.
SE3 = 0x3 - single ended external GPIO connection to pad31.
SE4 = 0x4 - single ended external GPIO connection to pad32.
SE5 = 0x5 - single ended external GPIO connection to pad33.
SE6 = 0x6 - single ended external GPIO connection to pad34.
SE7 = 0x7 - single ended external GPIO connection to pad35.
SE8 = 0x8 - single ended external GPIO connection to pad13.
SE9 = 0x9 - single ended external GPIO connection to pad12.
DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).
DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).
TEMP = 0xC - internal temperature sensor.
BATT = 0xD - internal voltage divide-by-3 connection.
VSS = 0xE - Input VSS
7:2 RSVD RO RESERVED.

1 WCEN5 RW This bit enables the window compare function for slot 5.

WCEN = 0x1 - Enable the window compare for slot 5.
0 SLEN5 RW This bit enables slot 5 for ADC conversions.

SLEN = 0x1 - Enable slot 5 for ADC conversions.

SL6CFG - Slot 6 Configuration Register

Address:

  Instance 0 Address:   0x50010024

Description:

Slot 6 Configuration Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADSEL6
0x0
RSVD
0x0
PRMODE6
0x0
RSVD
0x0
CHSEL6
0x0
RSVD
0x0
WCEN6
0x0
SLEN6
0x0

Bits Name RW Description
31:27 RSVD RO RESERVED.

26:24 ADSEL6 RW Select the number of measurements to average in the accumulate divide module for this slot.

AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:18 RSVD RO RESERVED.

17:16 PRMODE6 RW Set the Precision Mode For Slot.

P14B = 0x0 - 14-bit precision mode
P12B = 0x1 - 12-bit precision mode
P10B = 0x2 - 10-bit precision mode
P8B = 0x3 - 8-bit precision mode
15:12 RSVD RO RESERVED.

11:8 CHSEL6 RW Select one of the 14 channel inputs for this slot.

SE0 = 0x0 - single ended external GPIO connection to pad16.
SE1 = 0x1 - single ended external GPIO connection to pad29.
SE2 = 0x2 - single ended external GPIO connection to pad11.
SE3 = 0x3 - single ended external GPIO connection to pad31.
SE4 = 0x4 - single ended external GPIO connection to pad32.
SE5 = 0x5 - single ended external GPIO connection to pad33.
SE6 = 0x6 - single ended external GPIO connection to pad34.
SE7 = 0x7 - single ended external GPIO connection to pad35.
SE8 = 0x8 - single ended external GPIO connection to pad13.
SE9 = 0x9 - single ended external GPIO connection to pad12.
DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).
DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).
TEMP = 0xC - internal temperature sensor.
BATT = 0xD - internal voltage divide-by-3 connection.
VSS = 0xE - Input VSS
7:2 RSVD RO RESERVED.

1 WCEN6 RW This bit enables the window compare function for slot 6.

WCEN = 0x1 - Enable the window compare for slot 6.
0 SLEN6 RW This bit enables slot 6 for ADC conversions.

SLEN = 0x1 - Enable slot 6 for ADC conversions.

SL7CFG - Slot 7 Configuration Register

Address:

  Instance 0 Address:   0x50010028

Description:

Slot 7 Configuration Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADSEL7
0x0
RSVD
0x0
PRMODE7
0x0
RSVD
0x0
CHSEL7
0x0
RSVD
0x0
WCEN7
0x0
SLEN7
0x0

Bits Name RW Description
31:27 RSVD RO RESERVED.

26:24 ADSEL7 RW Select the number of measurements to average in the accumulate divide module for this slot.

AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:18 RSVD RO RESERVED.

17:16 PRMODE7 RW Set the Precision Mode For Slot.

P14B = 0x0 - 14-bit precision mode
P12B = 0x1 - 12-bit precision mode
P10B = 0x2 - 10-bit precision mode
P8B = 0x3 - 8-bit precision mode
15:12 RSVD RO RESERVED.

11:8 CHSEL7 RW Select one of the 14 channel inputs for this slot.

SE0 = 0x0 - single ended external GPIO connection to pad16.
SE1 = 0x1 - single ended external GPIO connection to pad29.
SE2 = 0x2 - single ended external GPIO connection to pad11.
SE3 = 0x3 - single ended external GPIO connection to pad31.
SE4 = 0x4 - single ended external GPIO connection to pad32.
SE5 = 0x5 - single ended external GPIO connection to pad33.
SE6 = 0x6 - single ended external GPIO connection to pad34.
SE7 = 0x7 - single ended external GPIO connection to pad35.
SE8 = 0x8 - single ended external GPIO connection to pad13.
SE9 = 0x9 - single ended external GPIO connection to pad12.
DF0 = 0xA - differential external GPIO connections to pad12(N) and pad13(P).
DF1 = 0xB - differential external GPIO connections to pad15(N) and pad14(P).
TEMP = 0xC - internal temperature sensor.
BATT = 0xD - internal voltage divide-by-3 connection.
VSS = 0xE - Input VSS
7:2 RSVD RO RESERVED.

1 WCEN7 RW This bit enables the window compare function for slot 7.

WCEN = 0x1 - Enable the window compare for slot 7.
0 SLEN7 RW This bit enables slot 7 for ADC conversions.

SLEN = 0x1 - Enable slot 7 for ADC conversions.

WULIM - Window Comparator Upper Limits Register

Address:

  Instance 0 Address:   0x5001002C

Description:

Window Comparator Upper Limits Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ULIM
0x0

Bits Name RW Description
31:20 RSVD RO RESERVED.

19:0 ULIM RW Sets the upper limit for the window comparator.


WLLIM - Window Comparator Lower Limits Register

Address:

  Instance 0 Address:   0x50010030

Description:

Window Comparator Lower Limits Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
LLIM
0x0

Bits Name RW Description
31:20 RSVD RO RESERVED.

19:0 LLIM RW Sets the lower limit for the window comparator.


SCWLIM - Scale Window Comparator Limits

Address:

  Instance 0 Address:   0x50010034

Description:

Scale Window Comparator Limits

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
SCWLIMEN
0x0

Bits Name RW Description
31:1 RSVD RO RESERVED.

0 SCWLIMEN RW Scale the window limits compare values per precision mode. When set to 0x0 (default), the values in the 20-bit limits registers will compare directly with the FIFO values regardless of the precision mode the slot is configured to. When set to 0x1, the compare values will be divided by the difference in precision bits while performing the window limit comparisons.


FIFO - FIFO Data and Valid Count Register

Address:

  Instance 0 Address:   0x50010038

Description:

The ADC FIFO Register contains the slot number and FIFO data for the oldest conversion data in the FIFO. The COUNT field indicates the total number of valid entries in the FIFO. A write to this register will pop one of the FIFO entries off the FIFO and decrease the COUNT by 1 if the COUNT is greater than zero.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
SLOTNUM
0x0
COUNT
0x0
DATA
0x0

Bits Name RW Description
31 RSVD RO RESERVED.

30:28 SLOTNUM RO Slot number associated with this FIFO data.

27:20 COUNT RO Number of valid entries in the ADC FIFO.

19:0 DATA RO Oldest data in the FIFO.


FIFOPR - FIFO Data and Valid Count Register

Address:

  Instance 0 Address:   0x5001003C

Description:

This is a Pop Read mirrored copy of the ADCFIFO register with the only difference being that reading this register will result in a simultaneous FIFO POP which is also achieved by writing to the ADCFIFO Register. Note: The DFIFORDEN bit must be set in the CFG register for the the destructive read to be enabled.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVDPR
0x0
SLOTNUMPR
0x0
COUNT
0x0
DATA
0x0

Bits Name RW Description
31 RSVDPR RO RESERVED.

30:28 SLOTNUMPR RO Slot number associated with this FIFO data.

27:20 COUNT RO Number of valid entries in the ADC FIFO.

19:0 DATA RO Oldest data in the FIFO.


INTEN - ADC Interrupt registers: Enable

Address:

  Instance 0 Address:   0x50010200

Description:

Set bits in this register to allow this module to generate the corresponding interrupt.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DERR
0x0
DCMP
0x0
WCINC
0x0
WCEXC
0x0
FIFOOVR2
0x0
FIFOOVR1
0x0
SCNCMP
0x0
CNVCMP
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED.

7 DERR RW DMA Error Condition

DMAERROR = 0x1 - DMA Error Condition Occurred
6 DCMP RW DMA Transfer Complete

DMACOMPLETE = 0x1 - DMA Completed a transfer
5 WCINC RW Window comparator voltage incursion interrupt.

WCINCINT = 0x1 - Window comparator voltage incursion interrupt.
4 WCEXC RW Window comparator voltage excursion interrupt.

WCEXCINT = 0x1 - Window comparator voltage excursion interrupt.
3 FIFOOVR2 RW FIFO 100 percent full interrupt.

FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt.
2 FIFOOVR1 RW FIFO 75 percent full interrupt.

FIFO75INT = 0x1 - FIFO 75 percent full interrupt.
1 SCNCMP RW ADC scan complete interrupt.

SCNCMPINT = 0x1 - ADC scan complete interrupt.
0 CNVCMP RW ADC conversion complete interrupt.

CNVCMPINT = 0x1 - ADC conversion complete interrupt.

INTSTAT - ADC Interrupt registers: Status

Address:

  Instance 0 Address:   0x50010204

Description:

Read bits from this register to discover the cause of a recent interrupt.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DERR
0x0
DCMP
0x0
WCINC
0x0
WCEXC
0x0
FIFOOVR2
0x0
FIFOOVR1
0x0
SCNCMP
0x0
CNVCMP
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED.

7 DERR RW DMA Error Condition

DMAERROR = 0x1 - DMA Error Condition Occurred
6 DCMP RW DMA Transfer Complete

DMACOMPLETE = 0x1 - DMA Completed a transfer
5 WCINC RW Window comparator voltage incursion interrupt.

WCINCINT = 0x1 - Window comparator voltage incursion interrupt.
4 WCEXC RW Window comparator voltage excursion interrupt.

WCEXCINT = 0x1 - Window comparator voltage excursion interrupt.
3 FIFOOVR2 RW FIFO 100 percent full interrupt.

FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt.
2 FIFOOVR1 RW FIFO 75 percent full interrupt.

FIFO75INT = 0x1 - FIFO 75 percent full interrupt.
1 SCNCMP RW ADC scan complete interrupt.

SCNCMPINT = 0x1 - ADC scan complete interrupt.
0 CNVCMP RW ADC conversion complete interrupt.

CNVCMPINT = 0x1 - ADC conversion complete interrupt.

INTCLR - ADC Interrupt registers: Clear

Address:

  Instance 0 Address:   0x50010208

Description:

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DERR
0x0
DCMP
0x0
WCINC
0x0
WCEXC
0x0
FIFOOVR2
0x0
FIFOOVR1
0x0
SCNCMP
0x0
CNVCMP
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED.

7 DERR RW DMA Error Condition

DMAERROR = 0x1 - DMA Error Condition Occurred
6 DCMP RW DMA Transfer Complete

DMACOMPLETE = 0x1 - DMA Completed a transfer
5 WCINC RW Window comparator voltage incursion interrupt.

WCINCINT = 0x1 - Window comparator voltage incursion interrupt.
4 WCEXC RW Window comparator voltage excursion interrupt.

WCEXCINT = 0x1 - Window comparator voltage excursion interrupt.
3 FIFOOVR2 RW FIFO 100 percent full interrupt.

FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt.
2 FIFOOVR1 RW FIFO 75 percent full interrupt.

FIFO75INT = 0x1 - FIFO 75 percent full interrupt.
1 SCNCMP RW ADC scan complete interrupt.

SCNCMPINT = 0x1 - ADC scan complete interrupt.
0 CNVCMP RW ADC conversion complete interrupt.

CNVCMPINT = 0x1 - ADC conversion complete interrupt.

INTSET - ADC Interrupt registers: Set

Address:

  Instance 0 Address:   0x5001020C

Description:

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DERR
0x0
DCMP
0x0
WCINC
0x0
WCEXC
0x0
FIFOOVR2
0x0
FIFOOVR1
0x0
SCNCMP
0x0
CNVCMP
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED.

7 DERR RW DMA Error Condition

DMAERROR = 0x1 - DMA Error Condition Occurred
6 DCMP RW DMA Transfer Complete

DMACOMPLETE = 0x1 - DMA Completed a transfer
5 WCINC RW Window comparator voltage incursion interrupt.

WCINCINT = 0x1 - Window comparator voltage incursion interrupt.
4 WCEXC RW Window comparator voltage excursion interrupt.

WCEXCINT = 0x1 - Window comparator voltage excursion interrupt.
3 FIFOOVR2 RW FIFO 100 percent full interrupt.

FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt.
2 FIFOOVR1 RW FIFO 75 percent full interrupt.

FIFO75INT = 0x1 - FIFO 75 percent full interrupt.
1 SCNCMP RW ADC scan complete interrupt.

SCNCMPINT = 0x1 - ADC scan complete interrupt.
0 CNVCMP RW ADC conversion complete interrupt.

CNVCMPINT = 0x1 - ADC conversion complete interrupt.

DMATRIGEN - DMA Trigger Enable Register

Address:

  Instance 0 Address:   0x50010240

Description:

DMA Trigger Enable Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DFIFOFULL
0x0
DFIFO75
0x0

Bits Name RW Description
31:2 RSVD RO RESERVED.

1 DFIFOFULL RW Trigger DMA upon FIFO 100 percent Full

0 DFIFO75 RW Trigger DMA upon FIFO 75 percent Full


DMATRIGSTAT - DMA Trigger Status Register

Address:

  Instance 0 Address:   0x50010244

Description:

DMA Trigger Status Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DFULLSTAT
0x0
D75STAT
0x0

Bits Name RW Description
31:2 RSVD RO RESERVED.

1 DFULLSTAT RO Triggered DMA from FIFO 100 percent Full

0 D75STAT RO Triggered DMA from FIFO 75 percent Full


DMACFG - DMA Configuration Register

Address:

  Instance 0 Address:   0x50010280

Description:

DMA Configuration Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DPWROFF
0x0
DMAMSK
0x0
DMAHONSTAT
0x0
RSVD
0x0
DMADYNPRI
0x0
DMAPRI
0x0
RSVD
0x0
DMADIR
0x0
RSVD
0x0
DMAEN
0x0

Bits Name RW Description
31:19 RSVD RO RESERVED.

18 DPWROFF RW Power Off the ADC System upon DMACPL.

17 DMAMSK RW Mask the FIFOCNT and SLOTNUM when transferring FIFO contents to memory

DIS = 0x0 - FIFO Contents are copied directly to memory without modification.
EN = 0x1 - Only the FIFODATA contents are copied to memory on DMA transfers. The SLOTNUM and FIFOCNT contents are cleared to zero.
16 DMAHONSTAT RW Halt New ADC conversions until DMA Status DMAERR and DMACPL Cleared.

DIS = 0x0 - ADC conversions will continue regardless of DMA status register
EN = 0x1 - ADC conversions will not progress if DMAERR or DMACPL bits in DMA status register are set.
15:10 RSVD RO RESERVED.

9 DMADYNPRI RW Enables dynamic priority based on FIFO fullness. When FIFO is full, priority is automatically set to HIGH. Otherwise, DMAPRI is used.

DIS = 0x0 - Disable dynamic priority (use DMAPRI setting only)
EN = 0x1 - Enable dynamic priority
8 DMAPRI RW Sets the Priority of the DMA request

LOW = 0x0 - Low Priority (service as best effort)
HIGH = 0x1 - High Priority (service immediately)
7:3 RSVD RO RESERVED.

2 DMADIR RO Direction

P2M = 0x0 - Peripheral to Memory (SRAM) transaction
M2P = 0x1 - Memory to Peripheral transaction
1 RSVD RO RESERVED.

0 DMAEN RW DMA Enable

DIS = 0x0 - Disable DMA Function
EN = 0x1 - Enable DMA Function

DMATOTCOUNT - DMA Total Transfer Count

Address:

  Instance 0 Address:   0x50010288

Description:

DMA Total Transfer Count

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
TOTCOUNT
0x0
BTOTCOUNT
0x0

Bits Name RW Description
31:18 RSVD RO RESERVED.

17:2 TOTCOUNT RW Total Transfer Count

1:0 BTOTCOUNT RO RESERVED.


DMATARGADDR - DMA Target Address Register

Address:

  Instance 0 Address:   0x5001028C

Description:

DMA Target Address Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UTARGADDR
0x400
LTARGADDR
0x0

Bits Name RW Description
31:19 UTARGADDR RO SRAM Target

18:0 LTARGADDR RW DMA Target Address


DMASTAT - DMA Status Register

Address:

  Instance 0 Address:   0x50010290

Description:

DMA Status Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DMAERR
0x0
DMACPL
0x0
DMATIP
0x0

Bits Name RW Description
31:3 RSVD RO RESERVED.

2 DMAERR RW DMA Error

1 DMACPL RW DMA Transfer Complete

0 DMATIP RW DMA Transfer In Progress