Apollo Register Documentation  v${version}
MCUCTRL - MCU Miscellaneous Control Logic

MCUCTRL Register Index

  0x00000000:   CHIP_INFO - Chip Information Register
  0x00000004:   CHIPID0 - Unique Chip ID 0
  0x00000008:   CHIPID1 - Unique Chip ID 1
  0x0000000C:   CHIPREV - Chip Revision
  0x00000010:   SUPPLYSRC - Memory and Core Voltage Supply Source Select Register
  0x00000014:   SUPPLYSTATUS - Memory and Core Voltage Supply Source Status Register
  0x000000FC:   BANDGAPEN - Band Gap Enable
  0x00000140:   SRAMPWDINSLEEP - Powerdown an SRAM Bank in Deep Sleep mode
  0x00000144:   SRAMPWRDIS - Disables individual banks of the SRAM array
  0x00000148:   FLASHPWRDIS - Disables individual banks of the Flash array
  0x000001C0:   ICODEFAULTADDR - ICODE bus address which was present when a bus fault occurred.
  0x000001C4:   DCODEFAULTADDR - DCODE bus address which was present when a bus fault occurred.
  0x000001C8:   SYSFAULTADDR - System bus address which was present when a bus fault occurred.
  0x000001CC:   FAULTSTATUS - Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.
  0x000001D0:   FAULTCAPTUREEN - Enable the fault capture registers
  0x00000250:   TPIUCTRL - TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.

CHIP_INFO - Chip Information Register

Address:

  Instance 0 Address:   0x40020000

Description:

Chip Information Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLASS
0x1
FLASH
0x4
RAM
0x1
MAJORREV
0x1
MINORREV
0x1
PKG
0x1
PINS
0x1
TEMP
0x1
QUAL
0x1

Bits Name RW Description
31:24 CLASS RO Device class.

APOLLO = 0x1 - APOLLO
23:20 FLASH RO Device flash size.

256K = 0x3 - 256K of available flash.
512K = 0x4 - 512K of available flash.
19:16 RAM RO Device RAM size.

32K = 0x0 - 32K of available SRAM.
64K = 0x1 - 64K of available SRAM.
15:12 MAJORREV RO Major device revision number.

11:8 MINORREV RO Minor device revision number.

7:6 PKG RO Device package type.

BGA = 0x2 - Ball grid array.
CSP = 0x3 - Chip-scale package.
5:3 PINS RO Number of pins.

41PINS = 0x1 - 41 package pins total.
64PINS = 0x1 - 64 package pins total.
2:1 TEMP RO Device temperature range.

COMMERCIAL = 0x0 - Commercial temperature range.
0 QUAL RO Device qualified.

PROTOTYPE = 0x0 - Prototype device.
QUALIFIED = 0x1 - Fully qualified device.

CHIPID0 - Unique Chip ID 0

Address:

  Instance 0 Address:   0x40020004

Description:

Unique Chip ID 0

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VALUE
0x0

Bits Name RW Description
31:0 VALUE RO Unique chip ID 0.

APOLLO = 0x0 - Apollo CHIPID0.

CHIPID1 - Unique Chip ID 1

Address:

  Instance 0 Address:   0x40020008

Description:

Unique Chip ID 1

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VALUE
0x0

Bits Name RW Description
31:0 VALUE RO Unique chip ID 1.

APOLLO = 0x0 - Apollo CHIPID1.

CHIPREV - Chip Revision

Address:

  Instance 0 Address:   0x4002000C

Description:

Chip Revision

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
REVISION
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED.

7:0 REVISION RO Chip Revision Number.

APOLLO = 0x0 - Apollo CHIPREV.

SUPPLYSRC - Memory and Core Voltage Supply Source Select Register

Address:

  Instance 0 Address:   0x40020010

Description:

Memory and Core Voltage Supply Source Select Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
COREBUCKEN
0x0
MEMBUCKEN
0x0

Bits Name RW Description
31:2 RSVD RO RESERVED.

1 COREBUCKEN RW Enables and Selects the Core Buck as the supply for the low-voltage power domain.

EN = 0x1 - Enable the Core Buck for the low-voltage power domain.
0 MEMBUCKEN RW Enables and select the Memory Buck as the supply for the Flash and SRAM power domain.

EN = 0x1 - Enable the Memory Buck as the supply for flash and SRAM.

SUPPLYSTATUS - Memory and Core Voltage Supply Source Status Register

Address:

  Instance 0 Address:   0x40020014

Description:

Memory and Core Voltage Supply Source Status Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
COREBUCKON
0x0
MEMBUCKON
0x0

Bits Name RW Description
31:2 RSVD RO RESERVED.

1 COREBUCKON RO Indicates whether the Core low-voltage domain is supplied from the LDO or the Buck.

LDO = 0x0 - Indicates the the LDO is supplying the Core low-voltage.
BUCK = 0x1 - Indicates the the Buck is supplying the Core low-voltage.
0 MEMBUCKON RO Indicate whether the Memory power domain is supplied from the LDO or the Buck.

LDO = 0x0 - Indicates the LDO is supplying the memory power domain.
BUCK = 0x1 - Indicates the Buck is supplying the memory power domain.

BANDGAPEN - Band Gap Enable

Address:

  Instance 0 Address:   0x400200FC

Description:

Band Gap Enable

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
BGPEN
0x0

Bits Name RW Description
31:1 RSVD RO RESERVED.

0 BGPEN RW Bandgap Enable

DIS = 0x0 - Bandgap disable.
EN = 0x1 - Bandgap enable.

SRAMPWDINSLEEP - Powerdown an SRAM Bank in Deep Sleep mode

Address:

  Instance 0 Address:   0x40020140

Description:

Powerdown an SRAM Bank in Deep Sleep mode

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
BANK7
0x0
BANK6
0x0
BANK5
0x0
BANK4
0x0
BANK3
0x0
BANK2
0x0
BANK1
0x0
BANK0
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED.

7 BANK7 RW Force SRAM Bank 7 to powerdown in deep sleep mode, causing the contents of the bank to be lost.

NORMAL = 0x0 - SRAM Bank 7 normal operation.
PWRDN_IN_DEEPSLEEP = 0x1 - SRAM Bank 7 deep sleep.
6 BANK6 RW Force SRAM Bank 6 to powerdown in deep sleep mode, causing the contents of the bank to be lost.

NORMAL = 0x0 - SRAM Bank 6 normal operation.
PWRDN_IN_DEEPSLEEP = 0x1 - SRAM Bank 6 deep sleep.
5 BANK5 RW Force SRAM Bank 5 to powerdown in deep sleep mode, causing the contents of the bank to be lost.

NORMAL = 0x0 - SRAM Bank 5 normal operation.
PWRDN_IN_DEEPSLEEP = 0x1 - SRAM Bank 5 deep sleep.
4 BANK4 RW Force SRAM Bank 4 to powerdown in deep sleep mode, causing the contents of the bank to be lost.

NORMAL = 0x0 - SRAM Bank 4 normal operation.
PWRDN_IN_DEEPSLEEP = 0x1 - SRAM Bank 4 deep sleep.
3 BANK3 RW Force SRAM Bank 3 to powerdown in deep sleep mode, causing the contents of the bank to be lost.

NORMAL = 0x0 - SRAM Bank 3 normal operation.
PWRDN_IN_DEEPSLEEP = 0x1 - SRAM Bank 3 deep sleep.
2 BANK2 RW Force SRAM Bank 2 to powerdown in deep sleep mode, causing the contents of the bank to be lost.

NORMAL = 0x0 - SRAM Bank 2 normal operation.
PWRDN_IN_DEEPSLEEP = 0x1 - SRAM Bank 2 deep sleep.
1 BANK1 RW Force SRAM Bank 1 to powerdown in deep sleep mode, causing the contents of the bank to be lost.

NORMAL = 0x0 - SRAM Bank 1 normal operation.
PWRDN_IN_DEEPSLEEP = 0x1 - SRAM Bank 1 deep sleep.
0 BANK0 RW Force SRAM Bank 0 to powerdown in deep sleep mode, causing the contents of the bank to be lost.

NORMAL = 0x0 - SRAM Bank 0 normal operation.
PWRDN_IN_DEEPSLEEP = 0x1 - SRAM Bank 0 deep sleep.

SRAMPWRDIS - Disables individual banks of the SRAM array

Address:

  Instance 0 Address:   0x40020144

Description:

Disables individual banks of the SRAM array

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
BANK7
0x0
BANK6
0x0
BANK5
0x0
BANK4
0x0
BANK3
0x0
BANK2
0x0
BANK1
0x0
BANK0
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED.

7 BANK7 RW Remove power from SRAM Bank 7 which will cause an access to its address space to generate a Hard Fault.

DIS = 0x1 - Disable SRAM Bank 7.
6 BANK6 RW Remove power from SRAM Bank 6 which will cause an access to its address space to generate a Hard Fault.

DIS = 0x1 - Disable SRAM Bank 6.
5 BANK5 RW Remove power from SRAM Bank 5 which will cause an access to its address space to generate a Hard Fault.

DIS = 0x1 - Disable SRAM Bank 5.
4 BANK4 RW Remove power from SRAM Bank 4 which will cause an access to its address space to generate a Hard Fault.

DIS = 0x1 - Disable SRAM Bank 4.
3 BANK3 RW Remove power from SRAM Bank 3 which will cause an access to its address space to generate a Hard Fault.

DIS = 0x1 - Disable SRAM Bank 3.
2 BANK2 RW Remove power from SRAM Bank 2 which will cause an access to its address space to generate a Hard Fault.

DIS = 0x1 - Disable SRAM Bank 2.
1 BANK1 RW Remove power from SRAM Bank 1 which will cause an access to its address space to generate a Hard Fault.

DIS = 0x1 - Disable SRAM Bank 1.
0 BANK0 RW Remove power from SRAM Bank 0 which will cause an access to its address space to generate a Hard Fault.

DIS = 0x1 - Disable SRAM Bank 0.

FLASHPWRDIS - Disables individual banks of the Flash array

Address:

  Instance 0 Address:   0x40020148

Description:

Disables individual banks of the Flash array

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
BANK1
0x0
BANK0
0x0

Bits Name RW Description
31:2 RSVD RO RESERVED.

1 BANK1 RW Remove power from Flash Bank 1 which will cause an access to its address space to generate a Hard Fault.

DIS = 0x1 - Disable Flash instance 1.
0 BANK0 RW Remove power from Flash Bank 0 which will cause an access to its address space to generate a Hard Fault.

DIS = 0x1 - Disable Flash instance 0.

ICODEFAULTADDR - ICODE bus address which was present when a bus fault occurred.

Address:

  Instance 0 Address:   0x400201C0

Description:

ICODE bus address which was present when a bus fault occurred.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
0x0

Bits Name RW Description
31:0 ADDR RO The ICODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.


DCODEFAULTADDR - DCODE bus address which was present when a bus fault occurred.

Address:

  Instance 0 Address:   0x400201C4

Description:

DCODE bus address which was present when a bus fault occurred.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
0x0

Bits Name RW Description
31:0 ADDR RO The DCODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.


SYSFAULTADDR - System bus address which was present when a bus fault occurred.

Address:

  Instance 0 Address:   0x400201C8

Description:

System bus address which was present when a bus fault occurred.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
0x0

Bits Name RW Description
31:0 ADDR RO SYS bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.


FAULTSTATUS - Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.

Address:

  Instance 0 Address:   0x400201CC

Description:

Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
SYS
0x0
DCODE
0x0
ICODE
0x0

Bits Name RW Description
31:3 RSVD RO RESERVED.

2 SYS RW SYS Bus Decoder Fault Detected bit. When set, a fault has been detected, and the SYSFAULTADDR register will contain the bus address which generated the fault.

NOFAULT = 0x0 - No bus fault has been detected.
FAULT = 0x1 - Bus fault detected.
1 DCODE RW DCODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the DCODEFAULTADDR register will contain the bus address which generated the fault.

NOFAULT = 0x0 - No DCODE fault has been detected.
FAULT = 0x1 - DCODE fault detected.
0 ICODE RW The ICODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the ICODEFAULTADDR register will contain the bus address which generated the fault.

NOFAULT = 0x0 - No ICODE fault has been detected.
FAULT = 0x1 - ICODE fault detected.

FAULTCAPTUREEN - Enable the fault capture registers

Address:

  Instance 0 Address:   0x400201D0

Description:

Enable the fault capture registers

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ENABLE
0x0

Bits Name RW Description
31:1 RSVD RO RESERVED.

0 ENABLE RW Fault Capture Enable field. When set, the Fault Capture monitors are enabled and addresses which generate a hard fault are captured into the FAULTADDR registers.

DIS = 0x0 - Disable fault capture.
EN = 0x1 - Enable fault capture.

TPIUCTRL - TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.

Address:

  Instance 0 Address:   0x40020250

Description:

TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CLKSEL
0x0
RSVD
0x0
ENABLE
0x0

Bits Name RW Description
31:10 RSVD RO RESERVED.

9:8 CLKSEL RW This field selects the frequency of the ARM M4 TPIU port.

LOW_PWR = 0x0 - Low power state.
0MHz = 0x0 - Low power state.
6MHZ = 0x1 - Selects 6MHz frequency.
3MHZ = 0x2 - Selects 3MHz frequency.
1_5MHZ = 0x3 - Selects 1.5 MHz frequency.
7:1 RSVD RO RESERVED.

0 ENABLE RW TPIU Enable field. When set, the ARM M4 TPIU is enabled and data can be streamed out of the MCU's SWO port using the ARM ITM and TPIU modules.

DIS = 0x0 - Disable the TPIU.
EN = 0x1 - Enable the TPIU.