Apollo Register Documentation  v${version}
ADC - Analog Digital Converter Control

ADC Register Index

  0x00000000:   CFG - Configuration Register
  0x00000004:   STAT - ADC Power Status
  0x00000008:   SWT - Software trigger
  0x0000000C:   SL0CFG - Slot 0 Configuration Register
  0x00000010:   SL1CFG - Slot 1 Configuration Register
  0x00000014:   SL2CFG - Slot 2 Configuration Register
  0x00000018:   SL3CFG - Slot 3 Configuration Register
  0x0000001C:   SL4CFG - Slot 4 Configuration Register
  0x00000020:   SL5CFG - Slot 5 Configuration Register
  0x00000024:   SL6CFG - Slot 6 Configuration Register
  0x00000028:   SL7CFG - Slot 7 Configuration Register
  0x0000002C:   WLIM - Window Comparator Limits Register
  0x00000030:   FIFO - FIFO Data and Valid Count Register
  0x00000200:   INTEN - ADC Interrupt registers: Enable
  0x00000204:   INTSTAT - ADC Interrupt registers: Status
  0x00000208:   INTCLR - ADC Interrupt registers: Clear
  0x0000020C:   INTSET - ADC Interrupt registers: Set

CFG - Configuration Register

Address:

  Instance 0 Address:   0x50008000

Description:

The ADC Configuration Register contains the software control for selecting the clock frequency used for the SAR conversions, the trigger polarity, the trigger select, the reference voltage select, the operating mode (current control for high frequency conversions), the low power mode, the operating mode (single scan per trigger vs. repeating mode), temperature sensor enable and ADC enable.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CLKSEL
0x0
RSVD
0x0
TRIGPOL
0x0
TRIGSEL
0x0
RSVD
0x0
REFSEL
0x0
BATTLOAD
0x0
OPMODE
0x0
LPMODE
0x0
RPTEN
0x0
TMPSPWR
0x0
ADCEN
0x0

Bits Name RW Description
31:27 RSVD RO RESERVED.

26:24 CLKSEL RW Select the source and frequency for the ADC clock. All values not enumerated below are undefined.

OFF = 0x0 - Low Power Mode.
12MHZ = 0x1 - 12 MHz ADC clock.
6MHZ = 0x2 - 6 MHz ADC clock.
3MHZ = 0x3 - 12 MHz ADC clock.
1_5MHZ = 0x4 - 1.5 MHz ADC clock.
23:21 RSVD RO RESERVED.

20 TRIGPOL RW This bit selects the ADC trigger polarity for external off chip triggers.

RISING_EDGE = 0x0 - Trigger on rising edge.
FALLING_EDGE = 0x1 - Trigger on falling edge.
19:16 TRIGSEL RW Select the ADC trigger source.

EXT0 = 0x0 - Off chip External Trigger0 (ADC_ET0)
EXT1 = 0x1 - Off chip External Trigger1 (ADC_ET1)
EXT2 = 0x2 - Off chip External Trigger2 (ADC_ET2)
EXT3 = 0x3 - Off chip External Trigger3 (ADC_ET3)
EXT4 = 0x4 - Off chip External Trigger4 (ADC_ET4)
EXT5 = 0x5 - Off chip External Trigger5 (ADC_ET5)
EXT6 = 0x6 - Off chip External Trigger6 (ADC_ET6)
EXT7 = 0x7 - Off chip External Trigger7 (ADC_ET7)
SWT = 0x8 - Software Trigger
15:10 RSVD RO RESERVED.

9:8 REFSEL RW Select the ADC reference voltage.

INTERNAL = 0x0 - Internal Bandgap Reference Voltage
VDD = 0x1 - Select VDD as the ADEC reference voltage.
ADCREF = 0x2 - Off Chip Reference (ADC_REF)
UNDEFINED = 0x3 - Reserved
7 BATTLOAD RW Control 500 Ohm battery load resistor.

DIS = 0x0 - Disable battery load.
EN = 0x1 - Enable battery load.
6:5 OPMODE RW Select the sample rate mode. It adjusts the current in the ADC for higher sample rates. A 12MHz ADC clock can result in a sample rate up to 1Msps depending on the trigger or repeating mode rate. A 1.5MHz ADC clock can result in a sample rate up 125K sps. NOTE: All other values not specified below are undefined.

SAMPLE_RATE_LE_125KSPS = 0x0 - Sample Rate <= 125K sps
SAMPLE_RATE_125K_1MSPS = 0x2 - Sample Rate 125K to 1M sps
4:3 LPMODE RW Select power mode to enter between active scans.

MODE0 = 0x0 - Low Power Mode 0 (2'b00). Leaves the ADC fully powered between scans with no latency between a trigger event and sample data collection.
MODE1 = 0x1 - Low Power Mode 1 (2'b01). Enables a low power mode for the ADC between scans requiring 50us initialization time (latency) between a trigger event and the scan (assuming the HFRC remains running and the MCU is not in deepsleep mode in which case additional startup latency for HFRC startup is required).
MODE2 = 0x2 - Low Power Mode 2 (2'b10). Disconnects power and clocks to the ADC effectively eliminating all active power associated with the ADC between scans. This mode requires 150us initialization (again, assuming the HFRC remains running and the MCU is not in deepsleep mode in which case additional startup latency for HFRC startup is required).
MODE_UNDEFINED = 0x3 - Undefined Mode (2'b11)
2 RPTEN RWx This bit enables Repeating Scan Mode.

SINGLE_SCAN = 0x0 - In Single Scan Mode, the ADC will complete a single scan upon each trigger event.
REPEATING_SCAN = 0x1 - In Repeating Scan Mode, the ADC will complete it's first scan upon the initial trigger event and all subsequent scans will occur at regular intervals defined by the configuration programmed for the CTTMRA3 internal timer until the timer is disabled or the ADC is disabled.
1 TMPSPWR RW This enables power to the temperature sensor module. After setting this bit, the temperature sensor will remain powered down while the ADC is power is disconnected (i.e, when the ADC PWDSTAT is 2'b10).

DIS = 0x0 - Power down the temperature sensor.
EN = 0x1 - Enable the temperature sensor when the ADC is in it's active state.
0 ADCEN RW This bit enables the ADC module. While the ADC is enabled, the ADCCFG and SLOT Configuration regsiter settings must remain stable and unchanged.

DIS = 0x0 - Disable the ADC module.
EN = 0x1 - Enable the ADC module.

STAT - ADC Power Status

Address:

  Instance 0 Address:   0x50008004

Description:

This register indicates the power status for the ADC. ADC power mode 0 indicates the ADC is in it's full power state and is ready to process scans. ADC Power mode 1 indicated the ADC power switch is on, but the ADC SAR module is in a low power state. From this state, a trigger will bring the ADC into it's active state after a 50us calibration period. ADC power mode 2 indicates the ADC is in it's lowest power state.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
PWDSTAT
0x0

Bits Name RW Description
31:2 RSVD RO RESERVED.

1:0 PWDSTAT RO Indicates the power-status of the ADC.

ON = 0x0 - Powered on.
SWITCH_ON_SAR_OFF = 0x1 - Power switch on, ADC Low Power Mode 1.
POWER_SWITCH_OFF = 0x2 - Power switch off, ADC disabled.

SWT - Software trigger

Address:

  Instance 0 Address:   0x50008008

Description:

This register enables initiating an ADC scan through software.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
SWT
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED.

7:0 SWT RW Writing 0x37 to this register generates a software trigger.

GEN_SW_TRIGGER = 0x37 - Writing this value generates a software trigger.

SL0CFG - Slot 0 Configuration Register

Address:

  Instance 0 Address:   0x5000800C

Description:

Slot 0 Configuration Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADSEL0
0x0
RSVD
0x0
THSEL0
0x0
RSVD
0x0
CHSEL0
0x0
RSVD
0x0
WCEN0
0x0
SLEN0
0x0

Bits Name RW Description
31:27 RSVD RO RESERVED.

26:24 ADSEL0 RW Select the number of measurements to average in the accumulate divide module for this slot.

AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:19 RSVD RO RESERVED.

18:16 THSEL0 RW Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.

1_ADC_CLK = 0x0 - 1 ADC clock cycle.
2_ADC_CLKS = 0x1 - 2 ADC clock cycles.
4_ADC_CLKS = 0x2 - 4 ADC clock cycles.
8_ADC_CLKS = 0x3 - 8 ADC clock cycles.
16_ADC_CLKS = 0x4 - 16 ADC clock cycles.
32_ADC_CLKS = 0x5 - 32 ADC clock cycles.
64_ADC_CLKS = 0x6 - 64 ADC clock cycles.
128_ADC_CLKS = 0x7 - 128 ADC clock cycles.
15:12 RSVD RO RESERVED.

11:8 CHSEL0 RW Select one of the 13 channel inputs for this slot.

EXT0 = 0x0 - ADC_EXT0 external GPIO pin connection.
EXT1 = 0x1 - ADC_EXT1 external GPIO pin connection.
EXT2 = 0x2 - ADC_EXT2 external GPIO pin connection.
EXT3 = 0x3 - ADC_EXT3 external GPIO pin connection.
EXT4 = 0x4 - ADC_EXT4 external GPIO pin connection.
EXT5 = 0x5 - ADC_EXT5 external GPIO pin connection.
EXT6 = 0x6 - ADC_EXT6 external GPIO pin connection.
EXT7 = 0x7 - ADC_EXT7 external GPIO pin connection.
TEMP = 0x8 - ADC_TEMP internal temperature sensor.
VDD = 0x9 - ADC_VDD internal power rail connection.
VSS = 0xA - ADC_VSS internal ground connection.
VBATT = 0xC - ADC_VBATT internal voltage divide-by-3 connection to input power rail.
7:2 RSVD RO RESERVED.

1 WCEN0 RW This bit enables the window compare function for slot 0.

WCEN = 0x1 - Enable the window compare for slot 0.
0 SLEN0 RW This bit enables slot 0 for ADC conversions.

SLEN = 0x1 - Enable slot 0 for ADC conversions.

SL1CFG - Slot 1 Configuration Register

Address:

  Instance 0 Address:   0x50008010

Description:

Slot 1 Configuration Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADSEL1
0x0
RSVD
0x0
THSEL1
0x0
RSVD
0x0
CHSEL1
0x0
RSVD
0x0
WCEN1
0x0
SLEN1
0x0

Bits Name RW Description
31:27 RSVD RO RESERVED.

26:24 ADSEL1 RW Select the number of measurements to average in the accumulate divide module for this slot.

AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:19 RSVD RO RESERVED.

18:16 THSEL1 RW Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5 Mhz clock, the track and hold delay cannot exceed 64 clocks.

1_ADC_CLK = 0x0 - 1 ADC clock cycle.
2_ADC_CLKS = 0x1 - 2 ADC clock cycles.
4_ADC_CLKS = 0x2 - 4 ADC clock cycles.
8_ADC_CLKS = 0x3 - 8 ADC clock cycles.
16_ADC_CLKS = 0x4 - 16 ADC clock cycles.
32_ADC_CLKS = 0x5 - 32 ADC clock cycles.
64_ADC_CLKS = 0x6 - 64 ADC clock cycles.
128_ADC_CLKS = 0x7 - 128 ADC clock cycles.
15:12 RSVD RO RESERVED.

11:8 CHSEL1 RW Select one of the 13 channel inputs for this slot.

EXT0 = 0x0 - ADC_EXT0 external GPIO pin connection.
EXT1 = 0x1 - ADC_EXT1 external GPIO pin connection.
EXT2 = 0x2 - ADC_EXT2 external GPIO pin connection.
EXT3 = 0x3 - ADC_EXT3 external GPIO pin connection.
EXT4 = 0x4 - ADC_EXT4 external GPIO pin connection.
EXT5 = 0x5 - ADC_EXT5 external GPIO pin connection.
EXT6 = 0x6 - ADC_EXT6 external GPIO pin connection.
EXT7 = 0x7 - ADC_EXT7 external GPIO pin connection.
TEMP = 0x8 - ADC_TEMP internal temperature sensor.
VDD = 0x9 - ADC_VDD internal power rail connection.
VSS = 0xA - ADC_VSS internal ground connection.
VBATT = 0xC - ADC_VBATT internal voltage divide-by-3 connection to input power rail.
7:2 RSVD RO RESERVED.

1 WCEN1 RW This bit enables the window compare function for slot 1.

WCEN = 0x1 - Enable the window compare for slot 1.
0 SLEN1 RW This bit enables slot 1 for ADC conversions.

SLEN = 0x1 - Enable slot 1 for ADC conversions.

SL2CFG - Slot 2 Configuration Register

Address:

  Instance 0 Address:   0x50008014

Description:

Slot 2 Configuration Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADSEL2
0x0
RSVD
0x0
THSEL2
0x0
RSVD
0x0
CHSEL2
0x0
RSVD
0x0
WCEN2
0x0
SLEN2
0x0

Bits Name RW Description
31:27 RSVD RO RESERVED.

26:24 ADSEL2 RW Select the number of measurements to average in the accumulate divide module for this slot.

AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:19 RSVD RO RESERVED.

18:16 THSEL2 RW Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.

1_ADC_CLK = 0x0 - 1 ADC clock cycle.
2_ADC_CLKS = 0x1 - 2 ADC clock cycles.
4_ADC_CLKS = 0x2 - 4 ADC clock cycles.
8_ADC_CLKS = 0x3 - 8 ADC clock cycles.
16_ADC_CLKS = 0x4 - 16 ADC clock cycles.
32_ADC_CLKS = 0x5 - 32 ADC clock cycles.
64_ADC_CLKS = 0x6 - 64 ADC clock cycles.
128_ADC_CLKS = 0x7 - 128 ADC clock cycles.
15:12 RSVD RO RESERVED.

11:8 CHSEL2 RW Select one of the 13 channel inputs for this slot.

EXT0 = 0x0 - ADC_EXT0 external GPIO pin connection.
EXT1 = 0x1 - ADC_EXT1 external GPIO pin connection.
EXT2 = 0x2 - ADC_EXT2 external GPIO pin connection.
EXT3 = 0x3 - ADC_EXT3 external GPIO pin connection.
EXT4 = 0x4 - ADC_EXT4 external GPIO pin connection.
EXT5 = 0x5 - ADC_EXT5 external GPIO pin connection.
EXT6 = 0x6 - ADC_EXT6 external GPIO pin connection.
EXT7 = 0x7 - ADC_EXT7 external GPIO pin connection.
TEMP = 0x8 - ADC_TEMP internal temperature sensor.
VDD = 0x9 - ADC_VDD internal power rail connection.
VSS = 0xA - ADC_VSS internal ground connection.
VBATT = 0xC - ADC_VBATT internal voltage divide-by-3 connection to input power rail.
7:2 RSVD RO RESERVED.

1 WCEN2 RW This bit enables the window compare function for slot 2.

WCEN = 0x1 - Enable the window compare for slot 2.
0 SLEN2 RW This bit enables slot 2 for ADC conversions.

SLEN = 0x1 - Enable slot 2 for ADC conversions.

SL3CFG - Slot 3 Configuration Register

Address:

  Instance 0 Address:   0x50008018

Description:

Slot 3 Configuration Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADSEL3
0x0
RSVD
0x0
THSEL3
0x0
RSVD
0x0
CHSEL3
0x0
RSVD
0x0
WCEN3
0x0
SLEN3
0x0

Bits Name RW Description
31:27 RSVD RO RESERVED.

26:24 ADSEL3 RW Select the number of measurements to average in the accumulate divide module for this slot.

AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:19 RSVD RO RESERVED.

18:16 THSEL3 RW Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.

1_ADC_CLK = 0x0 - 1 ADC clock cycle.
2_ADC_CLKS = 0x1 - 2 ADC clock cycles.
4_ADC_CLKS = 0x2 - 4 ADC clock cycles.
8_ADC_CLKS = 0x3 - 8 ADC clock cycles.
16_ADC_CLKS = 0x4 - 16 ADC clock cycles.
32_ADC_CLKS = 0x5 - 32 ADC clock cycles.
64_ADC_CLKS = 0x6 - 64 ADC clock cycles.
128_ADC_CLKS = 0x7 - 128 ADC clock cycles.
15:12 RSVD RO RESERVED.

11:8 CHSEL3 RW Select one of the 13 channel inputs for this slot.

EXT0 = 0x0 - ADC_EXT0 external GPIO pin connection.
EXT1 = 0x1 - ADC_EXT1 external GPIO pin connection.
EXT2 = 0x2 - ADC_EXT2 external GPIO pin connection.
EXT3 = 0x3 - ADC_EXT3 external GPIO pin connection.
EXT4 = 0x4 - ADC_EXT4 external GPIO pin connection.
EXT5 = 0x5 - ADC_EXT5 external GPIO pin connection.
EXT6 = 0x6 - ADC_EXT6 external GPIO pin connection.
EXT7 = 0x7 - ADC_EXT7 external GPIO pin connection.
TEMP = 0x8 - ADC_TEMP internal temperature sensor.
VDD = 0x9 - ADC_VDD internal power rail connection.
VSS = 0xA - ADC_VSS internal ground connection.
VBATT = 0xC - ADC_VBATT internal voltage divide-by-3 connection to input power rail.
7:2 RSVD RO RESERVED.

1 WCEN3 RW This bit enables the window compare function for slot 3.

WCEN = 0x1 - Enable the window compare for slot 3.
0 SLEN3 RW This bit enables slot 3 for ADC conversions.

SLEN = 0x1 - Enable slot 3 for ADC conversions.

SL4CFG - Slot 4 Configuration Register

Address:

  Instance 0 Address:   0x5000801C

Description:

Slot 4 Configuration Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADSEL4
0x0
RSVD
0x0
THSEL4
0x0
RSVD
0x0
CHSEL4
0x0
RSVD
0x0
WCEN4
0x0
SLEN4
0x0

Bits Name RW Description
31:27 RSVD RO RESERVED.

26:24 ADSEL4 RW Select the number of measurements to average in the accumulate divide module for this slot.

AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:19 RSVD RO RESERVED.

18:16 THSEL4 RW Select the track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.

1_ADC_CLK = 0x0 - 1 ADC clock cycle.
2_ADC_CLKS = 0x1 - 2 ADC clock cycles.
4_ADC_CLKS = 0x2 - 4 ADC clock cycles.
8_ADC_CLKS = 0x3 - 8 ADC clock cycles.
16_ADC_CLKS = 0x4 - 16 ADC clock cycles.
32_ADC_CLKS = 0x5 - 32 ADC clock cycles.
64_ADC_CLKS = 0x6 - 64 ADC clock cycles.
128_ADC_CLKS = 0x7 - 128 ADC clock cycles.
15:12 RSVD RO RESERVED.

11:8 CHSEL4 RW Select one of the 13 channel inputs for this slot.

EXT0 = 0x0 - ADC_EXT0 external GPIO pin connection.
EXT1 = 0x1 - ADC_EXT1 external GPIO pin connection.
EXT2 = 0x2 - ADC_EXT2 external GPIO pin connection.
EXT3 = 0x3 - ADC_EXT3 external GPIO pin connection.
EXT4 = 0x4 - ADC_EXT4 external GPIO pin connection.
EXT5 = 0x5 - ADC_EXT5 external GPIO pin connection.
EXT6 = 0x6 - ADC_EXT6 external GPIO pin connection.
EXT7 = 0x7 - ADC_EXT7 external GPIO pin connection.
TEMP = 0x8 - ADC_TEMP internal temperature sensor.
VDD = 0x9 - ADC_VDD internal power rail connection.
VSS = 0xA - ADC_VSS internal ground connection.
VBATT = 0xC - ADC_VBATT internal voltage divide-by-3 connection to input power rail.
7:2 RSVD RO RESERVED.

1 WCEN4 RW This bit enables the window compare function for slot 4.

WCEN = 0x1 - Enable the window compare for slot 4.
0 SLEN4 RW This bit enables slot 4 for ADC conversions.

SLEN = 0x1 - Enable slot 4 for ADC conversions.

SL5CFG - Slot 5 Configuration Register

Address:

  Instance 0 Address:   0x50008020

Description:

Slot 5 Configuration Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADSEL5
0x0
RSVD
0x0
THSEL5
0x0
RSVD
0x0
CHSEL5
0x0
RSVD
0x0
WCEN5
0x0
SLEN5
0x0

Bits Name RW Description
31:27 RSVD RO RESERVED.

26:24 ADSEL5 RW Select number of measurements to average in the accumulate divide module for this slot.

AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:19 RSVD RO RESERVED.

18:16 THSEL5 RW Select track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.

1_ADC_CLK = 0x0 - 1 ADC clock cycle.
2_ADC_CLKS = 0x1 - 2 ADC clock cycles.
4_ADC_CLKS = 0x2 - 4 ADC clock cycles.
8_ADC_CLKS = 0x3 - 8 ADC clock cycles.
16_ADC_CLKS = 0x4 - 16 ADC clock cycles.
32_ADC_CLKS = 0x5 - 32 ADC clock cycles.
64_ADC_CLKS = 0x6 - 64 ADC clock cycles.
128_ADC_CLKS = 0x7 - 128 ADC clock cycles.
15:12 RSVD RO RESERVED.

11:8 CHSEL5 RW Select one of the 13 channel inputs for this slot.

EXT0 = 0x0 - ADC_EXT0 external GPIO pin connection.
EXT1 = 0x1 - ADC_EXT1 external GPIO pin connection.
EXT2 = 0x2 - ADC_EXT2 external GPIO pin connection.
EXT3 = 0x3 - ADC_EXT3 external GPIO pin connection.
EXT4 = 0x4 - ADC_EXT4 external GPIO pin connection.
EXT5 = 0x5 - ADC_EXT5 external GPIO pin connection.
EXT6 = 0x6 - ADC_EXT6 external GPIO pin connection.
EXT7 = 0x7 - ADC_EXT7 external GPIO pin connection.
TEMP = 0x8 - ADC_TEMP internal temperature sensor.
VDD = 0x9 - ADC_VDD internal power rail connection.
VSS = 0xA - ADC_VSS internal ground connection.
VBATT = 0xC - ADC_VBATT internal voltage divide-by-3 connection to input power rail.
7:2 RSVD RO RESERVED.

1 WCEN5 RW This bit enables the window compare function for slot 5.

WCEN = 0x1 - Enable the window compare for slot 5.
0 SLEN5 RW This bit enables slot 5 for ADC conversions.

SLEN = 0x1 - Enable slot 5 for ADC conversions.

SL6CFG - Slot 6 Configuration Register

Address:

  Instance 0 Address:   0x50008024

Description:

Slot 6 Configuration Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADSEL6
0x0
RSVD
0x0
THSEL6
0x0
RSVD
0x0
CHSEL6
0x0
RSVD
0x0
WCEN6
0x0
SLEN6
0x0

Bits Name RW Description
31:27 RSVD RO RESERVED.

26:24 ADSEL6 RW Select the number of measurements to average in the accumulate divide module for this slot.

AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:19 RSVD RO RESERVED.

18:16 THSEL6 RW Select track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.

1_ADC_CLK = 0x0 - 1 ADC clock cycle.
2_ADC_CLKS = 0x1 - 2 ADC clock cycles.
4_ADC_CLKS = 0x2 - 4 ADC clock cycles.
8_ADC_CLKS = 0x3 - 8 ADC clock cycles.
16_ADC_CLKS = 0x4 - 16 ADC clock cycles.
32_ADC_CLKS = 0x5 - 32 ADC clock cycles.
64_ADC_CLKS = 0x6 - 64 ADC clock cycles.
128_ADC_CLKS = 0x7 - 128 ADC clock cycles.
15:12 RSVD RO RESERVED.

11:8 CHSEL6 RW Select one of the 13 channel inputs for this slot.

EXT0 = 0x0 - ADC_EXT0 external GPIO pin connection.
EXT1 = 0x1 - ADC_EXT1 external GPIO pin connection.
EXT2 = 0x2 - ADC_EXT2 external GPIO pin connection.
EXT3 = 0x3 - ADC_EXT3 external GPIO pin connection.
EXT4 = 0x4 - ADC_EXT4 external GPIO pin connection.
EXT5 = 0x5 - ADC_EXT5 external GPIO pin connection.
EXT6 = 0x6 - ADC_EXT6 external GPIO pin connection.
EXT7 = 0x7 - ADC_EXT7 external GPIO pin connection.
TEMP = 0x8 - ADC_TEMP internal temperature sensor.
VDD = 0x9 - ADC_VDD internal power rail connection.
VSS = 0xA - ADC_VSS internal ground connection.
VBATT = 0xC - ADC_VBATT internal voltage divide-by-3 connection to input power rail.
7:2 RSVD RO RESERVED.

1 WCEN6 RW This bit enables the window compare function for slot 6.

WCEN = 0x1 - Enable the window compare for slot 6.
0 SLEN6 RW This bit enables slot 6 for ADC conversions.

SLEN = 0x1 - Enable slot 6 for ADC conversions.

SL7CFG - Slot 7 Configuration Register

Address:

  Instance 0 Address:   0x50008028

Description:

Slot 7 Configuration Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADSEL7
0x0
RSVD
0x0
THSEL7
0x0
RSVD
0x0
CHSEL7
0x0
RSVD
0x0
WCEN7
0x0
SLEN7
0x0

Bits Name RW Description
31:27 RSVD RO RESERVED.

26:24 ADSEL7 RW Select the number of measurements to average in the accumulate divide module for this slot.

AVG_1_MSRMT = 0x0 - Average in 1 measurement in the accumulate divide module for this slot.
AVG_2_MSRMTS = 0x1 - Average in 2 measurements in the accumulate divide module for this slot.
AVG_4_MSRMTS = 0x2 - Average in 4 measurements in the accumulate divide module for this slot.
AVG_8_MSRMT = 0x3 - Average in 8 measurements in the accumulate divide module for this slot.
AVG_16_MSRMTS = 0x4 - Average in 16 measurements in the accumulate divide module for this slot.
AVG_32_MSRMTS = 0x5 - Average in 32 measurements in the accumulate divide module for this slot.
AVG_64_MSRMTS = 0x6 - Average in 64 measurements in the accumulate divide module for this slot.
AVG_128_MSRMTS = 0x7 - Average in 128 measurements in the accumulate divide module for this slot.
23:19 RSVD RO RESERVED.

18:16 THSEL7 RW Select track and hold delay for this slot. NOTE: The track and hold delay must be less than 50us for correct operation. When the ADC is configured to use the 1.5Mhz clock, the track and hold delay cannot exceed 64 clocks.

1_ADC_CLK = 0x0 - 1 ADC clock cycle.
2_ADC_CLKS = 0x1 - 2 ADC clock cycles.
4_ADC_CLKS = 0x2 - 4 ADC clock cycles.
8_ADC_CLKS = 0x3 - 8 ADC clock cycles.
16_ADC_CLKS = 0x4 - 16 ADC clock cycles.
32_ADC_CLKS = 0x5 - 32 ADC clock cycles.
64_ADC_CLKS = 0x6 - 64 ADC clock cycles.
128_ADC_CLKS = 0x7 - 128 ADC clock cycles.
15:12 RSVD RO RESERVED.

11:8 CHSEL7 RW Select one of the 13 channel inputs for this slot.

EXT0 = 0x0 - ADC_EXT0 external GPIO pin connection.
EXT1 = 0x1 - ADC_EXT1 external GPIO pin connection.
EXT2 = 0x2 - ADC_EXT2 external GPIO pin connection.
EXT3 = 0x3 - ADC_EXT3 external GPIO pin connection.
EXT4 = 0x4 - ADC_EXT4 external GPIO pin connection.
EXT5 = 0x5 - ADC_EXT5 external GPIO pin connection.
EXT6 = 0x6 - ADC_EXT6 external GPIO pin connection.
EXT7 = 0x7 - ADC_EXT7 external GPIO pin connection.
TEMP = 0x8 - ADC_TEMP internal temperature sensor.
VDD = 0x9 - ADC_VDD internal power rail connection.
VSS = 0xA - ADC_VSS internal ground connection.
VBATT = 0xC - ADC_VBATT internal voltage divide-by-3 connection to input power rail.
7:2 RSVD RO RESERVED.

1 WCEN7 RW This bit enables the window compare function for slot 7.

WCEN = 0x1 - Enable the window compare for slot 7.
0 SLEN7 RW This bit enables slot 7 for ADC conversions.

SLEN = 0x1 - Enable slot 7 for ADC conversions.

WLIM - Window Comparator Limits Register

Address:

  Instance 0 Address:   0x5000802C

Description:

Window Comparator Limits Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ULIM
0x0
LLIM
0x0

Bits Name RW Description
31:16 ULIM RW Sets the upper limit for the wondow comparator.

15:0 LLIM RW Sets the lower limit for the wondow comparator.


FIFO - FIFO Data and Valid Count Register

Address:

  Instance 0 Address:   0x50008030

Description:

The ADC FIFO Register contains the slot number and fifo data for the oldest conversion data in the FIFO. The COUNT field indicates the total number of valid entries in the FIFO. A write to this register will pop one of the FIFO entries off the FIFO and decrease the COUNT by 1 if the COUNT is greater than zero.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD_27
0x0
SLOTNUM
0x0
RSVD_20
0x0
COUNT
0x0
DATA
0x0

Bits Name RW Description
31:27 RSVD_27 RO RESERVED.

26:24 SLOTNUM RO Slot number associated with this FIFO data.

23:20 RSVD_20 RO RESERVED.

19:16 COUNT RO Number of valid entries in the ADC FIFO.

15:0 DATA RO Oldest data in the FIFO.


INTEN - ADC Interrupt registers: Enable

Address:

  Instance 0 Address:   0x50008200

Description:

Set bits in this register to allow this module to generate the corresponding interrupt.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
WCINC
0x0
WCEXC
0x0
FIFOOVR2
0x0
FIFOOVR1
0x0
SCNCMP
0x0
CNVCMP
0x0

Bits Name RW Description
31:6 RSVD RO RESERVED.

5 WCINC RW Window comparator voltage incursion interrupt.

WCINCINT = 0x1 - Window comparitor voltage incursion interrupt.
4 WCEXC RW Window comparator voltage excursion interrupt.

WCEXCINT = 0x1 - Window comparitor voltage excursion interrupt.
3 FIFOOVR2 RW FIFO 100 percent full interrupt.

FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt.
2 FIFOOVR1 RW FIFO 75 percent full interrupt.

FIFO75INT = 0x1 - FIFO 75 percent full interrupt.
1 SCNCMP RW ADC scan complete interrupt.

SCNCMPINT = 0x1 - ADC scan complete interrupt.
0 CNVCMP RW ADC conversion complete interrupt.

CNVCMPINT = 0x1 - ADC conversion complete interrupt.

INTSTAT - ADC Interrupt registers: Status

Address:

  Instance 0 Address:   0x50008204

Description:

Read bits from this register to discover the cause of a recent interrupt.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
WCINC
0x0
WCEXC
0x0
FIFOOVR2
0x0
FIFOOVR1
0x0
SCNCMP
0x0
CNVCMP
0x0

Bits Name RW Description
31:6 RSVD RO RESERVED.

5 WCINC RW Window comparator voltage incursion interrupt.

WCINCINT = 0x1 - Window comparitor voltage incursion interrupt.
4 WCEXC RW Window comparator voltage excursion interrupt.

WCEXCINT = 0x1 - Window comparitor voltage excursion interrupt.
3 FIFOOVR2 RW FIFO 100 percent full interrupt.

FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt.
2 FIFOOVR1 RW FIFO 75 percent full interrupt.

FIFO75INT = 0x1 - FIFO 75 percent full interrupt.
1 SCNCMP RW ADC scan complete interrupt.

SCNCMPINT = 0x1 - ADC scan complete interrupt.
0 CNVCMP RW ADC conversion complete interrupt.

CNVCMPINT = 0x1 - ADC conversion complete interrupt.

INTCLR - ADC Interrupt registers: Clear

Address:

  Instance 0 Address:   0x50008208

Description:

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
WCINC
0x0
WCEXC
0x0
FIFOOVR2
0x0
FIFOOVR1
0x0
SCNCMP
0x0
CNVCMP
0x0

Bits Name RW Description
31:6 RSVD RO RESERVED.

5 WCINC RW Window comparator voltage incursion interrupt.

WCINCINT = 0x1 - Window comparitor voltage incursion interrupt.
4 WCEXC RW Window comparator voltage excursion interrupt.

WCEXCINT = 0x1 - Window comparitor voltage excursion interrupt.
3 FIFOOVR2 RW FIFO 100 percent full interrupt.

FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt.
2 FIFOOVR1 RW FIFO 75 percent full interrupt.

FIFO75INT = 0x1 - FIFO 75 percent full interrupt.
1 SCNCMP RW ADC scan complete interrupt.

SCNCMPINT = 0x1 - ADC scan complete interrupt.
0 CNVCMP RW ADC conversion complete interrupt.

CNVCMPINT = 0x1 - ADC conversion complete interrupt.

INTSET - ADC Interrupt registers: Set

Address:

  Instance 0 Address:   0x5000820C

Description:

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
WCINC
0x0
WCEXC
0x0
FIFOOVR2
0x0
FIFOOVR1
0x0
SCNCMP
0x0
CNVCMP
0x0

Bits Name RW Description
31:6 RSVD RO RESERVED.

5 WCINC RW Window comparator voltage incursion interrupt.

WCINCINT = 0x1 - Window comparitor voltage incursion interrupt.
4 WCEXC RW Window comparator voltage excursion interrupt.

WCEXCINT = 0x1 - Window comparitor voltage excursion interrupt.
3 FIFOOVR2 RW FIFO 100 percent full interrupt.

FIFOFULLINT = 0x1 - FIFO 100 percent full interrupt.
2 FIFOOVR1 RW FIFO 75 percent full interrupt.

FIFO75INT = 0x1 - FIFO 75 percent full interrupt.
1 SCNCMP RW ADC scan complete interrupt.

SCNCMPINT = 0x1 - ADC scan complete interrupt.
0 CNVCMP RW ADC conversion complete interrupt.

CNVCMPINT = 0x1 - ADC conversion complete interrupt.