Apollo Register Documentation  v${version}
MSPI - Multi-bit SPI Master

MSPI Register Index

  0x00000000:   CTRL - MSPI PIO Transfer Control/Status
  0x00000004:   CFG - MSPI Transfer Configuration
  0x00000008:   ADDR - MSPI Transfer Address
  0x0000000C:   INSTR - MSPI Transfer Instruction
  0x00000010:   TXFIFO - TX Data FIFO
  0x00000014:   RXFIFO - RX Data FIFO
  0x00000018:   TXENTRIES - TX FIFO Entries
  0x0000001C:   RXENTRIES - RX FIFO Entries
  0x00000020:   THRESHOLD - TX/RX FIFO Threshold Levels
  0x00000100:   MSPICFG - MSPI Module Configuration
  0x00000104:   MSPIDDR - MSPI Module DDR Configuration Bits
  0x00000110:   PADCFG - MSPI Output Pad Configuration
  0x00000114:   PADOUTEN - MSPI Output Enable Pad Configuration
  0x00000118:   PADOVEREN - MSPI Output Pad Override
  0x0000011C:   PADOVER - MSPI Output Pad Override Value
  0x00000120:   FLASH - Configuration for XIP/DMA support of SPI flash modules.
  0x00000124:   XIPINSTR - Configuration for XIP/DMA support of SPI flash modules.
  0x00000128:   SCRAMBLING - External Flash Scrambling Controls
  0x00000200:   INTEN - MSPI Master Interrupts: Enable
  0x00000204:   INTSTAT - MSPI Master Interrupts: Status
  0x00000208:   INTCLR - MSPI Master Interrupts: Clear
  0x0000020C:   INTSET - MSPI Master Interrupts: Set
  0x00000250:   DMACFG - DMA Configuration
  0x00000254:   DMASTAT - DMA Status
  0x00000258:   DMATARGADDR - DMA Target Address
  0x0000025C:   DMADEVADDR - DMA Device Address
  0x00000260:   DMATOTCOUNT - DMA Total Transfer Count
  0x00000264:   DMABCOUNT - DMA BYTE Transfer Count
  0x00000268:   DMATHRESH - DMA Transmit Trigger Threshold
  0x0000026C:   DMABOUNDARY - DMA Transfer Boundary
  0x000002A0:   CQCFG - Command Queue Configuration
  0x000002A8:   CQADDR - CQ Target Read Address
  0x000002AC:   CQSTAT - Command Queue Status
  0x000002B0:   CQFLAGS - Command Queue Flags
  0x000002B4:   CQSETCLEAR - Command Queue Flag Set/Clear
  0x000002B8:   CQPAUSE - Command Queue Pause Mask
  0x000002C0:   CQCURIDX - Command Queue Current Index
  0x000002C4:   CQENDIDX - Command Queue End Index

CTRL - MSPI PIO Transfer Control/Status

Address:

  Instance 0 Address:   0x50014000
  Instance 1 Address:   0x50015000
  Instance 2 Address:   0x50016000

Description:

This register is used to enable individual PIO based transactions to a device on the bus. The CFG register must be programmed properly for the transfer, and the ADDR and INSTR registers should be programmed if the SENDI and SENDA fields are enabled.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFERBYTES
0x0
RSVD
0x0
ENDCX
0x0
PIOSCRAMBLE
0x0
TXRX
0x0
SENDI
0x0
SENDA
0x0
ENTURN
0x0
BIGENDIAN
0x0
CONT
0x0
ENWLAT
0x0
QUADCMD
0x0
BUSY
0x0
STATUS
0x0
START
0x0

Bits Name RW Description
31:16 XFERBYTES RW Number of bytes to transmit or receive (based on TXRX bit)

15:13 RSVD RO RESERVED

12 ENDCX RW Enable DCX signal on data [1]

11 PIOSCRAMBLE RW Enables data scrambling for PIO operations. This should only be used for data operations and never for commands to a device.

10 TXRX RW 1 Indicates a TX operation, 0 indicates an RX operation of XFERBYTES

9 SENDI RW Indicates whether an instruction phase should be sent (see INSTR field and ISIZE field in CFG register)

8 SENDA RW Indicates whether an address phase should be sent (see ADDR register and ASIZE field in CFG register)

7 ENTURN RW Indicates whether TX->RX turnaround cycles should be enabled for this operation (see TURNAROUND field in CFG register).

6 BIGENDIAN RW 1 indicates data in FIFO is in big endian format (MSB first); 0 indicates little endian data (default, LSB first).

5 CONT RW Continuation transfer. When 1, indicates that the MSPI will hold CE low after the transaction completes. This is included for compatibility with IOM module since the MSPI transfer module can handle most cases in a single transfer. NOTE: CONT functionality only works with CLKDIV=2 (24 MHz).

4 ENWLAT RW Enable Write Latency Counter (time between address and first data byte). Counter value is WRITELATENCY.

3 QUADCMD RW Flag indicating that the operation is a command that should be replicated to both devices in paired QUAD mode. This is typically only used when reading/writing configuration registers in paired flash devices (do not set for memory transfers).

2 BUSY RO Command status: 1 indicates controller is busy (command in progress)

1 STATUS RO Command status: 1 indicates command has completed. Cleared by writing 1 to this bit or starting a new transfer.

0 START RW Write to 1 to initiate a PIO transaction on the bus (typically the entire register should be written at once with this bit set).


CFG - MSPI Transfer Configuration

Address:

  Instance 0 Address:   0x50014004
  Instance 1 Address:   0x50015004
  Instance 2 Address:   0x50016004

Description:

Command formatting for PIO based transactions (initiated by writes to CTRL register)

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
WRITELATENCY
0x0
RSVD
0x0
CPOL
0x0
CPHA
0x0
RSVD
0x0
TURNAROUND
0x0
SEPIO
0x0
ISIZE
0x0
ASIZE
0x0
DEVCFG
0x1

Bits Name RW Description
31:26 RSVD RO RESERVED

25:20 WRITELATENCY RW Number of cycles between addressn and TX data. Qualified by ENLAT

19:18 RSVD RO RESERVED

17 CPOL RW Serial clock polarity.

LOW = 0x0 - Clock inactive state is low.
HIGH = 0x1 - Clock inactive state is high.
16 CPHA RW Serial clock phase.

MIDDLE = 0x0 - Clock toggles in middle of data bit.
START = 0x1 - Clock toggles at start of data bit.
15:14 RSVD RO RESERVED

13:8 TURNAROUND RW Number of turnaround cycles (for TX->RX transitions). Qualified by ENTURN or XIPENTURN bit field.

7 SEPIO RW Separate IO configuration. This bit should be set when the target device has separate MOSI and MISO pins. Respective IN/OUT bits below should be set to map pins.

6 ISIZE RW Instruction Size enum name = I8 value = 0x0 desc = Instruction is 1 byte enum name = I16 value = 0x1 desc = Instruction is 2 bytes

5:4 ASIZE RW Address Size. Address bytes to send from ADDR register

A1 = 0x0 - Send one address byte
A2 = 0x1 - Send two address bytes
A3 = 0x2 - Send three address bytes
A4 = 0x3 - Send four address bytes
3:0 DEVCFG RW Flash configuration for XIP and AUTO DMA operations. Controls value for SER (Slave Enable) for XIP operations and address generation for DMA/XIP modes. Also used to configure SPIFRF (frame format).

SERIAL0 = 0x1 - Single bit SPI flash on chip select 0
SERIAL1 = 0x2 - Single bit SPI flash on chip select 1
DUAL0 = 0x5 - Dual SPI flash on chip select 0
DUAL1 = 0x6 - Dual bit SPI flash on chip select 1
QUAD0 = 0x9 - Quad SPI flash on chip select 0
QUAD1 = 0xA - Quad SPI flash on chip select 1
OCTAL0 = 0xD - Octal SPI flash on chip select 0
OCTAL1 = 0xE - Octal SPI flash on chip select 1

ADDR - MSPI Transfer Address

Address:

  Instance 0 Address:   0x50014008
  Instance 1 Address:   0x50015008
  Instance 2 Address:   0x50016008

Description:

Optional Address field to send for PIO transfers

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
0x0

Bits Name RW Description
31:0 ADDR RW Optional Address field to send (after optional instruction field) - qualified by ASIZE in CMD register. NOTE: This register is aliased to DMADEVADDR.


INSTR - MSPI Transfer Instruction

Address:

  Instance 0 Address:   0x5001400C
  Instance 1 Address:   0x5001500C
  Instance 2 Address:   0x5001600C

Description:

Optional Instruction field to send for PIO transfers

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
INSTR
0x0

Bits Name RW Description
31:16 RSVD RO RESERVED

15:0 INSTR RW Optional Instruction field to send (1st byte) - qualified by ISEND/ISIZE


TXFIFO - TX Data FIFO

Address:

  Instance 0 Address:   0x50014010
  Instance 1 Address:   0x50015010
  Instance 2 Address:   0x50016010

Description:

TX Data FIFO

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXFIFO
0x0

Bits Name RW Description
31:0 TXFIFO WO Data to be transmitted. Data should normally be aligned to the LSB (pad the upper bits with zeros) unless BIGENDIAN is set.


RXFIFO - RX Data FIFO

Address:

  Instance 0 Address:   0x50014014
  Instance 1 Address:   0x50015014
  Instance 2 Address:   0x50016014

Description:

RX Data FIFO

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXFIFO
0x0

Bits Name RW Description
31:0 RXFIFO RO Receive data. Data is aligned to the LSB (padded zeros on upper bits) unless BIGENDIAN is set.


TXENTRIES - TX FIFO Entries

Address:

  Instance 0 Address:   0x50014018
  Instance 1 Address:   0x50015018
  Instance 2 Address:   0x50016018

Description:

Number of words in TX FIFO

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
TXENTRIES
0x0

Bits Name RW Description
31:6 RSVD RO RESERVED

5:0 TXENTRIES RO Number of 32-bit words/entries in TX FIFO


RXENTRIES - RX FIFO Entries

Address:

  Instance 0 Address:   0x5001401C
  Instance 1 Address:   0x5001501C
  Instance 2 Address:   0x5001601C

Description:

Number of words in RX FIFO

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
RXENTRIES
0x0

Bits Name RW Description
31:6 RSVD RO RESERVED

5:0 RXENTRIES RO Number of 32-bit words/entries in RX FIFO


THRESHOLD - TX/RX FIFO Threshold Levels

Address:

  Instance 0 Address:   0x50014020
  Instance 1 Address:   0x50015020
  Instance 2 Address:   0x50016020

Description:

Threshold levels that trigger RXFull and TXEmpty interrupts

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
RSVD
0x0
RXTHRESH
0x0
RSVD
0x0
TXTHRESH
0x0

Bits Name RW Description
31:16 RSVD RO RESERVED

15:14 RSVD RO RESERVED

13:8 RXTHRESH RW Number of entries in TX FIFO that cause RXE interrupt

7:6 RSVD RO RESERVED

5:0 TXTHRESH RW Number of entries in TX FIFO that cause TXF interrupt


MSPICFG - MSPI Module Configuration

Address:

  Instance 0 Address:   0x50014100
  Instance 1 Address:   0x50015100
  Instance 2 Address:   0x50016100

Description:

Timing configuration bits for the MSPI module. PRSTN, IPRSTN, and FIFORESET can be used to reset portions of the MSPI interface in order to clear error conditions. The remaining bits control clock frequency and TX/RX capture timings.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRSTN
0x1
IPRSTN
0x1
FIFORESET
0x0
RSVD
0x0
CLKDIV
0x2
IOMSEL
0x0
TXNEG
0x0
RXNEG
0x0
RXCAP
0x0
APBCLK
0x0

Bits Name RW Description
31 PRSTN RW Peripheral reset. Master reset to the entire MSPI module (DMA, XIP, and transfer state machines). 1=normal operation, 0=in reset.

30 IPRSTN RW IP block reset. Write to 0 to put the transfer module in reset or 1 for normal operation. This may be required after error conditions to clear the transfer on the bus.

29 FIFORESET RW Reset MSPI FIFO (active high). 1=reset FIFO, 0=normal operation. May be used to manually flush the FIFO in error handling.

28:14 RSVD RO RESERVED

13:8 CLKDIV RW Clock Divider. Allows dividing 48 MHz base clock by integer multiples. Enumerations are provided for common frequency, but any integer divide from 48 MHz is allowed. Odd divide ratios will result in a 33/66 percent duty cycle with a long low clock pulse (to allow longer round-trip for read data).

CLK48 = 0x1 - 48 MHz MSPI clock
CLK24 = 0x2 - 24 MHz MSPI clock
CLK12 = 0x4 - 12 MHz MSPI clock
CLK6 = 0x8 - 6 MHz MSPI clock
CLK3 = 0x10 - 3 MHz MSPI clock
CLK1_5 = 0x20 - 1.5 MHz MSPI clock
7:4 IOMSEL RW Selects which IOM is selected for CQ handshake status.

IOM0 = 0x0 - Select IOM0
IOM1 = 0x1 - Select IOM1
IOM2 = 0x2 - Select IOM2
IOM3 = 0x3 - Select IOM3
IOM4 = 0x4 - Select IOM4
IOM5 = 0x5 - Select IOM5
MSPI0 = 0x8 - Select MSPI0
MSPI1 = 0x9 - Select MSPI1
MSPI2 = 0xA - Select MSPI2
DISABLED = 0x7 - No IOM selected. Signals always zero.
3 TXNEG RW Launches TX data a half clock cycle (~10 ns) early. This should normally be programmed to zero (NORMAL).

NORMAL = 0x0 - TX launched from posedge internal clock
NEGEDGE = 0x1 - TX data launched from negedge of internal clock
2 RXNEG RW Adjusts the RX capture phase to the negedge of the 48MHz internal clock (~10 ns early). For normal operation, it is expected that RXNEG will be set to 0.

NORMAL = 0x0 - RX data sampled on posedge of internal clock
NEGEDGE = 0x1 - RX data sampled on negedge of internal clock
1 RXCAP RW Controls RX data capture phase. A setting of 0 (NORMAL) captures read data at the normal capture point relative to the internal clock launch point. However, to accommodate chip/pad/board delays, a setting of RXCAP of 1 is expected to be used to align the capture point with the return data window. This bit is used in conjunction with RXNEG to provide 4 unique capture points, all about 10 ns apart.

NORMAL = 0x0 - RX Capture phase aligns with CPHA setting
DELAY = 0x1 - RX Capture phase is delayed from CPHA setting by one clock edge
0 APBCLK RW Enable continuous APB clock. For power-efficient operation, APBCLK should be set to 0.

DIS = 0x0 - Disable continuous clock.
EN = 0x1 - Enable continuous clock.

MSPIDDR - MSPI Module DDR Configuration Bits

Address:

  Instance 0 Address:   0x50014104
  Instance 1 Address:   0x50015104
  Instance 2 Address:   0x50016104

Description:

Timing configuration bits for DDR operation of the MSPI module.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
RSVD
0x0
TXDQSDELAY
0x0
RSVD
0x0
RXDQSDELAY
0x0
RSVD
0x0
ENABLEFINEDELAY
0x0
OVERRIDEDDRCLKOUTDELAY
0x0
OVERRIDERXDQSDELAY
0x0
DQSSYNCNEG
0x0
ENABLEDQS
0x0
QUADDDR
0x0
EMULATEDDR
0x0

Bits Name RW Description
31:24 RSVD RO RESERVED

23:21 RSVD RO RESERVED

20:16 TXDQSDELAY RW When OVERRIDEDQSDELAY is set this sets the DQS delay line value. In ENABLEDQS mode, this acts as an offset to the computed value (should be set to 0 by default)

15:13 RSVD RO RESERVED

12:8 RXDQSDELAY RW When OVERRIDEDQSDELAY is set this sets the DQS delay line value. In ENABLEDQS mode, this acts as an offset to the computed value (should be set to 0 by default)

7 RSVD RO RESERVED

6 ENABLEFINEDELAY RW Enables use of delay line to provide fine control over traditional RX capture clock.

5 OVERRIDEDDRCLKOUTDELAY RW Override TX delay line with the value in DQSDELAY (for TX clock offset when in QUADDDR mode)

4 OVERRIDERXDQSDELAY RW Override DQS delay line with the value in DQSDELAY (for RX capture in QUADDDR mode)

3 DQSSYNCNEG RW Use negative edge of clock for DDR data sync

2 ENABLEDQS RW In EMULATEDDR mode, enable DQS for read capture

1 QUADDDR RW Enables use of delay line to provide fine control over traditional RX capture clock.

0 EMULATEDDR RW Drive external clock at 1/2 rate to emulate DDR mode


PADCFG - MSPI Output Pad Configuration

Address:

  Instance 0 Address:   0x50014110
  Instance 1 Address:   0x50015110
  Instance 2 Address:   0x50016110

Description:

Configuration bits for the MSPI pads. Allows pads associated with the upper quad to be mapped to corresponding bits on the lower quad. Use of Quad0 pins is recommended for optimal timing.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
REVCS
0x0
IN3
0x0
IN2
0x0
IN1
0x0
IN0
0x0
RSVD
0x0
OUT7
0x0
OUT6
0x0
OUT5
0x0
OUT4
0x0
OUT3
0x0

Bits Name RW Description
31:22 RSVD RO RESERVED

21 REVCS RW Reverse CS connections. Allows CS1 to be associated with lower data lanes and CS0 to be associated with upper data lines

20 IN3 RW Data Input pad 3 pin muxing: 0=pad[3] 1=pad[7]

19 IN2 RW Data Input pad 2 pin muxing: 0=pad[2] 1=pad[6]

18 IN1 RW Data Input pad 1 pin muxing: 0=pad[1] 1=pad[5]

17:16 IN0 RW Data Input pad 0 pin muxing: 0=pad[0] 1=pad[4] 2=pad[1] 3=pad[5]

15:5 RSVD RO RESERVED

4 OUT7 RW Output pad 7 configuration. 0=data[7] 1=data[3]

3 OUT6 RW Output pad 6 configuration. 0=data[6] 1=data[2]

2 OUT5 RW Output pad 5 configuration. 0=data[5] 1=data[1]

1 OUT4 RW Output pad 4 configuration. 0=data[4] 1=data[0]

0 OUT3 RW Output pad 3 configuration. 0=data[3] 1=CLK


PADOUTEN - MSPI Output Enable Pad Configuration

Address:

  Instance 0 Address:   0x50014114
  Instance 1 Address:   0x50015114
  Instance 2 Address:   0x50016114

Description:

Enable bits for the MSPI output pads. Each active MSPI line should be set to 1 in the OUTEN field below.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
OUTEN
0x0

Bits Name RW Description
31:10 RSVD RO RESERVED

9:0 OUTEN RW Output pad enable configuration. Indicates which pads should be driven. Bits [3:0] are Quad0 data, [7:4] are Quad1 data, and [8] is clock.

QUAD0 = 0x10F - Quad0 (4 data + 1 clock)
QUAD1 = 0x1F0 - Quad1 (4 data + 1 clock)
OCTAL = 0x3FF - Octal (8 data + 1 clock)
SERIAL0 = 0x103 - Serial (2 data + 1 clock)
SERIAL1 = 0x130 - Serial (2 data + 1 clock)

PADOVEREN - MSPI Output Pad Override

Address:

  Instance 0 Address:   0x50014118
  Instance 1 Address:   0x50015118
  Instance 2 Address:   0x50016118

Description:

Enables PIO-like pad override control

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
OVERRIDEEN
0x0

Bits Name RW Description
31:10 RSVD RO RESERVED

9:0 OVERRIDEEN RW Output pad override enable. Bit mask for pad outputs. When set to 1, the values in the OVERRIDE field are driven on the pad (output enable is implicitly set in this mode). [7:0]=data [8]=clock [9]=DM


PADOVER - MSPI Output Pad Override Value

Address:

  Instance 0 Address:   0x5001411C
  Instance 1 Address:   0x5001511C
  Instance 2 Address:   0x5001611C

Description:

Override data value

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
OVERRIDE
0x0

Bits Name RW Description
31:10 RSVD RO RESERVED

9:0 OVERRIDE RW Output pad override value. [7:0]=data [8]=clock [9]=DM


FLASH - Configuration for XIP/DMA support of SPI flash modules.

Address:

  Instance 0 Address:   0x50014120
  Instance 1 Address:   0x50015120
  Instance 2 Address:   0x50016120

Description:

When any SPI flash is configured, this register must be properly programmed before XIP or AUTO DMA operations commence.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
XIPENWLAT
0x0
XIPMIXED
0x0
XIPSENDI
0x0
XIPSENDA
0x0
XIPENTURN
0x0
XIPBIGENDIAN
0x0
XIPACK
0x0
XIPENDCX
0x0
XIPEN
0x0

Bits Name RW Description
31:12 RSVD RO RESERVED

11 XIPENWLAT RW Enable Write Latency counter for XIP write transactions

10:8 XIPMIXED RW Reserved. Set to 0x0

NORMAL = 0x0 - Transfers all proceed using the settings in DEVCFG register (everything in the same data rate)
D2 = 0x1 - Data operations proceed in dual data rate
AD2 = 0x3 - Address and Data operations proceed in dual data rate
D4 = 0x5 - Data operations proceed in quad data rate
AD4 = 0x7 - Address and Data operations proceed in quad data rate
7 XIPSENDI RW Indicates whether XIP/AUTO DMA operations should send an instruction (see READINSTR field and ISIZE field in CFG)

6 XIPSENDA RW Indicates whether XIP/AUTO DMA operations should send an an address phase (see DMADEVADDR register and ASIZE field in CFG)

5 XIPENTURN RW Indicates whether XIP/AUTO DMA operations should enable TX->RX turnaround cycles

4 XIPBIGENDIAN RW Indicates whether XIP/AUTO DMA data transfers are in big or little endian format

3:2 XIPACK RW Controls transmission of Micron XIP acknowledge cycles (Micron Flash devices only)

NOACK = 0x0 - No acknowledgment sent. Data IOs are tri-stated the first turnaround cycle
ACK = 0x2 - Positive acknowledgment sent. Data IOs are driven to 0 the first turnaround cycle to acknowledge XIP mode
TERMINATE = 0x3 - Negative acknowledgment sent. Data IOs are driven to 1 the first turnaround cycle to terminate XIP mode. XIPSENDI should be re-enabled for the next transfer
1 XIPENDCX RW Enable DCX signal on data [1] for XIP/DMA operations

0 XIPEN RW Enable the XIP (eXecute In Place) function which effectively enables the address decoding of the MSPI device in the flash/cache address space at address 0x04000000-0x07FFFFFF.


XIPINSTR - Configuration for XIP/DMA support of SPI flash modules.

Address:

  Instance 0 Address:   0x50014124
  Instance 1 Address:   0x50015124
  Instance 2 Address:   0x50016124

Description:

When any SPI flash is configured, this register must be properly programmed before XIP or AUTO DMA operations commence.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
READINSTR
0xb
WRITEINSTR
0x6

Bits Name RW Description
31:16 READINSTR RW Read command sent to flash for DMA/XIP operations

15:0 WRITEINSTR RW Write command sent for DMA operations


SCRAMBLING - External Flash Scrambling Controls

Address:

  Instance 0 Address:   0x50014128
  Instance 1 Address:   0x50015128
  Instance 2 Address:   0x50016128

Description:

Enables data scrambling for the specified range external flash addresses. Scrambling does not impact flash access performance.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRENABLE
0x0
RSVD
0x0
SCREND
0x0
RSVD
0x0
SCRSTART
0x0

Bits Name RW Description
31 SCRENABLE RW Enables Data Scrambling Region. When 1 reads and writes to the range will be scrambled. When 0, data will be read/written unmodified. Address range is specified in 64K granularity and the START/END ranges are included within the range.

30:26 RSVD RO RESERVED

25:16 SCREND RW Scrambling region end address [25:16] (64K block granularity). The END block is the LAST block included in the scrambled address range.

15:10 RSVD RO RESERVED

9:0 SCRSTART RW Scrambling region start address [25:16] (64K block granularity). The START block is the FIRST block included in the scrambled address range.


INTEN - MSPI Master Interrupts: Enable

Address:

  Instance 0 Address:   0x50014200
  Instance 1 Address:   0x50015200
  Instance 2 Address:   0x50016200

Description:

Set bits in this register to allow this module to generate the corresponding interrupt.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
SCRERR
0x0
CQERR
0x0
CQPAUSED
0x0
CQUPD
0x0
CQCMP
0x0
DERR
0x0
DCMP
0x0
RXF
0x0
RXO
0x0
RXU
0x0
TXO
0x0
TXE
0x0
CMDCMP
0x0

Bits Name RW Description
31:13 RSVD RO RESERVED

12 SCRERR RW Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address.

11 CQERR RW Command Queue Error Interrupt

10 CQPAUSED RW Command Queue is Paused.

9 CQUPD RW Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts.

8 CQCMP RW Command Queue Complete Interrupt

7 DERR RW DMA Error Interrupt

6 DCMP RW DMA Complete Interrupt

5 RXF RW Receive FIFO full

4 RXO RW Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)

3 RXU RW Receive FIFO underflow (only occurs when SW reads from an empty FIFO)

2 TXO RW Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).

1 TXE RW Transmit FIFO empty.

0 CMDCMP RW Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.


INTSTAT - MSPI Master Interrupts: Status

Address:

  Instance 0 Address:   0x50014204
  Instance 1 Address:   0x50015204
  Instance 2 Address:   0x50016204

Description:

Read bits from this register to discover the cause of a recent interrupt.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
SCRERR
0x0
CQERR
0x0
CQPAUSED
0x0
CQUPD
0x0
CQCMP
0x0
DERR
0x0
DCMP
0x0
RXF
0x0
RXO
0x0
RXU
0x0
TXO
0x0
TXE
0x0
CMDCMP
0x0

Bits Name RW Description
31:13 RSVD RO RESERVED

12 SCRERR RW Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address.

11 CQERR RW Command Queue Error Interrupt

10 CQPAUSED RW Command Queue is Paused.

9 CQUPD RW Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts.

8 CQCMP RW Command Queue Complete Interrupt

7 DERR RW DMA Error Interrupt

6 DCMP RW DMA Complete Interrupt

5 RXF RW Receive FIFO full

4 RXO RW Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)

3 RXU RW Receive FIFO underflow (only occurs when SW reads from an empty FIFO)

2 TXO RW Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).

1 TXE RW Transmit FIFO empty.

0 CMDCMP RW Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.


INTCLR - MSPI Master Interrupts: Clear

Address:

  Instance 0 Address:   0x50014208
  Instance 1 Address:   0x50015208
  Instance 2 Address:   0x50016208

Description:

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
SCRERR
0x0
CQERR
0x0
CQPAUSED
0x0
CQUPD
0x0
CQCMP
0x0
DERR
0x0
DCMP
0x0
RXF
0x0
RXO
0x0
RXU
0x0
TXO
0x0
TXE
0x0
CMDCMP
0x0

Bits Name RW Description
31:13 RSVD RO RESERVED

12 SCRERR RW Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address.

11 CQERR RW Command Queue Error Interrupt

10 CQPAUSED RW Command Queue is Paused.

9 CQUPD RW Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts.

8 CQCMP RW Command Queue Complete Interrupt

7 DERR RW DMA Error Interrupt

6 DCMP RW DMA Complete Interrupt

5 RXF RW Receive FIFO full

4 RXO RW Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)

3 RXU RW Receive FIFO underflow (only occurs when SW reads from an empty FIFO)

2 TXO RW Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).

1 TXE RW Transmit FIFO empty.

0 CMDCMP RW Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.


INTSET - MSPI Master Interrupts: Set

Address:

  Instance 0 Address:   0x5001420C
  Instance 1 Address:   0x5001520C
  Instance 2 Address:   0x5001620C

Description:

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
SCRERR
0x0
CQERR
0x0
CQPAUSED
0x0
CQUPD
0x0
CQCMP
0x0
DERR
0x0
DCMP
0x0
RXF
0x0
RXO
0x0
RXU
0x0
TXO
0x0
TXE
0x0
CMDCMP
0x0

Bits Name RW Description
31:13 RSVD RO RESERVED

12 SCRERR RW Scrambling Alignment Error. Scrambling operations must be aligned to word (4-byte) start address.

11 CQERR RW Command Queue Error Interrupt

10 CQPAUSED RW Command Queue is Paused.

9 CQUPD RW Command Queue Update Interrupt. Issued whenever the CQ performs an operation where address bit[0] is set. Useful for triggering CURIDX interrupts.

8 CQCMP RW Command Queue Complete Interrupt

7 DERR RW DMA Error Interrupt

6 DCMP RW DMA Complete Interrupt

5 RXF RW Receive FIFO full

4 RXO RW Receive FIFO overflow (cannot happen in MSPI design -- MSPI bus pins will stall)

3 RXU RW Receive FIFO underflow (only occurs when SW reads from an empty FIFO)

2 TXO RW Transmit FIFO Overflow (only occurs when SW writes to a full FIFO).

1 TXE RW Transmit FIFO empty.

0 CMDCMP RW Transfer complete. Note that DMA and CQ operations are layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.


DMACFG - DMA Configuration

Address:

  Instance 0 Address:   0x50014250
  Instance 1 Address:   0x50015250
  Instance 2 Address:   0x50016250

Description:

DMA Configuration

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DMAPWROFF
0x0
RSVD
0x0
DMAPRI
0x0
DMADIR
0x0
DMAEN
0x0

Bits Name RW Description
31:19 RSVD RO RESERVED.

18 DMAPWROFF RW Power off MSPI domain upon completion of DMA operation.

17:5 RSVD RO RESERVED.

4:3 DMAPRI RW Sets the Priority of the DMA request

LOW = 0x0 - Low Priority (service as best effort)
HIGH = 0x1 - High Priority (service immediately)
AUTO = 0x2 - Auto Priority (priority raised once TX FIFO empties or RX FIFO fills)
2 DMADIR RW Direction

P2M = 0x0 - Peripheral to Memory (SRAM) transaction
M2P = 0x1 - Memory to Peripheral transaction
1:0 DMAEN RW DMA Enable. Setting this bit to EN will start the DMA operation

DIS = 0x0 - Disable DMA Function
EN = 0x3 - Enable HW controlled DMA Function to manage DMA to flash devices. HW will automatically handle issuance of instruction/address bytes based on settings in the FLASH register.

DMASTAT - DMA Status

Address:

  Instance 0 Address:   0x50014254
  Instance 1 Address:   0x50015254
  Instance 2 Address:   0x50016254

Description:

DMA Status

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
SCRERR
0x0
DMAERR
0x0
DMACPL
0x0
DMATIP
0x0

Bits Name RW Description
31:4 RSVD RO RESERVED.

3 SCRERR RW Scrambling Access Alignment Error. This active high bit signals that a scrambling operation was specified for a non-word aligned DEVADDR.

2 DMAERR RW DMA Error. This active high bit signals that an error was encountered during the DMA operation.

1 DMACPL RW DMA Transfer Complete. This signals the end of the DMA operation.

0 DMATIP RO DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is active. The DMA transfer may be waiting on data, transferring data, or waiting for priority. All of these will be indicated with a 1. A 0 will indicate that the DMA is fully complete and no further transactions will be done.


DMATARGADDR - DMA Target Address

Address:

  Instance 0 Address:   0x50014258
  Instance 1 Address:   0x50015258
  Instance 2 Address:   0x50016258

Description:

DMA Target Address

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TARGADDR
0x0

Bits Name RW Description
31:0 TARGADDR RW Target byte address for source of DMA (either read or write). In cases of non-word aligned addresses, the DMA logic will take care for ensuring only the target bytes are read/written.


DMADEVADDR - DMA Device Address

Address:

  Instance 0 Address:   0x5001425C
  Instance 1 Address:   0x5001525C
  Instance 2 Address:   0x5001625C

Description:

DMA Device Address

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEVADDR
0x0

Bits Name RW Description
31:0 DEVADDR RW SPI Device address for automated DMA transactions (both read and write).


DMATOTCOUNT - DMA Total Transfer Count

Address:

  Instance 0 Address:   0x50014260
  Instance 1 Address:   0x50015260
  Instance 2 Address:   0x50016260

Description:

DMA Total Transfer Count

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
TOTCOUNT
0x0

Bits Name RW Description
31:24 RSVD RO Reserved

23:0 TOTCOUNT RW Total Transfer Count in bytes.


DMABCOUNT - DMA BYTE Transfer Count

Address:

  Instance 0 Address:   0x50014264
  Instance 1 Address:   0x50015264
  Instance 2 Address:   0x50016264

Description:

DMA BYTE Transfer Count

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
BCOUNT
0x20

Bits Name RW Description
31:8 RSVD RO Reserved

7:0 BCOUNT RW Burst transfer size in bytes. This is the number of bytes transferred when a FIFO trigger event occurs. Recommended value is 32.


DMATHRESH - DMA Transmit Trigger Threshold

Address:

  Instance 0 Address:   0x50014268
  Instance 1 Address:   0x50015268
  Instance 2 Address:   0x50016268

Description:

Indicates FIFO level at which a DMA should be triggered. For most configurations, a setting of 8 is recommended for both read and write operations.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DMARXTHRESH
0x8
RSVD
0x0
DMATXTHRESH
0x8

Bits Name RW Description
31:13 RSVD RO RESERVED

12:8 DMARXTHRESH RW DMA transfer FIFO level trigger. For read operations, DMA is triggered when the FIFO level is greater than this value. For write operations, DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of BCOUNT bytes.

7:5 RSVD RO RESERVED

4:0 DMATXTHRESH RW DMA transfer FIFO level trigger. For read operations, DMA is triggered when the FIFO level is greater than this value. For write operations, DMA is triggered when the FIFO level is less than this level. Each DMA operation will consist of BCOUNT bytes.


DMABOUNDARY - DMA Transfer Boundary

Address:

  Instance 0 Address:   0x5001426C
  Instance 1 Address:   0x5001526C
  Instance 2 Address:   0x5001626C

Description:

Allows large transfers to be broken up into smaller ones in hardware to accommodate needs of external devices and allow XIP/XIPMM. Only applicable for memory-mapped devices (PSRAM, Flash, etc) where address can be retransmitted without side effects.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DMABOUND
0x0
DMATIMELIMIT
0x0

Bits Name RW Description
31:16 RSVD RO RESERVED

15:12 DMABOUND RW DMA Address boundary

NONE = 0x0 - Disable DMA address boundary breaks
BREAK32 = 0x1 - Break at 32 byte boundary (0x20 increments)
BREAK64 = 0x2 - Break at 64 byte boundary (0x40 increments)
BREAK128 = 0x3 - Break at 128 byte boundary (0x80 increments)
BREAK256 = 0x4 - Break at 256 byte boundary (0x100 increments)
BREAK512 = 0x5 - Break at 512 byte boundary (0x200 increments)
BREAK1K = 0x6 - Break at 1KB boundary (0x400 increments)
BREAK2K = 0x7 - Break at 2KB boundary (0x800 increments)
BREAK4K = 0x8 - Break at 4KB boundary (0x1000 increments)
BREAK8K = 0x9 - Break at 8KB boundary (0x2000 increments)
BREAK16K = 0xA - Break at 16KB boundary (0x4000 increments)
11:0 DMATIMELIMIT RW DMA time limit. Can be used to limit the transaction time on the MSPI bus. The count is in 100 ns increments. A value of 0 disables the counter.


CQCFG - Command Queue Configuration

Address:

  Instance 0 Address:   0x500142A0
  Instance 1 Address:   0x500152A0
  Instance 2 Address:   0x500162A0

Description:

This register controls Command Queuing (CQ) operations in a manner similar to the DMACFG register.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CQAUTOCLEARMASK
0x0
CQPWROFF
0x0
CQPRI
0x0
CQEN
0x0

Bits Name RW Description
31:4 RSVD RO RESERVED.

3 CQAUTOCLEARMASK RW Enable clear of CQMASK after each pause operation. This may be useful when using software flags to pause CQ.

2 CQPWROFF RW Power off MSPI domain upon completion of DMA operation.

1 CQPRI RW Sets the Priority of the command queue DMA request

LOW = 0x0 - Low Priority (service as best effort)
HIGH = 0x1 - High Priority (service immediately)
0 CQEN RW Command queue enable. When set, will enable the processing of the command queue

DIS = 0x0 - Disable CQ Function
EN = 0x1 - Enable CQ Function

CQADDR - CQ Target Read Address

Address:

  Instance 0 Address:   0x500142A8
  Instance 1 Address:   0x500152A8
  Instance 2 Address:   0x500162A8

Description:

Location of the command queue in SRAM or flash memory. This register will increment as CQ operations commence. Software should only write CQADDR when CQEN is disabled, however the command queue script itself may update CQADDR in order to perform queue management functions (like resetting the pointers)

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CQADDR
0x0

Bits Name RW Description
31:29 RSVD RO Reserved

28:0 CQADDR RW Address of command queue buffer in SRAM or flash. The buffer address must be aligned to a word boundary.


CQSTAT - Command Queue Status

Address:

  Instance 0 Address:   0x500142AC
  Instance 1 Address:   0x500152AC
  Instance 2 Address:   0x500162AC

Description:

Command Queue Status

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CQPAUSED
0x0
CQERR
0x0
CQCPL
0x0
CQTIP
0x0

Bits Name RW Description
31:4 RSVD RO RESERVED.

3 CQPAUSED RO Command queue is currently paused status.

2 CQERR RW Command queue processing Error. This active high bit signals that an error was encountered during the CQ operation.

1 CQCPL RW Command queue operation Complete. This signals the end of the command queue operation.

0 CQTIP RO Command queue Transfer In Progress indicator. 1 will indicate that a CQ transfer is active and this will remain active even when paused waiting for external event.


CQFLAGS - Command Queue Flags

Address:

  Instance 0 Address:   0x500142B0
  Instance 1 Address:   0x500152B0
  Instance 2 Address:   0x500162B0

Description:

Command Queue Flags

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CQFLAGS
0x0

Bits Name RW Description
31:16 RSVD RO Reserved

15:0 CQFLAGS RO Current flag status (read-only). Bits [7:0] are software controllable and bits [15:8] are hardware status.

STOP = 0x8000 - CQ Stop Flag. When set, CQ processing will complete.
CQIDX = 0x4000 - CQ Index Pointers (CURIDX/ENDIDX) match.
BUF1XOREN = 0x2000 - Buffer 1 Ready Status (from selected IOM/MSPI). This status is the result of XOR'ing the IOM1START with the incoming status from the IOM. When high, MSPI can transfer the buffer.
BUF0XOREN = 0x1000 - Buffer 0 Ready Status (from selected IOM/MSPI). This status is the result of XOR'ing the IOM0START with the incoming status from the IOM. When high, MSPI can transfer the buffer.
DMACPL = 0x800 - DMA Complete Status (hardwired DMACPL bit in DMASTAT)
CMDCPL = 0x400 - PIO Operation completed (STATUS bit in CTRL register)
IOM1READY = 0x200 - IOM Buffer 1 Ready Status (from selected IOM). This status is the result of XNOR'ing the IOM0START with the incoming status from the IOM. When high, MSPI can send to the buffer.
IOM0READY = 0x100 - IOM Buffer 0 Ready Status (from selected IOM). This status is the result of XNOR'ing the IOM0START with the incoming status from the IOM. When high, MSPI can send to the buffer.
BUF1XNOREN = 0x200 - IOM Buffer 1 Ready Status (from selected IOM). This status is the result of XNOR'ing the IOM0START with the incoming status from the IOM. When high, MSPI can send to the buffer.
BUF0XNOREN = 0x100 - IOM Buffer 0 Ready Status (from selected IOM). This status is the result of XNOR'ing the IOM0START with the incoming status from the IOM. When high, MSPI can send to the buffer.
SWFLAG7 = 0x80 - Software flag 7. Can be used by software to start/pause operations.
SWFLAG6 = 0x40 - Software flag 6. Can be used by software to start/pause operations.
SWFLAG5 = 0x20 - Software flag 5. Can be used by software to start/pause operations.
SWFLAG4 = 0x10 - Software flag 4. Can be used by software to start/pause operations.
SWFLAG3 = 0x8 - Software flag 3. Can be used by software to start/pause operations.
SWFLAG2 = 0x4 - Software flag 2. Can be used by software to start/pause operations.
SWFLAG1 = 0x2 - Software flag 1. Can be used by software to start/pause operations.
SWFLAG0 = 0x1 - Software flag 0. Can be used by software to start/pause operations.
IOM1START = 0x2 - IOM Buffer 1 status (same as SWFLAG1). When linked to IOM, indicates to IOM that buffer 1 is ready.
IOM0START = 0x1 - IOM Buffer 0 status (same as SWFLAG0). When linked to IOM, indicates to IOM that buffer 0 is ready.

CQSETCLEAR - Command Queue Flag Set/Clear

Address:

  Instance 0 Address:   0x500142B4
  Instance 1 Address:   0x500152B4
  Instance 2 Address:   0x500162B4

Description:

Command Queue Flag Set/Clear

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CQFCLR
0x0
CQFTOGGLE
0x0
CQFSET
0x0

Bits Name RW Description
31:24 RSVD RO Reserved

23:16 CQFCLR WO Clear CQFlag status bits.

15:8 CQFTOGGLE RO Toggle CQFlag status bits

7:0 CQFSET WO Set CQFlag status bits. Set has priority over clear if both are high.


CQPAUSE - Command Queue Pause Mask

Address:

  Instance 0 Address:   0x500142B8
  Instance 1 Address:   0x500152B8
  Instance 2 Address:   0x500162B8

Description:

Command Queue Pause Mask

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CQMASK
0x0

Bits Name RW Description
31:16 RSVD RO Reserved

15:0 CQMASK RW CQ will pause processing when ALL specified events are satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK.

STOP = 0x8000 - CQ Stop Flag. When set, CQ processing will complete.
CQIDX = 0x4000 - CQ Index Pointers (CURIDX/ENDIDX) match.
BUF1XOREN = 0x2000 - Buffer 1 Ready Status (from selected IOM/MSPI). This status is the result of XOR'ing the IOM1START with the incoming status from the IOM. When high, MSPI can transfer the buffer.
BUF0XOREN = 0x1000 - Buffer 0 Ready Status (from selected IOM/MSPI). This status is the result of XOR'ing the IOM0START with the incoming status from the IOM. When high, MSPI can transfer the buffer.
DMACPL = 0x800 - DMA Complete Status (hardwired DMACPL bit in DMASTAT)
CMDCPL = 0x400 - PIO Operation completed (STATUS bit in CTRL register)
IOM1READY = 0x200 - IOM Buffer 1 Ready Status (from selected IOM). This status is the result of XNOR'ing the IOM0START with the incoming status from the IOM. When high, MSPI can send to the buffer.
IOM0READY = 0x100 - IOM Buffer 0 Ready Status (from selected IOM). This status is the result of XNOR'ing the IOM0START with the incoming status from the IOM. When high, MSPI can send to the buffer.
SWFLAG7 = 0x80 - Software flag 7. Can be used by software to start/pause operations.
SWFLAG6 = 0x40 - Software flag 6. Can be used by software to start/pause operations.
SWFLAG5 = 0x20 - Software flag 5. Can be used by software to start/pause operations.
SWFLAG4 = 0x10 - Software flag 4. Can be used by software to start/pause operations.
SWFLAG3 = 0x8 - Software flag 3. Can be used by software to start/pause operations.
SWFLAG2 = 0x4 - Software flag 2. Can be used by software to start/pause operations.
SWFLAG1 = 0x2 - Software flag 1. Can be used by software to start/pause operations.
SWFLAG0 = 0x1 - Software flag 0. Can be used by software to start/pause operations.
IOM1START = 0x2 - IOM Buffer 1 status (same as SWFLAG1). When linked to IOM, indicates to IOM that buffer 1 is ready.
IOM0START = 0x1 - IOM Buffer 0 status (same as SWFLAG0). When linked to IOM, indicates to IOM that buffer 0 is ready.
BUF1XNOREN = 0x200 - IOM Buffer 1 Ready Status (from selected IOM). This status is the result of XNOR'ing the IOM0START with the incoming status from the IOM. When high, MSPI can send to the buffer.
BUF0XNOREN = 0x100 - IOM Buffer 0 Ready Status (from selected IOM). This status is the result of XNOR'ing the IOM0START with the incoming status from the IOM. When high, MSPI can send to the buffer.

CQCURIDX - Command Queue Current Index

Address:

  Instance 0 Address:   0x500142C0
  Instance 1 Address:   0x500152C0
  Instance 2 Address:   0x500162C0

Description:

This register can be used in conjunction with the CQENDIDX register to manage the command queue. Typically software will initialize the CQCURIDX and CQENDIDX to the same value, which will cause the CQ to be paused when enabled. Software may then add entries to the command queue (in SRAM) and update CQENDIDX. The command queue operations will then increment CQCURIDX as it processes operations. Once CQCURIDX==CQENDIDX, the command queue hardware will automatically pause since no additional operations have been appended to the queue.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CQCURIDX
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED.

7:0 CQCURIDX RW Can be used to indicate the current position of the command queue by having CQ operations write this field. A CQ hardware status flag indicates when CURIDX and ENDIDX are not equal, allowing SW to pause the CQ processing until the end index is updated.


CQENDIDX - Command Queue End Index

Address:

  Instance 0 Address:   0x500142C4
  Instance 1 Address:   0x500152C4
  Instance 2 Address:   0x500162C4

Description:

Command Queue End Index

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CQENDIDX
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED.

7:0 CQENDIDX RW Can be used to indicate the end position of the command queue. A CQ hardware status bit indices when CURIDX != ENDIDX so that the CQ can be paused when it reaches the end pointer.