Apollo Register Documentation  v${version}
RSTGEN - MCU Reset Generator

RSTGEN Register Index

  0x00000000:   CFG - Configuration Register
  0x00000004:   SWPOI - Software POI Reset
  0x00000008:   SWPOR - Software POR Reset
  0x00000014:   TPIURST - TPIU reset
  0x00000200:   INTEN - Reset Interrupt register: Enable
  0x00000204:   INTSTAT - Reset Interrupt register: Status
  0x00000208:   INTCLR - Reset Interrupt register: Clear
  0x0000020C:   INTSET - Reset Interrupt register: Set
  0x0FFFF000:   STAT - Status Register (SBL)

CFG - Configuration Register

Address:

  Instance 0 Address:   0x40000000

Description:

Reset configuration register. This controls the reset enables for brownout condition, and for the expiration of the watch dog timer.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
WDREN
0x0
BODHREN
0x0

Bits Name RW Description
31:2 RSVD RO RESERVED.

1 WDREN RW Watchdog Timer Reset Enable. NOTE: The WDT module must also be configured for WDT reset. This includes enabling the RESEN bit in WDTCFG register in Watch dog timer block.

0 BODHREN RW Brown out high (2.1v) reset enable.


SWPOI - Software POI Reset

Address:

  Instance 0 Address:   0x40000004

Description:

This is the software POI reset. writing the key value to this register will trigger a POI to the system. This will cause a reset to all blocks except for registers in clock gen, RTC and the stimer.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
SWPOIKEY
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED.

7:0 SWPOIKEY WO 0x1B generates a software POI reset. This is a write-only register. Reading from this register will yield only all 0s.

KEYVALUE = 0x1B - Writing 0x1B key value generates a software POI reset.

SWPOR - Software POR Reset

Address:

  Instance 0 Address:   0x40000008

Description:

This is the software POR reset. Writing the key value to this register will trigger a POR to the system. This will cause a reset to all blocks except for registers in clock gen, RTC, power management unit, the stimer, and the power management unit.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
SWPORKEY
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED.

7:0 SWPORKEY WO 0xD4 generates a software POR reset.

KEYVALUE = 0xD4 - Writing 0xD4 key value generates a software POR reset.

TPIURST - TPIU reset

Address:

  Instance 0 Address:   0x40000014

Description:

This will trigger a reset for the TPIU unit.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
TPIURST
0x0

Bits Name RW Description
31:1 RSVD RW RESERVED.

0 TPIURST RW Static reset for the TPIU. Write to '1' to assert reset to TPIU. Write to '0' to clear the reset.


INTEN - Reset Interrupt register: Enable

Address:

  Instance 0 Address:   0x40000200

Description:

Set bits in this register to allow this module to generate the corresponding interrupt.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
BODH
0x0

Bits Name RW Description
31:1 RSVD RO RESERVED.

0 BODH RW Enables an interrupt that triggers when VCC is below BODH level.


INTSTAT - Reset Interrupt register: Status

Address:

  Instance 0 Address:   0x40000204

Description:

Read bits from this register to discover the cause of a recent interrupt.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
BODH
0x0

Bits Name RW Description
31:1 RSVD RO RESERVED.

0 BODH RW Enables an interrupt that triggers when VCC is below BODH level.


INTCLR - Reset Interrupt register: Clear

Address:

  Instance 0 Address:   0x40000208

Description:

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
BODH
0x0

Bits Name RW Description
31:1 RSVD RO RESERVED.

0 BODH RW Enables an interrupt that triggers when VCC is below BODH level.


INTSET - Reset Interrupt register: Set

Address:

  Instance 0 Address:   0x4000020C

Description:

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
BODH
0x0

Bits Name RW Description
31:1 RSVD RO RESERVED.

0 BODH RW Enables an interrupt that triggers when VCC is below BODH level.


STAT - Status Register (SBL)

Address:

  Instance 0 Address:   0x4FFFF000

Description:

This register contains the status for brownout events and the causes for resets.\n NOTE 1: All bits in this register, including reserved bits, are writable. Therefore care should be taken not to write this register.\n NOTE 2: This register does not retain its value across a core deepsleep cycle. Therefore applications needing to use this value after deep sleep must copy and save this register to SRAM before initiating the first deep sleep cycle.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBOOT
0x0
FBOOT
0x0
RSVD
0x0
BOBSTAT
0x0
BOFSTAT
0x0
BOCSTAT
0x0
BOUSTAT
0x0
WDRSTAT
0x0
DBGRSTAT
0x0
POIRSTAT
0x0
SWRSTAT
0x0
BORSTAT
0x0
PORSTAT
0x0
EXRSTAT
0x0

Bits Name RW Description
31 SBOOT RW Set when booting securely (SBL).

30 FBOOT RW Set if current boot was initiated by soft reset and resulted in Fast Boot (SBL).

29:11 RSVD RW RESERVED.

10 BOBSTAT RW A BLE/Burst Regulator Brownout Event occurred (SBL).

9 BOFSTAT RW A Memory Regulator Brownout Event occurred (SBL).

8 BOCSTAT RW A Core Regulator Brownout Event occurred (SBL).

7 BOUSTAT RW An Unregulated Supply Brownout Event occurred (SBL).

6 WDRSTAT RW Reset was initiated by a Watchdog Timer Reset (SBL).

5 DBGRSTAT RW Reset was a initiated by Debugger Reset (SBL).

4 POIRSTAT RW Reset was a initiated by Software POI Reset (SBL).

3 SWRSTAT RW Reset was a initiated by SW POR or AIRCR Reset (SBL).

2 BORSTAT RW Reset was initiated by a Brown-Out Reset (SBL).

1 PORSTAT RW Reset was initiated by a Power-On Reset (SBL).

0 EXRSTAT RW Reset was initiated by an External Reset (SBL).