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Apollo Register Documentation v${version}
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Instance 0 Address: | 0xE000E004 |
Interrupt Controller Type Register (NVIC)
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
INTLINESNUM
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:4 | RSVD | RO | RESERVED. |
3:0 | INTLINESNUM | RW | Total number of interrupt lines in groups of 32. |
Instance 0 Address: | 0xE000E008 |
Auxilliary Control Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
DISFPCA
0x0 |
DISOOFP
0x0 |
RSVD
0x0 |
DISFOLD
0x0 |
DISDEFWBUF
0x0 |
DISMCYCINT
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
30:10 | RSVD | RO | RESERVED. |
9 | DISFPCA | RW | Disables lazy stacking of floating point context. |
8 | DISOOFP | RW | Disables floating point instructions completing out of order with respect to integer instructions. |
6:3 | RSVD | RO | RESERVED. |
2 | DISFOLD | RW | Disables folding of IT instructions. |
1 | DISDEFWBUF | RW | Disables write buffer use during default memory map accesses. |
0 | DISMCYCINT | RW | Disables interruption of multi-cycle instructions. |
Instance 0 Address: | 0xE000ED04 |
Interrupt Control and State Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
NMIPENDSET
0x0 |
PENDSVSET
0x0 |
RSVD
0x0 |
PENDSVCLR
0x0 |
PENDSTSET
0x0 |
PENDSTCLR
0x0 |
RSVD
0x0 |
ISRPREEMPT
0x0 |
ISRPENDING
0x0 |
RSVD
0x0 |
VECTPENDING
0x0 |
RETTOBASE
0x0 |
RSVD
0x0 |
VECTACTIVE
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | NMIPENDSET | RW | Pend an NMI exception. |
28 | PENDSVSET | RW | Set the PendSV interrupt as pending. |
29:28 | RSVD | RO | RESERVED. |
27 | PENDSVCLR | WO | Remove the pending status of the PendSV exception. |
26 | PENDSTSET | RW | Set the SysTick exception as pending. |
25 | PENDSTCLR | WO | Remove the pending status of the SysTick exception. |
24 | RSVD | RO | RESERVED. |
23 | ISRPREEMPT | RO | Indicates whether a pending exception will be serviced on exit from debug halt state. |
22 | ISRPENDING | RO | Indicates whether an external interrupt, generated by the NVIC, is pending. |
21 | RSVD | RO | RESERVED. |
20:12 | VECTPENDING | RO | The exception number of the highest priority pending exception. |
11 | RETTOBASE | RO | Indicates whether there is an active exception other than the exception shown by IPSR. |
10:9 | RSVD | RO | RESERVED. |
8:0 | VECTACTIVE | RO | The exception number of the current executing exception. |
Instance 0 Address: | 0xE000ED08 |
Vector Table Offset Register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VALUE
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | VALUE | RW | Vector table base address. |
Instance 0 Address: | 0xE000ED0C |
Application Interrupt and Reset Control Register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VECTKEY
0x0 |
ENDIANNESS
0x0 |
RSVD
0x0 |
PRIGROUP
0x0 |
RSVD
0x0 |
SYSRESETREQ
0x0 |
VECTCLRACTIVE
0x0 |
VECTRESET
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:16 | VECTKEY | RW | Register writes must write 0x5FA to this field, otherwise the write is ignored. |
15 | ENDIANNESS | RO | Indicates endianness of memory architecture. (Little = 0, Big = 1) |
14:11 | RSVD | RO | RESERVED. |
10:8 | PRIGROUP | RW | Priority grouping, indicates the binary point position. |
7:3 | RSVD | RO | RESERVED. |
2 | SYSRESETREQ | RW | Writing a 1 to this bit reqests a local reset. |
1 | VECTCLRACTIVE | WO | Writing a 1 to this bit clears all active state information for fixed and configurable exceptions. |
0 | VECTRESET | WO | Writing a 1 to this bit causes a local system reset. |
Instance 0 Address: | 0xE000ED10 |
System Control Register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
SEVONPEND
0x0 |
RSVD
0x0 |
SLEEPDEEP
0x0 |
SLEEPONEXIT
0x0 |
RSVD
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:5 | RSVD | RO | RESERVED. |
4 | SEVONPEND | RW | Determines whether a pending interrupt is a wakeup event. |
3 | RSVD | RO | RESERVED. |
2 | SLEEPDEEP | RW | Determines whether the sleep mode should be regular or deep sleep |
1 | SLEEPONEXIT | RW | Determines whether the processor shoudl automatically sleep when an ISR returns to the base-level. |
0 | RSVD | RO | RESERVED. |
Instance 0 Address: | 0xE000ED14 |
Configuration and Control Register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
STKALIGN
0x0 |
BFHFNMIGN
0x0 |
RSVD
0x0 |
DIV0TRP
0x0 |
UNALIGNTRP
0x0 |
RSVD
0x0 |
USERSETMPEND
0x0 |
NONBASETHRDENA
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:10 | RSVD | RO | RESERVED. |
9 | STKALIGN | RW | Set to force 8-byte alignment for the stack pointer. |
8 | BFHFNMIGN | RW | Set to ignore precise data access faults during hard fault handlers. |
7:5 | RSVD | RO | RESERVED. |
4 | DIV0TRP | RW | Set to enable trapping on divide-by-zero. |
3 | UNALIGNTRP | RW | Set to enable trapping of unaligned word or halfword accesses. |
2 | RSVD | RO | RESERVED. |
1 | USERSETMPEND | RW | Set to allow unpriveleged software to access the STIR |
0 | NONBASETHRDENA | RW | Set to enable the processor to enter Thread mode at an execution priority other than base level. |
Instance 0 Address: | 0xE000ED18 |
System Handler Priority Register 1.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRI_7
0x0 |
PRI_6
0x0 |
PRI_5
0x0 |
PRI_4
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:24 | PRI_7 | RW | Reserved for priority of system handler 7. |
23:16 | PRI_6 | RW | Priority of system handler 6, UsageFault. |
15:8 | PRI_5 | RW | Priority of system handler 5, BusFault. |
7:0 | PRI_4 | RW | Priority of system handler 4, MemManage. |
Instance 0 Address: | 0xE000ED1C |
System Handler Priority Register 2.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRI_11
0x0 |
PRI_10
0x0 |
PRI_9
0x0 |
PRI_8
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:24 | PRI_11 | RW | Priority of system handler 11, SVCall. |
23:16 | PRI_10 | RW | Reserved for priority of system handler 10. |
15:8 | PRI_9 | RW | Reserved for priority of system handler 9. |
7:0 | PRI_8 | RW | Reserved for priority of system handler 8. |
Instance 0 Address: | 0xE000ED20 |
System Handler Priority Register 3.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PRI_15
0x0 |
PRI_14
0x0 |
PRI_13
0x0 |
PRI_12
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:24 | PRI_15 | RW | Priority of system handler 15, SysTick. |
23:16 | PRI_14 | RW | Priority of system handler 14, PendSV. |
15:8 | PRI_13 | RW | Reserved for priority of system handler 13. |
7:0 | PRI_12 | RW | Priority of system handler 12, DebugMonitor. |
Instance 0 Address: | 0xE000ED24 |
System Handler Control and State Register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
USAGEFAULTENA
0x0 |
BUSFAULTENA
0x0 |
MEMFAULTENA
0x0 |
SVCALLPENDED
0x0 |
BUSFAULTPENDED
0x0 |
MEMFAULTPENDED
0x0 |
USGFAULTPENDED
0x0 |
SYSTICKACT
0x0 |
PENDSVACT
0x0 |
RSVD
0x0 |
MONITORACT
0x0 |
SVCALLACT
0x0 |
RSVD
0x0 |
USGFAULTACT
0x0 |
RSVD
0x0 |
BUSFAULTACT
0x0 |
MEMFAULTACT
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:19 | RSVD | RO | RESERVED. |
18 | USAGEFAULTENA | RW | Set to enable UsageFault. |
17 | BUSFAULTENA | RW | Set to enable BusFault. |
16 | MEMFAULTENA | RW | Set to enable MemManageFault. |
15 | SVCALLPENDED | RW | Set to pend the SVCall exception. |
14 | BUSFAULTPENDED | RW | Set to pend the BusFault exception. |
13 | MEMFAULTPENDED | RW | Set to pend the MemManageFault exception. |
12 | USGFAULTPENDED | RW | Set to pend the UsageFault exception. |
11 | SYSTICKACT | RW | Set when SysTick is active. |
10 | PENDSVACT | RW | Set when PendSV is active. |
9 | RSVD | RO | RESERVED. |
8 | MONITORACT | RW | Set when Monitor is active. |
7 | SVCALLACT | RW | Set when SVCall is active. |
6:4 | RSVD | RO | RESERVED. |
3 | USGFAULTACT | RW | Set when UsageFault is active. |
2 | RSVD | RO | RESERVED. |
1 | BUSFAULTACT | RW | Set when BusFault is active. |
0 | MEMFAULTACT | RW | Set when MemManageFault is active. |
Instance 0 Address: | 0xE000ED28 |
Configurable Fault Status Register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
RSVD
0x0 |
DIVBYZERO
0x0 |
UNALIGNED
0x0 |
RSVD
0x0 |
NOCP
0x0 |
INVPC
0x0 |
INVSTATE
0x0 |
UNDEFINSTR
0x0 |
BFARVALID
0x0 |
RSVD
0x0 |
LSPERR
0x0 |
STKERR
0x0 |
UNSTKERR
0x0 |
IMPRECISERR
0x0 |
PRECISERR
0x0 |
IBUSERR
0x0 |
MMARVALID
0x0 |
RSVD
0x0 |
MLSPERR
0x0 |
MSTKERR
0x0 |
MUNSTKER
0x0 |
RSVD
0x0 |
DACCVIOL
0x0 |
IACCVIOL
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:26 | RSVD | RO | RESERVED. |
25 | DIVBYZERO | RW | Divide by zero error has occurred. |
24 | UNALIGNED | RW | Unaligned access error has occurred. |
23:20 | RSVD | RO | RESERVED. |
19 | NOCP | RW | A coprocessor access error has occurred. |
18 | INVPC | RW | An integrity check error has occurred on EXC_RETURN. |
17 | INVSTATE | RW | Instruction executed with invalid EPSR.T or EPSR.IT field. |
16 | UNDEFINSTR | RW | Processor attempted to execute an undefined instruction. |
15 | BFARVALID | RW | BFAR has valid contents. |
14 | RSVD | RO | RESERVED. |
13 | LSPERR | RW | A bus fault occurred during FP lazy state preservation. |
12 | STKERR | RW | A derived bus fault has occurred on exception entry. |
11 | UNSTKERR | RW | A derived bus fault has occurred on exception return. |
10 | IMPRECISERR | RW | Imprecise data access error has occurred. |
9 | PRECISERR | RW | A precise data access has occurrred. The faulting address is in BFAR. |
8 | IBUSERR | RW | A bus fault on an instruction prefetch has occurred. |
7 | MMARVALID | RW | MMAR has valid contents. |
6 | RSVD | RO | RESERVED. |
5 | MLSPERR | RW | MemManage fault occurred during FP lazy state preservation. |
4 | MSTKERR | RW | Derived MemManage fault occurred on exception entry. |
3 | MUNSTKER | RW | Derived MemManage fault occurred on exception return. |
2 | RSVD | RO | RESERVED. |
1 | DACCVIOL | RW | Data access violation. Address is in MMAR. |
0 | IACCVIOL | RW | MPU or Execute Never default memory map access violation. |
Instance 0 Address: | 0xE000ED2C |
Hard Fault Status Register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DEBUGEVT
0x0 |
FORCED
0x0 |
RSVD
0x0 |
VECTTBL
0x0 |
RSVD
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | DEBUGEVT | RW | Debug event has occurred. |
30 | FORCED | RW | Processor has elevated a configurable-priority fault to a HardFault. |
29:2 | RSVD | RO | RESERVED. |
1 | VECTTBL | RW | Vector table read fault has occurred. |
0 | RSVD | RO | RESERVED. |
Instance 0 Address: | 0xE000ED34 |
MemManage Fault Address Register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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ADDRESS
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | ADDRESS | RW | Address of the memory location that caused an MMU fault. |
Instance 0 Address: | 0xE000ED38 |
Bus Fault Address Register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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ADDRESS
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | ADDRESS | RW | Address of the memory location that caused an Bus fault. |
Instance 0 Address: | 0xE000ED88 |
Coprocessor Access Control Register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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RSVD
0x0 |
CP11
0x0 |
CP10
0x0 |
RSVD
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:24 | RSVD | RO | RESERVED. |
23:22 | CP11 | RW | Access priveleges for the Floating point unit. Must always match CP10. |
21:20 | CP10 | RW | Access priveleges for the Floating point unit. Must always match CP11. |
19:0 | RSVD | RO | RESERVED. |
Instance 0 Address: | 0xE000EDFC |
Debug Exception and Monitor Control Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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RSVD
0x0 |
TRCENA
0x0 |
RSVD
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:25 | RSVD | RO | RESERVED. |
24 | TRCENA | RW | Global enable for all DWT and ITM features. |
23:0 | RSVD | RO | RESERVED. |
Instance 0 Address: | 0xE000EF00 |
Software Triggered Interrupt Register
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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INTID
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | INTID | RW | Vector number of the interrupt that should be triggered. |
Instance 0 Address: | 0xE000EF34 |
Floating-Point Context Control Register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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ASPEN
0x0 |
LSPEN
0x0 |
RSVD
0x0 |
MONRDY
0x0 |
RSVD
0x0 |
BFRDY
0x0 |
MMRDY
0x0 |
HFRDY
0x0 |
THREAD
0x0 |
RSVD
0x0 |
USER
0x0 |
LSPACT
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31 | ASPEN | RW | Set to enable automatic saving of FP registers on exception entry. |
30 | LSPEN | RW | Set to enable lazy context saving of FP registers on exception entry. |
29:9 | RSVD | RO | RESERVED. |
8 | MONRDY | RW | Able to set DebugMonitor exception to pending on last FP stack allocation. |
7 | RSVD | RW | RESERVED. |
6 | BFRDY | RW | Able to set BusFault exception to pending on last FP stack allocation. |
5 | MMRDY | RW | Able to set MemManage exception to pending on last FP stack allocation. |
4 | HFRDY | RW | Able to set HardFault exception to pending on last FP stack allocation. |
3 | THREAD | RW | Running from Thread mode on last FP stack allocation. |
2 | RSVD | RO | RESERVED. |
1 | USER | RW | Running from unprivileged mode on last FP stack allocation. |
0 | LSPACT | RW | Lazy state preservation is active. |
Instance 0 Address: | 0xE000EF38 |
Floating-Point Context Address Register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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ADDRESS
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | ADDRESS | RW | Address of the unpopulated floating-point register space allocated on the exception stack frame. |
Instance 0 Address: | 0xE000EF3C |
Floating-Point Default Status Control Register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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RSVD
0x0 |
AHP
0x0 |
DN
0x0 |
FZ
0x0 |
RMODE
0x0 |
RSVD
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:27 | RSVD | RO | RESERVED. |
26 | AHP | RW | Default value for FPSCR.AHP. |
25 | DN | RW | Default value for FPSCR.DN. |
24 | FZ | RW | Default value for FPSCR.FZ. |
23:22 | RMODE | RW | Default value for FPSCR.RMode. |
21:0 | RSVD | RO | RESERVED. |