Apollo Register Documentation  v${version}
IOSLAVE - I2C/SPI Slave

IOSLAVE Register Index

  0x00000100:   FIFOPTR - Current FIFO Pointer
  0x00000104:   FIFOCFG - FIFO Configuration
  0x00000108:   FIFOTHR - FIFO Threshold Configuration
  0x0000010C:   FUPD - FIFO Update Status
  0x00000110:   FIFOCTR - Overall FIFO Counter
  0x00000114:   FIFOINC - Overall FIFO Counter Increment
  0x00000118:   CFG - I/O Slave Configuration
  0x0000011C:   PRENC - I/O Slave Interrupt Priority Encode
  0x00000120:   IOINTCTL - I/O Interrupt Control
  0x00000124:   GENADD - General Address Data
  0x00000200:   INTEN - IO Slave Interrupts: Enable
  0x00000204:   INTSTAT - IO Slave Interrupts: Status
  0x00000208:   INTCLR - IO Slave Interrupts: Clear
  0x0000020C:   INTSET - IO Slave Interrupts: Set
  0x00000210:   REGACCINTEN - Register Access Interrupts: Enable
  0x00000214:   REGACCINTSTAT - Register Access Interrupts: Status
  0x00000218:   REGACCINTCLR - Register Access Interrupts: Clear
  0x0000021C:   REGACCINTSET - Register Access Interrupts: Set

FIFOPTR - Current FIFO Pointer

Address:

  Instance 0 Address:   0x50000100

Description:

Current FIFO Pointer

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
FIFOSIZ
0x0
FIFOPTR
0x0

Bits Name RW Description
31:16 RSVD RO RESERVED

15:8 FIFOSIZ RW The number of bytes currently in the hardware FIFO.

7:0 FIFOPTR RW Current FIFO pointer.


FIFOCFG - FIFO Configuration

Address:

  Instance 0 Address:   0x50000104

Description:

FIFO Configuration

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ROBASE
0x20
RSVD
0x0
RSVD
0x0
FIFOMAX
0x0
RSVD
0x0
FIFOBASE
0x0

Bits Name RW Description
31:30 RSVD RO RESERVED

29:24 ROBASE RW Defines the read-only area. The IO Slave read-only area is situated in LRAM at (ROBASE*8) to (FIFOBASE*8-1)

23:16 RSVD RO RESERVED

15:14 RSVD RO RESERVED

13:8 FIFOMAX RW These bits hold the maximum FIFO address in 8 byte segments. It is also the beginning of the RAM area of the LRAM. Note that no RAM area is configured if FIFOMAX is set to 0x1F.

7:5 RSVD RO RESERVED

4:0 FIFOBASE RW These bits hold the base address of the I/O FIFO in 8 byte segments. The IO Slave FIFO is situated in LRAM at (FIFOBASE*8) to (FIFOMAX*8-1).


FIFOTHR - FIFO Threshold Configuration

Address:

  Instance 0 Address:   0x50000108

Description:

FIFO Threshold Configuration

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
FIFOTHR
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED

7:0 FIFOTHR RW FIFO size interrupt threshold.


FUPD - FIFO Update Status

Address:

  Instance 0 Address:   0x5000010C

Description:

FIFO Update Status

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
IOREAD
0x0
FIFOUPD
0x0

Bits Name RW Description
31:2 RSVD RO RESERVED

1 IOREAD RO This bit field indicates an IO read is active.

0 FIFOUPD RW This bit indicates that a FIFO update is underway.


FIFOCTR - Overall FIFO Counter

Address:

  Instance 0 Address:   0x50000110

Description:

Overall FIFO Counter

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
FIFOCTR
0x0

Bits Name RW Description
31:10 RSVD RO RESERVED

9:0 FIFOCTR RW Virtual FIFO byte count


FIFOINC - Overall FIFO Counter Increment

Address:

  Instance 0 Address:   0x50000114

Description:

Overall FIFO Counter Increment

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
FIFOINC
0x0

Bits Name RW Description
31:10 RSVD RO RESERVED

9:0 FIFOINC WO Increment the Overall FIFO Counter by this value on a write


CFG - I/O Slave Configuration

Address:

  Instance 0 Address:   0x50000118

Description:

I/O Slave Configuration

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IFCEN
0x0
RSVD
0x0
I2CADDR
0x0
RSVD
0x0
STARTRD
0x0
RSVD
0x0
LSB
0x0
SPOL
0x0
IFCSEL
0x0

Bits Name RW Description
31 IFCEN RW IOSLAVE interface enable.

DIS = 0x0 - Disable the IOSLAVE
EN = 0x1 - Enable the IOSLAVE
30:20 RSVD RO RESERVED

19:8 I2CADDR RW 7-bit or 10-bit I2C device address.

7:5 RSVD RO RESERVED

4 STARTRD RW This bit holds the cycle to initiate an I/O RAM read.

LATE = 0x0 - Initiate I/O RAM read late in each transferred byte.
EARLY = 0x1 - Initiate I/O RAM read early in each transferred byte.
3 RSVD RO RESERVED

2 LSB RW This bit selects the transfer bit ordering.

MSB_FIRST = 0x0 - Data is assumed to be sent and received with MSB first.
LSB_FIRST = 0x1 - Data is assumed to be sent and received with LSB first.
1 SPOL RW This bit selects SPI polarity.

SPI_MODES_0_3 = 0x0 - Polarity 0, handles SPI modes 0 and 3.
SPI_MODES_1_2 = 0x1 - Polarity 1, handles SPI modes 1 and 2.
0 IFCSEL RW This bit selects the I/O interface.

I2C = 0x0 - Selects I2C interface for the IO Slave.
SPI = 0x1 - Selects SPI interface for the IO Slave.

PRENC - I/O Slave Interrupt Priority Encode

Address:

  Instance 0 Address:   0x5000011C

Description:

I/O Slave Interrupt Priority Encode

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
PRENC
0x0

Bits Name RW Description
31:5 RSVD RO RESERVED

4:0 PRENC RO These bits hold the priority encode of the REGACC interrupts.


IOINTCTL - I/O Interrupt Control

Address:

  Instance 0 Address:   0x50000120

Description:

I/O Interrupt Control

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOINTSET
0x0
RSVD
0x0
IOINTCLR
0x0
IOINT
0x0
IOINTEN
0x0

Bits Name RW Description
31:24 IOINTSET WO These bits set the IOINT interrupts when written with a 1.

23:17 RSVD RO RESERVED

16 IOINTCLR WO This bit clears all of the IOINT interrupts when written with a 1.

15:8 IOINT RO These bits read the IOINT interrupts.

7:0 IOINTEN RO These read-only bits indicate whether the IOINT interrupts are enabled.


GENADD - General Address Data

Address:

  Instance 0 Address:   0x50000124

Description:

General Address Data

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
GADATA
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED

7:0 GADATA RO The data supplied on the last General Address reference.


INTEN - IO Slave Interrupts: Enable

Address:

  Instance 0 Address:   0x50000200

Description:

Set bits in this register to allow this module to generate the corresponding interrupt.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
XCMPWR
0x0
XCMPWF
0x0
XCMPRR
0x0
XCMPRF
0x0
IOINTW
0x0
GENAD
0x0
FRDERR
0x0
FUNDFL
0x0
FOVFL
0x0
FSIZE
0x0

Bits Name RW Description
31:10 RSVD RO RESERVED

9 XCMPWR RW Transfer complete interrupt, write to register space.

8 XCMPWF RW Transfer complete interrupt, write to FIFO space.

7 XCMPRR RW Transfer complete interrupt, read from register space.

6 XCMPRF RW Transfer complete interrupt, read from FIFO space.

5 IOINTW RW IO Write interrupt.

4 GENAD RW I2C General Address interrupt.

3 FRDERR RW FIFO Read Error interrupt.

2 FUNDFL RW FIFO Underflow interrupt.

1 FOVFL RW FIFO Overflow interrupt.

0 FSIZE RW FIFO Size interrupt.


INTSTAT - IO Slave Interrupts: Status

Address:

  Instance 0 Address:   0x50000204

Description:

Read bits from this register to discover the cause of a recent interrupt.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
XCMPWR
0x0
XCMPWF
0x0
XCMPRR
0x0
XCMPRF
0x0
IOINTW
0x0
GENAD
0x0
FRDERR
0x0
FUNDFL
0x0
FOVFL
0x0
FSIZE
0x0

Bits Name RW Description
31:10 RSVD RO RESERVED

9 XCMPWR RW Transfer complete interrupt, write to register space.

8 XCMPWF RW Transfer complete interrupt, write to FIFO space.

7 XCMPRR RW Transfer complete interrupt, read from register space.

6 XCMPRF RW Transfer complete interrupt, read from FIFO space.

5 IOINTW RW IO Write interrupt.

4 GENAD RW I2C General Address interrupt.

3 FRDERR RW FIFO Read Error interrupt.

2 FUNDFL RW FIFO Underflow interrupt.

1 FOVFL RW FIFO Overflow interrupt.

0 FSIZE RW FIFO Size interrupt.


INTCLR - IO Slave Interrupts: Clear

Address:

  Instance 0 Address:   0x50000208

Description:

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
XCMPWR
0x0
XCMPWF
0x0
XCMPRR
0x0
XCMPRF
0x0
IOINTW
0x0
GENAD
0x0
FRDERR
0x0
FUNDFL
0x0
FOVFL
0x0
FSIZE
0x0

Bits Name RW Description
31:10 RSVD RO RESERVED

9 XCMPWR RW Transfer complete interrupt, write to register space.

8 XCMPWF RW Transfer complete interrupt, write to FIFO space.

7 XCMPRR RW Transfer complete interrupt, read from register space.

6 XCMPRF RW Transfer complete interrupt, read from FIFO space.

5 IOINTW RW IO Write interrupt.

4 GENAD RW I2C General Address interrupt.

3 FRDERR RW FIFO Read Error interrupt.

2 FUNDFL RW FIFO Underflow interrupt.

1 FOVFL RW FIFO Overflow interrupt.

0 FSIZE RW FIFO Size interrupt.


INTSET - IO Slave Interrupts: Set

Address:

  Instance 0 Address:   0x5000020C

Description:

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
XCMPWR
0x0
XCMPWF
0x0
XCMPRR
0x0
XCMPRF
0x0
IOINTW
0x0
GENAD
0x0
FRDERR
0x0
FUNDFL
0x0
FOVFL
0x0
FSIZE
0x0

Bits Name RW Description
31:10 RSVD RO RESERVED

9 XCMPWR RW Transfer complete interrupt, write to register space.

8 XCMPWF RW Transfer complete interrupt, write to FIFO space.

7 XCMPRR RW Transfer complete interrupt, read from register space.

6 XCMPRF RW Transfer complete interrupt, read from FIFO space.

5 IOINTW RW IO Write interrupt.

4 GENAD RW I2C General Address interrupt.

3 FRDERR RW FIFO Read Error interrupt.

2 FUNDFL RW FIFO Underflow interrupt.

1 FOVFL RW FIFO Overflow interrupt.

0 FSIZE RW FIFO Size interrupt.


REGACCINTEN - Register Access Interrupts: Enable

Address:

  Instance 0 Address:   0x50000210

Description:

Set bits in this register to allow this module to generate the corresponding interrupt.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGACC
0x0

Bits Name RW Description
31:0 REGACC RW Register access interrupts.


REGACCINTSTAT - Register Access Interrupts: Status

Address:

  Instance 0 Address:   0x50000214

Description:

Read bits from this register to discover the cause of a recent interrupt.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGACC
0x0

Bits Name RW Description
31:0 REGACC RW Register access interrupts.


REGACCINTCLR - Register Access Interrupts: Clear

Address:

  Instance 0 Address:   0x50000218

Description:

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGACC
0x0

Bits Name RW Description
31:0 REGACC RW Register access interrupts.


REGACCINTSET - Register Access Interrupts: Set

Address:

  Instance 0 Address:   0x5000021C

Description:

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REGACC
0x0

Bits Name RW Description
31:0 REGACC RW Register access interrupts.