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Apollo Register Documentation v${version}
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0xE0040000: | SSPSR - Supported Parallel Port Sizes. |
0xE0040004: | CSPSR - Current Parallel Port Size. |
0xE0040010: | ACPR - Asynchronous Clock Prescaler. |
0xE00400F0: | SPPR - Selected Pin Protocol. |
0xE0040304: | FFCR - Formatter and Flush Control Register. |
0xE0040F00: | ITCTRL - Specifies normal or integration mode for the TPIU. |
0xE0040FC8: | TYPE - TPIU Type. |
Instance 0 Address: | 0xE0040000 |
Supported Parallel Port Sizes.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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SWIDTH0
0x1 |
Bits | Name | RW | Description |
---|---|---|---|
0 | SWIDTH0 | RO | Parallel Port Width 1 supported |
Instance 0 Address: | 0xE0040004 |
Current Parallel Port Size.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
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CWIDTH
0x1 |
Bits | Name | RW | Description |
---|---|---|---|
31:0 | CWIDTH | RW | One-hot representation of the current port width. 1BIT = 0x1 - Set width to 1. |
Instance 0 Address: | 0xE0040010 |
Asynchronous Clock Prescaler.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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RSVD
0x0 |
SWOSCALER
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:16 | RSVD | RO | RESERVED |
15:0 | SWOSCALER | RW | Prescaler value for the baudrate of SWO. 115200 = 0x33 - Set divisor correctly for 115200 baud. |
Instance 0 Address: | 0xE00400F0 |
Selected Pin Protocol.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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RSVD
0x0 |
TXMODE
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:2 | RSVD | RO | RESERVED |
1:0 | TXMODE | RW | Selects the protocol used for trace output. PARALLEL = 0x0 - Parallel trace port. MANCHESTER = 0x1 - Manchester encoded. NRZ = 0x2 - Non-return-to-zero encoding. UART = 0x2 - UART encoding. |
Instance 0 Address: | 0xE0040304 |
Formatter and Flush Control Register.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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RSVD
0x1 |
ENFCONT
0x0 |
RSVD
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
31:2 | RSVD | RO | RESERVED |
1 | ENFCONT | RW | Enable continuous formatting. |
0 | RSVD | RO | RESERVED |
Instance 0 Address: | 0xE0040F00 |
Specifies normal or integration mode for the TPIU.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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RSVD
0x0 |
MODE
0x0 |
Bits | Name | RW | Description |
---|---|---|---|
30:1 | RSVD | RO | RESERVED |
1:0 | MODE | RW | Specifies the current mode for the TPIU. NORMAL = 0x0 - Normal mode. TEST = 0x1 - Integration test mode. DATA_TEST = 0x2 - Integration data test mode. |
Instance 0 Address: | 0xE0040FC8 |
TPIU Type.
// // Register access is all performed through the standard CMSIS structure-based // interface. This includes module-level structure definitions with members and // bitfields corresponding to the physical registers and bitfields within each // module. In addition, Ambiq has provided instance-level macros for modules // that have more than one physical instance and a generic AM_REGVAL() macro // for directly accessing memory by address. // // The following examples show how to use these structures and macros: // Setting the ADC configuration register... AM_REGVAL(0x50010000) = 0x1234; // by address. ADC->CFG = 0x1234; // by structure pointer. ADCn(0)->CFG = 0x1234; // by structure pointer (with instance number). // Changing the ADC clock... ADCn(0)->CFG_b.CLKSEL = 0x2; // by raw value. ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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RSVD
0x0 |
NRZVALID
0x1 |
MANCVALID
0x1 |
PTINVALID
0x1 |
FIFOSZ
0x2 |
Bits | Name | RW | Description |
---|---|---|---|
31:12 | RSVD | RO | RESERVED |
11 | NRZVALID | RO | 1 Indicates UART/NRZ support. |
10 | MANCVALID | RO | 1 Indicates Manchester support. |
9 | PTINVALID | RO | 0 Indicates Parallel Trace support. |
8:6 | FIFOSZ | RO | FIFO Size reported as a power of two. For instance, 0x3 indicates a FIFO size of 8 bytes. |