Apollo Register Documentation  v${version}
MCUCTRL - MCU Miscellaneous Control Logic

MCUCTRL Register Index

  0x00000000:   CHIPPN - Chip Information Register
  0x00000004:   CHIPID0 - Unique Chip ID 0
  0x00000008:   CHIPID1 - Unique Chip ID 1
  0x0000000C:   CHIPREV - Chip Revision
  0x00000010:   VENDORID - Unique Vendor ID
  0x00000014:   SKU - Unique Chip SKU
  0x00000018:   FEATUREENABLE - Feature Enable on Burst and BLE
  0x00000020:   DEBUGGER - Debugger Control
  0x00000100:   BODCTRL - BOD control Register
  0x00000104:   ADCPWRDLY - ADC Power Up Delay Control
  0x0000010C:   ADCCAL - ADC Calibration Control
  0x00000110:   ADCBATTLOAD - ADC Battery Load Enable
  0x00000118:   ADCTRIM - ADC Trims
  0x0000011C:   ADCREFCOMP - ADC Reference Keeper and Comparator Control
  0x00000120:   XTALCTRL - XTAL Oscillator Control
  0x00000124:   XTALGENCTRL - XTAL Oscillator General Control
  0x00000198:   MISCCTRL - Miscellaneous control register.
  0x000001A0:   BOOTLOADER - Bootloader and secure boot functions
  0x000001A4:   SHADOWVALID - Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space.
  0x000001B0:   SCRATCH0 - Scratch register that is not reset by any reset
  0x000001B4:   SCRATCH1 - Scratch register that is not reset by any reset
  0x000001C0:   ICODEFAULTADDR - ICODE bus address which was present when a bus fault occurred.
  0x000001C4:   DCODEFAULTADDR - DCODE bus address which was present when a bus fault occurred.
  0x000001C8:   SYSFAULTADDR - System bus address which was present when a bus fault occurred.
  0x000001CC:   FAULTSTATUS - Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.
  0x000001D0:   FAULTCAPTUREEN - Enable the fault capture registers
  0x00000200:   DBGR1 - Read-only debug register 1
  0x00000204:   DBGR2 - Read-only debug register 2
  0x00000220:   PMUENABLE - Control bit to enable/disable the PMU
  0x00000250:   TPIUCTRL - TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.
  0x00000264:   OTAPOINTER - OTA (Over the Air) Update Pointer/Status. Reset only by POA
  0x00000280:   APBDMACTRL - DMA Control Register. Determines misc settings for DMA operation
  0x00000284:   SRAMMODE - SRAM Controller mode bits
  0x00000348:   KEXTCLKSEL - Key Register to enable the use of external clock selects via the EXTCLKSEL reg
  0x00000350:   SIMOBUCK1 - SIMO Buck Control Reg 1
  0x00000354:   SIMOBUCK2 - SIMO Buck Control Reg 2
  0x00000358:   SIMOBUCK3 - SIMO Buck Control Reg 3
  0x0000035C:   SIMOBUCK4 - SIMO Buck Control Reg 4
  0x00000368:   BLEBUCK2 - BLEBUCK2 Control Reg
  0x000003A0:   FLASHWPROT0 - Flash Write Protection Bits
  0x000003A4:   FLASHWPROT1 - Flash Write Protection Bits
  0x000003B0:   FLASHRPROT0 - Flash Read Protection Bits
  0x000003B4:   FLASHRPROT1 - Flash Read Protection Bits
  0x000003C0:   DMASRAMWRITEPROTECT0 - SRAM write-protection bits.
  0x000003C4:   DMASRAMWRITEPROTECT1 - SRAM write-protection bits.
  0x000003D0:   DMASRAMREADPROTECT0 - SRAM read-protection bits.
  0x000003D4:   DMASRAMREADPROTECT1 - SRAM read-protection bits.

CHIPPN - Chip Information Register

Address:

  Instance 0 Address:   0x40020000

Description:

Chip Information Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PARTNUM
0x4000000

Bits Name RW Description
31:0 PARTNUM RO BCD part number.

APOLLO3 = 0x6000000 - Apollo3 Blue part number is 0x06xxxxxx.
APOLLO2 = 0x3000000 - Apollo2 part number is 0x03xxxxxx.
APOLLO = 0x1000000 - Apollo part number is 0x01xxxxxx.
PN_M = 0xFF000000 - Mask for the part number field.
PN_S = 0x18 - Bit position for the part number field.
FLASHSIZE_M = 0xF00000 - Mask for the FLASH_SIZE field. Values: 0: 16KB 1: 32KB 2: 64KB 3: 128KB 4: 256KB 5: 512KB 6: 1MB 7: 2MB
FLASHSIZE_S = 0x14 - Bit position for the FLASH_SIZE field.
SRAMSIZE_M = 0xF0000 - Mask for the SRAM_SIZE field. Values: 0: 16KB 1: 32KB 2: 64KB 3: 128KB 4: 256KB 5: 512KB 6: 1MB 7: 384KB 8: 768KB
SRAMSIZE_S = 0x10 - Bit position for the SRAM_SIZE field.
REV_M = 0xFF00 - Mask for the revision field. Bits [15:12] are major rev, [11:8] are minor rev. Values: 0: Major Rev A, Minor Rev 0 1: Major Rev B, Minor Rev 1
REV_S = 0x8 - Bit position for the revision field.
PKG_M = 0xC0 - Mask for the package field. Values: 0: SIP 1: QFN 2: BGA 3: CSP
PKG_S = 0x6 - Bit position for the package field.
PINS_M = 0x38 - Mask for the pins field. Values: 0: 25 pins 1: 49 pins 2: 64 pins 3: 81 pins 4: 104 pins
PINS_S = 0x3 - Bit position for the pins field.
TEMP_M = 0x6 - Mask for the temperature field. Values: 0: Commercial 1: Military 2: Automotive 3: Industrial
TEMP_S = 0x1 - Bit position for the temperature field.
QUAL_M = 0x1 - Mask for the qualified field. Values: 0: Prototype/Sample 1: Qualified
QUAL_S = 0x0 - Bit position for the qualified field.

CHIPID0 - Unique Chip ID 0

Address:

  Instance 0 Address:   0x40020004

Description:

Unique Chip ID 0

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHIPID0
0x0

Bits Name RW Description
31:0 CHIPID0 RO Unique chip ID 0.

APOLLO3 = 0x0 - Apollo3 Blue CHIPID0.

CHIPID1 - Unique Chip ID 1

Address:

  Instance 0 Address:   0x40020008

Description:

Unique Chip ID 1

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHIPID1
0x0

Bits Name RW Description
31:0 CHIPID1 RO Unique chip ID 1.

APOLLO3 = 0x0 - Apollo3 Blue CHIPID1.

CHIPREV - Chip Revision

Address:

  Instance 0 Address:   0x4002000C

Description:

Chip Revision

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
SIPART
0x0
REVMAJ
0x0
REVMIN
0x1

Bits Name RW Description
31:20 RSVD RO RESERVED

19:8 SIPART RO Silicon Part ID

7:4 REVMAJ RO Major Revision ID.

B = 0x2 - Apollo3 Blue revision B
A = 0x1 - Apollo3 Blue revision A
3:0 REVMIN RO Minor Revision ID.

REV1 = 0x2 - Apollo3 Blue minor rev 1.
REV0 = 0x1 - Apollo3 Blue minor rev 0. Minor revision value, succeeding minor revisions will increment from this value.

VENDORID - Unique Vendor ID

Address:

  Instance 0 Address:   0x40020010

Description:

Unique Vendor ID

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VENDORID
0x0

Bits Name RW Description
31:0 VENDORID RO Unique Vendor ID

AMBIQ = 0x414D4251 - Ambiq Vendor ID 'AMBQ'

SKU - Unique Chip SKU

Address:

  Instance 0 Address:   0x40020014

Description:

Unique Chip SKU

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
SECBOOT
0x0
ALLOWBLE
0x0
ALLOWBURST
0x0

Bits Name RW Description
31:3 RSVD RO RESERVED

2 SECBOOT RO Secure boot feature allowed

1 ALLOWBLE RO Allow BLE feature

0 ALLOWBURST RO Allow Burst feature


FEATUREENABLE - Feature Enable on Burst and BLE

Address:

  Instance 0 Address:   0x40020018

Description:

Feature Enable on Burst and BLE

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
BURSTAVAIL
0x0
BURSTACK
0x0
BURSTREQ
0x0
RSVD
0x0
BLEAVAIL
0x0
BLEACK
0x0
BLEREQ
0x1

Bits Name RW Description
31:7 RSVD RO RESERVED

6 BURSTAVAIL RO Availability of Burst functionality

AVAIL = 0x1 - Burst functionality available
NOTAVAIL = 0x0 - Burst functionality not available
5 BURSTACK RO ACK for BURSTREQ

4 BURSTREQ RW Controls the Burst functionality

EN = 0x1 - Enable the Burst functionality
DIS = 0x0 - Disable the Burst functionality
3 RSVD RO RESERVED

2 BLEAVAIL RO AVAILABILITY of the BLE functionality

AVAIL = 0x1 - BLE functionality available
NOTAVAIL = 0x0 - BLE functionality not available
1 BLEACK RO ACK for BLEREQ

0 BLEREQ RW Controls the BLE functionality

EN = 0x1 - Enable the BLE functionality
DIS = 0x0 - Disable the BLE functionality

DEBUGGER - Debugger Control

Address:

  Instance 0 Address:   0x40020020

Description:

Debugger Control

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
LOCKOUT
0x0

Bits Name RW Description
31:1 RSVD RO RESERVED

0 LOCKOUT RW Lockout of debugger (SWD).


BODCTRL - BOD control Register

Address:

  Instance 0 Address:   0x40020100

Description:

BOD control Register

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
BODHVREFSEL
0x0
BODLVREFSEL
0x0
BODFPWD
0x0
BODCPWD
0x0
BODHPWD
0x0
BODLPWD
0x0

Bits Name RW Description
31:6 RSVD RO RESERVED

5 BODHVREFSEL RW BODH External Reference Select. Note: the SWE mux select in PWRSEQ2SWE must be set for this to take effect.

4 BODLVREFSEL RW BODL External Reference Select. Note: the SWE mux select in PWRSEQ2SWE must be set for this to take effect.

3 BODFPWD RW BODF Power Down.

2 BODCPWD RW BODC Power Down.

1 BODHPWD RW BODH Power Down.

0 BODLPWD RW BODL Power Down.


ADCPWRDLY - ADC Power Up Delay Control

Address:

  Instance 0 Address:   0x40020104

Description:

ADC Power Up Delay Control

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADCPWR1
0x0
ADCPWR0
0x0

Bits Name RW Description
31:16 RSVD RO RESERVED

15:8 ADCPWR1 RW ADC Reference Keeper enable delay in 16 ADC CLK increments for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL = 0x2.

7:0 ADCPWR0 RW ADC Reference Buffer Power Enable delay in 64 ADC CLK increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments for ADC_CLKSEL = 0x2.


ADCCAL - ADC Calibration Control

Address:

  Instance 0 Address:   0x4002010C

Description:

ADC Calibration Control

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADCCALIBRATED
0x0
CALONPWRUP
0x1

Bits Name RW Description
31:2 RSVD RO RESERVED

1 ADCCALIBRATED RO Status for ADC Calibration

FALSE = 0x0 - ADC is not calibrated
TRUE = 0x1 - ADC is calibrated
0 CALONPWRUP RW Run ADC Calibration on initial power up sequence

DIS = 0x0 - Disable automatic calibration on initial power up
EN = 0x1 - Enable automatic calibration on initial power up

ADCBATTLOAD - ADC Battery Load Enable

Address:

  Instance 0 Address:   0x40020110

Description:

ADC Battery Load Enable

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
BATTLOAD
0x0

Bits Name RW Description
31:1 RSVD RO RESERVED

0 BATTLOAD RW Enable the ADC battery load resistor

DIS = 0x0 - Battery load is disconnected
EN = 0x1 - Battery load is enabled

ADCTRIM - ADC Trims

Address:

  Instance 0 Address:   0x40020118

Description:

ADC Trims

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADCRFBUFIBTRIM
0x0
ADCREFBUFTRIM
0x8
RSVD
0x0
ADCREFKEEPIBTRIM
0x0

Bits Name RW Description
31:13 RSVD RO RESERVED

12:11 ADCRFBUFIBTRIM RW ADC reference buffer input bias trim

10:6 ADCREFBUFTRIM RW ADC Reference buffer trim

5:2 RSVD RO RESERVED

1:0 ADCREFKEEPIBTRIM RW ADC Reference Ibias trim


ADCREFCOMP - ADC Reference Keeper and Comparator Control

Address:

  Instance 0 Address:   0x4002011C

Description:

ADC Reference Keeper and Comparator Control

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADCRFCMPEN
0x0
RSVD
0x0
ADCREFKEEPTRIM
0x0
RSVD
0x0
ADC_REFCOMP_OUT
0x0

Bits Name RW Description
31:17 RSVD RO RESERVED

16 ADCRFCMPEN RW ADC Reference comparator power down

15:13 RSVD RO RESERVED

12:8 ADCREFKEEPTRIM RW ADC Reference Keeper Trim

7:1 RSVD RO RESERVED

0 ADC_REFCOMP_OUT RO Output of the ADC reference comparator


XTALCTRL - XTAL Oscillator Control

Address:

  Instance 0 Address:   0x40020120

Description:

XTAL Oscillator Control

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
XTALICOMPTRIM
0x3
XTALIBUFTRIM
0x1
PWDBODXTAL
0x0
PDNBCMPRXTAL
0x1
PDNBCOREXTAL
0x1
BYPCMPRXTAL
0x0
FDBKDSBLXTAL
0x0
XTALSWE
0x0

Bits Name RW Description
31:10 RSVD RO RESERVED

9:8 XTALICOMPTRIM RW XTAL ICOMP trim

7:6 XTALIBUFTRIM RW XTAL IBUFF trim

5 PWDBODXTAL RW XTAL Power down on brown out.

PWRUPBOD = 0x0 - Power up XTAL on BOD.
PWRDNBOD = 0x1 - Power down XTAL on BOD.
4 PDNBCMPRXTAL RW XTAL Oscillator Power Down Comparator.

PWRUPCOMP = 0x1 - Power up XTAL oscillator comparator.
PWRDNCOMP = 0x0 - Power down XTAL oscillator comparator.
3 PDNBCOREXTAL RW XTAL Oscillator Power Down Core.

PWRUPCORE = 0x1 - Power up XTAL oscillator core.
PWRDNCORE = 0x0 - Power down XTAL oscillator core.
2 BYPCMPRXTAL RW XTAL Oscillator Bypass Comparator.

USECOMP = 0x0 - Use the XTAL oscillator comparator.
BYPCOMP = 0x1 - Bypass the XTAL oscillator comparator.
1 FDBKDSBLXTAL RW XTAL Oscillator Disable Feedback.

EN = 0x0 - Enable XTAL oscillator comparator.
DIS = 0x1 - Disable XTAL oscillator comparator.
0 XTALSWE RW XTAL Software Override Enable.

OVERRIDE_DIS = 0x0 - XTAL Software Override Disable.
OVERRIDE_EN = 0x1 - XTAL Software Override Enable.

XTALGENCTRL - XTAL Oscillator General Control

Address:

  Instance 0 Address:   0x40020124

Description:

XTAL Oscillator General Control

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
XTALKSBIASTRIM
0x1
XTALBIASTRIM
0x0
ACWARMUP
0x0

Bits Name RW Description
31:14 RSVD RO RESERVED

13:8 XTALKSBIASTRIM RW XTAL IBIAS Kick start trim. This trim value is used during the startup process to enable a faster lock.

7:2 XTALBIASTRIM RW XTAL BIAS trim

1:0 ACWARMUP RW Auto-calibration delay control

SEC1 = 0x0 - Warm-up period of 1-2 seconds
SEC2 = 0x1 - Warm-up period of 2-4 seconds
SEC4 = 0x2 - Warm-up period of 4-8 seconds
SEC8 = 0x3 - Warm-up period of 8-16 seconds

MISCCTRL - Miscellaneous control register.

Address:

  Instance 0 Address:   0x40020198

Description:

Miscellaneous control register.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
BLE_RESETN
0x0
RESERVED_RW_0
0x0

Bits Name RW Description
31:6 RSVD RO RESERVED

5 BLE_RESETN RW BLE reset signal.

4:0 RESERVED_RW_0 RW Reserved bits, always leave unchanged. The MISCCTRL register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior.


BOOTLOADER - Bootloader and secure boot functions

Address:

  Instance 0 Address:   0x400201A0

Description:

Bootloader and secure boot functions

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBOOTONRST
0x0
SECBOOT
0x0
SECBOOTFEATURE
0x0
RSVD
0x0
PROTLOCK
0x1
SBLOCK
0x1
BOOTLOADERLOW
0x1

Bits Name RW Description
31:30 SECBOOTONRST RO Indicates whether the secure boot on warm reset is enabled

DISABLED = 0x0 - Secure boot disabled
ENABLED = 0x1 - Secure boot enabled
ERROR = 0x2 - Error in secure boot configuration
29:28 SECBOOT RO Indicates whether the secure boot on cold reset is enabled

DISABLED = 0x0 - Secure boot disabled
ENABLED = 0x1 - Secure boot enabled
ERROR = 0x2 - Error in secure boot configuration
27:26 SECBOOTFEATURE RO Indicates whether the secure boot feature is enabled.

DISABLED = 0x0 - Secure boot disabled
ENABLED = 0x1 - Secure boot enabled
ERROR = 0x2 - Error in secure boot configuration
25:3 RSVD RO RESERVED

2 PROTLOCK RW Flash protection lock. Always resets to 1, write 1 to clear. Enables writes to flash protection register set.

LOCK = 0x1 - Enable the secure boot lock
1 SBLOCK RW Secure boot lock. Always resets to 1, write 1 to clear. Enables system visibility to bootloader until set.

LOCK = 0x1 - Enable the secure boot lock
0 BOOTLOADERLOW RW Determines whether the bootloader code is visible at address 0x00000000 or not. Resets to 1, write 1 to clear.

ADDR0 = 0x1 - Bootloader code at 0x00000000.

SHADOWVALID - Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space.

Address:

  Instance 0 Address:   0x400201A4

Description:

Register to indicate whether the shadow registers have been successfully loaded from the Flash Information Space.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
INFO0_VALID
0x1
BLDSLEEP
0x1
VALID
0x1

Bits Name RW Description
31:3 RSVD RO RESERVED

2 INFO0_VALID RO Indicates whether INFO0 contains valid data

VALID = 0x1 - Flash INFO0 (customer) space contains valid data.
1 BLDSLEEP RO Indicates whether the bootloader should sleep or deep sleep if no image loaded.

DEEPSLEEP = 0x1 - Bootloader will go to deep sleep if no flash image loaded
0 VALID RO Indicates whether the shadow registers contain valid data from the Flash Information Space.

VALID = 0x1 - Flash information space contains valid data.

SCRATCH0 - Scratch register that is not reset by any reset

Address:

  Instance 0 Address:   0x400201B0

Description:

Scratch register that is not reset by any reset

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRATCH0
0x0

Bits Name RW Description
31:0 SCRATCH0 RW Scratch register 0.


SCRATCH1 - Scratch register that is not reset by any reset

Address:

  Instance 0 Address:   0x400201B4

Description:

Scratch register that is not reset by any reset

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRATCH1
0x0

Bits Name RW Description
31:0 SCRATCH1 RW Scratch register 1.


ICODEFAULTADDR - ICODE bus address which was present when a bus fault occurred.

Address:

  Instance 0 Address:   0x400201C0

Description:

ICODE bus address which was present when a bus fault occurred.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICODEFAULTADDR
0x0

Bits Name RW Description
31:0 ICODEFAULTADDR RO The ICODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.


DCODEFAULTADDR - DCODE bus address which was present when a bus fault occurred.

Address:

  Instance 0 Address:   0x400201C4

Description:

DCODE bus address which was present when a bus fault occurred.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCODEFAULTADDR
0x0

Bits Name RW Description
31:0 DCODEFAULTADDR RO The DCODE bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.


SYSFAULTADDR - System bus address which was present when a bus fault occurred.

Address:

  Instance 0 Address:   0x400201C8

Description:

System bus address which was present when a bus fault occurred.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSFAULTADDR
0x0

Bits Name RW Description
31:0 SYSFAULTADDR RO SYS bus address observed when a Bus Fault occurred. Once an address is captured in this field, it is held until the corresponding Fault Observed bit is cleared in the FAULTSTATUS register.


FAULTSTATUS - Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.

Address:

  Instance 0 Address:   0x400201CC

Description:

Reflects the status of the bus decoders' fault detection. Any write to this register will clear all of the status bits within the register.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
SYSFAULT
0x0
DCODEFAULT
0x0
ICODEFAULT
0x0

Bits Name RW Description
31:3 RSVD RO RESERVED

2 SYSFAULT RW SYS Bus Decoder Fault Detected bit. When set, a fault has been detected, and the SYSFAULTADDR register will contain the bus address which generated the fault.

NOFAULT = 0x0 - No bus fault has been detected.
FAULT = 0x1 - Bus fault detected.
1 DCODEFAULT RW DCODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the DCODEFAULTADDR register will contain the bus address which generated the fault.

NOFAULT = 0x0 - No DCODE fault has been detected.
FAULT = 0x1 - DCODE fault detected.
0 ICODEFAULT RW The ICODE Bus Decoder Fault Detected bit. When set, a fault has been detected, and the ICODEFAULTADDR register will contain the bus address which generated the fault.

NOFAULT = 0x0 - No ICODE fault has been detected.
FAULT = 0x1 - ICODE fault detected.

FAULTCAPTUREEN - Enable the fault capture registers

Address:

  Instance 0 Address:   0x400201D0

Description:

Enable the fault capture registers

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
FAULTCAPTUREEN
0x0

Bits Name RW Description
31:1 RSVD RO RESERVED

0 FAULTCAPTUREEN RW Fault Capture Enable field. When set, the Fault Capture monitors are enabled and addresses which generate a hard fault are captured into the FAULTADDR registers.

DIS = 0x0 - Disable fault capture.
EN = 0x1 - Enable fault capture.

DBGR1 - Read-only debug register 1

Address:

  Instance 0 Address:   0x40020200

Description:

Read-only debug register 1

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ONETO8
0x12345678

Bits Name RW Description
31:0 ONETO8 RO Read-only register for communication validation


DBGR2 - Read-only debug register 2

Address:

  Instance 0 Address:   0x40020204

Description:

Read-only debug register 2

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COOLCODE
0xc001c0de

Bits Name RW Description
31:0 COOLCODE RO Read-only register for communication validation


PMUENABLE - Control bit to enable/disable the PMU

Address:

  Instance 0 Address:   0x40020220

Description:

Control bit to enable/disable the PMU

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ENABLE
0x1

Bits Name RW Description
31:1 RSVD RO RESERVED

0 ENABLE RW PMU Enable Control bit. When set, the MCU's PMU will place the MCU into the lowest power consuming Deep Sleep mode upon execution of a WFI instruction (dependent on the setting of the SLEEPDEEP bit in the ARM SCR register). When cleared, regardless of the requested sleep mode, the PMU will not enter the lowest power Deep Sleep mode, instead entering the Sleep mode.

DIS = 0x0 - Disable MCU power management.
EN = 0x1 - Enable MCU power management.

TPIUCTRL - TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.

Address:

  Instance 0 Address:   0x40020250

Description:

TPIU Control Register. Determines the clock enable and frequency for the M4's TPIU interface.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CLKSEL
0x0
RSVD
0x0
ENABLE
0x0

Bits Name RW Description
31:11 RSVD RO RESERVED

10:8 CLKSEL RW This field selects the frequency of the ARM M4 TPIU port.

LOWPWR = 0x0 - Low power state.
HFRCDIV2 = 0x1 - Selects HFRC divided by 2 as the source TPIU clock
HFRCDIV8 = 0x2 - Selects HFRC divided by 8 as the source TPIU clock
HFRCDIV16 = 0x3 - Selects HFRC divided by 16 as the source TPIU clock
HFRCDIV32 = 0x4 - Selects HFRC divided by 32 as the source TPIU clock
LOW_PWR = 0x0 - Deprecated-do not use. Low power state.
HFRC_DIV_2 = 0x1 - Deprecated-do not use. Selects HFRC divided by 2 as the source TPIU clock
HFRC_DIV_8 = 0x2 - Deprecated-do not use. Selects HFRC divided by 8 as the source TPIU clock
HFRC_DIV_16 = 0x3 - Deprecated-do not use. Selects HFRC divided by 16 as the source TPIU clock
HFRC_DIV_32 = 0x4 - Deprecated-do not use. Selects HFRC divided by 32 as the source TPIU clock
7:1 RSVD RO RESERVED

0 ENABLE RW TPIU Enable field. When set, the ARM M4 TPIU is enabled and data can be streamed out of the MCU's SWO port using the ARM ITM and TPIU modules.

DIS = 0x0 - Disable the TPIU.
EN = 0x1 - Enable the TPIU.

OTAPOINTER - OTA (Over the Air) Update Pointer/Status. Reset only by POA

Address:

  Instance 0 Address:   0x40020264

Description:

OTA (Over the Air) Update Pointer/Status. Reset only by POA

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OTAPOINTER
0x0
OTASBLUPDATE
0x0
OTAVALID
0x0

Bits Name RW Description
31:2 OTAPOINTER RW Flash page pointer with updated OTA image

1 OTASBLUPDATE RW Indicates that the sbl_init has been updated

0 OTAVALID RW Indicates that an OTA update is valid


APBDMACTRL - DMA Control Register. Determines misc settings for DMA operation

Address:

  Instance 0 Address:   0x40020280

Description:

DMA Control Register. Determines misc settings for DMA operation

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
HYSTERESIS
0x2
RSVD
0x0
DECODEABORT
0x1
DMA_ENABLE
0x1

Bits Name RW Description
31:16 RSVD RO RESERVED

15:8 HYSTERESIS RW This field determines how long the DMA will remain active during deep sleep before shutting down and returning the system to full deep sleep. Values are based on a 94KHz clock and are roughly 10 us increments for a range of ~10 us to 2.55 ms

7:2 RSVD RO RESERVED

1 DECODEABORT RW APB Decode Abort. When set, the APB bridge will issue a data abort (bus fault) on transactions to peripherals that are powered down. When set to 0, writes are quietly discarded and reads return 0.

DISABLE = 0x0 - Bus operations to powered down peripherals are quietly discarded
ENABLE = 0x1 - Bus operations to powered down peripherals result in a bus fault.
0 DMA_ENABLE RW Enable the DMA controller. When disabled, DMA requests will be ignored by the controller

DISABLE = 0x0 - DMA operations disabled
ENABLE = 0x1 - DMA operations enabled

SRAMMODE - SRAM Controller mode bits

Address:

  Instance 0 Address:   0x40020284

Description:

SRAM Controller mode bits

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
RSVD
0x0
DPREFETCH_CACHE
0x0
DPREFETCH
0x0
RSVD
0x0
IPREFETCH_CACHE
0x0
IPREFETCH
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED

7:6 RSVD RO RESERVED

5 DPREFETCH_CACHE RW Secondary pre-fetch feature that will cache pre-fetched data across bus wait states (requires DPREFETCH to be set).

4 DPREFETCH RW When set, data bus accesses to the SRAM banks will be pre-fetched (normally 2 cycle read access). Use of this mode bit is only recommended if the work flow has a large number of sequential accesses.

3:2 RSVD RO RESERVED

1 IPREFETCH_CACHE RW Secondary pre-fetch feature that will cache pre-fetched data across bus wait states (requires IPREFETCH to be set).

0 IPREFETCH RW When set, instruction accesses to the SRAM banks will be pre-fetched (normally 2 cycle read access). Generally, this mode bit should be set for improved performance when executing instructions from SRAM.


KEXTCLKSEL - Key Register to enable the use of external clock selects via the EXTCLKSEL reg

Address:

  Instance 0 Address:   0x40020348

Description:

Locks the state of the EXTCLKSEL register from writes. This is done to prevent errant writes to the register, as this could cause the chip to halt. Write a value of 0x53 to unlock write access to the EXTCLKSEL register. Once unlocked, the register will read back a 1 to indicate this is unlocked. Writing the register with any other value other than 0x53 will enable the lock.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEXTCLKSEL
0x0

Bits Name RW Description
31:0 KEXTCLKSEL RW Key register value.

Key = 0x53 - Key value to unlock the register.

SIMOBUCK1 - SIMO Buck Control Reg 1

Address:

  Instance 0 Address:   0x40020350

Description:

SIMO Buck Control Reg 1

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED_RW_23
0x0
SIMOBUCKMEMLPTRIM
0x20
RESERVED_RW_00
0x0

Bits Name RW Description
31:28 RESERVED_RW_23 RW Reserved bits, always leave unchanged. The SIMOBUCK1 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior.

27:22 SIMOBUCKMEMLPTRIM RW simobuck_mem_lp_trim

21:0 RESERVED_RW_00 RW Reserved bits, always leave unchanged. The SIMOBUCK1 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior.


SIMOBUCK2 - SIMO Buck Control Reg 2

Address:

  Instance 0 Address:   0x40020354

Description:

SIMO Buck Control Reg 2

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED_RW_30
0x0
SIMOBUCKCORELEAKAGETRIM
0x0
RESERVED_RW_24
0x0
SIMOBUCKCORELPLOWTONTRIM
0xa
SIMOBUCKCORELPHIGHTONTRIM
0xa
RESERVED_RW_5
0x0
SIMOBUCKTONGENTRIM
0x10

Bits Name RW Description
31:30 RESERVED_RW_30 RW Reserved bits, always leave unchanged. The SIMOBUCK2 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior.

29:28 SIMOBUCKCORELEAKAGETRIM RW simobuck_core_leakage_trim

27:24 RESERVED_RW_24 RW Reserved bits, always leave unchanged. The SIMOBUCK2 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior.

23:20 SIMOBUCKCORELPLOWTONTRIM RW simobuck_core_lp_low_ton_trim

19:16 SIMOBUCKCORELPHIGHTONTRIM RW simobuck_core_lp_high_ton_trim

15:5 RESERVED_RW_5 RW Reserved bits, always leave unchanged. The SIMOBUCK2 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior.

4:0 SIMOBUCKTONGENTRIM RW simobuck_tongen_trim


SIMOBUCK3 - SIMO Buck Control Reg 3

Address:

  Instance 0 Address:   0x40020358

Description:

SIMO Buck Control Reg 3

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED_RW_31
0x0
SIMOBUCKMEMLPHIGHTONTRIM
0xa
RESERVED_RW_16
0x0
SIMOBUCKMEMLPLOWTOFFTRIM
0xa
SIMOBUCKMEMLPHIGHTOFFTRIM
0xa
SIMOBUCKCORELPLOWTOFFTRIM
0xa
SIMOBUCKCORELPHIGHTOFFTRIM
0xa

Bits Name RW Description
31 RESERVED_RW_31 RW Reserved bits, always leave unchanged. The SIMOBUCK2 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior.

30:27 SIMOBUCKMEMLPHIGHTONTRIM RW simobuck_mem_lp_high_ton_trim

26:16 RESERVED_RW_16 RW Reserved bits, always leave unchanged. The SIMOBUCK3 register must be modified via atomic RMW, leaving this bit field completely unmodified. Failure to do so will result in unpredictable behavior.

15:12 SIMOBUCKMEMLPLOWTOFFTRIM RW simobuck_mem_lp_low_toff_trim

11:8 SIMOBUCKMEMLPHIGHTOFFTRIM RW simobuck_mem_lp_high_toff_trim

7:4 SIMOBUCKCORELPLOWTOFFTRIM RW simobuck_core_lp_low_toff_trim

3:0 SIMOBUCKCORELPHIGHTOFFTRIM RW simobuck_core_lp_high_toff_trim


SIMOBUCK4 - SIMO Buck Control Reg 4

Address:

  Instance 0 Address:   0x4002035C

Description:

SIMO Buck Control Reg 4

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD28
0x3
RSVD26
0x3
RSVD25
0x0
SIMOBUCKCOMP2TIMEOUTEN
0x0
SIMOBUCKCOMP2LPEN
0x1
SIMOBUCKCLKDIVSEL
0x0
RSVD20
0x0
RSVD17
0x6
RSVD14
0x6
RSVD10
0x0
RSVD08
0x0
RSVD06
0x2
RSVD04
0x2
SIMOBUCKMEMLPLOWTONTRIM
0xa

Bits Name RW Description
31:28 RSVD28 RW RESERVED - this field should not be modified

27:26 RSVD26 RW RESERVED - this field should not be modified

25 RSVD25 RW RESERVED - this field should not be modified

24 SIMOBUCKCOMP2TIMEOUTEN RW simobuck_comp2_timeout_en

23 SIMOBUCKCOMP2LPEN RW simobuck_comp2_lp_en

22:21 SIMOBUCKCLKDIVSEL RW simobuck_clkdiv_sel

20 RSVD20 RW RESERVED - this field should not be modified

19:17 RSVD17 RW RESERVED - this field should not be modified

16:14 RSVD14 RW RESERVED - this field should not be modified

13:10 RSVD10 RW RESERVED - this field should not be modified

9:8 RSVD08 RW RESERVED - this field should not be modified

7:6 RSVD06 RW RESERVED - this field should not be modified

5:4 RSVD04 RW RESERVED - this field should not be modified

3:0 SIMOBUCKMEMLPLOWTONTRIM RW simobuck_mem_lp_low_ton_trim


BLEBUCK2 - BLEBUCK2 Control Reg

Address:

  Instance 0 Address:   0x40020368

Description:

BLEBUCK2 Control Reg

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
BLEBUCKTOND2ATRIM
0x0
BLEBUCKTONHITRIM
0x1
BLEBUCKTONLOWTRIM
0xe

Bits Name RW Description
31:18 RSVD RO RESERVED

17:12 BLEBUCKTOND2ATRIM RO blebuck_ton_trim

11:6 BLEBUCKTONHITRIM RW blebuck_ton_hi_trim

5:0 BLEBUCKTONLOWTRIM RW blebuck_ton_low_trim


FLASHWPROT0 - Flash Write Protection Bits

Address:

  Instance 0 Address:   0x400203A0

Description:

These bits write-protect flash in 16KB chunks.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FW0BITS
0x0

Bits Name RW Description
31:0 FW0BITS RW Write protect flash 0x00000000 - 0x0007FFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)


FLASHWPROT1 - Flash Write Protection Bits

Address:

  Instance 0 Address:   0x400203A4

Description:

These bits write-protect flash in 16KB chunks.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FW1BITS
0x0

Bits Name RW Description
31:0 FW1BITS RW Write protect flash 0x00080000 - 0x000FFFFF. Each bit provides write protection for 16KB chunks of flash data space. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)


FLASHRPROT0 - Flash Read Protection Bits

Address:

  Instance 0 Address:   0x400203B0

Description:

These bits read-protect flash in 16KB chunks.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FR0BITS
0x0

Bits Name RW Description
31:0 FR0BITS RW Copy (read) protect flash 0x00000000 - 0x0007FFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)


FLASHRPROT1 - Flash Read Protection Bits

Address:

  Instance 0 Address:   0x400203B4

Description:

These bits read-protect flash in 16KB chunks.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FR1BITS
0x0

Bits Name RW Description
31:0 FR1BITS RW Copy (read) protect flash 0x00080000 - 0x000FFFFF. Each bit provides read protection for 16KB chunks of flash. Bits are cleared by writing a 1 to the bit. When read, 0 indicates the region is protected. Bits are sticky (can be set when PROTLOCK is 1, but only cleared by reset)


DMASRAMWRITEPROTECT0 - SRAM write-protection bits.

Address:

  Instance 0 Address:   0x400203C0

Description:

These bits write-protect system SRAM from DMA operations in 8KB chunks.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA_WPROT0
0x0

Bits Name RW Description
31:0 DMA_WPROT0 RW Write protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA writes, when set to 0, DMA may write the region.


DMASRAMWRITEPROTECT1 - SRAM write-protection bits.

Address:

  Instance 0 Address:   0x400203C4

Description:

These bits write-protect system SRAM from DMA operations in 8KB chunks.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DMA_WPROT1
0x0

Bits Name RW Description
31:16 RSVD RO RESERVED

15:0 DMA_WPROT1 RW Write protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA writes, when set to 0, DMA may write the region.


DMASRAMREADPROTECT0 - SRAM read-protection bits.

Address:

  Instance 0 Address:   0x400203D0

Description:

These bits read-protect system SRAM from DMA operations in 8KB chunks.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA_RPROT0
0x0

Bits Name RW Description
31:0 DMA_RPROT0 RW Read protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA reads, when set to 0, DMA may read the region.


DMASRAMREADPROTECT1 - SRAM read-protection bits.

Address:

  Instance 0 Address:   0x400203D4

Description:

These bits read-protect system SRAM from DMA operations in 8KB chunks.

Example Macro Usage:

//
// Register access is all performed through the standard CMSIS structure-based
// interface. This includes module-level structure definitions with members and
// bitfields corresponding to the physical registers and bitfields within each
// module. In addition, Ambiq has provided instance-level macros for modules
// that have more than one physical instance and a generic AM_REGVAL() macro
// for directly accessing memory by address.
//
// The following examples show how to use these structures and macros:

// Setting the ADC configuration register...
AM_REGVAL(0x50010000) = 0x1234;              // by address.
ADC->CFG = 0x1234;                           // by structure pointer.
ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

// Changing the ADC clock...
ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DMA_RPROT1
0x0

Bits Name RW Description
31:16 RSVD RO RESERVED

15:0 DMA_RPROT1 RW Read protect SRAM from DMA. Each bit provides write protection for an 8KB region of memory. When set to 1, the region will be protected from DMA reads, when set to 0, DMA may read the region.