Apollo Register Documentation  v${version}
PWRCTRL - PWR Controller Register Bank

PWRCTRL Register Index

  0x00000000:   SUPPLYSRC - Memory and Core Voltage Supply Source Select Register
  0x00000004:   POWERSTATUS - Power Status Register for MCU supplies and peripherals
  0x00000008:   DEVICEEN - DEVICE ENABLES for SHELBY
  0x0000000C:   SRAMPWDINSLEEP - Powerdown an SRAM Banks in Deep Sleep mode
  0x00000010:   MEMEN - Disables individual banks of the MEMORY array
  0x00000014:   PWRONSTATUS - POWER ON Status
  0x00000018:   SRAMCTRL - SRAM Control register
  0x0000001C:   ADCSTATUS - Power Status Register for ADC Block
  0x00000020:   MISCOPT - Power Optimization Control Bits

SUPPLYSRC - Memory and Core Voltage Supply Source Select Register

Address:

  Instance 0 Address:   0x40021000

Description:

Memory and Core Voltage Supply Source Select Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
SWITCH_LDO_IN_SLEEP
0x1
COREBUCKEN
0x0
MEMBUCKEN
0x0

Bits Name RW Description
31:3 RSVD RO RESERVED.

2 SWITCH_LDO_IN_SLEEP RW Switches the CORE DOMAIN from BUCK mode (if enabled) to LDO when CPU is in DEEP SLEEP. If all the devices are off then this does not matter and LDO (low power mode) is used

EN = 0x1 - Automatically switch from CORE BUCK to CORE LDO when CPU is in DEEP SLEEP
1 COREBUCKEN RW Enables and Selects the Core Buck as the supply for the low-voltage power domain.

EN = 0x1 - Enable the Core Buck for the low-voltage power domain.
0 MEMBUCKEN RW Enables and select the Memory Buck as the supply for the Flash and SRAM power domain.

EN = 0x1 - Enable the Memory Buck as the supply for flash and SRAM.

POWERSTATUS - Power Status Register for MCU supplies and peripherals

Address:

  Instance 0 Address:   0x40021004

Description:

Power Status Register for MCU supplies and peripherals

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
COREBUCKON
0x0
MEMBUCKON
0x0

Bits Name RW Description
31:2 RSVD RO RESERVED.

1 COREBUCKON RO Indicates whether the Core low-voltage domain is supplied from the LDO or the Buck.

LDO = 0x0 - Indicates the the LDO is supplying the Core low-voltage.
BUCK = 0x1 - Indicates the the Buck is supplying the Core low-voltage.
0 MEMBUCKON RO Indicate whether the Memory power domain is supplied from the LDO or the Buck.

LDO = 0x0 - Indicates the LDO is supplying the memory power domain.
BUCK = 0x1 - Indicates the Buck is supplying the memory power domain.

DEVICEEN - DEVICE ENABLES for SHELBY

Address:

  Instance 0 Address:   0x40021008

Description:

DEVICE ENABLES for SHELBY

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
PWRPDM
0x0
PWRADC
0x0
PWRUART1
0x0
PWRUART0
0x0
IO_MASTER5
0x0
IO_MASTER4
0x0
IO_MASTER3
0x0
IO_MASTER2
0x0
IO_MASTER1
0x0
IO_MASTER0
0x0
IO_SLAVE
0x0

Bits Name RW Description
31:11 RSVD RO RESERVED.

10 PWRPDM RW Enable PDM Digital Block

EN = 0x1 - Enable PDM
DIS = 0x0 - Disables PDM
9 PWRADC RW Enable ADC Digital Block

EN = 0x1 - Enable ADC
DIS = 0x0 - Disables ADC
8 PWRUART1 RW Enable UART 1

EN = 0x1 - Enable UART 1
DIS = 0x0 - Disables UART 1
7 PWRUART0 RW Enable UART 0

EN = 0x1 - Enable UART 0
DIS = 0x0 - Disables UART 0
6 IO_MASTER5 RW Enable IO MASTER 5

EN = 0x1 - Enable IO MASTER 5
DIS = 0x0 - Disables IO MASTER 5
5 IO_MASTER4 RW Enable IO MASTER 4

EN = 0x1 - Enable IO MASTER 4
DIS = 0x0 - Disables IO MASTER 4
4 IO_MASTER3 RW Enable IO MASTER 3

EN = 0x1 - Enable IO MASTER 3
DIS = 0x0 - Disables IO MASTER 3
3 IO_MASTER2 RW Enable IO MASTER 2

EN = 0x1 - Enable IO MASTER 2
DIS = 0x0 - Disables IO MASTER 2
2 IO_MASTER1 RW Enable IO MASTER 1

EN = 0x1 - Enable IO MASTER 1
DIS = 0x0 - Disables IO MASTER 1
1 IO_MASTER0 RW Enable IO MASTER 0

EN = 0x1 - Enable IO MASTER 0
DIS = 0x0 - Disables IO MASTER 0
0 IO_SLAVE RW Enable IO SLAVE

EN = 0x1 - Enable IO SLAVE
DIS = 0x0 - Disables IO SLAVE

SRAMPWDINSLEEP - Powerdown an SRAM Banks in Deep Sleep mode

Address:

  Instance 0 Address:   0x4002100C

Description:

Powerdown an SRAM Banks in Deep Sleep mode

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CACHE_PWD_SLP
0x0
RSVD
0x0
SRAMSLEEPPOWERDOWN
0x0

Bits Name RW Description
31 CACHE_PWD_SLP RW Enable CACHE BANKS to power down in deep sleep

EN = 0x1 - CACHE BANKS POWER DOWN in CORE SLEEP
DIS = 0x0 - CACHE BANKS STAYS in Retention in CORE SLEEP
30:11 RSVD RO RESERVED.

10:0 SRAMSLEEPPOWERDOWN RW Selects which SRAM banks are powered down in deep sleep mode, causing the contents of the bank to be lost.

NONE = 0x0 - All banks retained
GROUP0_SRAM0 = 0x1 - 0KB-8KB SRAM
GROUP0_SRAM1 = 0x2 - 8KB-16KB SRAM
GROUP0_SRAM2 = 0x4 - 16KB-24KB SRAM
GROUP0_SRAM3 = 0x8 - 24KB-32KB SRAM
GROUP1 = 0x10 - 32KB-64KB SRAMs
GROUP2 = 0x20 - 64KB-96KB SRAMs
GROUP3 = 0x40 - 96KB-128KB SRAMs
GROUP4 = 0x80 - 128KB-160KB SRAMs
GROUP5 = 0x100 - 160KB-192KB SRAMs
GROUP6 = 0x200 - 192KB-224KB SRAMs
GROUP7 = 0x400 - 224KB-256KB SRAMs
SRAM8K = 0x1 - Do not Retain lower 8KB
SRAM16K = 0x3 - Do not Retain lower 16KB
SRAM32K = 0xF - Do not Retain lower 32KB
SRAM64K = 0x1F - Do not Retain lower 64KB
SRAM128K = 0x7F - Do not Retain lower 128KB
ALLBUTLOWER8K = 0x7FE - All banks but lower 8k powered down.
ALLBUTLOWER16K = 0x7FC - All banks but lower 16k powered down.
ALLBUTLOWER24K = 0x7F8 - All banks but lower 24k powered down.
ALLBUTLOWER32K = 0x7F0 - All banks but lower 32k powered down.
ALLBUTLOWER64K = 0x7E0 - All banks but lower 64k powered down.
ALLBUTLOWER128K = 0x780 - All banks but lower 128k powered down.
ALL = 0x7FF - All banks powered down.

MEMEN - Disables individual banks of the MEMORY array

Address:

  Instance 0 Address:   0x40021010

Description:

Disables individual banks of the MEMORY array

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CACHEB2
0x1
RSVD
0x0
CACHEB0
0x1
RSVD
0x0
FLASH1
0x1
FLASH0
0x1
SRAMEN
0x7ff

Bits Name RW Description
31 CACHEB2 RW Enable CACHE BANK 2

EN = 0x1 - Enable CACHE BANK 2
DIS = 0x0 - Disable CACHE BANK 2
30 RSVD RO Reserved

29 CACHEB0 RW Enable CACHE BANK 0

EN = 0x1 - Enable CACHE BANK 0
DIS = 0x0 - Disable CACHE BANK 0
28:13 RSVD RO RESERVED.

12 FLASH1 RW Enable FLASH1

EN = 0x1 - Enable FLASH1
DIS = 0x0 - Disables FLASH1
11 FLASH0 RW Enable FLASH 0

EN = 0x1 - Enable FLASH 0
DIS = 0x0 - Disables FLASH 0
10:0 SRAMEN RW Enables power for selected SRAM banks (else an access to its address space to generate a Hard Fault).

NONE = 0x0 - All banks disabled
GROUP0_SRAM0 = 0x1 - 0KB-8KB SRAM
GROUP0_SRAM1 = 0x2 - 8KB-16KB SRAM
GROUP0_SRAM2 = 0x4 - 16KB-24KB SRAM
GROUP0_SRAM3 = 0x8 - 24KB-32KB SRAM
GROUP1 = 0x10 - 32KB-64KB SRAMs
GROUP2 = 0x20 - 64KB-96KB SRAMs
GROUP3 = 0x40 - 96KB-128KB SRAMs
GROUP4 = 0x80 - 128KB-160KB SRAMs
GROUP5 = 0x100 - 160KB-192KB SRAMs
GROUP6 = 0x200 - 192KB-224KB SRAMs
GROUP7 = 0x400 - 224KB-256KB SRAMs
SRAM8K = 0x1 - ENABLE lower 8KB
SRAM16K = 0x3 - ENABLE lower 16KB
SRAM32K = 0xF - ENABLE lower 32KB
SRAM64K = 0x1F - ENABLE lower 64KB
SRAM128K = 0x7F - ENABLE lower 128KB
SRAM256K = 0x7FF - ENABLE lower 256KB
ALL = 0x7FF - All banks ENABLED

PWRONSTATUS - POWER ON Status

Address:

  Instance 0 Address:   0x40021014

Description:

POWER ON Status

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
RSVD
0x0
RSVD
0x0
RSVD
0x0
PD_CACHEB2
0x0
RSVD
0x0
PD_CACHEB0
0x0
PD_GRP7_SRAM
0x0
PD_GRP6_SRAM
0x0
PD_GRP5_SRAM
0x0
PD_GRP4_SRAM
0x0
PD_GRP3_SRAM
0x0
PD_GRP2_SRAM
0x0
PD_GRP1_SRAM
0x0
PD_GRP0_SRAM3
0x0
PD_GRP0_SRAM2
0x0
PD_GRP0_SRAM1
0x0
PD_GRP0_SRAM0
0x0
PDADC
0x0
PD_FLAM1
0x0
PD_FLAM0
0x0
PD_PDM
0x0
PDC
0x0
PDB
0x0
PDA
0x0
RSVD
0x0

Bits Name RW Description
31 RSVD RO RESERVED

30 RSVD RO RESERVED

29 RSVD RO RESERVED

28:22 RSVD RO This bitfield is reserved for future use.

21 PD_CACHEB2 RO This bit is 1 if power is supplied to CACHE BANK 2

20 RSVD RO Reserved

19 PD_CACHEB0 RO This bit is 1 if power is supplied to CACHE BANK 0

18 PD_GRP7_SRAM RO This bit is 1 if power is supplied to SRAM domain PD_GRP7

17 PD_GRP6_SRAM RO This bit is 1 if power is supplied to SRAM domain PD_GRP6

16 PD_GRP5_SRAM RO This bit is 1 if power is supplied to SRAM domain PD_GRP5

15 PD_GRP4_SRAM RO This bit is 1 if power is supplied to SRAM domain PD_GRP4

14 PD_GRP3_SRAM RO This bit is 1 if power is supplied to SRAM domain PD_GRP3

13 PD_GRP2_SRAM RO This bit is 1 if power is supplied to SRAM domain PD_GRP2

12 PD_GRP1_SRAM RO This bit is 1 if power is supplied to SRAM domain PD_GRP1

11 PD_GRP0_SRAM3 RO This bit is 1 if power is supplied to SRAM domain PD_SRAM0_3

10 PD_GRP0_SRAM2 RO This bit is 1 if power is supplied to SRAM domain PD_SRAM0_2

9 PD_GRP0_SRAM1 RO This bit is 1 if power is supplied to SRAM domain SRAM0_1

8 PD_GRP0_SRAM0 RO This bit is 1 if power is supplied to SRAM domain SRAM0_0

7 PDADC RO This bit is 1 if power is supplied to domain PD_ADC

6 PD_FLAM1 RO This bit is 1 if power is supplied to domain PD_FLAM1

5 PD_FLAM0 RO This bit is 1 if power is supplied to domain PD_FLAM0

4 PD_PDM RO This bit is 1 if power is supplied to domain PD_PDM

3 PDC RO This bit is 1 if power is supplied to power domain C, which supplies IOM3-5.

2 PDB RO This bit is 1 if power is supplied to power domain B, which supplies IOM0-2.

1 PDA RO This bit is 1 if power is supplied to power domain A, which supplies IOS and UART0,1.

0 RSVD RO RESERVED


SRAMCTRL - SRAM Control register

Address:

  Instance 0 Address:   0x40021018

Description:

SRAM Control register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
SRAM_MASTER_CLKGATE
0x0
SRAM_CLKGATE
0x0
SRAM_LIGHT_SLEEP
0x1

Bits Name RW Description
31:3 RSVD RO This bitfield is reserved for future use.

2 SRAM_MASTER_CLKGATE RW Enables top-level clock gating in the SRAM block. This bit should be enabled for lowest power operation.

EN = 0x1 - Enable Master SRAM Clock Gate
DIS = 0x0 - Disables Master SRAM Clock Gating
1 SRAM_CLKGATE RW Enables individual per-RAM clock gating in the SRAM block. This bit should be enabled for lowest power operation.

EN = 0x1 - Enable Individual SRAM Clock Gating
DIS = 0x0 - Disables Individual SRAM Clock Gating
0 SRAM_LIGHT_SLEEP RW Enable LS (light sleep) of cache RAMs. When this bit is set, the RAMS will be put into light sleep mode while inactive. NOTE: if the SRAM is actively used, this may have an adverse affect on power since entering/exiting LS mode may consume more power than would be saved.

EN = 0x1 - Enable LIGHT SLEEP for SRAMs
DIS = 0x0 - Disables LIGHT SLEEP for SRAMs

ADCSTATUS - Power Status Register for ADC Block

Address:

  Instance 0 Address:   0x4002101C

Description:

Power Status Register for ADC Block

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
ADC_REFBUF_PWD
0x0
ADC_REFKEEP_PWD
0x0
ADC_VBAT_PWD
0x0
ADC_VPTAT_PWD
0x0
ADC_BGT_PWD
0x0
ADC_PWD
0x0

Bits Name RW Description
31:6 RSVD RO RESERVED.

5 ADC_REFBUF_PWD RO This bit indicates that the ADC REFBUF is powered down

4 ADC_REFKEEP_PWD RO This bit indicates that the ADC REFKEEP is powered down

3 ADC_VBAT_PWD RO This bit indicates that the ADC VBAT resistor divider is powered down

2 ADC_VPTAT_PWD RO This bit indicates that the ADC temperature sensor input buffer is powered down

1 ADC_BGT_PWD RO This bit indicates that the ADC Band Gap is powered down

0 ADC_PWD RO This bit indicates that the ADC is powered down


MISCOPT - Power Optimization Control Bits

Address:

  Instance 0 Address:   0x40021020

Description:

Power Optimization Control Bits

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
DIS_LDOLPMODE_TIMERS
0x0
RSVD01
0x0
RSVD00
0x0

Bits Name RW Description
31:3 RSVD RO RESERVED.

2 DIS_LDOLPMODE_TIMERS RW Setting this bit will enable the MEM LDO to be in LPMODE during deep sleep even when the ctimers or stimers are running

1 RSVD01 RW RESERVED - this field should not be modified

0 RSVD00 RW RESERVED - this field should not be modified