Apollo Register Documentation  v${version}
CTIMER - Counter/Timer

CTIMER Register Index

  0x00000000:   TMR0 - Counter/Timer Register
  0x00000004:   CMPRA0 - Counter/Timer A0 Compare Registers
  0x00000008:   CMPRB0 - Counter/Timer B0 Compare Registers
  0x0000000C:   CTRL0 - Counter/Timer Control
  0x00000010:   TMR1 - Counter/Timer Register
  0x00000014:   CMPRA1 - Counter/Timer A1 Compare Registers
  0x00000018:   CMPRB1 - Counter/Timer B1 Compare Registers
  0x0000001C:   CTRL1 - Counter/Timer Control
  0x00000020:   TMR2 - Counter/Timer Register
  0x00000024:   CMPRA2 - Counter/Timer A2 Compare Registers
  0x00000028:   CMPRB2 - Counter/Timer B2 Compare Registers
  0x0000002C:   CTRL2 - Counter/Timer Control
  0x00000030:   TMR3 - Counter/Timer Register
  0x00000034:   CMPRA3 - Counter/Timer A3 Compare Registers
  0x00000038:   CMPRB3 - Counter/Timer B3 Compare Registers
  0x0000003C:   CTRL3 - Counter/Timer Control
  0x00000200:   INTEN - Counter/Timer Interrupts: Enable
  0x00000204:   INTSTAT - Counter/Timer Interrupts: Status
  0x00000208:   INTCLR - Counter/Timer Interrupts: Clear
  0x0000020C:   INTSET - Counter/Timer Interrupts: Set

TMR0 - Counter/Timer Register

Address:

  Instance 0 Address:   0x40008000

Description:

This register holds the running time or event count, either for each 16 bit half or for the whole 32 bit count when the pair is linked.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTTMRB0
0x0
CTTMRA0
0x0

Bits Name RW Description
31:16 CTTMRB0 RO Counter/Timer B0.

15:0 CTTMRA0 RO Counter/Timer A0.


CMPRA0 - Counter/Timer A0 Compare Registers

Address:

  Instance 0 Address:   0x40008004

Description:

Compare limits for timer half A.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1A0
0x0
CMPR0A0
0x0

Bits Name RW Description
31:16 CMPR1A0 RW Counter/Timer A0 Compare Register 1. Holds the upper limit for timer half A.

15:0 CMPR0A0 RW Counter/Timer A0 Compare Register 0. Holds the lower limit for timer half A.


CMPRB0 - Counter/Timer B0 Compare Registers

Address:

  Instance 0 Address:   0x40008008

Description:

Compare limits for timer half B.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1B0
0x0
CMPR0B0
0x0

Bits Name RW Description
31:16 CMPR1B0 RW Counter/Timer B0 Compare Register 1. Holds the upper limit for timer half B.

15:0 CMPR0B0 RW Counter/Timer B0 Compare Register 0. Holds the lower limit for timer half B.


CTRL0 - Counter/Timer Control

Address:

  Instance 0 Address:   0x4000800C

Description:

Control bit fields for both halves of timer 0.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTLINK0
0x0
RSVD
0x0
TMRB0POL
0x0
TMRB0CLR
0x0
TMRB0PE
0x0
TMRB0IE
0x0
TMRB0FN
0x0
TMRB0CLK
0x0
TMRB0EN
0x0
RSVD
0x0
TMRA0POL
0x0
TMRA0CLR
0x0
TMRA0PE
0x0
TMRA0IE
0x0
TMRA0FN
0x0
TMRA0CLK
0x0
TMRA0EN
0x0

Bits Name RW Description
31 CTLINK0 RW Counter/Timer A0/B0 Link bit.

TWO_16BIT_TIMERS = 0x0 - Use A0/B0 timers as two independent 16-bit timers (default).
32BIT_TIMER = 0x1 - Link A0/B0 timers into a single 32-bit timer.
30:29 RSVD RO RESERVED

28 TMRB0POL RW Counter/Timer B0 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINB0 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINB0 pin is the inverse of the timer output.
27 TMRB0CLR RW Counter/Timer B0 Clear bit.

RUN = 0x0 - Allow counter/timer B0 to run
CLEAR = 0x1 - Holds counter/timer B0 at 0x0000.
26 TMRB0PE RW Counter/Timer B0 Output Enable bit.

DIS = 0x0 - Counter/Timer B holds the TMRPINB signal at the value TMRB0POL.
EN = 0x1 - Enable counter/timer B0 to generate a signal on TMRPINB.
25 TMRB0IE RW Counter/Timer B0 Interrupt Enable bit.

DIS = 0x0 - Disable counter/timer B0 from generating an interrupt.
EN = 0x1 - Enable counter/timer B0 to generate an interrupt.
24:22 TMRB0FN RW Counter/Timer B0 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B0, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B0, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B0, assert, count to CMPR1B, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B0, assert, count to CMPR1B0, deassert, restart.
CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
21:17 TMRB0CLK RW Counter/Timer B0 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINB.
HFRC = 0x1 - Clock source is the HFRC
HFRC_DIV8 = 0x2 - Clock source is HFRC / 8
HFRC_DIV128 = 0x3 - Clock source is HFRC / 128
HFRC_DIV512 = 0x4 - Clock source is HFRC / 512
HFRC_DIV2K = 0x5 - Clock source is HFRC / 2048
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV256 = 0x9 - Clock source is XT / 256
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC / 16K
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK = 0xF - Clock source is HCLK.
BUCKB = 0x10 - Clock source is buck converter stream B.
16 TMRB0EN RW Counter/Timer B0 Enable bit.

DIS = 0x0 - Counter/Timer B0 Disable.
EN = 0x1 - Counter/Timer B0 Enable.
15:13 RSVD RO RESERVED

12 TMRA0POL RW Counter/Timer A0 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINA0 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINA0 pin is the inverse of the timer output.
11 TMRA0CLR RW Counter/Timer A0 Clear bit.

RUN = 0x0 - Allow counter/timer A0 to run
CLEAR = 0x1 - Holds counter/timer A0 at 0x0000.
10 TMRA0PE RW Counter/Timer A0 Output Enable bit.

DIS = 0x0 - Counter/Timer A holds the TMRPINA signal at the value TMRA0POL.
EN = 0x1 - Enable counter/timer B0 to generate a signal on TMRPINB.
9 TMRA0IE RW Counter/Timer A0 Interrupt Enable bit.

DIS = 0x0 - Disable counter/timer A0 from generating an interrupt.
EN = 0x1 - Enable counter/timer A0 to generate an interrupt.
8:6 TMRA0FN RW Counter/Timer A0 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A0, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A0, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A0, assert, count to CMPR1B, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A0, assert, count to CMPR1A0, deassert, restart.
CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
5:1 TMRA0CLK RW Counter/Timer A0 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINA.
HFRC = 0x1 - Clock source is the HFRC
HFRC_DIV8 = 0x2 - Clock source is HFRC / 8
HFRC_DIV128 = 0x3 - Clock source is HFRC / 128
HFRC_DIV512 = 0x4 - Clock source is HFRC / 512
HFRC_DIV2K = 0x5 - Clock source is HFRC / 2048
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV256 = 0x9 - Clock source is XT / 256
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC / 16K
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK = 0xF - Clock source is HCLK.
BUCKA = 0x10 - Clock source is buck converter stream A.
0 TMRA0EN RW Counter/Timer A0 Enable bit.

DIS = 0x0 - Counter/Timer A0 Disable.
EN = 0x1 - Counter/Timer A0 Enable.

TMR1 - Counter/Timer Register

Address:

  Instance 0 Address:   0x40008010

Description:

This register holds the running time or event count, either for each 16 bit half or for the whole 32 bit count when the pair is linked.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTTMRB1
0x0
CTTMRA1
0x0

Bits Name RW Description
31:16 CTTMRB1 RO Counter/Timer B1.

15:0 CTTMRA1 RO Counter/Timer A1.


CMPRA1 - Counter/Timer A1 Compare Registers

Address:

  Instance 0 Address:   0x40008014

Description:

This register holds the compare limits for timer half A.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1A1
0x0
CMPR0A1
0x0

Bits Name RW Description
31:16 CMPR1A1 RW Counter/Timer A1 Compare Register 1.

15:0 CMPR0A1 RW Counter/Timer A1 Compare Register 0.


CMPRB1 - Counter/Timer B1 Compare Registers

Address:

  Instance 0 Address:   0x40008018

Description:

This register holds the compare limits for timer half B.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1B1
0x0
CMPR0B1
0x0

Bits Name RW Description
31:16 CMPR1B1 RW Counter/Timer B1 Compare Register 1.

15:0 CMPR0B1 RW Counter/Timer B1 Compare Register 0.


CTRL1 - Counter/Timer Control

Address:

  Instance 0 Address:   0x4000801C

Description:

This register holds the control bit fields for both halves of timer 1.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTLINK1
0x0
RSVD
0x0
TMRB1POL
0x0
TMRB1CLR
0x0
TMRB1PE
0x0
TMRB1IE
0x0
TMRB1FN
0x0
TMRB1CLK
0x0
TMRB1EN
0x0
RSVD
0x0
TMRA1POL
0x0
TMRA1CLR
0x0
TMRA1PE
0x0
TMRA1IE
0x0
TMRA1FN
0x0
TMRA1CLK
0x0
TMRA1EN
0x0

Bits Name RW Description
31 CTLINK1 RW Counter/Timer A1/B1 Link bit.

TWO_16BIT_TIMERS = 0x0 - Use A0/B0 timers as two independent 16-bit timers (default).
32BIT_TIMER = 0x1 - Link A1/B1 timers into a single 32-bit timer.
30:29 RSVD RO RESERVED

28 TMRB1POL RW Counter/Timer B1 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINB1 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINB1 pin is the inverse of the timer output.
27 TMRB1CLR RW Counter/Timer B1 Clear bit.

RUN = 0x0 - Allow counter/timer B1 to run
CLEAR = 0x1 - Holds counter/timer B1 at 0x0000.
26 TMRB1PE RW Counter/Timer B1 Output Enable bit.

DIS = 0x0 - Counter/Timer B holds the TMRPINB signal at the value TMRB1POL.
EN = 0x1 - Enable counter/timer B1 to generate a signal on TMRPINB.
25 TMRB1IE RW Counter/Timer B1 Interrupt Enable bit.

DIS = 0x0 - Disable counter/timer B1 from generating an interrupt.
EN = 0x1 - Enable counter/timer B1 to generate an interrupt.
24:22 TMRB1FN RW Counter/Timer B1 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B1, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B1, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B1, assert, count to CMPR1B, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B1, assert, count to CMPR1B1, deassert, restart.
CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
21:17 TMRB1CLK RW Counter/Timer B1 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINB.
HFRC = 0x1 - Clock source is the HFRC
HFRC_DIV8 = 0x2 - Clock source is HFRC / 8
HFRC_DIV128 = 0x3 - Clock source is HFRC / 128
HFRC_DIV512 = 0x4 - Clock source is HFRC / 512
HFRC_DIV2K = 0x5 - Clock source is HFRC / 2048
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV256 = 0x9 - Clock source is XT / 256
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC / 16K
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK = 0xF - Clock source is HCLK.
BUCKB = 0x10 - Clock source is buck converter stream B.
16 TMRB1EN RW Counter/Timer B1 Enable bit.

DIS = 0x0 - Counter/Timer B1 Disable.
EN = 0x1 - Counter/Timer B1 Enable.
15:13 RSVD RO RESERVED

12 TMRA1POL RW Counter/Timer A1 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINA1 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINA1 pin is the inverse of the timer output.
11 TMRA1CLR RW Counter/Timer A1 Clear bit.

RUN = 0x0 - Allow counter/timer A1 to run
CLEAR = 0x1 - Holds counter/timer A1 at 0x0000.
10 TMRA1PE RW Counter/Timer A1 Output Enable bit.

DIS = 0x0 - Counter/Timer A holds the TMRPINA signal at the value TMRA1POL.
EN = 0x1 - Enable counter/timer A1 to generate a signal on TMRPINA.
9 TMRA1IE RW Counter/Timer A1 Interrupt Enable bit.

DIS = 0x0 - Disable counter/timer A1 from generating an interrupt.
EN = 0x1 - Enable counter/timer A1 to generate an interrupt.
8:6 TMRA1FN RW Counter/Timer A1 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A1, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A1, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A1, assert, count to CMPR1B, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A1, assert, count to CMPR1A1, deassert, restart.
CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
5:1 TMRA1CLK RW Counter/Timer A1 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINA.
HFRC = 0x1 - Clock source is the HFRC
HFRC_DIV8 = 0x2 - Clock source is the HFRC / 8
HFRC_DIV128 = 0x3 - Clock source is HFRC / 128
HFRC_DIV512 = 0x4 - Clock source is HFRC / 512
HFRC_DIV2K = 0x5 - Clock source is HFRC / 2048
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV256 = 0x9 - Clock source is XT / 256
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC / 16K
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK = 0xF - Clock source is HCLK.
BUCKA = 0x10 - Clock source is buck converter stream A.
0 TMRA1EN RW Counter/Timer A1 Enable bit.

DIS = 0x0 - Counter/Timer A1 Disable.
EN = 0x1 - Counter/Timer A1 Enable.

TMR2 - Counter/Timer Register

Address:

  Instance 0 Address:   0x40008020

Description:

Counter/Timer Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTTMRB2
0x0
CTTMRA2
0x0

Bits Name RW Description
31:16 CTTMRB2 RO Counter/Timer B2.

15:0 CTTMRA2 RO Counter/Timer A2.


CMPRA2 - Counter/Timer A2 Compare Registers

Address:

  Instance 0 Address:   0x40008024

Description:

This register holds the compare limits for timer half A.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1A2
0x0
CMPR0A2
0x0

Bits Name RW Description
31:16 CMPR1A2 RW Counter/Timer A2 Compare Register 1.

15:0 CMPR0A2 RW Counter/Timer A2 Compare Register 0.


CMPRB2 - Counter/Timer B2 Compare Registers

Address:

  Instance 0 Address:   0x40008028

Description:

This register holds the compare limits for timer half B.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1B2
0x0
CMPR0B2
0x0

Bits Name RW Description
31:16 CMPR1B2 RW Counter/Timer B2 Compare Register 1.

15:0 CMPR0B2 RW Counter/Timer B2 Compare Register 0.


CTRL2 - Counter/Timer Control

Address:

  Instance 0 Address:   0x4000802C

Description:

This register holds the control bit fields for both halves of timer 2.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTLINK2
0x0
RSVD
0x0
TMRB2POL
0x0
TMRB2CLR
0x0
TMRB2PE
0x0
TMRB2IE
0x0
TMRB2FN
0x0
TMRB2CLK
0x0
TMRB2EN
0x0
RSVD
0x0
TMRA2POL
0x0
TMRA2CLR
0x0
TMRA2PE
0x0
TMRA2IE
0x0
TMRA2FN
0x0
TMRA2CLK
0x0
TMRA2EN
0x0

Bits Name RW Description
31 CTLINK2 RW Counter/Timer A2/B2 Link bit.

TWO_16BIT_TIMERS = 0x0 - Use A0/B0 timers as two independent 16-bit timers (default).
32BIT_TIMER = 0x1 - Link A2/B2 timers into a single 32-bit timer.
30:29 RSVD RO RESERVED

28 TMRB2POL RW Counter/Timer B2 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINB2 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINB2 pin is the inverse of the timer output.
27 TMRB2CLR RW Counter/Timer B2 Clear bit.

RUN = 0x0 - Allow counter/timer B2 to run
CLEAR = 0x1 - Holds counter/timer B2 at 0x0000.
26 TMRB2PE RW Counter/Timer B2 Output Enable bit.

DIS = 0x0 - Counter/Timer B holds the TMRPINB signal at the value TMRB2POL.
EN = 0x1 - Enable counter/timer B2 to generate a signal on TMRPINB.
25 TMRB2IE RW Counter/Timer B2 Interrupt Enable bit.

DIS = 0x0 - Disable counter/timer B2 from generating an interrupt.
EN = 0x1 - Enable counter/timer B2 to generate an interrupt.
24:22 TMRB2FN RW Counter/Timer B2 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B2, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B2, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B2, assert, count to CMPR1B, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B2, assert, count to CMPR1B2, deassert, restart.
CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
21:17 TMRB2CLK RW Counter/Timer B2 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINB.
HFRC = 0x1 - Clock source is the HFRC
HFRC_DIV8 = 0x2 - Clock source is HFRC / 8
HFRC_DIV128 = 0x3 - Clock source is HFRC / 128
HFRC_DIV512 = 0x4 - Clock source is HFRC / 512
HFRC_DIV2K = 0x5 - Clock source is HFRC / 2048
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV256 = 0x9 - Clock source is XT / 256
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC / 16K
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK = 0xF - Clock source is HCLK.
BUCKA = 0x10 - Clock source is buck converter stream A.
16 TMRB2EN RW Counter/Timer B2 Enable bit.

DIS = 0x0 - Counter/Timer B2 Disable.
EN = 0x1 - Counter/Timer B2 Enable.
15:13 RSVD RO RESERVED

12 TMRA2POL RW Counter/Timer A2 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINA2 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINA2 pin is the inverse of the timer output.
11 TMRA2CLR RW Counter/Timer A2 Clear bit.

RUN = 0x0 - Allow counter/timer A2 to run
CLEAR = 0x1 - Holds counter/timer A2 at 0x0000.
10 TMRA2PE RW Counter/Timer A2 Output Enable bit.

DIS = 0x0 - Counter/Timer A holds the TMRPINA signal at the value TMRA2POL.
EN = 0x1 - Enable counter/timer A2 to generate a signal on TMRPINA.
9 TMRA2IE RW Counter/Timer A2 Interrupt Enable bit.

DIS = 0x0 - Disable counter/timer A2 from generating an interrupt.
EN = 0x1 - Enable counter/timer A2 to generate an interrupt.
8:6 TMRA2FN RW Counter/Timer A2 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A2, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A2, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A2, assert, count to CMPR1B, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A2, assert, count to CMPR1A2, deassert, restart.
CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
5:1 TMRA2CLK RW Counter/Timer A2 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINA.
HFRC = 0x1 - Clock source is the HFRC
HFRC_DIV8 = 0x2 - Clock source is HFRC / 8
HFRC_DIV128 = 0x3 - Clock source is HFRC / 128
HFRC_DIV512 = 0x4 - Clock source is HFRC / 512
HFRC_DIV2K = 0x5 - Clock source is HFRC / 2048
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV256 = 0x9 - Clock source is XT / 256
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC / 16K
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK = 0xF - Clock source is HCLK.
BUCKB = 0x10 - Clock source is buck converter stream B.
0 TMRA2EN RW Counter/Timer A2 Enable bit.

DIS = 0x0 - Counter/Timer A2 Disable.
EN = 0x1 - Counter/Timer A2 Enable.

TMR3 - Counter/Timer Register

Address:

  Instance 0 Address:   0x40008030

Description:

Counter/Timer Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTTMRB3
0x0
CTTMRA3
0x0

Bits Name RW Description
31:16 CTTMRB3 RO Counter/Timer B3.

15:0 CTTMRA3 RO Counter/Timer A3.


CMPRA3 - Counter/Timer A3 Compare Registers

Address:

  Instance 0 Address:   0x40008034

Description:

This register holds the compare limits for timer half A.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1A3
0x0
CMPR0A3
0x0

Bits Name RW Description
31:16 CMPR1A3 RW Counter/Timer A3 Compare Register 1.

15:0 CMPR0A3 RW Counter/Timer A3 Compare Register 0.


CMPRB3 - Counter/Timer B3 Compare Registers

Address:

  Instance 0 Address:   0x40008038

Description:

This register holds the compare limits for timer half B.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMPR1B3
0x0
CMPR0B3
0x0

Bits Name RW Description
31:16 CMPR1B3 RW Counter/Timer B3 Compare Register 1.

15:0 CMPR0B3 RW Counter/Timer B3 Compare Register 0.


CTRL3 - Counter/Timer Control

Address:

  Instance 0 Address:   0x4000803C

Description:

This register holds the control bit fields for both halves of timer 3.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTLINK3
0x0
RSVD
0x0
TMRB3POL
0x0
TMRB3CLR
0x0
TMRB3PE
0x0
TMRB3IE
0x0
TMRB3FN
0x0
TMRB3CLK
0x0
TMRB3EN
0x0
ADCEN
0x0
RSVD
0x0
TMRA3POL
0x0
TMRA3CLR
0x0
TMRA3PE
0x0
TMRA3IE
0x0
TMRA3FN
0x0
TMRA3CLK
0x0
TMRA3EN
0x0

Bits Name RW Description
31 CTLINK3 RW Counter/Timer A/B Link bit.

TWO_16BIT_TIMERS = 0x0 - Use A0/B0 timers as two independent 16-bit timers (default).
32BIT_TIMER = 0x1 - Link A3/B3 timers into a single 32-bit timer.
30:29 RSVD RO RESERVED

28 TMRB3POL RW Counter/Timer B3 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINB3 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINB3 pin is the inverse of the timer output.
27 TMRB3CLR RW Counter/Timer B3 Clear bit.

RUN = 0x0 - Allow counter/timer B3 to run.
CLEAR = 0x1 - Holds counter/timer B3 at 0x0000.
26 TMRB3PE RW Counter/Timer B3 Output Enable bit.

DIS = 0x0 - Counter/Timer B holds the TMRPINB signal at the value TMRB3POL.
EN = 0x1 - Enable counter/timer B3 to generate a signal on TMRPINB.
25 TMRB3IE RW Counter/Timer B3 Interrupt Enable bit.

DIS = 0x0 - Disable counter/timer B3 from generating an interrupt.
EN = 0x1 - Enable counter/timer B3 to generate an interrupt.
24:22 TMRB3FN RW Counter/Timer B3 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B3, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B3, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B3, assert, count to CMPR1B, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B3, assert, count to CMPR1B3, deassert, restart.
CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
21:17 TMRB3CLK RW Counter/Timer B3 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINB.
HFRC = 0x1 - Clock source is the HFRC
HFRC_DIV8 = 0x2 - Clock source is HFRC / 8
HFRC_DIV128 = 0x3 - Clock source is HFRC / 128
HFRC_DIV512 = 0x4 - Clock source is HFRC / 512
HFRC_DIV2K = 0x5 - Clock source is HFRC / 2048
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV256 = 0x9 - Clock source is XT / 256
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC / 16K
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK = 0xF - Clock source is HCLK.
BUCKA = 0x10 - Clock source is buck converter stream A.
16 TMRB3EN RW Counter/Timer B3 Enable bit.

DIS = 0x0 - Counter/Timer B3 Disable.
EN = 0x1 - Counter/Timer B3 Enable.
15 ADCEN RW Special Timer A3 enable for ADC function.

14:13 RSVD RO RESERVED

12 TMRA3POL RW Counter/Timer A3 output polarity.

NORMAL = 0x0 - The polarity of the TMRPINA3 pin is the same as the timer output.
INVERTED = 0x1 - The polarity of the TMRPINA3 pin is the inverse of the timer output.
11 TMRA3CLR RW Counter/Timer A3 Clear bit.

CLEAR = 0x1 - Holds counter/timer A3 at 0x0000.
10 TMRA3PE RW Counter/Timer A3 Output Enable bit.

DIS = 0x0 - Counter/Timer A holds the TMRPINA signal at the value TMRA3POL.
EN = 0x1 - Enable counter/timer A3 to generate a signal on TMRPINA.
9 TMRA3IE RW Counter/Timer A3 Interrupt Enable bit.

DIS = 0x0 - Disable counter/timer A3 from generating an interrupt.
EN = 0x1 - Enable counter/timer A3 to generate an interrupt.
8:6 TMRA3FN RW Counter/Timer A3 Function Select.

SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A3, stop.
REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A3, restart.
PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A3, assert, count to CMPR1B, deassert, stop.
PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A3, assert, count to CMPR1A3, deassert, restart.
CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
5:1 TMRA3CLK RW Counter/Timer A3 Clock Select.

TMRPIN = 0x0 - Clock source is TMRPINA.
HFRC = 0x1 - Clock source is the HFRC
HFRC_DIV8 = 0x2 - Clock source is HFRC / 8
HFRC_DIV128 = 0x3 - Clock source is HFRC / 128
HFRC_DIV512 = 0x4 - Clock source is HFRC / 512
HFRC_DIV2K = 0x5 - Clock source is HFRC / 2048
XT = 0x6 - Clock source is the XT (uncalibrated).
XT_DIV2 = 0x7 - Clock source is XT / 2
XT_DIV16 = 0x8 - Clock source is XT / 16
XT_DIV256 = 0x9 - Clock source is XT / 256
LFRC_DIV2 = 0xA - Clock source is LFRC / 2
LFRC_DIV32 = 0xB - Clock source is LFRC / 32
LFRC_DIV1K = 0xC - Clock source is LFRC / 1024
LFRC = 0xD - Clock source is LFRC / 16K
RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator.
HCLK = 0xF - Clock source is HCLK.
BUCKB = 0x10 - Clock source is buck converter stream B.
0 TMRA3EN RW Counter/Timer A3 Enable bit.

DIS = 0x0 - Counter/Timer A3 Disable.
EN = 0x1 - Counter/Timer A3 Enable.

INTEN - Counter/Timer Interrupts: Enable

Address:

  Instance 0 Address:   0x40008200

Description:

Set bits in this register to allow this module to generate the corresponding interrupt.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CTMRB3INT
0x0
CTMRA3INT
0x0
CTMRB2INT
0x0
CTMRA2INT
0x0
CTMRB1INT
0x0
CTMRA1INT
0x0
CTMRB0INT
0x0
CTMRA0INT
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED

7 CTMRB3INT RW Counter/Timer B3 interrupt.

6 CTMRA3INT RW Counter/Timer A3 interrupt.

5 CTMRB2INT RW Counter/Timer B2 interrupt.

4 CTMRA2INT RW Counter/Timer A2 interrupt.

3 CTMRB1INT RW Counter/Timer B1 interrupt.

2 CTMRA1INT RW Counter/Timer A1 interrupt.

1 CTMRB0INT RW Counter/Timer B0 interrupt.

0 CTMRA0INT RW Counter/Timer A0 interrupt.


INTSTAT - Counter/Timer Interrupts: Status

Address:

  Instance 0 Address:   0x40008204

Description:

Read bits from this register to discover the cause of a recent interrupt.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CTMRB3INT
0x0
CTMRA3INT
0x0
CTMRB2INT
0x0
CTMRA2INT
0x0
CTMRB1INT
0x0
CTMRA1INT
0x0
CTMRB0INT
0x0
CTMRA0INT
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED

7 CTMRB3INT RW Counter/Timer B3 interrupt.

6 CTMRA3INT RW Counter/Timer A3 interrupt.

5 CTMRB2INT RW Counter/Timer B2 interrupt.

4 CTMRA2INT RW Counter/Timer A2 interrupt.

3 CTMRB1INT RW Counter/Timer B1 interrupt.

2 CTMRA1INT RW Counter/Timer A1 interrupt.

1 CTMRB0INT RW Counter/Timer B0 interrupt.

0 CTMRA0INT RW Counter/Timer A0 interrupt.


INTCLR - Counter/Timer Interrupts: Clear

Address:

  Instance 0 Address:   0x40008208

Description:

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CTMRB3INT
0x0
CTMRA3INT
0x0
CTMRB2INT
0x0
CTMRA2INT
0x0
CTMRB1INT
0x0
CTMRA1INT
0x0
CTMRB0INT
0x0
CTMRA0INT
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED

7 CTMRB3INT RW Counter/Timer B3 interrupt.

6 CTMRA3INT RW Counter/Timer A3 interrupt.

5 CTMRB2INT RW Counter/Timer B2 interrupt.

4 CTMRA2INT RW Counter/Timer A2 interrupt.

3 CTMRB1INT RW Counter/Timer B1 interrupt.

2 CTMRA1INT RW Counter/Timer A1 interrupt.

1 CTMRB0INT RW Counter/Timer B0 interrupt.

0 CTMRA0INT RW Counter/Timer A0 interrupt.


INTSET - Counter/Timer Interrupts: Set

Address:

  Instance 0 Address:   0x4000820C

Description:

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
CTMRB3INT
0x0
CTMRA3INT
0x0
CTMRB2INT
0x0
CTMRA2INT
0x0
CTMRB1INT
0x0
CTMRA1INT
0x0
CTMRB0INT
0x0
CTMRA0INT
0x0

Bits Name RW Description
31:8 RSVD RO RESERVED

7 CTMRB3INT RW Counter/Timer B3 interrupt.

6 CTMRA3INT RW Counter/Timer A3 interrupt.

5 CTMRB2INT RW Counter/Timer B2 interrupt.

4 CTMRA2INT RW Counter/Timer A2 interrupt.

3 CTMRB1INT RW Counter/Timer B1 interrupt.

2 CTMRA1INT RW Counter/Timer A1 interrupt.

1 CTMRB0INT RW Counter/Timer B0 interrupt.

0 CTMRA0INT RW Counter/Timer A0 interrupt.