Apollo Register Documentation  v${version}
PDM - PDM Audio

PDM Register Index

  0x00000000:   PCFG - PDM Configuration Register
  0x00000004:   VCFG - Voice Configuration Register
  0x00000008:   FR - Voice Status Register
  0x0000000C:   FRD - FIFO Read
  0x00000010:   FLUSH - FIFO Flush
  0x00000014:   FTHR - FIFO Threshold
  0x00000200:   INTEN - IO Master Interrupts: Enable
  0x00000204:   INTSTAT - IO Master Interrupts: Status
  0x00000208:   INTCLR - IO Master Interrupts: Clear
  0x0000020C:   INTSET - IO Master Interrupts: Set

PCFG - PDM Configuration Register

Address:

  Instance 0 Address:   0x50011000

Description:

PDM Configuration Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LRSWAP
0x0
PGARIGHT
0x0
PGALEFT
0x0
RSVD
0x0
MCLKDIV
0x0
SINCRATE
0x30
ADCHPD
0x1
HPCUTOFF
0xb
CYCLES
0x1
SOFTMUTE
0x0
PDMCORE
0x1

Bits Name RW Description
31 LRSWAP RW Left/right channel swap.

EN = 0x1 - Swap left and right channels (FIFO Read RIGHT_LEFT).
NOSWAP = 0x0 - No channel swapping (IFO Read LEFT_RIGHT).
30:27 PGARIGHT RW Right channel PGA gain.

M15DB = 0xF - -1.5 db gain.
M300DB = 0xE - -3.0 db gain.
M45DB = 0xD - -4.5 db gain.
M60DB = 0xC - -6.0 db gain.
M75DB = 0xB - -7.5 db gain.
M90DB = 0xA - -9.0 db gain.
M105DB = 0x9 - -10.5 db gain.
M120DB = 0x8 - -12.0 db gain.
P105DB = 0x7 - 10.5 db gain.
P90DB = 0x6 - 9.0 db gain.
P75DB = 0x5 - 7.5 db gain.
P60DB = 0x4 - 6.0 db gain.
P45DB = 0x3 - 4.5 db gain.
P30DB = 0x2 - 3.0 db gain.
P15DB = 0x1 - 1.5 db gain.
0DB = 0x0 - 0.0 db gain.
26:23 PGALEFT RW Left channel PGA gain.

M15DB = 0xF - -1.5 db gain.
M300DB = 0xE - -3.0 db gain.
M45DB = 0xD - -4.5 db gain.
M60DB = 0xC - -6.0 db gain.
M75DB = 0xB - -7.5 db gain.
M90DB = 0xA - -9.0 db gain.
M105DB = 0x9 - -10.5 db gain.
M120DB = 0x8 - -12.0 db gain.
P105DB = 0x7 - 10.5 db gain.
P90DB = 0x6 - 9.0 db gain.
P75DB = 0x5 - 7.5 db gain.
P60DB = 0x4 - 6.0 db gain.
P45DB = 0x3 - 4.5 db gain.
P30DB = 0x2 - 3.0 db gain.
P15DB = 0x1 - 1.5 db gain.
0DB = 0x0 - 0.0 db gain.
22:19 RSVD RO This bitfield is reserved for future use.

18:17 MCLKDIV RW PDM_CLK frequency divisor.

MCKDIV4 = 0x3 - Divide input clock by 4
MCKDIV3 = 0x2 - Divide input clock by 3
MCKDIV2 = 0x1 - Divide input clock by 2
MCKDIV1 = 0x0 - Divide input clock by 1
16:10 SINCRATE RW SINC decimation rate.

9 ADCHPD RW High pass filter disable.

EN = 0x0 - Enable high pass filter.
DIS = 0x1 - Disable high pass filter.
8:5 HPCUTOFF RW High pass filter coefficients.

4:2 CYCLES RW Number of clocks during gain-setting changes.

1 SOFTMUTE RW Soft mute control.

EN = 0x1 - Enable Soft Mute.
DIS = 0x0 - Disable Soft Mute.
0 PDMCORE RW Data Streaming Control.

EN = 0x1 - Enable Data Streaming.
DIS = 0x0 - Disable Data Streaming.

VCFG - Voice Configuration Register

Address:

  Instance 0 Address:   0x50011004

Description:

Voice Configuration Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOCLKEN
0x0
RSTB
0x0
PDMCLKSEL
0x0
PDMCLK
0x0
RSVD
0x0
I2SMODE
0x0
BCLKINV
0x0
RSVD
0x0
DMICKDEL
0x0
SELAP
0x0
RSVD
0x0
PCMPACK
0x0
RSVD
0x0
CHSET
0x1
RSVD
0x0

Bits Name RW Description
31 IOCLKEN RW Enable the IO clock.

DIS = 0x0 - Disable FIFO read.
EN = 0x1 - Enable FIFO read.
30 RSTB RW Reset the IP core.

RESET = 0x0 - Reset the core.
NORM = 0x1 - Enable the core.
29:27 PDMCLKSEL RW Select the PDM input clock.

DISABLE = 0x0 - Static value.
12MHz = 0x1 - PDM clock is 12 MHz.
6MHz = 0x2 - PDM clock is 6 MHz.
3MHz = 0x3 - PDM clock is 3 MHz.
1_5MHz = 0x4 - PDM clock is 1.5 MHz.
750KHz = 0x5 - PDM clock is 750 KHz.
375KHz = 0x6 - PDM clock is 375 KHz.
187KHz = 0x7 - PDM clock is 187.5 KHz.
26 PDMCLK RW Enable the serial clock.

DIS = 0x0 - Disable serial clock.
EN = 0x1 - Enable serial clock.
25:21 RSVD RO This bitfield is reserved for future use.

20 I2SMODE RW I2S interface enable.

DIS = 0x0 - Disable I2S interface.
EN = 0x1 - Enable I2S interface.
19 BCLKINV RW I2S BCLK input inversion.

INV = 0x0 - BCLK inverted.
NORM = 0x1 - BCLK not inverted.
18 RSVD RO This bitfield is reserved for future use.

17 DMICKDEL RW PDM clock sampling delay.

0CYC = 0x0 - No delay.
1CYC = 0x1 - 1 cycle delay.
16 SELAP RW Select PDM input clock source.

I2S = 0x1 - Clock source from I2S BCLK.
INTERNAL = 0x0 - Clock source from internal clock generator.
15:9 RSVD RO This bitfield is reserved for future use.

8 PCMPACK RW PCM data packing enable.

DIS = 0x0 - Disable PCM packing.
EN = 0x1 - Enable PCM packing.
7:5 RSVD RO This bitfield is reserved for future use.

4:3 CHSET RW Set PCM channels.

DIS = 0x0 - Channel disabled.
LEFT = 0x1 - Mono left channel.
RIGHT = 0x2 - Mono right channel.
STEREO = 0x3 - Stereo channels.
2:0 RSVD RO This bitfield is reserved for future use.


FR - Voice Status Register

Address:

  Instance 0 Address:   0x50011008

Description:

Voice Status Register

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
FIFOCNT
0x0

Bits Name RW Description
31:9 RSVD RO This bitfield is reserved for future use.

8:0 FIFOCNT RO Valid 32-bit entries currently in the FIFO.


FRD - FIFO Read

Address:

  Instance 0 Address:   0x5001100C

Description:

FIFO Read

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFOREAD
0x0

Bits Name RW Description
31:0 FIFOREAD RO FIFO read data.


FLUSH - FIFO Flush

Address:

  Instance 0 Address:   0x50011010

Description:

FIFO Flush

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
FIFOFLUSH
0x0

Bits Name RW Description
31:1 RSVD RO This bitfield is reserved for future use.

0 FIFOFLUSH WO FIFO FLUSH.


FTHR - FIFO Threshold

Address:

  Instance 0 Address:   0x50011014

Description:

FIFO Threshold

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
FIFOTHR
0xc0

Bits Name RW Description
31:8 RSVD RO This bitfield is reserved for future use.

7:0 FIFOTHR RW FIFO interrupt threshold.


INTEN - IO Master Interrupts: Enable

Address:

  Instance 0 Address:   0x50011200

Description:

Set bits in this register to allow this module to generate the corresponding interrupt.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
UNDFL
0x0
OVF
0x0
THR
0x0

Bits Name RW Description
31:3 RSVD RO RESERVED

2 UNDFL RW This is the FIFO underflow interrupt.

1 OVF RW This is the FIFO overflow interrupt.

0 THR RW This is the FIFO threshold interrupt.


INTSTAT - IO Master Interrupts: Status

Address:

  Instance 0 Address:   0x50011204

Description:

Read bits from this register to discover the cause of a recent interrupt.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
UNDFL
0x0
OVF
0x0
THR
0x0

Bits Name RW Description
31:3 RSVD RO RESERVED

2 UNDFL RW This is the FIFO underflow interrupt.

1 OVF RW This is the FIFO overflow interrupt.

0 THR RW This is the FIFO threshold interrupt.


INTCLR - IO Master Interrupts: Clear

Address:

  Instance 0 Address:   0x50011208

Description:

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
UNDFL
0x0
OVF
0x0
THR
0x0

Bits Name RW Description
31:3 RSVD RO RESERVED

2 UNDFL RW This is the FIFO underflow interrupt.

1 OVF RW This is the FIFO overflow interrupt.

0 THR RW This is the FIFO threshold interrupt.


INTSET - IO Master Interrupts: Set

Address:

  Instance 0 Address:   0x5001120C

Description:

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

Example Macro Usage:

//
// All macro-based register writes follow the same basic format. For
// single-instance modules, you may use the simpler AM_REG macro. For
// multi-instance macros, you will need to specify the instance number using
// the AM_REGn macro format.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
// AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
//
// For registers that do not have specific enumeration values, you may use this alternate format instead.
//
// AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
//
// For example, the following three lines of code are equivalent methods of
// writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
//
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

Register Fields:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
0x0
UNDFL
0x0
OVF
0x0
THR
0x0

Bits Name RW Description
31:3 RSVD RO RESERVED

2 UNDFL RW This is the FIFO underflow interrupt.

1 OVF RW This is the FIFO overflow interrupt.

0 THR RW This is the FIFO threshold interrupt.